1 /*
2  * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * @file     ./out/R7FA2A1AB.h
7  * @brief    CMSIS HeaderFile
8  * @version  1.1
9  */
10 
11 /** @addtogroup Renesas
12  * @{
13  */
14 
15 /** @addtogroup R7FA2A1AB
16  * @{
17  */
18 
19 #ifndef R7FA2A1AB_H
20  #define R7FA2A1AB_H
21 
22  #ifdef __cplusplus
23 extern "C" {
24  #endif
25 
26 /** @addtogroup Configuration_of_CMSIS
27  * @{
28  */
29 
30 /* =========================================================================================================================== */
31 /* ================                                Interrupt Number Definition                                ================ */
32 /* =========================================================================================================================== */
33 
34 /* =========================================================================================================================== */
35 /* ================                           Processor and Core Peripheral Section                           ================ */
36 /* =========================================================================================================================== */
37 
38 /* ==========================  Configuration of the ARM Cortex-M23 Processor and Core Peripherals  =========================== */
39  #define __CM23_REV                0x0100U /*!< CM23 Core Revision                                                        */
40  #define __NVIC_PRIO_BITS          2       /*!< Number of Bits used for Priority Levels                                   */
41  #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
42  #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
43  #define __MPU_PRESENT             1       /*!< MPU present                                                               */
44  #define __FPU_PRESENT             0       /*!< FPU present                                                               */
45  #define __SAUREGION_PRESENT       0       /*!< SAU region present                                                        */
46 
47 /** @} */ /* End of group Configuration_of_CMSIS */
48 
49  #include "core_cm23.h"                    /*!< ARM Cortex-M23 processor and core peripherals                             */
50  #include "system.h"                       /*!< R7FA2A1AB System                                                          */
51 
52  #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
53   #define __IM     __I
54  #endif
55  #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
56   #define __OM     __O
57  #endif
58  #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
59   #define __IOM    __IO
60  #endif
61 
62 /* ========================================  Start of section using anonymous unions  ======================================== */
63  #if defined(__CC_ARM)
64   #pragma push
65   #pragma anon_unions
66  #elif defined(__ICCARM__)
67   #pragma language=extended
68  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
69   #pragma clang diagnostic push
70   #pragma clang diagnostic ignored "-Wc11-extensions"
71   #pragma clang diagnostic ignored "-Wreserved-id-macro"
72   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
73   #pragma clang diagnostic ignored "-Wnested-anon-types"
74  #elif defined(__GNUC__)
75 
76 /* anonymous unions are enabled by default */
77  #elif defined(__TMS470__)
78 
79 /* anonymous unions are enabled by default */
80  #elif defined(__TASKING__)
81   #pragma warning 586
82  #elif defined(__CSMC__)
83 
84 /* anonymous unions are enabled by default */
85  #else
86   #warning Not supported compiler type
87  #endif
88 
89 /* =========================================================================================================================== */
90 /* ================                              Device Specific Cluster Section                              ================ */
91 /* =========================================================================================================================== */
92 
93 /** @addtogroup Device_Peripheral_clusters
94  * @{
95  */
96 
97 /**
98  * @brief R_BUS_CSa [CSa] (CS Registers)
99  */
100 typedef struct
101 {
102     __IM uint16_t RESERVED;
103 
104     union
105     {
106         __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
107 
108         struct
109         {
110             __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
111             uint16_t             : 2;
112             __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
113             uint16_t             : 4;
114             __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
115             __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
116             uint16_t             : 5;
117             __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
118         } MOD_b;
119     };
120 
121     union
122     {
123         __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
124 
125         struct
126         {
127             __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select                                       */
128             uint32_t                : 5;
129             __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select                                       */
130             uint32_t                : 5;
131             __IOM uint32_t CSWWAIT  : 5; /*!< [20..16] Normal Write Cycle Wait Select                                   */
132             uint32_t                : 3;
133             __IOM uint32_t CSRWAIT  : 5; /*!< [28..24] Normal Read Cycle Wait Select                                    */
134             uint32_t                : 3;
135         } WCR1_b;
136     };
137 
138     union
139     {
140         __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
141 
142         struct
143         {
144             __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
145             uint32_t              : 1;
146             __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
147             uint32_t              : 1;
148             __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
149             uint32_t              : 1;
150             __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
151             uint32_t              : 2;
152             __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
153             uint32_t              : 1;
154             __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
155             uint32_t              : 1;
156             __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
157             uint32_t              : 1;
158             __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
159             uint32_t              : 1;
160         } WCR2_b;
161     };
162     __IM uint32_t RESERVED1;
163 } R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
164 
165 /**
166  * @brief R_BUS_CSb [CSb] (CS Registers)
167  */
168 typedef struct
169 {
170     __IM uint16_t RESERVED;
171 
172     union
173     {
174         __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
175 
176         struct
177         {
178             __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
179             uint16_t             : 3;
180             __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
181             uint16_t             : 2;
182             __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
183             uint16_t             : 3;
184             __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
185             uint16_t             : 3;
186         } CR_b;
187     };
188     __IM uint16_t RESERVED1[3];
189 
190     union
191     {
192         __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
193 
194         struct
195         {
196             __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
197             uint16_t            : 4;
198             __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
199             uint16_t            : 4;
200         } REC_b;
201     };
202     __IM uint16_t RESERVED2[2];
203 } R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
204 
205 /**
206  * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
207  */
208 typedef struct
209 {
210     union
211     {
212         __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
213 
214         struct
215         {
216             __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
217             uint8_t             : 3;
218             __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
219             uint8_t             : 2;
220         } SDCCR_b;
221     };
222 
223     union
224     {
225         __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
226 
227         struct
228         {
229             __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
230             uint8_t             : 7;
231         } SDCMOD_b;
232     };
233 
234     union
235     {
236         __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
237 
238         struct
239         {
240             __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
241             uint8_t          : 7;
242         } SDAMOD_b;
243     };
244     __IM uint8_t  RESERVED;
245     __IM uint32_t RESERVED1[3];
246 
247     union
248     {
249         __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
250 
251         struct
252         {
253             __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
254             uint8_t            : 7;
255         } SDSELF_b;
256     };
257     __IM uint8_t  RESERVED2;
258     __IM uint16_t RESERVED3;
259 
260     union
261     {
262         __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
263 
264         struct
265         {
266             __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
267             __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
268                                         *   Setting. ( REFW+1 Cycles )                                                */
269         } SDRFCR_b;
270     };
271 
272     union
273     {
274         __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
275 
276         struct
277         {
278             __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
279             uint8_t            : 7;
280         } SDRFEN_b;
281     };
282     __IM uint8_t  RESERVED4;
283     __IM uint32_t RESERVED5[2];
284 
285     union
286     {
287         __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
288 
289         struct
290         {
291             __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
292             uint8_t             : 7;
293         } SDICR_b;
294     };
295     __IM uint8_t  RESERVED6;
296     __IM uint16_t RESERVED7;
297 
298     union
299     {
300         __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
301 
302         struct
303         {
304             __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
305             __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
306             __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
307                                         *   )                                                                         */
308             uint16_t : 5;
309         } SDIR_b;
310     };
311     __IM uint16_t RESERVED8;
312     __IM uint32_t RESERVED9[6];
313 
314     union
315     {
316         __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
317 
318         struct
319         {
320             __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
321             uint8_t           : 6;
322         } SDADR_b;
323     };
324     __IM uint8_t  RESERVED10;
325     __IM uint16_t RESERVED11;
326 
327     union
328     {
329         __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
330 
331         struct
332         {
333             __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
334             uint32_t           : 5;
335             __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
336             __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
337             __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
338             uint32_t           : 2;
339             __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
340             uint32_t           : 13;
341         } SDTR_b;
342     };
343 
344     union
345     {
346         __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
347 
348         struct
349         {
350             __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register Setting                                             */
351             uint16_t          : 1;
352         } SDMOD_b;
353     };
354     __IM uint16_t RESERVED12;
355     __IM uint32_t RESERVED13;
356 
357     union
358     {
359         __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
360 
361         struct
362         {
363             __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
364             uint8_t            : 2;
365             __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
366             __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
367             uint8_t            : 3;
368         } SDSR_b;
369     };
370     __IM uint8_t  RESERVED14;
371     __IM uint16_t RESERVED15;
372 } R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
373 
374 /**
375  * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers)
376  */
377 typedef struct
378 {
379     union
380     {
381         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
382 
383         struct
384         {
385             __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error Address                                                 */
386         } ADD_b;
387     };
388 
389     union
390     {
391         union
392         {
393             __IM uint8_t STAT;            /*!< (@ 0x00000004) Bus Error Status Register                                  */
394 
395             struct
396             {
397                 __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status                                                */
398                 uint8_t              : 6;
399                 __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status                                                   */
400             } STAT_b;
401         };
402 
403         union
404         {
405             __IM uint8_t RW;             /*!< (@ 0x00000004) Bus Error Read Write                                       */
406 
407             struct
408             {
409                 __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status                                     */
410                 uint8_t             : 7;
411             } RW_b;
412         };
413     };
414     __IM uint8_t  RESERVED;
415     __IM uint16_t RESERVED1;
416     __IM uint32_t RESERVED2[2];
417 } R_BUS_BUSERRa_Type;                  /*!< Size = 16 (0x10)                                                          */
418 
419 /**
420  * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers)
421  */
422 typedef struct
423 {
424     union
425     {
426         __IM uint32_t ADD;               /*!< (@ 0x00000000) BUS TZF Error Address                                      */
427 
428         struct
429         {
430             __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address                                */
431         } ADD_b;
432     };
433 
434     union
435     {
436         __IM uint8_t RW;               /*!< (@ 0x00000004) BUS TZF Error Read Write                                   */
437 
438         struct
439         {
440             __IM uint8_t TRWSTAT : 1;  /*!< [0..0] TrustZone filter error access Read/Write Status                    */
441             uint8_t              : 7;
442         } RW_b;
443     };
444     __IM uint8_t  RESERVED;
445     __IM uint16_t RESERVED1;
446     __IM uint32_t RESERVED2[2];
447 } R_BUS_BTZFERR_Type;                  /*!< Size = 16 (0x10)                                                          */
448 
449 /**
450  * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers)
451  */
452 typedef struct
453 {
454     union
455     {
456         __IM uint8_t STAT;              /*!< (@ 0x00000000) Bus Error Status Register                                  */
457 
458         struct
459         {
460             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status.                                            */
461             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
462             uint8_t                : 1;
463             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status.                                           */
464             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status.                               */
465             __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status.                     */
466             uint8_t                : 2;
467         } STAT_b;
468     };
469     __IM uint8_t RESERVED[7];
470 
471     union
472     {
473         __IOM uint8_t CLR;              /*!< (@ 0x00000008) Bus Error Clear Register                                   */
474 
475         struct
476         {
477             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear.                                             */
478             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
479             uint8_t                : 1;
480             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear.                                            */
481             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear.                                */
482             __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear.                      */
483             uint8_t                : 2;
484         } CLR_b;
485     };
486     __IM uint8_t RESERVED1[7];
487 } R_BUS_BUSERRb_Type;                  /*!< Size = 16 (0x10)                                                          */
488 
489 /**
490  * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers)
491  */
492 typedef struct
493 {
494     __IM uint8_t RESERVED[36];
495 
496     union
497     {
498         __IM uint8_t STAT;              /*!< (@ 0x00000024) DMAC/DTC Error Status Register                             */
499 
500         struct
501         {
502             __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status                               */
503             uint8_t                : 7;
504         } STAT_b;
505     };
506     __IM uint8_t RESERVED1[7];
507 
508     union
509     {
510         __IOM uint8_t CLR;              /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register                              */
511 
512         struct
513         {
514             __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear                                */
515             uint8_t                : 7;
516         } CLR_b;
517     };
518 } R_BUS_DMACDTCERR_Type;                /*!< Size = 45 (0x2d)                                                          */
519 
520 /**
521  * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers)
522  */
523 typedef struct
524 {
525     __IM uint32_t RESERVED[2];
526 
527     union
528     {
529         __IOM uint32_t MRE0BI;         /*!< (@ 0x00000008) Bus Slave Arbitration Control Register                     */
530 
531         struct
532         {
533             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
534             uint32_t            : 31;
535         } MRE0BI_b;
536     };
537     __IM uint32_t RESERVED1;
538 
539     union
540     {
541         __IOM uint32_t FLBI;           /*!< (@ 0x00000010) Bus Slave Arbitration Control Register                     */
542 
543         struct
544         {
545             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
546             uint32_t            : 31;
547         } FLBI_b;
548     };
549     __IM uint32_t RESERVED2[3];
550 
551     union
552     {
553         __IOM uint32_t S0BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
554 
555         struct
556         {
557             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
558             uint32_t            : 31;
559         } S0BI_b;
560     };
561     __IM uint32_t RESERVED3;
562 
563     union
564     {
565         __IOM uint32_t S1BI;           /*!< (@ 0x00000028) Bus Slave Arbitration Control Register                     */
566 
567         struct
568         {
569             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
570             uint32_t            : 31;
571         } S1BI_b;
572     };
573     __IM uint32_t RESERVED4;
574 
575     union
576     {
577         __IOM uint32_t S2BI;           /*!< (@ 0x00000030) Bus Slave Arbitration Control Register                     */
578 
579         struct
580         {
581             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
582             uint32_t            : 31;
583         } S2BI_b;
584     };
585     __IM uint32_t RESERVED5;
586 
587     union
588     {
589         __IOM uint32_t S3BI;           /*!< (@ 0x00000038) Bus Slave Arbitration Control Register                     */
590 
591         struct
592         {
593             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
594             uint32_t            : 31;
595         } S3BI_b;
596     };
597     __IM uint32_t RESERVED6[3];
598 
599     union
600     {
601         __IOM uint32_t STBYSBI;        /*!< (@ 0x00000048) Bus Slave Arbitration Control Register                     */
602 
603         struct
604         {
605             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
606             uint32_t            : 31;
607         } STBYSBI_b;
608     };
609     __IM uint32_t RESERVED7;
610 
611     union
612     {
613         union
614         {
615             __IOM uint32_t ECBI;         /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
616 
617             struct
618             {
619                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
620                 uint32_t            : 31;
621             } ECBI_b;
622         };
623 
624         union
625         {
626             __IOM uint32_t SPI0BI;       /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
627 
628             struct
629             {
630                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
631                 uint32_t            : 31;
632             } SPI0BI_b;
633         };
634     };
635     __IM uint32_t RESERVED8;
636 
637     union
638     {
639         union
640         {
641             __IOM uint32_t EOBI;         /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
642 
643             struct
644             {
645                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
646                 uint32_t            : 31;
647             } EOBI_b;
648         };
649 
650         union
651         {
652             __IOM uint32_t SPI1BI;       /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
653 
654             struct
655             {
656                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
657                 uint32_t            : 31;
658             } SPI1BI_b;
659         };
660     };
661     __IM uint32_t RESERVED9;
662 
663     union
664     {
665         __IOM uint32_t PBBI;           /*!< (@ 0x00000060) Bus Slave Arbitration Control Register                     */
666 
667         struct
668         {
669             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
670             uint32_t            : 31;
671         } PBBI_b;
672     };
673     __IM uint32_t RESERVED10;
674 
675     union
676     {
677         union
678         {
679             __IOM uint32_t PABI;         /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
680 
681             struct
682             {
683                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
684                 uint32_t            : 31;
685             } PABI_b;
686         };
687 
688         union
689         {
690             __IOM uint32_t CPU0SAHBI;    /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
691 
692             struct
693             {
694                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
695                 uint32_t            : 31;
696             } CPU0SAHBI_b;
697         };
698     };
699     __IM uint32_t RESERVED11;
700 
701     union
702     {
703         union
704         {
705             __IOM uint32_t PIBI;         /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
706 
707             struct
708             {
709                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
710                 uint32_t            : 31;
711             } PIBI_b;
712         };
713 
714         union
715         {
716             __IOM uint32_t CPU1TCMBI;    /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
717 
718             struct
719             {
720                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
721                 uint32_t            : 31;
722             } CPU1TCMBI_b;
723         };
724     };
725     __IM uint32_t RESERVED12;
726 
727     union
728     {
729         __IOM uint32_t PSBI;           /*!< (@ 0x00000078) Bus Slave Arbitration Control Register                     */
730 
731         struct
732         {
733             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
734             uint32_t            : 31;
735         } PSBI_b;
736     };
737 } R_BUS_BUSSABT0_Type;                 /*!< Size = 124 (0x7c)                                                         */
738 
739 /**
740  * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers)
741  */
742 typedef struct
743 {
744     union
745     {
746         union
747         {
748             __IOM uint32_t FHBI;         /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
749 
750             struct
751             {
752                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
753                 uint32_t            : 30;
754             } FHBI_b;
755         };
756 
757         union
758         {
759             __IOM uint32_t MRC0BI;       /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
760 
761             struct
762             {
763                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
764                 uint32_t            : 30;
765             } MRC0BI_b;
766         };
767     };
768     __IM uint32_t RESERVED[5];
769 
770     union
771     {
772         __IOM uint32_t S0BI;           /*!< (@ 0x00000018) Bus Slave Arbitration Control Register                     */
773 
774         struct
775         {
776             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
777             uint32_t            : 30;
778         } S0BI_b;
779     };
780     __IM uint32_t RESERVED1;
781 
782     union
783     {
784         __IOM uint32_t S1BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
785 
786         struct
787         {
788             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
789             uint32_t            : 30;
790         } S1BI_b;
791     };
792 } R_BUS_BUSSABT1_Type;                 /*!< Size = 36 (0x24)                                                          */
793 
794 /**
795  * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.)
796  */
797 typedef struct
798 {
799     union
800     {
801         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address.        */
802 
803         struct
804         {
805             __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address.               */
806         } ADD_b;
807     };
808 
809     union
810     {
811         __IM uint8_t RW;                /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read
812                                          *                  Write.                                                     */
813 
814         struct
815         {
816             __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write
817                                          *   Status.                                                                   */
818             uint8_t : 7;
819         } RW_b;
820     };
821     __IM uint8_t  RESERVED;
822     __IM uint16_t RESERVED1;
823     __IM uint32_t RESERVED2[2];
824 } R_BUS_BMSAERR_Type;                  /*!< Size = 16 (0x10)                                                          */
825 
826 /**
827  * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers)
828  */
829 typedef struct
830 {
831     union
832     {
833         __IOM uint16_t BUSOAD;           /*!< (@ 0x00000000) Bus Operation After Detection Register                     */
834 
835         struct
836         {
837             __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection.            */
838             __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection.                         */
839             __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection.                  */
840             uint16_t                : 13;
841         } BUSOAD_b;
842     };
843     __IM uint16_t RESERVED;
844 
845     union
846     {
847         __IOM uint16_t BUSOADPT;        /*!< (@ 0x00000004) BUS Operation After Detection Protect Register.            */
848 
849         struct
850         {
851             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register.                                     */
852             uint16_t               : 7;
853             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
854         } BUSOADPT_b;
855     };
856     __IM uint16_t RESERVED1[5];
857 
858     union
859     {
860         __IOM uint16_t MSAOAD;         /*!< (@ 0x00000010) Master Security Attribution Operation After Detection
861                                         *                  Register.                                                  */
862 
863         struct
864         {
865             __IOM uint16_t OAD : 1;    /*!< [0..0] Master Security Attribution operation after detection.             */
866             uint16_t           : 7;
867             __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code.                                                         */
868         } MSAOAD_b;
869     };
870     __IM uint16_t RESERVED2;
871 
872     union
873     {
874         __IOM uint16_t MSAPT;           /*!< (@ 0x00000014) Master Security Attribution Protect Register.              */
875 
876         struct
877         {
878             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register.                                     */
879             uint16_t               : 7;
880             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
881         } MSAPT_b;
882     };
883 } R_BUS_OAD_Type;                       /*!< Size = 22 (0x16)                                                          */
884 
885 /**
886  * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers)
887  */
888 typedef struct
889 {
890     union
891     {
892         __IM uint32_t STAT;            /*!< (@ 0x00000000) Bufferable Write Error Status Register                     */
893 
894         struct
895         {
896             __IM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error in 0.                                       */
897             __IM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error in 1.                                       */
898             __IM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error in 2.                                       */
899             __IM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error in 3.                                       */
900             __IM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error in 4.                                       */
901             __IM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error in 5.                                       */
902             __IM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error in 6.                                       */
903             __IM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error in 7.                                       */
904             __IM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error in 8.                                       */
905             __IM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error in 9.                                       */
906             __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10.                                    */
907             __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11.                                    */
908             __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12.                                    */
909             __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13.                                    */
910             __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14.                                    */
911             __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15.                                    */
912             __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16.                                    */
913             __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17.                                    */
914             __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18.                                    */
915             __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19.                                    */
916             __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20.                                    */
917             __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21.                                    */
918             __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22.                                    */
919             __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23.                                    */
920             __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24.                                    */
921             __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25.                                    */
922             __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26.                                    */
923             __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27.                                    */
924             __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28.                                    */
925             __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29.                                    */
926             __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30.                                    */
927             __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31.                                    */
928         } STAT_b;
929     };
930     __IM uint32_t RESERVED;
931 
932     union
933     {
934         __IOM uint32_t CLR;             /*!< (@ 0x00000008) Bufferable Write Error Clear Register.                     */
935 
936         struct
937         {
938             __IOM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error Clear for 0.                                */
939             __IOM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error Clear for 1.                                */
940             __IOM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error Clear for 2.                                */
941             __IOM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error Clear for 3.                                */
942             __IOM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error Clear for 4.                                */
943             __IOM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error Clear for 5.                                */
944             __IOM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error Clear for 6.                                */
945             __IOM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error Clear for 7.                                */
946             __IOM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error Clear for 8.                                */
947             __IOM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error Clear for 9.                                */
948             __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10.                             */
949             __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11.                             */
950             __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12.                             */
951             __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13.                             */
952             __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14.                             */
953             __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15.                             */
954             __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16.                             */
955             __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17.                             */
956             __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18.                             */
957             __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19.                             */
958             __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20.                             */
959             __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21.                             */
960             __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22.                             */
961             __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23.                             */
962             __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24.                             */
963             __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25.                             */
964             __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26.                             */
965             __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27.                             */
966             __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28.                             */
967             __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29.                             */
968             __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30.                             */
969             __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31.                             */
970         } CLR_b;
971     };
972 } R_BUS_MBWERR_Type;                    /*!< Size = 12 (0xc)                                                           */
973 
974 /**
975  * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers)
976  */
977 typedef struct
978 {
979     union
980     {
981         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
982 
983         struct
984         {
985             uint16_t             : 15;
986             __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
987         } CNT_b;
988     };
989     __IM uint16_t RESERVED;
990 } R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
991 
992 /**
993  * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
994  */
995 typedef struct
996 {
997     union
998     {
999         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
1000 
1001         struct
1002         {
1003             __IOM uint16_t ARBS   : 2; /*!< [1..0] Arbitration Select                                                 */
1004             uint16_t              : 2;
1005             __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method                                                 */
1006             uint16_t              : 10;
1007         } CNT_b;
1008     };
1009     __IM uint16_t RESERVED;
1010 } R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
1011 
1012 /**
1013  * @brief R_CAN0_MB [MB] (Mailbox)
1014  */
1015 typedef struct
1016 {
1017     union
1018     {
1019         __IOM uint32_t ID;             /*!< (@ 0x00000000) Mailbox ID Register                                        */
1020 
1021         struct
1022         {
1023             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
1024             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
1025             uint32_t           : 1;
1026             __IOM uint32_t RTR : 1;    /*!< [30..30] Remote Transmission Request                                      */
1027             __IOM uint32_t IDE : 1;    /*!< [31..31] ID Extension                                                     */
1028         } ID_b;
1029     };
1030 
1031     union
1032     {
1033         __IOM uint16_t DL;             /*!< (@ 0x00000004) Mailbox DLC Register                                       */
1034 
1035         struct
1036         {
1037             __IOM uint16_t DLC : 4;    /*!< [3..0] Data Length Code                                                   */
1038             uint16_t           : 12;
1039         } DL_b;
1040     };
1041 
1042     union
1043     {
1044         __IOM uint8_t D[8];            /*!< (@ 0x00000006) Mailbox Data Register                                      */
1045 
1046         struct
1047         {
1048             __IOM uint8_t DATA : 8;    /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN
1049                                         *   message data. Transmission or reception starts from DATA0.
1050                                         *   The bit order on the CAN bus is MSB-first, and transmission
1051                                         *   or reception starts from bit 7                                            */
1052         } D_b[8];
1053     };
1054 
1055     union
1056     {
1057         __IOM uint16_t TS;             /*!< (@ 0x0000000E) Mailbox Timestamp Register                                 */
1058 
1059         struct
1060         {
1061             __IOM uint16_t TSL : 8;    /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter
1062                                         *   value of the time stamp when received messages are stored
1063                                         *   in the mailbox.                                                           */
1064             __IOM uint16_t TSH : 8;    /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter
1065                                         *   value of the time stamp when received messages are stored
1066                                         *   in the mailbox.                                                           */
1067         } TS_b;
1068     };
1069 } R_CAN0_MB_Type;                      /*!< Size = 16 (0x10)                                                          */
1070 
1071 /**
1072  * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
1073  */
1074 typedef struct
1075 {
1076     union
1077     {
1078         __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
1079 
1080         struct
1081         {
1082             __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
1083             uint8_t          : 5;
1084             __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
1085             __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
1086         } BY_b;
1087     };
1088     __IM uint8_t RESERVED;
1089 } R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
1090 
1091 /**
1092  * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
1093  */
1094 typedef struct
1095 {
1096     union
1097     {
1098         __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
1099 
1100         struct
1101         {
1102             __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
1103             uint16_t           : 7;
1104         } HA_b;
1105     };
1106     __IM uint16_t RESERVED;
1107 } R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
1108 
1109 /**
1110  * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
1111  */
1112 typedef struct
1113 {
1114     union
1115     {
1116         __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
1117 
1118         struct
1119         {
1120             __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
1121                                         *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
1122         } L_b;
1123     };
1124 
1125     union
1126     {
1127         __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
1128 
1129         struct
1130         {
1131             __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
1132             __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
1133             __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
1134             uint8_t            : 5;
1135         } U_b;
1136     };
1137 } R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
1138 
1139 /**
1140  * @brief R_MPU_MMPU_MMPU_REGION [REGION] (Address Region registers)
1141  */
1142 typedef struct
1143 {
1144     union
1145     {
1146         __IOM uint16_t AC;             /*!< (@ 0x00000000) Access Control Register                                    */
1147 
1148         struct
1149         {
1150             __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
1151             __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
1152             __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
1153             uint16_t              : 13;
1154         } AC_b;
1155     };
1156     __IM uint16_t RESERVED;
1157 
1158     union
1159     {
1160         __IOM uint32_t S;              /*!< (@ 0x00000004) Start Address Register                                     */
1161 
1162         struct
1163         {
1164             __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination.
1165                                         *   NOTE: Some low-order bits are fixed to 0.                                 */
1166         } S_b;
1167     };
1168 
1169     union
1170     {
1171         __IOM uint32_t E;              /*!< (@ 0x00000008) End Address Register                                       */
1172 
1173         struct
1174         {
1175             __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region
1176                                         *   end, for use in region determination. NOTE: Some low-order
1177                                         *   bits are fixed to 1.                                                      */
1178         } E_b;
1179     };
1180     __IM uint32_t RESERVED1;
1181 } R_MPU_MMPU_MMPU_REGION_Type;         /*!< Size = 16 (0x10)                                                          */
1182 
1183 /**
1184  * @brief R_MPU_MMPU_MMPU [MMPU] (Bus Master MPU Registers)
1185  */
1186 typedef struct
1187 {
1188     union
1189     {
1190         __IOM uint16_t CTL;            /*!< (@ 0x00000000) Bus Master MPU Control Register                            */
1191 
1192         struct
1193         {
1194             __IOM uint16_t ENABLE : 1; /*!< [0..0] Master Group enable                                                */
1195             __IOM uint16_t OAD    : 1; /*!< [1..1] Operation after detection                                          */
1196             uint16_t              : 6;
1197             __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1198                                         *   stored.                                                                   */
1199         } CTL_b;
1200     };
1201     __IM uint16_t RESERVED;
1202     __IM uint32_t RESERVED1[63];
1203     __IM uint16_t RESERVED2;
1204 
1205     union
1206     {
1207         __IOM uint16_t PT;                        /*!< (@ 0x00000102) Protection of Register                                     */
1208 
1209         struct
1210         {
1211             __IOM uint16_t PROTECT : 1;           /*!< [0..0] Protection of region register                                      */
1212             uint16_t               : 7;
1213             __OM uint16_t KEY      : 8;           /*!< [15..8] Write Keyword The data written to these bits are not
1214                                                    *   stored.                                                                   */
1215         } PT_b;
1216     };
1217     __IM uint32_t RESERVED3[63];
1218     __IOM R_MPU_MMPU_MMPU_REGION_Type REGION[32]; /*!< (@ 0x00000200) Address Region registers                                   */
1219 } R_MPU_MMPU_MMPU_Type;                           /*!< Size = 1024 (0x400)                                                       */
1220 
1221 /**
1222  * @brief R_MPU_SMPU_SMPU [SMPU] (Access Control Structure for MBIU)
1223  */
1224 typedef struct
1225 {
1226     union
1227     {
1228         __IOM uint16_t R;              /*!< (@ 0x00000000) Access Control Register for MBIU                           */
1229 
1230         struct
1231         {
1232             uint16_t              : 2;
1233             __IOM uint16_t RPGRPA : 1;   /*!< [2..2] Master Group A Read protection                                     */
1234             __IOM uint16_t WPGRPA : 1;   /*!< [3..3] Master Group A Write protection                                    */
1235             __IOM uint16_t RPGRPB : 1;   /*!< [4..4] Master Group B Read protection                                     */
1236             __IOM uint16_t WPGRPB : 1;   /*!< [5..5] Master Group B Write protection                                    */
1237             __IOM uint16_t RPGRPC : 1;   /*!< [6..6] Master Group C Read protection                                     */
1238             __IOM uint16_t WPGRPC : 1;   /*!< [7..7] Master Group C Write protection                                    */
1239             uint16_t              : 4;
1240             __IOM uint16_t RPFLI  : 1;   /*!< [12..12] Code Flash Memory Read Protection                                */
1241             __IOM uint16_t WPFLI  : 1;   /*!< [13..13] Code Flash Memory Write Protection (Note: This bit
1242                                           *   is read as 1. The write value should be 1.)                               */
1243             __IOM uint16_t RPSRAMHS : 1; /*!< [14..14] SRAMHS Read Protection                                           */
1244             __IOM uint16_t WPSRAMHS : 1; /*!< [15..15] SRAMHS Write Protection                                          */
1245         } R_b;
1246     };
1247     __IM uint16_t RESERVED;
1248 } R_MPU_SMPU_SMPU_Type;                  /*!< Size = 4 (0x4)                                                            */
1249 
1250 /**
1251  * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
1252  */
1253 typedef struct
1254 {
1255     union
1256     {
1257         __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
1258                                         *                  Register                                                   */
1259 
1260         struct
1261         {
1262             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
1263             uint16_t           : 7;
1264             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
1265                                         *   stored.                                                                   */
1266         } OAD_b;
1267     };
1268     __IM uint16_t RESERVED;
1269 
1270     union
1271     {
1272         __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
1273 
1274         struct
1275         {
1276             __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
1277             uint16_t              : 7;
1278             __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
1279             uint16_t              : 7;
1280         } CTL_b;
1281     };
1282 
1283     union
1284     {
1285         __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
1286 
1287         struct
1288         {
1289             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
1290             uint16_t               : 7;
1291             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1292                                          *   stored.                                                                   */
1293         } PT_b;
1294     };
1295 
1296     union
1297     {
1298         __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
1299 
1300         struct
1301         {
1302             __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
1303                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
1304                                            *   The low-order 2 bits are fixed to 0.                                      */
1305         } SA_b;
1306     };
1307 
1308     union
1309     {
1310         __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
1311 
1312         struct
1313         {
1314             __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
1315                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
1316                                            *   The low-order 2 bits are fixed to 1.                                      */
1317         } EA_b;
1318     };
1319 } R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
1320 
1321 /**
1322  * @brief R_OPAMP_AMP [AMP] (Input and Output Selectors for Operational Amplifier [0..3])
1323  */
1324 typedef struct
1325 {
1326     __IOM uint8_t OS;                  /*!< (@ 0x00000000) Output Select Register                                     */
1327     __IOM uint8_t MS;                  /*!< (@ 0x00000001) Minus Input Select Register                                */
1328     __IOM uint8_t PS;                  /*!< (@ 0x00000002) Plus Input Select Register                                 */
1329 } R_OPAMP_AMP_Type;                    /*!< Size = 3 (0x3)                                                            */
1330 
1331 /**
1332  * @brief R_OPAMP_AMPOT [AMPOT] (Operational Amplifier n Offset Trimming Registers)
1333  */
1334 typedef struct
1335 {
1336     union
1337     {
1338         __IOM uint8_t P;               /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Register       */
1339 
1340         struct
1341         {
1342             __IOM uint8_t TRMP : 5;    /*!< [4..0] AMPn input offset trimming Pch side                                */
1343             uint8_t            : 3;
1344         } P_b;
1345     };
1346 
1347     union
1348     {
1349         __IOM uint8_t N;               /*!< (@ 0x00000001) Operational Amplifier n Offset Trimming Nch Register       */
1350 
1351         struct
1352         {
1353             __IOM uint8_t TRMN : 5;    /*!< [4..0] AMPn input offset trimming Nch side                                */
1354             uint8_t            : 3;
1355         } N_b;
1356     };
1357 } R_OPAMP_AMPOT_Type;                  /*!< Size = 2 (0x2)                                                            */
1358 
1359 /**
1360  * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
1361  */
1362 typedef struct
1363 {
1364     union
1365     {
1366         union
1367         {
1368             __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
1369 
1370             struct
1371             {
1372                 __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1373                 __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1374                 __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1375                 uint32_t             : 1;
1376                 __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1377                 __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1378                 __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1379                 uint32_t             : 3;
1380                 __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
1381                 __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
1382                 __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
1383                 __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
1384                 __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
1385                 uint32_t             : 7;
1386                 __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
1387                                            *   function. For individual pin functions, see the MPC table                 */
1388                 uint32_t : 3;
1389             } PmnPFS_b;
1390         };
1391 
1392         struct
1393         {
1394             union
1395             {
1396                 struct
1397                 {
1398                     __IM uint16_t RESERVED;
1399 
1400                     union
1401                     {
1402                         __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
1403 
1404                         struct
1405                         {
1406                             __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1407                             __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1408                             __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1409                             uint16_t             : 1;
1410                             __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1411                             __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1412                             __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1413                             uint16_t             : 3;
1414                             __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
1415                             __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
1416                             __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
1417                             __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
1418                         } PmnPFS_HA_b;
1419                     };
1420                 };
1421 
1422                 struct
1423                 {
1424                     __IM uint16_t RESERVED1;
1425                     __IM uint8_t  RESERVED2;
1426 
1427                     union
1428                     {
1429                         __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
1430 
1431                         struct
1432                         {
1433                             __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1434                             __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1435                             __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1436                             uint8_t             : 1;
1437                             __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1438                             __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1439                             __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1440                             uint8_t             : 1;
1441                         } PmnPFS_BY_b;
1442                     };
1443                 };
1444             };
1445         };
1446     };
1447 } R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
1448 
1449 /**
1450  * @brief R_PFS_PORT [PORT] (Port [0..14])
1451  */
1452 typedef struct
1453 {
1454     __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
1455 } R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
1456 
1457 /**
1458  * @brief R_PFS_VLSEL [VLSEL] (VLSEL)
1459  */
1460 typedef struct
1461 {
1462     __IM uint8_t RESERVED[389];
1463 
1464     union
1465     {
1466         __IOM uint8_t VL1SEL;          /*!< (@ 0x00000185) VL1 Select Control Register                                */
1467 
1468         struct
1469         {
1470             __IOM uint8_t SELVL : 1;   /*!< [0..0] VL1 Voltage Connection Switching Control                           */
1471             uint8_t             : 7;
1472         } VL1SEL_b;
1473     };
1474 } R_PFS_VLSEL_Type;                    /*!< Size = 390 (0x186)                                                        */
1475 
1476 /**
1477  * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
1478  */
1479 typedef struct
1480 {
1481     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
1482 } R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
1483 
1484 /**
1485  * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
1486  */
1487 typedef struct
1488 {
1489     union
1490     {
1491         __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
1492 
1493         struct
1494         {
1495             __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
1496             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
1497             uint8_t            : 1;
1498             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
1499             uint8_t            : 1;
1500             __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
1501         } RTCCR_b;
1502     };
1503     __IM uint8_t RESERVED;
1504 } R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
1505 
1506 /**
1507  * @brief R_RTC_CP [CP] (Capture registers)
1508  */
1509 typedef struct
1510 {
1511     __IM uint8_t RESERVED[2];
1512 
1513     union
1514     {
1515         union
1516         {
1517             __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
1518 
1519             struct
1520             {
1521                 __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
1522                                          *   seconds                                                                   */
1523                 __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
1524                                          *   seconds                                                                   */
1525                 uint8_t : 1;
1526             } RSEC_b;
1527         };
1528 
1529         union
1530         {
1531             __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
1532 
1533             struct
1534             {
1535                 __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
1536                                            *   value when a time capture event is detected.                              */
1537             } BCNT0_b;
1538         };
1539     };
1540     __IM uint8_t RESERVED1;
1541 
1542     union
1543     {
1544         union
1545         {
1546             __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
1547 
1548             struct
1549             {
1550                 __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
1551                                          *   minutes                                                                   */
1552                 __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
1553                                          *   minutes                                                                   */
1554                 uint8_t : 1;
1555             } RMIN_b;
1556         };
1557 
1558         union
1559         {
1560             __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
1561 
1562             struct
1563             {
1564                 __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
1565                                            *   value when a time capture event is detected.                              */
1566             } BCNT1_b;
1567         };
1568     };
1569     __IM uint8_t RESERVED2;
1570 
1571     union
1572     {
1573         union
1574         {
1575             __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
1576 
1577             struct
1578             {
1579                 __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
1580                                         *   minutes                                                                   */
1581                 __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
1582                                         *   minutes                                                                   */
1583                 __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
1584                 uint8_t         : 1;
1585             } RHR_b;
1586         };
1587 
1588         union
1589         {
1590             __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
1591 
1592             struct
1593             {
1594                 __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
1595                                            *   value when a time capture event is detected.                              */
1596             } BCNT2_b;
1597         };
1598     };
1599     __IM uint8_t RESERVED3[3];
1600 
1601     union
1602     {
1603         union
1604         {
1605             __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
1606 
1607             struct
1608             {
1609                 __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
1610                 __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
1611                 uint8_t             : 2;
1612             } RDAY_b;
1613         };
1614 
1615         union
1616         {
1617             __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
1618 
1619             struct
1620             {
1621                 __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
1622                                            *   value when a time capture event is detected.                              */
1623             } BCNT3_b;
1624         };
1625     };
1626     __IM uint8_t RESERVED4;
1627 
1628     union
1629     {
1630         __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
1631 
1632         struct
1633         {
1634             __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
1635             __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
1636                                         *   months                                                                    */
1637             uint8_t : 3;
1638         } RMON_b;
1639     };
1640     __IM uint8_t RESERVED5[3];
1641 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
1642 
1643 /**
1644  * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
1645  */
1646 typedef struct
1647 {
1648     union
1649     {
1650         __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
1651 
1652         struct
1653         {
1654             uint16_t             : 8;
1655             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
1656             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
1657             uint16_t             : 6;
1658         } E_b;
1659     };
1660 
1661     union
1662     {
1663         __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
1664 
1665         struct
1666         {
1667             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
1668         } N_b;
1669     };
1670 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
1671 
1672 /**
1673  * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
1674  */
1675 typedef struct
1676 {
1677     union
1678     {
1679         __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
1680 
1681         struct
1682         {
1683             __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
1684             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
1685             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
1686             uint8_t              : 1;
1687             __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
1688             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
1689             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
1690             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
1691         } AGTCR_b;
1692     };
1693 
1694     union
1695     {
1696         __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
1697 
1698         struct
1699         {
1700             __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
1701             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
1702             __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
1703             uint8_t              : 1;
1704         } AGTMR1_b;
1705     };
1706 
1707     union
1708     {
1709         __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
1710 
1711         struct
1712         {
1713             __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
1714                                         *   ratio                                                                     */
1715             uint8_t           : 4;
1716             __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
1717         } AGTMR2_b;
1718     };
1719 
1720     union
1721     {
1722         __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
1723 
1724         struct
1725         {
1726             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
1727             uint8_t            : 2;
1728             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
1729             uint8_t            : 3;
1730         } AGTIOSEL_ALT_b;
1731     };
1732 
1733     union
1734     {
1735         __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
1736 
1737         struct
1738         {
1739             __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
1740                                         *   mode.                                                                     */
1741             uint8_t             : 1;
1742             __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
1743             uint8_t             : 1;
1744             __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
1745             __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
1746         } AGTIOC_b;
1747     };
1748 
1749     union
1750     {
1751         __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
1752 
1753         struct
1754         {
1755             uint8_t            : 2;
1756             __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
1757             uint8_t            : 5;
1758         } AGTISR_b;
1759     };
1760 
1761     union
1762     {
1763         __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
1764 
1765         struct
1766         {
1767             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
1768             __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
1769             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
1770             uint8_t              : 1;
1771             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
1772             __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
1773             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
1774             uint8_t              : 1;
1775         } AGTCMSR_b;
1776     };
1777 
1778     union
1779     {
1780         __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
1781 
1782         struct
1783         {
1784             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
1785             uint8_t            : 2;
1786             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
1787             uint8_t            : 3;
1788         } AGTIOSEL_b;
1789     };
1790 } R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
1791 
1792 /**
1793  * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
1794  */
1795 typedef struct
1796 {
1797     union
1798     {
1799         __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
1800 
1801         struct
1802         {
1803             __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
1804                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
1805                                         *   counter is forcibly stopped and set to FFFFH.                             */
1806         } AGT_b;
1807     };
1808 
1809     union
1810     {
1811         __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
1812 
1813         struct
1814         {
1815             __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
1816                                          *   written to the TSTOP bit in the AGTCRn register, set to
1817                                          *   FFFFH                                                                     */
1818         } AGTCMA_b;
1819     };
1820 
1821     union
1822     {
1823         __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
1824 
1825         struct
1826         {
1827             __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
1828                                          *   written to the TSTOP bit in the AGTCR register, set to
1829                                          *   FFFFH                                                                     */
1830         } AGTCMB_b;
1831     };
1832     __IM uint16_t                 RESERVED;
1833     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
1834 } R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
1835 
1836 /**
1837  * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
1838  */
1839 typedef struct
1840 {
1841     union
1842     {
1843         __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
1844 
1845         struct
1846         {
1847             __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
1848                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
1849                                         *   counter is forcibly stopped and set to FFFFH.                             */
1850         } AGT_b;
1851     };
1852 
1853     union
1854     {
1855         __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
1856 
1857         struct
1858         {
1859             __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
1860                                          *   written to the TSTOP bit in the AGTCRn register, set to
1861                                          *   FFFFH                                                                     */
1862         } AGTCMA_b;
1863     };
1864 
1865     union
1866     {
1867         __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
1868 
1869         struct
1870         {
1871             __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
1872                                          *   written to the TSTOP bit in the AGTCR register, set to
1873                                          *   FFFFH                                                                     */
1874         } AGTCMB_b;
1875     };
1876     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
1877 } R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
1878 
1879 /** @} */ /* End of group Device_Peripheral_clusters */
1880 
1881 /* =========================================================================================================================== */
1882 /* ================                            Device Specific Peripheral Section                             ================ */
1883 /* =========================================================================================================================== */
1884 
1885 /** @addtogroup Device_Peripheral_peripherals
1886  * @{
1887  */
1888 
1889 /* =========================================================================================================================== */
1890 /* ================                                         R_ACMPHS0                                         ================ */
1891 /* =========================================================================================================================== */
1892 
1893 /**
1894  * @brief High-Speed Analog Comparator (R_ACMPHS0)
1895  */
1896 
1897 typedef struct                         /*!< (@ 0x40085000) R_ACMPHS0 Structure                                        */
1898 {
1899     union
1900     {
1901         __IOM uint8_t CMPCTL;          /*!< (@ 0x00000000) Comparator Control Register                                */
1902 
1903         struct
1904         {
1905             __IOM uint8_t CINV   : 1;  /*!< [0..0] Comparator output polarity selection                               */
1906             __IOM uint8_t COE    : 1;  /*!< [1..1] Comparator output enable                                           */
1907             __IOM uint8_t CSTEN  : 1;  /*!< [2..2] Interrupt Select                                                   */
1908             __IOM uint8_t CEG    : 2;  /*!< [4..3] Selection of valid edge (Edge selector)                            */
1909             __IOM uint8_t CDFS   : 2;  /*!< [6..5] Noise filter selection                                             */
1910             __IOM uint8_t HCMPON : 1;  /*!< [7..7] Comparator operation control                                       */
1911         } CMPCTL_b;
1912     };
1913     __IM uint8_t RESERVED[3];
1914 
1915     union
1916     {
1917         __IOM uint8_t CMPSEL0;         /*!< (@ 0x00000004) Comparator Input Select Register                           */
1918 
1919         struct
1920         {
1921             __IOM uint8_t CMPSEL : 4;  /*!< [3..0] Comparator Input Selection                                         */
1922             uint8_t              : 4;
1923         } CMPSEL0_b;
1924     };
1925     __IM uint8_t RESERVED1[3];
1926 
1927     union
1928     {
1929         __IOM uint8_t CMPSEL1;         /*!< (@ 0x00000008) Comparator Reference Voltage Select Register               */
1930 
1931         struct
1932         {
1933             __IOM uint8_t CRVS : 6;    /*!< [5..0] Reference Voltage Selection                                        */
1934             uint8_t            : 2;
1935         } CMPSEL1_b;
1936     };
1937     __IM uint8_t RESERVED2[3];
1938 
1939     union
1940     {
1941         __IM uint8_t CMPMON;           /*!< (@ 0x0000000C) Comparator Output Monitor Register                         */
1942 
1943         struct
1944         {
1945             __IM uint8_t CMPMON : 1;   /*!< [0..0] Comparator output monitor                                          */
1946             uint8_t             : 7;
1947         } CMPMON_b;
1948     };
1949     __IM uint8_t RESERVED3[3];
1950 
1951     union
1952     {
1953         __IOM uint8_t CPIOC;           /*!< (@ 0x00000010) Comparator Output Control Register                         */
1954 
1955         struct
1956         {
1957             __IOM uint8_t CPOE   : 1;  /*!< [0..0] Comparator output selection                                        */
1958             uint8_t              : 6;
1959             __IOM uint8_t VREFEN : 1;  /*!< [7..7] Internal Vref enable                                               */
1960         } CPIOC_b;
1961     };
1962 } R_ACMPHS0_Type;                      /*!< Size = 17 (0x11)                                                          */
1963 
1964 /* =========================================================================================================================== */
1965 /* ================                                         R_ACMPLP                                          ================ */
1966 /* =========================================================================================================================== */
1967 
1968 /**
1969  * @brief Low-Power Analog Comparator (R_ACMPLP)
1970  */
1971 
1972 typedef struct                         /*!< (@ 0x40085E00) R_ACMPLP Structure                                         */
1973 {
1974     union
1975     {
1976         __IOM uint8_t COMPMDR;         /*!< (@ 0x00000000) ACMPLP Mode Setting Register                               */
1977 
1978         struct
1979         {
1980             __IOM uint8_t C0ENB : 1;   /*!< [0..0] ACMPLP0 Operation Enable                                           */
1981             __IOM uint8_t C0WDE : 1;   /*!< [1..1] ACMPLP0 Window Function Mode Enable                                */
1982             __IOM uint8_t C0VRF : 1;   /*!< [2..2] ACMPLP0 Reference Voltage Selection                                */
1983             __IM uint8_t  C0MON : 1;   /*!< [3..3] ACMPLP0 Monitor Flag                                               */
1984             __IOM uint8_t C1ENB : 1;   /*!< [4..4] ACMPLP1 Operation Enable                                           */
1985             __IOM uint8_t C1WDE : 1;   /*!< [5..5] ACMPLP1 Window Function Mode Enable                                */
1986             __IOM uint8_t C1VRF : 1;   /*!< [6..6] ACMPLP1 Reference Voltage Selection                                */
1987             __IM uint8_t  C1MON : 1;   /*!< [7..7] ACMPLP1 Monitor Flag                                               */
1988         } COMPMDR_b;
1989     };
1990 
1991     union
1992     {
1993         __IOM uint8_t COMPFIR;         /*!< (@ 0x00000001) ACMPLP Filter Control Register                             */
1994 
1995         struct
1996         {
1997             __IOM uint8_t C0FCK : 2;   /*!< [1..0] ACMPLP0 Filter Select                                              */
1998             __IOM uint8_t C0EPO : 1;   /*!< [2..2] ACMPLP0 Edge Polarity Switching                                    */
1999             __IOM uint8_t C0EDG : 1;   /*!< [3..3] ACMPLP0 Edge Detection Selection                                   */
2000             __IOM uint8_t C1FCK : 2;   /*!< [5..4] ACMPLP1 Filter Select                                              */
2001             __IOM uint8_t C1EPO : 1;   /*!< [6..6] ACMPLP1 Edge Polarity Switching                                    */
2002             __IOM uint8_t C1EDG : 1;   /*!< [7..7] ACMPLP1 Edge Detection Selection                                   */
2003         } COMPFIR_b;
2004     };
2005 
2006     union
2007     {
2008         __IOM uint8_t COMPOCR;         /*!< (@ 0x00000002) ACMPLP Output Control Register                             */
2009 
2010         struct
2011         {
2012             uint8_t             : 1;
2013             __IOM uint8_t C0OE  : 1;   /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable                                    */
2014             __IOM uint8_t C0OP  : 1;   /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection                            */
2015             uint8_t             : 2;
2016             __IOM uint8_t C1OE  : 1;   /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable                                    */
2017             __IOM uint8_t C1OP  : 1;   /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection                            */
2018             __IOM uint8_t SPDMD : 1;   /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection                                    */
2019         } COMPOCR_b;
2020     };
2021     __IM uint8_t RESERVED;
2022 
2023     union
2024     {
2025         __IOM uint8_t COMPSEL0;        /*!< (@ 0x00000004) Comparator Input Select Register                           */
2026 
2027         struct
2028         {
2029             __IOM uint8_t IVCMP0 : 3;  /*!< [2..0] ACMPLP0 Input (IVCMP0) Selection                                   */
2030             uint8_t              : 1;
2031             __IOM uint8_t IVCMP1 : 3;  /*!< [6..4] ACMPLP1 Input (IVCMP1) Selection                                   */
2032             uint8_t              : 1;
2033         } COMPSEL0_b;
2034     };
2035 
2036     union
2037     {
2038         __IOM uint8_t COMPSEL1;        /*!< (@ 0x00000005) Comparator Reference voltage Select Register               */
2039 
2040         struct
2041         {
2042             __IOM uint8_t IVREF0 : 3;  /*!< [2..0] ACMPLP0 Reference Voltage (IVREF0) Selection                       */
2043             uint8_t              : 1;
2044             __IOM uint8_t IVREF1 : 3;  /*!< [6..4] ACMPLP1 Reference Voltage(IVREF1) Selection                        */
2045             __IOM uint8_t C1VRF2 : 1;  /*!< [7..7] ACMPLP1 Reference Voltage Selection                                */
2046         } COMPSEL1_b;
2047     };
2048 } R_ACMPLP_Type;                       /*!< Size = 6 (0x6)                                                            */
2049 
2050 /* =========================================================================================================================== */
2051 /* ================                                          R_ADC0                                           ================ */
2052 /* =========================================================================================================================== */
2053 
2054 /**
2055  * @brief A/D Converter (R_ADC0)
2056  */
2057 
2058 typedef struct                         /*!< (@ 0x4005C000) R_ADC0 Structure                                           */
2059 {
2060     union
2061     {
2062         __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
2063 
2064         struct
2065         {
2066             __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
2067                                         *   input channel for double triggered operation. The setting
2068                                         *   is only effective while double trigger mode is selected.                  */
2069             uint16_t              : 1;
2070             __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
2071             __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
2072             __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
2073             __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
2074             __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
2075             uint16_t              : 1;
2076             __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
2077             __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
2078             __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
2079         } ADCSR_b;
2080     };
2081 
2082     union
2083     {
2084         __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
2085 
2086         struct
2087         {
2088             __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
2089                                         *   '1' while scanning.                                                       */
2090             uint8_t              : 6;
2091             __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
2092         } ADREF_b;
2093     };
2094 
2095     union
2096     {
2097         __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
2098 
2099         struct
2100         {
2101             __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
2102             uint8_t             : 7;
2103         } ADEXREF_b;
2104     };
2105 
2106     union
2107     {
2108         __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
2109 
2110         struct
2111         {
2112             __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
2113             __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
2114             __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
2115             __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
2116             __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
2117             __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
2118             __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
2119             __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
2120             __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
2121             __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
2122             __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
2123             __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
2124             __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
2125             __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
2126             __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
2127             __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
2128         } ADANSA_b[2];
2129     };
2130 
2131     union
2132     {
2133         __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
2134                                         *                  Select Register                                            */
2135 
2136         struct
2137         {
2138             __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
2139             __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
2140             __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
2141             __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
2142             __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
2143             __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
2144             __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
2145             __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
2146             __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
2147             __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
2148             __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
2149             __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
2150             __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
2151             __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
2152             __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
2153             __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
2154         } ADADS_b[2];
2155     };
2156 
2157     union
2158     {
2159         __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
2160                                         *                  Register                                                   */
2161 
2162         struct
2163         {
2164             __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
2165                                         *   at the only setting of ADC[2:0] bits = 001b or 011b. When
2166                                         *   average mode is selected by setting the ADADC.AVEE bit
2167                                         *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
2168                                         *   = 010b)                                                                   */
2169             uint8_t            : 4;
2170             __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
2171                                         *   by setting the ADADC.AVEE bit to 0, set the addition count
2172                                         *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
2173                                         *   can only be used with 12-bit accuracy selected. NOTE: AVEE
2174                                         *   bit is valid at the only setting of ADC[2:0] bits = 001b
2175                                         *   or 011b. When average mode is selected by setting the ADADC.AVEE
2176                                         *   bit to 1, do not set the addition count to three times
2177                                         *   (ADADC.ADC[2:0] = 010b)                                                   */
2178         } ADADC_b;
2179     };
2180     __IM uint8_t RESERVED;
2181 
2182     union
2183     {
2184         __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
2185 
2186         struct
2187         {
2188             uint16_t               : 1;
2189             __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
2190             uint16_t               : 1;
2191             __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
2192             __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
2193             uint16_t               : 2;
2194             __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
2195             __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
2196             __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
2197             uint16_t               : 2;
2198             __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
2199             __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
2200         } ADCER_b;
2201     };
2202 
2203     union
2204     {
2205         __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
2206 
2207         struct
2208         {
2209             __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
2210                                         *   the A/D conversion start trigger for group B in group scan
2211                                         *   mode.                                                                     */
2212             uint16_t            : 2;
2213             __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
2214                                         *   start trigger in single scan mode and continuous mode.
2215                                         *   In group scan mode, the A/D conversion start trigger for
2216                                         *   group A is selected.                                                      */
2217             uint16_t : 2;
2218         } ADSTRGR_b;
2219     };
2220 
2221     union
2222     {
2223         __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
2224 
2225         struct
2226         {
2227             __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
2228                                         *   Mode Select                                                               */
2229             __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
2230                                         *   Mode Select                                                               */
2231             uint16_t            : 6;
2232             __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
2233             __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
2234             __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
2235                                         *   Group B in group scan mode.                                               */
2236             __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
2237                                         *   Group B in group scan mode.                                               */
2238             uint16_t             : 2;
2239             __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
2240             __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
2241         } ADEXICR_b;
2242     };
2243 
2244     union
2245     {
2246         __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
2247 
2248         struct
2249         {
2250             __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
2251             __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
2252             __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
2253             __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
2254             __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
2255             __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
2256             __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
2257             __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
2258             __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
2259             __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
2260             __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
2261             __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
2262             __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
2263             __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
2264             __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
2265             __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
2266         } ADANSB_b[2];
2267     };
2268 
2269     union
2270     {
2271         __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
2272 
2273         struct
2274         {
2275             __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2276                                          *   result of A/D conversion in response to the second trigger
2277                                          *   in double trigger mode.                                                   */
2278         } ADDBLDR_b;
2279     };
2280 
2281     union
2282     {
2283         __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
2284 
2285         struct
2286         {
2287             __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2288                                         *   A/D conversion result of temperature sensor output.                       */
2289         } ADTSDR_b;
2290     };
2291 
2292     union
2293     {
2294         __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
2295 
2296         struct
2297         {
2298             __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2299                                         *   A/D result of internal reference voltage.                                 */
2300         } ADOCDR_b;
2301     };
2302 
2303     union
2304     {
2305         union
2306         {
2307             __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
2308 
2309             struct
2310             {
2311                 __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
2312                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
2313                 __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
2314             } ADRD_RIGHT_b;
2315         };
2316 
2317         union
2318         {
2319             __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
2320 
2321             struct
2322             {
2323                 __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
2324                 __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
2325                                             *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
2326             } ADRD_LEFT_b;
2327         };
2328     };
2329 
2330     union
2331     {
2332         __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
2333 
2334         struct
2335         {
2336             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
2337                                         *   storing the result of A/D conversion.                                     */
2338         } ADDR_b[29];
2339     };
2340     __IM uint16_t RESERVED1;
2341     __IM uint32_t RESERVED2;
2342     __IM uint16_t RESERVED3;
2343 
2344     union
2345     {
2346         __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
2347 
2348         struct
2349         {
2350             __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
2351         } ADAMPOFF_b;
2352     };
2353 
2354     union
2355     {
2356         __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
2357 
2358         struct
2359         {
2360             __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
2361             __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
2362             uint8_t            : 6;
2363         } ADTSTPR_b;
2364     };
2365 
2366     union
2367     {
2368         __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
2369 
2370         struct
2371         {
2372             __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
2373             uint16_t              : 3;
2374             __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
2375             uint16_t              : 2;
2376             __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
2377         } ADDDACER_b;
2378     };
2379 
2380     union
2381     {
2382         __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
2383 
2384         struct
2385         {
2386             __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
2387                                         *   Setting Set the sampling time (4 to 255 states)                           */
2388             __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
2389             __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
2390             __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
2391             uint16_t              : 5;
2392         } ADSHCR_b;
2393     };
2394 
2395     union
2396     {
2397         __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
2398 
2399         struct
2400         {
2401             __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
2402                                         *   only for channel.                                                         */
2403             uint16_t             : 1;
2404             __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
2405             uint16_t             : 2;
2406             __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
2407                                         *   for adjustment to hardening of process.                                   */
2408             uint16_t              : 1;
2409             __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
2410                                         *   power save bit for A/D hard macro to hardening of process.                */
2411             __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
2412                                         *   bit for A/D hard macro to hardening of process.                           */
2413             __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
2414                                         *   bit for A/D hard macro to hardening of process.                           */
2415         } ADEXTSTR_b;
2416     };
2417 
2418     union
2419     {
2420         __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
2421 
2422         struct
2423         {
2424             __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
2425             __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
2426                                            *   amplifier test.Refreshing the pressure switch that opens
2427                                            *   for the DAC output voltage charge period when the amplifier
2428                                            *   of the S&H circuit is tested only for the channel is set.                 */
2429             uint16_t            : 1;
2430             __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
2431                                            *   bit.                                                                      */
2432             __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
2433                                            *   bit                                                                       */
2434             uint16_t                 : 1;
2435             __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
2436                                            *   module Details are described to the bit explanation.                      */
2437             __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
2438                                            *   bit explanation.                                                          */
2439         } ADTSTRA_b;
2440     };
2441 
2442     union
2443     {
2444         __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
2445 
2446         struct
2447         {
2448             __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
2449                                         *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
2450             uint16_t : 1;
2451         } ADTSTRB_b;
2452     };
2453 
2454     union
2455     {
2456         __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
2457 
2458         struct
2459         {
2460             __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
2461                                          *   analog module.                                                            */
2462             uint16_t               : 4;
2463             __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
2464             uint16_t               : 3;
2465         } ADTSTRC_b;
2466     };
2467 
2468     union
2469     {
2470         __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
2471 
2472         struct
2473         {
2474             __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
2475                                          *   corresponds to ADVAL 16 input of A/D analog module.                       */
2476             uint16_t : 15;
2477         } ADTSTRD_b;
2478     };
2479 
2480     union
2481     {
2482         __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
2483 
2484         struct
2485         {
2486             __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
2487             __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
2488             __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
2489             __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
2490             __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
2491             __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
2492             uint16_t              : 10;
2493         } ADSWTSTR0_b;
2494     };
2495 
2496     union
2497     {
2498         __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
2499 
2500         struct
2501         {
2502             __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
2503             __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
2504             __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
2505             __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
2506             __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
2507             __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
2508             uint16_t              : 10;
2509         } ADSWTSTR1_b;
2510     };
2511 
2512     union
2513     {
2514         __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
2515 
2516         struct
2517         {
2518             __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
2519                                           *   (ANEX0 switch)                                                            */
2520             __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
2521                                           *   (ANEX1 switch).                                                           */
2522             uint16_t                : 2;
2523             __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
2524             __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
2525             __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
2526             uint16_t                : 1;
2527             __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
2528             __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
2529             __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
2530             __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
2531             __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
2532             uint16_t                : 3;
2533         } ADSWTSTR2_b;
2534     };
2535     __IM uint16_t RESERVED4;
2536 
2537     union
2538     {
2539         __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
2540 
2541         struct
2542         {
2543             __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
2544             __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
2545             uint8_t              : 3;
2546         } ADDISCR_b;
2547     };
2548 
2549     union
2550     {
2551         __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
2552 
2553         struct
2554         {
2555             __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
2556                                         *   the pressure switch in A/D analog module is set.                          */
2557             uint8_t               : 1;
2558             __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
2559             uint8_t               : 1;
2560         } ADSWCR_b;
2561     };
2562 
2563     union
2564     {
2565         __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
2566 
2567         struct
2568         {
2569             __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
2570                                         *   Select                                                                    */
2571             uint8_t : 7;
2572         } ADSHMSR_b;
2573     };
2574 
2575     union
2576     {
2577         __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
2578 
2579         struct
2580         {
2581             __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
2582             uint8_t            : 6;
2583         } ADICR_b;
2584     };
2585 
2586     union
2587     {
2588         __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
2589 
2590         struct
2591         {
2592             uint8_t             : 1;
2593             __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
2594             uint8_t             : 6;
2595         } ADACSR_b;
2596     };
2597     __IM uint8_t RESERVED5;
2598 
2599     union
2600     {
2601         __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
2602 
2603         struct
2604         {
2605             __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
2606                                          *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
2607                                          *   set to 01b (group scan mode). If the bits are set to any
2608                                          *   other values, proper operation is not guaranteed.                         */
2609             __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
2610                                          *   when PGS = 0.)                                                            */
2611             uint16_t               : 6;
2612             __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
2613             uint16_t               : 6;
2614             __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
2615                                          *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
2616                                          *   has been set to 1, single scan is performed continuously
2617                                          *   for group B regardless of the setting of the GBRSCN bit.                  */
2618         } ADGSPCR_b;
2619     };
2620 
2621     union
2622     {
2623         __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
2624                                         *                  Scan)                                                      */
2625 
2626         struct
2627         {
2628             __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
2629             __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
2630         } ADGSCS_b;
2631     };
2632 
2633     union
2634     {
2635         __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
2636 
2637         struct
2638         {
2639             __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
2640                                           *   the result of A/D conversion in response to the respective
2641                                           *   triggers during extended operation in double trigger mode.                */
2642         } ADDBLDRA_b;
2643     };
2644 
2645     union
2646     {
2647         __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
2648 
2649         struct
2650         {
2651             __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
2652                                           *   the result of A/D conversion in response to the respective
2653                                           *   triggers during extended operation in double trigger mode.                */
2654         } ADDBLDRB_b;
2655     };
2656 
2657     union
2658     {
2659         __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
2660 
2661         struct
2662         {
2663             uint8_t             : 7;
2664             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
2665         } ADSER_b;
2666     };
2667     __IM uint8_t RESERVED6;
2668 
2669     union
2670     {
2671         __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
2672                                         *                  Control Register                                           */
2673 
2674         struct
2675         {
2676             __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
2677             uint8_t             : 2;
2678             __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
2679             uint8_t             : 2;
2680             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
2681         } ADHVREFCNT_b;
2682     };
2683     __IM uint8_t RESERVED7;
2684 
2685     union
2686     {
2687         __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
2688                                         *                  Register                                                   */
2689 
2690         struct
2691         {
2692             __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
2693                                         *   result.This bit is valid when both window A operation and
2694                                         *   window B operation are enabled.                                           */
2695             uint8_t              : 3;
2696             __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
2697             __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
2698             uint8_t              : 2;
2699         } ADWINMON_b;
2700     };
2701     __IM uint8_t  RESERVED8;
2702     __IM uint16_t RESERVED9;
2703 
2704     union
2705     {
2706         __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
2707 
2708         struct
2709         {
2710             __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
2711                                         *   are valid when both window A and window B are enabled (CMPAE
2712                                         *   = 1 and CMPBE = 1).                                                       */
2713             uint16_t              : 7;
2714             __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
2715             uint16_t              : 1;
2716             __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
2717             uint16_t              : 1;
2718             __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
2719             __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
2720             __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
2721         } ADCMPCR_b;
2722     };
2723 
2724     union
2725     {
2726         __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
2727                                         *                  Select Register                                            */
2728 
2729         struct
2730         {
2731             __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
2732             __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
2733             uint8_t              : 6;
2734         } ADCMPANSER_b;
2735     };
2736 
2737     union
2738     {
2739         __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
2740                                         *                  Comparison Condition Setting Register                      */
2741 
2742         struct
2743         {
2744             __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
2745                                         *   Condition Select                                                          */
2746             __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
2747                                         *   Select                                                                    */
2748             uint8_t : 6;
2749         } ADCMPLER_b;
2750     };
2751 
2752     union
2753     {
2754         __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
2755                                           *                  Register                                                   */
2756 
2757         struct
2758         {
2759             __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
2760             __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
2761             __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
2762             __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
2763             __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
2764             __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
2765             __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
2766             __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
2767             __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
2768             __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
2769             __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
2770             __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
2771             __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
2772             __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
2773             __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
2774             __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
2775         } ADCMPANSR_b[2];
2776     };
2777 
2778     union
2779     {
2780         __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
2781                                            *                  Setting Register                                           */
2782 
2783         struct
2784         {
2785             __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
2786             __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
2787             __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
2788             __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
2789             __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
2790             __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
2791             __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
2792             __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
2793             __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
2794             __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
2795             __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
2796             __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
2797             __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
2798             __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
2799             __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
2800             __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
2801         } ADCMPLR_b[2];
2802     };
2803 
2804     union
2805     {
2806         __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
2807                                            *                  Setting Register                                           */
2808 
2809         struct
2810         {
2811             __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
2812                                            *   compare window A function is used. ADCMPDR0 sets the lower-side
2813                                            *   level of window A.                                                        */
2814         } ADCMPDR0_b;
2815     };
2816 
2817     union
2818     {
2819         __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
2820                                            *                  Setting Register                                           */
2821 
2822         struct
2823         {
2824             __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
2825                                            *   compare window A function is used. ADCMPDR1 sets the upper-side
2826                                            *   level of window A..                                                       */
2827         } ADCMPDR1_b;
2828     };
2829 
2830     union
2831     {
2832         __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
2833                                             *                  Register                                                   */
2834 
2835         struct
2836         {
2837             __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
2838             __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
2839             __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
2840             __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
2841             __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
2842             __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
2843             __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
2844             __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
2845             __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
2846             __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
2847             __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
2848             __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
2849             __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
2850             __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
2851             __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
2852             __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
2853         } ADCMPSR_b[2];
2854     };
2855 
2856     union
2857     {
2858         __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
2859                                          *                  Channel Status Register                                    */
2860 
2861         struct
2862         {
2863             __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
2864                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
2865                                          *   this bit indicates the temperature sensor output comparison
2866                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
2867                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
2868                                          *   time.                                                                     */
2869             __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
2870                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
2871                                          *   this bit indicates the temperature sensor output comparison
2872                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
2873                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
2874                                          *   time.                                                                     */
2875             uint8_t : 6;
2876         } ADCMPSER_b;
2877     };
2878     __IM uint8_t RESERVED10;
2879 
2880     union
2881     {
2882         __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
2883                                         *                  Register                                                   */
2884 
2885         struct
2886         {
2887             __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
2888                                         *   compares it on the condition of compare window B is selected.             */
2889             uint8_t             : 1;
2890             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
2891         } ADCMPBNSR_b;
2892     };
2893     __IM uint8_t RESERVED11;
2894 
2895     union
2896     {
2897         __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
2898                                            *                  Setting Register                                           */
2899 
2900         struct
2901         {
2902             __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
2903                                            *   used to set the lower level of the window B.                              */
2904         } ADWINLLB_b;
2905     };
2906 
2907     union
2908     {
2909         __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
2910                                            *                  Setting Register                                           */
2911 
2912         struct
2913         {
2914             __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
2915                                            *   used to set the higher level of the window B.                             */
2916         } ADWINULB_b;
2917     };
2918 
2919     union
2920     {
2921         __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
2922 
2923         struct
2924         {
2925             __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
2926                                         *   the comparative result of CH (AN000-AN027, temperature
2927                                         *   sensor, and internal reference voltage) made the object
2928                                         *   of window B relation condition.                                           */
2929             uint8_t : 7;
2930         } ADCMPBSR_b;
2931     };
2932     __IM uint8_t  RESERVED12;
2933     __IM uint16_t RESERVED13;
2934 
2935     union
2936     {
2937         __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
2938 
2939         struct
2940         {
2941             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
2942                                         *   registers that sequentially store all A/D converted values.
2943                                         *   The automatic clear function is not applied to these registers.           */
2944         } ADBUF0_b;
2945     };
2946 
2947     union
2948     {
2949         __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
2950 
2951         struct
2952         {
2953             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
2954                                         *   registers that sequentially store all A/D converted values.
2955                                         *   The automatic clear function is not applied to these registers.           */
2956         } ADBUF1_b;
2957     };
2958 
2959     union
2960     {
2961         __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
2962 
2963         struct
2964         {
2965             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
2966                                         *   registers that sequentially store all A/D converted values.
2967                                         *   The automatic clear function is not applied to these registers.           */
2968         } ADBUF2_b;
2969     };
2970 
2971     union
2972     {
2973         __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
2974 
2975         struct
2976         {
2977             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
2978                                         *   registers that sequentially store all A/D converted values.
2979                                         *   The automatic clear function is not applied to these registers.           */
2980         } ADBUF3_b;
2981     };
2982 
2983     union
2984     {
2985         __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
2986 
2987         struct
2988         {
2989             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
2990                                         *   registers that sequentially store all A/D converted values.
2991                                         *   The automatic clear function is not applied to these registers.           */
2992         } ADBUF4_b;
2993     };
2994 
2995     union
2996     {
2997         __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
2998 
2999         struct
3000         {
3001             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3002                                         *   registers that sequentially store all A/D converted values.
3003                                         *   The automatic clear function is not applied to these registers.           */
3004         } ADBUF5_b;
3005     };
3006 
3007     union
3008     {
3009         __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
3010 
3011         struct
3012         {
3013             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3014                                         *   registers that sequentially store all A/D converted values.
3015                                         *   The automatic clear function is not applied to these registers.           */
3016         } ADBUF6_b;
3017     };
3018 
3019     union
3020     {
3021         __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
3022 
3023         struct
3024         {
3025             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3026                                         *   registers that sequentially store all A/D converted values.
3027                                         *   The automatic clear function is not applied to these registers.           */
3028         } ADBUF7_b;
3029     };
3030 
3031     union
3032     {
3033         __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
3034 
3035         struct
3036         {
3037             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3038                                         *   registers that sequentially store all A/D converted values.
3039                                         *   The automatic clear function is not applied to these registers.           */
3040         } ADBUF8_b;
3041     };
3042 
3043     union
3044     {
3045         __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
3046 
3047         struct
3048         {
3049             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3050                                         *   registers that sequentially store all A/D converted values.
3051                                         *   The automatic clear function is not applied to these registers.           */
3052         } ADBUF9_b;
3053     };
3054 
3055     union
3056     {
3057         __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
3058 
3059         struct
3060         {
3061             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3062                                         *   registers that sequentially store all A/D converted values.
3063                                         *   The automatic clear function is not applied to these registers.           */
3064         } ADBUF10_b;
3065     };
3066 
3067     union
3068     {
3069         __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
3070 
3071         struct
3072         {
3073             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3074                                         *   registers that sequentially store all A/D converted values.
3075                                         *   The automatic clear function is not applied to these registers.           */
3076         } ADBUF11_b;
3077     };
3078 
3079     union
3080     {
3081         __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
3082 
3083         struct
3084         {
3085             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3086                                         *   registers that sequentially store all A/D converted values.
3087                                         *   The automatic clear function is not applied to these registers.           */
3088         } ADBUF12_b;
3089     };
3090 
3091     union
3092     {
3093         __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
3094 
3095         struct
3096         {
3097             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3098                                         *   registers that sequentially store all A/D converted values.
3099                                         *   The automatic clear function is not applied to these registers.           */
3100         } ADBUF13_b;
3101     };
3102 
3103     union
3104     {
3105         __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
3106 
3107         struct
3108         {
3109             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3110                                         *   registers that sequentially store all A/D converted values.
3111                                         *   The automatic clear function is not applied to these registers.           */
3112         } ADBUF14_b;
3113     };
3114 
3115     union
3116     {
3117         __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
3118 
3119         struct
3120         {
3121             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3122                                         *   registers that sequentially store all A/D converted values.
3123                                         *   The automatic clear function is not applied to these registers.           */
3124         } ADBUF15_b;
3125     };
3126 
3127     union
3128     {
3129         __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
3130 
3131         struct
3132         {
3133             __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
3134             uint8_t             : 7;
3135         } ADBUFEN_b;
3136     };
3137     __IM uint8_t RESERVED14;
3138 
3139     union
3140     {
3141         __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
3142 
3143         struct
3144         {
3145             __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
3146                                         *   data buffer to which the next A/D converted data is transferred.          */
3147             __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
3148             uint8_t             : 3;
3149         } ADBUFPTR_b;
3150     };
3151     __IM uint8_t  RESERVED15;
3152     __IM uint32_t RESERVED16[2];
3153     __IM uint8_t  RESERVED17;
3154 
3155     union
3156     {
3157         __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
3158 
3159         struct
3160         {
3161             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
3162         } ADSSTRL_b;
3163     };
3164 
3165     union
3166     {
3167         __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
3168 
3169         struct
3170         {
3171             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
3172         } ADSSTRT_b;
3173     };
3174 
3175     union
3176     {
3177         __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
3178 
3179         struct
3180         {
3181             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
3182         } ADSSTRO_b;
3183     };
3184 
3185     union
3186     {
3187         __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
3188 
3189         struct
3190         {
3191             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
3192         } ADSSTR_b[16];
3193     };
3194 
3195     union
3196     {
3197         __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
3198 
3199         struct
3200         {
3201             __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
3202             __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
3203             __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
3204             __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
3205             uint16_t             : 12;
3206         } ADANIM_b;
3207     };
3208 
3209     union
3210     {
3211         __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
3212 
3213         struct
3214         {
3215             uint8_t              : 6;
3216             __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
3217             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
3218         } ADCALEXE_b;
3219     };
3220     __IM uint8_t RESERVED18;
3221 
3222     union
3223     {
3224         __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
3225                                           *                  Register                                                   */
3226 
3227         struct
3228         {
3229             __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
3230             __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
3231             __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
3232             __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
3233             uint8_t                 : 2;
3234             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
3235         } VREFAMPCNT_b;
3236     };
3237     __IM uint8_t  RESERVED19;
3238     __IM uint16_t RESERVED20;
3239 
3240     union
3241     {
3242         __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
3243 
3244         struct
3245         {
3246             __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
3247         } ADRD_b;
3248     };
3249 
3250     union
3251     {
3252         __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
3253 
3254         struct
3255         {
3256             __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
3257             uint8_t             : 6;
3258         } ADRST_b;
3259     };
3260     __IM uint8_t  RESERVED21;
3261     __IM uint32_t RESERVED22[41];
3262 
3263     union
3264     {
3265         __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
3266 
3267         struct
3268         {
3269             __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
3270             __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
3271             __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
3272             __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
3273             __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
3274             __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
3275             __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
3276             __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
3277             __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
3278             __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
3279             __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
3280             __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
3281             __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
3282             __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
3283             __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
3284             __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
3285         } ADPGACR_b;
3286     };
3287 
3288     union
3289     {
3290         __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
3291                                           *                  Register 0                                                 */
3292 
3293         struct
3294         {
3295             __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
3296                                           *   b) when the shingle end is input and each PGA P000 is set.
3297                                           *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
3298                                           *   sets the gain magnification when the differential motion
3299                                           *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
3300             __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
3301                                           *   b) when the shingle end is input and each PGA P001 is set.
3302                                           *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
3303                                           *   sets the gain magnification when the differential motion
3304                                           *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
3305             __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
3306                                           *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
3307                                           *   each PGA P002 is set. When the differential motion is input,
3308                                           *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
3309                                           *   the differential motion is input by the combination with
3310                                           *   ADPGSDCR0.P002DG 1:0.                                                     */
3311             __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
3312                                           *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
3313                                           *   each PGA P003 is set. When the differential motion is input,
3314                                           *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
3315                                           *   the differential motion is input by the combination with
3316                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
3317         } ADPGAGS0_b;
3318     };
3319     __IM uint32_t RESERVED23[3];
3320 
3321     union
3322     {
3323         __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
3324                                          *                  Input Control Register                                     */
3325 
3326         struct
3327         {
3328             __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
3329                                          *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
3330             uint16_t               : 1;
3331             __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
3332             __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
3333                                          *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
3334             uint16_t               : 1;
3335             __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
3336             __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
3337                                          *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
3338             uint16_t               : 1;
3339             __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
3340             __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
3341                                          *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
3342             uint16_t               : 1;
3343             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
3344         } ADPGADCR0_b;
3345     };
3346     __IM uint16_t RESERVED24;
3347 
3348     union
3349     {
3350         __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
3351                                         *                  Input Bias Select Register 0                               */
3352 
3353         struct
3354         {
3355             __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
3356                                         *   SelectNOTE: This bit selects the input bias voltage value
3357                                         *   when differential inputs are used.                                        */
3358             uint8_t : 7;
3359         } ADPGADBS0_b;
3360     };
3361 
3362     union
3363     {
3364         __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
3365                                         *                  Input Bias Select Register 1                               */
3366 
3367         struct
3368         {
3369             __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
3370                                         *   This bit selects the input bias voltage value when differential
3371                                         *   inputs are used.                                                          */
3372             uint8_t : 7;
3373         } ADPGADBS1_b;
3374     };
3375     __IM uint16_t RESERVED25;
3376     __IM uint32_t RESERVED26[10];
3377 
3378     union
3379     {
3380         __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
3381 
3382         struct
3383         {
3384             __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
3385             uint32_t              : 13;
3386             __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
3387             uint32_t              : 12;
3388         } ADREFMON_b;
3389     };
3390 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
3391 
3392 /* =========================================================================================================================== */
3393 /* ================                                           R_BUS                                           ================ */
3394 /* =========================================================================================================================== */
3395 
3396 /**
3397  * @brief Bus Interface (R_BUS)
3398  */
3399 
3400 typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
3401 {
3402     __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
3403     __IM uint32_t        RESERVED[480];
3404     __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
3405 
3406     union
3407     {
3408         __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
3409 
3410         struct
3411         {
3412             __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
3413             __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
3414             __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
3415             __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
3416             __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
3417             __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
3418             __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
3419             __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
3420             __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
3421             __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
3422             __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3423             __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3424             __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3425             __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3426             __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3427             __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3428         } CSRECEN_b;
3429     };
3430     __IM uint16_t          RESERVED1;
3431     __IM uint32_t          RESERVED2[223];
3432     __IOM R_BUS_SDRAM_Type SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
3433     __IM uint32_t          RESERVED3[235];
3434 
3435     union
3436     {
3437         __IOM R_BUS_OAD_Type  OAD;     /*!< (@ 0x00001000) Bus Operation After Detection Registers                    */
3438         __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers                               */
3439     };
3440     __IM uint32_t RESERVED4[58];
3441 
3442     union
3443     {
3444         union
3445         {
3446             __IOM uint32_t BUSMABT;      /*!< (@ 0x00001100) Bus Master Arbitration Control Register.                   */
3447 
3448             struct
3449             {
3450                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI.                                     */
3451                 uint32_t            : 31;
3452             } BUSMABT_b;
3453         };
3454         __IOM R_BUS_BUSS_Type BUSS[18];  /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
3455     };
3456     __IM uint32_t RESERVED5[46];
3457 
3458     union
3459     {
3460         __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers                  */
3461         __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers                  */
3462     };
3463     __IM uint32_t RESERVED6[33];
3464 
3465     union
3466     {
3467         __IOM uint32_t BUSDIVBYP;        /*!< (@ 0x00001300) Bus Divider Bypass Register.                               */
3468 
3469         struct
3470         {
3471             __IOM uint32_t EDMABPE  : 1; /*!< [0..0] Divider for EDMACBI bypass enable.                                 */
3472             uint32_t                : 2;
3473             __IOM uint32_t GDSSBPE  : 1; /*!< [3..3] Divider for GDSSBI bypass enable.                                  */
3474             uint32_t                : 12;
3475             __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable.                              */
3476             uint32_t                : 15;
3477         } BUSDIVBYP_b;
3478     };
3479     __IM uint32_t            RESERVED7[319];
3480     __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers                                        */
3481     __IM uint32_t            RESERVED8[16];
3482 
3483     union
3484     {
3485         __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers                                    */
3486         __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address
3487                                               *                  and Read/Write Status registers.                           */
3488     };
3489     __IM uint32_t RESERVED9[28];
3490 
3491     union
3492     {
3493         __IOM R_BUS_BUSERRb_Type    BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers                                        */
3494         __IOM R_BUS_DMACDTCERR_Type DMACDTCERR;  /*!< (@ 0x00001A00) DMAC/DTC Error Registers                                   */
3495     };
3496     __IM uint32_t           RESERVED10[16];
3497     __IOM R_BUS_MBWERR_Type MBWERR;              /*!< (@ 0x00001B00) Master Bufferable Write Error Registers                    */
3498     __IM uint32_t           RESERVED11[5];
3499     __IOM R_BUS_MBWERR_Type SBWERR;              /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers                     */
3500 } R_BUS_Type;                                    /*!< Size = 6956 (0x1b2c)                                                      */
3501 
3502 /* =========================================================================================================================== */
3503 /* ================                                           R_CAC                                           ================ */
3504 /* =========================================================================================================================== */
3505 
3506 /**
3507  * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
3508  */
3509 
3510 typedef struct                         /*!< (@ 0x40044600) R_CAC Structure                                            */
3511 {
3512     union
3513     {
3514         __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
3515 
3516         struct
3517         {
3518             __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
3519             uint8_t            : 7;
3520         } CACR0_b;
3521     };
3522 
3523     union
3524     {
3525         __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
3526 
3527         struct
3528         {
3529             __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
3530             __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
3531             __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
3532             __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
3533         } CACR1_b;
3534     };
3535 
3536     union
3537     {
3538         __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
3539 
3540         struct
3541         {
3542             __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
3543             __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
3544             __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
3545                                         *   Select                                                                    */
3546             __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
3547         } CACR2_b;
3548     };
3549 
3550     union
3551     {
3552         __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
3553 
3554         struct
3555         {
3556             __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
3557             __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
3558             __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
3559             uint8_t              : 1;
3560             __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
3561             __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
3562             __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
3563             uint8_t              : 1;
3564         } CAICR_b;
3565     };
3566 
3567     union
3568     {
3569         __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
3570 
3571         struct
3572         {
3573             __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
3574             __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
3575             __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
3576             uint8_t            : 5;
3577         } CASTR_b;
3578     };
3579     __IM uint8_t RESERVED;
3580 
3581     union
3582     {
3583         __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
3584 
3585         struct
3586         {
3587             __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
3588                                          *   the upper-limit value of the frequency.                                   */
3589         } CAULVR_b;
3590     };
3591 
3592     union
3593     {
3594         __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
3595 
3596         struct
3597         {
3598             __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
3599                                          *   the lower-limit value of the frequency.                                   */
3600         } CALLVR_b;
3601     };
3602 
3603     union
3604     {
3605         __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
3606 
3607         struct
3608         {
3609             __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
3610                                          *   the counter value at the time a valid reference signal
3611                                          *   edge is input                                                             */
3612         } CACNTBR_b;
3613     };
3614 } R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
3615 
3616 /* =========================================================================================================================== */
3617 /* ================                                          R_CAN0                                           ================ */
3618 /* =========================================================================================================================== */
3619 
3620 /**
3621  * @brief Controller Area Network (CAN) Module (R_CAN0)
3622  */
3623 
3624 typedef struct                         /*!< (@ 0x40050000) R_CAN0 Structure                                           */
3625 {
3626     __IM uint32_t        RESERVED[128];
3627     __IOM R_CAN0_MB_Type MB[32];       /*!< (@ 0x00000200) Mailbox                                                    */
3628 
3629     union
3630     {
3631         __IOM uint32_t MKR[8];         /*!< (@ 0x00000400) Mask Register                                              */
3632 
3633         struct
3634         {
3635             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
3636             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
3637             uint32_t           : 3;
3638         } MKR_b[8];
3639     };
3640 
3641     union
3642     {
3643         __IOM uint32_t FIDCR[2];       /*!< (@ 0x00000420) FIFO Received ID Compare Registers                         */
3644 
3645         struct
3646         {
3647             __IOM uint32_t EID : 18;   /*!< [17..0] Extended ID                                                       */
3648             __IOM uint32_t SID : 11;   /*!< [28..18] Standard ID                                                      */
3649             uint32_t           : 1;
3650             __IOM uint32_t RTR : 1;    /*!< [30..30] Remote Transmission Request                                      */
3651             __IOM uint32_t IDE : 1;    /*!< [31..31] ID Extension                                                     */
3652         } FIDCR_b[2];
3653     };
3654 
3655     union
3656     {
3657         __IOM uint32_t MKIVLR;         /*!< (@ 0x00000428) Mask Invalid Register                                      */
3658 
3659         struct
3660         {
3661             __IOM uint32_t MB0  : 1;   /*!< [0..0] mailbox 0 Mask Invalid                                             */
3662             __IOM uint32_t MB1  : 1;   /*!< [1..1] mailbox 1 Mask Invalid                                             */
3663             __IOM uint32_t MB2  : 1;   /*!< [2..2] mailbox 2 Mask Invalid                                             */
3664             __IOM uint32_t MB3  : 1;   /*!< [3..3] mailbox 3 Mask Invalid                                             */
3665             __IOM uint32_t MB4  : 1;   /*!< [4..4] mailbox 4 Mask Invalid                                             */
3666             __IOM uint32_t MB5  : 1;   /*!< [5..5] mailbox 5 Mask Invalid                                             */
3667             __IOM uint32_t MB6  : 1;   /*!< [6..6] mailbox 6 Mask Invalid                                             */
3668             __IOM uint32_t MB7  : 1;   /*!< [7..7] mailbox 7 Mask Invalid                                             */
3669             __IOM uint32_t MB8  : 1;   /*!< [8..8] mailbox 8 Mask Invalid                                             */
3670             __IOM uint32_t MB9  : 1;   /*!< [9..9] mailbox 9 Mask Invalid                                             */
3671             __IOM uint32_t MB10 : 1;   /*!< [10..10] mailbox 10 Mask Invalid                                          */
3672             __IOM uint32_t MB11 : 1;   /*!< [11..11] mailbox 11 Mask Invalid                                          */
3673             __IOM uint32_t MB12 : 1;   /*!< [12..12] mailbox 12 Mask Invalid                                          */
3674             __IOM uint32_t MB13 : 1;   /*!< [13..13] mailbox 13 Mask Invalid                                          */
3675             __IOM uint32_t MB14 : 1;   /*!< [14..14] mailbox 14 Mask Invalid                                          */
3676             __IOM uint32_t MB15 : 1;   /*!< [15..15] mailbox 15 Mask Invalid                                          */
3677             __IOM uint32_t MB16 : 1;   /*!< [16..16] mailbox 16 Mask Invalid                                          */
3678             __IOM uint32_t MB17 : 1;   /*!< [17..17] mailbox 17 Mask Invalid                                          */
3679             __IOM uint32_t MB18 : 1;   /*!< [18..18] mailbox 18 Mask Invalid                                          */
3680             __IOM uint32_t MB19 : 1;   /*!< [19..19] mailbox 19 Mask Invalid                                          */
3681             __IOM uint32_t MB20 : 1;   /*!< [20..20] mailbox 20 Mask Invalid                                          */
3682             __IOM uint32_t MB21 : 1;   /*!< [21..21] mailbox 21 Mask Invalid                                          */
3683             __IOM uint32_t MB22 : 1;   /*!< [22..22] mailbox 22 Mask Invalid                                          */
3684             __IOM uint32_t MB23 : 1;   /*!< [23..23] mailbox 23 Mask Invalid                                          */
3685             __IOM uint32_t MB24 : 1;   /*!< [24..24] mailbox 24 Mask Invalid                                          */
3686             __IOM uint32_t MB25 : 1;   /*!< [25..25] mailbox 25 Mask Invalid                                          */
3687             __IOM uint32_t MB26 : 1;   /*!< [26..26] mailbox 26 Mask Invalid                                          */
3688             __IOM uint32_t MB27 : 1;   /*!< [27..27] mailbox 27 Mask Invalid                                          */
3689             __IOM uint32_t MB28 : 1;   /*!< [28..28] mailbox 28 Mask Invalid                                          */
3690             __IOM uint32_t MB29 : 1;   /*!< [29..29] mailbox 29 Mask Invalid                                          */
3691             __IOM uint32_t MB30 : 1;   /*!< [30..30] mailbox 30 Mask Invalid                                          */
3692             __IOM uint32_t MB31 : 1;   /*!< [31..31] mailbox 31 Mask Invalid                                          */
3693         } MKIVLR_b;
3694     };
3695 
3696     union
3697     {
3698         union
3699         {
3700             __IOM uint32_t MIER;         /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register                          */
3701 
3702             struct
3703             {
3704                 __IOM uint32_t MB0  : 1; /*!< [0..0] mailbox 0 Interrupt Enable                                         */
3705                 __IOM uint32_t MB1  : 1; /*!< [1..1] mailbox 1 Interrupt Enable                                         */
3706                 __IOM uint32_t MB2  : 1; /*!< [2..2] mailbox 2 Interrupt Enable                                         */
3707                 __IOM uint32_t MB3  : 1; /*!< [3..3] mailbox 3 Interrupt Enable                                         */
3708                 __IOM uint32_t MB4  : 1; /*!< [4..4] mailbox 4 Interrupt Enable                                         */
3709                 __IOM uint32_t MB5  : 1; /*!< [5..5] mailbox 5 Interrupt Enable                                         */
3710                 __IOM uint32_t MB6  : 1; /*!< [6..6] mailbox 6 Interrupt Enable                                         */
3711                 __IOM uint32_t MB7  : 1; /*!< [7..7] mailbox 7 Interrupt Enable                                         */
3712                 __IOM uint32_t MB8  : 1; /*!< [8..8] mailbox 8 Interrupt Enable                                         */
3713                 __IOM uint32_t MB9  : 1; /*!< [9..9] mailbox 9 Interrupt Enable                                         */
3714                 __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable                                      */
3715                 __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable                                      */
3716                 __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable                                      */
3717                 __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable                                      */
3718                 __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable                                      */
3719                 __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable                                      */
3720                 __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable                                      */
3721                 __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable                                      */
3722                 __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable                                      */
3723                 __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable                                      */
3724                 __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable                                      */
3725                 __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable                                      */
3726                 __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable                                      */
3727                 __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable                                      */
3728                 __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable                                      */
3729                 __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable                                      */
3730                 __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable                                      */
3731                 __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable                                      */
3732                 __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable                                      */
3733                 __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable                                      */
3734                 __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable                                      */
3735                 __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable                                      */
3736             } MIER_b;
3737         };
3738 
3739         union
3740         {
3741             __IOM uint32_t MIER_FIFO;    /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox
3742                                           *                  Mode                                                       */
3743 
3744             struct
3745             {
3746                 __IOM uint32_t MB0  : 1; /*!< [0..0] mailbox 0 Interrupt Enable                                         */
3747                 __IOM uint32_t MB1  : 1; /*!< [1..1] mailbox 1 Interrupt Enable                                         */
3748                 __IOM uint32_t MB2  : 1; /*!< [2..2] mailbox 2 Interrupt Enable                                         */
3749                 __IOM uint32_t MB3  : 1; /*!< [3..3] mailbox 3 Interrupt Enable                                         */
3750                 __IOM uint32_t MB4  : 1; /*!< [4..4] mailbox 4 Interrupt Enable                                         */
3751                 __IOM uint32_t MB5  : 1; /*!< [5..5] mailbox 5 Interrupt Enable                                         */
3752                 __IOM uint32_t MB6  : 1; /*!< [6..6] mailbox 6 Interrupt Enable                                         */
3753                 __IOM uint32_t MB7  : 1; /*!< [7..7] mailbox 7 Interrupt Enable                                         */
3754                 __IOM uint32_t MB8  : 1; /*!< [8..8] mailbox 8 Interrupt Enable                                         */
3755                 __IOM uint32_t MB9  : 1; /*!< [9..9] mailbox 9 Interrupt Enable                                         */
3756                 __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable                                      */
3757                 __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable                                      */
3758                 __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable                                      */
3759                 __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable                                      */
3760                 __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable                                      */
3761                 __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable                                      */
3762                 __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable                                      */
3763                 __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable                                      */
3764                 __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable                                      */
3765                 __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable                                      */
3766                 __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable                                      */
3767                 __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable                                      */
3768                 __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable                                      */
3769                 __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable                                      */
3770                 __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable                                   */
3771                 __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control                */
3772                 uint32_t            : 2;
3773                 __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable                                    */
3774                 __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control                 */
3775                 uint32_t            : 2;
3776             } MIER_FIFO_b;
3777         };
3778     };
3779     __IM uint32_t RESERVED1[252];
3780 
3781     union
3782     {
3783         union
3784         {
3785             __IOM uint8_t MCTL_TX[32];       /*!< (@ 0x00000820) Message Control Register for Transmit                      */
3786 
3787             struct
3788             {
3789                 __IOM uint8_t SENTDATA  : 1; /*!< [0..0] Transmission Complete Flag                                         */
3790                 __IM uint8_t  TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox
3791                                               *   setting enabled)                                                          */
3792                 __IOM uint8_t TRMABT : 1;    /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting
3793                                               *   enabled)                                                                  */
3794                 uint8_t               : 1;
3795                 __IOM uint8_t ONESHOT : 1;   /*!< [4..4] One-Shot Enable                                                    */
3796                 uint8_t               : 1;
3797                 __IOM uint8_t RECREQ  : 1;   /*!< [6..6] Receive Mailbox Request                                            */
3798                 __IOM uint8_t TRMREQ  : 1;   /*!< [7..7] Transmit Mailbox Request                                           */
3799             } MCTL_TX_b[32];
3800         };
3801 
3802         union
3803         {
3804             __IOM uint8_t MCTL_RX[32];       /*!< (@ 0x00000820) Message Control Register for Receive                       */
3805 
3806             struct
3807             {
3808                 __IOM uint8_t NEWDATA   : 1; /*!< [0..0] Reception Complete Flag                                            */
3809                 __IM uint8_t  INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting
3810                                               *   enabled)                                                                  */
3811                 __IOM uint8_t MSGLOST : 1;   /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled)                 */
3812                 uint8_t               : 1;
3813                 __IOM uint8_t ONESHOT : 1;   /*!< [4..4] One-Shot Enable                                                    */
3814                 uint8_t               : 1;
3815                 __IOM uint8_t RECREQ  : 1;   /*!< [6..6] Receive Mailbox Request                                            */
3816                 __IOM uint8_t TRMREQ  : 1;   /*!< [7..7] Transmit Mailbox Request                                           */
3817             } MCTL_RX_b[32];
3818         };
3819     };
3820 
3821     union
3822     {
3823         __IOM uint16_t CTLR;           /*!< (@ 0x00000840) Control Register                                           */
3824 
3825         struct
3826         {
3827             __IOM uint16_t MBM  : 1;   /*!< [0..0] CAN Mailbox Mode Select                                            */
3828             __IOM uint16_t IDFM : 2;   /*!< [2..1] ID Format Mode Select                                              */
3829             __IOM uint16_t MLM  : 1;   /*!< [3..3] Message Lost Mode Select                                           */
3830             __IOM uint16_t TPM  : 1;   /*!< [4..4] Transmission Priority Mode Select                                  */
3831             __IOM uint16_t TSRC : 1;   /*!< [5..5] Time Stamp Counter Reset Command                                   */
3832             __IOM uint16_t TSPS : 2;   /*!< [7..6] Time Stamp Prescaler Select                                        */
3833             __IOM uint16_t CANM : 2;   /*!< [9..8] CAN Operating Mode Select                                          */
3834             __IOM uint16_t SLPM : 1;   /*!< [10..10] CAN Sleep Mode                                                   */
3835             __IOM uint16_t BOM  : 2;   /*!< [12..11] Bus-Off Recovery Mode by a program request                       */
3836             __IOM uint16_t RBOC : 1;   /*!< [13..13] Forcible Return From Bus-Off                                     */
3837             uint16_t            : 2;
3838         } CTLR_b;
3839     };
3840 
3841     union
3842     {
3843         __IM uint16_t STR;             /*!< (@ 0x00000842) Status Register                                            */
3844 
3845         struct
3846         {
3847             __IM uint16_t NDST  : 1;   /*!< [0..0] NEWDATA Status Flag                                                */
3848             __IM uint16_t SDST  : 1;   /*!< [1..1] SENTDATA Status Flag                                               */
3849             __IM uint16_t RFST  : 1;   /*!< [2..2] Receive FIFO Status Flag                                           */
3850             __IM uint16_t TFST  : 1;   /*!< [3..3] Transmit FIFO Status Flag                                          */
3851             __IM uint16_t NMLST : 1;   /*!< [4..4] Normal Mailbox Message Lost Status Flag                            */
3852             __IM uint16_t FMLST : 1;   /*!< [5..5] FIFO Mailbox Message Lost Status Flag                              */
3853             __IM uint16_t TABST : 1;   /*!< [6..6] Transmission Abort Status Flag                                     */
3854             __IM uint16_t EST   : 1;   /*!< [7..7] Error Status Flag                                                  */
3855             __IM uint16_t RSTST : 1;   /*!< [8..8] CAN Reset Status Flag                                              */
3856             __IM uint16_t HLTST : 1;   /*!< [9..9] CAN Halt Status Flag                                               */
3857             __IM uint16_t SLPST : 1;   /*!< [10..10] CAN Sleep Status Flag                                            */
3858             __IM uint16_t EPST  : 1;   /*!< [11..11] Error-Passive Status Flag                                        */
3859             __IM uint16_t BOST  : 1;   /*!< [12..12] Bus-Off Status Flag                                              */
3860             __IM uint16_t TRMST : 1;   /*!< [13..13] Transmit Status Flag (transmitter)                               */
3861             __IM uint16_t RECST : 1;   /*!< [14..14] Receive Status Flag (receiver)                                   */
3862             uint16_t            : 1;
3863         } STR_b;
3864     };
3865 
3866     union
3867     {
3868         __IOM uint32_t BCR;            /*!< (@ 0x00000844) Bit Configuration Register                                 */
3869 
3870         struct
3871         {
3872             __IOM uint32_t CCLKS : 1;  /*!< [0..0] CAN Clock Source Selection                                         */
3873             uint32_t             : 7;
3874             __IOM uint32_t TSEG2 : 3;  /*!< [10..8] Time Segment 2 Control                                            */
3875             uint32_t             : 1;
3876             __IOM uint32_t SJW   : 2;  /*!< [13..12] Resynchronization Jump Width Control                             */
3877             uint32_t             : 2;
3878             __IOM uint32_t BRP   : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the
3879                                         *   frequency of the CAN communication clock (fCANCLK).                       */
3880             uint32_t             : 2;
3881             __IOM uint32_t TSEG1 : 4;  /*!< [31..28] Time Segment 1 Control                                           */
3882         } BCR_b;
3883     };
3884 
3885     union
3886     {
3887         __IOM uint8_t RFCR;            /*!< (@ 0x00000848) Receive FIFO Control Register                              */
3888 
3889         struct
3890         {
3891             __IOM uint8_t RFE   : 1;   /*!< [0..0] Receive FIFO Enable                                                */
3892             __IM uint8_t  RFUST : 3;   /*!< [3..1] Receive FIFO Unread Message Number Status                          */
3893             __IOM uint8_t RFMLF : 1;   /*!< [4..4] Receive FIFO Message Lost Flag                                     */
3894             __IM uint8_t  RFFST : 1;   /*!< [5..5] Receive FIFO Full Status Flag                                      */
3895             __IM uint8_t  RFWST : 1;   /*!< [6..6] Receive FIFO Buffer Warning Status Flag                            */
3896             __IM uint8_t  RFEST : 1;   /*!< [7..7] Receive FIFO Empty Status Flag                                     */
3897         } RFCR_b;
3898     };
3899 
3900     union
3901     {
3902         __OM uint8_t RFPCR;            /*!< (@ 0x00000849) Receive FIFO Pointer Control Register                      */
3903 
3904         struct
3905         {
3906             __OM uint8_t RFPCR : 8;    /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented
3907                                         *   by writing FFh to RFPCR.                                                  */
3908         } RFPCR_b;
3909     };
3910 
3911     union
3912     {
3913         __IOM uint8_t TFCR;            /*!< (@ 0x0000084A) Transmit FIFO Control Register                             */
3914 
3915         struct
3916         {
3917             __IOM uint8_t TFE   : 1;   /*!< [0..0] Transmit FIFO Enable                                               */
3918             __IM uint8_t  TFUST : 3;   /*!< [3..1] Transmit FIFO Unsent Message Number Status                         */
3919             uint8_t             : 2;
3920             __IM uint8_t TFFST  : 1;   /*!< [6..6] Transmit FIFO Full Status                                          */
3921             __IM uint8_t TFEST  : 1;   /*!< [7..7] Transmit FIFO Empty Status                                         */
3922         } TFCR_b;
3923     };
3924 
3925     union
3926     {
3927         __OM uint8_t TFPCR;            /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register                     */
3928 
3929         struct
3930         {
3931             __OM uint8_t TFPCR : 8;    /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented
3932                                         *   by writing FFh to TFPCR.                                                  */
3933         } TFPCR_b;
3934     };
3935 
3936     union
3937     {
3938         __IOM uint8_t EIER;            /*!< (@ 0x0000084C) Error Interrupt Enable Register                            */
3939 
3940         struct
3941         {
3942             __IOM uint8_t BEIE  : 1;   /*!< [0..0] Bus Error Interrupt Enable                                         */
3943             __IOM uint8_t EWIE  : 1;   /*!< [1..1] Error-Warning Interrupt Enable                                     */
3944             __IOM uint8_t EPIE  : 1;   /*!< [2..2] Error-Passive Interrupt Enable                                     */
3945             __IOM uint8_t BOEIE : 1;   /*!< [3..3] Bus-Off Entry Interrupt Enable                                     */
3946             __IOM uint8_t BORIE : 1;   /*!< [4..4] Bus-Off Recovery Interrupt Enable                                  */
3947             __IOM uint8_t ORIE  : 1;   /*!< [5..5] Overrun Interrupt Enable                                           */
3948             __IOM uint8_t OLIE  : 1;   /*!< [6..6] Overload Frame Transmit Interrupt Enable                           */
3949             __IOM uint8_t BLIE  : 1;   /*!< [7..7] Bus Lock Interrupt Enable                                          */
3950         } EIER_b;
3951     };
3952 
3953     union
3954     {
3955         __IOM uint8_t EIFR;            /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register                      */
3956 
3957         struct
3958         {
3959             __IOM uint8_t BEIF  : 1;   /*!< [0..0] Bus Error Detect Flag                                              */
3960             __IOM uint8_t EWIF  : 1;   /*!< [1..1] Error-Warning Detect Flag                                          */
3961             __IOM uint8_t EPIF  : 1;   /*!< [2..2] Error-Passive Detect Flag                                          */
3962             __IOM uint8_t BOEIF : 1;   /*!< [3..3] Bus-Off Entry Detect Flag                                          */
3963             __IOM uint8_t BORIF : 1;   /*!< [4..4] Bus-Off Recovery Detect Flag                                       */
3964             __IOM uint8_t ORIF  : 1;   /*!< [5..5] Receive Overrun Detect Flag                                        */
3965             __IOM uint8_t OLIF  : 1;   /*!< [6..6] Overload Frame Transmission Detect Flag                            */
3966             __IOM uint8_t BLIF  : 1;   /*!< [7..7] Bus Lock Detect Flag                                               */
3967         } EIFR_b;
3968     };
3969 
3970     union
3971     {
3972         __IM uint8_t RECR;             /*!< (@ 0x0000084E) Receive Error Count Register                               */
3973 
3974         struct
3975         {
3976             __IM uint8_t RECR : 8;     /*!< [7..0] Receive error count functionRECR increments or decrements
3977                                         *   the counter value according to the error status of the
3978                                         *   CAN module during reception.                                              */
3979         } RECR_b;
3980     };
3981 
3982     union
3983     {
3984         __IM uint8_t TECR;             /*!< (@ 0x0000084F) Transmit Error Count Register                              */
3985 
3986         struct
3987         {
3988             __IM uint8_t TECR : 8;     /*!< [7..0] Transmit error count functionTECR increments or decrements
3989                                         *   the counter value according to the error status of the
3990                                         *   CAN module during transmission.                                           */
3991         } TECR_b;
3992     };
3993 
3994     union
3995     {
3996         __IOM uint8_t ECSR;            /*!< (@ 0x00000850) Error Code Store Register                                  */
3997 
3998         struct
3999         {
4000             __IOM uint8_t SEF  : 1;    /*!< [0..0] Stuff Error Flag                                                   */
4001             __IOM uint8_t FEF  : 1;    /*!< [1..1] Form Error Flag                                                    */
4002             __IOM uint8_t AEF  : 1;    /*!< [2..2] ACK Error Flag                                                     */
4003             __IOM uint8_t CEF  : 1;    /*!< [3..3] CRC Error Flag                                                     */
4004             __IOM uint8_t BE1F : 1;    /*!< [4..4] Bit Error (recessive) Flag                                         */
4005             __IOM uint8_t BE0F : 1;    /*!< [5..5] Bit Error (dominant) Flag                                          */
4006             __IOM uint8_t ADEF : 1;    /*!< [6..6] ACK Delimiter Error Flag                                           */
4007             __IOM uint8_t EDPM : 1;    /*!< [7..7] Error Display Mode Select                                          */
4008         } ECSR_b;
4009     };
4010 
4011     union
4012     {
4013         __IOM uint8_t CSSR;            /*!< (@ 0x00000851) Channel Search Support Register                            */
4014 
4015         struct
4016         {
4017             __IOM uint8_t CSSR : 8;    /*!< [7..0] When the value for the channel search is input, the channel
4018                                         *   number is output to MSSR.                                                 */
4019         } CSSR_b;
4020     };
4021 
4022     union
4023     {
4024         __IM uint8_t MSSR;             /*!< (@ 0x00000852) Mailbox Search Status Register                             */
4025 
4026         struct
4027         {
4028             __IM uint8_t MBNST : 5;    /*!< [4..0] Search Result Mailbox Number Status These bits output
4029                                         *   the smallest mailbox number that is searched in each mode
4030                                         *   of MSMR.                                                                  */
4031             uint8_t           : 2;
4032             __IM uint8_t SEST : 1;     /*!< [7..7] Search Result Status                                               */
4033         } MSSR_b;
4034     };
4035 
4036     union
4037     {
4038         __IOM uint8_t MSMR;            /*!< (@ 0x00000853) Mailbox Search Mode Register                               */
4039 
4040         struct
4041         {
4042             __IOM uint8_t MBSM : 2;    /*!< [1..0] Mailbox Search Mode Select                                         */
4043             uint8_t            : 6;
4044         } MSMR_b;
4045     };
4046 
4047     union
4048     {
4049         __IM uint16_t TSR;             /*!< (@ 0x00000854) Time Stamp Register                                        */
4050 
4051         struct
4052         {
4053             __IM uint16_t TSR : 16;    /*!< [15..0] Free-running counter value for the time stamp function            */
4054         } TSR_b;
4055     };
4056 
4057     union
4058     {
4059         __IOM uint16_t AFSR;           /*!< (@ 0x00000856) Acceptance Filter Support Register                         */
4060 
4061         struct
4062         {
4063             __IOM uint16_t AFSR : 16;  /*!< [15..0] After the standard ID of a received message is written,
4064                                         *   the value converted for data table search can be read.                    */
4065         } AFSR_b;
4066     };
4067 
4068     union
4069     {
4070         __IOM uint8_t TCR;             /*!< (@ 0x00000858) Test Control Register                                      */
4071 
4072         struct
4073         {
4074             __IOM uint8_t TSTE : 1;    /*!< [0..0] CAN Test Mode Enable                                               */
4075             __IOM uint8_t TSTM : 2;    /*!< [2..1] CAN Test Mode Select                                               */
4076             uint8_t            : 5;
4077         } TCR_b;
4078     };
4079     __IM uint8_t  RESERVED2;
4080     __IM uint16_t RESERVED3;
4081 } R_CAN0_Type;                         /*!< Size = 2140 (0x85c)                                                       */
4082 
4083 /* =========================================================================================================================== */
4084 /* ================                                           R_CRC                                           ================ */
4085 /* =========================================================================================================================== */
4086 
4087 /**
4088  * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
4089  */
4090 
4091 typedef struct                         /*!< (@ 0x40074000) R_CRC Structure                                            */
4092 {
4093     union
4094     {
4095         __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
4096 
4097         struct
4098         {
4099             __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
4100             uint8_t              : 3;
4101             __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
4102             __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
4103         } CRCCR0_b;
4104     };
4105 
4106     union
4107     {
4108         __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
4109 
4110         struct
4111         {
4112             uint8_t              : 6;
4113             __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
4114             __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
4115         } CRCCR1_b;
4116     };
4117     __IM uint16_t RESERVED;
4118 
4119     union
4120     {
4121         union
4122         {
4123             __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
4124 
4125             struct
4126             {
4127                 __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
4128             } CRCDIR_b;
4129         };
4130 
4131         union
4132         {
4133             __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
4134 
4135             struct
4136             {
4137                 __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
4138                                               *   )                                                                         */
4139             } CRCDIR_BY_b;
4140         };
4141     };
4142 
4143     union
4144     {
4145         union
4146         {
4147             __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
4148 
4149             struct
4150             {
4151                 __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
4152             } CRCDOR_b;
4153         };
4154 
4155         union
4156         {
4157             __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
4158 
4159             struct
4160             {
4161                 __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
4162                                                 *   )                                                                         */
4163             } CRCDOR_HA_b;
4164         };
4165 
4166         union
4167         {
4168             __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
4169 
4170             struct
4171             {
4172                 __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
4173             } CRCDOR_BY_b;
4174         };
4175     };
4176 
4177     union
4178     {
4179         __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
4180 
4181         struct
4182         {
4183             __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
4184             uint16_t             : 2;
4185         } CRCSAR_b;
4186     };
4187     __IM uint16_t RESERVED1;
4188 } R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
4189 
4190 /* =========================================================================================================================== */
4191 /* ================                                          R_CTSU                                           ================ */
4192 /* =========================================================================================================================== */
4193 
4194 /**
4195  * @brief Capacitive Touch Sensing Unit (R_CTSU)
4196  */
4197 
4198 typedef struct                            /*!< (@ 0x40081000) R_CTSU Structure                                           */
4199 {
4200     union
4201     {
4202         __IOM uint8_t CTSUCR0;            /*!< (@ 0x00000000) CTSU Control Register 0                                    */
4203 
4204         struct
4205         {
4206             __IOM uint8_t CTSUSTRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
4207             __IOM uint8_t CTSUCAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
4208             __IOM uint8_t CTSUSNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
4209             __IOM uint8_t CTSUIOC    : 1; /*!< [3..3] CTSU Transmit Pin Control                                          */
4210             __IOM uint8_t CTSUINIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
4211             uint8_t                  : 2;
4212             __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection                           */
4213         } CTSUCR0_b;
4214     };
4215 
4216     union
4217     {
4218         __IOM uint8_t CTSUCR1;            /*!< (@ 0x00000001) CTSU Control Register 1                                    */
4219 
4220         struct
4221         {
4222             __IOM uint8_t CTSUPON    : 1; /*!< [0..0] CTSU Power Supply Enable                                           */
4223             __IOM uint8_t CTSUCSW    : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control                              */
4224             __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting                           */
4225             __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment                              */
4226             __IOM uint8_t CTSUCLK    : 2; /*!< [5..4] CTSU Operating Clock Select                                        */
4227             __IOM uint8_t CTSUMD     : 2; /*!< [7..6] CTSU Measurement Mode Select                                       */
4228         } CTSUCR1_b;
4229     };
4230 
4231     union
4232     {
4233         __IOM uint8_t CTSUSDPRS;           /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register          */
4234 
4235         struct
4236         {
4237             __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended
4238                                             *   setting: 3 (0011b)                                                        */
4239             __IOM uint8_t CTSUPRMODE : 2;  /*!< [5..4] CTSU Base Period and Pulse Count Setting                           */
4240             __IOM uint8_t CTSUSOFF   : 1;  /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting                */
4241             uint8_t                  : 1;
4242         } CTSUSDPRS_b;
4243     };
4244 
4245     union
4246     {
4247         __IOM uint8_t CTSUSST;         /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register            */
4248 
4249         struct
4250         {
4251             __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value
4252                                         *   of these bits should be fixed to 00010000b.                               */
4253         } CTSUSST_b;
4254     };
4255 
4256     union
4257     {
4258         __IOM uint8_t CTSUMCH0;         /*!< (@ 0x00000004) CTSU Measurement Channel Register 0                        */
4259 
4260         struct
4261         {
4262             __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits
4263                                          *   is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0]
4264                                          *   bits = 00b).Note2: If the value of CTSUMCH0 was set to
4265                                          *   b'111111 in mode other than self-capacitor single scan
4266                                          *   mode, the measurement is stopped.                                         */
4267             uint8_t : 2;
4268         } CTSUMCH0_b;
4269     };
4270 
4271     union
4272     {
4273         __IOM uint8_t CTSUMCH1;        /*!< (@ 0x00000005) CTSU Measurement Channel Register 1                        */
4274 
4275         struct
4276         {
4277             __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1
4278                                         *   was set to b'111111, the measurement is stopped.                          */
4279             uint8_t : 2;
4280         } CTSUMCH1_b;
4281     };
4282 
4283     union
4284     {
4285         __IOM uint8_t CTSUCHAC[5];     /*!< (@ 0x00000006) CTSU Channel Enable Control Register                       */
4286 
4287         struct
4288         {
4289             __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Enable Control                                        */
4290             __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Enable Control                                        */
4291             __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Enable Control                                        */
4292             __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Enable Control                                        */
4293             __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Enable Control                                        */
4294             __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Enable Control                                        */
4295             __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Enable Control                                        */
4296             __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Enable Control                                        */
4297         } CTSUCHAC_b[5];
4298     };
4299 
4300     union
4301     {
4302         __IOM uint8_t CTSUCHTRC[5];    /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register             */
4303 
4304         struct
4305         {
4306             __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Transmit/Receive Control                              */
4307             __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Transmit/Receive Control                              */
4308             __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Transmit/Receive Control                              */
4309             __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Transmit/Receive Control                              */
4310             __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Transmit/Receive Control                              */
4311             __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Transmit/Receive Control                              */
4312             __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Transmit/Receive Control                              */
4313             __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Transmit/Receive Control                              */
4314         } CTSUCHTRC_b[5];
4315     };
4316 
4317     union
4318     {
4319         __IOM uint8_t CTSUDCLKC;         /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register            */
4320 
4321         struct
4322         {
4323             __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should
4324                                           *   be set to 00b.                                                            */
4325             uint8_t                 : 2;
4326             __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should
4327                                           *   be set to 11b.                                                            */
4328             uint8_t : 2;
4329         } CTSUDCLKC_b;
4330     };
4331 
4332     union
4333     {
4334         __IOM uint8_t CTSUST;           /*!< (@ 0x00000011) CTSU Status Register                                       */
4335 
4336         struct
4337         {
4338             __IM uint8_t CTSUSTC   : 3; /*!< [2..0] CTSU Measurement Status Counter                                    */
4339             uint8_t                : 1;
4340             __IM uint8_t  CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag                                     */
4341             __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag                                  */
4342             __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag                               */
4343             __IM uint8_t  CTSUPS   : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag                                */
4344         } CTSUST_b;
4345     };
4346 
4347     union
4348     {
4349         __IOM uint16_t CTSUSSC;        /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion
4350                                         *                  Control Register                                           */
4351 
4352         struct
4353         {
4354             uint16_t                 : 8;
4355             __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting                */
4356             uint16_t                 : 4;
4357         } CTSUSSC_b;
4358     };
4359 
4360     union
4361     {
4362         __IOM uint16_t CTSUSO0;          /*!< (@ 0x00000014) CTSU Sensor Offset Register 0                              */
4363 
4364         struct
4365         {
4366             __IOM uint16_t CTSUSO : 10;  /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is
4367                                           *   CTSUSO ( 0 to 1023 )                                                      */
4368             __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting                                   */
4369         } CTSUSO0_b;
4370     };
4371 
4372     union
4373     {
4374         __IOM uint16_t CTSUSO1;           /*!< (@ 0x00000016) CTSU Sensor Offset Register 1                              */
4375 
4376         struct
4377         {
4378             __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount
4379                                            *   is CTSUSO ( 0 to 255 )                                                    */
4380             __IOM uint16_t CTSUSDPA : 5;  /*!< [12..8] CTSU Base Clock SettingOperating clock divided by (
4381                                            *   CTSUSDPA + 1 ) x 2                                                        */
4382             __IOM uint16_t CTSUICOG : 2;  /*!< [14..13] CTSU ICO Gain Adjustment                                         */
4383             uint16_t                : 1;
4384         } CTSUSO1_b;
4385     };
4386 
4387     union
4388     {
4389         __IM uint16_t CTSUSC;          /*!< (@ 0x00000018) CTSU Sensor Counter                                        */
4390 
4391         struct
4392         {
4393             __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement
4394                                         *   result of the CTSU. These bits indicate FFFFh when an overflow
4395                                         *   occurs.                                                                   */
4396         } CTSUSC_b;
4397     };
4398 
4399     union
4400     {
4401         __IM uint16_t CTSURC;          /*!< (@ 0x0000001A) CTSU Reference Counter                                     */
4402 
4403         struct
4404         {
4405             __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement
4406                                         *   result of the reference ICO.These bits indicate FFFFh when
4407                                         *   an overflow occurs.                                                       */
4408         } CTSURC_b;
4409     };
4410 
4411     union
4412     {
4413         __IM uint16_t CTSUERRS;             /*!< (@ 0x0000001C) CTSU Error Status Register                                 */
4414 
4415         struct
4416         {
4417             __IOM uint16_t CTSUSPMD    : 2; /*!< [1..0] Calibration Mode                                                   */
4418             __IOM uint16_t CTSUTSOD    : 1; /*!< [2..2] TS Pin Fixed Output                                                */
4419             __IOM uint16_t CTSUDRV     : 1; /*!< [3..3] Calibration Setting 1                                              */
4420             uint16_t                   : 2;
4421             __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3                                              */
4422             __IOM uint16_t CTSUTSOC    : 1; /*!< [7..7] Calibration Setting 2                                              */
4423             uint16_t                   : 7;
4424             __IM uint16_t CTSUICOMP    : 1; /*!< [15..15] TSCAP Voltage Error Monitor                                      */
4425         } CTSUERRS_b;
4426     };
4427     __IM uint16_t RESERVED;
4428     __IOM uint8_t CTSUTRMR;                 /*!< (@ 0x00000020) CTSU Reference Current Calibration Register                */
4429     __IM uint8_t  RESERVED1;
4430     __IM uint16_t RESERVED2;
4431 } R_CTSU_Type;                              /*!< Size = 36 (0x24)                                                          */
4432 
4433 /* =========================================================================================================================== */
4434 /* ================                                           R_DAC                                           ================ */
4435 /* =========================================================================================================================== */
4436 
4437 /**
4438  * @brief D/A Converter (R_DAC)
4439  */
4440 
4441 typedef struct                         /*!< (@ 0x4005E000) R_DAC Structure                                            */
4442 {
4443     union
4444     {
4445         __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
4446 
4447         struct
4448         {
4449             __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
4450                                         *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
4451                                         *   = 1, the low-order 4 bits are fixed to 0: left justified
4452                                         *   format.                                                                   */
4453         } DADR_b[2];
4454     };
4455 
4456     union
4457     {
4458         __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
4459 
4460         struct
4461         {
4462             uint8_t             : 5;
4463             __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
4464             __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
4465             __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
4466         } DACR_b;
4467     };
4468 
4469     union
4470     {
4471         __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
4472 
4473         struct
4474         {
4475             uint8_t             : 7;
4476             __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
4477         } DADPR_b;
4478     };
4479 
4480     union
4481     {
4482         __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
4483 
4484         struct
4485         {
4486             uint8_t              : 7;
4487             __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
4488         } DAADSCR_b;
4489     };
4490 
4491     union
4492     {
4493         __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
4494 
4495         struct
4496         {
4497             __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
4498             uint8_t           : 5;
4499         } DAVREFCR_b;
4500     };
4501 
4502     union
4503     {
4504         __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
4505 
4506         struct
4507         {
4508             uint8_t              : 6;
4509             __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
4510             __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
4511         } DAAMPCR_b;
4512     };
4513 
4514     union
4515     {
4516         __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
4517 
4518         struct
4519         {
4520             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
4521             uint8_t              : 7;
4522         } DAPC_b;
4523     };
4524     __IM uint16_t RESERVED[9];
4525 
4526     union
4527     {
4528         __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
4529 
4530         struct
4531         {
4532             uint8_t              : 6;
4533             __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
4534                                         *   to wait for stabilization of the output amplifier of D/A
4535                                         *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
4536                                         *   but the conversion result D/A is not output from channel
4537                                         *   0. When the DAASW0 bit is 0, the stabilization wait time
4538                                         *   stops, and the D/A conversion result of channel 0 is output
4539                                         *   through the output amplifier.                                             */
4540             __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
4541                                         *   to wait for stabilization of the output amplifier of D/A
4542                                         *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
4543                                         *   but the conversion result D/A is not output from channel
4544                                         *   1. When the DAASW1 bit is 0, the stabilization wait time
4545                                         *   stops, and the D/A conversion result of channel 1 is output
4546                                         *   through the output amplifier.                                             */
4547         } DAASWCR_b;
4548     };
4549     __IM uint8_t  RESERVED1;
4550     __IM uint16_t RESERVED2[2129];
4551 
4552     union
4553     {
4554         __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
4555 
4556         struct
4557         {
4558             __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
4559                                          *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
4560                                          *   select unit 0 as the target synchronous unit for the MCU.
4561                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
4562                                          *   conversions, select the target unit in this register in
4563                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
4564                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
4565                                          *   is set to 0.                                                              */
4566             __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
4567                                          *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
4568                                          *   select unit 1 as the target synchronous unit for the MCU.
4569                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
4570                                          *   conversions, select the target unit in this register in
4571                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
4572                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
4573                                          *   is set to 0.                                                              */
4574             uint8_t : 6;
4575         } DAADUSR_b;
4576     };
4577     __IM uint8_t  RESERVED3;
4578     __IM uint16_t RESERVED4;
4579 } R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
4580 
4581 /* =========================================================================================================================== */
4582 /* ================                                          R_DAC8                                           ================ */
4583 /* =========================================================================================================================== */
4584 
4585 /**
4586  * @brief 8-Bit D/A Converter (R_DAC8)
4587  */
4588 
4589 typedef struct                         /*!< (@ 0x4009E000) R_DAC8 Structure                                           */
4590 {
4591     union
4592     {
4593         __IOM uint8_t DACS[2];         /*!< (@ 0x00000000) D/A Conversion Value Setting Register [0..1]               */
4594 
4595         struct
4596         {
4597             __IOM uint8_t DACS : 8;    /*!< [7..0] DACS D/A conversion store data                                     */
4598         } DACS_b[2];
4599     };
4600     __IM uint8_t RESERVED;
4601 
4602     union
4603     {
4604         __IOM uint8_t DAM;             /*!< (@ 0x00000003) D/A Converter Mode Register                                */
4605 
4606         struct
4607         {
4608             __IOM uint8_t DAMD0 : 1;   /*!< [0..0] D/A operation mode select 0                                        */
4609             __IOM uint8_t DAMD1 : 1;   /*!< [1..1] D/A operation mode select 1                                        */
4610             uint8_t             : 2;
4611             __IOM uint8_t DACE0 : 1;   /*!< [4..4] D/A operation enable 0                                             */
4612             __IOM uint8_t DACE1 : 1;   /*!< [5..5] D/A operation enable 1                                             */
4613             uint8_t             : 2;
4614         } DAM_b;
4615     };
4616     __IM uint8_t RESERVED1[2];
4617 
4618     union
4619     {
4620         __IOM uint8_t DACADSCR;        /*!< (@ 0x00000006) D/A A/D Synchronous Start Control Register                 */
4621 
4622         struct
4623         {
4624             __IOM uint8_t DACADST : 1; /*!< [0..0] D/A A/D Synchronous Conversion                                     */
4625             uint8_t               : 7;
4626         } DACADSCR_b;
4627     };
4628 
4629     union
4630     {
4631         __IOM uint8_t DACPC;           /*!< (@ 0x00000007) D/A SW Charge Pump Control Register                        */
4632 
4633         struct
4634         {
4635             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge pump enable                                                 */
4636             uint8_t              : 7;
4637         } DACPC_b;
4638     };
4639 } R_DAC8_Type;                         /*!< Size = 8 (0x8)                                                            */
4640 
4641 /* =========================================================================================================================== */
4642 /* ================                                          R_DEBUG                                          ================ */
4643 /* =========================================================================================================================== */
4644 
4645 /**
4646  * @brief Debug Function (R_DEBUG)
4647  */
4648 
4649 typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
4650 {
4651     union
4652     {
4653         __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
4654 
4655         struct
4656         {
4657             uint32_t                   : 28;
4658             __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
4659             __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
4660             uint32_t                   : 2;
4661         } DBGSTR_b;
4662     };
4663     __IM uint32_t RESERVED[3];
4664 
4665     union
4666     {
4667         __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
4668 
4669         struct
4670         {
4671             __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
4672             __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
4673             uint32_t                     : 12;
4674             __IOM uint32_t DBGSTOP_TIM   : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt                            */
4675             __IOM uint32_t DBGSTOP_SIR   : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt              */
4676             __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
4677             __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
4678             __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
4679             uint32_t                     : 5;
4680             __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
4681             __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
4682             uint32_t                     : 5;
4683             __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
4684         } DBGSTOPCR_b;
4685     };
4686     __IM uint32_t RESERVED1[123];
4687 
4688     union
4689     {
4690         __IOM uint32_t FSBLSTAT;       /*!< (@ 0x00000200) First Stage Boot Loader Status Register                    */
4691 
4692         struct
4693         {
4694             __IOM uint32_t CS     : 1; /*!< [0..0] FSBL completion status.                                            */
4695             __IOM uint32_t RS     : 1; /*!< [1..1] FSBL result status.                                                */
4696             uint32_t              : 6;
4697             __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution            */
4698             uint32_t              : 21;
4699         } FSBLSTAT_b;
4700     };
4701 } R_DEBUG_Type;                        /*!< Size = 516 (0x204)                                                        */
4702 
4703 /* =========================================================================================================================== */
4704 /* ================                                           R_DOC                                           ================ */
4705 /* =========================================================================================================================== */
4706 
4707 /**
4708  * @brief Data Operation Circuit (R_DOC)
4709  */
4710 
4711 typedef struct                         /*!< (@ 0x40054100) R_DOC Structure                                            */
4712 {
4713     union
4714     {
4715         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
4716 
4717         struct
4718         {
4719             __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
4720             __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
4721             uint8_t               : 2;
4722             __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
4723             __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
4724             uint8_t               : 1;
4725         } DOCR_b;
4726     };
4727     __IM uint8_t RESERVED;
4728 
4729     union
4730     {
4731         __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
4732 
4733         struct
4734         {
4735             __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
4736                                         *   use in the operations are stored.                                         */
4737         } DODIR_b;
4738     };
4739 
4740     union
4741     {
4742         __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
4743 
4744         struct
4745         {
4746             __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
4747                                         *   in data comparison mode. This register also stores the
4748                                         *   results of operations in data addition and data subtraction
4749                                         *   modes.                                                                    */
4750         } DODSR_b;
4751     };
4752 } R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
4753 
4754 /* =========================================================================================================================== */
4755 /* ================                                           R_DTC                                           ================ */
4756 /* =========================================================================================================================== */
4757 
4758 /**
4759  * @brief Data Transfer Controller (R_DTC)
4760  */
4761 
4762 typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
4763 {
4764     union
4765     {
4766         __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
4767 
4768         struct
4769         {
4770             uint8_t           : 4;
4771             __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
4772             uint8_t           : 3;
4773         } DTCCR_b;
4774     };
4775     __IM uint8_t  RESERVED;
4776     __IM uint16_t RESERVED1;
4777 
4778     union
4779     {
4780         __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
4781 
4782         struct
4783         {
4784             __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
4785                                          *   in the lower-order 10 bits. These bits are fixed to 0.                    */
4786         } DTCVBR_b;
4787     };
4788     __IM uint32_t RESERVED2;
4789 
4790     union
4791     {
4792         __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
4793 
4794         struct
4795         {
4796             __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
4797             uint8_t             : 7;
4798         } DTCST_b;
4799     };
4800     __IM uint8_t RESERVED3;
4801 
4802     union
4803     {
4804         __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
4805 
4806         struct
4807         {
4808             __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
4809                                         *   the vector number for the activating source when DTC transfer
4810                                         *   is in progress.The value is only valid if DTC transfer
4811                                         *   is in progress (the value of the ACT flag is 1)                           */
4812             uint16_t          : 7;
4813             __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
4814         } DTCSTS_b;
4815     };
4816 
4817     union
4818     {
4819         __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
4820 
4821         struct
4822         {
4823             uint8_t            : 4;
4824             __IOM uint8_t RRSS : 1;    /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure               */
4825             uint8_t            : 3;
4826         } DTCCR_SEC_b;
4827     };
4828     __IM uint8_t   RESERVED4;
4829     __IM uint16_t  RESERVED5;
4830     __IOM uint32_t DTCVBR_SEC;         /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
4831     __IM uint32_t  RESERVED6[2];
4832 
4833     union
4834     {
4835         __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
4836 
4837         struct
4838         {
4839             __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
4840             __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
4841             uint32_t              : 7;
4842             __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
4843             uint32_t              : 15;
4844         } DTEVR_b;
4845     };
4846 } R_DTC_Type;                          /*!< Size = 36 (0x24)                                                          */
4847 
4848 /* =========================================================================================================================== */
4849 /* ================                                           R_ELC                                           ================ */
4850 /* =========================================================================================================================== */
4851 
4852 /**
4853  * @brief Event Link Controller (R_ELC)
4854  */
4855 
4856 typedef struct                         /*!< (@ 0x40041000) R_ELC Structure                                            */
4857 {
4858     union
4859     {
4860         __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
4861 
4862         struct
4863         {
4864             uint8_t             : 7;
4865             __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
4866         } ELCR_b;
4867     };
4868     __IM uint8_t            RESERVED;
4869     __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
4870     __IM uint16_t           RESERVED1[5];
4871     __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
4872     __IM uint16_t           RESERVED2[4];
4873 
4874     union
4875     {
4876         __IOM uint16_t ELCSARA;         /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
4877                                          *                  A                                                          */
4878 
4879         struct
4880         {
4881             __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
4882             __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
4883                                          *   Attribution                                                               */
4884             __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
4885                                          *   Attribution                                                               */
4886             uint16_t : 13;
4887         } ELCSARA_b;
4888     };
4889     __IM uint16_t RESERVED3;
4890 
4891     union
4892     {
4893         __IOM uint16_t ELCSARB;        /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
4894                                         *                  B                                                          */
4895 
4896         struct
4897         {
4898             __IOM uint16_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
4899             __IOM uint16_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
4900             __IOM uint16_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
4901             __IOM uint16_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
4902             __IOM uint16_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
4903             __IOM uint16_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
4904             __IOM uint16_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
4905             __IOM uint16_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
4906             __IOM uint16_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution                  */
4907             __IOM uint16_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution                  */
4908             __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution               */
4909             __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution               */
4910             __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
4911             __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
4912             __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
4913             __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
4914         } ELCSARB_b;
4915     };
4916     __IM uint16_t RESERVED4;
4917 
4918     union
4919     {
4920         __IOM uint16_t ELCSARC;        /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
4921                                         *                  C                                                          */
4922 
4923         struct
4924         {
4925             __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution                 */
4926             __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution                 */
4927             __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution                 */
4928             uint16_t              : 13;
4929         } ELCSARC_b;
4930     };
4931 } R_ELC_Type;                          /*!< Size = 126 (0x7e)                                                         */
4932 
4933 /* =========================================================================================================================== */
4934 /* ================                                         R_FACI_LP                                         ================ */
4935 /* =========================================================================================================================== */
4936 
4937 /**
4938  * @brief Flash Application Command Interface (R_FACI_LP)
4939  */
4940 
4941 typedef struct                         /*!< (@ 0x407EC000) R_FACI_LP Structure                                        */
4942 {
4943     __IM uint32_t RESERVED[36];
4944     __IOM uint8_t DFLCTL;              /*!< (@ 0x00000090) Flash P/E Mode Control Register                            */
4945     __IM uint8_t  RESERVED1;
4946     __IM uint16_t RESERVED2;
4947     __IM uint32_t RESERVED3[27];
4948 
4949     union
4950     {
4951         __IOM uint8_t FPMCR;           /*!< (@ 0x00000100) Flash P/E Mode Control Register                            */
4952 
4953         struct
4954         {
4955             uint8_t            : 1;
4956             __IOM uint8_t FMS0 : 1;    /*!< [1..1] Flash Operating Mode Select 0FMS2,1,0: 000: Read mode
4957                                         *   011: Discharge mode 1 111: Discharge mode 2 101: Code Flash
4958                                         *   P/E mode 010: Data flash P/E mode Others: Setting prohibited.             */
4959             uint8_t             : 1;
4960             __IOM uint8_t RPDIS : 1;   /*!< [3..3] Code Flash P/E Disable                                             */
4961             __IOM uint8_t FMS1  : 1;   /*!< [4..4] The bit to make data flash a programming modeRefer to
4962                                         *   the description of the FMS0 bit.                                          */
4963             uint8_t            : 1;
4964             __IOM uint8_t VLPE : 1;    /*!< [6..6] Low-Voltage P/E Mode Enable                                        */
4965             __IOM uint8_t FMS2 : 1;    /*!< [7..7] Flash Operating Mode Select 2.Refer to the description
4966                                         *   of the FMS0 bit.                                                          */
4967         } FPMCR_b;
4968     };
4969     __IM uint8_t  RESERVED4;
4970     __IM uint16_t RESERVED5;
4971 
4972     union
4973     {
4974         __IOM uint8_t FASR;            /*!< (@ 0x00000104) Flash Area Select Register                                 */
4975 
4976         struct
4977         {
4978             __IOM uint8_t EXS : 1;     /*!< [0..0] Extra area select                                                  */
4979             uint8_t           : 7;
4980         } FASR_b;
4981     };
4982     __IM uint8_t  RESERVED6;
4983     __IM uint16_t RESERVED7;
4984 
4985     union
4986     {
4987         __IOM uint16_t FSARL;             /*!< (@ 0x00000108) Flash Processing Start Address Register L                  */
4988 
4989         struct
4990         {
4991             __IOM uint16_t FSAR15_0 : 16; /*!< [15..0] Start address                                                     */
4992         } FSARL_b;
4993     };
4994     __IM uint16_t RESERVED8;
4995     __IM uint32_t RESERVED9;
4996 
4997     union
4998     {
4999         __IOM uint16_t FSARH;             /*!< (@ 0x00000110) Flash Processing Start Address Register H                  */
5000 
5001         struct
5002         {
5003             __IOM uint16_t FSAR20_16 : 5; /*!< [4..0] Start address                                                      */
5004             uint16_t                 : 4;
5005             __IOM uint16_t FSAR31_25 : 7; /*!< [15..9] Start address                                                     */
5006         } FSARH_b;
5007     };
5008     __IM uint16_t RESERVED10;
5009 
5010     union
5011     {
5012         __IOM uint8_t FCR;             /*!< (@ 0x00000114) Flash Control Register                                     */
5013 
5014         struct
5015         {
5016             __IOM uint8_t CMD  : 4;    /*!< [3..0] Software Command Setting                                           */
5017             __IOM uint8_t DRC  : 1;    /*!< [4..4] Data Read Completion                                               */
5018             uint8_t            : 1;
5019             __IOM uint8_t STOP : 1;    /*!< [6..6] Forced Processing Stop                                             */
5020             __IOM uint8_t OPST : 1;    /*!< [7..7] Processing Start                                                   */
5021         } FCR_b;
5022     };
5023     __IM uint8_t  RESERVED11;
5024     __IM uint16_t RESERVED12;
5025 
5026     union
5027     {
5028         __IOM uint16_t FEARL;             /*!< (@ 0x00000118) Flash Processing End Address Register L                    */
5029 
5030         struct
5031         {
5032             __IOM uint16_t FEAR15_0 : 16; /*!< [15..0] End address                                                       */
5033         } FEARL_b;
5034     };
5035     __IM uint16_t RESERVED13;
5036     __IM uint32_t RESERVED14;
5037 
5038     union
5039     {
5040         __IOM uint32_t FEARH;             /*!< (@ 0x00000120) Flash Processing End Address Register H                    */
5041 
5042         struct
5043         {
5044             __IOM uint32_t FEAR20_16 : 5; /*!< [4..0] End address                                                        */
5045             uint32_t                 : 4;
5046             __IOM uint32_t FEAR31_25 : 7; /*!< [15..9] End address                                                       */
5047             uint32_t                 : 16;
5048         } FEARH_b;
5049     };
5050 
5051     union
5052     {
5053         __IOM uint32_t FRESETR;        /*!< (@ 0x00000124) Flash Reset Register                                       */
5054 
5055         struct
5056         {
5057             __IOM uint32_t FRESET : 1; /*!< [0..0] Software Reset of the registers                                    */
5058             uint32_t              : 31;
5059         } FRESETR_b;
5060     };
5061 
5062     union
5063     {
5064         __IM uint32_t FSTATR00;         /*!< (@ 0x00000128) Flash Status Register00                                    */
5065 
5066         struct
5067         {
5068             __IM uint32_t ERERR0   : 1; /*!< [0..0] Erase Error Flag0                                                  */
5069             __IM uint32_t PRGERR0  : 1; /*!< [1..1] Program Error Flag0                                                */
5070             __IM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
5071             __IM uint32_t BCERR0   : 1; /*!< [3..3] Blank Check Error Flag0                                            */
5072             __IM uint32_t ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
5073             __IM uint32_t EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
5074             uint32_t               : 26;
5075         } FSTATR00_b;
5076     };
5077 
5078     union
5079     {
5080         __IM uint32_t FSTATR1;         /*!< (@ 0x0000012C) Flash Status Register1                                     */
5081 
5082         struct
5083         {
5084             uint32_t            : 1;
5085             __IM uint32_t DRRDY : 1;   /*!< [1..1] Data read request                                                  */
5086             uint32_t            : 4;
5087             __IM uint32_t FRDY  : 1;   /*!< [6..6] End status signal of a sequencer                                   */
5088             __IM uint32_t EXRDY : 1;   /*!< [7..7] End status signal of a Extra programming sequencer                 */
5089             uint32_t            : 24;
5090         } FSTATR1_b;
5091     };
5092 
5093     union
5094     {
5095         __IOM uint32_t FWBL0;          /*!< (@ 0x00000130) Flash Write Buffer Register L0                             */
5096 
5097         struct
5098         {
5099             __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
5100             uint32_t             : 16;
5101         } FWBL0_b;
5102     };
5103     __IM uint32_t RESERVED15;
5104 
5105     union
5106     {
5107         __IOM uint32_t FWBH0;          /*!< (@ 0x00000138) Flash Write Buffer Register H0                             */
5108 
5109         struct
5110         {
5111             __IOM uint32_t WDATA : 16; /*!< [15..0] Program data of the program command                               */
5112             uint32_t             : 16;
5113         } FWBH0_b;
5114     };
5115 
5116     union
5117     {
5118         __IM uint32_t FSTATR01;        /*!< (@ 0x0000013C) Flash Status Register01                                    */
5119 
5120         struct
5121         {
5122             __IM uint32_t ERERR1  : 1; /*!< [0..0] Erase Error Flag1                                                  */
5123             __IM uint32_t PRGERR1 : 1; /*!< [1..1] Program Error Flag1                                                */
5124             uint32_t              : 1;
5125             __IM uint32_t BCERR1  : 1; /*!< [3..3] Blank Check Error Flag1                                            */
5126             uint32_t              : 28;
5127         } FSTATR01_b;
5128     };
5129 
5130     union
5131     {
5132         __IOM uint32_t FWBL1;               /*!< (@ 0x00000140) Flash Write Buffer Register L1                             */
5133 
5134         struct
5135         {
5136             __IOM uint32_t WDATA47_32 : 16; /*!< [15..0] Program data of the program command                               */
5137             uint32_t                  : 16;
5138         } FWBL1_b;
5139     };
5140 
5141     union
5142     {
5143         __IOM uint32_t FWBH1;               /*!< (@ 0x00000144) Flash Write Buffer Register H1                             */
5144 
5145         struct
5146         {
5147             __IOM uint32_t WDATA63_48 : 16; /*!< [15..0] Program data of the program command                               */
5148             uint32_t                  : 16;
5149         } FWBH1_b;
5150     };
5151 
5152     union
5153     {
5154         __IM uint32_t FRBL1;               /*!< (@ 0x00000148) Flash Read Buffer Register L1                              */
5155 
5156         struct
5157         {
5158             __IM uint32_t RDATA47_32 : 16; /*!< [15..0] Read data of the consecutive read command                         */
5159             uint32_t                 : 16;
5160         } FRBL1_b;
5161     };
5162 
5163     union
5164     {
5165         __IM uint32_t FRBH1;               /*!< (@ 0x0000014C) Flash Read Buffer Register H1                              */
5166 
5167         struct
5168         {
5169             __IM uint32_t RDATA63_48 : 16; /*!< [15..0] Read data of the consecutive read command                         */
5170             uint32_t                 : 16;
5171         } FRBH1_b;
5172     };
5173     __IM uint32_t RESERVED16[12];
5174 
5175     union
5176     {
5177         __OM uint32_t FPR;             /*!< (@ 0x00000180) Protection Unlock Register                                 */
5178 
5179         struct
5180         {
5181             __OM uint32_t FPR : 8;     /*!< [7..0] Protection Unlock Register                                         */
5182             uint32_t          : 24;
5183         } FPR_b;
5184     };
5185 
5186     union
5187     {
5188         __IM uint32_t FPSR;            /*!< (@ 0x00000184) Protection Unlock Status Register                          */
5189 
5190         struct
5191         {
5192             __IM uint32_t PERR : 1;    /*!< [0..0] Protect Error Flag                                                 */
5193             uint32_t           : 31;
5194         } FPSR_b;
5195     };
5196 
5197     union
5198     {
5199         __IM uint32_t FRBL0;           /*!< (@ 0x00000188) Flash Read Buffer Register L0                              */
5200 
5201         struct
5202         {
5203             __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
5204             uint32_t            : 16;
5205         } FRBL0_b;
5206     };
5207     __IM uint32_t RESERVED17;
5208 
5209     union
5210     {
5211         __IM uint32_t FRBH0;           /*!< (@ 0x00000190) Flash Read Buffer Register H0                              */
5212 
5213         struct
5214         {
5215             __IM uint32_t RDATA : 16;  /*!< [15..0] Read data of the consecutive read command                         */
5216             uint32_t            : 16;
5217         } FRBH0_b;
5218     };
5219     __IM uint32_t RESERVED18[11];
5220 
5221     union
5222     {
5223         __IM uint32_t FSCMR;           /*!< (@ 0x000001C0) Flash Start-Up Setting Monitor Register                    */
5224 
5225         struct
5226         {
5227             uint32_t            : 8;
5228             __IM uint32_t SASMF : 1;   /*!< [8..8] Start-up Area Setting Monitor Flag                                 */
5229             uint32_t            : 5;
5230             __IM uint32_t FSPR  : 1;   /*!< [14..14] Access Window Protection Flag                                    */
5231             uint32_t            : 17;
5232         } FSCMR_b;
5233     };
5234     __IM uint32_t RESERVED19;
5235 
5236     union
5237     {
5238         __IM uint32_t FAWSMR;          /*!< (@ 0x000001C8) Flash Access Window Start Address Monitor Register         */
5239 
5240         struct
5241         {
5242             __IM uint32_t FAWS : 12;   /*!< [11..0] Flash Access Window Start Address                                 */
5243             uint32_t           : 20;
5244         } FAWSMR_b;
5245     };
5246     __IM uint32_t RESERVED20;
5247 
5248     union
5249     {
5250         __IM uint32_t FAWEMR;          /*!< (@ 0x000001D0) Flash Access Window End Address Monitor Register           */
5251 
5252         struct
5253         {
5254             __IM uint32_t FAWE : 12;   /*!< [11..0] Flash Access Window End Address                                   */
5255             uint32_t           : 20;
5256         } FAWEMR_b;
5257     };
5258     __IM uint32_t RESERVED21;
5259 
5260     union
5261     {
5262         __IOM uint32_t FISR;           /*!< (@ 0x000001D8) Flash Initial Setting Register                             */
5263 
5264         struct
5265         {
5266             __IOM uint32_t PCKA : 6;   /*!< [5..0] Peripheral Clock Notification                                      */
5267             __IOM uint32_t SAS  : 2;   /*!< [7..6] Temporary boot swap mode                                           */
5268             uint32_t            : 24;
5269         } FISR_b;
5270     };
5271 
5272     union
5273     {
5274         __IOM uint32_t FEXCR;          /*!< (@ 0x000001DC) Flash Extra Area Control Register                          */
5275 
5276         struct
5277         {
5278             __IOM uint32_t CMD  : 3;   /*!< [2..0] Processing Start)                                                  */
5279             uint32_t            : 4;
5280             __IOM uint32_t OPST : 1;   /*!< [7..7] Software Command Setting                                           */
5281             uint32_t            : 24;
5282         } FEXCR_b;
5283     };
5284 
5285     union
5286     {
5287         __IM uint32_t FEAML;           /*!< (@ 0x000001E0) Flash Error Address Monitor Register L                     */
5288 
5289         struct
5290         {
5291             __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
5292             uint32_t           : 16;
5293         } FEAML_b;
5294     };
5295     __IM uint32_t RESERVED22;
5296 
5297     union
5298     {
5299         __IM uint32_t FEAMH;           /*!< (@ 0x000001E8) Flash Error Address Monitor Register H                     */
5300 
5301         struct
5302         {
5303             __IM uint32_t FEAM : 16;   /*!< [15..0] Flash Error Address Monitor Register                              */
5304             uint32_t           : 16;
5305         } FEAMH_b;
5306     };
5307     __IM uint32_t RESERVED23;
5308 
5309     union
5310     {
5311         __IM uint32_t FSTATR2;           /*!< (@ 0x000001F0) Flash Status Register2                                     */
5312 
5313         struct
5314         {
5315             __IM uint32_t  ERERR    : 1; /*!< [0..0] Erase Error Flag                                                   */
5316             __IM uint32_t  PRGERR1  : 1; /*!< [1..1] Program Error Flag                                                 */
5317             __IOM uint32_t PRGERR01 : 1; /*!< [2..2] Program Error Flag 01                                              */
5318             __IM uint32_t  BCERR    : 1; /*!< [3..3] Blank Check Error Flag                                             */
5319             __IM uint32_t  ILGLERR  : 1; /*!< [4..4] Illegal Command Error Flag                                         */
5320             __IM uint32_t  EILGLERR : 1; /*!< [5..5] Extra Area Illegal Command Error Flag                              */
5321             uint32_t                : 26;
5322         } FSTATR2_b;
5323     };
5324     __IM uint32_t RESERVED24[3];
5325 
5326     union
5327     {
5328         __IOM uint8_t HIOTRM;          /*!< (@ 0x00000200) High-speed On-chip Oscillator Trimming Register            */
5329 
5330         struct
5331         {
5332             __IOM uint8_t HIOTRM : 6;  /*!< [5..0] HOCO User Trimming                                                 */
5333             uint8_t              : 2;
5334         } HIOTRM_b;
5335     };
5336     __IM uint8_t  RESERVED25;
5337     __IM uint16_t RESERVED26;
5338     __IM uint32_t RESERVED27;
5339     __IM uint16_t RESERVED28;
5340 
5341     union
5342     {
5343         __IOM uint8_t FLMODE;          /*!< (@ 0x0000020A) Flash Operating Mode Control Register                      */
5344 
5345         struct
5346         {
5347             uint8_t            : 6;
5348             __IOM uint8_t MODE : 2;    /*!< [7..6] Operating Mode Select                                              */
5349         } FLMODE_b;
5350     };
5351 
5352     union
5353     {
5354         __IOM uint8_t FLMWRP;          /*!< (@ 0x0000020B) Flash Operating Mode Protect Register                      */
5355 
5356         struct
5357         {
5358             __IOM uint8_t FLMWEN : 1;  /*!< [0..0] Control of Flash Operation Mode Select Register                    */
5359             uint8_t              : 7;
5360         } FLMWRP_b;
5361     };
5362     __IM uint32_t RESERVED29[89];
5363 
5364     union
5365     {
5366         __IOM uint32_t FCTLFR;          /*!< (@ 0x00000370) Flash Control Flag Register                                */
5367 
5368         struct
5369         {
5370             __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting                                                  */
5371             uint32_t               : 29;
5372         } FCTLFR_b;
5373     };
5374     __IM uint32_t  RESERVED30[3855];
5375     __IOM uint16_t FENTRYR_MF4;        /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4                      */
5376     __IOM uint16_t FENTRYR;            /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register                              */
5377     __IM uint32_t  RESERVED31[3];
5378     __IOM uint8_t  FLWAITR;            /*!< (@ 0x00003FC0) Flash Wait Cycle Register                                  */
5379     __IM uint8_t   RESERVED32;
5380     __IM uint16_t  RESERVED33;
5381 
5382     union
5383     {
5384         __IOM uint8_t FLDWAITR;         /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash          */
5385 
5386         struct
5387         {
5388             __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash                            */
5389             uint8_t                : 7;
5390         } FLDWAITR_b;
5391     };
5392     __IM uint8_t  RESERVED34;
5393     __IM uint16_t RESERVED35;
5394     __IOM uint8_t PFBER;               /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register                            */
5395     __IM uint8_t  RESERVED36;
5396     __IM uint16_t RESERVED37;
5397     __IM uint32_t RESERVED38;
5398 
5399     union
5400     {
5401         __IOM uint16_t FBKPGCR;        /*!< (@ 0x00003FD0) Flash Bank Program Control Register                        */
5402 
5403         struct
5404         {
5405             __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable                                    */
5406             uint16_t              : 7;
5407             __OM uint16_t FEKEY   : 8; /*!< [15..8] Key Code                                                          */
5408         } FBKPGCR_b;
5409     };
5410     __IM uint16_t RESERVED39;
5411 
5412     union
5413     {
5414         __IOM uint16_t FBKSWCR;          /*!< (@ 0x00003FD4) Flash Bank Swap Control Register                           */
5415 
5416         struct
5417         {
5418             __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable                                            */
5419             uint16_t                : 7;
5420             __OM uint16_t FEKEY     : 8; /*!< [15..8] Key Code                                                          */
5421         } FBKSWCR_b;
5422     };
5423     __IM uint16_t RESERVED40;
5424 } R_FACI_LP_Type;                        /*!< Size = 16344 (0x3fd8)                                                     */
5425 
5426 /* =========================================================================================================================== */
5427 /* ================                                         R_FCACHE                                          ================ */
5428 /* =========================================================================================================================== */
5429 
5430 /**
5431  * @brief Flash Memory Cache (R_FCACHE)
5432  */
5433 
5434 typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
5435 {
5436     __IM uint16_t RESERVED[128];
5437 
5438     union
5439     {
5440         __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */
5441 
5442         struct
5443         {
5444             __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
5445             uint16_t                : 15;
5446         } FCACHEE_b;
5447     };
5448     __IM uint16_t RESERVED1;
5449 
5450     union
5451     {
5452         __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */
5453 
5454         struct
5455         {
5456             __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
5457             uint16_t                : 15;
5458         } FCACHEIV_b;
5459     };
5460     __IM uint16_t RESERVED2[11];
5461 
5462     union
5463     {
5464         __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */
5465 
5466         struct
5467         {
5468             __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
5469             uint8_t            : 5;
5470         } FLWT_b;
5471     };
5472     __IM uint8_t  RESERVED3;
5473     __IM uint16_t RESERVED4[17];
5474 
5475     union
5476     {
5477         __IOM uint16_t FSAR;             /*!< (@ 0x00000140) Flash Security Attribution Register                        */
5478 
5479         struct
5480         {
5481             __IOM uint16_t FLWTSA   : 1; /*!< [0..0] FLWT Security Attribution                                          */
5482             uint16_t                : 7;
5483             __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
5484             uint16_t                : 7;
5485         } FSAR_b;
5486     };
5487 } R_FCACHE_Type;                         /*!< Size = 322 (0x142)                                                        */
5488 
5489 /* =========================================================================================================================== */
5490 /* ================                                          R_GPT0                                           ================ */
5491 /* =========================================================================================================================== */
5492 
5493 /**
5494  * @brief General PWM Timer (R_GPT0)
5495  */
5496 
5497 typedef struct                         /*!< (@ 0x40078000) R_GPT0 Structure                                           */
5498 {
5499     union
5500     {
5501         __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
5502 
5503         struct
5504         {
5505             __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
5506             __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
5507             __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
5508             __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
5509             __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
5510             uint32_t             : 3;
5511             __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
5512             uint32_t             : 16;
5513         } GTWP_b;
5514     };
5515 
5516     union
5517     {
5518         __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
5519 
5520         struct
5521         {
5522             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
5523                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5524                                          *   means counter running.                                                    */
5525             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
5526                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5527                                          *   means counter running.                                                    */
5528             __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
5529                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5530                                          *   means counter running.                                                    */
5531             __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
5532                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5533                                          *   means counter running.                                                    */
5534             __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
5535                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5536                                          *   means counter running.                                                    */
5537             __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
5538                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5539                                          *   means counter running.                                                    */
5540             __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
5541                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5542                                          *   means counter running.                                                    */
5543             __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
5544                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5545                                          *   means counter running.                                                    */
5546             __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
5547                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5548                                          *   means counter running.                                                    */
5549             __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
5550                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5551                                          *   means counter running.                                                    */
5552             __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
5553                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5554                                          *   means counter running.                                                    */
5555             __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
5556                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5557                                          *   means counter running.                                                    */
5558             __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
5559                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5560                                          *   means counter running.                                                    */
5561             __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
5562                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5563                                          *   means counter running.                                                    */
5564             __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
5565                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5566                                          *   means counter running.                                                    */
5567             __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
5568                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5569                                          *   means counter running.                                                    */
5570             __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
5571                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5572                                          *   means counter running.                                                    */
5573             __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
5574                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5575                                          *   means counter running.                                                    */
5576             __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
5577                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5578                                          *   means counter running.                                                    */
5579             __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
5580                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5581                                          *   means counter running.                                                    */
5582             __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
5583                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5584                                          *   means counter running.                                                    */
5585             __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
5586                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5587                                          *   means counter running.                                                    */
5588             __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
5589                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5590                                          *   means counter running.                                                    */
5591             __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
5592                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5593                                          *   means counter running.                                                    */
5594             __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
5595                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5596                                          *   means counter running.                                                    */
5597             __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
5598                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5599                                          *   means counter running.                                                    */
5600             __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
5601                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5602                                          *   means counter running.                                                    */
5603             __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
5604                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5605                                          *   means counter running.                                                    */
5606             __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
5607                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5608                                          *   means counter running.                                                    */
5609             __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
5610                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5611                                          *   means counter running.                                                    */
5612             __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
5613                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5614                                          *   means counter running.                                                    */
5615             __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
5616                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
5617                                          *   means counter running.                                                    */
5618         } GTSTR_b;
5619     };
5620 
5621     union
5622     {
5623         __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
5624 
5625         struct
5626         {
5627             __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
5628                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5629                                          *   1 means counter stop.                                                     */
5630             __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
5631                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5632                                          *   1 means counter stop.                                                     */
5633             __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
5634                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5635                                          *   1 means counter stop.                                                     */
5636             __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
5637                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5638                                          *   1 means counter stop.                                                     */
5639             __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
5640                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5641                                          *   1 means counter stop.                                                     */
5642             __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
5643                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5644                                          *   1 means counter stop.                                                     */
5645             __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
5646                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5647                                          *   1 means counter stop.                                                     */
5648             __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
5649                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5650                                          *   1 means counter stop.                                                     */
5651             __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
5652                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5653                                          *   1 means counter stop.                                                     */
5654             __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
5655                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5656                                          *   1 means counter stop.                                                     */
5657             __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
5658                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5659                                          *   1 means counter stop.                                                     */
5660             __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
5661                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5662                                          *   1 means counter stop.                                                     */
5663             __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
5664                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5665                                          *   1 means counter stop.                                                     */
5666             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
5667                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5668                                          *   1 means counter stop.                                                     */
5669             __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
5670                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5671                                          *   1 means counter stop.                                                     */
5672             __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
5673                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5674                                          *   1 means counter stop.                                                     */
5675             __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
5676                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5677                                          *   1 means counter stop.                                                     */
5678             __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
5679                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5680                                          *   1 means counter stop.                                                     */
5681             __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
5682                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5683                                          *   1 means counter stop.                                                     */
5684             __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
5685                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5686                                          *   1 means counter stop.                                                     */
5687             __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
5688                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5689                                          *   1 means counter stop.                                                     */
5690             __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
5691                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5692                                          *   1 means counter stop.                                                     */
5693             __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
5694                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5695                                          *   1 means counter stop.                                                     */
5696             __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
5697                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5698                                          *   1 means counter stop.                                                     */
5699             __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
5700                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5701                                          *   1 means counter stop.                                                     */
5702             __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
5703                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5704                                          *   1 means counter stop.                                                     */
5705             __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
5706                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5707                                          *   1 means counter stop.                                                     */
5708             __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
5709                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5710                                          *   1 means counter stop.                                                     */
5711             __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
5712                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5713                                          *   1 means counter stop.                                                     */
5714             __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
5715                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5716                                          *   1 means counter stop.                                                     */
5717             __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
5718                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5719                                          *   1 means counter stop.                                                     */
5720             __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
5721                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
5722                                          *   1 means counter stop.                                                     */
5723         } GTSTP_b;
5724     };
5725 
5726     union
5727     {
5728         __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
5729 
5730         struct
5731         {
5732             __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
5733             __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
5734             __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
5735             __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
5736             __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
5737             __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
5738             __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
5739             __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
5740             __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
5741             __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
5742             __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
5743             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
5744             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
5745             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
5746             __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
5747             __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
5748             __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
5749             __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
5750             __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
5751             __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
5752             __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
5753             __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
5754             __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
5755             __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
5756             __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
5757             __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
5758             __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
5759             __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
5760             __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
5761             __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
5762             __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
5763             __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
5764         } GTCLR_b;
5765     };
5766 
5767     union
5768     {
5769         __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
5770 
5771         struct
5772         {
5773             __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
5774             __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
5775             __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
5776             __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
5777             __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
5778             __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
5779             __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
5780             __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
5781             __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
5782                                           *   Counter Start Enable                                                      */
5783             __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
5784                                           *   Counter Start Enable                                                      */
5785             __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
5786                                           *   Counter Start Enable                                                      */
5787             __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
5788                                           *   Counter Start Enable                                                      */
5789             __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
5790                                           *   Counter Start Enable                                                      */
5791             __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
5792                                           *   Counter Start Enable                                                      */
5793             __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
5794                                           *   Counter Start Enable                                                      */
5795             __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
5796                                           *   Counter Start Enable                                                      */
5797             __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
5798             __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
5799             __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
5800             __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
5801             __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
5802             __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
5803             __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
5804             __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
5805             uint32_t              : 7;
5806             __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
5807         } GTSSR_b;
5808     };
5809 
5810     union
5811     {
5812         __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
5813 
5814         struct
5815         {
5816             __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
5817             __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
5818             __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
5819             __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
5820             __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
5821             __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
5822             __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
5823             __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
5824             __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
5825                                           *   Counter Stop Enable                                                       */
5826             __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
5827                                           *   Counter Stop Enable                                                       */
5828             __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
5829                                           *   Counter Stop Enable                                                       */
5830             __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
5831                                           *   Counter Stop Enable                                                       */
5832             __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
5833                                           *   Counter Stop Enable                                                       */
5834             __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
5835                                           *   Counter Stop Enable                                                       */
5836             __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
5837                                           *   Counter Stop Enable                                                       */
5838             __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
5839                                           *   Counter Stop Enable                                                       */
5840             __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
5841             __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
5842             __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
5843             __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
5844             __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
5845             __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
5846             __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
5847             __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
5848             uint32_t              : 7;
5849             __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
5850         } GTPSR_b;
5851     };
5852 
5853     union
5854     {
5855         __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
5856 
5857         struct
5858         {
5859             __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
5860             __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
5861             __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
5862             __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
5863             __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
5864             __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
5865             __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
5866             __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
5867             __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
5868                                           *   Counter Clear Enable                                                      */
5869             __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
5870                                           *   Counter Clear Enable                                                      */
5871             __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
5872                                           *   Counter Clear Enable                                                      */
5873             __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
5874                                           *   Counter Clear Enable                                                      */
5875             __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
5876                                           *   Counter Clear Enable                                                      */
5877             __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
5878                                           *   Counter Clear Enable                                                      */
5879             __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
5880                                           *   Counter Clear Enable                                                      */
5881             __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
5882                                           *   Counter Clear Enable                                                      */
5883             __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
5884             __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
5885             __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
5886             __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
5887             __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
5888             __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
5889             __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
5890             __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
5891             __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
5892                                           *   Source Counter Clear Enable.                                              */
5893             __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
5894                                           *   Enable (This bit is only available in GPT324 to GPT329.
5895                                           *   In GPT320 to GPT323, this bit is read as 0. The write value
5896                                           *   should be 0.)                                                             */
5897             uint32_t            : 3;
5898             __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
5899         } GTCSR_b;
5900     };
5901 
5902     union
5903     {
5904         __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
5905 
5906         struct
5907         {
5908             __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
5909             __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
5910             __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
5911             __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
5912             __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
5913             __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
5914             __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
5915             __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
5916             __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
5917                                           *   Counter Count Up Enable                                                   */
5918             __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
5919                                           *   Counter Count Up Enable                                                   */
5920             __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
5921                                           *   Counter Count Up Enable                                                   */
5922             __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
5923                                           *   Counter Count Up Enable                                                   */
5924             __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
5925                                           *   Counter Count Up Enable                                                   */
5926             __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
5927                                           *   Counter Count Up Enable                                                   */
5928             __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
5929                                           *   Counter Count Up Enable                                                   */
5930             __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
5931                                           *   Counter Count Up Enable                                                   */
5932             __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
5933             __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
5934             __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
5935             __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
5936             __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
5937             __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
5938             __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
5939             __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
5940             __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
5941             uint32_t              : 4;
5942         } GTUPSR_b;
5943     };
5944 
5945     union
5946     {
5947         __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
5948 
5949         struct
5950         {
5951             __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
5952             __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
5953             __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
5954             __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
5955             __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
5956             __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
5957             __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
5958             __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
5959             __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
5960                                           *   Counter Count Down Enable                                                 */
5961             __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
5962                                           *   Counter Count Down Enable                                                 */
5963             __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
5964                                           *   Counter Count Down Enable                                                 */
5965             __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
5966                                           *   Counter Count Down Enable                                                 */
5967             __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
5968                                           *   Counter Count Down Enable                                                 */
5969             __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
5970                                           *   Counter Count Down Enable                                                 */
5971             __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
5972                                           *   Counter Count Down Enable                                                 */
5973             __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
5974                                           *   Counter Count Down Enable                                                 */
5975             __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
5976             __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
5977             __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
5978             __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
5979             __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
5980             __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
5981             __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
5982             __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
5983             __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
5984             uint32_t              : 4;
5985         } GTDNSR_b;
5986     };
5987 
5988     union
5989     {
5990         __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
5991                                           *                  Register A                                                 */
5992 
5993         struct
5994         {
5995             __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
5996             __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
5997                                           *   Enable                                                                    */
5998             __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
5999             __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
6000                                           *   Enable                                                                    */
6001             __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
6002             __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
6003                                           *   Enable                                                                    */
6004             __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
6005             __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
6006                                           *   Enable                                                                    */
6007             __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
6008                                           *   GTCCRA Input Capture Enable                                               */
6009             __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
6010                                           *   GTCCRA Input Capture Enable                                               */
6011             __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
6012                                           *   GTCCRA Input Capture Enable                                               */
6013             __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
6014                                           *   GTCCRA Input Capture Enable                                               */
6015             __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
6016                                           *   GTCCRA Input Capture Enable                                               */
6017             __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
6018                                           *   GTCCRA Input Capture Enable                                               */
6019             __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
6020                                           *   GTCCRA Input Capture Enable                                               */
6021             __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
6022                                           *   GTCCRA Input Capture Enable                                               */
6023             __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
6024             __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
6025             __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
6026             __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
6027             __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
6028             __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
6029             __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
6030             __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
6031             uint32_t              : 8;
6032         } GTICASR_b;
6033     };
6034 
6035     union
6036     {
6037         __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
6038                                           *                  Register B                                                 */
6039 
6040         struct
6041         {
6042             __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
6043             __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
6044                                           *   Enable                                                                    */
6045             __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
6046             __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
6047                                           *   Enable                                                                    */
6048             __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
6049             __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
6050                                           *   Enable                                                                    */
6051             __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
6052             __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
6053                                           *   Enable                                                                    */
6054             __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
6055                                           *   GTCCRB Input Capture Enable                                               */
6056             __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
6057                                           *   GTCCRB Input Capture Enable                                               */
6058             __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
6059                                           *   GTCCRB Input Capture Enable                                               */
6060             __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
6061                                           *   GTCCRB Input Capture Enable                                               */
6062             __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
6063                                           *   GTCCRB Input Capture Enable                                               */
6064             __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
6065                                           *   GTCCRB Input Capture Enable                                               */
6066             __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
6067                                           *   GTCCRB Input Capture Enable                                               */
6068             __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
6069                                           *   GTCCRB Input Capture Enable                                               */
6070             __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
6071             __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
6072             __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
6073             __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
6074             __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
6075             __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
6076             __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
6077             __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
6078             uint32_t              : 8;
6079         } GTICBSR_b;
6080     };
6081 
6082     union
6083     {
6084         __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
6085 
6086         struct
6087         {
6088             __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
6089             uint32_t               : 7;
6090             __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
6091             __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
6092             __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
6093             __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
6094             uint32_t               : 2;
6095             __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
6096             __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
6097             uint32_t               : 4;
6098             __IOM uint32_t TPCS    : 3; /*!< [26..24] Timer Prescaler Select                                           */
6099             __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
6100             uint32_t               : 3;
6101         } GTCR_b;
6102     };
6103 
6104     union
6105     {
6106         __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
6107                                         *                  Register                                                   */
6108 
6109         struct
6110         {
6111             __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
6112             __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
6113             uint32_t              : 14;
6114             __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
6115             __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
6116             __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
6117                                         *   percent Duty Setting                                                      */
6118             uint32_t              : 4;
6119             __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
6120             __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
6121             __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
6122                                         *   percent Duty Setting                                                      */
6123             uint32_t : 4;
6124         } GTUDDTYC_b;
6125     };
6126 
6127     union
6128     {
6129         __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
6130 
6131         struct
6132         {
6133             __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
6134             __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
6135                                         *   Clear Disable.(This bit is only available in GPT324 to
6136                                         *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
6137                                         *   write value should be 0.)                                                 */
6138             __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
6139             __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
6140             __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
6141             __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
6142             __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
6143                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
6144                                         *   GPT323, this bit is read as 0. The write value should be
6145                                         *   0.)                                                                       */
6146             __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
6147             __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
6148             __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
6149             __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
6150             uint32_t              : 1;
6151             __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
6152             __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
6153             __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
6154             __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
6155             __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
6156                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
6157                                         *   GPT323, this bit is read as 0. The write value should be
6158                                         *   0.)                                                                       */
6159             uint32_t             : 1;
6160             __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
6161             __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
6162         } GTIOR_b;
6163     };
6164 
6165     union
6166     {
6167         __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
6168 
6169         struct
6170         {
6171             uint32_t            : 8;
6172             __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
6173                                           *   Clear Enable                                                              */
6174             __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
6175                                           *   Clear Enable                                                              */
6176             __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
6177                                           *   Synchronous Clear Enable                                                  */
6178             __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
6179                                           *   Synchronous Clear Enable                                                  */
6180             __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
6181                                           *   Synchronous Clear Enable                                                  */
6182             __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
6183                                           *   Synchronous Clear Enable                                                  */
6184             __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
6185             __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
6186             __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
6187                                           *   Start Request Enable                                                      */
6188             __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
6189                                           *   Conversion Start Request Enable                                           */
6190             __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
6191                                           *   Start Request Enable                                                      */
6192             __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
6193                                           *   Conversion Start Request Enable                                           */
6194             uint32_t               : 4;
6195             __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
6196             uint32_t               : 2;
6197             __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
6198             __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
6199             __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
6200             __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
6201         } GTINTAD_b;
6202     };
6203 
6204     union
6205     {
6206         __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
6207 
6208         struct
6209         {
6210             __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
6211             __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
6212             __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
6213             __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
6214             __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
6215             __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
6216             __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
6217             __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
6218             __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
6219                                          *   for counting the number of times a timer interrupt has
6220                                          *   been skipped.)                                                            */
6221             uint32_t               : 4;
6222             __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
6223             __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
6224                                          *   Request Interrupt Enable                                                  */
6225             __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
6226                                          *   Start Request Flag                                                        */
6227             __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
6228                                          *   Request Flag                                                              */
6229             __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
6230                                          *   Start Request Flag                                                        */
6231             uint32_t             : 4;
6232             __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
6233             uint32_t             : 3;
6234             __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
6235             __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
6236             __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
6237             __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
6238         } GTST_b;
6239     };
6240 
6241     union
6242     {
6243         __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
6244 
6245         struct
6246         {
6247             __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
6248             __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
6249             __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
6250             __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
6251             uint32_t               : 4;
6252             __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
6253             uint32_t               : 1;
6254             __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
6255             uint32_t               : 5;
6256             __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
6257             __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
6258             __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
6259             __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
6260                                          *   is read as 0.                                                             */
6261             uint32_t             : 1;
6262             __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
6263                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
6264                                          *   at an underflow (in down-counting) or overflow (in up-counting)
6265                                          *   is performed.                                                             */
6266             __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
6267             uint32_t             : 1;
6268             __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
6269                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
6270                                          *   at an underflow (in down-counting) or overflow (in up-counting)
6271                                          *   is performed.                                                             */
6272             __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
6273             uint32_t             : 1;
6274         } GTBER_b;
6275     };
6276 
6277     union
6278     {
6279         __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
6280                                         *                  Start Request Skipping Setting Register                    */
6281 
6282         struct
6283         {
6284             __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
6285             __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
6286             __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
6287             __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
6288             __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
6289             __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
6290             __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
6291             __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
6292             uint32_t             : 1;
6293             __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
6294             uint32_t             : 1;
6295             __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
6296             uint32_t             : 17;
6297         } GTITC_b;
6298     };
6299 
6300     union
6301     {
6302         __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
6303 
6304         struct
6305         {
6306             __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
6307         } GTCNT_b;
6308     };
6309 
6310     union
6311     {
6312         __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
6313 
6314         struct
6315         {
6316             __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
6317         } GTCCR_b[6];
6318     };
6319 
6320     union
6321     {
6322         __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
6323 
6324         struct
6325         {
6326             __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
6327         } GTPR_b;
6328     };
6329 
6330     union
6331     {
6332         __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
6333 
6334         struct
6335         {
6336             __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
6337         } GTPBR_b;
6338     };
6339 
6340     union
6341     {
6342         __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
6343                                          *                  Register                                                   */
6344 
6345         struct
6346         {
6347             __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
6348         } GTPDBR_b;
6349     };
6350 
6351     union
6352     {
6353         __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
6354 
6355         struct
6356         {
6357             __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
6358         } GTADTRA_b;
6359     };
6360 
6361     union
6362     {
6363         __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
6364                                            *                  A                                                          */
6365 
6366         struct
6367         {
6368             __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
6369         } GTADTBRA_b;
6370     };
6371 
6372     union
6373     {
6374         __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
6375                                             *                  Register A                                                 */
6376 
6377         struct
6378         {
6379             __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
6380                                             *   A                                                                         */
6381         } GTADTDBRA_b;
6382     };
6383 
6384     union
6385     {
6386         __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
6387 
6388         struct
6389         {
6390             __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
6391         } GTADTRB_b;
6392     };
6393 
6394     union
6395     {
6396         __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
6397                                            *                  B                                                          */
6398 
6399         struct
6400         {
6401             __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
6402         } GTADTBRB_b;
6403     };
6404 
6405     union
6406     {
6407         __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
6408                                             *                  Register B                                                 */
6409 
6410         struct
6411         {
6412             __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
6413                                             *   B                                                                         */
6414         } GTADTDBRB_b;
6415     };
6416 
6417     union
6418     {
6419         __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
6420 
6421         struct
6422         {
6423             __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
6424             uint32_t             : 3;
6425             __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
6426             __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
6427             uint32_t             : 2;
6428             __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
6429             uint32_t             : 23;
6430         } GTDTCR_b;
6431     };
6432 
6433     union
6434     {
6435         __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
6436 
6437         struct
6438         {
6439             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
6440         } GTDVU_b;
6441     };
6442 
6443     union
6444     {
6445         __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
6446 
6447         struct
6448         {
6449             __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
6450         } GTDVD_b;
6451     };
6452 
6453     union
6454     {
6455         __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
6456 
6457         struct
6458         {
6459             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
6460         } GTDBU_b;
6461     };
6462 
6463     union
6464     {
6465         __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
6466 
6467         struct
6468         {
6469             __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
6470         } GTDBD_b;
6471     };
6472 
6473     union
6474     {
6475         __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
6476                                         *                  Status Register                                            */
6477 
6478         struct
6479         {
6480             __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
6481             uint32_t          : 30;
6482         } GTSOS_b;
6483     };
6484 
6485     union
6486     {
6487         __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
6488                                         *                  Temporary Release Register                                 */
6489 
6490         struct
6491         {
6492             __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
6493             uint32_t            : 31;
6494         } GTSOTR_b;
6495     };
6496 
6497     union
6498     {
6499         __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
6500                                          *                  Signal Monitoring Register                                 */
6501 
6502         struct
6503         {
6504             __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
6505             uint32_t               : 6;
6506             __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
6507                                          *   Enabling                                                                  */
6508             uint32_t               : 7;
6509             __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
6510             uint32_t               : 6;
6511             __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
6512                                          *   Enabling                                                                  */
6513             uint32_t : 7;
6514         } GTADSMR_b;
6515     };
6516 
6517     union
6518     {
6519         __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
6520                                            *                  Counter Control Register                                   */
6521 
6522         struct
6523         {
6524             __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
6525             uint32_t               : 2;
6526             __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
6527             uint32_t               : 4;
6528             __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
6529             __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
6530                                            *   select                                                                    */
6531             uint32_t                 : 2;
6532             __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
6533             __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
6534             __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
6535         } GTEITC_b;
6536     };
6537 
6538     union
6539     {
6540         __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
6541                                         *                  Setting Register 1                                         */
6542 
6543         struct
6544         {
6545             __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
6546                                         *   Extended Skipping Function Select                                         */
6547             uint32_t             : 1;
6548             __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
6549                                         *   Extended Skipping Function Select                                         */
6550             uint32_t             : 1;
6551             __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
6552                                         *   Function Select                                                           */
6553             uint32_t             : 1;
6554             __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
6555                                         *   Function Select                                                           */
6556             uint32_t             : 1;
6557             __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
6558                                         *   Function Select                                                           */
6559             uint32_t             : 1;
6560             __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
6561                                         *   Function Select                                                           */
6562             uint32_t             : 1;
6563             __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
6564             uint32_t             : 1;
6565             __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
6566             uint32_t             : 1;
6567         } GTEITLI1_b;
6568     };
6569 
6570     union
6571     {
6572         __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
6573                                         *                  Setting Register 2                                         */
6574 
6575         struct
6576         {
6577             __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
6578                                         *   Skipping Function Select                                                  */
6579             uint32_t              : 1;
6580             __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
6581                                         *   Skipping Function Select                                                  */
6582             uint32_t : 25;
6583         } GTEITLI2_b;
6584     };
6585 
6586     union
6587     {
6588         __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
6589                                          *                  Setting Register                                           */
6590 
6591         struct
6592         {
6593             __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
6594                                          *   Select                                                                    */
6595             uint32_t              : 1;
6596             __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
6597                                          *   Select                                                                    */
6598             uint32_t              : 1;
6599             __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
6600                                          *   Select                                                                    */
6601             uint32_t               : 5;
6602             __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
6603                                          *   Function Select                                                           */
6604             uint32_t               : 1;
6605             __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
6606                                          *   Function Select                                                           */
6607             uint32_t               : 1;
6608             __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
6609                                          *   Select                                                                    */
6610             uint32_t               : 1;
6611             __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
6612                                          *   Select                                                                    */
6613             uint32_t : 1;
6614         } GTEITLB_b;
6615     };
6616 
6617     union
6618     {
6619         __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
6620                                           *                  Function Setting Register                                  */
6621 
6622         struct
6623         {
6624             __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
6625             uint32_t                : 1;
6626             __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
6627             uint32_t                : 6;
6628             __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
6629             uint32_t                : 1;
6630             __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
6631             uint32_t                : 6;
6632         } GTICLF_b;
6633     };
6634 
6635     union
6636     {
6637         __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
6638 
6639         struct
6640         {
6641             __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
6642             uint32_t            : 7;
6643             __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
6644             uint32_t            : 7;
6645             __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
6646             uint32_t            : 4;
6647         } GTPC_b;
6648     };
6649     __IM uint32_t RESERVED[4];
6650 
6651     union
6652     {
6653         __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
6654                                          *                  Control Channel Select Register                            */
6655 
6656         struct
6657         {
6658             __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
6659                                          *   Select                                                                    */
6660             __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
6661                                          *   Select                                                                    */
6662             __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
6663                                          *   Select                                                                    */
6664             __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
6665                                          *   Select                                                                    */
6666             __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
6667                                          *   Select                                                                    */
6668             __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
6669                                          *   Select                                                                    */
6670             __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
6671                                          *   Select                                                                    */
6672             __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
6673                                          *   Select                                                                    */
6674             __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
6675                                          *   Select                                                                    */
6676             __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
6677                                          *   Select                                                                    */
6678             uint32_t : 22;
6679         } GTSECSR_b;
6680     };
6681 
6682     union
6683     {
6684         __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
6685                                         *                  Control Register                                           */
6686 
6687         struct
6688         {
6689             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
6690             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
6691             __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
6692             __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
6693             uint32_t             : 4;
6694             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
6695             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
6696             __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
6697             __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
6698             uint32_t             : 4;
6699             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
6700             __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
6701             uint32_t             : 6;
6702             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
6703             __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
6704             uint32_t             : 6;
6705         } GTSECR_b;
6706     };
6707     __IM uint32_t RESERVED1[2];
6708 
6709     union
6710     {
6711         __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
6712 
6713         struct
6714         {
6715             __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
6716                                         *   Disable                                                                   */
6717             __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
6718                                         *   Disable                                                                   */
6719             __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
6720             __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
6721                                         *   Disable                                                                   */
6722             __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
6723                                         *   Disable                                                                   */
6724             __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
6725                                         *   Disable                                                                   */
6726             uint32_t             : 2;
6727             __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
6728                                         *   Enable                                                                    */
6729             __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
6730                                         *   Enable                                                                    */
6731             uint32_t              : 1;
6732             __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
6733                                         *   Enable                                                                    */
6734             __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
6735                                         *   Enable                                                                    */
6736             uint32_t             : 1;
6737             __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
6738                                         *   Disable                                                                   */
6739             __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
6740                                         *   Disable                                                                   */
6741             __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
6742                                         *   Disable                                                                   */
6743             __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
6744                                         *   Disable                                                                   */
6745             __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
6746                                         *   Disable                                                                   */
6747             __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
6748                                         *   Transfer Disable                                                          */
6749             uint32_t             : 2;
6750             __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
6751             __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
6752             __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
6753             __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
6754             uint32_t             : 2;
6755         } GTBER2_b;
6756     };
6757 
6758     union
6759     {
6760         __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
6761 
6762         struct
6763         {
6764             __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
6765             uint32_t              : 11;
6766             __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
6767             uint32_t              : 11;
6768         } GTOLBR_b;
6769     };
6770     __IM uint32_t RESERVED2;
6771 
6772     union
6773     {
6774         __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
6775                                         *                  Capture Control Register                                   */
6776 
6777         struct
6778         {
6779             __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
6780                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
6781             __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
6782                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
6783             __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
6784                                         *   Channel GTCCRA Input Capture Source Enable                                */
6785             __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
6786                                         *   Channel GTCCRA Input Capture Source Enable                                */
6787             __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
6788                                         *   Channel GTCCRA Input Capture Source Enable                                */
6789             __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
6790                                         *   Channel GTCCRA Input Capture Source Enable                                */
6791             __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
6792                                         *   Source Enable                                                             */
6793             __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
6794                                         *   Source Enable                                                             */
6795             __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
6796                                         *   Capture Source Enable                                                     */
6797             uint32_t              : 5;
6798             __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
6799             __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
6800                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
6801             __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
6802                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
6803             __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
6804                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
6805             __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
6806                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
6807             __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
6808                                         *   Other Channel GTCCRb Input Capture Source Enable                          */
6809             __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
6810                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
6811             __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
6812                                         *   Source Enable                                                             */
6813             __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
6814                                         *   Capture Source Enable                                                     */
6815             __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
6816                                         *   Capture Source Enable                                                     */
6817             uint32_t              : 5;
6818             __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
6819         } GTICCR_b;
6820     };
6821 } R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
6822 
6823 /* =========================================================================================================================== */
6824 /* ================                                         R_GPT_OPS                                         ================ */
6825 /* =========================================================================================================================== */
6826 
6827 /**
6828  * @brief Output Phase Switching for GPT (R_GPT_OPS)
6829  */
6830 
6831 typedef struct                         /*!< (@ 0x40078FF0) R_GPT_OPS Structure                                        */
6832 {
6833     union
6834     {
6835         __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
6836 
6837         struct
6838         {
6839             __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
6840                                         *   by the software settings.This bit setting is valid when
6841                                         *   the OPSCR.FB bit = 1.                                                     */
6842             __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
6843                                         *   by the software settings.This bit setting is valid when
6844                                         *   the OPSCR.FB bit = 1.                                                     */
6845             __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
6846                                         *   by the software settings.This bit setting is valid when
6847                                         *   the OPSCR.FB bit = 1.                                                     */
6848             uint32_t        : 1;
6849             __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
6850                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
6851                                         *   e settings (UF/VF/WF)                                                     */
6852             __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
6853                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
6854                                         *   e settings (UF/VF/WF)                                                     */
6855             __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
6856                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
6857                                         *   e settings (UF/VF/WF)                                                     */
6858             uint32_t          : 1;
6859             __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
6860             uint32_t          : 7;
6861             __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
6862                                         *   input phase from the software settings and external input.                */
6863             __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
6864             __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
6865             __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
6866             __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
6867             __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
6868             uint32_t             : 2;
6869             __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
6870             __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
6871             uint32_t             : 2;
6872             __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
6873             __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
6874                                         *   sampling clock setting of the external input.                             */
6875         } OPSCR_b;
6876     };
6877 } R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
6878 
6879 /* =========================================================================================================================== */
6880 /* ================                                        R_GPT_POEG0                                        ================ */
6881 /* =========================================================================================================================== */
6882 
6883 /**
6884  * @brief Port Output Enable for GPT (R_GPT_POEG0)
6885  */
6886 
6887 typedef struct                          /*!< (@ 0x40042000) R_GPT_POEG0 Structure                                      */
6888 {
6889     union
6890     {
6891         __IOM uint32_t POEGG;           /*!< (@ 0x00000000) POEG Group Setting Register                                */
6892 
6893         struct
6894         {
6895             __IOM uint32_t PIDF  : 1;   /*!< [0..0] Port Input Detection Flag                                          */
6896             __IOM uint32_t IOCF  : 1;   /*!< [1..1] Real Time Overcurrent Detection Flag                               */
6897             __IOM uint32_t OSTPF : 1;   /*!< [2..2] Oscillation Stop Detection Flag                                    */
6898             __IOM uint32_t SSF   : 1;   /*!< [3..3] Software Stop Flag                                                 */
6899             __IOM uint32_t PIDE  : 1;   /*!< [4..4] Port Input Detection Enable. Note: Can be modified only
6900                                          *   once after a reset.                                                       */
6901             __IOM uint32_t IOCE : 1;    /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified
6902                                          *   only once after a reset.                                                  */
6903             __IOM uint32_t OSTPE : 1;   /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified
6904                                          *   only once after a reset.                                                  */
6905             uint32_t             : 1;
6906             __IOM uint32_t CDRE0 : 1;   /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
6907                                          *   only once after a reset.                                                  */
6908             __IOM uint32_t CDRE1 : 1;   /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
6909                                          *   only once after a reset.                                                  */
6910             __IOM uint32_t CDRE2 : 1;   /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
6911                                          *   only once after a reset.                                                  */
6912             __IOM uint32_t CDRE3 : 1;   /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
6913                                          *   only once after a reset.                                                  */
6914             __IOM uint32_t CDRE4 : 1;   /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
6915                                          *   only once after a reset.                                                  */
6916             __IOM uint32_t CDRE5 : 1;   /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
6917                                          *   only once after a reset.                                                  */
6918             uint32_t               : 2;
6919             __IM uint32_t ST       : 1; /*!< [16..16] GTETRG Input Status Flag                                         */
6920             uint32_t               : 7;
6921             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag                                      */
6922             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag                                      */
6923             __IOM uint32_t DERR0E  : 1; /*!< [26..26] DSMIF0 Error Detection Enable                                    */
6924             __IOM uint32_t DERR1E  : 1; /*!< [27..27] DSMIF1 Error Detection Enable                                    */
6925             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRG Input Reverse                                             */
6926             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise Filter Enable                                              */
6927             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise Filter Clock Select                                        */
6928         } POEGG_b;
6929     };
6930     __IM uint32_t RESERVED[15];
6931 
6932     union
6933     {
6934         __IOM uint16_t GTONCWP;        /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection
6935                                         *                  Register                                                   */
6936 
6937         struct
6938         {
6939             __IOM uint16_t WP    : 1;  /*!< [0..0] Register Writing Disable                                           */
6940             uint16_t             : 7;
6941             __IOM uint16_t PRKEY : 8;  /*!< [15..8] Key Code                                                          */
6942         } GTONCWP_b;
6943     };
6944     __IM uint16_t RESERVED1;
6945 
6946     union
6947     {
6948         __IOM uint16_t GTONCCR;        /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling
6949                                         *                  Register                                                   */
6950 
6951         struct
6952         {
6953             __IOM uint16_t NE  : 1;    /*!< [0..0] Direct Stopping Request Setting                                    */
6954             uint16_t           : 3;
6955             __IOM uint16_t NFS : 4;    /*!< [7..4] Direct Stopping Request Selection                                  */
6956             __IOM uint16_t NFV : 1;    /*!< [8..8] Direct Stopping Request Active Sense                               */
6957             uint16_t           : 7;
6958         } GTONCCR_b;
6959     };
6960     __IM uint16_t RESERVED2;
6961 } R_GPT_POEG0_Type;                    /*!< Size = 72 (0x48)                                                          */
6962 
6963 /* =========================================================================================================================== */
6964 /* ================                                           R_ICU                                           ================ */
6965 /* =========================================================================================================================== */
6966 
6967 /**
6968  * @brief Interrupt Controller Unit (R_ICU)
6969  */
6970 
6971 typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
6972 {
6973     union
6974     {
6975         __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
6976 
6977         struct
6978         {
6979             __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
6980             uint8_t               : 2;
6981             __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
6982             uint8_t               : 1;
6983             __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
6984         } IRQCR_b[16];
6985     };
6986     __IM uint32_t RESERVED[60];
6987 
6988     union
6989     {
6990         __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */
6991 
6992         struct
6993         {
6994             __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
6995             uint8_t                : 3;
6996             __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
6997             uint8_t                : 1;
6998             __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
6999         } NMICR_b;
7000     };
7001     __IM uint8_t  RESERVED1;
7002     __IM uint16_t RESERVED2;
7003     __IM uint32_t RESERVED3[7];
7004 
7005     union
7006     {
7007         __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */
7008 
7009         struct
7010         {
7011             __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
7012             __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
7013             __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
7014             __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
7015             __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
7016             uint16_t               : 1;
7017             __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
7018             __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
7019             __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
7020             __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
7021             __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
7022             __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
7023             __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
7024             __IOM uint16_t TZFEN   : 1; /*!< [13..13] TZFEN                                                            */
7025             uint16_t               : 1;
7026             __IOM uint16_t CPEEN   : 1; /*!< [15..15] CPEEN                                                            */
7027         } NMIER_b;
7028     };
7029     __IM uint16_t RESERVED4;
7030     __IM uint32_t RESERVED5[3];
7031 
7032     union
7033     {
7034         __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */
7035 
7036         struct
7037         {
7038             __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
7039             __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
7040             __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
7041             __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
7042             __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
7043             uint16_t               : 1;
7044             __OM uint16_t  OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
7045             __OM uint16_t  NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
7046             __OM uint16_t  RPECLR  : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
7047             __OM uint16_t  RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
7048             __OM uint16_t  BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear                                            */
7049             __OM uint16_t  BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear                                           */
7050             __OM uint16_t  SPECLR  : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
7051             __IOM uint16_t TZFCLR  : 1; /*!< [13..13] TZFCLR                                                           */
7052             uint16_t               : 1;
7053             __IOM uint16_t CPECLR  : 1; /*!< [15..15] CPECLR                                                           */
7054         } NMICLR_b;
7055     };
7056     __IM uint16_t RESERVED6;
7057     __IM uint32_t RESERVED7[3];
7058 
7059     union
7060     {
7061         __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */
7062 
7063         struct
7064         {
7065             __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
7066             __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
7067             __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
7068             __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
7069             __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
7070             uint16_t              : 1;
7071             __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
7072             __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
7073             __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
7074             __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
7075             __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
7076             __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
7077             __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
7078             __IM uint16_t TZFST   : 1; /*!< [13..13] TZFST                                                            */
7079             uint16_t              : 1;
7080             __IM uint16_t CPEST   : 1; /*!< [15..15] CPEST                                                            */
7081         } NMISR_b;
7082     };
7083     __IM uint16_t RESERVED8;
7084     __IM uint32_t RESERVED9[23];
7085 
7086     union
7087     {
7088         __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */
7089 
7090         struct
7091         {
7092             __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
7093             __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
7094             __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
7095             __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
7096             __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
7097             __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
7098             __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
7099             __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
7100             __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
7101             __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
7102             __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
7103             __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
7104             __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
7105             __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
7106             __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
7107             __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
7108             __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
7109             __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
7110             __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
7111             __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
7112             __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
7113             uint32_t                    : 1;
7114             __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
7115             __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
7116             __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
7117             __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
7118             __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
7119             __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
7120             __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
7121             __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
7122                                               *   enable                                                                    */
7123             __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
7124                                               *   enable                                                                    */
7125             __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
7126         } WUPEN_b;
7127     };
7128 
7129     union
7130     {
7131         __IOM uint32_t WUPEN1;              /*!< (@ 0x000001A4) Wake Up interrupt enable register 1                        */
7132 
7133         struct
7134         {
7135             __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit            */
7136             __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable
7137                                              *   bit                                                                       */
7138             __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable
7139                                              *   bit                                                                       */
7140             uint32_t : 29;
7141         } WUPEN1_b;
7142     };
7143     __IM uint32_t RESERVED10[6];
7144 
7145     union
7146     {
7147         __IOM uint8_t IELEN;            /*!< (@ 0x000001C0) ICU event Enable Register                                  */
7148 
7149         struct
7150         {
7151             __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
7152                                          *   = 1)                                                                      */
7153             __IOM uint8_t IELEN : 1;    /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
7154                                          *   LPOPTEN bit = 1)                                                          */
7155             uint8_t : 6;
7156         } IELEN_b;
7157     };
7158     __IM uint8_t  RESERVED11;
7159     __IM uint16_t RESERVED12;
7160     __IM uint32_t RESERVED13[15];
7161 
7162     union
7163     {
7164         __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */
7165 
7166         struct
7167         {
7168             __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
7169             uint16_t            : 7;
7170         } SELSR0_b;
7171     };
7172     __IM uint16_t RESERVED14;
7173     __IM uint32_t RESERVED15[31];
7174 
7175     union
7176     {
7177         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */
7178 
7179         struct
7180         {
7181             __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
7182             uint32_t            : 7;
7183             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
7184                                         *   IR flag is prohibited.                                                    */
7185             uint32_t : 15;
7186         } DELSR_b[8];
7187     };
7188     __IM uint32_t RESERVED16[24];
7189 
7190     union
7191     {
7192         __IOM uint32_t IELSR[96];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95]                    */
7193 
7194         struct
7195         {
7196             __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
7197                                         *   signal to be linked .                                                     */
7198             uint32_t            : 7;
7199             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
7200             uint32_t            : 7;
7201             __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
7202             uint32_t            : 7;
7203         } IELSR_b[96];
7204     };
7205 } R_ICU_Type;                          /*!< Size = 1152 (0x480)                                                       */
7206 
7207 /* =========================================================================================================================== */
7208 /* ================                                          R_IIC0                                           ================ */
7209 /* =========================================================================================================================== */
7210 
7211 /**
7212  * @brief I2C Bus Interface (R_IIC0)
7213  */
7214 
7215 typedef struct                         /*!< (@ 0x40053000) R_IIC0 Structure                                           */
7216 {
7217     union
7218     {
7219         __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
7220 
7221         struct
7222         {
7223             __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
7224             __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
7225             __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
7226             __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
7227             __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
7228             __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
7229             __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
7230                                         *   is initiated using the IICRST bit for a bus hang-up occurred
7231                                         *   during communication with the master device in slave mode,
7232                                         *   the states may become different between the slave device
7233                                         *   and the master device (due to the difference in the bit
7234                                         *   counter information).                                                     */
7235             __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
7236         } ICCR1_b;
7237     };
7238 
7239     union
7240     {
7241         __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
7242 
7243         struct
7244         {
7245             uint8_t          : 1;
7246             __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
7247                                         *   condition issuance request) when the BBSY flag is set to
7248                                         *   0 (bus free state).                                                       */
7249             __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
7250                                         *   RS bit to 1 while issuing a stop condition.                               */
7251             __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
7252                                         *   bit is not possible while the setting of the BBSY flag
7253                                         *   is 0 (bus free state).Note: Do not set the SP bit to 1
7254                                         *   while a restart condition is being issued.                                */
7255             uint8_t            : 1;
7256             __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
7257             __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
7258             __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
7259         } ICCR2_b;
7260     };
7261 
7262     union
7263     {
7264         __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
7265 
7266         struct
7267         {
7268             __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
7269             __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
7270             __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
7271                                         *   / 2^CKS )                                                                 */
7272             __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
7273         } ICMR1_b;
7274     };
7275 
7276     union
7277     {
7278         __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
7279 
7280         struct
7281         {
7282             __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
7283             __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
7284             __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
7285             uint8_t            : 1;
7286             __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
7287             __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
7288         } ICMR2_b;
7289     };
7290 
7291     union
7292     {
7293         __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
7294 
7295         struct
7296         {
7297             __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
7298             __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
7299             __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
7300             __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
7301             __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
7302             __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
7303                                         *   be sure to read the ICDRR beforehand.                                     */
7304             __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
7305         } ICMR3_b;
7306     };
7307 
7308     union
7309     {
7310         __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
7311 
7312         struct
7313         {
7314             __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
7315             __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
7316             __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
7317             __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
7318             __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
7319             __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
7320             __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
7321             __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
7322         } ICFER_b;
7323     };
7324 
7325     union
7326     {
7327         __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
7328 
7329         struct
7330         {
7331             __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
7332             __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
7333             __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
7334             __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
7335             uint8_t             : 1;
7336             __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
7337             uint8_t             : 1;
7338             __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
7339         } ICSER_b;
7340     };
7341 
7342     union
7343     {
7344         __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
7345 
7346         struct
7347         {
7348             __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
7349             __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
7350             __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
7351             __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
7352             __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
7353             __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
7354             __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
7355             __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
7356         } ICIER_b;
7357     };
7358 
7359     union
7360     {
7361         __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
7362 
7363         struct
7364         {
7365             __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
7366             __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
7367             __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
7368             __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
7369             uint8_t            : 1;
7370             __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
7371             uint8_t            : 1;
7372             __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
7373         } ICSR1_b;
7374     };
7375 
7376     union
7377     {
7378         __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
7379 
7380         struct
7381         {
7382             __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
7383             __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
7384             __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
7385             __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
7386             __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
7387             __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
7388             __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
7389             __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
7390         } ICSR2_b;
7391     };
7392     __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
7393 
7394     union
7395     {
7396         __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
7397 
7398         struct
7399         {
7400             __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
7401             uint8_t           : 3;
7402         } ICBRL_b;
7403     };
7404 
7405     union
7406     {
7407         __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
7408 
7409         struct
7410         {
7411             __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
7412             uint8_t           : 3;
7413         } ICBRH_b;
7414     };
7415 
7416     union
7417     {
7418         __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
7419 
7420         struct
7421         {
7422             __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
7423         } ICDRT_b;
7424     };
7425 
7426     union
7427     {
7428         __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
7429 
7430         struct
7431         {
7432             __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
7433         } ICDRR_b;
7434     };
7435     __IM uint8_t RESERVED[2];
7436 
7437     union
7438     {
7439         __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
7440 
7441         struct
7442         {
7443             __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
7444             uint8_t             : 3;
7445             __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
7446             __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
7447             __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
7448             __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
7449         } ICWUR_b;
7450     };
7451 
7452     union
7453     {
7454         __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
7455 
7456         struct
7457         {
7458             __IOM uint8_t WUSEN  : 1;  /*!< [0..0] Wake-up Function Synchronous Enable                                */
7459             __IM uint8_t  WUASYF : 1;  /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
7460             __IM uint8_t  WUSYF  : 1;  /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
7461             uint8_t              : 5;
7462         } ICWUR2_b;
7463     };
7464 } R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
7465 
7466 /* =========================================================================================================================== */
7467 /* ================                                          R_IWDT                                           ================ */
7468 /* =========================================================================================================================== */
7469 
7470 /**
7471  * @brief Independent Watchdog Timer (R_IWDT)
7472  */
7473 
7474 typedef struct                         /*!< (@ 0x40044400) R_IWDT Structure                                           */
7475 {
7476     union
7477     {
7478         __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
7479 
7480         struct
7481         {
7482             __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
7483                                         *   0xFF to this register.                                                    */
7484         } IWDTRR_b;
7485     };
7486     __IM uint8_t RESERVED;
7487 
7488     union
7489     {
7490         __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */
7491 
7492         struct
7493         {
7494             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
7495             uint16_t            : 2;
7496             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
7497             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
7498             uint16_t            : 2;
7499             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
7500             uint16_t            : 2;
7501         } IWDTCR_b;
7502     };
7503 
7504     union
7505     {
7506         __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
7507 
7508         struct
7509         {
7510             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
7511             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
7512             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
7513         } IWDTSR_b;
7514     };
7515 
7516     union
7517     {
7518         __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */
7519 
7520         struct
7521         {
7522             uint8_t               : 7;
7523             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
7524         } IWDTRCR_b;
7525     };
7526     __IM uint8_t RESERVED1;
7527 
7528     union
7529     {
7530         __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */
7531 
7532         struct
7533         {
7534             uint8_t              : 7;
7535             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
7536         } IWDTCSTPR_b;
7537     };
7538     __IM uint8_t  RESERVED2;
7539     __IM uint16_t RESERVED3;
7540 } R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */
7541 
7542 /* =========================================================================================================================== */
7543 /* ================                                          R_KINT                                           ================ */
7544 /* =========================================================================================================================== */
7545 
7546 /**
7547  * @brief Key Interrupt Function (R_KINT)
7548  */
7549 
7550 typedef struct                         /*!< (@ 0x40080000) R_KINT Structure                                           */
7551 {
7552     union
7553     {
7554         __IOM uint8_t KRCTL;           /*!< (@ 0x00000000) KEY Return Control Register                                */
7555 
7556         struct
7557         {
7558             __IOM uint8_t KREG : 1;    /*!< [0..0] Detection Edge Selection (KRF0 to KRF7)                            */
7559             uint8_t            : 6;
7560             __IOM uint8_t KRMD : 1;    /*!< [7..7] Usage of Key Interrupt Flags(KR0 to KR7)                           */
7561         } KRCTL_b;
7562     };
7563     __IM uint8_t RESERVED[3];
7564 
7565     union
7566     {
7567         __IOM uint8_t KRF;             /*!< (@ 0x00000004) KEY Return Flag Register                                   */
7568 
7569         struct
7570         {
7571             __IOM uint8_t KRF0 : 1;    /*!< [0..0] Key interrupt flag 0                                               */
7572             __IOM uint8_t KRF1 : 1;    /*!< [1..1] Key interrupt flag 1                                               */
7573             __IOM uint8_t KRF2 : 1;    /*!< [2..2] Key interrupt flag 2                                               */
7574             __IOM uint8_t KRF3 : 1;    /*!< [3..3] Key interrupt flag 3                                               */
7575             __IOM uint8_t KRF4 : 1;    /*!< [4..4] Key interrupt flag 4                                               */
7576             __IOM uint8_t KRF5 : 1;    /*!< [5..5] Key interrupt flag 5                                               */
7577             __IOM uint8_t KRF6 : 1;    /*!< [6..6] Key interrupt flag 6                                               */
7578             __IOM uint8_t KRF7 : 1;    /*!< [7..7] Key interrupt flag 7                                               */
7579         } KRF_b;
7580     };
7581     __IM uint8_t RESERVED1[3];
7582 
7583     union
7584     {
7585         __IOM uint8_t KRM;             /*!< (@ 0x00000008) KEY Return Mode Register                                   */
7586 
7587         struct
7588         {
7589             __IOM uint8_t KRM0 : 1;    /*!< [0..0] Key interrupt mode control 0                                       */
7590             __IOM uint8_t KRM1 : 1;    /*!< [1..1] Key interrupt mode control 1                                       */
7591             __IOM uint8_t KRM2 : 1;    /*!< [2..2] Key interrupt mode control 2                                       */
7592             __IOM uint8_t KRM3 : 1;    /*!< [3..3] Key interrupt mode control 3                                       */
7593             __IOM uint8_t KRM4 : 1;    /*!< [4..4] Key interrupt mode control 4                                       */
7594             __IOM uint8_t KRM5 : 1;    /*!< [5..5] Key interrupt mode control 5                                       */
7595             __IOM uint8_t KRM6 : 1;    /*!< [6..6] Key interrupt mode control 6                                       */
7596             __IOM uint8_t KRM7 : 1;    /*!< [7..7] Key interrupt mode control 7                                       */
7597         } KRM_b;
7598     };
7599 } R_KINT_Type;                         /*!< Size = 9 (0x9)                                                            */
7600 
7601 /* =========================================================================================================================== */
7602 /* ================                                           R_MMF                                           ================ */
7603 /* =========================================================================================================================== */
7604 
7605 /**
7606  * @brief Memory Mirror Function (R_MMF)
7607  */
7608 
7609 typedef struct                         /*!< (@ 0x40001000) R_MMF Structure                                            */
7610 {
7611     union
7612     {
7613         __IOM uint32_t MMSFR;          /*!< (@ 0x00000000) MemMirror Special Function Register                        */
7614 
7615         struct
7616         {
7617             uint32_t                  : 7;
7618             __IOM uint32_t MEMMIRADDR : 16; /*!< [22..7] Specifies the memory mirror address.NOTE: A value cannot
7619                                              *   be set in the low-order 7 bits. These bits are fixed to
7620                                              *   0.                                                                        */
7621             uint32_t          : 1;
7622             __OM uint32_t KEY : 8;          /*!< [31..24] MMSFR Key Code                                                   */
7623         } MMSFR_b;
7624     };
7625 
7626     union
7627     {
7628         __IOM uint32_t MMEN;           /*!< (@ 0x00000004) MemMirror Enable Register                                  */
7629 
7630         struct
7631         {
7632             __IOM uint32_t EN : 1;     /*!< [0..0] Memory Mirror Function Enable                                      */
7633             uint32_t          : 23;
7634             __OM uint32_t KEY : 8;     /*!< [31..24] MMEN Key Code                                                    */
7635         } MMEN_b;
7636     };
7637 } R_MMF_Type;                          /*!< Size = 8 (0x8)                                                            */
7638 
7639 /* =========================================================================================================================== */
7640 /* ================                                        R_MPU_MMPU                                         ================ */
7641 /* =========================================================================================================================== */
7642 
7643 /**
7644  * @brief Bus Master MPU (R_MPU_MMPU)
7645  */
7646 
7647 typedef struct                          /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
7648 {
7649     __IOM R_MPU_MMPU_MMPU_Type MMPU[3]; /*!< (@ 0x00000000) Bus Master MPU Registers                                   */
7650 } R_MPU_MMPU_Type;                      /*!< Size = 3072 (0xc00)                                                       */
7651 
7652 /* =========================================================================================================================== */
7653 /* ================                                        R_MPU_SMPU                                         ================ */
7654 /* =========================================================================================================================== */
7655 
7656 /**
7657  * @brief Bus Slave MPU (R_MPU_SMPU)
7658  */
7659 
7660 typedef struct                           /*!< (@ 0x40000C00) R_MPU_SMPU Structure                                       */
7661 {
7662     union
7663     {
7664         __IOM uint16_t SMPUCTL;          /*!< (@ 0x00000000) Slave MPU Control Register                                 */
7665 
7666         struct
7667         {
7668             __IOM uint16_t OAD     : 1;  /*!< [0..0] Master Group enable                                                */
7669             __IOM uint16_t PROTECT : 1;  /*!< [1..1] Protection of register                                             */
7670             uint16_t               : 6;
7671             __OM uint16_t KEY      : 8;  /*!< [15..8] Key Code This bit is used to enable or disable rewriting
7672                                           *   of the PROTECT and OAD bit.                                               */
7673         } SMPUCTL_b;
7674     };
7675     __IM uint16_t              RESERVED[7];
7676     __IOM R_MPU_SMPU_SMPU_Type SMPU[10]; /*!< (@ 0x00000010) Access Control Structure for MBIU                          */
7677 } R_MPU_SMPU_Type;                       /*!< Size = 56 (0x38)                                                          */
7678 
7679 /* =========================================================================================================================== */
7680 /* ================                                        R_MPU_SPMON                                        ================ */
7681 /* =========================================================================================================================== */
7682 
7683 /**
7684  * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
7685  */
7686 
7687 typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
7688 {
7689     __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
7690 } R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
7691 
7692 /* =========================================================================================================================== */
7693 /* ================                                          R_MSTP                                           ================ */
7694 /* =========================================================================================================================== */
7695 
7696 /**
7697  * @brief System-Module Stop (R_MSTP)
7698  */
7699 
7700 typedef struct                          /*!< (@ 0x40047000) R_MSTP Structure                                           */
7701 {
7702     union
7703     {
7704         __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
7705 
7706         struct
7707         {
7708             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
7709             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
7710             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
7711             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
7712             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
7713             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
7714             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
7715             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
7716             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
7717             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
7718             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
7719                                          *   usage.                                                                    */
7720             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
7721                                          *   usage.                                                                    */
7722             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
7723                                          *   usage.                                                                    */
7724             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
7725                                          *   usage.                                                                    */
7726             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
7727                                          *   usage.                                                                    */
7728             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
7729                                          *   usage.                                                                    */
7730             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
7731                                          *   usage.                                                                    */
7732             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
7733                                          *   usage.                                                                    */
7734             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
7735                                          *   usage.                                                                    */
7736             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
7737                                          *   usage.                                                                    */
7738             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
7739                                          *   usage.                                                                    */
7740             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
7741                                          *   usage.                                                                    */
7742             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
7743                                          *   usage.                                                                    */
7744             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
7745                                          *   usage.                                                                    */
7746             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
7747                                          *   usage.                                                                    */
7748             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
7749                                          *   usage.                                                                    */
7750             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
7751                                          *   usage.                                                                    */
7752             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
7753                                          *   usage.                                                                    */
7754             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
7755                                          *   usage.                                                                    */
7756             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
7757                                          *   usage.                                                                    */
7758             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
7759                                          *   usage.                                                                    */
7760             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
7761                                          *   usage.                                                                    */
7762         } MSTPCRA_b;
7763     };
7764 
7765     union
7766     {
7767         __IOM uint32_t MSTPCRB;         /*!< (@ 0x00000004) Module Stop Control Register B                             */
7768 
7769         struct
7770         {
7771             __IOM uint32_t MSTPB0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
7772             __IOM uint32_t MSTPB1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
7773             __IOM uint32_t MSTPB2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
7774             __IOM uint32_t MSTPB3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
7775             __IOM uint32_t MSTPB4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
7776             __IOM uint32_t MSTPB5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
7777             __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
7778             __IOM uint32_t MSTPB7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
7779             __IOM uint32_t MSTPB8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
7780             __IOM uint32_t MSTPB9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
7781             __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
7782                                          *   usage.                                                                    */
7783             __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
7784                                          *   usage.                                                                    */
7785             __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
7786                                          *   usage.                                                                    */
7787             __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
7788                                          *   usage.                                                                    */
7789             __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
7790                                          *   usage.                                                                    */
7791             __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
7792                                          *   usage.                                                                    */
7793             __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
7794                                          *   usage.                                                                    */
7795             __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
7796                                          *   usage.                                                                    */
7797             __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
7798                                          *   usage.                                                                    */
7799             __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
7800                                          *   usage.                                                                    */
7801             __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
7802                                          *   usage.                                                                    */
7803             __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
7804                                          *   usage.                                                                    */
7805             __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
7806                                          *   usage.                                                                    */
7807             __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
7808                                          *   usage.                                                                    */
7809             __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
7810                                          *   usage.                                                                    */
7811             __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
7812                                          *   usage.                                                                    */
7813             __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
7814                                          *   usage.                                                                    */
7815             __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
7816                                          *   usage.                                                                    */
7817             __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
7818                                          *   usage.                                                                    */
7819             __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
7820                                          *   usage.                                                                    */
7821             __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
7822                                          *   usage.                                                                    */
7823             __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
7824                                          *   usage.                                                                    */
7825         } MSTPCRB_b;
7826     };
7827 
7828     union
7829     {
7830         __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
7831 
7832         struct
7833         {
7834             __IOM uint32_t MSTPC0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
7835             __IOM uint32_t MSTPC1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
7836             __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
7837             __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
7838             __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
7839             __IOM uint32_t MSTPC5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
7840             __IOM uint32_t MSTPC6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
7841             __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
7842             __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
7843             __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
7844             __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
7845                                          *   usage.                                                                    */
7846             __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
7847                                          *   usage.                                                                    */
7848             __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
7849                                          *   usage.                                                                    */
7850             __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
7851                                          *   usage.                                                                    */
7852             __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
7853                                          *   usage.                                                                    */
7854             __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
7855                                          *   usage.                                                                    */
7856             __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
7857                                          *   usage.                                                                    */
7858             __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
7859                                          *   usage.                                                                    */
7860             __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
7861                                          *   usage.                                                                    */
7862             __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
7863                                          *   usage.                                                                    */
7864             __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
7865                                          *   usage.                                                                    */
7866             __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
7867                                          *   usage.                                                                    */
7868             __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
7869                                          *   usage.                                                                    */
7870             __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
7871                                          *   usage.                                                                    */
7872             __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
7873                                          *   usage.                                                                    */
7874             __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
7875                                          *   usage.                                                                    */
7876             __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
7877                                          *   usage.                                                                    */
7878             __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
7879                                          *   usage.                                                                    */
7880             __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
7881                                          *   usage.                                                                    */
7882             __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
7883                                          *   usage.                                                                    */
7884             __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
7885                                          *   usage.                                                                    */
7886             __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
7887                                          *   usage.                                                                    */
7888         } MSTPCRC_b;
7889     };
7890 
7891     union
7892     {
7893         __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
7894 
7895         struct
7896         {
7897             __IOM uint32_t MSTPD0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
7898             __IOM uint32_t MSTPD1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
7899             __IOM uint32_t MSTPD2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
7900             __IOM uint32_t MSTPD3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
7901             __IOM uint32_t MSTPD4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
7902             __IOM uint32_t MSTPD5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
7903             __IOM uint32_t MSTPD6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
7904             __IOM uint32_t MSTPD7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
7905             __IOM uint32_t MSTPD8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
7906             __IOM uint32_t MSTPD9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
7907             __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
7908                                          *   usage.                                                                    */
7909             __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
7910                                          *   usage.                                                                    */
7911             __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
7912                                          *   usage.                                                                    */
7913             __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
7914                                          *   usage.                                                                    */
7915             __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
7916                                          *   usage.                                                                    */
7917             __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
7918                                          *   usage.                                                                    */
7919             __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
7920                                          *   usage.                                                                    */
7921             __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
7922                                          *   usage.                                                                    */
7923             __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
7924                                          *   usage.                                                                    */
7925             __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
7926                                          *   usage.                                                                    */
7927             __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
7928                                          *   usage.                                                                    */
7929             __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
7930                                          *   usage.                                                                    */
7931             __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
7932                                          *   usage.                                                                    */
7933             __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
7934                                          *   usage.                                                                    */
7935             __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
7936                                          *   usage.                                                                    */
7937             __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
7938                                          *   usage.                                                                    */
7939             __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
7940                                          *   usage.                                                                    */
7941             __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
7942                                          *   usage.                                                                    */
7943             __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
7944                                          *   usage.                                                                    */
7945             __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
7946                                          *   usage.                                                                    */
7947             __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
7948                                          *   usage.                                                                    */
7949             __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
7950                                          *   usage.                                                                    */
7951         } MSTPCRD_b;
7952     };
7953 
7954     union
7955     {
7956         union
7957         {
7958             __IOM uint32_t MSTPCRE;         /*!< (@ 0x00000010) Module Stop Control Register E                             */
7959 
7960             struct
7961             {
7962                 __IOM uint32_t MSTPE0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
7963                 __IOM uint32_t MSTPE1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
7964                 __IOM uint32_t MSTPE2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
7965                 __IOM uint32_t MSTPE3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
7966                 __IOM uint32_t MSTPE4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
7967                 __IOM uint32_t MSTPE5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
7968                 __IOM uint32_t MSTPE6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
7969                 __IOM uint32_t MSTPE7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
7970                 __IOM uint32_t MSTPE8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
7971                 __IOM uint32_t MSTPE9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
7972                 __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
7973                                              *   usage.                                                                    */
7974                 __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
7975                                              *   usage.                                                                    */
7976                 __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
7977                                              *   usage.                                                                    */
7978                 __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
7979                                              *   usage.                                                                    */
7980                 __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
7981                                              *   usage.                                                                    */
7982                 __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
7983                                              *   usage.                                                                    */
7984                 __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
7985                                              *   usage.                                                                    */
7986                 __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
7987                                              *   usage.                                                                    */
7988                 __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
7989                                              *   usage.                                                                    */
7990                 __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
7991                                              *   usage.                                                                    */
7992                 __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
7993                                              *   usage.                                                                    */
7994                 __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
7995                                              *   usage.                                                                    */
7996                 __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
7997                                              *   usage.                                                                    */
7998                 __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
7999                                              *   usage.                                                                    */
8000                 __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
8001                                              *   usage.                                                                    */
8002                 __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
8003                                              *   usage.                                                                    */
8004                 __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
8005                                              *   usage.                                                                    */
8006                 __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
8007                                              *   usage.                                                                    */
8008                 __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
8009                                              *   usage.                                                                    */
8010                 __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
8011                                              *   usage.                                                                    */
8012                 __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
8013                                              *   usage.                                                                    */
8014                 __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
8015                                              *   usage.                                                                    */
8016             } MSTPCRE_b;
8017         };
8018 
8019         union
8020         {
8021             __IOM uint16_t LSMRWDIS;         /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register              */
8022 
8023             struct
8024             {
8025                 __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control                                    */
8026                 __IOM uint16_t WDTDIS   : 1; /*!< [1..1] WDT Operate Clock Control                                          */
8027                 __IOM uint16_t IWDTIDS  : 1; /*!< [2..2] IWDT Register Clock Control                                        */
8028                 uint16_t                : 4;
8029                 __IOM uint16_t WREN     : 1; /*!< [7..7] Write Enable for bits [2:0]                                        */
8030                 __OM uint16_t  PRKEY    : 8; /*!< [15..8] LSMRWDIS Key Code                                                 */
8031             } LSMRWDIS_b;
8032         };
8033     };
8034 } R_MSTP_Type;                               /*!< Size = 20 (0x14)                                                          */
8035 
8036 /* =========================================================================================================================== */
8037 /* ================                                          R_OPAMP                                          ================ */
8038 /* =========================================================================================================================== */
8039 
8040 /**
8041  * @brief Operational Amplifier (R_OPAMP)
8042  */
8043 
8044 typedef struct                         /*!< (@ 0x400867F8) R_OPAMP Structure                                          */
8045 {
8046     __IM uint8_t RESERVED[8];
8047 
8048     union
8049     {
8050         __IOM uint8_t AMPMC;           /*!< (@ 0x00000008) Operational amplifier mode control register                */
8051 
8052         struct
8053         {
8054             __IOM uint8_t AMPPC0 : 1;  /*!< [0..0] Operational amplifier precharge control status                     */
8055             __IOM uint8_t AMPPC1 : 1;  /*!< [1..1] Operational amplifier precharge control status                     */
8056             __IOM uint8_t AMPPC2 : 1;  /*!< [2..2] Operational amplifier precharge control status                     */
8057             uint8_t              : 4;
8058             __IOM uint8_t AMPSP  : 1;  /*!< [7..7] Operation mode selection                                           */
8059         } AMPMC_b;
8060     };
8061 
8062     union
8063     {
8064         __IOM uint8_t AMPTRM;          /*!< (@ 0x00000009) Operational amplifier trigger mode control register        */
8065 
8066         struct
8067         {
8068             __IOM uint8_t AMPTRM0 : 2; /*!< [1..0] Operational amplifier function activation/stop trigger
8069                                         *   control                                                                   */
8070             __IOM uint8_t AMPTRM1 : 2; /*!< [3..2] Operational amplifier function activation/stop trigger
8071                                         *   control                                                                   */
8072             __IOM uint8_t AMPTRM2 : 2; /*!< [5..4] Operational amplifier function activation/stop trigger
8073                                         *   control                                                                   */
8074             __IOM uint8_t AMPTRM3 : 2; /*!< [7..6] Operational amplifier function activation/stop trigger
8075                                         *   control                                                                   */
8076         } AMPTRM_b;
8077     };
8078 
8079     union
8080     {
8081         __IOM uint8_t AMPTRS;          /*!< (@ 0x0000000A) Operational Amplifier Activation Trigger Select
8082                                         *                  Register                                                   */
8083 
8084         struct
8085         {
8086             __IOM uint8_t AMPTRS : 2;  /*!< [1..0] ELC trigger selection Do not change the value of the
8087                                         *   AMPTRS register after setting the AMPTRM register.                        */
8088             uint8_t : 6;
8089         } AMPTRS_b;
8090     };
8091 
8092     union
8093     {
8094         __IOM uint8_t AMPC;            /*!< (@ 0x0000000B) Operational amplifier control register                     */
8095 
8096         struct
8097         {
8098             __IOM uint8_t AMPE0 : 1;   /*!< [0..0] Operation control of operational amplifier                         */
8099             __IOM uint8_t AMPE1 : 1;   /*!< [1..1] Operation control of operational amplifier                         */
8100             __IOM uint8_t AMPE2 : 1;   /*!< [2..2] Operation control of operational amplifier                         */
8101             __IOM uint8_t AMPE3 : 1;   /*!< [3..3] Operation control of operational amplifier                         */
8102             uint8_t             : 3;
8103             __IOM uint8_t IREFE : 1;   /*!< [7..7] Operation control of operational amplifier reference
8104                                         *   current circuit                                                           */
8105         } AMPC_b;
8106     };
8107 
8108     union
8109     {
8110         __IM uint8_t AMPMON;           /*!< (@ 0x0000000C) Operational amplifier monitor register                     */
8111 
8112         struct
8113         {
8114             __IM uint8_t AMPMON0 : 1;  /*!< [0..0] Operational amplifier status                                       */
8115             __IM uint8_t AMPMON1 : 1;  /*!< [1..1] Operational amplifier status                                       */
8116             __IM uint8_t AMPMON2 : 1;  /*!< [2..2] Operational amplifier status                                       */
8117             __IM uint8_t AMPMON3 : 1;  /*!< [3..3] Operational amplifier status                                       */
8118             uint8_t              : 4;
8119         } AMPMON_b;
8120     };
8121     __IM uint8_t           RESERVED1;
8122     __IOM R_OPAMP_AMP_Type AMP[4];     /*!< (@ 0x0000000E) Input and Output Selectors for Operational Amplifier
8123                                         *                  [0..3]                                                     */
8124 
8125     union
8126     {
8127         __IOM uint8_t AMPCPC;          /*!< (@ 0x0000001A) Operational amplifier switch charge pump control
8128                                         *                  register                                                   */
8129 
8130         struct
8131         {
8132             __IOM uint8_t PUMP0EN : 1; /*!< [0..0] charge pump for AMP0 enable/disable                                */
8133             __IOM uint8_t PUMP1EN : 1; /*!< [1..1] charge pump for AMP1 enable/disable                                */
8134             __IOM uint8_t PUMP2EN : 1; /*!< [2..2] charge pump for AMP2 enable/disable                                */
8135             uint8_t               : 5;
8136         } AMPCPC_b;
8137     };
8138     __IM uint8_t RESERVED2[4];
8139 
8140     union
8141     {
8142         __IOM uint8_t AMPUOTE;         /*!< (@ 0x0000001F) Operational Amplifier User Offset Trimming Enable
8143                                         *                  Register                                                   */
8144 
8145         struct
8146         {
8147             __IOM uint8_t AMP0TE : 1;  /*!< [0..0] AMP0OT write enable                                                */
8148             __IOM uint8_t AMP1TE : 1;  /*!< [1..1] AMP1OT write enable                                                */
8149             __IOM uint8_t AMP2TE : 1;  /*!< [2..2] AMP2OT write enable                                                */
8150             uint8_t              : 5;
8151         } AMPUOTE_b;
8152     };
8153     __IOM R_OPAMP_AMPOT_Type AMPOT[3]; /*!< (@ 0x00000020) Operational Amplifier n Offset Trimming Registers          */
8154 } R_OPAMP_Type;                        /*!< Size = 38 (0x26)                                                          */
8155 
8156 /* =========================================================================================================================== */
8157 /* ================                                          R_PORT0                                          ================ */
8158 /* =========================================================================================================================== */
8159 
8160 /**
8161  * @brief I/O Ports (R_PORT0)
8162  */
8163 
8164 typedef struct                         /*!< (@ 0x40040000) R_PORT0 Structure                                          */
8165 {
8166     union
8167     {
8168         union
8169         {
8170             __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
8171 
8172             struct
8173             {
8174                 __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
8175                 __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
8176             } PCNTR1_b;
8177         };
8178 
8179         struct
8180         {
8181             union
8182             {
8183                 __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */
8184 
8185                 struct
8186                 {
8187                     __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
8188                     __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
8189                     __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
8190                     __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
8191                     __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
8192                     __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
8193                     __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
8194                     __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
8195                     __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
8196                     __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
8197                     __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
8198                     __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
8199                     __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
8200                     __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
8201                     __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
8202                     __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
8203                 } PODR_b;
8204             };
8205 
8206             union
8207             {
8208                 __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */
8209 
8210                 struct
8211                 {
8212                     __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
8213                     __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
8214                     __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
8215                     __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
8216                     __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
8217                     __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
8218                     __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
8219                     __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
8220                     __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
8221                     __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
8222                     __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
8223                     __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
8224                     __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
8225                     __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
8226                     __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
8227                     __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
8228                 } PDR_b;
8229             };
8230         };
8231     };
8232 
8233     union
8234     {
8235         union
8236         {
8237             __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
8238 
8239             struct
8240             {
8241                 __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
8242                 __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
8243             } PCNTR2_b;
8244         };
8245 
8246         struct
8247         {
8248             union
8249             {
8250                 __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */
8251 
8252                 struct
8253                 {
8254                     __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
8255                     __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
8256                     __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
8257                     __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
8258                     __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
8259                     __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
8260                     __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
8261                     __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
8262                     __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
8263                     __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
8264                     __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
8265                     __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
8266                     __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
8267                     __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
8268                     __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
8269                     __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
8270                 } EIDR_b;
8271             };
8272 
8273             union
8274             {
8275                 __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */
8276 
8277                 struct
8278                 {
8279                     __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
8280                     __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
8281                     __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
8282                     __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
8283                     __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
8284                     __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
8285                     __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
8286                     __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
8287                     __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
8288                     __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
8289                     __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
8290                     __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
8291                     __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
8292                     __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
8293                     __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
8294                     __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
8295                 } PIDR_b;
8296             };
8297         };
8298     };
8299 
8300     union
8301     {
8302         union
8303         {
8304             __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
8305 
8306             struct
8307             {
8308                 __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
8309                 __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
8310             } PCNTR3_b;
8311         };
8312 
8313         struct
8314         {
8315             union
8316             {
8317                 __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */
8318 
8319                 struct
8320                 {
8321                     __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
8322                     __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
8323                     __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
8324                     __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
8325                     __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
8326                     __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
8327                     __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
8328                     __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
8329                     __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
8330                     __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
8331                     __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
8332                     __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
8333                     __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
8334                     __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
8335                     __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
8336                     __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
8337                 } PORR_b;
8338             };
8339 
8340             union
8341             {
8342                 __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */
8343 
8344                 struct
8345                 {
8346                     __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
8347                     __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
8348                     __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
8349                     __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
8350                     __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
8351                     __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
8352                     __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
8353                     __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
8354                     __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
8355                     __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
8356                     __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
8357                     __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
8358                     __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
8359                     __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
8360                     __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
8361                     __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
8362                 } POSR_b;
8363             };
8364         };
8365     };
8366 
8367     union
8368     {
8369         union
8370         {
8371             __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
8372 
8373             struct
8374             {
8375                 __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
8376                 __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
8377             } PCNTR4_b;
8378         };
8379 
8380         struct
8381         {
8382             union
8383             {
8384                 __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */
8385 
8386                 struct
8387                 {
8388                     __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
8389                     __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
8390                     __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
8391                     __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
8392                     __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
8393                     __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
8394                     __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
8395                     __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
8396                     __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
8397                     __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
8398                     __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
8399                     __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
8400                     __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
8401                     __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
8402                     __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
8403                     __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
8404                 } EORR_b;
8405             };
8406 
8407             union
8408             {
8409                 __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */
8410 
8411                 struct
8412                 {
8413                     __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
8414                     __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
8415                     __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
8416                     __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
8417                     __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
8418                     __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
8419                     __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
8420                     __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
8421                     __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
8422                     __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
8423                     __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
8424                     __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
8425                     __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
8426                     __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
8427                     __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
8428                     __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
8429                 } EOSR_b;
8430             };
8431         };
8432     };
8433 } R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
8434 
8435 /* =========================================================================================================================== */
8436 /* ================                                           R_PFS                                           ================ */
8437 /* =========================================================================================================================== */
8438 
8439 /**
8440  * @brief I/O Ports-PFS (R_PFS)
8441  */
8442 
8443 typedef struct                           /*!< (@ 0x40040800) R_PFS Structure                                            */
8444 {
8445     union
8446     {
8447         __IOM R_PFS_PORT_Type  PORT[15]; /*!< (@ 0x00000000) Port [0..14]                                               */
8448         __IOM R_PFS_VLSEL_Type VLSEL;    /*!< (@ 0x00000000) VLSEL                                                      */
8449     };
8450 } R_PFS_Type;                            /*!< Size = 960 (0x3c0)                                                        */
8451 
8452 /* =========================================================================================================================== */
8453 /* ================                                          R_PMISC                                          ================ */
8454 /* =========================================================================================================================== */
8455 
8456 /**
8457  * @brief I/O Ports-MISC (R_PMISC)
8458  */
8459 
8460 typedef struct                         /*!< (@ 0x40040D00) R_PMISC Structure                                          */
8461 {
8462     union
8463     {
8464         __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
8465 
8466         struct
8467         {
8468             uint8_t                : 4;
8469             __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
8470             __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1                                          */
8471             uint8_t                : 2;
8472         } PFENET_b;
8473     };
8474     __IM uint8_t RESERVED[2];
8475 
8476     union
8477     {
8478         __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */
8479 
8480         struct
8481         {
8482             uint8_t             : 6;
8483             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
8484             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
8485         } PWPR_b;
8486     };
8487     __IM uint8_t RESERVED1;
8488 
8489     union
8490     {
8491         __IOM uint8_t PWPRS;           /*!< (@ 0x00000005) Write-Protect Register for Secure                          */
8492 
8493         struct
8494         {
8495             uint8_t             : 6;
8496             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
8497             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
8498         } PWPRS_b;
8499     };
8500     __IM uint16_t RESERVED2[4];
8501     __IM uint8_t  RESERVED3;
8502 
8503     union
8504     {
8505         __IOM uint8_t PRWCNTR;          /*!< (@ 0x0000000F) Port Read Wait Control Register                            */
8506 
8507         struct
8508         {
8509             __IOM uint8_t WAIT : 2;     /*!< [1..0] Wait Cycle Control                                                 */
8510             uint8_t            : 6;
8511         } PRWCNTR_b;
8512     };
8513     __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register                         */
8514 } R_PMISC_Type;                         /*!< Size = 40 (0x28)                                                          */
8515 
8516 /* =========================================================================================================================== */
8517 /* ================                                           R_RTC                                           ================ */
8518 /* =========================================================================================================================== */
8519 
8520 /**
8521  * @brief Realtime Clock (R_RTC)
8522  */
8523 
8524 typedef struct                         /*!< (@ 0x40044000) R_RTC Structure                                            */
8525 {
8526     union
8527     {
8528         __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
8529 
8530         struct
8531         {
8532             __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
8533             __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
8534             __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
8535             __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
8536             __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
8537             __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
8538             __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
8539             uint8_t            : 1;
8540         } R64CNT_b;
8541     };
8542     __IM uint8_t RESERVED;
8543 
8544     union
8545     {
8546         union
8547         {
8548             __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
8549 
8550             struct
8551             {
8552                 __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
8553                                           *   counter b7 to b0.                                                         */
8554             } BCNT0_b;
8555         };
8556 
8557         union
8558         {
8559             __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
8560 
8561             struct
8562             {
8563                 __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
8564                                           *   a carry is generated, 1 is added to the tens place.                       */
8565                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
8566                 uint8_t             : 1;
8567             } RSECCNT_b;
8568         };
8569     };
8570     __IM uint8_t RESERVED1;
8571 
8572     union
8573     {
8574         union
8575         {
8576             __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
8577 
8578             struct
8579             {
8580                 __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
8581                                           *   counter b15 to b8.                                                        */
8582             } BCNT1_b;
8583         };
8584 
8585         union
8586         {
8587             __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
8588 
8589             struct
8590             {
8591                 __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
8592                                           *   a carry is generated, 1 is added to the tens place.                       */
8593                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
8594                 uint8_t             : 1;
8595             } RMINCNT_b;
8596         };
8597     };
8598     __IM uint8_t RESERVED2;
8599 
8600     union
8601     {
8602         union
8603         {
8604             __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
8605 
8606             struct
8607             {
8608                 __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
8609                                           *   counter b23 to b16.                                                       */
8610             } BCNT2_b;
8611         };
8612 
8613         union
8614         {
8615             __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
8616 
8617             struct
8618             {
8619                 __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
8620                                          *   carry is generated, 1 is added to the tens place.                         */
8621                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
8622                                          *   the ones place.                                                           */
8623                 __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
8624                 uint8_t          : 1;
8625             } RHRCNT_b;
8626         };
8627     };
8628     __IM uint8_t RESERVED3;
8629 
8630     union
8631     {
8632         union
8633         {
8634             __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
8635 
8636             struct
8637             {
8638                 __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
8639                                           *   counter b31 to b24.                                                       */
8640             } BCNT3_b;
8641         };
8642 
8643         union
8644         {
8645             __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
8646 
8647             struct
8648             {
8649                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
8650                 uint8_t            : 5;
8651             } RWKCNT_b;
8652         };
8653     };
8654     __IM uint8_t RESERVED4;
8655 
8656     union
8657     {
8658         __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
8659 
8660         struct
8661         {
8662             __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
8663                                         *   is generated, 1 is added to the tens place.                               */
8664             __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
8665                                         *   ones place.                                                               */
8666             uint8_t : 2;
8667         } RDAYCNT_b;
8668     };
8669     __IM uint8_t RESERVED5;
8670 
8671     union
8672     {
8673         __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
8674 
8675         struct
8676         {
8677             __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
8678                                         *   a carry is generated, 1 is added to the tens place.                       */
8679             __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
8680                                         *   the ones place.                                                           */
8681             uint8_t : 3;
8682         } RMONCNT_b;
8683     };
8684     __IM uint8_t RESERVED6;
8685 
8686     union
8687     {
8688         __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
8689 
8690         struct
8691         {
8692             __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
8693                                         *   carry is generated, 1 is added to the tens place.                         */
8694             __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
8695                                         *   ones place. When a carry is generated in the tens place,
8696                                         *   1 is added to the hundreds place.                                         */
8697             uint16_t : 8;
8698         } RYRCNT_b;
8699     };
8700 
8701     union
8702     {
8703         union
8704         {
8705             __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
8706 
8707             struct
8708             {
8709                 __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
8710                                             *   corresponding to 32-bit binary counter b7 to b0.                          */
8711             } BCNT0AR_b;
8712         };
8713 
8714         union
8715         {
8716             __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
8717 
8718             struct
8719             {
8720                 __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
8721                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
8722                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
8723             } RSECAR_b;
8724         };
8725     };
8726     __IM uint8_t RESERVED7;
8727 
8728     union
8729     {
8730         union
8731         {
8732             __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
8733 
8734             struct
8735             {
8736                 __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
8737                                             *   corresponding to 32-bit binary counter b15 to b8.                         */
8738             } BCNT1AR_b;
8739         };
8740 
8741         union
8742         {
8743             __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
8744 
8745             struct
8746             {
8747                 __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
8748                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
8749                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
8750             } RMINAR_b;
8751         };
8752     };
8753     __IM uint8_t RESERVED8;
8754 
8755     union
8756     {
8757         union
8758         {
8759             __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
8760 
8761             struct
8762             {
8763                 __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
8764                                             *   counter b23 to b16.                                                       */
8765             } BCNT2AR_b;
8766         };
8767 
8768         union
8769         {
8770             __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
8771 
8772             struct
8773             {
8774                 __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
8775                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
8776                 __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
8777                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
8778             } RHRAR_b;
8779         };
8780     };
8781     __IM uint8_t RESERVED9;
8782 
8783     union
8784     {
8785         union
8786         {
8787             __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
8788 
8789             struct
8790             {
8791                 __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
8792                                             *   counter b31 to b24.                                                       */
8793             } BCNT3AR_b;
8794         };
8795 
8796         union
8797         {
8798             __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
8799 
8800             struct
8801             {
8802                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
8803                 uint8_t            : 4;
8804                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
8805             } RWKAR_b;
8806         };
8807     };
8808     __IM uint8_t RESERVED10;
8809 
8810     union
8811     {
8812         union
8813         {
8814             __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
8815 
8816             struct
8817             {
8818                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
8819                                         *   for setting the alarm enable corresponding to 32-bit binary
8820                                         *   counter b7 to b0.                                                         */
8821             } BCNT0AER_b;
8822         };
8823 
8824         union
8825         {
8826             __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
8827 
8828             struct
8829             {
8830                 __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
8831                 __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
8832                 uint8_t              : 1;
8833                 __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
8834             } RDAYAR_b;
8835         };
8836     };
8837     __IM uint8_t RESERVED11;
8838 
8839     union
8840     {
8841         union
8842         {
8843             __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
8844 
8845             struct
8846             {
8847                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
8848                                         *   for setting the alarm enable corresponding to 32-bit binary
8849                                         *   counter b15 to b8.                                                        */
8850             } BCNT1AER_b;
8851         };
8852 
8853         union
8854         {
8855             __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
8856 
8857             struct
8858             {
8859                 __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
8860                 __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
8861                 uint8_t             : 2;
8862                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
8863             } RMONAR_b;
8864         };
8865     };
8866     __IM uint8_t RESERVED12;
8867 
8868     union
8869     {
8870         union
8871         {
8872             __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
8873 
8874             struct
8875             {
8876                 __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
8877                                          *   for setting the alarm enable corresponding to 32-bit binary
8878                                          *   counter b23 to b16.                                                       */
8879                 uint16_t : 8;
8880             } BCNT2AER_b;
8881         };
8882 
8883         union
8884         {
8885             __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
8886 
8887             struct
8888             {
8889                 __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
8890                 __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
8891                 uint16_t            : 8;
8892             } RYRAR_b;
8893         };
8894     };
8895 
8896     union
8897     {
8898         union
8899         {
8900             __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
8901 
8902             struct
8903             {
8904                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
8905                                         *   for setting the alarm enable corresponding to 32-bit binary
8906                                         *   counter b31 to b24.                                                       */
8907             } BCNT3AER_b;
8908         };
8909 
8910         union
8911         {
8912             __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
8913 
8914             struct
8915             {
8916                 uint8_t           : 7;
8917                 __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
8918             } RYRAREN_b;
8919         };
8920     };
8921     __IM uint8_t  RESERVED13;
8922     __IM uint16_t RESERVED14;
8923 
8924     union
8925     {
8926         __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
8927 
8928         struct
8929         {
8930             __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
8931             __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
8932             __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
8933             __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
8934             __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
8935         } RCR1_b;
8936     };
8937     __IM uint8_t RESERVED15;
8938 
8939     union
8940     {
8941         __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
8942 
8943         struct
8944         {
8945             __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
8946             __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
8947             __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
8948             __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
8949             __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
8950                                         *   the setting of this bit is disabled.)                                     */
8951             __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
8952                                         *   is selected, the setting of this bit is disabled.)                        */
8953             __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
8954             __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
8955         } RCR2_b;
8956     };
8957     __IM uint8_t  RESERVED16;
8958     __IM uint16_t RESERVED17;
8959 
8960     union
8961     {
8962         __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
8963 
8964         struct
8965         {
8966             __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
8967             uint8_t              : 6;
8968             __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
8969         } RCR4_b;
8970     };
8971     __IM uint8_t RESERVED18;
8972 
8973     union
8974     {
8975         __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
8976 
8977         struct
8978         {
8979             __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
8980                                         *   clock from the LOCOclock, this bit sets the comparison
8981                                         *   value of the 128-Hz clock cycle.                                          */
8982             uint16_t : 15;
8983         } RFRH_b;
8984     };
8985 
8986     union
8987     {
8988         __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
8989 
8990         struct
8991         {
8992             __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
8993                                         *   clock from the main clock, this bit sets the comparison
8994                                         *   value of the 128-Hz clock cycle.                                          */
8995         } RFRL_b;
8996     };
8997 
8998     union
8999     {
9000         __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
9001 
9002         struct
9003         {
9004             __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
9005                                         *   from the prescaler.                                                       */
9006             __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
9007         } RADJ_b;
9008     };
9009     __IM uint8_t           RESERVED19;
9010     __IM uint16_t          RESERVED20[8];
9011     __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
9012     __IM uint16_t          RESERVED21[5];
9013     __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
9014 } R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
9015 
9016 /* =========================================================================================================================== */
9017 /* ================                                          R_SCI0                                           ================ */
9018 /* =========================================================================================================================== */
9019 
9020 /**
9021  * @brief Serial Communications Interface (R_SCI0)
9022  */
9023 
9024 typedef struct                         /*!< (@ 0x40070000) R_SCI0 Structure                                           */
9025 {
9026     union
9027     {
9028         union
9029         {
9030             __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
9031 
9032             struct
9033             {
9034                 __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
9035                 __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
9036                 __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
9037                 __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
9038                 __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
9039                 __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
9040                 __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
9041             } SMR_b;
9042         };
9043 
9044         union
9045         {
9046             __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
9047 
9048             struct
9049             {
9050                 __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
9051                 __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
9052                 __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
9053                 __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
9054                 __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
9055                 __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
9056             } SMR_SMCI_b;
9057         };
9058     };
9059 
9060     union
9061     {
9062         __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
9063 
9064         struct
9065         {
9066             __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
9067         } BRR_b;
9068     };
9069 
9070     union
9071     {
9072         union
9073         {
9074             __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
9075 
9076             struct
9077             {
9078                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
9079                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
9080                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
9081                                          *   mode when SMR.MP = 1)                                                     */
9082                 __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
9083                 __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
9084                 __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
9085                 __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
9086             } SCR_b;
9087         };
9088 
9089         union
9090         {
9091             __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
9092 
9093             struct
9094             {
9095                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
9096                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
9097                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
9098                 __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
9099                 __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
9100                 __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
9101                 __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
9102             } SCR_SMCI_b;
9103         };
9104     };
9105 
9106     union
9107     {
9108         __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
9109 
9110         struct
9111         {
9112             __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
9113         } TDR_b;
9114     };
9115 
9116     union
9117     {
9118         union
9119         {
9120             __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
9121 
9122             struct
9123             {
9124                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
9125                 __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
9126                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
9127                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
9128                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
9129                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
9130                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
9131                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
9132             } SSR_b;
9133         };
9134 
9135         union
9136         {
9137             __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
9138 
9139             struct
9140             {
9141                 __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
9142                                          *   multi-processor) and FIFO selected)                                       */
9143                 uint8_t            : 1;
9144                 __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
9145                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
9146                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
9147                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
9148                 __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
9149                 __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
9150             } SSR_FIFO_b;
9151         };
9152 
9153         union
9154         {
9155             __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
9156 
9157             struct
9158             {
9159                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
9160                                          *   card interface mode.                                                      */
9161                 __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
9162                                          *   mode.                                                                     */
9163                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
9164                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
9165                 __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
9166                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
9167                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
9168                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
9169             } SSR_SMCI_b;
9170         };
9171     };
9172 
9173     union
9174     {
9175         __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
9176 
9177         struct
9178         {
9179             __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
9180         } RDR_b;
9181     };
9182 
9183     union
9184     {
9185         __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
9186 
9187         struct
9188         {
9189             __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
9190             uint8_t            : 1;
9191             __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
9192                                         *   operation is to be in simple I2C mode.                                    */
9193             __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
9194                                         *   setting is invalid and a fixed data length of 8 bits is
9195                                         *   used in modes other than asynchronous mode.Set this bit
9196                                         *   to 1 if operation is to be in simple I2C mode.                            */
9197             __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
9198             uint8_t            : 2;
9199             __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
9200                                         *   in combination with the SMR.BCP[1:0] bits                                 */
9201         } SCMR_b;
9202     };
9203 
9204     union
9205     {
9206         __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
9207 
9208         struct
9209         {
9210             __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
9211                                         *   asynchronous mode).                                                       */
9212             __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
9213                                         *   mode).                                                                    */
9214             __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
9215             __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
9216                                         *   only in asynchronous mode and SCR.CKE[1]=0)                               */
9217             __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
9218                                         *   mode)                                                                     */
9219             __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
9220                                         *   be 0 without simple I2C mode and asynchronous mode.)In
9221                                         *   asynchronous mode, for RXDn input only. In simple I2C mode,
9222                                         *   for RXDn/TxDn input.                                                      */
9223             __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
9224                                         *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
9225             __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
9226                                         *   in asynchronous mode)                                                     */
9227         } SEMR_b;
9228     };
9229 
9230     union
9231     {
9232         __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
9233 
9234         struct
9235         {
9236             __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
9237             uint8_t            : 5;
9238         } SNFR_b;
9239     };
9240 
9241     union
9242     {
9243         __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
9244 
9245         struct
9246         {
9247             __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
9248             uint8_t             : 2;
9249             __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
9250                                         *   signal from the on-chip baud rate generator.                              */
9251         } SIMR1_b;
9252     };
9253 
9254     union
9255     {
9256         __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
9257 
9258         struct
9259         {
9260             __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
9261             __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
9262             uint8_t               : 3;
9263             __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
9264             uint8_t               : 2;
9265         } SIMR2_b;
9266     };
9267 
9268     union
9269     {
9270         __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
9271 
9272         struct
9273         {
9274             __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
9275             __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
9276             __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
9277             __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
9278                                            *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
9279             __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
9280             __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
9281         } SIMR3_b;
9282     };
9283 
9284     union
9285     {
9286         __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
9287 
9288         struct
9289         {
9290             __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
9291             uint8_t              : 7;
9292         } SISR_b;
9293     };
9294 
9295     union
9296     {
9297         __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
9298 
9299         struct
9300         {
9301             __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
9302             __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
9303             __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
9304             __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
9305             __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
9306             uint8_t              : 1;
9307             __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
9308             __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
9309         } SPMR_b;
9310     };
9311 
9312     union
9313     {
9314         union
9315         {
9316             __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
9317 
9318             struct
9319             {
9320                 __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
9321             } TDRHL_b;
9322         };
9323 
9324         union
9325         {
9326             __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
9327 
9328             struct
9329             {
9330                 __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
9331                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
9332                 __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
9333                                          *   mode and SMR.MP=1 and FIFO selected)                                      */
9334                 uint16_t : 6;
9335             } FTDRHL_b;
9336         };
9337 
9338         struct
9339         {
9340             union
9341             {
9342                 __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
9343 
9344                 struct
9345                 {
9346                     __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
9347                                              *   mode(including multi-processor) or clock synchronous mode,
9348                                              *   and FIFO selected)                                                        */
9349                     __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
9350                                              *   mode and SMR.MP=1 and FIFO selected)                                      */
9351                     uint8_t : 6;
9352                 } FTDRH_b;
9353             };
9354 
9355             union
9356             {
9357                 __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
9358 
9359                 struct
9360                 {
9361                     __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
9362                                              *   mode(including multi-processor) or clock synchronous mode,
9363                                              *   and FIFO selected)                                                        */
9364                 } FTDRL_b;
9365             };
9366         };
9367     };
9368 
9369     union
9370     {
9371         union
9372         {
9373             __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
9374 
9375             struct
9376             {
9377                 __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
9378             } RDRHL_b;
9379         };
9380 
9381         union
9382         {
9383             __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
9384 
9385             struct
9386             {
9387                 __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
9388                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
9389                 __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
9390                                          *   with SMR.MP=1 and FIFO selected) It can read multi-processor
9391                                          *   bit corresponded to serial receive data(RDATA[8:0])                       */
9392                 __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
9393                 __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
9394                 __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
9395                 __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
9396                 __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
9397                 uint16_t           : 1;
9398             } FRDRHL_b;
9399         };
9400 
9401         struct
9402         {
9403             union
9404             {
9405                 __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
9406 
9407                 struct
9408                 {
9409                     __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
9410                                              *   multi-processor) or clock synchronous mode, and FIFO selected)            */
9411                     __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
9412                                              *   with SMR.MP=1 and FIFO selected) It can read multi-processor
9413                                              *   bit corresponded to serial receive data(RDATA[8:0])                       */
9414                     __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
9415                     __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
9416                     __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
9417                     __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
9418                     __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
9419                     uint8_t           : 1;
9420                 } FRDRH_b;
9421             };
9422 
9423             union
9424             {
9425                 __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
9426 
9427                 struct
9428                 {
9429                     __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
9430                                              *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
9431                                              *   When reading both of FRDRH register and FRDRL register,
9432                                              *   please read by an order of the FRDRH register and the FRDRL
9433                                              *   register.                                                                 */
9434                 } FRDRL_b;
9435             };
9436         };
9437     };
9438 
9439     union
9440     {
9441         __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
9442 
9443         struct
9444         {
9445             __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
9446         } MDDR_b;
9447     };
9448 
9449     union
9450     {
9451         __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
9452 
9453         struct
9454         {
9455             __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
9456             uint8_t             : 2;
9457             __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
9458             __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
9459             uint8_t             : 1;
9460             __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
9461                                         *   multi-processor)                                                          */
9462             __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
9463                                         *   mode(including multi-processor)                                           */
9464         } DCCR_b;
9465     };
9466 
9467     union
9468     {
9469         __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
9470 
9471         struct
9472         {
9473             __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
9474                                         *   multi-processor) or clock synchronous mode)                               */
9475             __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
9476             __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
9477             __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
9478                                         *   reception data ready, the interrupt request is selected.)                 */
9479             __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
9480                                         *   mode(including multi-processor) or clock synchronous mode)                */
9481             __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
9482                                         *   mode(including multi-processor) or clock synchronous mode)                */
9483             __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
9484                                         *   in asynchronous mode(including multi-processor) or clock
9485                                         *   synchronous mode)                                                         */
9486         } FCR_b;
9487     };
9488 
9489     union
9490     {
9491         __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
9492 
9493         struct
9494         {
9495             __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
9496                                         *   data stored in FRDRH and FRDRL(Valid only in asynchronous
9497                                         *   mode(including multi-processor) or clock synchronous mode,
9498                                         *   while FCR.FM=1)                                                           */
9499             uint16_t        : 3;
9500             __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
9501                                         *   data stored in FTDRH and FTDRL(Valid only in asynchronous
9502                                         *   mode(including multi-processor) or clock synchronous mode,
9503                                         *   while FCR.FM=1)                                                           */
9504             uint16_t : 3;
9505         } FDR_b;
9506     };
9507 
9508     union
9509     {
9510         __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
9511 
9512         struct
9513         {
9514             __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
9515                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
9516             uint16_t           : 1;
9517             __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
9518                                         *   a framing error among the receive data stored in the receive
9519                                         *   FIFO data register (FRDRH and FRDRL).                                     */
9520             uint16_t           : 1;
9521             __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
9522                                         *   a parity error among the receive data stored in the receive
9523                                         *   FIFO data register (FRDRH and FRDRL).                                     */
9524             uint16_t : 3;
9525         } LSR_b;
9526     };
9527 
9528     union
9529     {
9530         __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
9531 
9532         struct
9533         {
9534             __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
9535                                         *   wake-up function                                                          */
9536             uint16_t : 7;
9537         } CDR_b;
9538     };
9539 
9540     union
9541     {
9542         __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
9543 
9544         struct
9545         {
9546             __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
9547                                         *   is shown.)                                                                */
9548             __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
9549                                         *   TxD terminal is selected when SCR.TE = 0.)                                */
9550             __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
9551                                         *   of SPB2DT is output to TxD terminal.)                                     */
9552             uint8_t            : 1;
9553             __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
9554             __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
9555             __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
9556             __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
9557         } SPTR_b;
9558     };
9559 
9560     union
9561     {
9562         __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
9563 
9564         struct
9565         {
9566             __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
9567             __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
9568             __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
9569             __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
9570         } ACTR_b;
9571     };
9572     __IM uint16_t RESERVED;
9573 
9574     union
9575     {
9576         __IOM uint8_t ESMER;           /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
9577 
9578         struct
9579         {
9580             __IOM uint8_t ESME : 1;    /*!< [0..0] Extended Serial Mode Enable                                        */
9581             uint8_t            : 7;
9582         } ESMER_b;
9583     };
9584 
9585     union
9586     {
9587         __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
9588 
9589         struct
9590         {
9591             uint8_t             : 1;
9592             __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
9593             __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
9594             __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
9595             uint8_t             : 4;
9596         } CR0_b;
9597     };
9598 
9599     union
9600     {
9601         __IOM uint8_t CR1;             /*!< (@ 0x00000022) Control Register 1                                         */
9602 
9603         struct
9604         {
9605             __IOM uint8_t BFE   : 1;   /*!< [0..0] Break Field Enable                                                 */
9606             __IOM uint8_t CF0RE : 1;   /*!< [1..1] Control Field 0 Reception Enable                                   */
9607             __IOM uint8_t CF1DS : 2;   /*!< [3..2] Control Field 1 Data Register Select                               */
9608             __IOM uint8_t PIBE  : 1;   /*!< [4..4] Priority Interrupt Bit Enable                                      */
9609             __IOM uint8_t PIBS  : 3;   /*!< [7..5] Priority Interrupt Bit Select                                      */
9610         } CR1_b;
9611     };
9612 
9613     union
9614     {
9615         __IOM uint8_t CR2;             /*!< (@ 0x00000023) Control Register 2                                         */
9616 
9617         struct
9618         {
9619             __IOM uint8_t DFCS : 3;    /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
9620             uint8_t            : 1;
9621             __IOM uint8_t BCCS : 2;    /*!< [5..4] Bus Collision Detection Clock Select                               */
9622             __IOM uint8_t RTS  : 2;    /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
9623         } CR2_b;
9624     };
9625 
9626     union
9627     {
9628         __IOM uint8_t CR3;             /*!< (@ 0x00000024) Control Register 3                                         */
9629 
9630         struct
9631         {
9632             __IOM uint8_t SDST : 1;    /*!< [0..0] Start Frame Detection Start                                        */
9633             uint8_t            : 7;
9634         } CR3_b;
9635     };
9636 
9637     union
9638     {
9639         __IOM uint8_t PCR;             /*!< (@ 0x00000025) Port Control Register                                      */
9640 
9641         struct
9642         {
9643             __IOM uint8_t TXDXPS : 1;  /*!< [0..0] TXDXn Signal Polarity Select                                       */
9644             __IOM uint8_t RXDXPS : 1;  /*!< [1..1] RXDXn Signal Polarity Select                                       */
9645             uint8_t              : 2;
9646             __IOM uint8_t SHARPS : 1;  /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
9647             uint8_t              : 3;
9648         } PCR_b;
9649     };
9650 
9651     union
9652     {
9653         __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
9654 
9655         struct
9656         {
9657             __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
9658             __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
9659             __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
9660             __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
9661             __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
9662             __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
9663             uint8_t              : 2;
9664         } ICR_b;
9665     };
9666 
9667     union
9668     {
9669         __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
9670 
9671         struct
9672         {
9673             __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
9674             __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
9675             __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
9676             __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
9677             __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
9678             __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
9679             uint8_t            : 2;
9680         } STR_b;
9681     };
9682 
9683     union
9684     {
9685         __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
9686 
9687         struct
9688         {
9689             __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
9690             __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
9691             __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
9692             __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
9693             __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
9694             __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
9695             uint8_t              : 2;
9696         } STCR_b;
9697     };
9698     __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
9699 
9700     union
9701     {
9702         __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
9703 
9704         struct
9705         {
9706             __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
9707             __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
9708             __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
9709             __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
9710             __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
9711             __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
9712             __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
9713             __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
9714         } CF0CR_b;
9715     };
9716     __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
9717     __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
9718     __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
9719 
9720     union
9721     {
9722         __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
9723 
9724         struct
9725         {
9726             __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
9727             __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
9728             __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
9729             __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
9730             __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
9731             __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
9732             __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
9733             __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
9734         } CF1CR_b;
9735     };
9736     __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
9737 
9738     union
9739     {
9740         __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
9741 
9742         struct
9743         {
9744             __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
9745             uint8_t            : 7;
9746         } TCR_b;
9747     };
9748 
9749     union
9750     {
9751         __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
9752 
9753         struct
9754         {
9755             __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
9756             uint8_t            : 1;
9757             __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
9758             __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
9759             uint8_t            : 1;
9760         } TMR_b;
9761     };
9762     __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
9763     __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
9764 } R_SCI0_Type;                         /*!< Size = 52 (0x34)                                                          */
9765 
9766 /* =========================================================================================================================== */
9767 /* ================                                         R_SDADC0                                          ================ */
9768 /* =========================================================================================================================== */
9769 
9770 /**
9771  * @brief R_SDADC0 (R_SDADC0)
9772  */
9773 
9774 typedef struct                          /*!< (@ 0x4009C000) R_SDADC0 Structure                                         */
9775 {
9776     union
9777     {
9778         __IOM uint16_t STC1;            /*!< (@ 0x00000000) Startup Control Register 1                                 */
9779 
9780         struct
9781         {
9782             __IOM uint16_t CLKDIV  : 4; /*!< [3..0] SDADC24 Reference Clock Division                                   */
9783             uint16_t               : 3;
9784             __IOM uint16_t SDADLPM : 1; /*!< [7..7] A/D conversion operation model select                              */
9785             __IOM uint16_t VSBIAS  : 4; /*!< [11..8] Reference voltage select                                          */
9786             uint16_t               : 3;
9787             __IOM uint16_t VREFSEL : 1; /*!< [15..15] VREF mode select                                                 */
9788         } STC1_b;
9789     };
9790     __IM uint16_t RESERVED;
9791 
9792     union
9793     {
9794         __IOM uint8_t STC2;            /*!< (@ 0x00000004) Startup Control Register 2                                 */
9795 
9796         struct
9797         {
9798             __IOM uint8_t BGRPON  : 1; /*!< [0..0] BGR part power control                                             */
9799             __IOM uint8_t ADCPON  : 1; /*!< [1..1] ADREG forced power-down                                            */
9800             __IOM uint8_t ADFPWDS : 1; /*!< [2..2] ADC reference supply part                                          */
9801             uint8_t               : 5;
9802         } STC2_b;
9803     };
9804     __IM uint8_t  RESERVED1;
9805     __IM uint16_t RESERVED2;
9806 
9807     union
9808     {
9809         __IOM uint32_t PGAC[5];        /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register                  */
9810 
9811         struct
9812         {
9813             __IOM uint32_t PGAGC : 5;  /*!< [4..0] Gain selection of a programmable gain instrumentation
9814                                         *   amplifier ( Gset1, Gset2, Gtotal )                                        */
9815             __IOM uint32_t PGAOSR : 3; /*!< [7..5] Oversampling ratio select                                          */
9816             __IOM uint32_t PGAOFS : 5; /*!< [12..8] Offset voltage select                                             */
9817             uint32_t              : 1;
9818             __IOM uint32_t PGAPOL : 1; /*!< [14..14] Polarity select                                                  */
9819             __IOM uint32_t PGASEL : 1; /*!< [15..15] Analog Channel Input Mode Select                                 */
9820             __IOM uint32_t PGACTM : 5; /*!< [20..16] Coefficient (m) selection of the A/D conversion count
9821                                         *   (N) in AUTOSCAN                                                           */
9822             __IOM uint32_t PGACTN : 3; /*!< [23..21] Coefficient (n) selection of the A/D conversion count
9823                                         *   (N) in AUTOSCAN                                                           */
9824             __IOM uint32_t PGAAVN : 2; /*!< [25..24] Selection of the number of data to be averaged                   */
9825             __IOM uint32_t PGAAVE : 2; /*!< [27..26] Selection of averaging processing                                */
9826             __IOM uint32_t PGAREV : 1; /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
9827             uint32_t              : 1;
9828             __IOM uint32_t PGACVE : 1; /*!< [30..30] Calibration enable                                               */
9829             __IOM uint32_t PGAASN : 1; /*!< [31..31] Selection of the mode for specifying the number of
9830                                         *   A/D conversions in ADSCAN                                                 */
9831         } PGAC_b[5];
9832     };
9833 
9834     union
9835     {
9836         __IOM uint32_t ADC1;            /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1               */
9837 
9838         struct
9839         {
9840             __IOM uint32_t SDADSCM : 1; /*!< [0..0] Selection of autoscan mode                                         */
9841             uint32_t               : 3;
9842             __IOM uint32_t SDADTMD : 1; /*!< [4..4] Selection of A/D conversion trigger signal                         */
9843             uint32_t               : 3;
9844             __IOM uint32_t SDADBMP : 5; /*!< [12..8] A/D conversion control of the signal from input multiplexer       */
9845             uint32_t               : 3;
9846             __IOM uint32_t PGADISA : 1; /*!< [16..16] Control of disconnection detection                               */
9847             __IOM uint32_t PGADISC : 1; /*!< [17..17] Disconnection Detection Assist Setting                           */
9848             uint32_t               : 2;
9849             __IOM uint32_t PGASLFT : 1; /*!< [20..20] PGA offset self-diagnosis enable                                 */
9850             uint32_t               : 11;
9851         } ADC1_b;
9852     };
9853 
9854     union
9855     {
9856         __IOM uint8_t ADC2;            /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2               */
9857 
9858         struct
9859         {
9860             __IOM uint8_t SDADST : 1;  /*!< [0..0] Control of A/D conversion                                          */
9861             uint8_t              : 7;
9862         } ADC2_b;
9863     };
9864     __IM uint8_t  RESERVED3;
9865     __IM uint16_t RESERVED4;
9866 
9867     union
9868     {
9869         __IOM uint32_t ADCR;            /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register       */
9870 
9871         struct
9872         {
9873             __IM uint32_t SDADCRD : 24; /*!< [23..0] The 24-bit A/D conversion result                                  */
9874             __IM uint32_t SDADCRS : 1;  /*!< [24..24] Status of an A/D conversion result                               */
9875             __IM uint32_t SDADCRC : 3;  /*!< [27..25] Channel number for an A/D conversion result                      */
9876             uint32_t              : 4;
9877         } ADCR_b;
9878     };
9879 
9880     union
9881     {
9882         __IM uint32_t ADAR;             /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register           */
9883 
9884         struct
9885         {
9886             __IM uint32_t SDADMVD : 24; /*!< [23..0] The 24-bit A/D average value                                      */
9887             __IM uint32_t SDADMVS : 1;  /*!< [24..24] Status of an A/D conversion result                               */
9888             __IM uint32_t SDADMVC : 3;  /*!< [27..25] Channel number for an A/D conversion result                      */
9889             uint32_t              : 4;
9890         } ADAR_b;
9891     };
9892     __IM uint32_t RESERVED5;
9893 
9894     union
9895     {
9896         __IOM uint8_t CLBC;            /*!< (@ 0x00000030) Calibration Control Register                               */
9897 
9898         struct
9899         {
9900             __IOM uint8_t CLBMD : 2;   /*!< [1..0] These bits are read as 0. The write value should be 0.             */
9901             uint8_t             : 6;
9902         } CLBC_b;
9903     };
9904     __IM uint8_t  RESERVED6;
9905     __IM uint16_t RESERVED7;
9906 
9907     union
9908     {
9909         __IOM uint8_t CLBSTR;          /*!< (@ 0x00000034) Calibration Start Control Register                         */
9910 
9911         struct
9912         {
9913             __IOM uint8_t CLBST : 1;   /*!< [0..0] Calibration start control                                          */
9914             uint8_t             : 7;
9915         } CLBSTR_b;
9916     };
9917     __IM uint8_t  RESERVED8;
9918     __IM uint16_t RESERVED9;
9919     __IM uint32_t RESERVED10;
9920 
9921     union
9922     {
9923         __IM uint8_t CLBSSR;           /*!< (@ 0x0000003C) Calibration Status Register                                */
9924 
9925         struct
9926         {
9927             __IM uint8_t CLBSS : 1;    /*!< [0..0] Calibration status                                                 */
9928             uint8_t            : 7;
9929         } CLBSSR_b;
9930     };
9931     __IM uint8_t  RESERVED11;
9932     __IM uint16_t RESERVED12;
9933 } R_SDADC0_Type;                       /*!< Size = 64 (0x40)                                                          */
9934 
9935 /* =========================================================================================================================== */
9936 /* ================                                          R_SPI0                                           ================ */
9937 /* =========================================================================================================================== */
9938 
9939 /**
9940  * @brief Serial Peripheral Interface (R_SPI0)
9941  */
9942 
9943 typedef struct                         /*!< (@ 0x40072000) R_SPI0 Structure                                           */
9944 {
9945     union
9946     {
9947         __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
9948 
9949         struct
9950         {
9951             __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
9952             __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
9953             __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
9954             __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
9955             __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
9956             __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
9957             __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
9958             __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
9959         } SPCR_b;
9960     };
9961 
9962     union
9963     {
9964         __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
9965 
9966         struct
9967         {
9968             __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
9969             __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
9970             __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
9971             __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
9972             __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
9973             __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
9974             __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
9975             __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
9976         } SSLP_b;
9977     };
9978 
9979     union
9980     {
9981         __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
9982 
9983         struct
9984         {
9985             __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
9986             __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
9987             uint8_t             : 2;
9988             __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
9989             __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
9990             uint8_t             : 2;
9991         } SPPCR_b;
9992     };
9993 
9994     union
9995     {
9996         __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
9997 
9998         struct
9999         {
10000             __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
10001             __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
10002             __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
10003             __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
10004             __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
10005             __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
10006             __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
10007             __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
10008         } SPSR_b;
10009     };
10010 
10011     union
10012     {
10013         __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
10014         __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
10015         __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
10016     };
10017 
10018     union
10019     {
10020         __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
10021 
10022         struct
10023         {
10024             __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
10025                                         *   the SPCMD0 to SPCMD07 registers are to be referenced is
10026                                         *   changed in accordance with the sequence length that is
10027                                         *   set in these bits. The relationship among the setting of
10028                                         *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
10029                                         *   referenced by the RSPI is shown above. However, the RSPI
10030                                         *   in slave mode always references SPCMD0.                                   */
10031             uint8_t : 5;
10032         } SPSCR_b;
10033     };
10034 
10035     union
10036     {
10037         __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
10038 
10039         struct
10040         {
10041             __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
10042             uint8_t            : 1;
10043             __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
10044             uint8_t            : 1;
10045         } SPSSR_b;
10046     };
10047 
10048     union
10049     {
10050         __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
10051 
10052         struct
10053         {
10054             __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
10055         } SPBR_b;
10056     };
10057 
10058     union
10059     {
10060         __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
10061 
10062         struct
10063         {
10064             __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
10065             __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
10066             __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
10067             __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
10068             __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
10069             uint8_t              : 1;
10070         } SPDCR_b;
10071     };
10072 
10073     union
10074     {
10075         __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
10076 
10077         struct
10078         {
10079             __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
10080             uint8_t             : 5;
10081         } SPCKD_b;
10082     };
10083 
10084     union
10085     {
10086         __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
10087 
10088         struct
10089         {
10090             __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
10091             uint8_t             : 5;
10092         } SSLND_b;
10093     };
10094 
10095     union
10096     {
10097         __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
10098 
10099         struct
10100         {
10101             __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
10102             uint8_t             : 5;
10103         } SPND_b;
10104     };
10105 
10106     union
10107     {
10108         __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
10109 
10110         struct
10111         {
10112             __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
10113             __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
10114             __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
10115             __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
10116             __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
10117             __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
10118         } SPCR2_b;
10119     };
10120 
10121     union
10122     {
10123         __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
10124 
10125         struct
10126         {
10127             __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
10128             __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
10129             __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
10130             __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
10131             __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
10132             __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
10133             __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
10134             __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
10135             __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
10136             __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
10137         } SPCMD_b[8];
10138     };
10139 
10140     union
10141     {
10142         __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
10143 
10144         struct
10145         {
10146             __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
10147             __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
10148             uint8_t            : 6;
10149         } SPDCR2_b;
10150     };
10151 
10152     union
10153     {
10154         __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
10155 
10156         struct
10157         {
10158             __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
10159             __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
10160             uint8_t              : 2;
10161             __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
10162             uint8_t              : 3;
10163         } SPCR3_b;
10164     };
10165     __IM uint16_t RESERVED;
10166     __IM uint32_t RESERVED1[6];
10167     __IM uint16_t RESERVED2;
10168 
10169     union
10170     {
10171         __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
10172 
10173         struct
10174         {
10175             uint16_t              : 4;
10176             __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
10177             uint16_t              : 3;
10178             __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
10179             uint16_t              : 1;
10180             __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
10181         } SPPR_b;
10182     };
10183 } R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
10184 
10185 /* =========================================================================================================================== */
10186 /* ================                                          R_SRAM                                           ================ */
10187 /* =========================================================================================================================== */
10188 
10189 /**
10190  * @brief SRAM (R_SRAM)
10191  */
10192 
10193 typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
10194 {
10195     union
10196     {
10197         __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */
10198 
10199         struct
10200         {
10201             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
10202             uint8_t           : 7;
10203         } PARIOAD_b;
10204     };
10205     __IM uint8_t RESERVED[3];
10206 
10207     union
10208     {
10209         __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */
10210 
10211         struct
10212         {
10213             __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
10214             __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
10215         } SRAMPRCR_b;
10216     };
10217     __IM uint8_t  RESERVED1[3];
10218     __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
10219     __IM uint8_t  RESERVED2[3];
10220 
10221     union
10222     {
10223         __IOM uint8_t SRAMPRCR2;         /*!< (@ 0x0000000C) SRAM Protection Register 2                                 */
10224 
10225         struct
10226         {
10227             __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
10228             __OM uint8_t  KW        : 7; /*!< [7..1] Write Key Code                                                     */
10229         } SRAMPRCR2_b;
10230     };
10231     __IM uint8_t RESERVED3[179];
10232 
10233     union
10234     {
10235         __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */
10236 
10237         struct
10238         {
10239             __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
10240             uint8_t              : 6;
10241         } ECCMODE_b;
10242     };
10243 
10244     union
10245     {
10246         __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */
10247 
10248         struct
10249         {
10250             __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
10251             uint8_t               : 7;
10252         } ECC2STS_b;
10253     };
10254 
10255     union
10256     {
10257         __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */
10258 
10259         struct
10260         {
10261             __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
10262             uint8_t               : 7;
10263         } ECC1STSEN_b;
10264     };
10265 
10266     union
10267     {
10268         __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */
10269 
10270         struct
10271         {
10272             __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
10273             uint8_t               : 7;
10274         } ECC1STS_b;
10275     };
10276 
10277     union
10278     {
10279         __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */
10280 
10281         struct
10282         {
10283             __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
10284             __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
10285         } ECCPRCR_b;
10286     };
10287     __IM uint8_t RESERVED4[11];
10288 
10289     union
10290     {
10291         __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */
10292 
10293         struct
10294         {
10295             __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
10296             __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
10297         } ECCPRCR2_b;
10298     };
10299     __IM uint8_t RESERVED5[3];
10300 
10301     union
10302     {
10303         __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */
10304 
10305         struct
10306         {
10307             __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
10308             uint8_t              : 7;
10309         } ECCETST_b;
10310     };
10311     __IM uint8_t RESERVED6[3];
10312 
10313     union
10314     {
10315         __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */
10316 
10317         struct
10318         {
10319             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
10320             uint8_t           : 7;
10321         } ECCOAD_b;
10322     };
10323 } R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */
10324 
10325 /* =========================================================================================================================== */
10326 /* ================                                         R_SYSTEM                                          ================ */
10327 /* =========================================================================================================================== */
10328 
10329 /**
10330  * @brief System Pins (R_SYSTEM)
10331  */
10332 
10333 typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
10334 {
10335     __IM uint32_t RESERVED[3];
10336 
10337     union
10338     {
10339         __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */
10340 
10341         struct
10342         {
10343             uint16_t            : 14;
10344             __IOM uint16_t OPE  : 1;   /*!< [14..14] Output Port Enable                                               */
10345             __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
10346         } SBYCR_b;
10347     };
10348     __IM uint16_t RESERVED1;
10349     __IM uint32_t RESERVED2[3];
10350 
10351     union
10352     {
10353         __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
10354 
10355         struct
10356         {
10357             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage.           */
10358             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage.           */
10359             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage.           */
10360             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage.           */
10361             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage.           */
10362             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage.           */
10363             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage.           */
10364             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage.           */
10365             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage.           */
10366             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage.           */
10367             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for
10368                                          *   usage.                                                                    */
10369             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for
10370                                          *   usage.                                                                    */
10371             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for
10372                                          *   usage.                                                                    */
10373             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for
10374                                          *   usage.                                                                    */
10375             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for
10376                                          *   usage.                                                                    */
10377             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for
10378                                          *   usage.                                                                    */
10379             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for
10380                                          *   usage.                                                                    */
10381             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for
10382                                          *   usage.                                                                    */
10383             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for
10384                                          *   usage.                                                                    */
10385             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for
10386                                          *   usage.                                                                    */
10387             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for
10388                                          *   usage.                                                                    */
10389             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for
10390                                          *   usage.                                                                    */
10391             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for
10392                                          *   usage.                                                                    */
10393             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for
10394                                          *   usage.                                                                    */
10395             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for
10396                                          *   usage.                                                                    */
10397             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for
10398                                          *   usage.                                                                    */
10399             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for
10400                                          *   usage.                                                                    */
10401             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for
10402                                          *   usage.                                                                    */
10403             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for
10404                                          *   usage.                                                                    */
10405             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for
10406                                          *   usage.                                                                    */
10407             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for
10408                                          *   usage.                                                                    */
10409             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for
10410                                          *   usage.                                                                    */
10411         } MSTPCRA_b;
10412     };
10413 
10414     union
10415     {
10416         __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
10417 
10418         struct
10419         {
10420             __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
10421             uint32_t            : 1;
10422             __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
10423             uint32_t            : 1;
10424             __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
10425             uint32_t            : 1;
10426             __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
10427             uint32_t            : 1;
10428             __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
10429             uint32_t            : 5;
10430             __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
10431             uint32_t            : 1;
10432             __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
10433             uint32_t            : 1;
10434         } SCKDIVCR_b;
10435     };
10436 
10437     union
10438     {
10439         __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
10440 
10441         struct
10442         {
10443             uint8_t           : 4;
10444             __IOM uint8_t UCK : 3;     /*!< [6..4] USB Clock (UCLK) Select                                            */
10445             uint8_t           : 1;
10446         } SCKDIVCR2_b;
10447     };
10448     __IM uint8_t RESERVED3;
10449 
10450     union
10451     {
10452         __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
10453 
10454         struct
10455         {
10456             __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
10457             uint8_t             : 5;
10458         } SCKSCR_b;
10459     };
10460     __IM uint8_t RESERVED4;
10461 
10462     union
10463     {
10464         __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
10465 
10466         struct
10467         {
10468             __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
10469             uint16_t                : 2;
10470             __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
10471             uint16_t                : 3;
10472             __IOM uint16_t PLLMUL   : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
10473                                           *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
10474                                           *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
10475                                           *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
10476                                           *   111011: x30.0                                                             */
10477             uint16_t : 2;
10478         } PLLCCR_b;
10479     };
10480 
10481     union
10482     {
10483         __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
10484 
10485         struct
10486         {
10487             __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
10488             uint8_t              : 7;
10489         } PLLCR_b;
10490     };
10491 
10492     union
10493     {
10494         __IOM uint8_t PLLCCR2;         /*!< (@ 0x0000002B) PLL Clock Control Register2                                */
10495 
10496         struct
10497         {
10498             __IOM uint8_t PLLMUL : 5;  /*!< [4..0] PLL Frequency Multiplication Factor Select                         */
10499             uint8_t              : 1;
10500             __IOM uint8_t PLODIV : 2;  /*!< [7..6] PLL Output Frequency Division Ratio Select                         */
10501         } PLLCCR2_b;
10502     };
10503     __IM uint32_t RESERVED5;
10504 
10505     union
10506     {
10507         __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
10508 
10509         struct
10510         {
10511             __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
10512             uint8_t               : 7;
10513         } BCKCR_b;
10514     };
10515 
10516     union
10517     {
10518         __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */
10519 
10520         struct
10521         {
10522             __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
10523                                         *   is prohibited when SCKDIVCR.ICK selects division by 1 and
10524                                         *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
10525                                         *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
10526             uint8_t : 7;
10527         } MEMWAIT_b;
10528     };
10529 
10530     union
10531     {
10532         __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
10533 
10534         struct
10535         {
10536             __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
10537             uint8_t             : 7;
10538         } MOSCCR_b;
10539     };
10540     __IM uint8_t  RESERVED6;
10541     __IM uint16_t RESERVED7;
10542 
10543     union
10544     {
10545         __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
10546 
10547         struct
10548         {
10549             __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
10550             uint8_t             : 7;
10551         } HOCOCR_b;
10552     };
10553 
10554     union
10555     {
10556         __IOM uint8_t HOCOCR2;         /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
10557                                         *                  2                                                          */
10558 
10559         struct
10560         {
10561             __IOM uint8_t HCFRQ0 : 2;  /*!< [1..0] HOCO Frequency Setting 0                                           */
10562             uint8_t              : 1;
10563             __IOM uint8_t HCFRQ1 : 3;  /*!< [5..3] HOCO Frequency Setting 1                                           */
10564             uint8_t              : 2;
10565         } HOCOCR2_b;
10566     };
10567 
10568     union
10569     {
10570         __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
10571 
10572         struct
10573         {
10574             __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
10575             uint8_t             : 7;
10576         } MOCOCR_b;
10577     };
10578 
10579     union
10580     {
10581         __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
10582 
10583         struct
10584         {
10585             __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
10586             uint8_t             : 7;
10587         } FLLCR1_b;
10588     };
10589 
10590     union
10591     {
10592         __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
10593 
10594         struct
10595         {
10596             __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
10597                                           *   FLL reference clock select                                                */
10598             uint16_t : 5;
10599         } FLLCR2_b;
10600     };
10601 
10602     union
10603     {
10604         __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
10605 
10606         struct
10607         {
10608             __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
10609                                         *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
10610                                         *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
10611             uint8_t             : 2;
10612             __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
10613             uint8_t             : 1;
10614             __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
10615             __IM uint8_t PLL2SF : 1;   /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag                          */
10616             uint8_t             : 1;
10617         } OSCSF_b;
10618     };
10619     __IM uint8_t RESERVED8;
10620 
10621     union
10622     {
10623         __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
10624 
10625         struct
10626         {
10627             __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
10628             uint8_t              : 1;
10629             __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
10630             __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
10631         } CKOCR_b;
10632     };
10633 
10634     union
10635     {
10636         __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
10637 
10638         struct
10639         {
10640             __IOM uint8_t TRCK   : 4;  /*!< [3..0] Trace Clock operating frequency select                             */
10641             uint8_t              : 3;
10642             __IOM uint8_t TRCKEN : 1;  /*!< [7..7] Trace Clock operating Enable                                       */
10643         } TRCKCR_b;
10644     };
10645 
10646     union
10647     {
10648         __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
10649 
10650         struct
10651         {
10652             __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
10653             uint8_t              : 6;
10654             __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
10655         } OSTDCR_b;
10656     };
10657 
10658     union
10659     {
10660         __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
10661 
10662         struct
10663         {
10664             __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
10665             uint8_t             : 7;
10666         } OSTDSR_b;
10667     };
10668     __IM uint16_t RESERVED9;
10669     __IM uint32_t RESERVED10;
10670 
10671     union
10672     {
10673         __IOM uint16_t PLL2CCR;           /*!< (@ 0x00000048) PLL2 Clock Control Register                                */
10674 
10675         struct
10676         {
10677             __IOM uint16_t PL2IDIV   : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select                         */
10678             uint16_t                 : 2;
10679             __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select                                           */
10680             uint16_t                 : 3;
10681             __IOM uint16_t PLL2MUL   : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select                       */
10682             uint16_t                 : 2;
10683         } PLL2CCR_b;
10684     };
10685 
10686     union
10687     {
10688         __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
10689 
10690         struct
10691         {
10692             __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
10693             uint8_t               : 7;
10694         } PLL2CR_b;
10695     };
10696     __IM uint8_t RESERVED11;
10697 
10698     union
10699     {
10700         __IOM uint8_t LPOPT;             /*!< (@ 0x0000004C) Lower Power Operation Control Register                     */
10701 
10702         struct
10703         {
10704             __IOM uint8_t MPUDIS : 1;    /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
10705                                           *   (valid only when LPOPTEN = 1)                                             */
10706             __IOM uint8_t DCLKDIS   : 2; /*!< [2..1] Debug Clock Disable Control                                        */
10707             __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
10708                                           *   clock (valid only when LPOPT.LPOPTEN = 1)                                 */
10709             uint8_t               : 3;
10710             __IOM uint8_t LPOPTEN : 1;   /*!< [7..7] Lower Power Operation Enable                                       */
10711         } LPOPT_b;
10712     };
10713     __IM uint8_t  RESERVED12;
10714     __IM uint16_t RESERVED13;
10715 
10716     union
10717     {
10718         __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */
10719 
10720         struct
10721         {
10722             __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
10723             uint8_t                 : 4;
10724             __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
10725         } SLCDSCKCR_b;
10726     };
10727     __IM uint8_t RESERVED14;
10728 
10729     union
10730     {
10731         __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
10732 
10733         struct
10734         {
10735             __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
10736             uint8_t               : 7;
10737         } EBCKOCR_b;
10738     };
10739 
10740     union
10741     {
10742         __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
10743 
10744         struct
10745         {
10746             __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
10747             uint8_t               : 7;
10748         } SDCKOCR_b;
10749     };
10750     __IM uint32_t RESERVED15[3];
10751     __IM uint8_t  RESERVED16;
10752 
10753     union
10754     {
10755         __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
10756 
10757         struct
10758         {
10759             __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
10760                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
10761                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
10762                                          +126 0111_1111 : +127These bits are added to original MOCO
10763                                          *   trimming bits                                                             */
10764         } MOCOUTCR_b;
10765     };
10766 
10767     union
10768     {
10769         __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
10770 
10771         struct
10772         {
10773             __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
10774                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
10775                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
10776                                          +126 0111_1111 : +127These bits are added to original HOCO
10777                                          *   trimming bits                                                             */
10778         } HOCOUTCR_b;
10779     };
10780     __IM uint8_t  RESERVED17;
10781     __IM uint32_t RESERVED18[2];
10782 
10783     union
10784     {
10785         __IOM uint8_t USBCKDIVCR;       /*!< (@ 0x0000006C) USB Clock Division Control Register                        */
10786 
10787         struct
10788         {
10789             __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select                                 */
10790             uint8_t                : 5;
10791         } USBCKDIVCR_b;
10792     };
10793 
10794     union
10795     {
10796         union
10797         {
10798             __IOM uint8_t OCTACKDIVCR;       /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register                  */
10799 
10800             struct
10801             {
10802                 __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select                          */
10803                 uint8_t                 : 5;
10804             } OCTACKDIVCR_b;
10805         };
10806 
10807         union
10808         {
10809             __IOM uint8_t SCISPICKDIVCR;       /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register                    */
10810 
10811             struct
10812             {
10813                 __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select                          */
10814                 uint8_t                   : 5;
10815             } SCISPICKDIVCR_b;
10816         };
10817     };
10818 
10819     union
10820     {
10821         __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Clock Division Control Register                      */
10822 
10823         struct
10824         {
10825             __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select                             */
10826             uint8_t                  : 5;
10827         } CANFDCKDIVCR_b;
10828     };
10829 
10830     union
10831     {
10832         union
10833         {
10834             __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000006F) GPT Clock Division Control Register                        */
10835 
10836             struct
10837             {
10838                 __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select                                 */
10839                 uint8_t                : 5;
10840             } GPTCKDIVCR_b;
10841         };
10842 
10843         union
10844         {
10845             __IOM uint8_t USB60CKDIVCR;       /*!< (@ 0x0000006F) USB60 Clock Division Control Register                      */
10846 
10847             struct
10848             {
10849                 __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select                               */
10850                 uint8_t                  : 5;
10851             } USB60CKDIVCR_b;
10852         };
10853     };
10854 
10855     union
10856     {
10857         union
10858         {
10859             __IOM uint8_t CECCKDIVCR;       /*!< (@ 0x00000070) CEC Clock Division Control Register                        */
10860 
10861             struct
10862             {
10863                 __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select                                 */
10864                 uint8_t                : 5;
10865             } CECCKDIVCR_b;
10866         };
10867 
10868         union
10869         {
10870             __IOM uint8_t IICCKDIVCR;       /*!< (@ 0x00000070) IIC Clock Division Control Register                        */
10871 
10872             struct
10873             {
10874                 __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select                                 */
10875                 uint8_t                : 5;
10876             } IICCKDIVCR_b;
10877         };
10878     };
10879 
10880     union
10881     {
10882         __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
10883 
10884         struct
10885         {
10886             __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
10887             uint8_t                : 5;
10888         } I3CCKDIVCR_b;
10889     };
10890     __IM uint16_t RESERVED19;
10891 
10892     union
10893     {
10894         __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB Clock Control Register                                 */
10895 
10896         struct
10897         {
10898             __IOM uint8_t USBCKSEL  : 3; /*!< [2..0] USB Clock (USBCLK) Source Select                                   */
10899             uint8_t                 : 3;
10900             __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request                               */
10901             __IM uint8_t  USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag                      */
10902         } USBCKCR_b;
10903     };
10904 
10905     union
10906     {
10907         union
10908         {
10909             __IOM uint8_t OCTACKCR;           /*!< (@ 0x00000075) Octal-SPI Clock Control Register                           */
10910 
10911             struct
10912             {
10913                 __IOM uint8_t OCTACKSEL  : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select                            */
10914                 uint8_t                  : 3;
10915                 __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request                        */
10916                 __IM uint8_t  OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag               */
10917             } OCTACKCR_b;
10918         };
10919 
10920         union
10921         {
10922             __IOM uint8_t SCISPICKCR;           /*!< (@ 0x00000075) SCI SPI Clock Control Register                             */
10923 
10924             struct
10925             {
10926                 __IOM uint8_t SCISPICKSEL  : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select                            */
10927                 uint8_t                    : 3;
10928                 __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request                        */
10929                 __IM uint8_t  SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag               */
10930             } SCISPICKCR_b;
10931         };
10932     };
10933 
10934     union
10935     {
10936         __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Clock Control Register                               */
10937 
10938         struct
10939         {
10940             __IOM uint8_t CANFDCKSEL  : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select                               */
10941             uint8_t                   : 3;
10942             __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request                           */
10943             __IM uint8_t  CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag                  */
10944         } CANFDCKCR_b;
10945     };
10946 
10947     union
10948     {
10949         union
10950         {
10951             __IOM uint8_t GPTCKCR;           /*!< (@ 0x00000077) GPT Clock Control Register                                 */
10952 
10953             struct
10954             {
10955                 __IOM uint8_t GPTCKSEL  : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select                                   */
10956                 uint8_t                 : 3;
10957                 __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request                               */
10958                 __IM uint8_t  GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag                      */
10959             } GPTCKCR_b;
10960         };
10961 
10962         union
10963         {
10964             __IOM uint8_t USB60CKCR;           /*!< (@ 0x00000077) USB60 clock control register                               */
10965 
10966             struct
10967             {
10968                 __IOM uint8_t USB60CKSEL  : 4; /*!< [3..0] USB clock (USB60CLK) Source Select                                 */
10969                 uint8_t                   : 2;
10970                 __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request                             */
10971                 __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag                    */
10972             } USB60CKCR_b;
10973         };
10974     };
10975 
10976     union
10977     {
10978         union
10979         {
10980             __IOM uint8_t CECCKCR;           /*!< (@ 0x00000078) CEC Clock Control Register                                 */
10981 
10982             struct
10983             {
10984                 __IOM uint8_t CECCKSEL  : 3; /*!< [2..0] CEC clock (CECCLK) Source Select                                   */
10985                 uint8_t                 : 3;
10986                 __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request                               */
10987                 __IM uint8_t  CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag                      */
10988             } CECCKCR_b;
10989         };
10990 
10991         union
10992         {
10993             __IOM uint8_t IICCKCR;           /*!< (@ 0x00000078) IIC Clock Control Register                                 */
10994 
10995             struct
10996             {
10997                 __IOM uint8_t IICCKSEL  : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select                                   */
10998                 uint8_t                 : 3;
10999                 __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request                               */
11000                 __IM uint8_t  IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag                      */
11001             } IICCKCR_b;
11002         };
11003     };
11004 
11005     union
11006     {
11007         __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000079) I3C Clock Control Register                                 */
11008 
11009         struct
11010         {
11011             __IOM uint8_t I3CCKSEL  : 3; /*!< [2..0] I3C clock (I3CCLK) source select                                   */
11012             uint8_t                 : 3;
11013             __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request                               */
11014             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
11015         } I3CCKCR_b;
11016     };
11017     __IM uint16_t RESERVED20;
11018     __IM uint32_t RESERVED21[3];
11019 
11020     union
11021     {
11022         __IOM uint32_t SNZREQCR1;         /*!< (@ 0x00000088) Snooze Request Control Register 1                          */
11023 
11024         struct
11025         {
11026             __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request                               */
11027             __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request                               */
11028             __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request                               */
11029             uint32_t                 : 29;
11030         } SNZREQCR1_b;
11031     };
11032     __IM uint32_t RESERVED22;
11033     __IM uint16_t RESERVED23;
11034 
11035     union
11036     {
11037         __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */
11038 
11039         struct
11040         {
11041             __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
11042                                          *   than in asynchronous mode.                                                */
11043             __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
11044             uint8_t                : 5;
11045             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
11046         } SNZCR_b;
11047     };
11048     __IM uint8_t RESERVED24;
11049 
11050     union
11051     {
11052         __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */
11053 
11054         struct
11055         {
11056             __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
11057             __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
11058             __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
11059             __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
11060             __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
11061             __IOM uint8_t AD1MATED  : 1; /*!< [5..5] AD compare match 1 Snooze End Enable                               */
11062             __IOM uint8_t AD1UMTED  : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable                            */
11063             __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
11064                                           *   to 1 other than in asynchronous mode.                                     */
11065         } SNZEDCR_b;
11066     };
11067 
11068     union
11069     {
11070         __IOM uint8_t SNZEDCR1;          /*!< (@ 0x00000095) Snooze End Control Register 1                              */
11071 
11072         struct
11073         {
11074             __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable                                   */
11075             uint8_t                 : 7;
11076         } SNZEDCR1_b;
11077     };
11078     __IM uint16_t RESERVED25;
11079 
11080     union
11081     {
11082         __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */
11083 
11084         struct
11085         {
11086             __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
11087             __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
11088             __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
11089             __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
11090             __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
11091             __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
11092             __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
11093             __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
11094             __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
11095             __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
11096             __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
11097             __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
11098             __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
11099             __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
11100             __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
11101             __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
11102             uint32_t                  : 1;
11103             __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request                 */
11104             uint32_t                  : 4;
11105             __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
11106                                             *   request                                                                   */
11107             __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
11108                                             *   request                                                                   */
11109             __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
11110             __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
11111             uint32_t                  : 2;
11112             __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
11113                                             *   request                                                                   */
11114             __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
11115                                             *   snooze request                                                            */
11116             __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
11117                                             *   snooze request                                                            */
11118             uint32_t : 1;
11119         } SNZREQCR_b;
11120     };
11121     __IM uint16_t RESERVED26;
11122 
11123     union
11124     {
11125         __IOM uint8_t FLSTOP;          /*!< (@ 0x0000009E) Flash Operation Control Register                           */
11126 
11127         struct
11128         {
11129             __IOM uint8_t FLSTOP : 1;  /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation                     */
11130             uint8_t              : 3;
11131             __IOM uint8_t FLSTPF : 1;  /*!< [4..4] Flash Memory Operation Status Flag                                 */
11132             uint8_t              : 3;
11133         } FLSTOP_b;
11134     };
11135 
11136     union
11137     {
11138         __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */
11139 
11140         struct
11141         {
11142             __IOM uint8_t PSMC : 2;    /*!< [1..0] Power save memory control.                                         */
11143             uint8_t            : 6;
11144         } PSMCR_b;
11145     };
11146 
11147     union
11148     {
11149         __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
11150 
11151         struct
11152         {
11153             __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
11154             uint8_t              : 2;
11155             __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
11156             uint8_t              : 3;
11157         } OPCCR_b;
11158     };
11159     __IM uint8_t RESERVED27;
11160 
11161     union
11162     {
11163         __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
11164 
11165         struct
11166         {
11167             __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
11168             uint8_t            : 4;
11169         } MOSCWTCR_b;
11170     };
11171     __IM uint8_t RESERVED28[2];
11172 
11173     union
11174     {
11175         __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
11176 
11177         struct
11178         {
11179             __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
11180                                         *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
11181             uint8_t : 5;
11182         } HOCOWTCR_b;
11183     };
11184     __IM uint16_t RESERVED29[2];
11185 
11186     union
11187     {
11188         __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
11189 
11190         struct
11191         {
11192             __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
11193             uint8_t               : 3;
11194             __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
11195             uint8_t               : 3;
11196         } SOPCCR_b;
11197     };
11198     __IM uint8_t  RESERVED30;
11199     __IM uint32_t RESERVED31[5];
11200 
11201     union
11202     {
11203         __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
11204 
11205         struct
11206         {
11207             __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
11208                                         *   only to clear the flag. Confirm the value is 1 and then
11209                                         *   write 0.                                                                  */
11210             __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
11211                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
11212             __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
11213                                         *   the flag. Confirm the value is 1 and then write 0.                        */
11214             uint16_t             : 5;
11215             __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
11216                                         *   to clear the flag. Confirm the value is 1 and then write
11217                                         *   0.                                                                        */
11218             __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
11219                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
11220             __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
11221                                         *   to clear the flag. Confirm the value is 1 and then write
11222                                         *   0.                                                                        */
11223             __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
11224                                         *   to clear the flag. Confirm the value is 1 and then write
11225                                         *   0.                                                                        */
11226             __IOM uint16_t SPERF : 1;  /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
11227                                         *   the flag. Confirm the value is 1 and then write 0.                        */
11228             __IOM uint16_t TZERF : 1;  /*!< [13..13] Trust Zone Error Reset Detect Flag                               */
11229             uint16_t             : 1;
11230             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
11231         } RSTSR1_b;
11232     };
11233     __IM uint16_t RESERVED32;
11234     __IM uint32_t RESERVED33[3];
11235 
11236     union
11237     {
11238         __IOM uint8_t USBCKCR_ALT;       /*!< (@ 0x000000D0) USB Clock Control Register                                 */
11239 
11240         struct
11241         {
11242             __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
11243                                           *   (UCLK).                                                                   */
11244             uint8_t : 7;
11245         } USBCKCR_ALT_b;
11246     };
11247 
11248     union
11249     {
11250         __IOM uint8_t SDADCCKCR;          /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
11251                                            *                  Register                                                   */
11252 
11253         struct
11254         {
11255             __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select                      */
11256             uint8_t                  : 6;
11257             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
11258         } SDADCCKCR_b;
11259     };
11260     __IM uint16_t RESERVED34;
11261     __IM uint32_t RESERVED35[3];
11262 
11263     union
11264     {
11265         __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
11266 
11267         struct
11268         {
11269             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
11270             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
11271             uint8_t              : 5;
11272         } LVD1CR1_b;
11273     };
11274 
11275     union
11276     {
11277         __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
11278 
11279         struct
11280         {
11281             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
11282                                         *   0 can be written to this bit. After writing 0 to this bit,
11283                                         *   it takes 2 system clock cycles for the bit to be read as
11284                                         *   0.                                                                        */
11285             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
11286             uint8_t          : 6;
11287         } LVD1SR_b;
11288     };
11289 
11290     union
11291     {
11292         __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
11293 
11294         struct
11295         {
11296             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
11297             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
11298             uint8_t              : 5;
11299         } LVD2CR1_b;
11300     };
11301 
11302     union
11303     {
11304         __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
11305 
11306         struct
11307         {
11308             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
11309                                         *   0 can be written to this bit. After writing 0 to this bit,
11310                                         *   it takes 2 system clock cycles for the bit to be read as
11311                                         *   0.                                                                        */
11312             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
11313             uint8_t          : 6;
11314         } LVD2SR_b;
11315     };
11316     __IM uint32_t RESERVED36[183];
11317 
11318     union
11319     {
11320         __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
11321                                           *                  Register                                                   */
11322 
11323         struct
11324         {
11325             __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00                                        */
11326             uint32_t                : 1;
11327             __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02                                        */
11328             __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03                                        */
11329             __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04                                        */
11330             __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05                                        */
11331             __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06                                        */
11332             __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07                                        */
11333             __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08                                        */
11334             __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09                                        */
11335             uint32_t                : 1;
11336             __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11                                      */
11337             __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12                                      */
11338             uint32_t                : 3;
11339             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
11340             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
11341             uint32_t                : 14;
11342         } CGFSAR_b;
11343     };
11344     __IM uint32_t RESERVED37;
11345 
11346     union
11347     {
11348         __IOM uint32_t LPMSAR;          /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
11349 
11350         struct
11351         {
11352             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
11353             uint32_t               : 1;
11354             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
11355             uint32_t               : 1;
11356             __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4                                         */
11357             uint32_t               : 3;
11358             __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8                                         */
11359             __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9                                         */
11360             uint32_t               : 22;
11361         } LPMSAR_b;
11362     };
11363 
11364     union
11365     {
11366         union
11367         {
11368             __IOM uint32_t LVDSAR;          /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register        */
11369 
11370             struct
11371             {
11372                 __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
11373                 __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
11374                 uint32_t               : 30;
11375             } LVDSAR_b;
11376         };
11377 
11378         union
11379         {
11380             __IOM uint32_t RSTSAR;          /*!< (@ 0x000003CC) Reset Security Attribution Register                        */
11381 
11382             struct
11383             {
11384                 __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
11385                 __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
11386                 __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
11387                 uint32_t               : 29;
11388             } RSTSAR_b;
11389         };
11390     };
11391 
11392     union
11393     {
11394         __IOM uint32_t BBFSAR;           /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register        */
11395 
11396         struct
11397         {
11398             __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
11399             __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
11400             __IOM uint32_t NONSEC2  : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
11401             uint32_t                : 13;
11402             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
11403             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
11404             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18                                      */
11405             __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19                                      */
11406             __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20                                      */
11407             __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21                                      */
11408             __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22                                      */
11409             __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23                                      */
11410             uint32_t                : 8;
11411         } BBFSAR_b;
11412     };
11413     __IM uint32_t RESERVED38[3];
11414 
11415     union
11416     {
11417         __IOM uint32_t DPFSAR;          /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
11418                                          *                  Register                                                   */
11419 
11420         struct
11421         {
11422             __IOM uint32_t DPFSA0 : 1;  /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit
11423                                          *   0                                                                         */
11424             __IOM uint32_t DPFSA1 : 1;  /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit
11425                                          *   1                                                                         */
11426             __IOM uint32_t DPFSA2 : 1;  /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit
11427                                          *   2                                                                         */
11428             __IOM uint32_t DPFSA3 : 1;  /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit
11429                                          *   3                                                                         */
11430             __IOM uint32_t DPFSA4 : 1;  /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit
11431                                          *   4                                                                         */
11432             __IOM uint32_t DPFSA5 : 1;  /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit
11433                                          *   5                                                                         */
11434             __IOM uint32_t DPFSA6 : 1;  /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit
11435                                          *   6                                                                         */
11436             __IOM uint32_t DPFSA7 : 1;  /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit
11437                                          *   7                                                                         */
11438             __IOM uint32_t DPFSA8 : 1;  /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit
11439                                          *   8                                                                         */
11440             __IOM uint32_t DPFSA9 : 1;  /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit
11441                                          *   9                                                                         */
11442             __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit
11443                                          *   10                                                                        */
11444             __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit
11445                                          *   11                                                                        */
11446             __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit
11447                                          *   12                                                                        */
11448             __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit
11449                                          *   13                                                                        */
11450             __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit
11451                                          *   14                                                                        */
11452             __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit
11453                                          *   15                                                                        */
11454             __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
11455                                          *   16                                                                        */
11456             __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
11457                                          *   17                                                                        */
11458             __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
11459                                          *   18                                                                        */
11460             __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
11461                                          *   19                                                                        */
11462             __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
11463                                          *   20                                                                        */
11464             uint32_t               : 3;
11465             __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
11466                                          *   24                                                                        */
11467             uint32_t               : 1;
11468             __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
11469                                          *   26                                                                        */
11470             __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
11471                                          *   27                                                                        */
11472             uint32_t : 4;
11473         } DPFSAR_b;
11474     };
11475     __IM uint32_t RESERVED39[6];
11476     __IM uint16_t RESERVED40;
11477 
11478     union
11479     {
11480         __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */
11481 
11482         struct
11483         {
11484             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
11485                                         *   generation circuit.                                                       */
11486             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
11487                                         *   modes, the low power consumption modes and the battery
11488                                         *   backup function.                                                          */
11489             uint16_t            : 1;
11490             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
11491             __IOM uint16_t PRC4 : 1;   /*!< [4..4] PRC4                                                               */
11492             uint16_t            : 3;
11493             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
11494         } PRCR_b;
11495     };
11496 
11497     union
11498     {
11499         __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000400) Deep Standby Control Register                              */
11500 
11501         struct
11502         {
11503             __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control                                               */
11504             uint8_t               : 4;
11505             __IOM uint8_t IOKEEP  : 1; /*!< [6..6] I/O Port Retention                                                 */
11506             __IOM uint8_t DPSBY   : 1; /*!< [7..7] Deep Software Standby                                              */
11507         } DPSBYCR_b;
11508     };
11509 
11510     union
11511     {
11512         __IOM uint8_t DPSWCR;          /*!< (@ 0x00000401) Deep Standby Wait Control Register                         */
11513 
11514         struct
11515         {
11516             __IOM uint8_t WTSTS : 6;   /*!< [5..0] Deep Software Wait Standby Time Setting Bit                        */
11517             uint8_t             : 2;
11518         } DPSWCR_b;
11519     };
11520 
11521     union
11522     {
11523         __IOM uint8_t DPSIER0;         /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0                   */
11524 
11525         struct
11526         {
11527             __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ-DS Pin Enable                                                  */
11528             __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ-DS Pin Enable                                                  */
11529             __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ-DS Pin Enable                                                  */
11530             __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ-DS Pin Enable                                                  */
11531             __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ-DS Pin Enable                                                  */
11532             __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ-DS Pin Enable                                                  */
11533             __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ-DS Pin Enable                                                  */
11534             __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ-DS Pin Enable                                                  */
11535         } DPSIER0_b;
11536     };
11537 
11538     union
11539     {
11540         __IOM uint8_t DPSIER1;         /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1                   */
11541 
11542         struct
11543         {
11544             __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ-DS Pin Enable                                                  */
11545             __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ-DS Pin Enable                                                  */
11546             __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable                                                  */
11547             __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable                                                  */
11548             __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable                                                  */
11549             __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable                                                  */
11550             __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable                                                  */
11551             __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable                                                  */
11552         } DPSIER1_b;
11553     };
11554 
11555     union
11556     {
11557         __IOM uint8_t DPSIER2;          /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2                   */
11558 
11559         struct
11560         {
11561             __IOM uint8_t DLVD1IE  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable                             */
11562             __IOM uint8_t DLVD2IE  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable                             */
11563             __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
11564             __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
11565             __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
11566             uint8_t                : 3;
11567         } DPSIER2_b;
11568     };
11569 
11570     union
11571     {
11572         __IOM uint8_t DPSIER3;          /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3                   */
11573 
11574         struct
11575         {
11576             __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
11577             __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
11578             __IOM uint8_t DAGT1IE  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable                   */
11579             __IOM uint8_t DAGT3IE  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable                   */
11580             uint8_t                : 4;
11581         } DPSIER3_b;
11582     };
11583 
11584     union
11585     {
11586         __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0                     */
11587 
11588         struct
11589         {
11590             __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
11591             __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
11592             __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
11593             __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
11594             __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
11595             __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
11596             __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
11597             __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
11598         } DPSIFR0_b;
11599     };
11600 
11601     union
11602     {
11603         __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1                     */
11604 
11605         struct
11606         {
11607             __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
11608             __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
11609             __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
11610             __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
11611             __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
11612             __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
11613             __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
11614             __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
11615         } DPSIFR1_b;
11616     };
11617 
11618     union
11619     {
11620         __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2                     */
11621 
11622         struct
11623         {
11624             __IOM uint8_t DLVD1IF  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag                                      */
11625             __IOM uint8_t DLVD2IF  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag                                      */
11626             __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
11627             __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
11628             __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
11629             uint8_t                : 3;
11630         } DPSIFR2_b;
11631     };
11632 
11633     union
11634     {
11635         __IOM uint8_t DPSIFR3;          /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3                     */
11636 
11637         struct
11638         {
11639             __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
11640             __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
11641             __IOM uint8_t DAGT1IF  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag                            */
11642             __IOM uint8_t DAGT3IF  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag                            */
11643             uint8_t                : 4;
11644         } DPSIFR3_b;
11645     };
11646 
11647     union
11648     {
11649         __IOM uint8_t DPSIEGR0;        /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0                     */
11650 
11651         struct
11652         {
11653             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
11654             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
11655             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
11656             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
11657             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
11658             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
11659             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
11660             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
11661         } DPSIEGR0_b;
11662     };
11663 
11664     union
11665     {
11666         __IOM uint8_t DPSIEGR1;        /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1                     */
11667 
11668         struct
11669         {
11670             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
11671             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
11672             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
11673             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
11674             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
11675             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
11676             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
11677             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
11678         } DPSIEGR1_b;
11679     };
11680 
11681     union
11682     {
11683         __IOM uint8_t DPSIEGR2;         /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2                     */
11684 
11685         struct
11686         {
11687             __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select                                                   */
11688             __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select                                                   */
11689             uint8_t                : 2;
11690             __IOM uint8_t DNMIEG   : 1; /*!< [4..4] NMI Pin Edge Select                                                */
11691             uint8_t                : 3;
11692         } DPSIEGR2_b;
11693     };
11694     __IM uint8_t RESERVED41;
11695 
11696     union
11697     {
11698         __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */
11699 
11700         struct
11701         {
11702             __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
11703             uint8_t             : 6;
11704             __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
11705         } SYOCDCR_b;
11706     };
11707 
11708     union
11709     {
11710         __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
11711 
11712         struct
11713         {
11714             __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
11715             uint8_t             : 6;
11716         } STCONR_b;
11717     };
11718 
11719     union
11720     {
11721         __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */
11722 
11723         struct
11724         {
11725             __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
11726                                         *   the flag. Confirm the value is 1 and then write 0.                        */
11727             __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
11728                                         *   to clear the flag. Confirm the value is 1 and then write
11729                                         *   0.                                                                        */
11730             __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
11731                                         *   to clear the flag. Confirm the value is 1 and then write
11732                                         *   0.                                                                        */
11733             __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
11734                                         *   to clear the flag. Confirm the value is 1 and then write
11735                                         *   0.                                                                        */
11736             uint8_t               : 3;
11737             __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
11738                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
11739         } RSTSR0_b;
11740     };
11741 
11742     union
11743     {
11744         __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */
11745 
11746         struct
11747         {
11748             __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
11749             uint8_t            : 7;
11750         } RSTSR2_b;
11751     };
11752     __IM uint8_t RESERVED42;
11753 
11754     union
11755     {
11756         __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
11757                                         *                  Register                                                   */
11758 
11759         struct
11760         {
11761             uint8_t                 : 3;
11762             __IOM uint8_t MODRV1    : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
11763             __IOM uint8_t MODRV0    : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching                 */
11764             __IOM uint8_t MOSEL     : 1; /*!< [6..6] Main Clock Oscillator Switching                                    */
11765             __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
11766                                           *   Enable                                                                    */
11767         } MOMCR_b;
11768     };
11769     __IM uint16_t RESERVED43;
11770 
11771     union
11772     {
11773         __IOM uint8_t FWEPROR;         /*!< (@ 0x00000416) Flash P/E Protect Register                                 */
11774 
11775         struct
11776         {
11777             __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programming and Erasure                                      */
11778             uint8_t            : 6;
11779         } FWEPROR_b;
11780     };
11781 
11782     union
11783     {
11784         union
11785         {
11786             __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */
11787 
11788             struct
11789             {
11790                 uint8_t             : 5;
11791                 __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
11792                 __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
11793                 uint8_t             : 1;
11794             } LVCMPCR_b;
11795         };
11796 
11797         union
11798         {
11799             __IOM uint8_t LVD1CMPCR;       /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register           */
11800 
11801             struct
11802             {
11803                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
11804                                             *   drop in voltage)                                                          */
11805                 uint8_t             : 2;
11806                 __IOM uint8_t LVD1E : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
11807             } LVD1CMPCR_b;
11808         };
11809     };
11810 
11811     union
11812     {
11813         union
11814         {
11815             __IOM uint8_t LVDLVLR;         /*!< (@ 0x00000418) Voltage Detection Level Select Register                    */
11816 
11817             struct
11818             {
11819                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
11820                                             *   fall in voltage)                                                          */
11821                 __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
11822                                             *   fall in voltage)                                                          */
11823             } LVDLVLR_b;
11824         };
11825 
11826         union
11827         {
11828             __IOM uint8_t LVD2CMPCR;       /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register           */
11829 
11830             struct
11831             {
11832                 __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
11833                                             *   drop in voltage)                                                          */
11834                 uint8_t             : 4;
11835                 __IOM uint8_t LVD2E : 1;   /*!< [7..7] Voltage Detection 2 Enable                                         */
11836             } LVD2CMPCR_b;
11837         };
11838     };
11839     __IM uint8_t RESERVED44;
11840 
11841     union
11842     {
11843         __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */
11844 
11845         struct
11846         {
11847             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
11848             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
11849             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
11850             uint8_t             : 1;
11851             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
11852             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
11853             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
11854         } LVD1CR0_b;
11855     };
11856 
11857     union
11858     {
11859         __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */
11860 
11861         struct
11862         {
11863             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
11864             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
11865             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
11866             uint8_t             : 1;
11867             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
11868             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
11869             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
11870         } LVD2CR0_b;
11871     };
11872     __IM uint8_t RESERVED45;
11873 
11874     union
11875     {
11876         __IOM uint8_t VBATTMNSELR;        /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select
11877                                            *                  Register                                                   */
11878 
11879         struct
11880         {
11881             __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit                       */
11882             uint8_t                  : 7;
11883         } VBATTMNSELR_b;
11884     };
11885 
11886     union
11887     {
11888         __IM uint8_t VBATTMONR;        /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register                    */
11889 
11890         struct
11891         {
11892             __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit                                          */
11893             uint8_t               : 7;
11894         } VBATTMONR_b;
11895     };
11896 
11897     union
11898     {
11899         __IOM uint8_t VBTCR1;           /*!< (@ 0x0000041F) VBATT Control Register1                                    */
11900 
11901         struct
11902         {
11903             __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop                                   */
11904             uint8_t                : 7;
11905         } VBTCR1_b;
11906     };
11907     __IM uint32_t RESERVED46[8];
11908 
11909     union
11910     {
11911         union
11912         {
11913             __IOM uint8_t DCDCCTL;         /*!< (@ 0x00000440) DCDC/LDO Control Register                                  */
11914 
11915             struct
11916             {
11917                 __IOM uint8_t DCDCON  : 1; /*!< [0..0] LDO/DCDC on/off Control bit                                        */
11918                 __IOM uint8_t OCPEN   : 1; /*!< [1..1] DCDC OCP Function Enable bit                                       */
11919                 uint8_t               : 2;
11920                 __IOM uint8_t STOPZA  : 1; /*!< [4..4] DCDC IO Buffer Power Control bit                                   */
11921                 __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit                                       */
11922                 __IOM uint8_t FST     : 1; /*!< [6..6] DCDC Fast Startup                                                  */
11923                 __IOM uint8_t PD      : 1; /*!< [7..7] DCDC VREF Generate Disable bit                                     */
11924             } DCDCCTL_b;
11925         };
11926 
11927         union
11928         {
11929             __IOM uint8_t LDOSCR;          /*!< (@ 0x00000440) LDO Stop Control Register                                  */
11930 
11931             struct
11932             {
11933                 __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop                                                          */
11934                 __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop                                                          */
11935                 uint8_t               : 6;
11936             } LDOSCR_b;
11937         };
11938     };
11939 
11940     union
11941     {
11942         __IOM uint8_t VCCSEL;          /*!< (@ 0x00000441) Voltage Level Selection Control Register                   */
11943 
11944         struct
11945         {
11946             __IOM uint8_t VCCSEL : 2;  /*!< [1..0] DCDC Working Voltage Level Selection                               */
11947             uint8_t              : 6;
11948         } VCCSEL_b;
11949     };
11950     __IM uint16_t RESERVED47;
11951 
11952     union
11953     {
11954         __IOM uint8_t PL2LDOSCR;         /*!< (@ 0x00000444) PLL2-LDO Stop Control Register                             */
11955 
11956         struct
11957         {
11958             __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop                                                          */
11959             uint8_t                 : 7;
11960         } PL2LDOSCR_b;
11961     };
11962     __IM uint8_t  RESERVED48;
11963     __IM uint16_t RESERVED49;
11964     __IM uint32_t RESERVED50[14];
11965 
11966     union
11967     {
11968         __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */
11969 
11970         struct
11971         {
11972             __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
11973             uint8_t             : 7;
11974         } SOSCCR_b;
11975     };
11976 
11977     union
11978     {
11979         __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */
11980 
11981         struct
11982         {
11983             __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
11984             uint8_t             : 6;
11985         } SOMCR_b;
11986     };
11987 
11988     union
11989     {
11990         __IOM uint8_t SOMRG;           /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register                 */
11991 
11992         struct
11993         {
11994             __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching                        */
11995             uint8_t               : 6;
11996         } SOMRG_b;
11997     };
11998     __IM uint8_t  RESERVED51;
11999     __IM uint32_t RESERVED52[3];
12000 
12001     union
12002     {
12003         __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */
12004 
12005         struct
12006         {
12007             __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
12008             uint8_t             : 7;
12009         } LOCOCR_b;
12010     };
12011     __IM uint8_t RESERVED53;
12012 
12013     union
12014     {
12015         __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */
12016 
12017         struct
12018         {
12019             __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
12020                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
12021                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
12022                                          +126 0111_1111 : +127These bits are added to original LOCO
12023                                          *   trimming bits                                                             */
12024         } LOCOUTCR_b;
12025     };
12026     __IM uint8_t  RESERVED54;
12027     __IM uint32_t RESERVED55[7];
12028 
12029     union
12030     {
12031         __IOM uint8_t VBTCR2;          /*!< (@ 0x000004B0) VBATT Control Register2                                    */
12032 
12033         struct
12034         {
12035             uint8_t                 : 4;
12036             __IOM uint8_t VBTLVDEN  : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit                            */
12037             uint8_t                 : 1;
12038             __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit              */
12039         } VBTCR2_b;
12040     };
12041 
12042     union
12043     {
12044         __IOM uint8_t VBTSR;           /*!< (@ 0x000004B1) VBATT Status Register                                      */
12045 
12046         struct
12047         {
12048             __IOM uint8_t VBTRDF  : 1; /*!< [0..0] VBAT_R Reset Detect Flag                                           */
12049             __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag                              */
12050             uint8_t               : 2;
12051             __IM uint8_t VBTRVLD  : 1; /*!< [4..4] VBATT_R Valid                                                      */
12052             uint8_t               : 3;
12053         } VBTSR_b;
12054     };
12055 
12056     union
12057     {
12058         __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004B2) VBATT Comparator Control Register                          */
12059 
12060         struct
12061         {
12062             __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable                 */
12063             uint8_t               : 7;
12064         } VBTCMPCR_b;
12065     };
12066     __IM uint8_t RESERVED56;
12067 
12068     union
12069     {
12070         __IOM uint8_t VBTLVDICR;          /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
12071                                            *                  Register                                                   */
12072 
12073         struct
12074         {
12075             __IOM uint8_t VBTLVDIE   : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit                  */
12076             __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit                        */
12077             uint8_t                  : 6;
12078         } VBTLVDICR_b;
12079     };
12080     __IM uint8_t RESERVED57;
12081 
12082     union
12083     {
12084         __IOM uint8_t VBTWCTLR;        /*!< (@ 0x000004B6) VBATT Wakeup function Control Register                     */
12085 
12086         struct
12087         {
12088             __IOM uint8_t VWEN : 1;    /*!< [0..0] VBATT wakeup enable                                                */
12089             uint8_t            : 7;
12090         } VBTWCTLR_b;
12091     };
12092     __IM uint8_t RESERVED58;
12093 
12094     union
12095     {
12096         __IOM uint8_t VBTWCH0OTSR;     /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register          */
12097 
12098         struct
12099         {
12100             uint8_t                  : 1;
12101             __IOM uint8_t CH0VCH1TE  : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable                            */
12102             __IOM uint8_t CH0VCH2TE  : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable                            */
12103             __IOM uint8_t CH0VRTCTE  : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable                         */
12104             __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable                            */
12105             __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable                        */
12106             uint8_t                  : 2;
12107         } VBTWCH0OTSR_b;
12108     };
12109 
12110     union
12111     {
12112         __IOM uint8_t VBTWCH1OTSR;        /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register          */
12113 
12114         struct
12115         {
12116             __IOM uint8_t CH1VCH0TE  : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable                            */
12117             uint8_t                  : 1;
12118             __IOM uint8_t CH1VCH2TE  : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable                            */
12119             __IOM uint8_t CH1VRTCTE  : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable                         */
12120             __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable                            */
12121             __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable                        */
12122             uint8_t                  : 2;
12123         } VBTWCH1OTSR_b;
12124     };
12125 
12126     union
12127     {
12128         __IOM uint8_t VBTWCH2OTSR;        /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register          */
12129 
12130         struct
12131         {
12132             __IOM uint8_t CH2VCH0TE  : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable                            */
12133             __IOM uint8_t CH2VCH1TE  : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable                            */
12134             uint8_t                  : 1;
12135             __IOM uint8_t CH2VRTCTE  : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable                         */
12136             __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable                            */
12137             __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable                        */
12138             uint8_t                  : 2;
12139         } VBTWCH2OTSR_b;
12140     };
12141 
12142     union
12143     {
12144         __IOM uint8_t VBTICTLR;         /*!< (@ 0x000004BB) VBATT Input Control Register                               */
12145 
12146         struct
12147         {
12148             __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
12149             __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
12150             __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
12151             uint8_t                : 5;
12152         } VBTICTLR_b;
12153     };
12154 
12155     union
12156     {
12157         __IOM uint8_t VBTOCTLR;          /*!< (@ 0x000004BC) VBATT Output Control Register                              */
12158 
12159         struct
12160         {
12161             __IOM uint8_t VCH0OEN   : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable                                   */
12162             __IOM uint8_t VCH1OEN   : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable                                   */
12163             __IOM uint8_t VCH2OEN   : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable                                   */
12164             __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection                          */
12165             __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection                          */
12166             __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection                          */
12167             uint8_t                 : 2;
12168         } VBTOCTLR_b;
12169     };
12170 
12171     union
12172     {
12173         __IOM uint8_t VBTWTER;         /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register                */
12174 
12175         struct
12176         {
12177             __IOM uint8_t VCH0E  : 1;  /*!< [0..0] VBATWIO0 Pin Enable                                                */
12178             __IOM uint8_t VCH1E  : 1;  /*!< [1..1] VBATWIO1 Pin Enable                                                */
12179             __IOM uint8_t VCH2E  : 1;  /*!< [2..2] VBATWIO2 Pin Enable                                                */
12180             __IOM uint8_t VRTCIE : 1;  /*!< [3..3] RTC Periodic Signal Enable                                         */
12181             __IOM uint8_t VRTCAE : 1;  /*!< [4..4] RTC Alarm Signal Enable                                            */
12182             __IOM uint8_t VAGTUE : 1;  /*!< [5..5] AGT(ch1) underflow Signal Enable                                   */
12183             uint8_t              : 2;
12184         } VBTWTER_b;
12185     };
12186 
12187     union
12188     {
12189         __IOM uint8_t VBTWEGR;         /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register                  */
12190 
12191         struct
12192         {
12193             __IOM uint8_t VCH0EG : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select                         */
12194             __IOM uint8_t VCH1EG : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select                         */
12195             __IOM uint8_t VCH2EG : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select                         */
12196             uint8_t              : 5;
12197         } VBTWEGR_b;
12198     };
12199 
12200     union
12201     {
12202         __IOM uint8_t VBTWFR;          /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register                  */
12203 
12204         struct
12205         {
12206             __IOM uint8_t VCH0F  : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Flag                                       */
12207             __IOM uint8_t VCH1F  : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Flag                                       */
12208             __IOM uint8_t VCH2F  : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Flag                                       */
12209             __IOM uint8_t VRTCIF : 1;  /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag                             */
12210             __IOM uint8_t VRTCAF : 1;  /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag                                */
12211             __IOM uint8_t VAGTUF : 1;  /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag                       */
12212             uint8_t              : 2;
12213         } VBTWFR_b;
12214     };
12215 
12216     union
12217     {
12218         __IOM uint8_t VBTBER;          /*!< (@ 0x000004C0) VBATT Backup Enable Register                               */
12219 
12220         struct
12221         {
12222             uint8_t            : 3;
12223             __IOM uint8_t VBAE : 1;    /*!< [3..3] VBATT backup register access enable bit                            */
12224             uint8_t            : 4;
12225         } VBTBER_b;
12226     };
12227     __IM uint8_t  RESERVED59;
12228     __IM uint16_t RESERVED60;
12229     __IM uint32_t RESERVED61[15];
12230 
12231     union
12232     {
12233         __IOM uint8_t VBTBKR[512];     /*!< (@ 0x00000500) VBATT Backup Register [0..511]                             */
12234 
12235         struct
12236         {
12237             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
12238                                         *   data powered by VBATT.The value of this register is retained
12239                                         *   even when VCC is not powered but VBATT is powered.VBTBKR
12240                                         *   is initialized by VBATT selected voltage power-on-reset.                  */
12241         } VBTBKR_b[512];
12242     };
12243 } R_SYSTEM_Type;                       /*!< Size = 1792 (0x700)                                                       */
12244 
12245 /* =========================================================================================================================== */
12246 /* ================                                          R_TRNG                                           ================ */
12247 /* =========================================================================================================================== */
12248 
12249 /**
12250  * @brief True Random Number Generator (R_TRNG)
12251  */
12252 
12253 typedef struct                         /*!< (@ 0x400D1000) R_TRNG Structure                                           */
12254 {
12255     union
12256     {
12257         __IM uint8_t TRNGSDR;          /*!< (@ 0x00000000) TRNG SEED Data Register                                    */
12258 
12259         struct
12260         {
12261             __IM uint8_t SDATA : 8;    /*!< [7..0] When RDRDY bit is 1, these bits hold the generated SEED.
12262                                         *   When RDRDY bit is 0, these bits are read as 00h.The SEED
12263                                         *   is generated as 32-bit data. When TRNGSDR is read 4 times
12264                                         *   while RDRDY = 1, SEED reading is completed and RDRDY bit
12265                                         *   changes to 0                                                              */
12266         } TRNGSDR_b;
12267     };
12268     __IM uint8_t RESERVED;
12269 
12270     union
12271     {
12272         __IOM uint8_t TRNGSCR0;        /*!< (@ 0x00000002) TRNG SEED Command Register 0                               */
12273 
12274         struct
12275         {
12276             uint8_t               : 2;
12277             __OM uint8_t  SGSTART : 1; /*!< [2..2] SEED Generation Start                                              */
12278             __IOM uint8_t SGCEN   : 1; /*!< [3..3] SEED Generation Circuit Enable                                     */
12279             uint8_t               : 3;
12280             __IM uint8_t RDRDY    : 1; /*!< [7..7] When SEED geenration is completed, this bit changes to
12281                                         *   0                                                                         */
12282         } TRNGSCR0_b;
12283     };
12284 
12285     union
12286     {
12287         __IOM uint8_t TRNGSCR1;        /*!< (@ 0x00000003) TRNG SEED Command Register 1                               */
12288 
12289         struct
12290         {
12291             __IOM uint8_t INTEN : 1;   /*!< [0..0] TRNG Interrupt Enable                                              */
12292             uint8_t             : 7;
12293         } TRNGSCR1_b;
12294     };
12295 } R_TRNG_Type;                         /*!< Size = 4 (0x4)                                                            */
12296 
12297 /* =========================================================================================================================== */
12298 /* ================                                           R_TSN                                           ================ */
12299 /* =========================================================================================================================== */
12300 
12301 /**
12302  * @brief Temperature Sensor (R_TSN)
12303  */
12304 
12305 typedef struct                         /*!< (@ 0x407EC000) R_TSN Structure                                            */
12306 {
12307     __IM uint16_t RESERVED[276];
12308 
12309     union
12310     {
12311         __IM uint16_t TSCDR;           /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register               */
12312 
12313         struct
12314         {
12315             union
12316             {
12317                 __IM uint8_t TSCDRL;         /*!< (@ 0x00000228) Temperature Sensor Calibration Data Register
12318                                               *                  L                                                          */
12319 
12320                 struct
12321                 {
12322                     __IM uint8_t TSCDRL : 8; /*!< [7..0] The calibration data stores the lower 8 bits of the convertedvalue. */
12323                 } TSCDRL_b;
12324             };
12325 
12326             union
12327             {
12328                 __IM uint8_t TSCDRH;         /*!< (@ 0x00000229) Temperature Sensor Calibration Data Register
12329                                               *                  H                                                          */
12330 
12331                 struct
12332                 {
12333                     __IM uint8_t TSCDRH : 8; /*!< [7..0] The calibration data stores the higher 8 bits of the
12334                                               *   convertedvalue.                                                           */
12335                 } TSCDRH_b;
12336             };
12337         };
12338     };
12339 } R_TSN_Type;                          /*!< Size = 554 (0x22a)                                                        */
12340 
12341 /* =========================================================================================================================== */
12342 /* ================                                         R_USB_FS0                                         ================ */
12343 /* =========================================================================================================================== */
12344 
12345 /**
12346  * @brief USB 2.0 Module (R_USB_FS0)
12347  */
12348 
12349 typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
12350 {
12351     union
12352     {
12353         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
12354 
12355         struct
12356         {
12357             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
12358             uint16_t             : 2;
12359             __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
12360             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
12361             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
12362             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
12363             uint16_t             : 1;
12364             __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
12365             uint16_t             : 1;
12366             __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
12367             uint16_t             : 5;
12368         } SYSCFG_b;
12369     };
12370 
12371     union
12372     {
12373         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
12374 
12375         struct
12376         {
12377             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
12378                                         *   access cycles)                                                            */
12379             uint16_t : 12;
12380         } BUSWAIT_b;
12381     };
12382 
12383     union
12384     {
12385         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
12386 
12387         struct
12388         {
12389             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
12390             __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
12391             uint16_t            : 2;
12392             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
12393                                         *   Selected.                                                                 */
12394             __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
12395             uint16_t             : 7;
12396             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
12397                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
12398                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
12399                                         *   pin.                                                                      */
12400         } SYSSTS0_b;
12401     };
12402 
12403     union
12404     {
12405         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
12406 
12407         struct
12408         {
12409             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
12410             uint16_t              : 15;
12411         } PLLSTA_b;
12412     };
12413 
12414     union
12415     {
12416         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
12417 
12418         struct
12419         {
12420             __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
12421             uint16_t               : 1;
12422             __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
12423             __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
12424             __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
12425             __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
12426             __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
12427             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
12428             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
12429             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
12430                                          *   used when switching from device B to device A while in
12431                                          *   OTG mode. If the HNPBTOA bit is 1, the internal function
12432                                          *   control keeps the suspended state until the HNP processing
12433                                          *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
12434                                          *   set.                                                                      */
12435             uint16_t : 4;
12436         } DVSTCTR0_b;
12437     };
12438     __IM uint16_t RESERVED;
12439 
12440     union
12441     {
12442         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
12443 
12444         struct
12445         {
12446             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
12447             uint16_t            : 12;
12448         } TESTMODE_b;
12449     };
12450     __IM uint16_t RESERVED1;
12451     __IM uint32_t RESERVED2;
12452 
12453     union
12454     {
12455         __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
12456 
12457         struct
12458         {
12459             union
12460             {
12461                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
12462                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
12463             };
12464 
12465             union
12466             {
12467                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
12468 
12469                 struct
12470                 {
12471                     __IM uint8_t  RESERVED3;
12472                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
12473                 };
12474             };
12475         };
12476     };
12477 
12478     union
12479     {
12480         __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
12481 
12482         struct
12483         {
12484             union
12485             {
12486                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
12487                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
12488             };
12489 
12490             union
12491             {
12492                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
12493 
12494                 struct
12495                 {
12496                     __IM uint8_t  RESERVED4;
12497                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
12498                 };
12499             };
12500         };
12501     };
12502 
12503     union
12504     {
12505         __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
12506 
12507         struct
12508         {
12509             union
12510             {
12511                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
12512                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
12513             };
12514 
12515             union
12516             {
12517                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
12518 
12519                 struct
12520                 {
12521                     __IM uint8_t  RESERVED5;
12522                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
12523                 };
12524             };
12525         };
12526     };
12527 
12528     union
12529     {
12530         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
12531 
12532         struct
12533         {
12534             __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
12535             uint16_t               : 1;
12536             __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
12537             uint16_t               : 2;
12538             __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
12539             uint16_t               : 1;
12540             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
12541             uint16_t               : 2;
12542             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
12543             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
12544         } CFIFOSEL_b;
12545     };
12546 
12547     union
12548     {
12549         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
12550 
12551         struct
12552         {
12553             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
12554                                         *   data.                                                                     */
12555             uint16_t            : 1;
12556             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
12557             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
12558             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
12559         } CFIFOCTR_b;
12560     };
12561     __IM uint32_t RESERVED6;
12562 
12563     union
12564     {
12565         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
12566 
12567         struct
12568         {
12569             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
12570             uint16_t               : 4;
12571             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
12572             uint16_t               : 1;
12573             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
12574             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
12575             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
12576                                          *   Pipe Data is Read                                                         */
12577             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
12578             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
12579         } D0FIFOSEL_b;
12580     };
12581 
12582     union
12583     {
12584         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
12585 
12586         struct
12587         {
12588             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
12589                                         *   data.                                                                     */
12590             uint16_t            : 1;
12591             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
12592             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
12593             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
12594         } D0FIFOCTR_b;
12595     };
12596 
12597     union
12598     {
12599         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
12600 
12601         struct
12602         {
12603             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
12604             uint16_t               : 4;
12605             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
12606             uint16_t               : 1;
12607             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
12608             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
12609             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
12610                                          *   Pipe Data is Read                                                         */
12611             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
12612             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
12613         } D1FIFOSEL_b;
12614     };
12615 
12616     union
12617     {
12618         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
12619 
12620         struct
12621         {
12622             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
12623                                         *   data.                                                                     */
12624             uint16_t            : 1;
12625             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
12626             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
12627             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
12628         } D1FIFOCTR_b;
12629     };
12630 
12631     union
12632     {
12633         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
12634 
12635         struct
12636         {
12637             uint16_t             : 8;
12638             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
12639             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
12640             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
12641             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
12642             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
12643             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
12644             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
12645             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
12646         } INTENB0_b;
12647     };
12648 
12649     union
12650     {
12651         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
12652 
12653         struct
12654         {
12655             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
12656             uint16_t                  : 3;
12657             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
12658             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
12659             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
12660             uint16_t                  : 4;
12661             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
12662             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
12663             uint16_t                  : 1;
12664             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
12665             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
12666         } INTENB1_b;
12667     };
12668     __IM uint16_t RESERVED7;
12669 
12670     union
12671     {
12672         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
12673 
12674         struct
12675         {
12676             __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
12677             __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
12678             __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
12679             __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
12680             __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
12681             __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
12682             __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
12683             __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
12684             __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
12685             __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
12686             uint16_t                  : 6;
12687         } BRDYENB_b;
12688     };
12689 
12690     union
12691     {
12692         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
12693 
12694         struct
12695         {
12696             __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
12697             __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
12698             __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
12699             __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
12700             __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
12701             __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
12702             __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
12703             __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
12704             __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
12705             __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
12706             uint16_t                  : 6;
12707         } NRDYENB_b;
12708     };
12709 
12710     union
12711     {
12712         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
12713 
12714         struct
12715         {
12716             __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
12717             __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
12718             __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
12719             __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
12720             __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
12721             __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
12722             __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
12723             __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
12724             __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
12725             __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
12726             uint16_t                  : 6;
12727         } BEMPENB_b;
12728     };
12729 
12730     union
12731     {
12732         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
12733 
12734         struct
12735         {
12736             uint16_t                : 4;
12737             __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
12738             __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
12739             __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
12740             uint16_t                : 1;
12741             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
12742             uint16_t                : 7;
12743         } SOFCFG_b;
12744     };
12745 
12746     union
12747     {
12748         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
12749 
12750         struct
12751         {
12752             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
12753             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
12754             uint16_t                : 1;
12755             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
12756             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
12757             uint16_t                : 2;
12758             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
12759             uint16_t                : 1;
12760             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
12761             uint16_t                : 3;
12762             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
12763         } PHYSET_b;
12764     };
12765 
12766     union
12767     {
12768         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
12769 
12770         struct
12771         {
12772             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
12773             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
12774             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
12775             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
12776             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
12777             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
12778             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
12779             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
12780             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
12781             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
12782             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
12783             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
12784         } INTSTS0_b;
12785     };
12786 
12787     union
12788     {
12789         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
12790 
12791         struct
12792         {
12793             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
12794             uint16_t                 : 3;
12795             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
12796             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
12797             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
12798             uint16_t                 : 1;
12799             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
12800             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
12801             uint16_t                 : 1;
12802             __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
12803             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
12804             uint16_t                 : 1;
12805             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
12806             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
12807         } INTSTS1_b;
12808     };
12809     __IM uint16_t RESERVED8;
12810 
12811     union
12812     {
12813         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
12814 
12815         struct
12816         {
12817             __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
12818             __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
12819             __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
12820             __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
12821             __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
12822             __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
12823             __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
12824             __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
12825             __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
12826             __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
12827             uint16_t                 : 6;
12828         } BRDYSTS_b;
12829     };
12830 
12831     union
12832     {
12833         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
12834 
12835         struct
12836         {
12837             __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
12838             __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
12839             __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
12840             __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
12841             __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
12842             __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
12843             __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
12844             __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
12845             __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
12846             __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
12847             uint16_t                 : 6;
12848         } NRDYSTS_b;
12849     };
12850 
12851     union
12852     {
12853         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
12854 
12855         struct
12856         {
12857             __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
12858             __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
12859             __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
12860             __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
12861             __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
12862             __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
12863             __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
12864             __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
12865             __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
12866             __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
12867             uint16_t                 : 6;
12868         } BEMPSTS_b;
12869     };
12870 
12871     union
12872     {
12873         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
12874 
12875         struct
12876         {
12877             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
12878             uint16_t            : 3;
12879             __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
12880             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
12881         } FRMNUM_b;
12882     };
12883 
12884     union
12885     {
12886         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
12887 
12888         struct
12889         {
12890             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
12891             uint16_t             : 12;
12892             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
12893         } UFRMNUM_b;
12894     };
12895 
12896     union
12897     {
12898         __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
12899 
12900         struct
12901         {
12902             __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
12903                                            *   the USB address assigned by the host when the USBHS processed
12904                                            *   the SET_ADDRESS request successfully.                                     */
12905             uint16_t                 : 1;
12906             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
12907             uint16_t                 : 5;
12908         } USBADDR_b;
12909     };
12910     __IM uint16_t RESERVED9;
12911 
12912     union
12913     {
12914         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
12915 
12916         struct
12917         {
12918             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
12919                                                *   value.                                                                    */
12920             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
12921         } USBREQ_b;
12922     };
12923 
12924     union
12925     {
12926         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
12927 
12928         struct
12929         {
12930             __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
12931         } USBVAL_b;
12932     };
12933 
12934     union
12935     {
12936         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
12937 
12938         struct
12939         {
12940             __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
12941         } USBINDX_b;
12942     };
12943 
12944     union
12945     {
12946         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
12947 
12948         struct
12949         {
12950             __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
12951         } USBLENG_b;
12952     };
12953 
12954     union
12955     {
12956         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
12957 
12958         struct
12959         {
12960             uint16_t              : 4;
12961             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
12962             uint16_t              : 2;
12963             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
12964             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
12965             uint16_t              : 7;
12966         } DCPCFG_b;
12967     };
12968 
12969     union
12970     {
12971         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
12972 
12973         struct
12974         {
12975             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
12976                                         *   of data (maximum packet size) in payloads for the DCP.                    */
12977             uint16_t              : 5;
12978             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
12979         } DCPMAXP_b;
12980     };
12981 
12982     union
12983     {
12984         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
12985 
12986         struct
12987         {
12988             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
12989             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
12990             uint16_t                : 2;
12991             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
12992             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
12993             __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
12994             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
12995             uint16_t                : 2;
12996             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
12997             uint16_t                : 2;
12998             __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
12999             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
13000         } DCPCTR_b;
13001     };
13002     __IM uint16_t RESERVED10;
13003 
13004     union
13005     {
13006         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
13007 
13008         struct
13009         {
13010             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
13011             uint16_t               : 12;
13012         } PIPESEL_b;
13013     };
13014     __IM uint16_t RESERVED11;
13015 
13016     union
13017     {
13018         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
13019 
13020         struct
13021         {
13022             __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
13023                                         *   for the selected pipe.Setting 0000b means unused pipe.                    */
13024             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
13025             uint16_t              : 2;
13026             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
13027             uint16_t              : 1;
13028             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
13029             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
13030             uint16_t              : 3;
13031             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
13032         } PIPECFG_b;
13033     };
13034     __IM uint16_t RESERVED12;
13035 
13036     union
13037     {
13038         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
13039 
13040         struct
13041         {
13042             __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
13043                                         *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
13044                                         *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
13045                                         *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
13046                                         *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
13047             uint16_t              : 3;
13048             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
13049         } PIPEMAXP_b;
13050     };
13051 
13052     union
13053     {
13054         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
13055 
13056         struct
13057         {
13058             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
13059                                         *   error detection timing for the selected pipe in terms of
13060                                         *   frames, which is expressed as nth power of 2.                             */
13061             uint16_t            : 9;
13062             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
13063             uint16_t            : 3;
13064         } PIPEPERI_b;
13065     };
13066 
13067     union
13068     {
13069         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
13070 
13071         struct
13072         {
13073             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
13074             uint16_t              : 3;
13075             __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
13076             __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
13077             __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
13078             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
13079             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
13080             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
13081             uint16_t              : 1;
13082             __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
13083                                         *   Split Transaction of the relevant pipe                                    */
13084             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
13085                                         *   the CSSTS bit of the relevant pipe                                        */
13086             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
13087             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
13088         } PIPE_CTR_b[9];
13089     };
13090     __IM uint16_t                RESERVED13;
13091     __IM uint32_t                RESERVED14[3];
13092     __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
13093     __IM uint32_t                RESERVED15[3];
13094 
13095     union
13096     {
13097         __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
13098 
13099         struct
13100         {
13101             __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
13102             __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
13103             __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
13104             __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
13105             __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
13106             __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
13107             uint16_t                  : 1;
13108             __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
13109             __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
13110             __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
13111             uint16_t                  : 6;
13112         } USBBCCTRL0_b;
13113     };
13114     __IM uint16_t RESERVED16;
13115     __IM uint32_t RESERVED17[4];
13116 
13117     union
13118     {
13119         __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
13120 
13121         struct
13122         {
13123             __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
13124             uint16_t               : 15;
13125         } UCKSEL_b;
13126     };
13127     __IM uint16_t RESERVED18;
13128     __IM uint32_t RESERVED19;
13129 
13130     union
13131     {
13132         __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
13133 
13134         struct
13135         {
13136             __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
13137             uint16_t               : 6;
13138             __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
13139             uint16_t               : 8;
13140         } USBMC_b;
13141     };
13142     __IM uint16_t RESERVED20;
13143 
13144     union
13145     {
13146         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
13147 
13148         struct
13149         {
13150             uint16_t               : 6;
13151             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
13152             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
13153             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
13154             uint16_t               : 1;
13155         } DEVADD_b[10];
13156     };
13157     __IM uint32_t RESERVED21[3];
13158 
13159     union
13160     {
13161         __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
13162 
13163         struct
13164         {
13165             __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
13166             __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
13167             __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
13168             __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
13169             uint32_t               : 28;
13170         } PHYSLEW_b;
13171     };
13172     __IM uint32_t RESERVED22[3];
13173 
13174     union
13175     {
13176         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
13177 
13178         struct
13179         {
13180             uint16_t             : 7;
13181             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
13182             uint16_t             : 8;
13183         } LPCTRL_b;
13184     };
13185 
13186     union
13187     {
13188         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
13189 
13190         struct
13191         {
13192             uint16_t                : 14;
13193             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
13194             uint16_t                : 1;
13195         } LPSTS_b;
13196     };
13197     __IM uint32_t RESERVED23[15];
13198 
13199     union
13200     {
13201         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
13202 
13203         struct
13204         {
13205             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
13206             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
13207             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
13208             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
13209             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
13210             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
13211             uint16_t                : 2;
13212             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
13213             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
13214             uint16_t                : 6;
13215         } BCCTRL_b;
13216     };
13217     __IM uint16_t RESERVED24;
13218 
13219     union
13220     {
13221         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
13222 
13223         struct
13224         {
13225             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
13226             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
13227             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
13228                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
13229             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
13230                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
13231             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
13232                                           *   value used for L1NEGOMD.The format is the same as the HIRD
13233                                           *   field in HL1CTRL.                                                         */
13234             uint16_t               : 2;
13235             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
13236             uint16_t               : 1;
13237         } PL1CTRL1_b;
13238     };
13239 
13240     union
13241     {
13242         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
13243 
13244         struct
13245         {
13246             uint16_t               : 8;
13247             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
13248             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
13249             uint16_t               : 3;
13250         } PL1CTRL2_b;
13251     };
13252 
13253     union
13254     {
13255         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
13256 
13257         struct
13258         {
13259             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
13260             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
13261             uint16_t                : 13;
13262         } HL1CTRL1_b;
13263     };
13264 
13265     union
13266     {
13267         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
13268 
13269         struct
13270         {
13271             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
13272                                         *   be set in the ADDR field of LPM token.                                    */
13273             uint16_t             : 4;
13274             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
13275             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
13276                                         *   value to be set in the RWE field of LPM token.                            */
13277             uint16_t            : 2;
13278             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
13279                                         *   period at the time of L1 Resume.                                          */
13280         } HL1CTRL2_b;
13281     };
13282     __IM uint32_t RESERVED25[5];
13283 
13284     union
13285     {
13286         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
13287                                         *                  Register                                                   */
13288 
13289         struct
13290         {
13291             uint32_t              : 20;
13292             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
13293                                          *   HS side of USB port.                                                      */
13294             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
13295                                          *   HS side of USB port.                                                      */
13296             uint32_t               : 1;
13297             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
13298                                          *   of USB port.                                                              */
13299             uint32_t : 8;
13300         } DPUSR0R_b;
13301     };
13302 
13303     union
13304     {
13305         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
13306 
13307         struct
13308         {
13309             uint32_t                : 4;
13310             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
13311             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
13312             uint32_t                : 1;
13313             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
13314             uint32_t                : 12;
13315             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
13316             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
13317             uint32_t                : 1;
13318             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
13319             uint32_t                : 8;
13320         } DPUSR1R_b;
13321     };
13322 
13323     union
13324     {
13325         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
13326 
13327         struct
13328         {
13329             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
13330             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
13331             uint16_t            : 2;
13332             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
13333                                         *   port.                                                                     */
13334             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
13335                                         *   port.                                                                     */
13336             uint16_t              : 2;
13337             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
13338             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
13339             uint16_t              : 6;
13340         } DPUSR2R_b;
13341     };
13342 
13343     union
13344     {
13345         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
13346 
13347         struct
13348         {
13349             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
13350             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
13351             uint16_t                : 14;
13352         } DPUSRCR_b;
13353     };
13354     __IM uint32_t RESERVED26[165];
13355 
13356     union
13357     {
13358         __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
13359                                          *                  Monitor Register                                           */
13360 
13361         struct
13362         {
13363             __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
13364             __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
13365             uint32_t               : 1;
13366             __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
13367             __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
13368             uint32_t               : 11;
13369             __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
13370             __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
13371             uint32_t               : 2;
13372             __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
13373                                          *   of the USB.                                                               */
13374             __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
13375                                          *   of the USB.                                                               */
13376             uint32_t              : 1;
13377             __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
13378                                          *   USB.                                                                      */
13379             uint32_t : 8;
13380         } DPUSR0R_FS_b;
13381     };
13382 
13383     union
13384     {
13385         __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
13386                                            *                  Register                                                   */
13387 
13388         struct
13389         {
13390             __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
13391             __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
13392             uint32_t                 : 2;
13393             __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
13394             __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
13395             uint32_t                 : 1;
13396             __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
13397             uint32_t                 : 8;
13398             __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
13399             __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
13400             uint32_t                 : 2;
13401             __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
13402             __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
13403             uint32_t                 : 1;
13404             __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
13405             uint32_t                 : 8;
13406         } DPUSR1R_FS_b;
13407     };
13408 } R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
13409 
13410 /* =========================================================================================================================== */
13411 /* ================                                           R_WDT                                           ================ */
13412 /* =========================================================================================================================== */
13413 
13414 /**
13415  * @brief Watchdog Timer (R_WDT)
13416  */
13417 
13418 typedef struct                         /*!< (@ 0x40044200) R_WDT Structure                                            */
13419 {
13420     union
13421     {
13422         __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
13423 
13424         struct
13425         {
13426             __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
13427                                         *   of the WDT.                                                               */
13428         } WDTRR_b;
13429     };
13430     __IM uint8_t RESERVED;
13431 
13432     union
13433     {
13434         __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
13435 
13436         struct
13437         {
13438             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
13439             uint16_t            : 2;
13440             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
13441             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
13442             uint16_t            : 2;
13443             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
13444             uint16_t            : 2;
13445         } WDTCR_b;
13446     };
13447 
13448     union
13449     {
13450         __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
13451 
13452         struct
13453         {
13454             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
13455             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
13456             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
13457         } WDTSR_b;
13458     };
13459 
13460     union
13461     {
13462         __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
13463 
13464         struct
13465         {
13466             uint8_t               : 7;
13467             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
13468         } WDTRCR_b;
13469     };
13470     __IM uint8_t RESERVED1;
13471 
13472     union
13473     {
13474         __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
13475 
13476         struct
13477         {
13478             uint8_t              : 7;
13479             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
13480         } WDTCSTPR_b;
13481     };
13482     __IM uint8_t  RESERVED2;
13483     __IM uint16_t RESERVED3;
13484 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
13485 
13486 /* =========================================================================================================================== */
13487 /* ================                                           R_AES                                           ================ */
13488 /* =========================================================================================================================== */
13489 
13490 /**
13491  * @brief AES Engine (R_AES)
13492  */
13493 
13494 typedef struct                         /*!< (@ 0x400D0000) R_AES Structure                                            */
13495 {
13496     union
13497     {
13498         __IOM uint16_t AESMOD;         /*!< (@ 0x00000000) AES Mode Register                                          */
13499 
13500         struct
13501         {
13502             __IOM uint16_t MODEN  : 1; /*!< [0..0] Read Request Enable                                                */
13503             uint16_t              : 7;
13504             __IOM uint16_t RDRQEN : 1; /*!< [8..8] Read Request Enable                                                */
13505             __IOM uint16_t WRRQEN : 1; /*!< [9..9] Write Request Enable                                               */
13506             uint16_t              : 6;
13507         } AESMOD_b;
13508     };
13509     __IM uint16_t RESERVED;
13510 
13511     union
13512     {
13513         __IOM uint32_t AESCMD;           /*!< (@ 0x00000004) AES Command Register                                       */
13514 
13515         struct
13516         {
13517             __IOM uint32_t INVCIP   : 1; /*!< [0..0] Select data encryption/decryption                                  */
13518             __IOM uint32_t KEYLN    : 1; /*!< [1..1] Select the Key Length                                              */
13519             uint32_t                : 2;
13520             __IOM uint32_t CHAIN    : 2; /*!< [5..4] Select the chaining mode                                           */
13521             uint32_t                : 2;
13522             __IOM uint32_t STORESEL : 2; /*!< [9..8] Read Request Enable                                                */
13523             uint32_t                : 2;
13524             __IOM uint32_t KEYSEL   : 1; /*!< [12..12] Select the Key Register                                          */
13525             uint32_t                : 11;
13526             __IM uint32_t DWRDY     : 1; /*!< [24..24] This bit indicates that AESDW is ready to write or
13527                                           *   is writing                                                                */
13528             __IM uint32_t DRRDY : 1;     /*!< [25..25] This bit indicates that AESDW is ready to read or is
13529                                           *   reading                                                                   */
13530             __IM uint32_t CWRDY : 1;     /*!< [26..26] This bit indicates that AESCMD is ready to write                 */
13531             __IM uint32_t IWRDY : 1;     /*!< [27..27] This bit indicates that AESIVW is ready to write or
13532                                           *   is writing                                                                */
13533             __IM uint32_t IRRDY : 1;     /*!< [28..28] This bit indicates that AESIVW is ready to read or
13534                                           *   is reading                                                                */
13535             __IM uint32_t KWRDY0 : 1;    /*!< [29..29] This bit indicates that AESKW0 is ready to write or
13536                                           *   is writing                                                                */
13537             __IM uint32_t KWRDY1 : 1;    /*!< [30..30] This bit indicates that AESKW1 is ready to write or
13538                                           *   is writing                                                                */
13539             __IM uint32_t ILOP : 1;      /*!< [31..31] This bit shows that the relation of Key Register 0
13540                                           *   and Key Register1 is not correct (for 256-bit key-length)                 */
13541         } AESCMD_b;
13542     };
13543     __IOM uint32_t AESDW;                /*!< (@ 0x00000008) AES Data Window Register                                   */
13544     __IOM uint32_t AESIVW;               /*!< (@ 0x0000000C) AES IV Window Register                                     */
13545     __IOM uint32_t AESKW0;               /*!< (@ 0x00000010) AES Key Window 0 Register                                  */
13546     __IOM uint32_t AESKW1;               /*!< (@ 0x00000014) AES Key Window 1 Register                                  */
13547 } R_AES_Type;                            /*!< Size = 24 (0x18)                                                          */
13548 
13549 /* =========================================================================================================================== */
13550 /* ================                                          R_AGTX0                                          ================ */
13551 /* =========================================================================================================================== */
13552 
13553 /**
13554  * @brief Asynchronous General Purpose Timer (R_AGTX0)
13555  */
13556 
13557 typedef struct                          /*!< (@ 0x40084000) R_AGTX0 Structure                                          */
13558 {
13559     union
13560     {
13561         __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
13562         __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
13563     };
13564 } R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
13565 
13566 /** @} */ /* End of group Device_Peripheral_peripherals */
13567 
13568 /* =========================================================================================================================== */
13569 /* ================                          Device Specific Peripheral Address Map                           ================ */
13570 /* =========================================================================================================================== */
13571 
13572 /** @addtogroup Device_Peripheral_peripheralAddr
13573  * @{
13574  */
13575 
13576  #define R_ACMPHS0_BASE      0x40085000UL
13577  #define R_ACMPHS1_BASE      0x40085100UL
13578  #define R_ACMPHS2_BASE      0x40085200UL
13579  #define R_ACMPHS3_BASE      0x40085300UL
13580  #define R_ACMPHS4_BASE      0x40085400UL
13581  #define R_ACMPHS5_BASE      0x40085500UL
13582  #define R_ACMPLP_BASE       0x40085E00UL
13583  #define R_ADC0_BASE         0x4005C000UL
13584  #define R_ADC1_BASE         0x4005C200UL
13585  #define R_BUS_BASE          0x40003000UL
13586  #define R_CAC_BASE          0x40044600UL
13587  #define R_CAN0_BASE         0x40050000UL
13588  #define R_CAN1_BASE         0x40051000UL
13589  #define R_CRC_BASE          0x40074000UL
13590  #define R_CTSU_BASE         0x40081000UL
13591  #define R_DAC_BASE          0x4005E000UL
13592  #define R_DAC8_BASE         0x4009E000UL
13593  #define R_DEBUG_BASE        0x4001B000UL
13594  #define R_DOC_BASE          0x40054100UL
13595  #define R_DTC_BASE          0x40005400UL
13596  #define R_ELC_BASE          0x40041000UL
13597  #define R_FACI_LP_BASE      0x407EC000UL
13598  #define R_FCACHE_BASE       0x4001C000UL
13599  #define R_GPT0_BASE         0x40078000UL
13600  #define R_GPT1_BASE         0x40078100UL
13601  #define R_GPT2_BASE         0x40078200UL
13602  #define R_GPT3_BASE         0x40078300UL
13603  #define R_GPT4_BASE         0x40078400UL
13604  #define R_GPT5_BASE         0x40078500UL
13605  #define R_GPT6_BASE         0x40078600UL
13606  #define R_GPT7_BASE         0x40078700UL
13607  #define R_GPT8_BASE         0x40078800UL
13608  #define R_GPT9_BASE         0x40078900UL
13609  #define R_GPT10_BASE        0x40078A00UL
13610  #define R_GPT11_BASE        0x40078B00UL
13611  #define R_GPT12_BASE        0x40078C00UL
13612  #define R_GPT13_BASE        0x40078D00UL
13613  #define R_GPT_OPS_BASE      0x40078FF0UL
13614  #define R_GPT_POEG0_BASE    0x40042000UL
13615  #define R_GPT_POEG1_BASE    0x40042100UL
13616  #define R_GPT_POEG2_BASE    0x40042200UL
13617  #define R_GPT_POEG3_BASE    0x40042300UL
13618  #define R_ICU_BASE          0x40006000UL
13619  #define R_IIC0_BASE         0x40053000UL
13620  #define R_IIC1_BASE         0x40053100UL
13621  #define R_IIC2_BASE         0x40053200UL
13622  #define R_IWDT_BASE         0x40044400UL
13623  #define R_KINT_BASE         0x40080000UL
13624  #define R_MMF_BASE          0x40001000UL
13625  #define R_MPU_MMPU_BASE     0x40000000UL
13626  #define R_MPU_SMPU_BASE     0x40000C00UL
13627  #define R_MPU_SPMON_BASE    0x40000D00UL
13628  #define R_MSTP_BASE         (0x40047000UL - 4UL) /* MSTPCRA is not located in R_MSTP so the base address must be moved so that MSTPCRB is located at 0x40047000. */
13629  #define R_OPAMP_BASE        0x400867F8UL
13630  #define R_PORT0_BASE        0x40040000UL
13631  #define R_PORT1_BASE        0x40040020UL
13632  #define R_PORT2_BASE        0x40040040UL
13633  #define R_PORT3_BASE        0x40040060UL
13634  #define R_PORT4_BASE        0x40040080UL
13635  #define R_PORT5_BASE        0x400400A0UL
13636  #define R_PORT6_BASE        0x400400C0UL
13637  #define R_PORT7_BASE        0x400400E0UL
13638  #define R_PORT8_BASE        0x40040100UL
13639  #define R_PORT9_BASE        0x40040120UL
13640  #define R_PORT10_BASE       0x40040140UL
13641  #define R_PORT11_BASE       0x40040160UL
13642  #define R_PORT12_BASE       0x40040180UL
13643  #define R_PORT13_BASE       0x400401A0UL
13644  #define R_PORT14_BASE       0x400401C0UL
13645  #define R_PFS_BASE          0x40040800UL
13646  #define R_PMISC_BASE        0x40040D00UL
13647  #define R_RTC_BASE          0x40044000UL
13648  #define R_SCI0_BASE         0x40070000UL
13649  #define R_SCI1_BASE         0x40070020UL
13650  #define R_SCI2_BASE         0x40070040UL
13651  #define R_SCI3_BASE         0x40070060UL
13652  #define R_SCI4_BASE         0x40070080UL
13653  #define R_SCI5_BASE         0x400700A0UL
13654  #define R_SCI6_BASE         0x400700C0UL
13655  #define R_SCI7_BASE         0x400700E0UL
13656  #define R_SCI8_BASE         0x40070100UL
13657  #define R_SCI9_BASE         0x40070120UL
13658  #define R_SDADC0_BASE       0x4009C000UL
13659  #define R_SPI0_BASE         0x40072000UL
13660  #define R_SPI1_BASE         0x40072100UL
13661  #define R_SRAM_BASE         0x40002000UL
13662  #define R_SYSTEM_BASE       0x4001E000UL
13663  #define R_TRNG_BASE         0x400D1000UL
13664  #define R_TSN_BASE          0x407EC000UL
13665  #define R_USB_FS0_BASE      0x40090000UL
13666  #define R_WDT_BASE          0x40044200UL
13667  #define R_AES_BASE          0x400D0000UL
13668  #define R_AGTX0_BASE        0x40084000UL
13669  #define R_AGTX1_BASE        0x40084100UL
13670  #define R_AGTX2_BASE        0x40084200UL
13671  #define R_AGTX3_BASE        0x40084300UL
13672  #define R_AGTX4_BASE        0x40084400UL
13673  #define R_AGTX5_BASE        0x40084500UL
13674  #define R_AGTX6_BASE        0x40084600UL
13675  #define R_AGTX7_BASE        0x40084700UL
13676  #define R_AGTX8_BASE        0x40084800UL
13677  #define R_AGTX9_BASE        0x40084900UL
13678 
13679 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
13680 
13681 /* =========================================================================================================================== */
13682 /* ================                                  Peripheral declaration                                   ================ */
13683 /* =========================================================================================================================== */
13684 
13685 /** @addtogroup Device_Peripheral_declaration
13686  * @{
13687  */
13688 
13689  #define R_ACMPHS0      ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
13690  #define R_ACMPHS1      ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
13691  #define R_ACMPHS2      ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
13692  #define R_ACMPHS3      ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
13693  #define R_ACMPHS4      ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
13694  #define R_ACMPHS5      ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
13695  #define R_ACMPLP       ((R_ACMPLP_Type *) R_ACMPLP_BASE)
13696  #define R_ADC0         ((R_ADC0_Type *) R_ADC0_BASE)
13697  #define R_ADC1         ((R_ADC0_Type *) R_ADC1_BASE)
13698  #define R_BUS          ((R_BUS_Type *) R_BUS_BASE)
13699  #define R_CAC          ((R_CAC_Type *) R_CAC_BASE)
13700  #define R_CAN0         ((R_CAN0_Type *) R_CAN0_BASE)
13701  #define R_CAN1         ((R_CAN0_Type *) R_CAN1_BASE)
13702  #define R_CRC          ((R_CRC_Type *) R_CRC_BASE)
13703  #define R_CTSU         ((R_CTSU_Type *) R_CTSU_BASE)
13704  #define R_DAC          ((R_DAC_Type *) R_DAC_BASE)
13705  #define R_DAC8         ((R_DAC8_Type *) R_DAC8_BASE)
13706  #define R_DEBUG        ((R_DEBUG_Type *) R_DEBUG_BASE)
13707  #define R_DOC          ((R_DOC_Type *) R_DOC_BASE)
13708  #define R_DTC          ((R_DTC_Type *) R_DTC_BASE)
13709  #define R_ELC          ((R_ELC_Type *) R_ELC_BASE)
13710  #define R_FACI_LP      ((R_FACI_LP_Type *) R_FACI_LP_BASE)
13711  #define R_FCACHE       ((R_FCACHE_Type *) R_FCACHE_BASE)
13712  #define R_GPT0         ((R_GPT0_Type *) R_GPT0_BASE)
13713  #define R_GPT1         ((R_GPT0_Type *) R_GPT1_BASE)
13714  #define R_GPT2         ((R_GPT0_Type *) R_GPT2_BASE)
13715  #define R_GPT3         ((R_GPT0_Type *) R_GPT3_BASE)
13716  #define R_GPT4         ((R_GPT0_Type *) R_GPT4_BASE)
13717  #define R_GPT5         ((R_GPT0_Type *) R_GPT5_BASE)
13718  #define R_GPT6         ((R_GPT0_Type *) R_GPT6_BASE)
13719  #define R_GPT7         ((R_GPT0_Type *) R_GPT7_BASE)
13720  #define R_GPT8         ((R_GPT0_Type *) R_GPT8_BASE)
13721  #define R_GPT9         ((R_GPT0_Type *) R_GPT9_BASE)
13722  #define R_GPT10        ((R_GPT0_Type *) R_GPT10_BASE)
13723  #define R_GPT11        ((R_GPT0_Type *) R_GPT11_BASE)
13724  #define R_GPT12        ((R_GPT0_Type *) R_GPT12_BASE)
13725  #define R_GPT13        ((R_GPT0_Type *) R_GPT13_BASE)
13726  #define R_GPT_OPS      ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
13727  #define R_GPT_POEG0    ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
13728  #define R_GPT_POEG1    ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
13729  #define R_GPT_POEG2    ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
13730  #define R_GPT_POEG3    ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
13731  #define R_ICU          ((R_ICU_Type *) R_ICU_BASE)
13732  #define R_IIC0         ((R_IIC0_Type *) R_IIC0_BASE)
13733  #define R_IIC1         ((R_IIC0_Type *) R_IIC1_BASE)
13734  #define R_IIC2         ((R_IIC0_Type *) R_IIC2_BASE)
13735  #define R_IWDT         ((R_IWDT_Type *) R_IWDT_BASE)
13736  #define R_KINT         ((R_KINT_Type *) R_KINT_BASE)
13737  #define R_MMF          ((R_MMF_Type *) R_MMF_BASE)
13738  #define R_MPU_MMPU     ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
13739  #define R_MPU_SMPU     ((R_MPU_SMPU_Type *) R_MPU_SMPU_BASE)
13740  #define R_MPU_SPMON    ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
13741  #define R_MSTP         ((R_MSTP_Type *) R_MSTP_BASE)
13742  #define R_OPAMP        ((R_OPAMP_Type *) R_OPAMP_BASE)
13743  #define R_PORT0        ((R_PORT0_Type *) R_PORT0_BASE)
13744  #define R_PORT1        ((R_PORT0_Type *) R_PORT1_BASE)
13745  #define R_PORT2        ((R_PORT0_Type *) R_PORT2_BASE)
13746  #define R_PORT3        ((R_PORT0_Type *) R_PORT3_BASE)
13747  #define R_PORT4        ((R_PORT0_Type *) R_PORT4_BASE)
13748  #define R_PORT5        ((R_PORT0_Type *) R_PORT5_BASE)
13749  #define R_PORT6        ((R_PORT0_Type *) R_PORT6_BASE)
13750  #define R_PORT7        ((R_PORT0_Type *) R_PORT7_BASE)
13751  #define R_PORT8        ((R_PORT0_Type *) R_PORT8_BASE)
13752  #define R_PORT9        ((R_PORT0_Type *) R_PORT9_BASE)
13753  #define R_PORT10       ((R_PORT0_Type *) R_PORT10_BASE)
13754  #define R_PORT11       ((R_PORT0_Type *) R_PORT11_BASE)
13755  #define R_PORT12       ((R_PORT0_Type *) R_PORT12_BASE)
13756  #define R_PORT13       ((R_PORT0_Type *) R_PORT13_BASE)
13757  #define R_PORT14       ((R_PORT0_Type *) R_PORT14_BASE)
13758  #define R_PFS          ((R_PFS_Type *) R_PFS_BASE)
13759  #define R_PMISC        ((R_PMISC_Type *) R_PMISC_BASE)
13760  #define R_RTC          ((R_RTC_Type *) R_RTC_BASE)
13761  #define R_SCI0         ((R_SCI0_Type *) R_SCI0_BASE)
13762  #define R_SCI1         ((R_SCI0_Type *) R_SCI1_BASE)
13763  #define R_SCI2         ((R_SCI0_Type *) R_SCI2_BASE)
13764  #define R_SCI3         ((R_SCI0_Type *) R_SCI3_BASE)
13765  #define R_SCI4         ((R_SCI0_Type *) R_SCI4_BASE)
13766  #define R_SCI5         ((R_SCI0_Type *) R_SCI5_BASE)
13767  #define R_SCI6         ((R_SCI0_Type *) R_SCI6_BASE)
13768  #define R_SCI7         ((R_SCI0_Type *) R_SCI7_BASE)
13769  #define R_SCI8         ((R_SCI0_Type *) R_SCI8_BASE)
13770  #define R_SCI9         ((R_SCI0_Type *) R_SCI9_BASE)
13771  #define R_SDADC0       ((R_SDADC0_Type *) R_SDADC0_BASE)
13772  #define R_SPI0         ((R_SPI0_Type *) R_SPI0_BASE)
13773  #define R_SPI1         ((R_SPI0_Type *) R_SPI1_BASE)
13774  #define R_SRAM         ((R_SRAM_Type *) R_SRAM_BASE)
13775  #define R_SYSTEM       ((R_SYSTEM_Type *) R_SYSTEM_BASE)
13776  #define R_TRNG         ((R_TRNG_Type *) R_TRNG_BASE)
13777  #define R_TSN          ((R_TSN_Type *) R_TSN_BASE)
13778  #define R_USB_FS0      ((R_USB_FS0_Type *) R_USB_FS0_BASE)
13779  #define R_WDT          ((R_WDT_Type *) R_WDT_BASE)
13780  #define R_AES          ((R_AES_Type *) R_AES_BASE)
13781  #define R_AGT0         ((R_AGTX0_Type *) R_AGTX0_BASE)
13782  #define R_AGT1         ((R_AGTX0_Type *) R_AGTX1_BASE)
13783  #define R_AGT2         ((R_AGTX0_Type *) R_AGTX2_BASE)
13784  #define R_AGT3         ((R_AGTX0_Type *) R_AGTX3_BASE)
13785  #define R_AGT4         ((R_AGTX0_Type *) R_AGTX4_BASE)
13786  #define R_AGT5         ((R_AGTX0_Type *) R_AGTX5_BASE)
13787  #define R_AGT6         ((R_AGTX0_Type *) R_AGTX6_BASE)
13788  #define R_AGT7         ((R_AGTX0_Type *) R_AGTX7_BASE)
13789  #define R_AGT8         ((R_AGTX0_Type *) R_AGTX8_BASE)
13790  #define R_AGT9         ((R_AGTX0_Type *) R_AGTX9_BASE)
13791 
13792 /** @} */ /* End of group Device_Peripheral_declaration */
13793 
13794 /* =========================================  End of section using anonymous unions  ========================================= */
13795  #if defined(__CC_ARM)
13796   #pragma pop
13797  #elif defined(__ICCARM__)
13798 
13799 /* leave anonymous unions enabled */
13800  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
13801   #pragma clang diagnostic pop
13802  #elif defined(__GNUC__)
13803 
13804 /* anonymous unions are enabled by default */
13805  #elif defined(__TMS470__)
13806 
13807 /* anonymous unions are enabled by default */
13808  #elif defined(__TASKING__)
13809   #pragma warning restore
13810  #elif defined(__CSMC__)
13811 
13812 /* anonymous unions are enabled by default */
13813  #endif
13814 
13815 /* =========================================================================================================================== */
13816 /* ================                                 Pos/Mask Cluster Section                                  ================ */
13817 /* =========================================================================================================================== */
13818 
13819 /** @addtogroup PosMask_clusters
13820  * @{
13821  */
13822 
13823 /* =========================================================================================================================== */
13824 /* ================                                            CSa                                            ================ */
13825 /* =========================================================================================================================== */
13826 
13827 /* ==========================================================  MOD  ========================================================== */
13828  #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
13829  #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
13830  #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
13831  #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
13832  #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
13833  #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
13834  #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
13835  #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
13836  #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
13837  #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
13838 /* =========================================================  WCR1  ========================================================== */
13839  #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
13840  #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
13841  #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
13842  #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
13843  #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
13844  #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
13845  #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
13846  #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
13847 /* =========================================================  WCR2  ========================================================== */
13848  #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
13849  #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
13850  #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
13851  #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
13852  #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
13853  #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
13854  #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
13855  #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
13856  #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
13857  #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
13858  #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
13859  #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
13860  #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
13861  #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
13862  #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
13863  #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
13864 
13865 /* =========================================================================================================================== */
13866 /* ================                                            CSb                                            ================ */
13867 /* =========================================================================================================================== */
13868 
13869 /* ==========================================================  CR  =========================================================== */
13870  #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
13871  #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
13872  #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
13873  #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
13874  #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
13875  #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
13876  #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
13877  #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
13878 /* ==========================================================  REC  ========================================================== */
13879  #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
13880  #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
13881  #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
13882  #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
13883 
13884 /* =========================================================================================================================== */
13885 /* ================                                           SDRAM                                           ================ */
13886 /* =========================================================================================================================== */
13887 
13888 /* =========================================================  SDCCR  ========================================================= */
13889  #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
13890  #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
13891  #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
13892  #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
13893 /* ========================================================  SDCMOD  ========================================================= */
13894  #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
13895  #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
13896 /* ========================================================  SDAMOD  ========================================================= */
13897  #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
13898  #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
13899 /* ========================================================  SDSELF  ========================================================= */
13900  #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
13901  #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
13902 /* ========================================================  SDRFCR  ========================================================= */
13903  #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
13904  #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
13905  #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
13906  #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
13907 /* ========================================================  SDRFEN  ========================================================= */
13908  #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
13909  #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
13910 /* =========================================================  SDICR  ========================================================= */
13911  #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
13912  #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
13913 /* =========================================================  SDIR  ========================================================== */
13914  #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
13915  #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
13916  #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
13917  #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
13918  #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
13919  #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
13920 /* =========================================================  SDADR  ========================================================= */
13921  #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
13922  #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
13923 /* =========================================================  SDTR  ========================================================== */
13924  #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
13925  #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
13926  #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
13927  #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
13928  #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
13929  #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
13930  #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
13931  #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
13932  #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
13933  #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
13934 /* =========================================================  SDMOD  ========================================================= */
13935  #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
13936  #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
13937 /* =========================================================  SDSR  ========================================================== */
13938  #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
13939  #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
13940  #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
13941  #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
13942  #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
13943  #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
13944 
13945 /* =========================================================================================================================== */
13946 /* ================                                          BUSERRa                                          ================ */
13947 /* =========================================================================================================================== */
13948 
13949 /* ==========================================================  ADD  ========================================================== */
13950  #define R_BUS_BUSERRa_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
13951  #define R_BUS_BUSERRa_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
13952 /* =========================================================  STAT  ========================================================== */
13953  #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
13954  #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
13955  #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
13956  #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
13957 /* ==========================================================  RW  =========================================================== */
13958  #define R_BUS_BUSERRa_RW_RWSTAT_Pos       (0UL)          /*!< RWSTAT (Bit 0)                                        */
13959  #define R_BUS_BUSERRa_RW_RWSTAT_Msk       (0x1UL)        /*!< RWSTAT (Bitfield-Mask: 0x01)                          */
13960 
13961 /* =========================================================================================================================== */
13962 /* ================                                          BTZFERR                                          ================ */
13963 /* =========================================================================================================================== */
13964 
13965 /* ==========================================================  ADD  ========================================================== */
13966  #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos    (0UL)          /*!< BTZFERAD (Bit 0)                                      */
13967  #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk    (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff)                  */
13968 /* ==========================================================  RW  =========================================================== */
13969  #define R_BUS_BTZFERR_RW_TRWSTAT_Pos      (0UL)          /*!< TRWSTAT (Bit 0)                                       */
13970  #define R_BUS_BTZFERR_RW_TRWSTAT_Msk      (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */
13971 
13972 /* =========================================================================================================================== */
13973 /* ================                                          BUSERRb                                          ================ */
13974 /* =========================================================================================================================== */
13975 
13976 /* =========================================================  STAT  ========================================================== */
13977  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos    (5UL)    /*!< MSERRSTAT (Bit 5)                                     */
13978  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk    (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01)                       */
13979  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos    (4UL)    /*!< ILERRSTAT (Bit 4)                                     */
13980  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk    (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
13981  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos    (3UL)    /*!< MMERRSTAT (Bit 3)                                     */
13982  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk    (0x8UL)  /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
13983  #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos    (1UL)    /*!< STERRSTAT (Bit 1)                                     */
13984  #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk    (0x2UL)  /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
13985  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos    (0UL)    /*!< SLERRSTAT (Bit 0)                                     */
13986  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk    (0x1UL)  /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
13987 /* ==========================================================  CLR  ========================================================== */
13988  #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos      (5UL)    /*!< MSERRCLR (Bit 5)                                      */
13989  #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk      (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01)                        */
13990  #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos      (4UL)    /*!< ILERRCLR (Bit 4)                                      */
13991  #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk      (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
13992  #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos      (3UL)    /*!< MMERRCLR (Bit 3)                                      */
13993  #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk      (0x8UL)  /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
13994  #define R_BUS_BUSERRb_CLR_STERRCLR_Pos      (1UL)    /*!< STERRCLR (Bit 1)                                      */
13995  #define R_BUS_BUSERRb_CLR_STERRCLR_Msk      (0x2UL)  /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
13996  #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos      (0UL)    /*!< SLERRCLR (Bit 0)                                      */
13997  #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk      (0x1UL)  /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
13998 
13999 /* =========================================================================================================================== */
14000 /* ================                                        DMACDTCERR                                         ================ */
14001 /* =========================================================================================================================== */
14002 
14003 /* =========================================================  STAT  ========================================================== */
14004  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos    (0UL)   /*!< MTERRSTAT (Bit 0)                                     */
14005  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk    (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01)                       */
14006 /* ==========================================================  CLR  ========================================================== */
14007  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos      (0UL)   /*!< MTERRCLR (Bit 0)                                      */
14008  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk      (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01)                        */
14009 
14010 /* =========================================================================================================================== */
14011 /* ================                                         BUSSABT0                                          ================ */
14012 /* =========================================================================================================================== */
14013 
14014 /* =========================================================  FLBI  ========================================================== */
14015  #define R_BUS_BUSSABT0_FLBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14016  #define R_BUS_BUSSABT0_FLBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14017 /* ========================================================  MRE0BI  ========================================================= */
14018  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
14019  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14020 /* =========================================================  S0BI  ========================================================== */
14021  #define R_BUS_BUSSABT0_S0BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14022  #define R_BUS_BUSSABT0_S0BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14023 /* =========================================================  S1BI  ========================================================== */
14024  #define R_BUS_BUSSABT0_S1BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14025  #define R_BUS_BUSSABT0_S1BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14026 /* =========================================================  S2BI  ========================================================== */
14027  #define R_BUS_BUSSABT0_S2BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14028  #define R_BUS_BUSSABT0_S2BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14029 /* =========================================================  S3BI  ========================================================== */
14030  #define R_BUS_BUSSABT0_S3BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14031  #define R_BUS_BUSSABT0_S3BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14032 /* ========================================================  STBYSBI  ======================================================== */
14033  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
14034  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk      (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14035 /* =========================================================  ECBI  ========================================================== */
14036  #define R_BUS_BUSSABT0_ECBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14037  #define R_BUS_BUSSABT0_ECBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14038 /* =========================================================  EOBI  ========================================================== */
14039  #define R_BUS_BUSSABT0_EOBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14040  #define R_BUS_BUSSABT0_EOBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14041 /* ========================================================  SPI0BI  ========================================================= */
14042  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
14043  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14044 /* ========================================================  SPI1BI  ========================================================= */
14045  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
14046  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14047 /* =========================================================  PBBI  ========================================================== */
14048  #define R_BUS_BUSSABT0_PBBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14049  #define R_BUS_BUSSABT0_PBBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14050 /* =========================================================  PABI  ========================================================== */
14051  #define R_BUS_BUSSABT0_PABI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14052  #define R_BUS_BUSSABT0_PABI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14053 /* =========================================================  PIBI  ========================================================== */
14054  #define R_BUS_BUSSABT0_PIBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14055  #define R_BUS_BUSSABT0_PIBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14056 /* =========================================================  PSBI  ========================================================== */
14057  #define R_BUS_BUSSABT0_PSBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
14058  #define R_BUS_BUSSABT0_PSBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14059 /* =======================================================  CPU0SAHBI  ======================================================= */
14060  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
14061  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14062 /* =======================================================  CPU1TCMBI  ======================================================= */
14063  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
14064  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
14065 
14066 /* =========================================================================================================================== */
14067 /* ================                                         BUSSABT1                                          ================ */
14068 /* =========================================================================================================================== */
14069 
14070 /* =========================================================  FHBI  ========================================================== */
14071  #define R_BUS_BUSSABT1_FHBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
14072  #define R_BUS_BUSSABT1_FHBI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
14073 /* ========================================================  MRC0BI  ========================================================= */
14074  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
14075  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk    (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
14076 /* =========================================================  S0BI  ========================================================== */
14077  #define R_BUS_BUSSABT1_S0BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
14078  #define R_BUS_BUSSABT1_S0BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
14079 /* =========================================================  S1BI  ========================================================== */
14080  #define R_BUS_BUSSABT1_S1BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
14081  #define R_BUS_BUSSABT1_S1BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
14082 
14083 /* =========================================================================================================================== */
14084 /* ================                                          BMSAERR                                          ================ */
14085 /* =========================================================================================================================== */
14086 
14087 /* ==========================================================  ADD  ========================================================== */
14088  #define R_BUS_BMSAERR_ADD_MSERAD_Pos      (0UL)          /*!< MSERAD (Bit 0)                                        */
14089  #define R_BUS_BMSAERR_ADD_MSERAD_Msk      (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff)                    */
14090 /* ==========================================================  RW  =========================================================== */
14091  #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos    (0UL)          /*!< MSARWSTAT (Bit 0)                                     */
14092  #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk    (0x1UL)        /*!< MSARWSTAT (Bitfield-Mask: 0x01)                       */
14093 
14094 /* =========================================================================================================================== */
14095 /* ================                                            OAD                                            ================ */
14096 /* =========================================================================================================================== */
14097 
14098 /* ========================================================  BUSOAD  ========================================================= */
14099  #define R_BUS_OAD_BUSOAD_BWERROAD_Pos     (2UL)      /*!< BWERROAD (Bit 2)                                      */
14100  #define R_BUS_OAD_BUSOAD_BWERROAD_Msk     (0x4UL)    /*!< BWERROAD (Bitfield-Mask: 0x01)                        */
14101  #define R_BUS_OAD_BUSOAD_SLERROAD_Pos     (1UL)      /*!< SLERROAD (Bit 1)                                      */
14102  #define R_BUS_OAD_BUSOAD_SLERROAD_Msk     (0x2UL)    /*!< SLERROAD (Bitfield-Mask: 0x01)                        */
14103  #define R_BUS_OAD_BUSOAD_ILERROAD_Pos     (0UL)      /*!< ILERROAD (Bit 0)                                      */
14104  #define R_BUS_OAD_BUSOAD_ILERROAD_Msk     (0x1UL)    /*!< ILERROAD (Bitfield-Mask: 0x01)                        */
14105 /* =======================================================  BUSOADPT  ======================================================== */
14106  #define R_BUS_OAD_BUSOADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
14107  #define R_BUS_OAD_BUSOADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
14108  #define R_BUS_OAD_BUSOADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
14109  #define R_BUS_OAD_BUSOADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
14110 /* ========================================================  MSAOAD  ========================================================= */
14111  #define R_BUS_OAD_MSAOAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
14112  #define R_BUS_OAD_MSAOAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
14113  #define R_BUS_OAD_MSAOAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
14114  #define R_BUS_OAD_MSAOAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
14115 /* =========================================================  MSAPT  ========================================================= */
14116  #define R_BUS_OAD_MSAPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
14117  #define R_BUS_OAD_MSAPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
14118  #define R_BUS_OAD_MSAPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
14119  #define R_BUS_OAD_MSAPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
14120 
14121 /* =========================================================================================================================== */
14122 /* ================                                          MBWERR                                           ================ */
14123 /* =========================================================================================================================== */
14124 
14125 /* =========================================================  STAT  ========================================================== */
14126  #define R_BUS_MBWERR_STAT_BWERR_Pos    (0UL)   /*!< BWERR (Bit 0)                                         */
14127  #define R_BUS_MBWERR_STAT_BWERR_Msk    (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
14128 /* ==========================================================  CLR  ========================================================== */
14129  #define R_BUS_MBWERR_CLR_BWERR_Pos     (0UL)   /*!< BWERR (Bit 0)                                         */
14130  #define R_BUS_MBWERR_CLR_BWERR_Msk     (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
14131 
14132 /* =========================================================================================================================== */
14133 /* ================                                           BUSM                                            ================ */
14134 /* =========================================================================================================================== */
14135 
14136 /* ==========================================================  CNT  ========================================================== */
14137  #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
14138  #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
14139 
14140 /* =========================================================================================================================== */
14141 /* ================                                           BUSS                                            ================ */
14142 /* =========================================================================================================================== */
14143 
14144 /* ==========================================================  CNT  ========================================================== */
14145  #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
14146  #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
14147  #define R_BUS_BUSS_CNT_ARBS_Pos      (0UL)    /*!< ARBS (Bit 0)                                          */
14148  #define R_BUS_BUSS_CNT_ARBS_Msk      (0x3UL)  /*!< ARBS (Bitfield-Mask: 0x03)                            */
14149 
14150 /* =========================================================================================================================== */
14151 /* ================                                            MB                                             ================ */
14152 /* =========================================================================================================================== */
14153 
14154 /* ==========================================================  ID  =========================================================== */
14155  #define R_CAN0_MB_ID_IDE_Pos    (31UL)         /*!< IDE (Bit 31)                                          */
14156  #define R_CAN0_MB_ID_IDE_Msk    (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01)                             */
14157  #define R_CAN0_MB_ID_RTR_Pos    (30UL)         /*!< RTR (Bit 30)                                          */
14158  #define R_CAN0_MB_ID_RTR_Msk    (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01)                             */
14159  #define R_CAN0_MB_ID_SID_Pos    (18UL)         /*!< SID (Bit 18)                                          */
14160  #define R_CAN0_MB_ID_SID_Msk    (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
14161  #define R_CAN0_MB_ID_EID_Pos    (0UL)          /*!< EID (Bit 0)                                           */
14162  #define R_CAN0_MB_ID_EID_Msk    (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
14163 /* ==========================================================  DL  =========================================================== */
14164  #define R_CAN0_MB_DL_DLC_Pos    (0UL)          /*!< DLC (Bit 0)                                           */
14165  #define R_CAN0_MB_DL_DLC_Msk    (0xfUL)        /*!< DLC (Bitfield-Mask: 0x0f)                             */
14166 /* ===========================================================  D  =========================================================== */
14167  #define R_CAN0_MB_D_DATA_Pos    (0UL)          /*!< DATA (Bit 0)                                          */
14168  #define R_CAN0_MB_D_DATA_Msk    (0xffUL)       /*!< DATA (Bitfield-Mask: 0xff)                            */
14169 /* ==========================================================  TS  =========================================================== */
14170  #define R_CAN0_MB_TS_TSH_Pos    (8UL)          /*!< TSH (Bit 8)                                           */
14171  #define R_CAN0_MB_TS_TSH_Msk    (0xff00UL)     /*!< TSH (Bitfield-Mask: 0xff)                             */
14172  #define R_CAN0_MB_TS_TSL_Pos    (0UL)          /*!< TSL (Bit 0)                                           */
14173  #define R_CAN0_MB_TS_TSL_Msk    (0xffUL)       /*!< TSL (Bitfield-Mask: 0xff)                             */
14174 
14175 /* =========================================================================================================================== */
14176 /* ================                                          ELSEGR                                           ================ */
14177 /* =========================================================================================================================== */
14178 
14179 /* ==========================================================  BY  =========================================================== */
14180  #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
14181  #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
14182  #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
14183  #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
14184  #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
14185  #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
14186 
14187 /* =========================================================================================================================== */
14188 /* ================                                           ELSR                                            ================ */
14189 /* =========================================================================================================================== */
14190 
14191 /* ==========================================================  HA  =========================================================== */
14192  #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
14193  #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
14194 
14195 /* =========================================================================================================================== */
14196 /* ================                                            SAR                                            ================ */
14197 /* =========================================================================================================================== */
14198 
14199 /* ===========================================================  L  =========================================================== */
14200  #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
14201  #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
14202 /* ===========================================================  U  =========================================================== */
14203  #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
14204  #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
14205  #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
14206  #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
14207  #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
14208  #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
14209 
14210 /* =========================================================================================================================== */
14211 /* ================                                          REGION                                           ================ */
14212 /* =========================================================================================================================== */
14213 
14214 /* ==========================================================  AC  =========================================================== */
14215  #define R_MPU_MMPU_MMPU_REGION_AC_WP_Pos        (2UL)          /*!< WP (Bit 2)                                            */
14216  #define R_MPU_MMPU_MMPU_REGION_AC_WP_Msk        (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
14217  #define R_MPU_MMPU_MMPU_REGION_AC_RP_Pos        (1UL)          /*!< RP (Bit 1)                                            */
14218  #define R_MPU_MMPU_MMPU_REGION_AC_RP_Msk        (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
14219  #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Pos    (0UL)          /*!< ENABLE (Bit 0)                                        */
14220  #define R_MPU_MMPU_MMPU_REGION_AC_ENABLE_Msk    (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
14221 /* ===========================================================  S  =========================================================== */
14222  #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Pos      (0UL)          /*!< MMPUS (Bit 0)                                         */
14223  #define R_MPU_MMPU_MMPU_REGION_S_MMPUS_Msk      (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff)                     */
14224 /* ===========================================================  E  =========================================================== */
14225  #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Pos      (0UL)          /*!< MMPUE (Bit 0)                                         */
14226  #define R_MPU_MMPU_MMPU_REGION_E_MMPUE_Msk      (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff)                     */
14227 
14228 /* =========================================================================================================================== */
14229 /* ================                                           MMPU                                            ================ */
14230 /* =========================================================================================================================== */
14231 
14232 /* ==========================================================  CTL  ========================================================== */
14233  #define R_MPU_MMPU_MMPU_CTL_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
14234  #define R_MPU_MMPU_MMPU_CTL_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
14235  #define R_MPU_MMPU_MMPU_CTL_OAD_Pos       (1UL)      /*!< OAD (Bit 1)                                           */
14236  #define R_MPU_MMPU_MMPU_CTL_OAD_Msk       (0x2UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
14237  #define R_MPU_MMPU_MMPU_CTL_ENABLE_Pos    (0UL)      /*!< ENABLE (Bit 0)                                        */
14238  #define R_MPU_MMPU_MMPU_CTL_ENABLE_Msk    (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
14239 /* ==========================================================  PT  =========================================================== */
14240  #define R_MPU_MMPU_MMPU_PT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
14241  #define R_MPU_MMPU_MMPU_PT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
14242  #define R_MPU_MMPU_MMPU_PT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
14243  #define R_MPU_MMPU_MMPU_PT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
14244 
14245 /* =========================================================================================================================== */
14246 /* ================                                           SMPU                                            ================ */
14247 /* =========================================================================================================================== */
14248 
14249 /* ===========================================================  R  =========================================================== */
14250  #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Pos    (15UL)     /*!< WPSRAMHS (Bit 15)                                     */
14251  #define R_MPU_SMPU_SMPU_R_WPSRAMHS_Msk    (0x8000UL) /*!< WPSRAMHS (Bitfield-Mask: 0x01)                        */
14252  #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Pos    (14UL)     /*!< RPSRAMHS (Bit 14)                                     */
14253  #define R_MPU_SMPU_SMPU_R_RPSRAMHS_Msk    (0x4000UL) /*!< RPSRAMHS (Bitfield-Mask: 0x01)                        */
14254  #define R_MPU_SMPU_SMPU_R_WPFLI_Pos       (13UL)     /*!< WPFLI (Bit 13)                                        */
14255  #define R_MPU_SMPU_SMPU_R_WPFLI_Msk       (0x2000UL) /*!< WPFLI (Bitfield-Mask: 0x01)                           */
14256  #define R_MPU_SMPU_SMPU_R_RPFLI_Pos       (12UL)     /*!< RPFLI (Bit 12)                                        */
14257  #define R_MPU_SMPU_SMPU_R_RPFLI_Msk       (0x1000UL) /*!< RPFLI (Bitfield-Mask: 0x01)                           */
14258  #define R_MPU_SMPU_SMPU_R_WPGRPC_Pos      (7UL)      /*!< WPGRPC (Bit 7)                                        */
14259  #define R_MPU_SMPU_SMPU_R_WPGRPC_Msk      (0x80UL)   /*!< WPGRPC (Bitfield-Mask: 0x01)                          */
14260  #define R_MPU_SMPU_SMPU_R_RPGRPC_Pos      (6UL)      /*!< RPGRPC (Bit 6)                                        */
14261  #define R_MPU_SMPU_SMPU_R_RPGRPC_Msk      (0x40UL)   /*!< RPGRPC (Bitfield-Mask: 0x01)                          */
14262  #define R_MPU_SMPU_SMPU_R_WPGRPB_Pos      (5UL)      /*!< WPGRPB (Bit 5)                                        */
14263  #define R_MPU_SMPU_SMPU_R_WPGRPB_Msk      (0x20UL)   /*!< WPGRPB (Bitfield-Mask: 0x01)                          */
14264  #define R_MPU_SMPU_SMPU_R_RPGRPB_Pos      (4UL)      /*!< RPGRPB (Bit 4)                                        */
14265  #define R_MPU_SMPU_SMPU_R_RPGRPB_Msk      (0x10UL)   /*!< RPGRPB (Bitfield-Mask: 0x01)                          */
14266  #define R_MPU_SMPU_SMPU_R_WPGRPA_Pos      (3UL)      /*!< WPGRPA (Bit 3)                                        */
14267  #define R_MPU_SMPU_SMPU_R_WPGRPA_Msk      (0x8UL)    /*!< WPGRPA (Bitfield-Mask: 0x01)                          */
14268  #define R_MPU_SMPU_SMPU_R_RPGRPA_Pos      (2UL)      /*!< RPGRPA (Bit 2)                                        */
14269  #define R_MPU_SMPU_SMPU_R_RPGRPA_Msk      (0x4UL)    /*!< RPGRPA (Bitfield-Mask: 0x01)                          */
14270 
14271 /* =========================================================================================================================== */
14272 /* ================                                            SP                                             ================ */
14273 /* =========================================================================================================================== */
14274 
14275 /* ==========================================================  OAD  ========================================================== */
14276  #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
14277  #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
14278  #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
14279  #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
14280 /* ==========================================================  CTL  ========================================================== */
14281  #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
14282  #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
14283  #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
14284  #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
14285 /* ==========================================================  PT  =========================================================== */
14286  #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
14287  #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
14288  #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
14289  #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
14290 /* ==========================================================  SA  =========================================================== */
14291  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
14292  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
14293 /* ==========================================================  EA  =========================================================== */
14294  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
14295  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
14296 
14297 /* =========================================================================================================================== */
14298 /* ================                                            AMP                                            ================ */
14299 /* =========================================================================================================================== */
14300 
14301 /* ==========================================================  OS  =========================================================== */
14302 /* ==========================================================  PS  =========================================================== */
14303 /* ==========================================================  MS  =========================================================== */
14304 
14305 /* =========================================================================================================================== */
14306 /* ================                                           AMPOT                                           ================ */
14307 /* =========================================================================================================================== */
14308 
14309 /* ===========================================================  P  =========================================================== */
14310  #define R_OPAMP_AMPOT_P_TRMP_Pos    (0UL)    /*!< TRMP (Bit 0)                                          */
14311  #define R_OPAMP_AMPOT_P_TRMP_Msk    (0x1fUL) /*!< TRMP (Bitfield-Mask: 0x1f)                            */
14312 /* ===========================================================  N  =========================================================== */
14313  #define R_OPAMP_AMPOT_N_TRMN_Pos    (0UL)    /*!< TRMN (Bit 0)                                          */
14314  #define R_OPAMP_AMPOT_N_TRMN_Msk    (0x1fUL) /*!< TRMN (Bitfield-Mask: 0x1f)                            */
14315 
14316 /* =========================================================================================================================== */
14317 /* ================                                            PIN                                            ================ */
14318 /* =========================================================================================================================== */
14319 
14320 /* =======================================================  PmnPFS_BY  ======================================================= */
14321  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
14322  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
14323  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
14324  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
14325  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
14326  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
14327  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
14328  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
14329  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
14330  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
14331  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
14332  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
14333 /* =======================================================  PmnPFS_HA  ======================================================= */
14334  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
14335  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
14336  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
14337  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
14338  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
14339  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
14340  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
14341  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
14342  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
14343  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
14344  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
14345  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
14346  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
14347  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
14348  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
14349  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
14350  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
14351  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
14352  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
14353  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
14354 /* ========================================================  PmnPFS  ========================================================= */
14355  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
14356  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
14357  #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
14358  #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
14359  #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
14360  #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
14361  #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
14362  #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
14363  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
14364  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
14365  #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
14366  #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
14367  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
14368  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
14369  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
14370  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
14371  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
14372  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
14373  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
14374  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
14375  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
14376  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
14377  #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
14378  #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
14379 
14380 /* =========================================================================================================================== */
14381 /* ================                                           PORT                                            ================ */
14382 /* =========================================================================================================================== */
14383 
14384 /* =========================================================================================================================== */
14385 /* ================                                           VLSEL                                           ================ */
14386 /* =========================================================================================================================== */
14387 
14388 /* ========================================================  VL1SEL  ========================================================= */
14389  #define R_PFS_VLSEL_VL1SEL_SELVL_Pos    (0UL)   /*!< SELVL (Bit 0)                                         */
14390  #define R_PFS_VLSEL_VL1SEL_SELVL_Msk    (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01)                           */
14391 
14392 /* =========================================================================================================================== */
14393 /* ================                                           PMSAR                                           ================ */
14394 /* =========================================================================================================================== */
14395 
14396 /* =========================================================  PMSAR  ========================================================= */
14397 
14398 /* =========================================================================================================================== */
14399 /* ================                                           RTCCR                                           ================ */
14400 /* =========================================================================================================================== */
14401 
14402 /* =========================================================  RTCCR  ========================================================= */
14403  #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
14404  #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
14405  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
14406  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
14407  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
14408  #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
14409  #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
14410  #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
14411 
14412 /* =========================================================================================================================== */
14413 /* ================                                            CP                                             ================ */
14414 /* =========================================================================================================================== */
14415 
14416 /* =========================================================  RSEC  ========================================================== */
14417  #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
14418  #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
14419  #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
14420  #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
14421 /* =========================================================  BCNT0  ========================================================= */
14422  #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
14423  #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
14424 /* =========================================================  RMIN  ========================================================== */
14425  #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
14426  #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
14427  #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
14428  #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
14429 /* =========================================================  BCNT1  ========================================================= */
14430  #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
14431  #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
14432 /* ==========================================================  RHR  ========================================================== */
14433  #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
14434  #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
14435  #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
14436  #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
14437  #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
14438  #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
14439 /* =========================================================  BCNT2  ========================================================= */
14440  #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
14441  #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
14442 /* =========================================================  RDAY  ========================================================== */
14443  #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
14444  #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
14445  #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
14446  #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
14447 /* =========================================================  BCNT3  ========================================================= */
14448  #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
14449  #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
14450 /* =========================================================  RMON  ========================================================== */
14451  #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
14452  #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
14453  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
14454  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
14455 
14456 /* =========================================================================================================================== */
14457 /* ================                                          PIPE_TR                                          ================ */
14458 /* =========================================================================================================================== */
14459 
14460 /* ===========================================================  E  =========================================================== */
14461  #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
14462  #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
14463  #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
14464  #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
14465 /* ===========================================================  N  =========================================================== */
14466  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
14467  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
14468 
14469 /* =========================================================================================================================== */
14470 /* ================                                           CTRL                                            ================ */
14471 /* =========================================================================================================================== */
14472 
14473 /* =========================================================  AGTCR  ========================================================= */
14474  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
14475  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
14476  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
14477  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
14478  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
14479  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
14480  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
14481  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
14482  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
14483  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
14484  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
14485  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
14486  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
14487  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
14488 /* ========================================================  AGTMR1  ========================================================= */
14489  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
14490  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
14491  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
14492  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
14493  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
14494  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
14495 /* ========================================================  AGTMR2  ========================================================= */
14496  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
14497  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
14498  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
14499  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
14500 /* =====================================================  AGTIOSEL_ALT  ====================================================== */
14501  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
14502  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
14503  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
14504  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
14505 /* ========================================================  AGTIOC  ========================================================= */
14506  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
14507  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
14508  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
14509  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
14510  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
14511  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
14512  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
14513  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
14514 /* ========================================================  AGTISR  ========================================================= */
14515  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
14516  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
14517 /* ========================================================  AGTCMSR  ======================================================== */
14518  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
14519  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
14520  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
14521  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
14522  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
14523  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
14524  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
14525  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
14526  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
14527  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
14528  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
14529  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
14530 /* =======================================================  AGTIOSEL  ======================================================== */
14531  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
14532  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
14533  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
14534  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
14535 
14536 /* =========================================================================================================================== */
14537 /* ================                                           AGT16                                           ================ */
14538 /* =========================================================================================================================== */
14539 
14540 /* ==========================================================  AGT  ========================================================== */
14541  #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
14542  #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
14543 /* ========================================================  AGTCMA  ========================================================= */
14544  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
14545  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
14546 /* ========================================================  AGTCMB  ========================================================= */
14547  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
14548  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
14549 
14550 /* =========================================================================================================================== */
14551 /* ================                                           AGT32                                           ================ */
14552 /* =========================================================================================================================== */
14553 
14554 /* ==========================================================  AGT  ========================================================== */
14555  #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
14556  #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
14557 /* ========================================================  AGTCMA  ========================================================= */
14558  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
14559  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
14560 /* ========================================================  AGTCMB  ========================================================= */
14561  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
14562  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
14563 
14564 /** @} */ /* End of group PosMask_clusters */
14565 
14566 /* =========================================================================================================================== */
14567 /* ================                                Pos/Mask Peripheral Section                                ================ */
14568 /* =========================================================================================================================== */
14569 
14570 /** @addtogroup PosMask_peripherals
14571  * @{
14572  */
14573 
14574 /* =========================================================================================================================== */
14575 /* ================                                         R_ACMPHS0                                         ================ */
14576 /* =========================================================================================================================== */
14577 
14578 /* ========================================================  CMPCTL  ========================================================= */
14579  #define R_ACMPHS0_CMPCTL_HCMPON_Pos     (7UL)    /*!< HCMPON (Bit 7)                                        */
14580  #define R_ACMPHS0_CMPCTL_HCMPON_Msk     (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01)                          */
14581  #define R_ACMPHS0_CMPCTL_CDFS_Pos       (5UL)    /*!< CDFS (Bit 5)                                          */
14582  #define R_ACMPHS0_CMPCTL_CDFS_Msk       (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03)                            */
14583  #define R_ACMPHS0_CMPCTL_CEG_Pos        (3UL)    /*!< CEG (Bit 3)                                           */
14584  #define R_ACMPHS0_CMPCTL_CEG_Msk        (0x18UL) /*!< CEG (Bitfield-Mask: 0x03)                             */
14585  #define R_ACMPHS0_CMPCTL_CSTEN_Pos      (2UL)    /*!< CSTEN (Bit 2)                                         */
14586  #define R_ACMPHS0_CMPCTL_CSTEN_Msk      (0x4UL)  /*!< CSTEN (Bitfield-Mask: 0x01)                           */
14587  #define R_ACMPHS0_CMPCTL_COE_Pos        (1UL)    /*!< COE (Bit 1)                                           */
14588  #define R_ACMPHS0_CMPCTL_COE_Msk        (0x2UL)  /*!< COE (Bitfield-Mask: 0x01)                             */
14589  #define R_ACMPHS0_CMPCTL_CINV_Pos       (0UL)    /*!< CINV (Bit 0)                                          */
14590  #define R_ACMPHS0_CMPCTL_CINV_Msk       (0x1UL)  /*!< CINV (Bitfield-Mask: 0x01)                            */
14591 /* ========================================================  CMPSEL0  ======================================================== */
14592  #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos    (0UL)    /*!< CMPSEL (Bit 0)                                        */
14593  #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk    (0xfUL)  /*!< CMPSEL (Bitfield-Mask: 0x0f)                          */
14594 /* ========================================================  CMPSEL1  ======================================================== */
14595  #define R_ACMPHS0_CMPSEL1_CRVS_Pos      (0UL)    /*!< CRVS (Bit 0)                                          */
14596  #define R_ACMPHS0_CMPSEL1_CRVS_Msk      (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f)                            */
14597 /* ========================================================  CMPMON  ========================================================= */
14598  #define R_ACMPHS0_CMPMON_CMPMON_Pos     (0UL)    /*!< CMPMON (Bit 0)                                        */
14599  #define R_ACMPHS0_CMPMON_CMPMON_Msk     (0x1UL)  /*!< CMPMON (Bitfield-Mask: 0x01)                          */
14600 /* =========================================================  CPIOC  ========================================================= */
14601  #define R_ACMPHS0_CPIOC_VREFEN_Pos      (7UL)    /*!< VREFEN (Bit 7)                                        */
14602  #define R_ACMPHS0_CPIOC_VREFEN_Msk      (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01)                          */
14603  #define R_ACMPHS0_CPIOC_CPOE_Pos        (0UL)    /*!< CPOE (Bit 0)                                          */
14604  #define R_ACMPHS0_CPIOC_CPOE_Msk        (0x1UL)  /*!< CPOE (Bitfield-Mask: 0x01)                            */
14605 
14606 /* =========================================================================================================================== */
14607 /* ================                                         R_ACMPLP                                          ================ */
14608 /* =========================================================================================================================== */
14609 
14610 /* ========================================================  COMPMDR  ======================================================== */
14611  #define R_ACMPLP_COMPMDR_C1MON_Pos      (7UL)    /*!< C1MON (Bit 7)                                         */
14612  #define R_ACMPLP_COMPMDR_C1MON_Msk      (0x80UL) /*!< C1MON (Bitfield-Mask: 0x01)                           */
14613  #define R_ACMPLP_COMPMDR_C1VRF_Pos      (6UL)    /*!< C1VRF (Bit 6)                                         */
14614  #define R_ACMPLP_COMPMDR_C1VRF_Msk      (0x40UL) /*!< C1VRF (Bitfield-Mask: 0x01)                           */
14615  #define R_ACMPLP_COMPMDR_C1WDE_Pos      (5UL)    /*!< C1WDE (Bit 5)                                         */
14616  #define R_ACMPLP_COMPMDR_C1WDE_Msk      (0x20UL) /*!< C1WDE (Bitfield-Mask: 0x01)                           */
14617  #define R_ACMPLP_COMPMDR_C1ENB_Pos      (4UL)    /*!< C1ENB (Bit 4)                                         */
14618  #define R_ACMPLP_COMPMDR_C1ENB_Msk      (0x10UL) /*!< C1ENB (Bitfield-Mask: 0x01)                           */
14619  #define R_ACMPLP_COMPMDR_C0MON_Pos      (3UL)    /*!< C0MON (Bit 3)                                         */
14620  #define R_ACMPLP_COMPMDR_C0MON_Msk      (0x8UL)  /*!< C0MON (Bitfield-Mask: 0x01)                           */
14621  #define R_ACMPLP_COMPMDR_C0WDE_Pos      (1UL)    /*!< C0WDE (Bit 1)                                         */
14622  #define R_ACMPLP_COMPMDR_C0WDE_Msk      (0x2UL)  /*!< C0WDE (Bitfield-Mask: 0x01)                           */
14623  #define R_ACMPLP_COMPMDR_C0VRF_Pos      (2UL)    /*!< C0VRF (Bit 2)                                         */
14624  #define R_ACMPLP_COMPMDR_C0VRF_Msk      (0x4UL)  /*!< C0VRF (Bitfield-Mask: 0x01)                           */
14625  #define R_ACMPLP_COMPMDR_C0ENB_Pos      (0UL)    /*!< C0ENB (Bit 0)                                         */
14626  #define R_ACMPLP_COMPMDR_C0ENB_Msk      (0x1UL)  /*!< C0ENB (Bitfield-Mask: 0x01)                           */
14627 /* ========================================================  COMPFIR  ======================================================== */
14628  #define R_ACMPLP_COMPFIR_C1EDG_Pos      (7UL)    /*!< C1EDG (Bit 7)                                         */
14629  #define R_ACMPLP_COMPFIR_C1EDG_Msk      (0x80UL) /*!< C1EDG (Bitfield-Mask: 0x01)                           */
14630  #define R_ACMPLP_COMPFIR_C1EPO_Pos      (6UL)    /*!< C1EPO (Bit 6)                                         */
14631  #define R_ACMPLP_COMPFIR_C1EPO_Msk      (0x40UL) /*!< C1EPO (Bitfield-Mask: 0x01)                           */
14632  #define R_ACMPLP_COMPFIR_C1FCK_Pos      (4UL)    /*!< C1FCK (Bit 4)                                         */
14633  #define R_ACMPLP_COMPFIR_C1FCK_Msk      (0x30UL) /*!< C1FCK (Bitfield-Mask: 0x03)                           */
14634  #define R_ACMPLP_COMPFIR_C0EDG_Pos      (3UL)    /*!< C0EDG (Bit 3)                                         */
14635  #define R_ACMPLP_COMPFIR_C0EDG_Msk      (0x8UL)  /*!< C0EDG (Bitfield-Mask: 0x01)                           */
14636  #define R_ACMPLP_COMPFIR_C0EPO_Pos      (2UL)    /*!< C0EPO (Bit 2)                                         */
14637  #define R_ACMPLP_COMPFIR_C0EPO_Msk      (0x4UL)  /*!< C0EPO (Bitfield-Mask: 0x01)                           */
14638  #define R_ACMPLP_COMPFIR_C0FCK_Pos      (0UL)    /*!< C0FCK (Bit 0)                                         */
14639  #define R_ACMPLP_COMPFIR_C0FCK_Msk      (0x3UL)  /*!< C0FCK (Bitfield-Mask: 0x03)                           */
14640 /* ========================================================  COMPOCR  ======================================================== */
14641  #define R_ACMPLP_COMPOCR_SPDMD_Pos      (7UL)    /*!< SPDMD (Bit 7)                                         */
14642  #define R_ACMPLP_COMPOCR_SPDMD_Msk      (0x80UL) /*!< SPDMD (Bitfield-Mask: 0x01)                           */
14643  #define R_ACMPLP_COMPOCR_C1OP_Pos       (6UL)    /*!< C1OP (Bit 6)                                          */
14644  #define R_ACMPLP_COMPOCR_C1OP_Msk       (0x40UL) /*!< C1OP (Bitfield-Mask: 0x01)                            */
14645  #define R_ACMPLP_COMPOCR_C1OE_Pos       (5UL)    /*!< C1OE (Bit 5)                                          */
14646  #define R_ACMPLP_COMPOCR_C1OE_Msk       (0x20UL) /*!< C1OE (Bitfield-Mask: 0x01)                            */
14647  #define R_ACMPLP_COMPOCR_C0OP_Pos       (2UL)    /*!< C0OP (Bit 2)                                          */
14648  #define R_ACMPLP_COMPOCR_C0OP_Msk       (0x4UL)  /*!< C0OP (Bitfield-Mask: 0x01)                            */
14649  #define R_ACMPLP_COMPOCR_C0OE_Pos       (1UL)    /*!< C0OE (Bit 1)                                          */
14650  #define R_ACMPLP_COMPOCR_C0OE_Msk       (0x2UL)  /*!< C0OE (Bitfield-Mask: 0x01)                            */
14651 /* =======================================================  COMPSEL0  ======================================================== */
14652  #define R_ACMPLP_COMPSEL0_IVCMP1_Pos    (4UL)    /*!< IVCMP1 (Bit 4)                                        */
14653  #define R_ACMPLP_COMPSEL0_IVCMP1_Msk    (0x70UL) /*!< IVCMP1 (Bitfield-Mask: 0x07)                          */
14654  #define R_ACMPLP_COMPSEL0_IVCMP0_Pos    (0UL)    /*!< IVCMP0 (Bit 0)                                        */
14655  #define R_ACMPLP_COMPSEL0_IVCMP0_Msk    (0x7UL)  /*!< IVCMP0 (Bitfield-Mask: 0x07)                          */
14656 /* =======================================================  COMPSEL1  ======================================================== */
14657  #define R_ACMPLP_COMPSEL1_C1VRF2_Pos    (7UL)    /*!< C1VRF2 (Bit 7)                                        */
14658  #define R_ACMPLP_COMPSEL1_C1VRF2_Msk    (0x80UL) /*!< C1VRF2 (Bitfield-Mask: 0x01)                          */
14659  #define R_ACMPLP_COMPSEL1_IVREF1_Pos    (4UL)    /*!< IVREF1 (Bit 4)                                        */
14660  #define R_ACMPLP_COMPSEL1_IVREF1_Msk    (0x70UL) /*!< IVREF1 (Bitfield-Mask: 0x07)                          */
14661  #define R_ACMPLP_COMPSEL1_IVREF0_Pos    (0UL)    /*!< IVREF0 (Bit 0)                                        */
14662  #define R_ACMPLP_COMPSEL1_IVREF0_Msk    (0x7UL)  /*!< IVREF0 (Bitfield-Mask: 0x07)                          */
14663 
14664 /* =========================================================================================================================== */
14665 /* ================                                          R_ADC0                                           ================ */
14666 /* =========================================================================================================================== */
14667 
14668 /* =========================================================  ADCSR  ========================================================= */
14669  #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
14670  #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
14671  #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
14672  #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
14673  #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
14674  #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
14675  #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
14676  #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
14677  #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
14678  #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
14679  #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
14680  #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
14681  #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
14682  #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
14683  #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
14684  #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
14685  #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
14686  #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
14687 /* ========================================================  ADANSA  ========================================================= */
14688  #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
14689  #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
14690 /* =========================================================  ADADS  ========================================================= */
14691  #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
14692  #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
14693 /* =========================================================  ADADC  ========================================================= */
14694  #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
14695  #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
14696  #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
14697  #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
14698 /* =========================================================  ADCER  ========================================================= */
14699  #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
14700  #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
14701  #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
14702  #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
14703  #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
14704  #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
14705  #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
14706  #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
14707  #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
14708  #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
14709  #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
14710  #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
14711  #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
14712  #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
14713  #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
14714  #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
14715 /* ========================================================  ADSTRGR  ======================================================== */
14716  #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
14717  #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
14718  #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
14719  #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
14720 /* ========================================================  ADEXICR  ======================================================== */
14721  #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
14722  #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
14723  #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
14724  #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
14725  #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
14726  #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
14727  #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
14728  #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
14729  #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
14730  #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
14731  #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
14732  #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
14733  #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
14734  #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
14735  #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
14736  #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
14737 /* ========================================================  ADANSB  ========================================================= */
14738  #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
14739  #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
14740 /* ========================================================  ADDBLDR  ======================================================== */
14741  #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
14742  #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
14743 /* ========================================================  ADTSDR  ========================================================= */
14744  #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
14745  #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
14746 /* ========================================================  ADOCDR  ========================================================= */
14747  #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
14748  #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
14749 /* ======================================================  ADRD_RIGHT  ======================================================= */
14750  #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
14751  #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
14752  #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
14753  #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
14754 /* =======================================================  ADRD_LEFT  ======================================================= */
14755  #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
14756  #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
14757  #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
14758  #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
14759 /* =========================================================  ADDR  ========================================================== */
14760  #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
14761  #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
14762 /* ========================================================  ADSHCR  ========================================================= */
14763  #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
14764  #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
14765  #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
14766  #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
14767  #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
14768  #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
14769  #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
14770  #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
14771 /* ========================================================  ADDISCR  ======================================================== */
14772  #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
14773  #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
14774  #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
14775  #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
14776 /* ========================================================  ADSHMSR  ======================================================== */
14777  #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
14778  #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
14779 /* ========================================================  ADACSR  ========================================================= */
14780  #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
14781  #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
14782 /* ========================================================  ADGSPCR  ======================================================== */
14783  #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
14784  #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
14785  #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
14786  #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
14787  #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
14788  #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
14789  #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
14790  #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
14791 /* =========================================================  ADICR  ========================================================= */
14792  #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
14793  #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
14794 /* =======================================================  ADDBLDRA  ======================================================== */
14795  #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
14796  #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
14797 /* =======================================================  ADDBLDRB  ======================================================== */
14798  #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
14799  #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
14800 /* ======================================================  ADHVREFCNT  ======================================================= */
14801  #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
14802  #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
14803  #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
14804  #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
14805  #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
14806  #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
14807 /* =======================================================  ADWINMON  ======================================================== */
14808  #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
14809  #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
14810  #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
14811  #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
14812  #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
14813  #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
14814 /* ========================================================  ADCMPCR  ======================================================== */
14815  #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
14816  #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
14817  #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
14818  #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
14819  #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
14820  #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
14821  #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
14822  #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
14823  #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
14824  #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
14825  #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
14826  #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
14827 /* ======================================================  ADCMPANSER  ======================================================= */
14828  #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
14829  #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
14830  #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
14831  #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
14832 /* =======================================================  ADCMPLER  ======================================================== */
14833  #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
14834  #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
14835  #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
14836  #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
14837 /* =======================================================  ADCMPANSR  ======================================================= */
14838  #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
14839  #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
14840 /* ========================================================  ADCMPLR  ======================================================== */
14841  #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
14842  #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
14843 /* =======================================================  ADCMPDR0  ======================================================== */
14844  #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
14845  #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
14846 /* =======================================================  ADCMPDR1  ======================================================== */
14847  #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
14848  #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
14849 /* ========================================================  ADCMPSR  ======================================================== */
14850  #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
14851  #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
14852 /* =======================================================  ADCMPSER  ======================================================== */
14853  #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
14854  #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
14855  #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
14856  #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
14857 /* =======================================================  ADCMPBNSR  ======================================================= */
14858  #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
14859  #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
14860  #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
14861  #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
14862 /* =======================================================  ADWINLLB  ======================================================== */
14863  #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
14864  #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
14865 /* =======================================================  ADWINULB  ======================================================== */
14866  #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
14867  #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
14868 /* =======================================================  ADCMPBSR  ======================================================== */
14869  #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
14870  #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
14871 /* ========================================================  ADSSTRL  ======================================================== */
14872  #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
14873  #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
14874 /* ========================================================  ADSSTRT  ======================================================== */
14875  #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
14876  #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
14877 /* ========================================================  ADSSTRO  ======================================================== */
14878  #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
14879  #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
14880 /* ========================================================  ADSSTR  ========================================================= */
14881  #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
14882  #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
14883 /* ========================================================  ADPGACR  ======================================================== */
14884  #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
14885  #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
14886  #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
14887  #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
14888  #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
14889  #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
14890  #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
14891  #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
14892  #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
14893  #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
14894  #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
14895  #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
14896  #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
14897  #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
14898  #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
14899  #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
14900  #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
14901  #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
14902  #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
14903  #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
14904  #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
14905  #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
14906  #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
14907  #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
14908  #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
14909  #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
14910  #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
14911  #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
14912  #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
14913  #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
14914  #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
14915  #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
14916 /* =========================================================  ADRD  ========================================================== */
14917  #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
14918  #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
14919 /* =========================================================  ADRST  ========================================================= */
14920  #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
14921  #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
14922 /* ======================================================  VREFAMPCNT  ======================================================= */
14923  #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
14924  #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
14925  #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
14926  #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
14927  #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
14928  #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
14929  #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
14930  #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
14931  #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
14932  #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
14933 /* =======================================================  ADCALEXE  ======================================================== */
14934  #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
14935  #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
14936  #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
14937  #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
14938 /* ========================================================  ADANIM  ========================================================= */
14939  #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
14940  #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
14941 /* =======================================================  ADPGAGS0  ======================================================== */
14942  #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
14943  #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
14944  #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
14945  #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
14946  #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
14947  #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
14948  #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
14949  #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
14950 /* =======================================================  ADPGADCR0  ======================================================= */
14951  #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
14952  #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
14953  #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
14954  #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
14955  #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
14956  #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
14957  #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
14958  #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
14959  #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
14960  #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
14961  #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
14962  #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
14963  #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
14964  #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
14965  #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
14966  #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
14967 /* =========================================================  ADREF  ========================================================= */
14968  #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
14969  #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
14970  #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
14971  #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
14972 /* ========================================================  ADEXREF  ======================================================== */
14973  #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
14974  #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
14975 /* =======================================================  ADAMPOFF  ======================================================== */
14976  #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
14977  #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
14978 /* ========================================================  ADTSTPR  ======================================================== */
14979  #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
14980  #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
14981  #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
14982  #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
14983 /* =======================================================  ADDDACER  ======================================================== */
14984  #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
14985  #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
14986  #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
14987  #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
14988  #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
14989  #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
14990 /* =======================================================  ADEXTSTR  ======================================================== */
14991  #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
14992  #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
14993  #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
14994  #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
14995  #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
14996  #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
14997  #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
14998  #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
14999  #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
15000  #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
15001  #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
15002  #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
15003 /* ========================================================  ADTSTRA  ======================================================== */
15004  #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
15005  #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
15006  #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
15007  #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
15008  #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
15009  #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
15010  #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
15011  #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
15012  #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
15013  #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
15014  #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
15015  #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
15016 /* ========================================================  ADTSTRB  ======================================================== */
15017  #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
15018  #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
15019 /* ========================================================  ADTSTRC  ======================================================== */
15020  #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
15021  #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
15022  #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
15023  #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
15024 /* ========================================================  ADTSTRD  ======================================================== */
15025  #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
15026  #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
15027 /* =======================================================  ADSWTSTR0  ======================================================= */
15028  #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
15029  #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
15030  #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
15031  #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
15032  #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
15033  #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
15034  #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
15035  #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
15036  #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
15037  #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
15038  #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
15039  #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
15040 /* =======================================================  ADSWTSTR1  ======================================================= */
15041  #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
15042  #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
15043  #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
15044  #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
15045  #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
15046  #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
15047  #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
15048  #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
15049  #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
15050  #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
15051  #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
15052  #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
15053 /* =======================================================  ADSWTSTR2  ======================================================= */
15054  #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
15055  #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
15056  #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
15057  #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
15058  #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
15059  #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
15060  #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
15061  #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
15062  #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
15063  #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
15064  #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
15065  #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
15066  #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
15067  #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
15068  #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
15069  #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
15070  #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
15071  #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
15072  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
15073  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
15074 /* ========================================================  ADSWCR  ========================================================= */
15075  #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
15076  #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
15077  #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
15078  #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
15079 /* ========================================================  ADGSCS  ========================================================= */
15080  #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
15081  #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
15082  #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
15083  #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
15084 /* =========================================================  ADSER  ========================================================= */
15085  #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
15086  #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
15087 /* ========================================================  ADBUF0  ========================================================= */
15088  #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15089  #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15090 /* ========================================================  ADBUF1  ========================================================= */
15091  #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15092  #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15093 /* ========================================================  ADBUF2  ========================================================= */
15094  #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15095  #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15096 /* ========================================================  ADBUF3  ========================================================= */
15097  #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15098  #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15099 /* ========================================================  ADBUF4  ========================================================= */
15100  #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15101  #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15102 /* ========================================================  ADBUF5  ========================================================= */
15103  #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15104  #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15105 /* ========================================================  ADBUF6  ========================================================= */
15106  #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15107  #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15108 /* ========================================================  ADBUF7  ========================================================= */
15109  #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15110  #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15111 /* ========================================================  ADBUF8  ========================================================= */
15112  #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15113  #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15114 /* ========================================================  ADBUF9  ========================================================= */
15115  #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
15116  #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15117 /* ========================================================  ADBUF10  ======================================================== */
15118  #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
15119  #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15120 /* ========================================================  ADBUF11  ======================================================== */
15121  #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
15122  #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15123 /* ========================================================  ADBUF12  ======================================================== */
15124  #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
15125  #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15126 /* ========================================================  ADBUF13  ======================================================== */
15127  #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
15128  #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15129 /* ========================================================  ADBUF14  ======================================================== */
15130  #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
15131  #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15132 /* ========================================================  ADBUF15  ======================================================== */
15133  #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
15134  #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
15135 /* ========================================================  ADBUFEN  ======================================================== */
15136  #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
15137  #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
15138 /* =======================================================  ADBUFPTR  ======================================================== */
15139  #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
15140  #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
15141  #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
15142  #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
15143 /* =======================================================  ADPGADBS0  ======================================================= */
15144  #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
15145  #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
15146 /* =======================================================  ADPGADBS1  ======================================================= */
15147  #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
15148  #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
15149 /* =======================================================  ADREFMON  ======================================================== */
15150  #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
15151  #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
15152  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
15153  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
15154 
15155 /* =========================================================================================================================== */
15156 /* ================                                           R_BUS                                           ================ */
15157 /* =========================================================================================================================== */
15158 
15159 /* ========================================================  CSRECEN  ======================================================== */
15160  #define R_BUS_CSRECEN_RCVENM_Pos        (8UL)       /*!< RCVENM (Bit 8)                                        */
15161  #define R_BUS_CSRECEN_RCVENM_Msk        (0x100UL)   /*!< RCVENM (Bitfield-Mask: 0x01)                          */
15162  #define R_BUS_CSRECEN_RCVEN_Pos         (0UL)       /*!< RCVEN (Bit 0)                                         */
15163  #define R_BUS_CSRECEN_RCVEN_Msk         (0x1UL)     /*!< RCVEN (Bitfield-Mask: 0x01)                           */
15164 /* ========================================================  BUSMABT  ======================================================== */
15165  #define R_BUS_BUSMABT_ARBS_Pos          (0UL)       /*!< ARBS (Bit 0)                                          */
15166  #define R_BUS_BUSMABT_ARBS_Msk          (0x1UL)     /*!< ARBS (Bitfield-Mask: 0x01)                            */
15167 /* =======================================================  BUSDIVBYP  ======================================================= */
15168  #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos    (16UL)      /*!< CPU0SBPE (Bit 16)                                     */
15169  #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk    (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01)                        */
15170  #define R_BUS_BUSDIVBYP_GDSSBPE_Pos     (3UL)       /*!< GDSSBPE (Bit 3)                                       */
15171  #define R_BUS_BUSDIVBYP_GDSSBPE_Msk     (0x8UL)     /*!< GDSSBPE (Bitfield-Mask: 0x01)                         */
15172  #define R_BUS_BUSDIVBYP_EDMABPE_Pos     (0UL)       /*!< EDMABPE (Bit 0)                                       */
15173  #define R_BUS_BUSDIVBYP_EDMABPE_Msk     (0x1UL)     /*!< EDMABPE (Bitfield-Mask: 0x01)                         */
15174 
15175 /* =========================================================================================================================== */
15176 /* ================                                           R_CAC                                           ================ */
15177 /* =========================================================================================================================== */
15178 
15179 /* =========================================================  CACR0  ========================================================= */
15180  #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
15181  #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
15182 /* =========================================================  CACR1  ========================================================= */
15183  #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
15184  #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
15185  #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
15186  #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
15187  #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
15188  #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
15189  #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
15190  #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
15191 /* =========================================================  CACR2  ========================================================= */
15192  #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
15193  #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
15194  #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
15195  #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
15196  #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
15197  #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
15198  #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
15199  #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
15200 /* =========================================================  CAICR  ========================================================= */
15201  #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
15202  #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
15203  #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
15204  #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
15205  #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
15206  #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
15207  #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
15208  #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
15209  #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
15210  #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
15211  #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
15212  #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
15213 /* =========================================================  CASTR  ========================================================= */
15214  #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
15215  #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
15216  #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
15217  #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
15218  #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
15219  #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
15220 /* ========================================================  CAULVR  ========================================================= */
15221  #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
15222  #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
15223 /* ========================================================  CALLVR  ========================================================= */
15224  #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
15225  #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
15226 /* ========================================================  CACNTBR  ======================================================== */
15227  #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
15228  #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
15229 
15230 /* =========================================================================================================================== */
15231 /* ================                                          R_CAN0                                           ================ */
15232 /* =========================================================================================================================== */
15233 
15234 /* ==========================================================  MKR  ========================================================== */
15235  #define R_CAN0_MKR_SID_Pos              (18UL)         /*!< SID (Bit 18)                                          */
15236  #define R_CAN0_MKR_SID_Msk              (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
15237  #define R_CAN0_MKR_EID_Pos              (0UL)          /*!< EID (Bit 0)                                           */
15238  #define R_CAN0_MKR_EID_Msk              (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
15239 /* =========================================================  FIDCR  ========================================================= */
15240  #define R_CAN0_FIDCR_IDE_Pos            (31UL)         /*!< IDE (Bit 31)                                          */
15241  #define R_CAN0_FIDCR_IDE_Msk            (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01)                             */
15242  #define R_CAN0_FIDCR_RTR_Pos            (30UL)         /*!< RTR (Bit 30)                                          */
15243  #define R_CAN0_FIDCR_RTR_Msk            (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01)                             */
15244  #define R_CAN0_FIDCR_SID_Pos            (18UL)         /*!< SID (Bit 18)                                          */
15245  #define R_CAN0_FIDCR_SID_Msk            (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff)                            */
15246  #define R_CAN0_FIDCR_EID_Pos            (0UL)          /*!< EID (Bit 0)                                           */
15247  #define R_CAN0_FIDCR_EID_Msk            (0x3ffffUL)    /*!< EID (Bitfield-Mask: 0x3ffff)                          */
15248 /* ========================================================  MKIVLR  ========================================================= */
15249  #define R_CAN0_MKIVLR_MB31_Pos          (31UL)         /*!< MB31 (Bit 31)                                         */
15250  #define R_CAN0_MKIVLR_MB31_Msk          (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01)                            */
15251  #define R_CAN0_MKIVLR_MB30_Pos          (30UL)         /*!< MB30 (Bit 30)                                         */
15252  #define R_CAN0_MKIVLR_MB30_Msk          (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01)                            */
15253  #define R_CAN0_MKIVLR_MB29_Pos          (29UL)         /*!< MB29 (Bit 29)                                         */
15254  #define R_CAN0_MKIVLR_MB29_Msk          (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
15255  #define R_CAN0_MKIVLR_MB28_Pos          (28UL)         /*!< MB28 (Bit 28)                                         */
15256  #define R_CAN0_MKIVLR_MB28_Msk          (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
15257  #define R_CAN0_MKIVLR_MB27_Pos          (27UL)         /*!< MB27 (Bit 27)                                         */
15258  #define R_CAN0_MKIVLR_MB27_Msk          (0x8000000UL)  /*!< MB27 (Bitfield-Mask: 0x01)                            */
15259  #define R_CAN0_MKIVLR_MB26_Pos          (26UL)         /*!< MB26 (Bit 26)                                         */
15260  #define R_CAN0_MKIVLR_MB26_Msk          (0x4000000UL)  /*!< MB26 (Bitfield-Mask: 0x01)                            */
15261  #define R_CAN0_MKIVLR_MB25_Pos          (25UL)         /*!< MB25 (Bit 25)                                         */
15262  #define R_CAN0_MKIVLR_MB25_Msk          (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
15263  #define R_CAN0_MKIVLR_MB24_Pos          (24UL)         /*!< MB24 (Bit 24)                                         */
15264  #define R_CAN0_MKIVLR_MB24_Msk          (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
15265  #define R_CAN0_MKIVLR_MB23_Pos          (23UL)         /*!< MB23 (Bit 23)                                         */
15266  #define R_CAN0_MKIVLR_MB23_Msk          (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
15267  #define R_CAN0_MKIVLR_MB22_Pos          (22UL)         /*!< MB22 (Bit 22)                                         */
15268  #define R_CAN0_MKIVLR_MB22_Msk          (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
15269  #define R_CAN0_MKIVLR_MB21_Pos          (21UL)         /*!< MB21 (Bit 21)                                         */
15270  #define R_CAN0_MKIVLR_MB21_Msk          (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
15271  #define R_CAN0_MKIVLR_MB20_Pos          (20UL)         /*!< MB20 (Bit 20)                                         */
15272  #define R_CAN0_MKIVLR_MB20_Msk          (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
15273  #define R_CAN0_MKIVLR_MB19_Pos          (19UL)         /*!< MB19 (Bit 19)                                         */
15274  #define R_CAN0_MKIVLR_MB19_Msk          (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
15275  #define R_CAN0_MKIVLR_MB18_Pos          (18UL)         /*!< MB18 (Bit 18)                                         */
15276  #define R_CAN0_MKIVLR_MB18_Msk          (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
15277  #define R_CAN0_MKIVLR_MB17_Pos          (17UL)         /*!< MB17 (Bit 17)                                         */
15278  #define R_CAN0_MKIVLR_MB17_Msk          (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
15279  #define R_CAN0_MKIVLR_MB16_Pos          (16UL)         /*!< MB16 (Bit 16)                                         */
15280  #define R_CAN0_MKIVLR_MB16_Msk          (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
15281  #define R_CAN0_MKIVLR_MB15_Pos          (15UL)         /*!< MB15 (Bit 15)                                         */
15282  #define R_CAN0_MKIVLR_MB15_Msk          (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
15283  #define R_CAN0_MKIVLR_MB14_Pos          (14UL)         /*!< MB14 (Bit 14)                                         */
15284  #define R_CAN0_MKIVLR_MB14_Msk          (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
15285  #define R_CAN0_MKIVLR_MB13_Pos          (13UL)         /*!< MB13 (Bit 13)                                         */
15286  #define R_CAN0_MKIVLR_MB13_Msk          (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
15287  #define R_CAN0_MKIVLR_MB12_Pos          (12UL)         /*!< MB12 (Bit 12)                                         */
15288  #define R_CAN0_MKIVLR_MB12_Msk          (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
15289  #define R_CAN0_MKIVLR_MB11_Pos          (11UL)         /*!< MB11 (Bit 11)                                         */
15290  #define R_CAN0_MKIVLR_MB11_Msk          (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
15291  #define R_CAN0_MKIVLR_MB10_Pos          (10UL)         /*!< MB10 (Bit 10)                                         */
15292  #define R_CAN0_MKIVLR_MB10_Msk          (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
15293  #define R_CAN0_MKIVLR_MB9_Pos           (9UL)          /*!< MB9 (Bit 9)                                           */
15294  #define R_CAN0_MKIVLR_MB9_Msk           (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
15295  #define R_CAN0_MKIVLR_MB8_Pos           (8UL)          /*!< MB8 (Bit 8)                                           */
15296  #define R_CAN0_MKIVLR_MB8_Msk           (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
15297  #define R_CAN0_MKIVLR_MB7_Pos           (7UL)          /*!< MB7 (Bit 7)                                           */
15298  #define R_CAN0_MKIVLR_MB7_Msk           (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
15299  #define R_CAN0_MKIVLR_MB6_Pos           (6UL)          /*!< MB6 (Bit 6)                                           */
15300  #define R_CAN0_MKIVLR_MB6_Msk           (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
15301  #define R_CAN0_MKIVLR_MB5_Pos           (5UL)          /*!< MB5 (Bit 5)                                           */
15302  #define R_CAN0_MKIVLR_MB5_Msk           (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
15303  #define R_CAN0_MKIVLR_MB4_Pos           (4UL)          /*!< MB4 (Bit 4)                                           */
15304  #define R_CAN0_MKIVLR_MB4_Msk           (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
15305  #define R_CAN0_MKIVLR_MB3_Pos           (3UL)          /*!< MB3 (Bit 3)                                           */
15306  #define R_CAN0_MKIVLR_MB3_Msk           (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
15307  #define R_CAN0_MKIVLR_MB2_Pos           (2UL)          /*!< MB2 (Bit 2)                                           */
15308  #define R_CAN0_MKIVLR_MB2_Msk           (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
15309  #define R_CAN0_MKIVLR_MB1_Pos           (1UL)          /*!< MB1 (Bit 1)                                           */
15310  #define R_CAN0_MKIVLR_MB1_Msk           (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
15311  #define R_CAN0_MKIVLR_MB0_Pos           (0UL)          /*!< MB0 (Bit 0)                                           */
15312  #define R_CAN0_MKIVLR_MB0_Msk           (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
15313 /* =========================================================  MIER  ========================================================== */
15314  #define R_CAN0_MIER_MB31_Pos            (31UL)         /*!< MB31 (Bit 31)                                         */
15315  #define R_CAN0_MIER_MB31_Msk            (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01)                            */
15316  #define R_CAN0_MIER_MB30_Pos            (30UL)         /*!< MB30 (Bit 30)                                         */
15317  #define R_CAN0_MIER_MB30_Msk            (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01)                            */
15318  #define R_CAN0_MIER_MB29_Pos            (29UL)         /*!< MB29 (Bit 29)                                         */
15319  #define R_CAN0_MIER_MB29_Msk            (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
15320  #define R_CAN0_MIER_MB28_Pos            (28UL)         /*!< MB28 (Bit 28)                                         */
15321  #define R_CAN0_MIER_MB28_Msk            (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
15322  #define R_CAN0_MIER_MB27_Pos            (27UL)         /*!< MB27 (Bit 27)                                         */
15323  #define R_CAN0_MIER_MB27_Msk            (0x8000000UL)  /*!< MB27 (Bitfield-Mask: 0x01)                            */
15324  #define R_CAN0_MIER_MB26_Pos            (26UL)         /*!< MB26 (Bit 26)                                         */
15325  #define R_CAN0_MIER_MB26_Msk            (0x4000000UL)  /*!< MB26 (Bitfield-Mask: 0x01)                            */
15326  #define R_CAN0_MIER_MB25_Pos            (25UL)         /*!< MB25 (Bit 25)                                         */
15327  #define R_CAN0_MIER_MB25_Msk            (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
15328  #define R_CAN0_MIER_MB24_Pos            (24UL)         /*!< MB24 (Bit 24)                                         */
15329  #define R_CAN0_MIER_MB24_Msk            (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
15330  #define R_CAN0_MIER_MB23_Pos            (23UL)         /*!< MB23 (Bit 23)                                         */
15331  #define R_CAN0_MIER_MB23_Msk            (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
15332  #define R_CAN0_MIER_MB22_Pos            (22UL)         /*!< MB22 (Bit 22)                                         */
15333  #define R_CAN0_MIER_MB22_Msk            (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
15334  #define R_CAN0_MIER_MB21_Pos            (21UL)         /*!< MB21 (Bit 21)                                         */
15335  #define R_CAN0_MIER_MB21_Msk            (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
15336  #define R_CAN0_MIER_MB20_Pos            (20UL)         /*!< MB20 (Bit 20)                                         */
15337  #define R_CAN0_MIER_MB20_Msk            (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
15338  #define R_CAN0_MIER_MB19_Pos            (19UL)         /*!< MB19 (Bit 19)                                         */
15339  #define R_CAN0_MIER_MB19_Msk            (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
15340  #define R_CAN0_MIER_MB18_Pos            (18UL)         /*!< MB18 (Bit 18)                                         */
15341  #define R_CAN0_MIER_MB18_Msk            (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
15342  #define R_CAN0_MIER_MB17_Pos            (17UL)         /*!< MB17 (Bit 17)                                         */
15343  #define R_CAN0_MIER_MB17_Msk            (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
15344  #define R_CAN0_MIER_MB16_Pos            (16UL)         /*!< MB16 (Bit 16)                                         */
15345  #define R_CAN0_MIER_MB16_Msk            (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
15346  #define R_CAN0_MIER_MB15_Pos            (15UL)         /*!< MB15 (Bit 15)                                         */
15347  #define R_CAN0_MIER_MB15_Msk            (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
15348  #define R_CAN0_MIER_MB14_Pos            (14UL)         /*!< MB14 (Bit 14)                                         */
15349  #define R_CAN0_MIER_MB14_Msk            (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
15350  #define R_CAN0_MIER_MB13_Pos            (13UL)         /*!< MB13 (Bit 13)                                         */
15351  #define R_CAN0_MIER_MB13_Msk            (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
15352  #define R_CAN0_MIER_MB12_Pos            (12UL)         /*!< MB12 (Bit 12)                                         */
15353  #define R_CAN0_MIER_MB12_Msk            (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
15354  #define R_CAN0_MIER_MB11_Pos            (11UL)         /*!< MB11 (Bit 11)                                         */
15355  #define R_CAN0_MIER_MB11_Msk            (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
15356  #define R_CAN0_MIER_MB10_Pos            (10UL)         /*!< MB10 (Bit 10)                                         */
15357  #define R_CAN0_MIER_MB10_Msk            (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
15358  #define R_CAN0_MIER_MB9_Pos             (9UL)          /*!< MB9 (Bit 9)                                           */
15359  #define R_CAN0_MIER_MB9_Msk             (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
15360  #define R_CAN0_MIER_MB8_Pos             (8UL)          /*!< MB8 (Bit 8)                                           */
15361  #define R_CAN0_MIER_MB8_Msk             (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
15362  #define R_CAN0_MIER_MB7_Pos             (7UL)          /*!< MB7 (Bit 7)                                           */
15363  #define R_CAN0_MIER_MB7_Msk             (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
15364  #define R_CAN0_MIER_MB6_Pos             (6UL)          /*!< MB6 (Bit 6)                                           */
15365  #define R_CAN0_MIER_MB6_Msk             (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
15366  #define R_CAN0_MIER_MB5_Pos             (5UL)          /*!< MB5 (Bit 5)                                           */
15367  #define R_CAN0_MIER_MB5_Msk             (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
15368  #define R_CAN0_MIER_MB4_Pos             (4UL)          /*!< MB4 (Bit 4)                                           */
15369  #define R_CAN0_MIER_MB4_Msk             (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
15370  #define R_CAN0_MIER_MB3_Pos             (3UL)          /*!< MB3 (Bit 3)                                           */
15371  #define R_CAN0_MIER_MB3_Msk             (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
15372  #define R_CAN0_MIER_MB2_Pos             (2UL)          /*!< MB2 (Bit 2)                                           */
15373  #define R_CAN0_MIER_MB2_Msk             (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
15374  #define R_CAN0_MIER_MB1_Pos             (1UL)          /*!< MB1 (Bit 1)                                           */
15375  #define R_CAN0_MIER_MB1_Msk             (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
15376  #define R_CAN0_MIER_MB0_Pos             (0UL)          /*!< MB0 (Bit 0)                                           */
15377  #define R_CAN0_MIER_MB0_Msk             (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
15378 /* =======================================================  MIER_FIFO  ======================================================= */
15379  #define R_CAN0_MIER_FIFO_MB29_Pos       (29UL)         /*!< MB29 (Bit 29)                                         */
15380  #define R_CAN0_MIER_FIFO_MB29_Msk       (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01)                            */
15381  #define R_CAN0_MIER_FIFO_MB28_Pos       (28UL)         /*!< MB28 (Bit 28)                                         */
15382  #define R_CAN0_MIER_FIFO_MB28_Msk       (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01)                            */
15383  #define R_CAN0_MIER_FIFO_MB25_Pos       (25UL)         /*!< MB25 (Bit 25)                                         */
15384  #define R_CAN0_MIER_FIFO_MB25_Msk       (0x2000000UL)  /*!< MB25 (Bitfield-Mask: 0x01)                            */
15385  #define R_CAN0_MIER_FIFO_MB24_Pos       (24UL)         /*!< MB24 (Bit 24)                                         */
15386  #define R_CAN0_MIER_FIFO_MB24_Msk       (0x1000000UL)  /*!< MB24 (Bitfield-Mask: 0x01)                            */
15387  #define R_CAN0_MIER_FIFO_MB23_Pos       (23UL)         /*!< MB23 (Bit 23)                                         */
15388  #define R_CAN0_MIER_FIFO_MB23_Msk       (0x800000UL)   /*!< MB23 (Bitfield-Mask: 0x01)                            */
15389  #define R_CAN0_MIER_FIFO_MB22_Pos       (22UL)         /*!< MB22 (Bit 22)                                         */
15390  #define R_CAN0_MIER_FIFO_MB22_Msk       (0x400000UL)   /*!< MB22 (Bitfield-Mask: 0x01)                            */
15391  #define R_CAN0_MIER_FIFO_MB21_Pos       (21UL)         /*!< MB21 (Bit 21)                                         */
15392  #define R_CAN0_MIER_FIFO_MB21_Msk       (0x200000UL)   /*!< MB21 (Bitfield-Mask: 0x01)                            */
15393  #define R_CAN0_MIER_FIFO_MB20_Pos       (20UL)         /*!< MB20 (Bit 20)                                         */
15394  #define R_CAN0_MIER_FIFO_MB20_Msk       (0x100000UL)   /*!< MB20 (Bitfield-Mask: 0x01)                            */
15395  #define R_CAN0_MIER_FIFO_MB19_Pos       (19UL)         /*!< MB19 (Bit 19)                                         */
15396  #define R_CAN0_MIER_FIFO_MB19_Msk       (0x80000UL)    /*!< MB19 (Bitfield-Mask: 0x01)                            */
15397  #define R_CAN0_MIER_FIFO_MB18_Pos       (18UL)         /*!< MB18 (Bit 18)                                         */
15398  #define R_CAN0_MIER_FIFO_MB18_Msk       (0x40000UL)    /*!< MB18 (Bitfield-Mask: 0x01)                            */
15399  #define R_CAN0_MIER_FIFO_MB17_Pos       (17UL)         /*!< MB17 (Bit 17)                                         */
15400  #define R_CAN0_MIER_FIFO_MB17_Msk       (0x20000UL)    /*!< MB17 (Bitfield-Mask: 0x01)                            */
15401  #define R_CAN0_MIER_FIFO_MB16_Pos       (16UL)         /*!< MB16 (Bit 16)                                         */
15402  #define R_CAN0_MIER_FIFO_MB16_Msk       (0x10000UL)    /*!< MB16 (Bitfield-Mask: 0x01)                            */
15403  #define R_CAN0_MIER_FIFO_MB15_Pos       (15UL)         /*!< MB15 (Bit 15)                                         */
15404  #define R_CAN0_MIER_FIFO_MB15_Msk       (0x8000UL)     /*!< MB15 (Bitfield-Mask: 0x01)                            */
15405  #define R_CAN0_MIER_FIFO_MB14_Pos       (14UL)         /*!< MB14 (Bit 14)                                         */
15406  #define R_CAN0_MIER_FIFO_MB14_Msk       (0x4000UL)     /*!< MB14 (Bitfield-Mask: 0x01)                            */
15407  #define R_CAN0_MIER_FIFO_MB13_Pos       (13UL)         /*!< MB13 (Bit 13)                                         */
15408  #define R_CAN0_MIER_FIFO_MB13_Msk       (0x2000UL)     /*!< MB13 (Bitfield-Mask: 0x01)                            */
15409  #define R_CAN0_MIER_FIFO_MB12_Pos       (12UL)         /*!< MB12 (Bit 12)                                         */
15410  #define R_CAN0_MIER_FIFO_MB12_Msk       (0x1000UL)     /*!< MB12 (Bitfield-Mask: 0x01)                            */
15411  #define R_CAN0_MIER_FIFO_MB11_Pos       (11UL)         /*!< MB11 (Bit 11)                                         */
15412  #define R_CAN0_MIER_FIFO_MB11_Msk       (0x800UL)      /*!< MB11 (Bitfield-Mask: 0x01)                            */
15413  #define R_CAN0_MIER_FIFO_MB10_Pos       (10UL)         /*!< MB10 (Bit 10)                                         */
15414  #define R_CAN0_MIER_FIFO_MB10_Msk       (0x400UL)      /*!< MB10 (Bitfield-Mask: 0x01)                            */
15415  #define R_CAN0_MIER_FIFO_MB9_Pos        (9UL)          /*!< MB9 (Bit 9)                                           */
15416  #define R_CAN0_MIER_FIFO_MB9_Msk        (0x200UL)      /*!< MB9 (Bitfield-Mask: 0x01)                             */
15417  #define R_CAN0_MIER_FIFO_MB8_Pos        (8UL)          /*!< MB8 (Bit 8)                                           */
15418  #define R_CAN0_MIER_FIFO_MB8_Msk        (0x100UL)      /*!< MB8 (Bitfield-Mask: 0x01)                             */
15419  #define R_CAN0_MIER_FIFO_MB7_Pos        (7UL)          /*!< MB7 (Bit 7)                                           */
15420  #define R_CAN0_MIER_FIFO_MB7_Msk        (0x80UL)       /*!< MB7 (Bitfield-Mask: 0x01)                             */
15421  #define R_CAN0_MIER_FIFO_MB6_Pos        (6UL)          /*!< MB6 (Bit 6)                                           */
15422  #define R_CAN0_MIER_FIFO_MB6_Msk        (0x40UL)       /*!< MB6 (Bitfield-Mask: 0x01)                             */
15423  #define R_CAN0_MIER_FIFO_MB5_Pos        (5UL)          /*!< MB5 (Bit 5)                                           */
15424  #define R_CAN0_MIER_FIFO_MB5_Msk        (0x20UL)       /*!< MB5 (Bitfield-Mask: 0x01)                             */
15425  #define R_CAN0_MIER_FIFO_MB4_Pos        (4UL)          /*!< MB4 (Bit 4)                                           */
15426  #define R_CAN0_MIER_FIFO_MB4_Msk        (0x10UL)       /*!< MB4 (Bitfield-Mask: 0x01)                             */
15427  #define R_CAN0_MIER_FIFO_MB3_Pos        (3UL)          /*!< MB3 (Bit 3)                                           */
15428  #define R_CAN0_MIER_FIFO_MB3_Msk        (0x8UL)        /*!< MB3 (Bitfield-Mask: 0x01)                             */
15429  #define R_CAN0_MIER_FIFO_MB2_Pos        (2UL)          /*!< MB2 (Bit 2)                                           */
15430  #define R_CAN0_MIER_FIFO_MB2_Msk        (0x4UL)        /*!< MB2 (Bitfield-Mask: 0x01)                             */
15431  #define R_CAN0_MIER_FIFO_MB1_Pos        (1UL)          /*!< MB1 (Bit 1)                                           */
15432  #define R_CAN0_MIER_FIFO_MB1_Msk        (0x2UL)        /*!< MB1 (Bitfield-Mask: 0x01)                             */
15433  #define R_CAN0_MIER_FIFO_MB0_Pos        (0UL)          /*!< MB0 (Bit 0)                                           */
15434  #define R_CAN0_MIER_FIFO_MB0_Msk        (0x1UL)        /*!< MB0 (Bitfield-Mask: 0x01)                             */
15435 /* ========================================================  MCTL_TX  ======================================================== */
15436  #define R_CAN0_MCTL_TX_TRMREQ_Pos       (7UL)          /*!< TRMREQ (Bit 7)                                        */
15437  #define R_CAN0_MCTL_TX_TRMREQ_Msk       (0x80UL)       /*!< TRMREQ (Bitfield-Mask: 0x01)                          */
15438  #define R_CAN0_MCTL_TX_RECREQ_Pos       (6UL)          /*!< RECREQ (Bit 6)                                        */
15439  #define R_CAN0_MCTL_TX_RECREQ_Msk       (0x40UL)       /*!< RECREQ (Bitfield-Mask: 0x01)                          */
15440  #define R_CAN0_MCTL_TX_ONESHOT_Pos      (4UL)          /*!< ONESHOT (Bit 4)                                       */
15441  #define R_CAN0_MCTL_TX_ONESHOT_Msk      (0x10UL)       /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
15442  #define R_CAN0_MCTL_TX_TRMABT_Pos       (2UL)          /*!< TRMABT (Bit 2)                                        */
15443  #define R_CAN0_MCTL_TX_TRMABT_Msk       (0x4UL)        /*!< TRMABT (Bitfield-Mask: 0x01)                          */
15444  #define R_CAN0_MCTL_TX_TRMACTIVE_Pos    (1UL)          /*!< TRMACTIVE (Bit 1)                                     */
15445  #define R_CAN0_MCTL_TX_TRMACTIVE_Msk    (0x2UL)        /*!< TRMACTIVE (Bitfield-Mask: 0x01)                       */
15446  #define R_CAN0_MCTL_TX_SENTDATA_Pos     (0UL)          /*!< SENTDATA (Bit 0)                                      */
15447  #define R_CAN0_MCTL_TX_SENTDATA_Msk     (0x1UL)        /*!< SENTDATA (Bitfield-Mask: 0x01)                        */
15448 /* ========================================================  MCTL_RX  ======================================================== */
15449  #define R_CAN0_MCTL_RX_TRMREQ_Pos       (7UL)          /*!< TRMREQ (Bit 7)                                        */
15450  #define R_CAN0_MCTL_RX_TRMREQ_Msk       (0x80UL)       /*!< TRMREQ (Bitfield-Mask: 0x01)                          */
15451  #define R_CAN0_MCTL_RX_RECREQ_Pos       (6UL)          /*!< RECREQ (Bit 6)                                        */
15452  #define R_CAN0_MCTL_RX_RECREQ_Msk       (0x40UL)       /*!< RECREQ (Bitfield-Mask: 0x01)                          */
15453  #define R_CAN0_MCTL_RX_ONESHOT_Pos      (4UL)          /*!< ONESHOT (Bit 4)                                       */
15454  #define R_CAN0_MCTL_RX_ONESHOT_Msk      (0x10UL)       /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
15455  #define R_CAN0_MCTL_RX_MSGLOST_Pos      (2UL)          /*!< MSGLOST (Bit 2)                                       */
15456  #define R_CAN0_MCTL_RX_MSGLOST_Msk      (0x4UL)        /*!< MSGLOST (Bitfield-Mask: 0x01)                         */
15457  #define R_CAN0_MCTL_RX_INVALDATA_Pos    (1UL)          /*!< INVALDATA (Bit 1)                                     */
15458  #define R_CAN0_MCTL_RX_INVALDATA_Msk    (0x2UL)        /*!< INVALDATA (Bitfield-Mask: 0x01)                       */
15459  #define R_CAN0_MCTL_RX_NEWDATA_Pos      (0UL)          /*!< NEWDATA (Bit 0)                                       */
15460  #define R_CAN0_MCTL_RX_NEWDATA_Msk      (0x1UL)        /*!< NEWDATA (Bitfield-Mask: 0x01)                         */
15461 /* =========================================================  CTLR  ========================================================== */
15462  #define R_CAN0_CTLR_RBOC_Pos            (13UL)         /*!< RBOC (Bit 13)                                         */
15463  #define R_CAN0_CTLR_RBOC_Msk            (0x2000UL)     /*!< RBOC (Bitfield-Mask: 0x01)                            */
15464  #define R_CAN0_CTLR_BOM_Pos             (11UL)         /*!< BOM (Bit 11)                                          */
15465  #define R_CAN0_CTLR_BOM_Msk             (0x1800UL)     /*!< BOM (Bitfield-Mask: 0x03)                             */
15466  #define R_CAN0_CTLR_SLPM_Pos            (10UL)         /*!< SLPM (Bit 10)                                         */
15467  #define R_CAN0_CTLR_SLPM_Msk            (0x400UL)      /*!< SLPM (Bitfield-Mask: 0x01)                            */
15468  #define R_CAN0_CTLR_CANM_Pos            (8UL)          /*!< CANM (Bit 8)                                          */
15469  #define R_CAN0_CTLR_CANM_Msk            (0x300UL)      /*!< CANM (Bitfield-Mask: 0x03)                            */
15470  #define R_CAN0_CTLR_TSPS_Pos            (6UL)          /*!< TSPS (Bit 6)                                          */
15471  #define R_CAN0_CTLR_TSPS_Msk            (0xc0UL)       /*!< TSPS (Bitfield-Mask: 0x03)                            */
15472  #define R_CAN0_CTLR_TSRC_Pos            (5UL)          /*!< TSRC (Bit 5)                                          */
15473  #define R_CAN0_CTLR_TSRC_Msk            (0x20UL)       /*!< TSRC (Bitfield-Mask: 0x01)                            */
15474  #define R_CAN0_CTLR_TPM_Pos             (4UL)          /*!< TPM (Bit 4)                                           */
15475  #define R_CAN0_CTLR_TPM_Msk             (0x10UL)       /*!< TPM (Bitfield-Mask: 0x01)                             */
15476  #define R_CAN0_CTLR_MLM_Pos             (3UL)          /*!< MLM (Bit 3)                                           */
15477  #define R_CAN0_CTLR_MLM_Msk             (0x8UL)        /*!< MLM (Bitfield-Mask: 0x01)                             */
15478  #define R_CAN0_CTLR_IDFM_Pos            (1UL)          /*!< IDFM (Bit 1)                                          */
15479  #define R_CAN0_CTLR_IDFM_Msk            (0x6UL)        /*!< IDFM (Bitfield-Mask: 0x03)                            */
15480  #define R_CAN0_CTLR_MBM_Pos             (0UL)          /*!< MBM (Bit 0)                                           */
15481  #define R_CAN0_CTLR_MBM_Msk             (0x1UL)        /*!< MBM (Bitfield-Mask: 0x01)                             */
15482 /* ==========================================================  STR  ========================================================== */
15483  #define R_CAN0_STR_RECST_Pos            (14UL)         /*!< RECST (Bit 14)                                        */
15484  #define R_CAN0_STR_RECST_Msk            (0x4000UL)     /*!< RECST (Bitfield-Mask: 0x01)                           */
15485  #define R_CAN0_STR_TRMST_Pos            (13UL)         /*!< TRMST (Bit 13)                                        */
15486  #define R_CAN0_STR_TRMST_Msk            (0x2000UL)     /*!< TRMST (Bitfield-Mask: 0x01)                           */
15487  #define R_CAN0_STR_BOST_Pos             (12UL)         /*!< BOST (Bit 12)                                         */
15488  #define R_CAN0_STR_BOST_Msk             (0x1000UL)     /*!< BOST (Bitfield-Mask: 0x01)                            */
15489  #define R_CAN0_STR_EPST_Pos             (11UL)         /*!< EPST (Bit 11)                                         */
15490  #define R_CAN0_STR_EPST_Msk             (0x800UL)      /*!< EPST (Bitfield-Mask: 0x01)                            */
15491  #define R_CAN0_STR_SLPST_Pos            (10UL)         /*!< SLPST (Bit 10)                                        */
15492  #define R_CAN0_STR_SLPST_Msk            (0x400UL)      /*!< SLPST (Bitfield-Mask: 0x01)                           */
15493  #define R_CAN0_STR_HLTST_Pos            (9UL)          /*!< HLTST (Bit 9)                                         */
15494  #define R_CAN0_STR_HLTST_Msk            (0x200UL)      /*!< HLTST (Bitfield-Mask: 0x01)                           */
15495  #define R_CAN0_STR_RSTST_Pos            (8UL)          /*!< RSTST (Bit 8)                                         */
15496  #define R_CAN0_STR_RSTST_Msk            (0x100UL)      /*!< RSTST (Bitfield-Mask: 0x01)                           */
15497  #define R_CAN0_STR_EST_Pos              (7UL)          /*!< EST (Bit 7)                                           */
15498  #define R_CAN0_STR_EST_Msk              (0x80UL)       /*!< EST (Bitfield-Mask: 0x01)                             */
15499  #define R_CAN0_STR_TABST_Pos            (6UL)          /*!< TABST (Bit 6)                                         */
15500  #define R_CAN0_STR_TABST_Msk            (0x40UL)       /*!< TABST (Bitfield-Mask: 0x01)                           */
15501  #define R_CAN0_STR_FMLST_Pos            (5UL)          /*!< FMLST (Bit 5)                                         */
15502  #define R_CAN0_STR_FMLST_Msk            (0x20UL)       /*!< FMLST (Bitfield-Mask: 0x01)                           */
15503  #define R_CAN0_STR_NMLST_Pos            (4UL)          /*!< NMLST (Bit 4)                                         */
15504  #define R_CAN0_STR_NMLST_Msk            (0x10UL)       /*!< NMLST (Bitfield-Mask: 0x01)                           */
15505  #define R_CAN0_STR_TFST_Pos             (3UL)          /*!< TFST (Bit 3)                                          */
15506  #define R_CAN0_STR_TFST_Msk             (0x8UL)        /*!< TFST (Bitfield-Mask: 0x01)                            */
15507  #define R_CAN0_STR_RFST_Pos             (2UL)          /*!< RFST (Bit 2)                                          */
15508  #define R_CAN0_STR_RFST_Msk             (0x4UL)        /*!< RFST (Bitfield-Mask: 0x01)                            */
15509  #define R_CAN0_STR_SDST_Pos             (1UL)          /*!< SDST (Bit 1)                                          */
15510  #define R_CAN0_STR_SDST_Msk             (0x2UL)        /*!< SDST (Bitfield-Mask: 0x01)                            */
15511  #define R_CAN0_STR_NDST_Pos             (0UL)          /*!< NDST (Bit 0)                                          */
15512  #define R_CAN0_STR_NDST_Msk             (0x1UL)        /*!< NDST (Bitfield-Mask: 0x01)                            */
15513 /* ==========================================================  BCR  ========================================================== */
15514  #define R_CAN0_BCR_TSEG1_Pos            (28UL)         /*!< TSEG1 (Bit 28)                                        */
15515  #define R_CAN0_BCR_TSEG1_Msk            (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f)                           */
15516  #define R_CAN0_BCR_BRP_Pos              (16UL)         /*!< BRP (Bit 16)                                          */
15517  #define R_CAN0_BCR_BRP_Msk              (0x3ff0000UL)  /*!< BRP (Bitfield-Mask: 0x3ff)                            */
15518  #define R_CAN0_BCR_SJW_Pos              (12UL)         /*!< SJW (Bit 12)                                          */
15519  #define R_CAN0_BCR_SJW_Msk              (0x3000UL)     /*!< SJW (Bitfield-Mask: 0x03)                             */
15520  #define R_CAN0_BCR_TSEG2_Pos            (8UL)          /*!< TSEG2 (Bit 8)                                         */
15521  #define R_CAN0_BCR_TSEG2_Msk            (0x700UL)      /*!< TSEG2 (Bitfield-Mask: 0x07)                           */
15522  #define R_CAN0_BCR_CCLKS_Pos            (0UL)          /*!< CCLKS (Bit 0)                                         */
15523  #define R_CAN0_BCR_CCLKS_Msk            (0x1UL)        /*!< CCLKS (Bitfield-Mask: 0x01)                           */
15524 /* =========================================================  RFCR  ========================================================== */
15525  #define R_CAN0_RFCR_RFEST_Pos           (7UL)          /*!< RFEST (Bit 7)                                         */
15526  #define R_CAN0_RFCR_RFEST_Msk           (0x80UL)       /*!< RFEST (Bitfield-Mask: 0x01)                           */
15527  #define R_CAN0_RFCR_RFWST_Pos           (6UL)          /*!< RFWST (Bit 6)                                         */
15528  #define R_CAN0_RFCR_RFWST_Msk           (0x40UL)       /*!< RFWST (Bitfield-Mask: 0x01)                           */
15529  #define R_CAN0_RFCR_RFFST_Pos           (5UL)          /*!< RFFST (Bit 5)                                         */
15530  #define R_CAN0_RFCR_RFFST_Msk           (0x20UL)       /*!< RFFST (Bitfield-Mask: 0x01)                           */
15531  #define R_CAN0_RFCR_RFMLF_Pos           (4UL)          /*!< RFMLF (Bit 4)                                         */
15532  #define R_CAN0_RFCR_RFMLF_Msk           (0x10UL)       /*!< RFMLF (Bitfield-Mask: 0x01)                           */
15533  #define R_CAN0_RFCR_RFUST_Pos           (1UL)          /*!< RFUST (Bit 1)                                         */
15534  #define R_CAN0_RFCR_RFUST_Msk           (0xeUL)        /*!< RFUST (Bitfield-Mask: 0x07)                           */
15535  #define R_CAN0_RFCR_RFE_Pos             (0UL)          /*!< RFE (Bit 0)                                           */
15536  #define R_CAN0_RFCR_RFE_Msk             (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
15537 /* =========================================================  RFPCR  ========================================================= */
15538  #define R_CAN0_RFPCR_RFPCR_Pos          (0UL)          /*!< RFPCR (Bit 0)                                         */
15539  #define R_CAN0_RFPCR_RFPCR_Msk          (0xffUL)       /*!< RFPCR (Bitfield-Mask: 0xff)                           */
15540 /* =========================================================  TFCR  ========================================================== */
15541  #define R_CAN0_TFCR_TFEST_Pos           (7UL)          /*!< TFEST (Bit 7)                                         */
15542  #define R_CAN0_TFCR_TFEST_Msk           (0x80UL)       /*!< TFEST (Bitfield-Mask: 0x01)                           */
15543  #define R_CAN0_TFCR_TFFST_Pos           (6UL)          /*!< TFFST (Bit 6)                                         */
15544  #define R_CAN0_TFCR_TFFST_Msk           (0x40UL)       /*!< TFFST (Bitfield-Mask: 0x01)                           */
15545  #define R_CAN0_TFCR_TFUST_Pos           (1UL)          /*!< TFUST (Bit 1)                                         */
15546  #define R_CAN0_TFCR_TFUST_Msk           (0xeUL)        /*!< TFUST (Bitfield-Mask: 0x07)                           */
15547  #define R_CAN0_TFCR_TFE_Pos             (0UL)          /*!< TFE (Bit 0)                                           */
15548  #define R_CAN0_TFCR_TFE_Msk             (0x1UL)        /*!< TFE (Bitfield-Mask: 0x01)                             */
15549 /* =========================================================  TFPCR  ========================================================= */
15550  #define R_CAN0_TFPCR_TFPCR_Pos          (0UL)          /*!< TFPCR (Bit 0)                                         */
15551  #define R_CAN0_TFPCR_TFPCR_Msk          (0xffUL)       /*!< TFPCR (Bitfield-Mask: 0xff)                           */
15552 /* =========================================================  EIER  ========================================================== */
15553  #define R_CAN0_EIER_BLIE_Pos            (7UL)          /*!< BLIE (Bit 7)                                          */
15554  #define R_CAN0_EIER_BLIE_Msk            (0x80UL)       /*!< BLIE (Bitfield-Mask: 0x01)                            */
15555  #define R_CAN0_EIER_OLIE_Pos            (6UL)          /*!< OLIE (Bit 6)                                          */
15556  #define R_CAN0_EIER_OLIE_Msk            (0x40UL)       /*!< OLIE (Bitfield-Mask: 0x01)                            */
15557  #define R_CAN0_EIER_ORIE_Pos            (5UL)          /*!< ORIE (Bit 5)                                          */
15558  #define R_CAN0_EIER_ORIE_Msk            (0x20UL)       /*!< ORIE (Bitfield-Mask: 0x01)                            */
15559  #define R_CAN0_EIER_BORIE_Pos           (4UL)          /*!< BORIE (Bit 4)                                         */
15560  #define R_CAN0_EIER_BORIE_Msk           (0x10UL)       /*!< BORIE (Bitfield-Mask: 0x01)                           */
15561  #define R_CAN0_EIER_BOEIE_Pos           (3UL)          /*!< BOEIE (Bit 3)                                         */
15562  #define R_CAN0_EIER_BOEIE_Msk           (0x8UL)        /*!< BOEIE (Bitfield-Mask: 0x01)                           */
15563  #define R_CAN0_EIER_EPIE_Pos            (2UL)          /*!< EPIE (Bit 2)                                          */
15564  #define R_CAN0_EIER_EPIE_Msk            (0x4UL)        /*!< EPIE (Bitfield-Mask: 0x01)                            */
15565  #define R_CAN0_EIER_EWIE_Pos            (1UL)          /*!< EWIE (Bit 1)                                          */
15566  #define R_CAN0_EIER_EWIE_Msk            (0x2UL)        /*!< EWIE (Bitfield-Mask: 0x01)                            */
15567  #define R_CAN0_EIER_BEIE_Pos            (0UL)          /*!< BEIE (Bit 0)                                          */
15568  #define R_CAN0_EIER_BEIE_Msk            (0x1UL)        /*!< BEIE (Bitfield-Mask: 0x01)                            */
15569 /* =========================================================  EIFR  ========================================================== */
15570  #define R_CAN0_EIFR_BLIF_Pos            (7UL)          /*!< BLIF (Bit 7)                                          */
15571  #define R_CAN0_EIFR_BLIF_Msk            (0x80UL)       /*!< BLIF (Bitfield-Mask: 0x01)                            */
15572  #define R_CAN0_EIFR_OLIF_Pos            (6UL)          /*!< OLIF (Bit 6)                                          */
15573  #define R_CAN0_EIFR_OLIF_Msk            (0x40UL)       /*!< OLIF (Bitfield-Mask: 0x01)                            */
15574  #define R_CAN0_EIFR_ORIF_Pos            (5UL)          /*!< ORIF (Bit 5)                                          */
15575  #define R_CAN0_EIFR_ORIF_Msk            (0x20UL)       /*!< ORIF (Bitfield-Mask: 0x01)                            */
15576  #define R_CAN0_EIFR_BORIF_Pos           (4UL)          /*!< BORIF (Bit 4)                                         */
15577  #define R_CAN0_EIFR_BORIF_Msk           (0x10UL)       /*!< BORIF (Bitfield-Mask: 0x01)                           */
15578  #define R_CAN0_EIFR_BOEIF_Pos           (3UL)          /*!< BOEIF (Bit 3)                                         */
15579  #define R_CAN0_EIFR_BOEIF_Msk           (0x8UL)        /*!< BOEIF (Bitfield-Mask: 0x01)                           */
15580  #define R_CAN0_EIFR_EPIF_Pos            (2UL)          /*!< EPIF (Bit 2)                                          */
15581  #define R_CAN0_EIFR_EPIF_Msk            (0x4UL)        /*!< EPIF (Bitfield-Mask: 0x01)                            */
15582  #define R_CAN0_EIFR_EWIF_Pos            (1UL)          /*!< EWIF (Bit 1)                                          */
15583  #define R_CAN0_EIFR_EWIF_Msk            (0x2UL)        /*!< EWIF (Bitfield-Mask: 0x01)                            */
15584  #define R_CAN0_EIFR_BEIF_Pos            (0UL)          /*!< BEIF (Bit 0)                                          */
15585  #define R_CAN0_EIFR_BEIF_Msk            (0x1UL)        /*!< BEIF (Bitfield-Mask: 0x01)                            */
15586 /* =========================================================  RECR  ========================================================== */
15587  #define R_CAN0_RECR_RECR_Pos            (0UL)          /*!< RECR (Bit 0)                                          */
15588  #define R_CAN0_RECR_RECR_Msk            (0xffUL)       /*!< RECR (Bitfield-Mask: 0xff)                            */
15589 /* =========================================================  TECR  ========================================================== */
15590  #define R_CAN0_TECR_TECR_Pos            (0UL)          /*!< TECR (Bit 0)                                          */
15591  #define R_CAN0_TECR_TECR_Msk            (0xffUL)       /*!< TECR (Bitfield-Mask: 0xff)                            */
15592 /* =========================================================  ECSR  ========================================================== */
15593  #define R_CAN0_ECSR_EDPM_Pos            (7UL)          /*!< EDPM (Bit 7)                                          */
15594  #define R_CAN0_ECSR_EDPM_Msk            (0x80UL)       /*!< EDPM (Bitfield-Mask: 0x01)                            */
15595  #define R_CAN0_ECSR_ADEF_Pos            (6UL)          /*!< ADEF (Bit 6)                                          */
15596  #define R_CAN0_ECSR_ADEF_Msk            (0x40UL)       /*!< ADEF (Bitfield-Mask: 0x01)                            */
15597  #define R_CAN0_ECSR_BE0F_Pos            (5UL)          /*!< BE0F (Bit 5)                                          */
15598  #define R_CAN0_ECSR_BE0F_Msk            (0x20UL)       /*!< BE0F (Bitfield-Mask: 0x01)                            */
15599  #define R_CAN0_ECSR_BE1F_Pos            (4UL)          /*!< BE1F (Bit 4)                                          */
15600  #define R_CAN0_ECSR_BE1F_Msk            (0x10UL)       /*!< BE1F (Bitfield-Mask: 0x01)                            */
15601  #define R_CAN0_ECSR_CEF_Pos             (3UL)          /*!< CEF (Bit 3)                                           */
15602  #define R_CAN0_ECSR_CEF_Msk             (0x8UL)        /*!< CEF (Bitfield-Mask: 0x01)                             */
15603  #define R_CAN0_ECSR_AEF_Pos             (2UL)          /*!< AEF (Bit 2)                                           */
15604  #define R_CAN0_ECSR_AEF_Msk             (0x4UL)        /*!< AEF (Bitfield-Mask: 0x01)                             */
15605  #define R_CAN0_ECSR_FEF_Pos             (1UL)          /*!< FEF (Bit 1)                                           */
15606  #define R_CAN0_ECSR_FEF_Msk             (0x2UL)        /*!< FEF (Bitfield-Mask: 0x01)                             */
15607  #define R_CAN0_ECSR_SEF_Pos             (0UL)          /*!< SEF (Bit 0)                                           */
15608  #define R_CAN0_ECSR_SEF_Msk             (0x1UL)        /*!< SEF (Bitfield-Mask: 0x01)                             */
15609 /* =========================================================  CSSR  ========================================================== */
15610  #define R_CAN0_CSSR_CSSR_Pos            (0UL)          /*!< CSSR (Bit 0)                                          */
15611  #define R_CAN0_CSSR_CSSR_Msk            (0xffUL)       /*!< CSSR (Bitfield-Mask: 0xff)                            */
15612 /* =========================================================  MSSR  ========================================================== */
15613  #define R_CAN0_MSSR_SEST_Pos            (7UL)          /*!< SEST (Bit 7)                                          */
15614  #define R_CAN0_MSSR_SEST_Msk            (0x80UL)       /*!< SEST (Bitfield-Mask: 0x01)                            */
15615  #define R_CAN0_MSSR_MBNST_Pos           (0UL)          /*!< MBNST (Bit 0)                                         */
15616  #define R_CAN0_MSSR_MBNST_Msk           (0x1fUL)       /*!< MBNST (Bitfield-Mask: 0x1f)                           */
15617 /* =========================================================  MSMR  ========================================================== */
15618  #define R_CAN0_MSMR_MBSM_Pos            (0UL)          /*!< MBSM (Bit 0)                                          */
15619  #define R_CAN0_MSMR_MBSM_Msk            (0x3UL)        /*!< MBSM (Bitfield-Mask: 0x03)                            */
15620 /* ==========================================================  TSR  ========================================================== */
15621  #define R_CAN0_TSR_TSR_Pos              (0UL)          /*!< TSR (Bit 0)                                           */
15622  #define R_CAN0_TSR_TSR_Msk              (0xffffUL)     /*!< TSR (Bitfield-Mask: 0xffff)                           */
15623 /* =========================================================  AFSR  ========================================================== */
15624  #define R_CAN0_AFSR_AFSR_Pos            (0UL)          /*!< AFSR (Bit 0)                                          */
15625  #define R_CAN0_AFSR_AFSR_Msk            (0xffffUL)     /*!< AFSR (Bitfield-Mask: 0xffff)                          */
15626 /* ==========================================================  TCR  ========================================================== */
15627  #define R_CAN0_TCR_TSTM_Pos             (1UL)          /*!< TSTM (Bit 1)                                          */
15628  #define R_CAN0_TCR_TSTM_Msk             (0x6UL)        /*!< TSTM (Bitfield-Mask: 0x03)                            */
15629  #define R_CAN0_TCR_TSTE_Pos             (0UL)          /*!< TSTE (Bit 0)                                          */
15630  #define R_CAN0_TCR_TSTE_Msk             (0x1UL)        /*!< TSTE (Bitfield-Mask: 0x01)                            */
15631 
15632 /* =========================================================================================================================== */
15633 /* ================                                           R_CRC                                           ================ */
15634 /* =========================================================================================================================== */
15635 
15636 /* ========================================================  CRCCR0  ========================================================= */
15637  #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
15638  #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
15639  #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
15640  #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
15641  #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
15642  #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
15643 /* ========================================================  CRCCR1  ========================================================= */
15644  #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
15645  #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
15646  #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
15647  #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
15648 /* ========================================================  CRCDIR  ========================================================= */
15649  #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
15650  #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
15651 /* =======================================================  CRCDIR_BY  ======================================================= */
15652  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
15653  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
15654 /* ========================================================  CRCDOR  ========================================================= */
15655  #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
15656  #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
15657 /* =======================================================  CRCDOR_HA  ======================================================= */
15658  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
15659  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
15660 /* =======================================================  CRCDOR_BY  ======================================================= */
15661  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
15662  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
15663 /* ========================================================  CRCSAR  ========================================================= */
15664  #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
15665  #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
15666 
15667 /* =========================================================================================================================== */
15668 /* ================                                          R_CTSU                                           ================ */
15669 /* =========================================================================================================================== */
15670 
15671 /* ========================================================  CTSUCR0  ======================================================== */
15672  #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos       (7UL)      /*!< CTSUTXVSEL (Bit 7)                                    */
15673  #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk       (0x80UL)   /*!< CTSUTXVSEL (Bitfield-Mask: 0x01)                      */
15674  #define R_CTSU_CTSUCR0_CTSUINIT_Pos         (4UL)      /*!< CTSUINIT (Bit 4)                                      */
15675  #define R_CTSU_CTSUCR0_CTSUINIT_Msk         (0x10UL)   /*!< CTSUINIT (Bitfield-Mask: 0x01)                        */
15676  #define R_CTSU_CTSUCR0_CTSUIOC_Pos          (3UL)      /*!< CTSUIOC (Bit 3)                                       */
15677  #define R_CTSU_CTSUCR0_CTSUIOC_Msk          (0x8UL)    /*!< CTSUIOC (Bitfield-Mask: 0x01)                         */
15678  #define R_CTSU_CTSUCR0_CTSUSNZ_Pos          (2UL)      /*!< CTSUSNZ (Bit 2)                                       */
15679  #define R_CTSU_CTSUCR0_CTSUSNZ_Msk          (0x4UL)    /*!< CTSUSNZ (Bitfield-Mask: 0x01)                         */
15680  #define R_CTSU_CTSUCR0_CTSUCAP_Pos          (1UL)      /*!< CTSUCAP (Bit 1)                                       */
15681  #define R_CTSU_CTSUCR0_CTSUCAP_Msk          (0x2UL)    /*!< CTSUCAP (Bitfield-Mask: 0x01)                         */
15682  #define R_CTSU_CTSUCR0_CTSUSTRT_Pos         (0UL)      /*!< CTSUSTRT (Bit 0)                                      */
15683  #define R_CTSU_CTSUCR0_CTSUSTRT_Msk         (0x1UL)    /*!< CTSUSTRT (Bitfield-Mask: 0x01)                        */
15684 /* ========================================================  CTSUCR1  ======================================================== */
15685  #define R_CTSU_CTSUCR1_CTSUMD_Pos           (6UL)      /*!< CTSUMD (Bit 6)                                        */
15686  #define R_CTSU_CTSUCR1_CTSUMD_Msk           (0xc0UL)   /*!< CTSUMD (Bitfield-Mask: 0x03)                          */
15687  #define R_CTSU_CTSUCR1_CTSUCLK_Pos          (4UL)      /*!< CTSUCLK (Bit 4)                                       */
15688  #define R_CTSU_CTSUCR1_CTSUCLK_Msk          (0x30UL)   /*!< CTSUCLK (Bitfield-Mask: 0x03)                         */
15689  #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos       (3UL)      /*!< CTSUATUNE1 (Bit 3)                                    */
15690  #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk       (0x8UL)    /*!< CTSUATUNE1 (Bitfield-Mask: 0x01)                      */
15691  #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos       (2UL)      /*!< CTSUATUNE0 (Bit 2)                                    */
15692  #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk       (0x4UL)    /*!< CTSUATUNE0 (Bitfield-Mask: 0x01)                      */
15693  #define R_CTSU_CTSUCR1_CTSUCSW_Pos          (1UL)      /*!< CTSUCSW (Bit 1)                                       */
15694  #define R_CTSU_CTSUCR1_CTSUCSW_Msk          (0x2UL)    /*!< CTSUCSW (Bitfield-Mask: 0x01)                         */
15695  #define R_CTSU_CTSUCR1_CTSUPON_Pos          (0UL)      /*!< CTSUPON (Bit 0)                                       */
15696  #define R_CTSU_CTSUCR1_CTSUPON_Msk          (0x1UL)    /*!< CTSUPON (Bitfield-Mask: 0x01)                         */
15697 /* =======================================================  CTSUSDPRS  ======================================================= */
15698  #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos       (6UL)      /*!< CTSUSOFF (Bit 6)                                      */
15699  #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk       (0x40UL)   /*!< CTSUSOFF (Bitfield-Mask: 0x01)                        */
15700  #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos     (4UL)      /*!< CTSUPRMODE (Bit 4)                                    */
15701  #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk     (0x30UL)   /*!< CTSUPRMODE (Bitfield-Mask: 0x03)                      */
15702  #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos    (0UL)      /*!< CTSUPRRATIO (Bit 0)                                   */
15703  #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk    (0xfUL)    /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f)                     */
15704 /* ========================================================  CTSUSST  ======================================================== */
15705  #define R_CTSU_CTSUSST_CTSUSST_Pos          (0UL)      /*!< CTSUSST (Bit 0)                                       */
15706  #define R_CTSU_CTSUSST_CTSUSST_Msk          (0xffUL)   /*!< CTSUSST (Bitfield-Mask: 0xff)                         */
15707 /* =======================================================  CTSUMCH0  ======================================================== */
15708  #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos        (0UL)      /*!< CTSUMCH0 (Bit 0)                                      */
15709  #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk        (0x3fUL)   /*!< CTSUMCH0 (Bitfield-Mask: 0x3f)                        */
15710 /* =======================================================  CTSUMCH1  ======================================================== */
15711  #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos        (0UL)      /*!< CTSUMCH1 (Bit 0)                                      */
15712  #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk        (0x3fUL)   /*!< CTSUMCH1 (Bitfield-Mask: 0x3f)                        */
15713 /* =======================================================  CTSUCHAC  ======================================================== */
15714  #define R_CTSU_CTSUCHAC_TS_Pos              (0UL)      /*!< TS (Bit 0)                                            */
15715  #define R_CTSU_CTSUCHAC_TS_Msk              (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
15716 /* =======================================================  CTSUCHTRC  ======================================================= */
15717  #define R_CTSU_CTSUCHTRC_TS_Pos             (0UL)      /*!< TS (Bit 0)                                            */
15718  #define R_CTSU_CTSUCHTRC_TS_Msk             (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
15719 /* =======================================================  CTSUDCLKC  ======================================================= */
15720  #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos      (4UL)      /*!< CTSUSSCNT (Bit 4)                                     */
15721  #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk      (0x30UL)   /*!< CTSUSSCNT (Bitfield-Mask: 0x03)                       */
15722  #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos      (0UL)      /*!< CTSUSSMOD (Bit 0)                                     */
15723  #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk      (0x3UL)    /*!< CTSUSSMOD (Bitfield-Mask: 0x03)                       */
15724 /* ========================================================  CTSUST  ========================================================= */
15725  #define R_CTSU_CTSUST_CTSUPS_Pos            (7UL)      /*!< CTSUPS (Bit 7)                                        */
15726  #define R_CTSU_CTSUST_CTSUPS_Msk            (0x80UL)   /*!< CTSUPS (Bitfield-Mask: 0x01)                          */
15727  #define R_CTSU_CTSUST_CTSUROVF_Pos          (6UL)      /*!< CTSUROVF (Bit 6)                                      */
15728  #define R_CTSU_CTSUST_CTSUROVF_Msk          (0x40UL)   /*!< CTSUROVF (Bitfield-Mask: 0x01)                        */
15729  #define R_CTSU_CTSUST_CTSUSOVF_Pos          (5UL)      /*!< CTSUSOVF (Bit 5)                                      */
15730  #define R_CTSU_CTSUST_CTSUSOVF_Msk          (0x20UL)   /*!< CTSUSOVF (Bitfield-Mask: 0x01)                        */
15731  #define R_CTSU_CTSUST_CTSUDTSR_Pos          (4UL)      /*!< CTSUDTSR (Bit 4)                                      */
15732  #define R_CTSU_CTSUST_CTSUDTSR_Msk          (0x10UL)   /*!< CTSUDTSR (Bitfield-Mask: 0x01)                        */
15733  #define R_CTSU_CTSUST_CTSUSTC_Pos           (0UL)      /*!< CTSUSTC (Bit 0)                                       */
15734  #define R_CTSU_CTSUST_CTSUSTC_Msk           (0x7UL)    /*!< CTSUSTC (Bitfield-Mask: 0x07)                         */
15735 /* ========================================================  CTSUSSC  ======================================================== */
15736  #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos        (8UL)      /*!< CTSUSSDIV (Bit 8)                                     */
15737  #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk        (0xf00UL)  /*!< CTSUSSDIV (Bitfield-Mask: 0x0f)                       */
15738 /* ========================================================  CTSUSO0  ======================================================== */
15739  #define R_CTSU_CTSUSO0_CTSUSNUM_Pos         (10UL)     /*!< CTSUSNUM (Bit 10)                                     */
15740  #define R_CTSU_CTSUSO0_CTSUSNUM_Msk         (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f)                        */
15741  #define R_CTSU_CTSUSO0_CTSUSO_Pos           (0UL)      /*!< CTSUSO (Bit 0)                                        */
15742  #define R_CTSU_CTSUSO0_CTSUSO_Msk           (0x3ffUL)  /*!< CTSUSO (Bitfield-Mask: 0x3ff)                         */
15743 /* ========================================================  CTSUSO1  ======================================================== */
15744  #define R_CTSU_CTSUSO1_CTSUICOG_Pos         (13UL)     /*!< CTSUICOG (Bit 13)                                     */
15745  #define R_CTSU_CTSUSO1_CTSUICOG_Msk         (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03)                        */
15746  #define R_CTSU_CTSUSO1_CTSUSDPA_Pos         (8UL)      /*!< CTSUSDPA (Bit 8)                                      */
15747  #define R_CTSU_CTSUSO1_CTSUSDPA_Msk         (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f)                        */
15748  #define R_CTSU_CTSUSO1_CTSURICOA_Pos        (0UL)      /*!< CTSURICOA (Bit 0)                                     */
15749  #define R_CTSU_CTSUSO1_CTSURICOA_Msk        (0xffUL)   /*!< CTSURICOA (Bitfield-Mask: 0xff)                       */
15750 /* ========================================================  CTSUSC  ========================================================= */
15751  #define R_CTSU_CTSUSC_CTSUSC_Pos            (0UL)      /*!< CTSUSC (Bit 0)                                        */
15752  #define R_CTSU_CTSUSC_CTSUSC_Msk            (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff)                        */
15753 /* ========================================================  CTSURC  ========================================================= */
15754  #define R_CTSU_CTSURC_CTSURC_Pos            (0UL)      /*!< CTSURC (Bit 0)                                        */
15755  #define R_CTSU_CTSURC_CTSURC_Msk            (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff)                        */
15756 /* =======================================================  CTSUERRS  ======================================================== */
15757  #define R_CTSU_CTSUERRS_CTSUICOMP_Pos       (15UL)     /*!< CTSUICOMP (Bit 15)                                    */
15758  #define R_CTSU_CTSUERRS_CTSUICOMP_Msk       (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01)                       */
15759  #define R_CTSU_CTSUERRS_CTSUSPMD_Pos        (0UL)      /*!< CTSUSPMD (Bit 0)                                      */
15760  #define R_CTSU_CTSUERRS_CTSUSPMD_Msk        (0x3UL)    /*!< CTSUSPMD (Bitfield-Mask: 0x03)                        */
15761  #define R_CTSU_CTSUERRS_CTSUTSOD_Pos        (2UL)      /*!< CTSUTSOD (Bit 2)                                      */
15762  #define R_CTSU_CTSUERRS_CTSUTSOD_Msk        (0x4UL)    /*!< CTSUTSOD (Bitfield-Mask: 0x01)                        */
15763  #define R_CTSU_CTSUERRS_CTSUDRV_Pos         (3UL)      /*!< CTSUDRV (Bit 3)                                       */
15764  #define R_CTSU_CTSUERRS_CTSUDRV_Msk         (0x8UL)    /*!< CTSUDRV (Bitfield-Mask: 0x01)                         */
15765  #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos     (6UL)      /*!< CTSUCLKSEL1 (Bit 6)                                   */
15766  #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk     (0x40UL)   /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01)                     */
15767  #define R_CTSU_CTSUERRS_CTSUTSOC_Pos        (7UL)      /*!< CTSUTSOC (Bit 7)                                      */
15768  #define R_CTSU_CTSUERRS_CTSUTSOC_Msk        (0x80UL)   /*!< CTSUTSOC (Bitfield-Mask: 0x01)                        */
15769 /* =======================================================  CTSUTRMR  ======================================================== */
15770 
15771 /* =========================================================================================================================== */
15772 /* ================                                           R_DAC                                           ================ */
15773 /* =========================================================================================================================== */
15774 
15775 /* =========================================================  DACR  ========================================================== */
15776  #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
15777  #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
15778  #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
15779  #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
15780 /* =========================================================  DADR  ========================================================== */
15781  #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
15782  #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
15783 /* =========================================================  DADPR  ========================================================= */
15784  #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
15785  #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
15786 /* ========================================================  DAADSCR  ======================================================== */
15787  #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
15788  #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
15789 /* =======================================================  DAVREFCR  ======================================================== */
15790  #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
15791  #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
15792 /* =========================================================  DAPC  ========================================================== */
15793  #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
15794  #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
15795 /* ========================================================  DAAMPCR  ======================================================== */
15796  #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
15797  #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
15798 /* ========================================================  DAASWCR  ======================================================== */
15799  #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
15800  #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
15801  #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
15802  #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
15803 /* ========================================================  DAADUSR  ======================================================== */
15804  #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
15805  #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
15806  #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
15807  #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
15808 
15809 /* =========================================================================================================================== */
15810 /* ================                                          R_DAC8                                           ================ */
15811 /* =========================================================================================================================== */
15812 
15813 /* ==========================================================  DAM  ========================================================== */
15814  #define R_DAC8_DAM_DACE1_Pos           (5UL)    /*!< DACE1 (Bit 5)                                         */
15815  #define R_DAC8_DAM_DACE1_Msk           (0x20UL) /*!< DACE1 (Bitfield-Mask: 0x01)                           */
15816  #define R_DAC8_DAM_DACE0_Pos           (4UL)    /*!< DACE0 (Bit 4)                                         */
15817  #define R_DAC8_DAM_DACE0_Msk           (0x10UL) /*!< DACE0 (Bitfield-Mask: 0x01)                           */
15818  #define R_DAC8_DAM_DAMD1_Pos           (1UL)    /*!< DAMD1 (Bit 1)                                         */
15819  #define R_DAC8_DAM_DAMD1_Msk           (0x2UL)  /*!< DAMD1 (Bitfield-Mask: 0x01)                           */
15820  #define R_DAC8_DAM_DAMD0_Pos           (0UL)    /*!< DAMD0 (Bit 0)                                         */
15821  #define R_DAC8_DAM_DAMD0_Msk           (0x1UL)  /*!< DAMD0 (Bitfield-Mask: 0x01)                           */
15822 /* =========================================================  DACS  ========================================================== */
15823  #define R_DAC8_DACS_DACS_Pos           (0UL)    /*!< DACS (Bit 0)                                          */
15824  #define R_DAC8_DACS_DACS_Msk           (0xffUL) /*!< DACS (Bitfield-Mask: 0xff)                            */
15825 /* =======================================================  DACADSCR  ======================================================== */
15826  #define R_DAC8_DACADSCR_DACADST_Pos    (0UL)    /*!< DACADST (Bit 0)                                       */
15827  #define R_DAC8_DACADSCR_DACADST_Msk    (0x1UL)  /*!< DACADST (Bitfield-Mask: 0x01)                         */
15828 /* =========================================================  DACPC  ========================================================= */
15829  #define R_DAC8_DACPC_PUMPEN_Pos        (0UL)    /*!< PUMPEN (Bit 0)                                        */
15830  #define R_DAC8_DACPC_PUMPEN_Msk        (0x1UL)  /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
15831 
15832 /* =========================================================================================================================== */
15833 /* ================                                          R_DEBUG                                          ================ */
15834 /* =========================================================================================================================== */
15835 
15836 /* ========================================================  DBGSTR  ========================================================= */
15837  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
15838  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
15839  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
15840  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
15841 /* =======================================================  DBGSTOPCR  ======================================================= */
15842  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
15843  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
15844  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos      (14UL)         /*!< DBGSTOP_TIM (Bit 14)                                  */
15845  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk      (0x4000UL)     /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01)                     */
15846  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos      (15UL)         /*!< DBGSTOP_SIR (Bit 15)                                  */
15847  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk      (0x8000UL)     /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01)                     */
15848  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
15849  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
15850  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
15851  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
15852  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
15853  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
15854  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
15855  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
15856  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
15857  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
15858 /* =======================================================  FSBLSTAT  ======================================================== */
15859  #define R_DEBUG_FSBLSTAT_CS_Pos                (0UL)          /*!< CS (Bit 0)                                            */
15860  #define R_DEBUG_FSBLSTAT_CS_Msk                (0x1UL)        /*!< CS (Bitfield-Mask: 0x01)                              */
15861  #define R_DEBUG_FSBLSTAT_RS_Pos                (1UL)          /*!< RS (Bit 1)                                            */
15862  #define R_DEBUG_FSBLSTAT_RS_Msk                (0x2UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
15863  #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos           (8UL)          /*!< FSBLCLK (Bit 8)                                       */
15864  #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk           (0x700UL)      /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */
15865 
15866 /* =========================================================================================================================== */
15867 /* ================                                           R_DOC                                           ================ */
15868 /* =========================================================================================================================== */
15869 
15870 /* =========================================================  DOCR  ========================================================== */
15871  #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
15872  #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
15873  #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
15874  #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
15875  #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
15876  #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
15877  #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
15878  #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
15879 /* =========================================================  DODIR  ========================================================= */
15880  #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
15881  #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
15882 /* =========================================================  DODSR  ========================================================= */
15883  #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
15884  #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
15885 
15886 /* =========================================================================================================================== */
15887 /* ================                                           R_DTC                                           ================ */
15888 /* =========================================================================================================================== */
15889 
15890 /* =========================================================  DTCCR  ========================================================= */
15891  #define R_DTC_DTCCR_RRS_Pos         (4UL)          /*!< RRS (Bit 4)                                           */
15892  #define R_DTC_DTCCR_RRS_Msk         (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
15893 /* ========================================================  DTCVBR  ========================================================= */
15894  #define R_DTC_DTCVBR_DTCVBR_Pos     (0UL)          /*!< DTCVBR (Bit 0)                                        */
15895  #define R_DTC_DTCVBR_DTCVBR_Msk     (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
15896 /* =========================================================  DTCST  ========================================================= */
15897  #define R_DTC_DTCST_DTCST_Pos       (0UL)          /*!< DTCST (Bit 0)                                         */
15898  #define R_DTC_DTCST_DTCST_Msk       (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
15899 /* ========================================================  DTCSTS  ========================================================= */
15900  #define R_DTC_DTCSTS_ACT_Pos        (15UL)         /*!< ACT (Bit 15)                                          */
15901  #define R_DTC_DTCSTS_ACT_Msk        (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
15902  #define R_DTC_DTCSTS_VECN_Pos       (0UL)          /*!< VECN (Bit 0)                                          */
15903  #define R_DTC_DTCSTS_VECN_Msk       (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
15904 /* =======================================================  DTCCR_SEC  ======================================================= */
15905  #define R_DTC_DTCCR_SEC_RRSS_Pos    (4UL)          /*!< RRSS (Bit 4)                                          */
15906  #define R_DTC_DTCCR_SEC_RRSS_Msk    (0x10UL)       /*!< RRSS (Bitfield-Mask: 0x01)                            */
15907 /* ======================================================  DTCVBR_SEC  ======================================================= */
15908 /* =========================================================  DTEVR  ========================================================= */
15909  #define R_DTC_DTEVR_DTEV_Pos        (0UL)          /*!< DTEV (Bit 0)                                          */
15910  #define R_DTC_DTEVR_DTEV_Msk        (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
15911  #define R_DTC_DTEVR_DTEVSAM_Pos     (8UL)          /*!< DTEVSAM (Bit 8)                                       */
15912  #define R_DTC_DTEVR_DTEVSAM_Msk     (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
15913  #define R_DTC_DTEVR_DTESTA_Pos      (16UL)         /*!< DTESTA (Bit 16)                                       */
15914  #define R_DTC_DTEVR_DTESTA_Msk      (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
15915 
15916 /* =========================================================================================================================== */
15917 /* ================                                           R_ELC                                           ================ */
15918 /* =========================================================================================================================== */
15919 
15920 /* =========================================================  ELCR  ========================================================== */
15921  #define R_ELC_ELCR_ELCON_Pos         (7UL)      /*!< ELCON (Bit 7)                                         */
15922  #define R_ELC_ELCR_ELCON_Msk         (0x80UL)   /*!< ELCON (Bitfield-Mask: 0x01)                           */
15923 /* ========================================================  ELCSARA  ======================================================== */
15924  #define R_ELC_ELCSARA_ELCR_Pos       (0UL)      /*!< ELCR (Bit 0)                                          */
15925  #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)    /*!< ELCR (Bitfield-Mask: 0x01)                            */
15926  #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)      /*!< ELSEGR0 (Bit 1)                                       */
15927  #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)    /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
15928  #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)      /*!< ELSEGR1 (Bit 2)                                       */
15929  #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)    /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
15930 /* ========================================================  ELCSARB  ======================================================== */
15931  #define R_ELC_ELCSARB_ELSR0_Pos      (0UL)      /*!< ELSR0 (Bit 0)                                         */
15932  #define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)    /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
15933  #define R_ELC_ELCSARB_ELSR1_Pos      (1UL)      /*!< ELSR1 (Bit 1)                                         */
15934  #define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)    /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
15935  #define R_ELC_ELCSARB_ELSR2_Pos      (2UL)      /*!< ELSR2 (Bit 2)                                         */
15936  #define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)    /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
15937  #define R_ELC_ELCSARB_ELSR3_Pos      (3UL)      /*!< ELSR3 (Bit 3)                                         */
15938  #define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)    /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
15939  #define R_ELC_ELCSARB_ELSR4_Pos      (4UL)      /*!< ELSR4 (Bit 4)                                         */
15940  #define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)   /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
15941  #define R_ELC_ELCSARB_ELSR5_Pos      (5UL)      /*!< ELSR5 (Bit 5)                                         */
15942  #define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)   /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
15943  #define R_ELC_ELCSARB_ELSR6_Pos      (6UL)      /*!< ELSR6 (Bit 6)                                         */
15944  #define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)   /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
15945  #define R_ELC_ELCSARB_ELSR7_Pos      (7UL)      /*!< ELSR7 (Bit 7)                                         */
15946  #define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)   /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
15947  #define R_ELC_ELCSARB_ELSR8_Pos      (8UL)      /*!< ELSR8 (Bit 8)                                         */
15948  #define R_ELC_ELCSARB_ELSR8_Msk      (0x100UL)  /*!< ELSR8 (Bitfield-Mask: 0x01)                           */
15949  #define R_ELC_ELCSARB_ELSR9_Pos      (9UL)      /*!< ELSR9 (Bit 9)                                         */
15950  #define R_ELC_ELCSARB_ELSR9_Msk      (0x200UL)  /*!< ELSR9 (Bitfield-Mask: 0x01)                           */
15951  #define R_ELC_ELCSARB_ELSR10_Pos     (10UL)     /*!< ELSR10 (Bit 10)                                       */
15952  #define R_ELC_ELCSARB_ELSR10_Msk     (0x400UL)  /*!< ELSR10 (Bitfield-Mask: 0x01)                          */
15953  #define R_ELC_ELCSARB_ELSR11_Pos     (11UL)     /*!< ELSR11 (Bit 11)                                       */
15954  #define R_ELC_ELCSARB_ELSR11_Msk     (0x800UL)  /*!< ELSR11 (Bitfield-Mask: 0x01)                          */
15955  #define R_ELC_ELCSARB_ELSR12_Pos     (12UL)     /*!< ELSR12 (Bit 12)                                       */
15956  #define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
15957  #define R_ELC_ELCSARB_ELSR13_Pos     (13UL)     /*!< ELSR13 (Bit 13)                                       */
15958  #define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
15959  #define R_ELC_ELCSARB_ELSR14_Pos     (14UL)     /*!< ELSR14 (Bit 14)                                       */
15960  #define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
15961  #define R_ELC_ELCSARB_ELSR15_Pos     (15UL)     /*!< ELSR15 (Bit 15)                                       */
15962  #define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
15963 /* ========================================================  ELCSARC  ======================================================== */
15964  #define R_ELC_ELCSARC_ELSR16_Pos     (0UL)      /*!< ELSR16 (Bit 0)                                        */
15965  #define R_ELC_ELCSARC_ELSR16_Msk     (0x1UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
15966  #define R_ELC_ELCSARC_ELSR17_Pos     (1UL)      /*!< ELSR17 (Bit 1)                                        */
15967  #define R_ELC_ELCSARC_ELSR17_Msk     (0x2UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
15968  #define R_ELC_ELCSARC_ELSR18_Pos     (2UL)      /*!< ELSR18 (Bit 2)                                        */
15969  #define R_ELC_ELCSARC_ELSR18_Msk     (0x4UL)    /*!< ELSR18 (Bitfield-Mask: 0x01)                          */
15970 
15971 /* =========================================================================================================================== */
15972 /* ================                                         R_FACI_LP                                         ================ */
15973 /* =========================================================================================================================== */
15974 
15975 /* ========================================================  DFLCTL  ========================================================= */
15976 /* =========================================================  FPMCR  ========================================================= */
15977  #define R_FACI_LP_FPMCR_FMS2_Pos           (7UL)      /*!< FMS2 (Bit 7)                                          */
15978  #define R_FACI_LP_FPMCR_FMS2_Msk           (0x80UL)   /*!< FMS2 (Bitfield-Mask: 0x01)                            */
15979  #define R_FACI_LP_FPMCR_VLPE_Pos           (6UL)      /*!< VLPE (Bit 6)                                          */
15980  #define R_FACI_LP_FPMCR_VLPE_Msk           (0x40UL)   /*!< VLPE (Bitfield-Mask: 0x01)                            */
15981  #define R_FACI_LP_FPMCR_FMS1_Pos           (4UL)      /*!< FMS1 (Bit 4)                                          */
15982  #define R_FACI_LP_FPMCR_FMS1_Msk           (0x10UL)   /*!< FMS1 (Bitfield-Mask: 0x01)                            */
15983  #define R_FACI_LP_FPMCR_RPDIS_Pos          (3UL)      /*!< RPDIS (Bit 3)                                         */
15984  #define R_FACI_LP_FPMCR_RPDIS_Msk          (0x8UL)    /*!< RPDIS (Bitfield-Mask: 0x01)                           */
15985  #define R_FACI_LP_FPMCR_FMS0_Pos           (1UL)      /*!< FMS0 (Bit 1)                                          */
15986  #define R_FACI_LP_FPMCR_FMS0_Msk           (0x2UL)    /*!< FMS0 (Bitfield-Mask: 0x01)                            */
15987 /* =========================================================  FASR  ========================================================== */
15988  #define R_FACI_LP_FASR_EXS_Pos             (0UL)      /*!< EXS (Bit 0)                                           */
15989  #define R_FACI_LP_FASR_EXS_Msk             (0x1UL)    /*!< EXS (Bitfield-Mask: 0x01)                             */
15990 /* =========================================================  FSARL  ========================================================= */
15991  #define R_FACI_LP_FSARL_FSAR15_0_Pos       (0UL)      /*!< FSAR15_0 (Bit 0)                                      */
15992  #define R_FACI_LP_FSARL_FSAR15_0_Msk       (0xffffUL) /*!< FSAR15_0 (Bitfield-Mask: 0xffff)                      */
15993 /* =========================================================  FSARH  ========================================================= */
15994  #define R_FACI_LP_FSARH_FSAR31_25_Pos      (9UL)      /*!< FSAR31_25 (Bit 9)                                     */
15995  #define R_FACI_LP_FSARH_FSAR31_25_Msk      (0xfe00UL) /*!< FSAR31_25 (Bitfield-Mask: 0x7f)                       */
15996  #define R_FACI_LP_FSARH_FSAR20_16_Pos      (0UL)      /*!< FSAR20_16 (Bit 0)                                     */
15997  #define R_FACI_LP_FSARH_FSAR20_16_Msk      (0x1fUL)   /*!< FSAR20_16 (Bitfield-Mask: 0x1f)                       */
15998 /* ==========================================================  FCR  ========================================================== */
15999  #define R_FACI_LP_FCR_OPST_Pos             (7UL)      /*!< OPST (Bit 7)                                          */
16000  #define R_FACI_LP_FCR_OPST_Msk             (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
16001  #define R_FACI_LP_FCR_STOP_Pos             (6UL)      /*!< STOP (Bit 6)                                          */
16002  #define R_FACI_LP_FCR_STOP_Msk             (0x40UL)   /*!< STOP (Bitfield-Mask: 0x01)                            */
16003  #define R_FACI_LP_FCR_DRC_Pos              (4UL)      /*!< DRC (Bit 4)                                           */
16004  #define R_FACI_LP_FCR_DRC_Msk              (0x10UL)   /*!< DRC (Bitfield-Mask: 0x01)                             */
16005  #define R_FACI_LP_FCR_CMD_Pos              (0UL)      /*!< CMD (Bit 0)                                           */
16006  #define R_FACI_LP_FCR_CMD_Msk              (0xfUL)    /*!< CMD (Bitfield-Mask: 0x0f)                             */
16007 /* =========================================================  FEARL  ========================================================= */
16008  #define R_FACI_LP_FEARL_FEAR15_0_Pos       (0UL)      /*!< FEAR15_0 (Bit 0)                                      */
16009  #define R_FACI_LP_FEARL_FEAR15_0_Msk       (0xffffUL) /*!< FEAR15_0 (Bitfield-Mask: 0xffff)                      */
16010 /* =========================================================  FEARH  ========================================================= */
16011  #define R_FACI_LP_FEARH_FEAR31_25_Pos      (9UL)      /*!< FEAR31_25 (Bit 9)                                     */
16012  #define R_FACI_LP_FEARH_FEAR31_25_Msk      (0xfe00UL) /*!< FEAR31_25 (Bitfield-Mask: 0x7f)                       */
16013  #define R_FACI_LP_FEARH_FEAR20_16_Pos      (0UL)      /*!< FEAR20_16 (Bit 0)                                     */
16014  #define R_FACI_LP_FEARH_FEAR20_16_Msk      (0x1fUL)   /*!< FEAR20_16 (Bitfield-Mask: 0x1f)                       */
16015 /* ========================================================  FRESETR  ======================================================== */
16016  #define R_FACI_LP_FRESETR_FRESET_Pos       (0UL)      /*!< FRESET (Bit 0)                                        */
16017  #define R_FACI_LP_FRESETR_FRESET_Msk       (0x1UL)    /*!< FRESET (Bitfield-Mask: 0x01)                          */
16018 /* =======================================================  FSTATR00  ======================================================== */
16019  #define R_FACI_LP_FSTATR00_EILGLERR_Pos    (5UL)      /*!< EILGLERR (Bit 5)                                      */
16020  #define R_FACI_LP_FSTATR00_EILGLERR_Msk    (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
16021  #define R_FACI_LP_FSTATR00_ILGLERR_Pos     (4UL)      /*!< ILGLERR (Bit 4)                                       */
16022  #define R_FACI_LP_FSTATR00_ILGLERR_Msk     (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
16023  #define R_FACI_LP_FSTATR00_BCERR0_Pos      (3UL)      /*!< BCERR0 (Bit 3)                                        */
16024  #define R_FACI_LP_FSTATR00_BCERR0_Msk      (0x8UL)    /*!< BCERR0 (Bitfield-Mask: 0x01)                          */
16025  #define R_FACI_LP_FSTATR00_PRGERR01_Pos    (2UL)      /*!< PRGERR01 (Bit 2)                                      */
16026  #define R_FACI_LP_FSTATR00_PRGERR01_Msk    (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
16027  #define R_FACI_LP_FSTATR00_PRGERR0_Pos     (1UL)      /*!< PRGERR0 (Bit 1)                                       */
16028  #define R_FACI_LP_FSTATR00_PRGERR0_Msk     (0x2UL)    /*!< PRGERR0 (Bitfield-Mask: 0x01)                         */
16029  #define R_FACI_LP_FSTATR00_ERERR0_Pos      (0UL)      /*!< ERERR0 (Bit 0)                                        */
16030  #define R_FACI_LP_FSTATR00_ERERR0_Msk      (0x1UL)    /*!< ERERR0 (Bitfield-Mask: 0x01)                          */
16031 /* ========================================================  FSTATR1  ======================================================== */
16032  #define R_FACI_LP_FSTATR1_EXRDY_Pos        (7UL)      /*!< EXRDY (Bit 7)                                         */
16033  #define R_FACI_LP_FSTATR1_EXRDY_Msk        (0x80UL)   /*!< EXRDY (Bitfield-Mask: 0x01)                           */
16034  #define R_FACI_LP_FSTATR1_FRDY_Pos         (6UL)      /*!< FRDY (Bit 6)                                          */
16035  #define R_FACI_LP_FSTATR1_FRDY_Msk         (0x40UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
16036  #define R_FACI_LP_FSTATR1_DRRDY_Pos        (1UL)      /*!< DRRDY (Bit 1)                                         */
16037  #define R_FACI_LP_FSTATR1_DRRDY_Msk        (0x2UL)    /*!< DRRDY (Bitfield-Mask: 0x01)                           */
16038 /* =========================================================  FWBL0  ========================================================= */
16039  #define R_FACI_LP_FWBL0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
16040  #define R_FACI_LP_FWBL0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
16041 /* =========================================================  FWBH0  ========================================================= */
16042  #define R_FACI_LP_FWBH0_WDATA_Pos          (0UL)      /*!< WDATA (Bit 0)                                         */
16043  #define R_FACI_LP_FWBH0_WDATA_Msk          (0xffffUL) /*!< WDATA (Bitfield-Mask: 0xffff)                         */
16044 /* =======================================================  FSTATR01  ======================================================== */
16045  #define R_FACI_LP_FSTATR01_BCERR1_Pos      (3UL)      /*!< BCERR1 (Bit 3)                                        */
16046  #define R_FACI_LP_FSTATR01_BCERR1_Msk      (0x8UL)    /*!< BCERR1 (Bitfield-Mask: 0x01)                          */
16047  #define R_FACI_LP_FSTATR01_PRGERR1_Pos     (1UL)      /*!< PRGERR1 (Bit 1)                                       */
16048  #define R_FACI_LP_FSTATR01_PRGERR1_Msk     (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
16049  #define R_FACI_LP_FSTATR01_ERERR1_Pos      (0UL)      /*!< ERERR1 (Bit 0)                                        */
16050  #define R_FACI_LP_FSTATR01_ERERR1_Msk      (0x1UL)    /*!< ERERR1 (Bitfield-Mask: 0x01)                          */
16051 /* =========================================================  FWBL1  ========================================================= */
16052  #define R_FACI_LP_FWBL1_WDATA47_32_Pos     (0UL)      /*!< WDATA47_32 (Bit 0)                                    */
16053  #define R_FACI_LP_FWBL1_WDATA47_32_Msk     (0xffffUL) /*!< WDATA47_32 (Bitfield-Mask: 0xffff)                    */
16054 /* =========================================================  FWBH1  ========================================================= */
16055  #define R_FACI_LP_FWBH1_WDATA63_48_Pos     (0UL)      /*!< WDATA63_48 (Bit 0)                                    */
16056  #define R_FACI_LP_FWBH1_WDATA63_48_Msk     (0xffffUL) /*!< WDATA63_48 (Bitfield-Mask: 0xffff)                    */
16057 /* =========================================================  FRBL1  ========================================================= */
16058  #define R_FACI_LP_FRBL1_RDATA47_32_Pos     (0UL)      /*!< RDATA47_32 (Bit 0)                                    */
16059  #define R_FACI_LP_FRBL1_RDATA47_32_Msk     (0xffffUL) /*!< RDATA47_32 (Bitfield-Mask: 0xffff)                    */
16060 /* =========================================================  FRBH1  ========================================================= */
16061  #define R_FACI_LP_FRBH1_RDATA63_48_Pos     (0UL)      /*!< RDATA63_48 (Bit 0)                                    */
16062  #define R_FACI_LP_FRBH1_RDATA63_48_Msk     (0xffffUL) /*!< RDATA63_48 (Bitfield-Mask: 0xffff)                    */
16063 /* ==========================================================  FPR  ========================================================== */
16064  #define R_FACI_LP_FPR_FPR_Pos              (0UL)      /*!< FPR (Bit 0)                                           */
16065  #define R_FACI_LP_FPR_FPR_Msk              (0xffUL)   /*!< FPR (Bitfield-Mask: 0xff)                             */
16066 /* =========================================================  FPSR  ========================================================== */
16067  #define R_FACI_LP_FPSR_PERR_Pos            (0UL)      /*!< PERR (Bit 0)                                          */
16068  #define R_FACI_LP_FPSR_PERR_Msk            (0x1UL)    /*!< PERR (Bitfield-Mask: 0x01)                            */
16069 /* =========================================================  FRBL0  ========================================================= */
16070  #define R_FACI_LP_FRBL0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
16071  #define R_FACI_LP_FRBL0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
16072 /* =========================================================  FRBH0  ========================================================= */
16073  #define R_FACI_LP_FRBH0_RDATA_Pos          (0UL)      /*!< RDATA (Bit 0)                                         */
16074  #define R_FACI_LP_FRBH0_RDATA_Msk          (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff)                         */
16075 /* =========================================================  FSCMR  ========================================================= */
16076  #define R_FACI_LP_FSCMR_FSPR_Pos           (14UL)     /*!< FSPR (Bit 14)                                         */
16077  #define R_FACI_LP_FSCMR_FSPR_Msk           (0x4000UL) /*!< FSPR (Bitfield-Mask: 0x01)                            */
16078  #define R_FACI_LP_FSCMR_SASMF_Pos          (8UL)      /*!< SASMF (Bit 8)                                         */
16079  #define R_FACI_LP_FSCMR_SASMF_Msk          (0x100UL)  /*!< SASMF (Bitfield-Mask: 0x01)                           */
16080 /* ========================================================  FAWSMR  ========================================================= */
16081  #define R_FACI_LP_FAWSMR_FAWS_Pos          (0UL)      /*!< FAWS (Bit 0)                                          */
16082  #define R_FACI_LP_FAWSMR_FAWS_Msk          (0xfffUL)  /*!< FAWS (Bitfield-Mask: 0xfff)                           */
16083 /* ========================================================  FAWEMR  ========================================================= */
16084  #define R_FACI_LP_FAWEMR_FAWE_Pos          (0UL)      /*!< FAWE (Bit 0)                                          */
16085  #define R_FACI_LP_FAWEMR_FAWE_Msk          (0xfffUL)  /*!< FAWE (Bitfield-Mask: 0xfff)                           */
16086 /* =========================================================  FISR  ========================================================== */
16087  #define R_FACI_LP_FISR_SAS_Pos             (6UL)      /*!< SAS (Bit 6)                                           */
16088  #define R_FACI_LP_FISR_SAS_Msk             (0xc0UL)   /*!< SAS (Bitfield-Mask: 0x03)                             */
16089  #define R_FACI_LP_FISR_PCKA_Pos            (0UL)      /*!< PCKA (Bit 0)                                          */
16090  #define R_FACI_LP_FISR_PCKA_Msk            (0x3fUL)   /*!< PCKA (Bitfield-Mask: 0x3f)                            */
16091 /* =========================================================  FEXCR  ========================================================= */
16092  #define R_FACI_LP_FEXCR_OPST_Pos           (7UL)      /*!< OPST (Bit 7)                                          */
16093  #define R_FACI_LP_FEXCR_OPST_Msk           (0x80UL)   /*!< OPST (Bitfield-Mask: 0x01)                            */
16094  #define R_FACI_LP_FEXCR_CMD_Pos            (0UL)      /*!< CMD (Bit 0)                                           */
16095  #define R_FACI_LP_FEXCR_CMD_Msk            (0x7UL)    /*!< CMD (Bitfield-Mask: 0x07)                             */
16096 /* =========================================================  FEAML  ========================================================= */
16097  #define R_FACI_LP_FEAML_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
16098  #define R_FACI_LP_FEAML_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
16099 /* =========================================================  FEAMH  ========================================================= */
16100  #define R_FACI_LP_FEAMH_FEAM_Pos           (0UL)      /*!< FEAM (Bit 0)                                          */
16101  #define R_FACI_LP_FEAMH_FEAM_Msk           (0xffffUL) /*!< FEAM (Bitfield-Mask: 0xffff)                          */
16102 /* ========================================================  FSTATR2  ======================================================== */
16103  #define R_FACI_LP_FSTATR2_EILGLERR_Pos     (5UL)      /*!< EILGLERR (Bit 5)                                      */
16104  #define R_FACI_LP_FSTATR2_EILGLERR_Msk     (0x20UL)   /*!< EILGLERR (Bitfield-Mask: 0x01)                        */
16105  #define R_FACI_LP_FSTATR2_ILGLERR_Pos      (4UL)      /*!< ILGLERR (Bit 4)                                       */
16106  #define R_FACI_LP_FSTATR2_ILGLERR_Msk      (0x10UL)   /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
16107  #define R_FACI_LP_FSTATR2_BCERR_Pos        (3UL)      /*!< BCERR (Bit 3)                                         */
16108  #define R_FACI_LP_FSTATR2_BCERR_Msk        (0x8UL)    /*!< BCERR (Bitfield-Mask: 0x01)                           */
16109  #define R_FACI_LP_FSTATR2_PRGERR01_Pos     (2UL)      /*!< PRGERR01 (Bit 2)                                      */
16110  #define R_FACI_LP_FSTATR2_PRGERR01_Msk     (0x4UL)    /*!< PRGERR01 (Bitfield-Mask: 0x01)                        */
16111  #define R_FACI_LP_FSTATR2_PRGERR1_Pos      (1UL)      /*!< PRGERR1 (Bit 1)                                       */
16112  #define R_FACI_LP_FSTATR2_PRGERR1_Msk      (0x2UL)    /*!< PRGERR1 (Bitfield-Mask: 0x01)                         */
16113  #define R_FACI_LP_FSTATR2_ERERR_Pos        (0UL)      /*!< ERERR (Bit 0)                                         */
16114  #define R_FACI_LP_FSTATR2_ERERR_Msk        (0x1UL)    /*!< ERERR (Bitfield-Mask: 0x01)                           */
16115 /* ========================================================  FCTLFR  ========================================================= */
16116  #define R_FACI_LP_FCTLFR_BANKSWP_Pos       (0UL)      /*!< BANKSWP (Bit 0)                                       */
16117  #define R_FACI_LP_FCTLFR_BANKSWP_Msk       (0x7UL)    /*!< BANKSWP (Bitfield-Mask: 0x07)                         */
16118 /* ======================================================  FENTRYR_MF4  ====================================================== */
16119 /* ========================================================  FENTRYR  ======================================================== */
16120 /* ========================================================  FLWAITR  ======================================================== */
16121 /* =======================================================  FLDWAITR  ======================================================== */
16122  #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos    (0UL)      /*!< FLDWAIT1 (Bit 0)                                      */
16123  #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk    (0x1UL)    /*!< FLDWAIT1 (Bitfield-Mask: 0x01)                        */
16124 /* =========================================================  PFBER  ========================================================= */
16125 /* ========================================================  FBKPGCR  ======================================================== */
16126  #define R_FACI_LP_FBKPGCR_BKPGEN_Pos       (0UL)      /*!< BKPGEN (Bit 0)                                        */
16127  #define R_FACI_LP_FBKPGCR_BKPGEN_Msk       (0x1UL)    /*!< BKPGEN (Bitfield-Mask: 0x01)                          */
16128  #define R_FACI_LP_FBKPGCR_FEKEY_Pos        (8UL)      /*!< FEKEY (Bit 8)                                         */
16129  #define R_FACI_LP_FBKPGCR_FEKEY_Msk        (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff)                           */
16130 /* ========================================================  FBKSWCR  ======================================================== */
16131  #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos     (0UL)      /*!< BKSWUPEN (Bit 0)                                      */
16132  #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk     (0x1UL)    /*!< BKSWUPEN (Bitfield-Mask: 0x01)                        */
16133  #define R_FACI_LP_FBKSWCR_FEKEY_Pos        (8UL)      /*!< FEKEY (Bit 8)                                         */
16134  #define R_FACI_LP_FBKSWCR_FEKEY_Msk        (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff)                           */
16135 /* ========================================================  HIOTRM  ========================================================= */
16136  #define R_FACI_LP_HIOTRM_HIOTRM_Pos        (0UL)      /*!< HIOTRM (Bit 0)                                        */
16137  #define R_FACI_LP_HIOTRM_HIOTRM_Msk        (0x3fUL)   /*!< HIOTRM (Bitfield-Mask: 0x3f)                          */
16138 /* ========================================================  FLMODE  ========================================================= */
16139  #define R_FACI_LP_FLMODE_MODE_Pos          (6UL)      /*!< MODE (Bit 6)                                          */
16140  #define R_FACI_LP_FLMODE_MODE_Msk          (0xc0UL)   /*!< MODE (Bitfield-Mask: 0x03)                            */
16141 /* ========================================================  FLMWRP  ========================================================= */
16142  #define R_FACI_LP_FLMWRP_FLMWEN_Pos        (0UL)      /*!< FLMWEN (Bit 0)                                        */
16143  #define R_FACI_LP_FLMWRP_FLMWEN_Msk        (0x1UL)    /*!< FLMWEN (Bitfield-Mask: 0x01)                          */
16144 
16145 /* =========================================================================================================================== */
16146 /* ================                                         R_FCACHE                                          ================ */
16147 /* =========================================================================================================================== */
16148 
16149 /* ========================================================  FCACHEE  ======================================================== */
16150  #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)     /*!< FCACHEEN (Bit 0)                                      */
16151  #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)   /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
16152 /* =======================================================  FCACHEIV  ======================================================== */
16153  #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)     /*!< FCACHEIV (Bit 0)                                      */
16154  #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)   /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
16155 /* =========================================================  FLWT  ========================================================== */
16156  #define R_FCACHE_FLWT_FLWT_Pos            (0UL)     /*!< FLWT (Bit 0)                                          */
16157  #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)   /*!< FLWT (Bitfield-Mask: 0x07)                            */
16158 /* =========================================================  FSAR  ========================================================== */
16159  #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)     /*!< FLWTSA (Bit 0)                                        */
16160  #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)   /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
16161  #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)     /*!< FCKMHZSA (Bit 8)                                      */
16162  #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
16163 
16164 /* =========================================================================================================================== */
16165 /* ================                                          R_GPT0                                           ================ */
16166 /* =========================================================================================================================== */
16167 
16168 /* =========================================================  GTWP  ========================================================== */
16169  #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
16170  #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
16171  #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
16172  #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
16173  #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
16174  #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
16175  #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
16176  #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
16177  #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
16178  #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
16179  #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
16180  #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
16181 /* =========================================================  GTSTR  ========================================================= */
16182  #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
16183  #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
16184 /* =========================================================  GTSTP  ========================================================= */
16185  #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
16186  #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
16187 /* =========================================================  GTCLR  ========================================================= */
16188  #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
16189  #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
16190 /* =========================================================  GTSSR  ========================================================= */
16191  #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
16192  #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
16193  #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
16194  #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
16195  #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
16196  #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
16197  #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
16198  #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
16199  #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
16200  #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
16201  #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
16202  #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
16203  #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
16204  #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
16205  #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
16206  #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
16207  #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
16208  #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
16209  #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
16210  #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
16211  #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
16212  #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
16213  #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
16214  #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
16215 /* =========================================================  GTPSR  ========================================================= */
16216  #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
16217  #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
16218  #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
16219  #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
16220  #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
16221  #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
16222  #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
16223  #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
16224  #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
16225  #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
16226  #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
16227  #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
16228  #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
16229  #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
16230  #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
16231  #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
16232  #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
16233  #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
16234  #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
16235  #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
16236  #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
16237  #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
16238  #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
16239  #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
16240 /* =========================================================  GTCSR  ========================================================= */
16241  #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
16242  #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
16243  #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
16244  #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
16245  #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
16246  #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
16247  #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
16248  #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
16249  #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
16250  #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
16251  #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
16252  #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
16253  #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
16254  #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
16255  #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
16256  #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
16257  #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
16258  #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
16259  #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
16260  #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
16261  #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
16262  #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
16263  #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
16264  #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
16265  #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
16266  #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
16267  #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
16268  #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
16269 /* ========================================================  GTUPSR  ========================================================= */
16270  #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
16271  #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
16272  #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
16273  #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
16274  #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
16275  #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
16276  #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
16277  #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
16278  #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
16279  #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
16280  #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
16281  #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
16282  #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
16283  #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
16284  #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
16285  #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
16286  #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
16287  #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
16288  #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
16289  #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
16290  #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
16291  #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
16292  #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
16293  #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
16294 /* ========================================================  GTDNSR  ========================================================= */
16295  #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
16296  #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
16297  #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
16298  #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
16299  #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
16300  #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
16301  #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
16302  #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
16303  #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
16304  #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
16305  #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
16306  #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
16307  #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
16308  #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
16309  #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
16310  #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
16311  #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
16312  #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
16313  #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
16314  #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
16315  #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
16316  #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
16317  #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
16318  #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
16319 /* ========================================================  GTICASR  ======================================================== */
16320  #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
16321  #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
16322  #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
16323  #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
16324  #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
16325  #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
16326  #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
16327  #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
16328  #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
16329  #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
16330  #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
16331  #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
16332  #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
16333  #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
16334  #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
16335  #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
16336  #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
16337  #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
16338  #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
16339  #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
16340  #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
16341  #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
16342 /* ========================================================  GTICBSR  ======================================================== */
16343  #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
16344  #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
16345  #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
16346  #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
16347  #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
16348  #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
16349  #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
16350  #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
16351  #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
16352  #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
16353  #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
16354  #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
16355  #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
16356  #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
16357  #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
16358  #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
16359  #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
16360  #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
16361  #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
16362  #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
16363  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
16364  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
16365 /* =========================================================  GTCR  ========================================================== */
16366  #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
16367  #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
16368  #define R_GPT0_GTCR_TPCS_Pos              (24UL)         /*!< TPCS (Bit 24)                                         */
16369  #define R_GPT0_GTCR_TPCS_Msk              (0x7000000UL)  /*!< TPCS (Bitfield-Mask: 0x07)                            */
16370  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
16371  #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
16372  #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
16373  #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
16374  #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
16375  #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
16376  #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
16377  #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
16378  #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
16379  #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
16380  #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
16381  #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
16382  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
16383  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
16384 /* =======================================================  GTUDDTYC  ======================================================== */
16385  #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
16386  #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
16387  #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
16388  #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
16389  #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
16390  #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
16391  #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
16392  #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
16393  #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
16394  #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
16395  #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
16396  #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
16397  #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
16398  #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
16399  #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
16400  #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
16401 /* =========================================================  GTIOR  ========================================================= */
16402  #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
16403  #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
16404  #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
16405  #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
16406  #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
16407  #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
16408  #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
16409  #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
16410  #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
16411  #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
16412  #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
16413  #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
16414  #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
16415  #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
16416  #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
16417  #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
16418  #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
16419  #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
16420  #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
16421  #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
16422  #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
16423  #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
16424  #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
16425  #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
16426  #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
16427  #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
16428  #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
16429  #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
16430  #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
16431  #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
16432  #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
16433  #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
16434  #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
16435  #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
16436  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
16437  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
16438 /* ========================================================  GTINTAD  ======================================================== */
16439  #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
16440  #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
16441  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
16442  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
16443  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
16444  #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
16445  #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
16446  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
16447  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
16448  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
16449  #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
16450  #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
16451  #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
16452  #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
16453  #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
16454  #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
16455  #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
16456  #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
16457  #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
16458  #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
16459 /* =========================================================  GTST  ========================================================== */
16460  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
16461  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
16462  #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
16463  #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
16464  #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
16465  #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
16466  #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
16467  #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
16468  #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
16469  #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
16470  #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
16471  #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
16472  #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
16473  #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
16474  #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
16475  #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
16476  #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
16477  #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
16478  #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
16479  #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
16480  #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
16481  #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
16482  #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
16483  #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
16484  #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
16485  #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
16486  #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
16487  #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
16488  #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
16489  #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
16490  #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
16491  #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
16492  #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
16493  #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
16494  #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
16495  #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
16496  #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
16497  #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
16498 /* =========================================================  GTBER  ========================================================= */
16499  #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
16500  #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
16501  #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
16502  #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
16503  #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
16504  #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
16505  #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
16506  #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
16507  #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
16508  #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
16509  #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
16510  #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
16511  #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
16512  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
16513  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
16514  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
16515  #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
16516  #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
16517  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
16518  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
16519  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
16520  #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
16521  #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
16522  #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
16523  #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
16524  #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
16525 /* =========================================================  GTITC  ========================================================= */
16526  #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
16527  #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
16528  #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
16529  #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
16530  #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
16531  #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
16532  #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
16533  #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
16534  #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
16535  #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
16536  #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
16537  #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
16538  #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
16539  #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
16540  #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
16541  #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
16542  #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
16543  #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
16544  #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
16545  #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
16546 /* =========================================================  GTCNT  ========================================================= */
16547  #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
16548  #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
16549 /* =========================================================  GTCCR  ========================================================= */
16550  #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
16551  #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
16552 /* =========================================================  GTPR  ========================================================== */
16553  #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
16554  #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
16555 /* =========================================================  GTPBR  ========================================================= */
16556  #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
16557  #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
16558 /* ========================================================  GTPDBR  ========================================================= */
16559  #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
16560  #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
16561 /* ========================================================  GTADTRA  ======================================================== */
16562  #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
16563  #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
16564 /* ========================================================  GTADTRB  ======================================================== */
16565  #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
16566  #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
16567 /* =======================================================  GTADTBRA  ======================================================== */
16568  #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
16569  #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
16570 /* =======================================================  GTADTBRB  ======================================================== */
16571  #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
16572  #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
16573 /* =======================================================  GTADTDBRA  ======================================================= */
16574  #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
16575  #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
16576 /* =======================================================  GTADTDBRB  ======================================================= */
16577  #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
16578  #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
16579 /* ========================================================  GTDTCR  ========================================================= */
16580  #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
16581  #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
16582  #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
16583  #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
16584  #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
16585  #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
16586  #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
16587  #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
16588 /* =========================================================  GTDVU  ========================================================= */
16589  #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
16590  #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
16591 /* =========================================================  GTDVD  ========================================================= */
16592  #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
16593  #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
16594 /* =========================================================  GTDBU  ========================================================= */
16595  #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
16596  #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
16597 /* =========================================================  GTDBD  ========================================================= */
16598  #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
16599  #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
16600 /* =========================================================  GTSOS  ========================================================= */
16601  #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
16602  #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
16603 /* ========================================================  GTSOTR  ========================================================= */
16604  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
16605  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
16606 /* ========================================================  GTADSMR  ======================================================== */
16607  #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
16608  #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
16609  #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
16610  #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
16611  #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
16612  #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
16613  #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
16614  #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
16615 /* ========================================================  GTEITC  ========================================================= */
16616  #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
16617  #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
16618  #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
16619  #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
16620  #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
16621  #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
16622  #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
16623  #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
16624  #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
16625  #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
16626  #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
16627  #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
16628  #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
16629  #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
16630 /* =======================================================  GTEITLI1  ======================================================== */
16631  #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
16632  #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
16633  #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
16634  #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
16635  #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
16636  #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
16637  #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
16638  #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
16639  #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
16640  #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
16641  #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
16642  #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
16643  #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
16644  #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
16645  #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
16646  #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
16647 /* =======================================================  GTEITLI2  ======================================================== */
16648  #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
16649  #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
16650  #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
16651  #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
16652 /* ========================================================  GTEITLB  ======================================================== */
16653  #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
16654  #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
16655  #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
16656  #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
16657  #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
16658  #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
16659  #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
16660  #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
16661  #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
16662  #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
16663  #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
16664  #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
16665  #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
16666  #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
16667 /* ========================================================  GTICLF  ========================================================= */
16668  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
16669  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
16670  #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
16671  #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
16672  #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
16673  #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
16674  #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
16675  #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
16676 /* =========================================================  GTPC  ========================================================== */
16677  #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
16678  #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
16679  #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
16680  #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
16681  #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
16682  #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
16683 /* ========================================================  GTSECSR  ======================================================== */
16684  #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
16685  #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
16686  #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
16687  #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
16688  #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
16689  #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
16690  #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
16691  #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
16692  #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
16693  #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
16694  #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
16695  #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
16696  #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
16697  #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
16698  #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
16699  #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
16700  #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
16701  #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
16702  #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
16703  #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
16704 /* ========================================================  GTSECR  ========================================================= */
16705  #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
16706  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
16707  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
16708  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
16709  #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
16710  #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
16711  #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
16712  #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
16713  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
16714  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
16715  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
16716  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
16717  #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
16718  #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
16719  #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
16720  #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
16721  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
16722  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
16723  #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
16724  #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
16725  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
16726  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
16727  #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
16728  #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
16729 /* ========================================================  GTBER2  ========================================================= */
16730  #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
16731  #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
16732  #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
16733  #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
16734  #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
16735  #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
16736  #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
16737  #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
16738  #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
16739  #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
16740  #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
16741  #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
16742  #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
16743  #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
16744  #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
16745  #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
16746  #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
16747  #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
16748  #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
16749  #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
16750  #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
16751  #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
16752  #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
16753  #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
16754  #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
16755  #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
16756  #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
16757  #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
16758  #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
16759  #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
16760  #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
16761  #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
16762  #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
16763  #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
16764  #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
16765  #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
16766  #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
16767  #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
16768  #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
16769  #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
16770 /* ========================================================  GTOLBR  ========================================================= */
16771  #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
16772  #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
16773  #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
16774  #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
16775 /* ========================================================  GTICCR  ========================================================= */
16776  #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
16777  #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
16778  #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
16779  #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
16780  #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
16781  #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
16782  #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
16783  #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
16784  #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
16785  #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
16786  #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
16787  #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
16788  #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
16789  #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
16790  #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
16791  #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
16792  #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
16793  #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
16794  #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
16795  #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
16796  #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
16797  #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
16798  #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
16799  #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
16800  #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
16801  #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
16802  #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
16803  #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
16804  #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
16805  #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
16806  #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
16807  #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
16808  #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
16809  #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
16810  #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
16811  #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
16812  #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
16813  #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
16814  #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
16815  #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
16816 
16817 /* =========================================================================================================================== */
16818 /* ================                                         R_GPT_OPS                                         ================ */
16819 /* =========================================================================================================================== */
16820 
16821 /* =========================================================  OPSCR  ========================================================= */
16822  #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
16823  #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
16824  #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
16825  #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
16826  #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
16827  #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
16828  #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
16829  #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
16830  #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
16831  #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
16832  #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
16833  #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
16834  #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
16835  #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
16836  #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
16837  #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
16838  #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
16839  #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
16840  #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
16841  #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
16842  #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
16843  #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
16844  #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
16845  #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
16846  #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
16847  #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
16848  #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
16849  #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
16850  #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
16851  #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
16852  #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
16853  #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
16854  #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
16855  #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
16856 
16857 /* =========================================================================================================================== */
16858 /* ================                                        R_GPT_POEG0                                        ================ */
16859 /* =========================================================================================================================== */
16860 
16861 /* =========================================================  POEGG  ========================================================= */
16862  #define R_GPT_POEG0_POEGG_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
16863  #define R_GPT_POEG0_POEGG_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
16864  #define R_GPT_POEG0_POEGG_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
16865  #define R_GPT_POEG0_POEGG_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
16866  #define R_GPT_POEG0_POEGG_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
16867  #define R_GPT_POEG0_POEGG_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
16868  #define R_GPT_POEG0_POEGG_DERRE_Pos      (26UL)         /*!< DERRE (Bit 26)                                        */
16869  #define R_GPT_POEG0_POEGG_DERRE_Msk      (0x4000000UL)  /*!< DERRE (Bitfield-Mask: 0x01)                           */
16870  #define R_GPT_POEG0_POEGG_DERRST_Pos     (24UL)         /*!< DERRST (Bit 24)                                       */
16871  #define R_GPT_POEG0_POEGG_DERRST_Msk     (0x1000000UL)  /*!< DERRST (Bitfield-Mask: 0x01)                          */
16872  #define R_GPT_POEG0_POEGG_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
16873  #define R_GPT_POEG0_POEGG_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
16874  #define R_GPT_POEG0_POEGG_CDRE_Pos       (8UL)          /*!< CDRE (Bit 8)                                          */
16875  #define R_GPT_POEG0_POEGG_CDRE_Msk       (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
16876  #define R_GPT_POEG0_POEGG_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
16877  #define R_GPT_POEG0_POEGG_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
16878  #define R_GPT_POEG0_POEGG_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
16879  #define R_GPT_POEG0_POEGG_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
16880  #define R_GPT_POEG0_POEGG_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
16881  #define R_GPT_POEG0_POEGG_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
16882  #define R_GPT_POEG0_POEGG_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
16883  #define R_GPT_POEG0_POEGG_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
16884  #define R_GPT_POEG0_POEGG_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
16885  #define R_GPT_POEG0_POEGG_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
16886  #define R_GPT_POEG0_POEGG_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
16887  #define R_GPT_POEG0_POEGG_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
16888  #define R_GPT_POEG0_POEGG_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
16889  #define R_GPT_POEG0_POEGG_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
16890 /* ========================================================  GTONCWP  ======================================================== */
16891  #define R_GPT_POEG0_GTONCWP_WP_Pos       (0UL)          /*!< WP (Bit 0)                                            */
16892  #define R_GPT_POEG0_GTONCWP_WP_Msk       (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
16893  #define R_GPT_POEG0_GTONCWP_PRKEY_Pos    (8UL)          /*!< PRKEY (Bit 8)                                         */
16894  #define R_GPT_POEG0_GTONCWP_PRKEY_Msk    (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
16895 /* ========================================================  GTONCCR  ======================================================== */
16896  #define R_GPT_POEG0_GTONCCR_NE_Pos       (0UL)          /*!< NE (Bit 0)                                            */
16897  #define R_GPT_POEG0_GTONCCR_NE_Msk       (0x1UL)        /*!< NE (Bitfield-Mask: 0x01)                              */
16898  #define R_GPT_POEG0_GTONCCR_NFS_Pos      (4UL)          /*!< NFS (Bit 4)                                           */
16899  #define R_GPT_POEG0_GTONCCR_NFS_Msk      (0xf0UL)       /*!< NFS (Bitfield-Mask: 0x0f)                             */
16900  #define R_GPT_POEG0_GTONCCR_NFV_Pos      (8UL)          /*!< NFV (Bit 8)                                           */
16901  #define R_GPT_POEG0_GTONCCR_NFV_Msk      (0x100UL)      /*!< NFV (Bitfield-Mask: 0x01)                             */
16902 
16903 /* =========================================================================================================================== */
16904 /* ================                                           R_ICU                                           ================ */
16905 /* =========================================================================================================================== */
16906 
16907 /* =========================================================  IRQCR  ========================================================= */
16908  #define R_ICU_IRQCR_FLTEN_Pos           (7UL)          /*!< FLTEN (Bit 7)                                         */
16909  #define R_ICU_IRQCR_FLTEN_Msk           (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
16910  #define R_ICU_IRQCR_FCLKSEL_Pos         (4UL)          /*!< FCLKSEL (Bit 4)                                       */
16911  #define R_ICU_IRQCR_FCLKSEL_Msk         (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
16912  #define R_ICU_IRQCR_IRQMD_Pos           (0UL)          /*!< IRQMD (Bit 0)                                         */
16913  #define R_ICU_IRQCR_IRQMD_Msk           (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
16914 /* =========================================================  NMISR  ========================================================= */
16915  #define R_ICU_NMISR_SPEST_Pos           (12UL)         /*!< SPEST (Bit 12)                                        */
16916  #define R_ICU_NMISR_SPEST_Msk           (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
16917  #define R_ICU_NMISR_BUSMST_Pos          (11UL)         /*!< BUSMST (Bit 11)                                       */
16918  #define R_ICU_NMISR_BUSMST_Msk          (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
16919  #define R_ICU_NMISR_BUSSST_Pos          (10UL)         /*!< BUSSST (Bit 10)                                       */
16920  #define R_ICU_NMISR_BUSSST_Msk          (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
16921  #define R_ICU_NMISR_RECCST_Pos          (9UL)          /*!< RECCST (Bit 9)                                        */
16922  #define R_ICU_NMISR_RECCST_Msk          (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
16923  #define R_ICU_NMISR_RPEST_Pos           (8UL)          /*!< RPEST (Bit 8)                                         */
16924  #define R_ICU_NMISR_RPEST_Msk           (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
16925  #define R_ICU_NMISR_NMIST_Pos           (7UL)          /*!< NMIST (Bit 7)                                         */
16926  #define R_ICU_NMISR_NMIST_Msk           (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
16927  #define R_ICU_NMISR_OSTST_Pos           (6UL)          /*!< OSTST (Bit 6)                                         */
16928  #define R_ICU_NMISR_OSTST_Msk           (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
16929  #define R_ICU_NMISR_VBATTST_Pos         (4UL)          /*!< VBATTST (Bit 4)                                       */
16930  #define R_ICU_NMISR_VBATTST_Msk         (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
16931  #define R_ICU_NMISR_LVD2ST_Pos          (3UL)          /*!< LVD2ST (Bit 3)                                        */
16932  #define R_ICU_NMISR_LVD2ST_Msk          (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
16933  #define R_ICU_NMISR_LVD1ST_Pos          (2UL)          /*!< LVD1ST (Bit 2)                                        */
16934  #define R_ICU_NMISR_LVD1ST_Msk          (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
16935  #define R_ICU_NMISR_WDTST_Pos           (1UL)          /*!< WDTST (Bit 1)                                         */
16936  #define R_ICU_NMISR_WDTST_Msk           (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
16937  #define R_ICU_NMISR_IWDTST_Pos          (0UL)          /*!< IWDTST (Bit 0)                                        */
16938  #define R_ICU_NMISR_IWDTST_Msk          (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
16939  #define R_ICU_NMISR_TZFST_Pos           (13UL)         /*!< TZFST (Bit 13)                                        */
16940  #define R_ICU_NMISR_TZFST_Msk           (0x2000UL)     /*!< TZFST (Bitfield-Mask: 0x01)                           */
16941  #define R_ICU_NMISR_CPEST_Pos           (15UL)         /*!< CPEST (Bit 15)                                        */
16942  #define R_ICU_NMISR_CPEST_Msk           (0x8000UL)     /*!< CPEST (Bitfield-Mask: 0x01)                           */
16943 /* =========================================================  NMIER  ========================================================= */
16944  #define R_ICU_NMIER_SPEEN_Pos           (12UL)         /*!< SPEEN (Bit 12)                                        */
16945  #define R_ICU_NMIER_SPEEN_Msk           (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
16946  #define R_ICU_NMIER_BUSMEN_Pos          (11UL)         /*!< BUSMEN (Bit 11)                                       */
16947  #define R_ICU_NMIER_BUSMEN_Msk          (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
16948  #define R_ICU_NMIER_BUSSEN_Pos          (10UL)         /*!< BUSSEN (Bit 10)                                       */
16949  #define R_ICU_NMIER_BUSSEN_Msk          (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
16950  #define R_ICU_NMIER_RECCEN_Pos          (9UL)          /*!< RECCEN (Bit 9)                                        */
16951  #define R_ICU_NMIER_RECCEN_Msk          (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
16952  #define R_ICU_NMIER_RPEEN_Pos           (8UL)          /*!< RPEEN (Bit 8)                                         */
16953  #define R_ICU_NMIER_RPEEN_Msk           (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
16954  #define R_ICU_NMIER_NMIEN_Pos           (7UL)          /*!< NMIEN (Bit 7)                                         */
16955  #define R_ICU_NMIER_NMIEN_Msk           (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
16956  #define R_ICU_NMIER_OSTEN_Pos           (6UL)          /*!< OSTEN (Bit 6)                                         */
16957  #define R_ICU_NMIER_OSTEN_Msk           (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
16958  #define R_ICU_NMIER_VBATTEN_Pos         (4UL)          /*!< VBATTEN (Bit 4)                                       */
16959  #define R_ICU_NMIER_VBATTEN_Msk         (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
16960  #define R_ICU_NMIER_LVD2EN_Pos          (3UL)          /*!< LVD2EN (Bit 3)                                        */
16961  #define R_ICU_NMIER_LVD2EN_Msk          (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
16962  #define R_ICU_NMIER_LVD1EN_Pos          (2UL)          /*!< LVD1EN (Bit 2)                                        */
16963  #define R_ICU_NMIER_LVD1EN_Msk          (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
16964  #define R_ICU_NMIER_WDTEN_Pos           (1UL)          /*!< WDTEN (Bit 1)                                         */
16965  #define R_ICU_NMIER_WDTEN_Msk           (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
16966  #define R_ICU_NMIER_IWDTEN_Pos          (0UL)          /*!< IWDTEN (Bit 0)                                        */
16967  #define R_ICU_NMIER_IWDTEN_Msk          (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
16968  #define R_ICU_NMIER_TZFEN_Pos           (13UL)         /*!< TZFEN (Bit 13)                                        */
16969  #define R_ICU_NMIER_TZFEN_Msk           (0x2000UL)     /*!< TZFEN (Bitfield-Mask: 0x01)                           */
16970  #define R_ICU_NMIER_CPEEN_Pos           (15UL)         /*!< CPEEN (Bit 15)                                        */
16971  #define R_ICU_NMIER_CPEEN_Msk           (0x8000UL)     /*!< CPEEN (Bitfield-Mask: 0x01)                           */
16972 /* ========================================================  NMICLR  ========================================================= */
16973  #define R_ICU_NMICLR_SPECLR_Pos         (12UL)         /*!< SPECLR (Bit 12)                                       */
16974  #define R_ICU_NMICLR_SPECLR_Msk         (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
16975  #define R_ICU_NMICLR_BUSMCLR_Pos        (11UL)         /*!< BUSMCLR (Bit 11)                                      */
16976  #define R_ICU_NMICLR_BUSMCLR_Msk        (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
16977  #define R_ICU_NMICLR_BUSSCLR_Pos        (10UL)         /*!< BUSSCLR (Bit 10)                                      */
16978  #define R_ICU_NMICLR_BUSSCLR_Msk        (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
16979  #define R_ICU_NMICLR_RECCCLR_Pos        (9UL)          /*!< RECCCLR (Bit 9)                                       */
16980  #define R_ICU_NMICLR_RECCCLR_Msk        (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
16981  #define R_ICU_NMICLR_RPECLR_Pos         (8UL)          /*!< RPECLR (Bit 8)                                        */
16982  #define R_ICU_NMICLR_RPECLR_Msk         (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
16983  #define R_ICU_NMICLR_NMICLR_Pos         (7UL)          /*!< NMICLR (Bit 7)                                        */
16984  #define R_ICU_NMICLR_NMICLR_Msk         (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
16985  #define R_ICU_NMICLR_OSTCLR_Pos         (6UL)          /*!< OSTCLR (Bit 6)                                        */
16986  #define R_ICU_NMICLR_OSTCLR_Msk         (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
16987  #define R_ICU_NMICLR_VBATTCLR_Pos       (4UL)          /*!< VBATTCLR (Bit 4)                                      */
16988  #define R_ICU_NMICLR_VBATTCLR_Msk       (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
16989  #define R_ICU_NMICLR_LVD2CLR_Pos        (3UL)          /*!< LVD2CLR (Bit 3)                                       */
16990  #define R_ICU_NMICLR_LVD2CLR_Msk        (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
16991  #define R_ICU_NMICLR_LVD1CLR_Pos        (2UL)          /*!< LVD1CLR (Bit 2)                                       */
16992  #define R_ICU_NMICLR_LVD1CLR_Msk        (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
16993  #define R_ICU_NMICLR_WDTCLR_Pos         (1UL)          /*!< WDTCLR (Bit 1)                                        */
16994  #define R_ICU_NMICLR_WDTCLR_Msk         (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
16995  #define R_ICU_NMICLR_IWDTCLR_Pos        (0UL)          /*!< IWDTCLR (Bit 0)                                       */
16996  #define R_ICU_NMICLR_IWDTCLR_Msk        (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
16997  #define R_ICU_NMICLR_TZFCLR_Pos         (13UL)         /*!< TZFCLR (Bit 13)                                       */
16998  #define R_ICU_NMICLR_TZFCLR_Msk         (0x2000UL)     /*!< TZFCLR (Bitfield-Mask: 0x01)                          */
16999  #define R_ICU_NMICLR_CPECLR_Pos         (15UL)         /*!< CPECLR (Bit 15)                                       */
17000  #define R_ICU_NMICLR_CPECLR_Msk         (0x8000UL)     /*!< CPECLR (Bitfield-Mask: 0x01)                          */
17001 /* =========================================================  NMICR  ========================================================= */
17002  #define R_ICU_NMICR_NFLTEN_Pos          (7UL)          /*!< NFLTEN (Bit 7)                                        */
17003  #define R_ICU_NMICR_NFLTEN_Msk          (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
17004  #define R_ICU_NMICR_NFCLKSEL_Pos        (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
17005  #define R_ICU_NMICR_NFCLKSEL_Msk        (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
17006  #define R_ICU_NMICR_NMIMD_Pos           (0UL)          /*!< NMIMD (Bit 0)                                         */
17007  #define R_ICU_NMICR_NMIMD_Msk           (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
17008 /* =========================================================  IELSR  ========================================================= */
17009  #define R_ICU_IELSR_DTCE_Pos            (24UL)         /*!< DTCE (Bit 24)                                         */
17010  #define R_ICU_IELSR_DTCE_Msk            (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
17011  #define R_ICU_IELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
17012  #define R_ICU_IELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
17013  #define R_ICU_IELSR_IELS_Pos            (0UL)          /*!< IELS (Bit 0)                                          */
17014  #define R_ICU_IELSR_IELS_Msk            (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
17015 /* =========================================================  DELSR  ========================================================= */
17016  #define R_ICU_DELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
17017  #define R_ICU_DELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
17018  #define R_ICU_DELSR_DELS_Pos            (0UL)          /*!< DELS (Bit 0)                                          */
17019  #define R_ICU_DELSR_DELS_Msk            (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
17020 /* ========================================================  SELSR0  ========================================================= */
17021  #define R_ICU_SELSR0_SELS_Pos           (0UL)          /*!< SELS (Bit 0)                                          */
17022  #define R_ICU_SELSR0_SELS_Msk           (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
17023 /* =========================================================  WUPEN  ========================================================= */
17024  #define R_ICU_WUPEN_IIC0WUPEN_Pos       (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
17025  #define R_ICU_WUPEN_IIC0WUPEN_Msk       (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
17026  #define R_ICU_WUPEN_AGT1CBWUPEN_Pos     (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
17027  #define R_ICU_WUPEN_AGT1CBWUPEN_Msk     (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
17028  #define R_ICU_WUPEN_AGT1CAWUPEN_Pos     (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
17029  #define R_ICU_WUPEN_AGT1CAWUPEN_Msk     (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
17030  #define R_ICU_WUPEN_AGT1UDWUPEN_Pos     (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
17031  #define R_ICU_WUPEN_AGT1UDWUPEN_Msk     (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
17032  #define R_ICU_WUPEN_USBFSWUPEN_Pos      (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
17033  #define R_ICU_WUPEN_USBFSWUPEN_Msk      (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
17034  #define R_ICU_WUPEN_USBHSWUPEN_Pos      (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
17035  #define R_ICU_WUPEN_USBHSWUPEN_Msk      (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
17036  #define R_ICU_WUPEN_RTCPRDWUPEN_Pos     (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
17037  #define R_ICU_WUPEN_RTCPRDWUPEN_Msk     (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
17038  #define R_ICU_WUPEN_RTCALMWUPEN_Pos     (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
17039  #define R_ICU_WUPEN_RTCALMWUPEN_Msk     (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
17040  #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos    (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
17041  #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk    (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
17042  #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos    (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
17043  #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk    (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
17044  #define R_ICU_WUPEN_VBATTWUPEN_Pos      (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
17045  #define R_ICU_WUPEN_VBATTWUPEN_Msk      (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
17046  #define R_ICU_WUPEN_LVD2WUPEN_Pos       (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
17047  #define R_ICU_WUPEN_LVD2WUPEN_Msk       (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
17048  #define R_ICU_WUPEN_LVD1WUPEN_Pos       (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
17049  #define R_ICU_WUPEN_LVD1WUPEN_Msk       (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
17050  #define R_ICU_WUPEN_KEYWUPEN_Pos        (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
17051  #define R_ICU_WUPEN_KEYWUPEN_Msk        (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
17052  #define R_ICU_WUPEN_IWDTWUPEN_Pos       (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
17053  #define R_ICU_WUPEN_IWDTWUPEN_Msk       (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
17054  #define R_ICU_WUPEN_IRQWUPEN_Pos        (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
17055  #define R_ICU_WUPEN_IRQWUPEN_Msk        (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
17056 /* ========================================================  WUPEN1  ========================================================= */
17057  #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos    (0UL)          /*!< AGT3UDWUPEN (Bit 0)                                   */
17058  #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk    (0x1UL)        /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01)                     */
17059  #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos    (1UL)          /*!< AGT3CAWUPEN (Bit 1)                                   */
17060  #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk    (0x2UL)        /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01)                     */
17061  #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos    (2UL)          /*!< AGT3CBWUPEN (Bit 2)                                   */
17062  #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk    (0x4UL)        /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01)                     */
17063 /* =========================================================  IELEN  ========================================================= */
17064  #define R_ICU_IELEN_IELEN_Pos           (1UL)          /*!< IELEN (Bit 1)                                         */
17065  #define R_ICU_IELEN_IELEN_Msk           (0x2UL)        /*!< IELEN (Bitfield-Mask: 0x01)                           */
17066  #define R_ICU_IELEN_RTCINTEN_Pos        (0UL)          /*!< RTCINTEN (Bit 0)                                      */
17067  #define R_ICU_IELEN_RTCINTEN_Msk        (0x1UL)        /*!< RTCINTEN (Bitfield-Mask: 0x01)                        */
17068 
17069 /* =========================================================================================================================== */
17070 /* ================                                          R_IIC0                                           ================ */
17071 /* =========================================================================================================================== */
17072 
17073 /* =========================================================  ICCR1  ========================================================= */
17074  #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
17075  #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
17076  #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
17077  #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
17078  #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
17079  #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
17080  #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
17081  #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
17082  #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
17083  #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
17084  #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
17085  #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
17086  #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
17087  #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
17088  #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
17089  #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
17090 /* =========================================================  ICCR2  ========================================================= */
17091  #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
17092  #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
17093  #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
17094  #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
17095  #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
17096  #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
17097  #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
17098  #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
17099  #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
17100  #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
17101  #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
17102  #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
17103 /* =========================================================  ICMR1  ========================================================= */
17104  #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
17105  #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
17106  #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
17107  #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
17108  #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
17109  #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
17110  #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
17111  #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
17112 /* =========================================================  ICMR2  ========================================================= */
17113  #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
17114  #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
17115  #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
17116  #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
17117  #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
17118  #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
17119  #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
17120  #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
17121  #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
17122  #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
17123 /* =========================================================  ICMR3  ========================================================= */
17124  #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
17125  #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
17126  #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
17127  #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
17128  #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
17129  #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
17130  #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
17131  #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
17132  #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
17133  #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
17134  #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
17135  #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
17136  #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
17137  #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
17138 /* =========================================================  ICFER  ========================================================= */
17139  #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
17140  #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
17141  #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
17142  #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
17143  #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
17144  #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
17145  #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
17146  #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
17147  #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
17148  #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
17149  #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
17150  #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
17151  #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
17152  #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
17153  #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
17154  #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
17155 /* =========================================================  ICSER  ========================================================= */
17156  #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
17157  #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
17158  #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
17159  #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
17160  #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
17161  #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
17162  #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
17163  #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
17164  #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
17165  #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
17166  #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
17167  #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
17168 /* =========================================================  ICIER  ========================================================= */
17169  #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
17170  #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
17171  #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
17172  #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
17173  #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
17174  #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
17175  #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
17176  #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
17177  #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
17178  #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
17179  #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
17180  #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
17181  #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
17182  #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
17183  #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
17184  #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
17185 /* =========================================================  ICSR1  ========================================================= */
17186  #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
17187  #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
17188  #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
17189  #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
17190  #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
17191  #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
17192  #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
17193  #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
17194  #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
17195  #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
17196  #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
17197  #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
17198 /* =========================================================  ICSR2  ========================================================= */
17199  #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
17200  #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
17201  #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
17202  #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
17203  #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
17204  #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
17205  #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
17206  #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
17207  #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
17208  #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
17209  #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
17210  #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
17211  #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
17212  #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
17213  #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
17214  #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
17215 /* =========================================================  ICBRL  ========================================================= */
17216  #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
17217  #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
17218 /* =========================================================  ICBRH  ========================================================= */
17219  #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
17220  #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
17221 /* =========================================================  ICDRT  ========================================================= */
17222  #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
17223  #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
17224 /* =========================================================  ICDRR  ========================================================= */
17225  #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
17226  #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
17227 /* =========================================================  ICWUR  ========================================================= */
17228  #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
17229  #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
17230  #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
17231  #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
17232  #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
17233  #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
17234  #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
17235  #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
17236  #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
17237  #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
17238 /* ========================================================  ICWUR2  ========================================================= */
17239  #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
17240  #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
17241  #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
17242  #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
17243  #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
17244  #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
17245 
17246 /* =========================================================================================================================== */
17247 /* ================                                          R_IWDT                                           ================ */
17248 /* =========================================================================================================================== */
17249 
17250 /* ========================================================  IWDTRR  ========================================================= */
17251  #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
17252  #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
17253 /* ========================================================  IWDTCR  ========================================================= */
17254  #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
17255  #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
17256  #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
17257  #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
17258  #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
17259  #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
17260  #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
17261  #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
17262 /* ========================================================  IWDTSR  ========================================================= */
17263  #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
17264  #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
17265  #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
17266  #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
17267  #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
17268  #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
17269 /* ========================================================  IWDTRCR  ======================================================== */
17270  #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
17271  #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
17272 /* =======================================================  IWDTCSTPR  ======================================================= */
17273  #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
17274  #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
17275 
17276 /* =========================================================================================================================== */
17277 /* ================                                          R_KINT                                           ================ */
17278 /* =========================================================================================================================== */
17279 
17280 /* =========================================================  KRCTL  ========================================================= */
17281  #define R_KINT_KRCTL_KRMD_Pos    (7UL)    /*!< KRMD (Bit 7)                                          */
17282  #define R_KINT_KRCTL_KRMD_Msk    (0x80UL) /*!< KRMD (Bitfield-Mask: 0x01)                            */
17283  #define R_KINT_KRCTL_KREG_Pos    (0UL)    /*!< KREG (Bit 0)                                          */
17284  #define R_KINT_KRCTL_KREG_Msk    (0x1UL)  /*!< KREG (Bitfield-Mask: 0x01)                            */
17285 /* ==========================================================  KRF  ========================================================== */
17286  #define R_KINT_KRF_KRF7_Pos      (7UL)    /*!< KRF7 (Bit 7)                                          */
17287  #define R_KINT_KRF_KRF7_Msk      (0x80UL) /*!< KRF7 (Bitfield-Mask: 0x01)                            */
17288  #define R_KINT_KRF_KRF6_Pos      (6UL)    /*!< KRF6 (Bit 6)                                          */
17289  #define R_KINT_KRF_KRF6_Msk      (0x40UL) /*!< KRF6 (Bitfield-Mask: 0x01)                            */
17290  #define R_KINT_KRF_KRF5_Pos      (5UL)    /*!< KRF5 (Bit 5)                                          */
17291  #define R_KINT_KRF_KRF5_Msk      (0x20UL) /*!< KRF5 (Bitfield-Mask: 0x01)                            */
17292  #define R_KINT_KRF_KRF4_Pos      (4UL)    /*!< KRF4 (Bit 4)                                          */
17293  #define R_KINT_KRF_KRF4_Msk      (0x10UL) /*!< KRF4 (Bitfield-Mask: 0x01)                            */
17294  #define R_KINT_KRF_KRF3_Pos      (3UL)    /*!< KRF3 (Bit 3)                                          */
17295  #define R_KINT_KRF_KRF3_Msk      (0x8UL)  /*!< KRF3 (Bitfield-Mask: 0x01)                            */
17296  #define R_KINT_KRF_KRF2_Pos      (2UL)    /*!< KRF2 (Bit 2)                                          */
17297  #define R_KINT_KRF_KRF2_Msk      (0x4UL)  /*!< KRF2 (Bitfield-Mask: 0x01)                            */
17298  #define R_KINT_KRF_KRF1_Pos      (1UL)    /*!< KRF1 (Bit 1)                                          */
17299  #define R_KINT_KRF_KRF1_Msk      (0x2UL)  /*!< KRF1 (Bitfield-Mask: 0x01)                            */
17300  #define R_KINT_KRF_KRF0_Pos      (0UL)    /*!< KRF0 (Bit 0)                                          */
17301  #define R_KINT_KRF_KRF0_Msk      (0x1UL)  /*!< KRF0 (Bitfield-Mask: 0x01)                            */
17302 /* ==========================================================  KRM  ========================================================== */
17303  #define R_KINT_KRM_KRM7_Pos      (7UL)    /*!< KRM7 (Bit 7)                                          */
17304  #define R_KINT_KRM_KRM7_Msk      (0x80UL) /*!< KRM7 (Bitfield-Mask: 0x01)                            */
17305  #define R_KINT_KRM_KRM6_Pos      (6UL)    /*!< KRM6 (Bit 6)                                          */
17306  #define R_KINT_KRM_KRM6_Msk      (0x40UL) /*!< KRM6 (Bitfield-Mask: 0x01)                            */
17307  #define R_KINT_KRM_KRM5_Pos      (5UL)    /*!< KRM5 (Bit 5)                                          */
17308  #define R_KINT_KRM_KRM5_Msk      (0x20UL) /*!< KRM5 (Bitfield-Mask: 0x01)                            */
17309  #define R_KINT_KRM_KRM4_Pos      (4UL)    /*!< KRM4 (Bit 4)                                          */
17310  #define R_KINT_KRM_KRM4_Msk      (0x10UL) /*!< KRM4 (Bitfield-Mask: 0x01)                            */
17311  #define R_KINT_KRM_KRM3_Pos      (3UL)    /*!< KRM3 (Bit 3)                                          */
17312  #define R_KINT_KRM_KRM3_Msk      (0x8UL)  /*!< KRM3 (Bitfield-Mask: 0x01)                            */
17313  #define R_KINT_KRM_KRM2_Pos      (2UL)    /*!< KRM2 (Bit 2)                                          */
17314  #define R_KINT_KRM_KRM2_Msk      (0x4UL)  /*!< KRM2 (Bitfield-Mask: 0x01)                            */
17315  #define R_KINT_KRM_KRM1_Pos      (1UL)    /*!< KRM1 (Bit 1)                                          */
17316  #define R_KINT_KRM_KRM1_Msk      (0x2UL)  /*!< KRM1 (Bitfield-Mask: 0x01)                            */
17317  #define R_KINT_KRM_KRM0_Pos      (0UL)    /*!< KRM0 (Bit 0)                                          */
17318  #define R_KINT_KRM_KRM0_Msk      (0x1UL)  /*!< KRM0 (Bitfield-Mask: 0x01)                            */
17319 
17320 /* =========================================================================================================================== */
17321 /* ================                                           R_MMF                                           ================ */
17322 /* =========================================================================================================================== */
17323 
17324 /* =========================================================  MMSFR  ========================================================= */
17325  #define R_MMF_MMSFR_KEY_Pos           (24UL)         /*!< KEY (Bit 24)                                          */
17326  #define R_MMF_MMSFR_KEY_Msk           (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
17327  #define R_MMF_MMSFR_MEMMIRADDR_Pos    (7UL)          /*!< MEMMIRADDR (Bit 7)                                    */
17328  #define R_MMF_MMSFR_MEMMIRADDR_Msk    (0x7fff80UL)   /*!< MEMMIRADDR (Bitfield-Mask: 0xffff)                    */
17329 /* =========================================================  MMEN  ========================================================== */
17330  #define R_MMF_MMEN_KEY_Pos            (24UL)         /*!< KEY (Bit 24)                                          */
17331  #define R_MMF_MMEN_KEY_Msk            (0xff000000UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
17332  #define R_MMF_MMEN_EN_Pos             (0UL)          /*!< EN (Bit 0)                                            */
17333  #define R_MMF_MMEN_EN_Msk             (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
17334 
17335 /* =========================================================================================================================== */
17336 /* ================                                        R_MPU_MMPU                                         ================ */
17337 /* =========================================================================================================================== */
17338 
17339 /* =========================================================================================================================== */
17340 /* ================                                        R_MPU_SMPU                                         ================ */
17341 /* =========================================================================================================================== */
17342 
17343 /* ========================================================  SMPUCTL  ======================================================== */
17344  #define R_MPU_SMPU_SMPUCTL_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
17345  #define R_MPU_SMPU_SMPUCTL_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
17346  #define R_MPU_SMPU_SMPUCTL_PROTECT_Pos    (1UL)      /*!< PROTECT (Bit 1)                                       */
17347  #define R_MPU_SMPU_SMPUCTL_PROTECT_Msk    (0x2UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
17348  #define R_MPU_SMPU_SMPUCTL_OAD_Pos        (0UL)      /*!< OAD (Bit 0)                                           */
17349  #define R_MPU_SMPU_SMPUCTL_OAD_Msk        (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
17350 
17351 /* =========================================================================================================================== */
17352 /* ================                                        R_MPU_SPMON                                        ================ */
17353 /* =========================================================================================================================== */
17354 
17355 /* =========================================================================================================================== */
17356 /* ================                                          R_MSTP                                           ================ */
17357 /* =========================================================================================================================== */
17358 
17359 /* ========================================================  MSTPCRA  ======================================================== */
17360  #define R_MSTP_MSTPCRA_MSTPA_Pos        (0UL)      /*!< MSTPA (Bit 0)                                         */
17361  #define R_MSTP_MSTPCRA_MSTPA_Msk        (0x1UL)    /*!< MSTPA (Bitfield-Mask: 0x01)                           */
17362 /* ========================================================  MSTPCRB  ======================================================== */
17363  #define R_MSTP_MSTPCRB_MSTPB_Pos        (0UL)      /*!< MSTPB (Bit 0)                                         */
17364  #define R_MSTP_MSTPCRB_MSTPB_Msk        (0x1UL)    /*!< MSTPB (Bitfield-Mask: 0x01)                           */
17365 /* ========================================================  MSTPCRC  ======================================================== */
17366  #define R_MSTP_MSTPCRC_MSTPC_Pos        (0UL)      /*!< MSTPC (Bit 0)                                         */
17367  #define R_MSTP_MSTPCRC_MSTPC_Msk        (0x1UL)    /*!< MSTPC (Bitfield-Mask: 0x01)                           */
17368 /* ========================================================  MSTPCRD  ======================================================== */
17369  #define R_MSTP_MSTPCRD_MSTPD_Pos        (0UL)      /*!< MSTPD (Bit 0)                                         */
17370  #define R_MSTP_MSTPCRD_MSTPD_Msk        (0x1UL)    /*!< MSTPD (Bitfield-Mask: 0x01)                           */
17371 /* ========================================================  MSTPCRE  ======================================================== */
17372  #define R_MSTP_MSTPCRE_MSTPE_Pos        (0UL)      /*!< MSTPE (Bit 0)                                         */
17373  #define R_MSTP_MSTPCRE_MSTPE_Msk        (0x1UL)    /*!< MSTPE (Bitfield-Mask: 0x01)                           */
17374 /* =======================================================  LSMRWDIS  ======================================================== */
17375  #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos    (0UL)      /*!< RTCRWDIS (Bit 0)                                      */
17376  #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk    (0x1UL)    /*!< RTCRWDIS (Bitfield-Mask: 0x01)                        */
17377  #define R_MSTP_LSMRWDIS_WDTDIS_Pos      (1UL)      /*!< WDTDIS (Bit 1)                                        */
17378  #define R_MSTP_LSMRWDIS_WDTDIS_Msk      (0x2UL)    /*!< WDTDIS (Bitfield-Mask: 0x01)                          */
17379  #define R_MSTP_LSMRWDIS_IWDTIDS_Pos     (2UL)      /*!< IWDTIDS (Bit 2)                                       */
17380  #define R_MSTP_LSMRWDIS_IWDTIDS_Msk     (0x4UL)    /*!< IWDTIDS (Bitfield-Mask: 0x01)                         */
17381  #define R_MSTP_LSMRWDIS_WREN_Pos        (7UL)      /*!< WREN (Bit 7)                                          */
17382  #define R_MSTP_LSMRWDIS_WREN_Msk        (0x80UL)   /*!< WREN (Bitfield-Mask: 0x01)                            */
17383  #define R_MSTP_LSMRWDIS_PRKEY_Pos       (8UL)      /*!< PRKEY (Bit 8)                                         */
17384  #define R_MSTP_LSMRWDIS_PRKEY_Msk       (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
17385 
17386 /* =========================================================================================================================== */
17387 /* ================                                          R_OPAMP                                          ================ */
17388 /* =========================================================================================================================== */
17389 
17390 /* =========================================================  AMPMC  ========================================================= */
17391  #define R_OPAMP_AMPMC_AMPSP_Pos      (7UL)    /*!< AMPSP (Bit 7)                                         */
17392  #define R_OPAMP_AMPMC_AMPSP_Msk      (0x80UL) /*!< AMPSP (Bitfield-Mask: 0x01)                           */
17393  #define R_OPAMP_AMPMC_AMPPC_Pos      (0UL)    /*!< AMPPC (Bit 0)                                         */
17394  #define R_OPAMP_AMPMC_AMPPC_Msk      (0x1UL)  /*!< AMPPC (Bitfield-Mask: 0x01)                           */
17395 /* ========================================================  AMPTRM  ========================================================= */
17396  #define R_OPAMP_AMPTRM_AMPTRM_Pos    (0UL)    /*!< AMPTRM (Bit 0)                                        */
17397  #define R_OPAMP_AMPTRM_AMPTRM_Msk    (0x3UL)  /*!< AMPTRM (Bitfield-Mask: 0x03)                          */
17398 /* ========================================================  AMPTRS  ========================================================= */
17399  #define R_OPAMP_AMPTRS_AMPTRS_Pos    (0UL)    /*!< AMPTRS (Bit 0)                                        */
17400  #define R_OPAMP_AMPTRS_AMPTRS_Msk    (0x3UL)  /*!< AMPTRS (Bitfield-Mask: 0x03)                          */
17401 /* =========================================================  AMPC  ========================================================== */
17402  #define R_OPAMP_AMPC_IREFE_Pos       (7UL)    /*!< IREFE (Bit 7)                                         */
17403  #define R_OPAMP_AMPC_IREFE_Msk       (0x80UL) /*!< IREFE (Bitfield-Mask: 0x01)                           */
17404  #define R_OPAMP_AMPC_AMPE_Pos        (0UL)    /*!< AMPE (Bit 0)                                          */
17405  #define R_OPAMP_AMPC_AMPE_Msk        (0x1UL)  /*!< AMPE (Bitfield-Mask: 0x01)                            */
17406 /* ========================================================  AMPMON  ========================================================= */
17407  #define R_OPAMP_AMPMON_AMPMON_Pos    (0UL)    /*!< AMPMON (Bit 0)                                        */
17408  #define R_OPAMP_AMPMON_AMPMON_Msk    (0x1UL)  /*!< AMPMON (Bitfield-Mask: 0x01)                          */
17409 /* ========================================================  AMPCPC  ========================================================= */
17410  #define R_OPAMP_AMPCPC_PUMPEN_Pos    (0UL)    /*!< PUMPEN (Bit 0)                                        */
17411  #define R_OPAMP_AMPCPC_PUMPEN_Msk    (0x1UL)  /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
17412 /* ========================================================  AMPUOTE  ======================================================== */
17413  #define R_OPAMP_AMPUOTE_AMPTE_Pos    (0UL)    /*!< AMPTE (Bit 0)                                         */
17414  #define R_OPAMP_AMPUOTE_AMPTE_Msk    (0x1UL)  /*!< AMPTE (Bitfield-Mask: 0x01)                           */
17415 
17416 /* =========================================================================================================================== */
17417 /* ================                                          R_PORT0                                          ================ */
17418 /* =========================================================================================================================== */
17419 
17420 /* ========================================================  PCNTR1  ========================================================= */
17421  #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
17422  #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
17423  #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
17424  #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
17425 /* =========================================================  PODR  ========================================================== */
17426  #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
17427  #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
17428 /* ==========================================================  PDR  ========================================================== */
17429  #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
17430  #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
17431 /* ========================================================  PCNTR2  ========================================================= */
17432  #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
17433  #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
17434  #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
17435  #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
17436 /* =========================================================  EIDR  ========================================================== */
17437  #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
17438  #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
17439 /* =========================================================  PIDR  ========================================================== */
17440  #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
17441  #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
17442 /* ========================================================  PCNTR3  ========================================================= */
17443  #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
17444  #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
17445  #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
17446  #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
17447 /* =========================================================  PORR  ========================================================== */
17448  #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
17449  #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
17450 /* =========================================================  POSR  ========================================================== */
17451  #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
17452  #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
17453 /* ========================================================  PCNTR4  ========================================================= */
17454  #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
17455  #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
17456  #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
17457  #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
17458 /* =========================================================  EORR  ========================================================== */
17459  #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
17460  #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
17461 /* =========================================================  EOSR  ========================================================== */
17462  #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
17463  #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
17464 
17465 /* =========================================================================================================================== */
17466 /* ================                                           R_PFS                                           ================ */
17467 /* =========================================================================================================================== */
17468 
17469 /* =========================================================================================================================== */
17470 /* ================                                          R_PMISC                                          ================ */
17471 /* =========================================================================================================================== */
17472 
17473 /* ========================================================  PFENET  ========================================================= */
17474  #define R_PMISC_PFENET_PHYMODE1_Pos    (5UL)    /*!< PHYMODE1 (Bit 5)                                      */
17475  #define R_PMISC_PFENET_PHYMODE1_Msk    (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01)                        */
17476  #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
17477  #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
17478 /* =========================================================  PWPR  ========================================================== */
17479  #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
17480  #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
17481  #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
17482  #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
17483 /* =========================================================  PWPRS  ========================================================= */
17484  #define R_PMISC_PWPRS_PFSWE_Pos        (6UL)    /*!< PFSWE (Bit 6)                                         */
17485  #define R_PMISC_PWPRS_PFSWE_Msk        (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
17486  #define R_PMISC_PWPRS_B0WI_Pos         (7UL)    /*!< B0WI (Bit 7)                                          */
17487  #define R_PMISC_PWPRS_B0WI_Msk         (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
17488 /* ========================================================  PRWCNTR  ======================================================== */
17489  #define R_PMISC_PRWCNTR_WAIT_Pos       (0UL)    /*!< WAIT (Bit 0)                                          */
17490  #define R_PMISC_PRWCNTR_WAIT_Msk       (0x3UL)  /*!< WAIT (Bitfield-Mask: 0x03)                            */
17491 
17492 /* =========================================================================================================================== */
17493 /* ================                                           R_RTC                                           ================ */
17494 /* =========================================================================================================================== */
17495 
17496 /* ========================================================  R64CNT  ========================================================= */
17497  #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
17498  #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
17499  #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
17500  #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
17501  #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
17502  #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
17503  #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
17504  #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
17505  #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
17506  #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
17507  #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
17508  #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
17509  #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
17510  #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
17511 /* =========================================================  BCNT0  ========================================================= */
17512  #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
17513  #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
17514 /* ========================================================  RSECCNT  ======================================================== */
17515  #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
17516  #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
17517  #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
17518  #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
17519 /* =========================================================  BCNT1  ========================================================= */
17520  #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
17521  #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
17522 /* ========================================================  RMINCNT  ======================================================== */
17523  #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
17524  #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
17525  #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
17526  #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
17527 /* =========================================================  BCNT2  ========================================================= */
17528  #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
17529  #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
17530 /* ========================================================  RHRCNT  ========================================================= */
17531  #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
17532  #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
17533  #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
17534  #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
17535  #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
17536  #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
17537 /* =========================================================  BCNT3  ========================================================= */
17538  #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
17539  #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
17540 /* ========================================================  RWKCNT  ========================================================= */
17541  #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
17542  #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
17543 /* ========================================================  RDAYCNT  ======================================================== */
17544  #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
17545  #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
17546  #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
17547  #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
17548 /* ========================================================  RMONCNT  ======================================================== */
17549  #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
17550  #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
17551  #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
17552  #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
17553 /* ========================================================  RYRCNT  ========================================================= */
17554  #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
17555  #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
17556  #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
17557  #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
17558 /* ========================================================  BCNT0AR  ======================================================== */
17559  #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
17560  #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
17561 /* ========================================================  RSECAR  ========================================================= */
17562  #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
17563  #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
17564  #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
17565  #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
17566  #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
17567  #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
17568 /* ========================================================  BCNT1AR  ======================================================== */
17569  #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
17570  #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
17571 /* ========================================================  RMINAR  ========================================================= */
17572  #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
17573  #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
17574  #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
17575  #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
17576  #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
17577  #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
17578 /* ========================================================  BCNT2AR  ======================================================== */
17579  #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
17580  #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
17581 /* =========================================================  RHRAR  ========================================================= */
17582  #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
17583  #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
17584  #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
17585  #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
17586  #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
17587  #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
17588  #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
17589  #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
17590 /* ========================================================  BCNT3AR  ======================================================== */
17591  #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
17592  #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
17593 /* =========================================================  RWKAR  ========================================================= */
17594  #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
17595  #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
17596  #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
17597  #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
17598 /* =======================================================  BCNT0AER  ======================================================== */
17599  #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
17600  #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
17601 /* ========================================================  RDAYAR  ========================================================= */
17602  #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
17603  #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
17604  #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
17605  #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
17606  #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
17607  #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
17608 /* =======================================================  BCNT1AER  ======================================================== */
17609  #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
17610  #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
17611 /* ========================================================  RMONAR  ========================================================= */
17612  #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
17613  #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
17614  #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
17615  #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
17616  #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
17617  #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
17618 /* =======================================================  BCNT2AER  ======================================================== */
17619  #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
17620  #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
17621 /* =========================================================  RYRAR  ========================================================= */
17622  #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
17623  #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
17624  #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
17625  #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
17626 /* =======================================================  BCNT3AER  ======================================================== */
17627  #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
17628  #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
17629 /* ========================================================  RYRAREN  ======================================================== */
17630  #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
17631  #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
17632 /* =========================================================  RCR1  ========================================================== */
17633  #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
17634  #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
17635  #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
17636  #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
17637  #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
17638  #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
17639  #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
17640  #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
17641  #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
17642  #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
17643 /* =========================================================  RCR2  ========================================================== */
17644  #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
17645  #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
17646  #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
17647  #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
17648  #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
17649  #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
17650  #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
17651  #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
17652  #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
17653  #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
17654  #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
17655  #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
17656  #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
17657  #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
17658  #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
17659  #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
17660 /* =========================================================  RCR4  ========================================================== */
17661  #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
17662  #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
17663  #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
17664  #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
17665 /* =========================================================  RFRH  ========================================================== */
17666  #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
17667  #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
17668 /* =========================================================  RFRL  ========================================================== */
17669  #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
17670  #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
17671 /* =========================================================  RADJ  ========================================================== */
17672  #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
17673  #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
17674  #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
17675  #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
17676 
17677 /* =========================================================================================================================== */
17678 /* ================                                          R_SCI0                                           ================ */
17679 /* =========================================================================================================================== */
17680 
17681 /* ==========================================================  SMR  ========================================================== */
17682  #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
17683  #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
17684  #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
17685  #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
17686  #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
17687  #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
17688  #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
17689  #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
17690  #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
17691  #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
17692  #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
17693  #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
17694  #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
17695  #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
17696 /* =======================================================  SMR_SMCI  ======================================================== */
17697  #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
17698  #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
17699  #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
17700  #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
17701  #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
17702  #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
17703  #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
17704  #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
17705  #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
17706  #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
17707  #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
17708  #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
17709 /* ==========================================================  BRR  ========================================================== */
17710  #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
17711  #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
17712 /* ==========================================================  SCR  ========================================================== */
17713  #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
17714  #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
17715  #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
17716  #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
17717  #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
17718  #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
17719  #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
17720  #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
17721  #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
17722  #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
17723  #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
17724  #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
17725  #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
17726  #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
17727 /* =======================================================  SCR_SMCI  ======================================================== */
17728  #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
17729  #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
17730  #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
17731  #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
17732  #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
17733  #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
17734  #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
17735  #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
17736  #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
17737  #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
17738  #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
17739  #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
17740  #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
17741  #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
17742 /* ==========================================================  TDR  ========================================================== */
17743  #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
17744  #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
17745 /* ==========================================================  SSR  ========================================================== */
17746  #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
17747  #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
17748  #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
17749  #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
17750  #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
17751  #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
17752  #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
17753  #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
17754  #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
17755  #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
17756  #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
17757  #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
17758  #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
17759  #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
17760  #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
17761  #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
17762 /* =======================================================  SSR_FIFO  ======================================================== */
17763  #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
17764  #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
17765  #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
17766  #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
17767  #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
17768  #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
17769  #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
17770  #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
17771  #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
17772  #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
17773  #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
17774  #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
17775  #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
17776  #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
17777 /* =======================================================  SSR_SMCI  ======================================================== */
17778  #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
17779  #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
17780  #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
17781  #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
17782  #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
17783  #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
17784  #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
17785  #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
17786  #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
17787  #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
17788  #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
17789  #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
17790  #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
17791  #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
17792  #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
17793  #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
17794 /* ==========================================================  RDR  ========================================================== */
17795  #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
17796  #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
17797 /* =========================================================  SCMR  ========================================================== */
17798  #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
17799  #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
17800  #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
17801  #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
17802  #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
17803  #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
17804  #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
17805  #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
17806  #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
17807  #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
17808 /* =========================================================  SEMR  ========================================================== */
17809  #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
17810  #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
17811  #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
17812  #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
17813  #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
17814  #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
17815  #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
17816  #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
17817  #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
17818  #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
17819  #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
17820  #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
17821  #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
17822  #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
17823  #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
17824  #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
17825 /* =========================================================  SNFR  ========================================================== */
17826  #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
17827  #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
17828 /* =========================================================  SIMR1  ========================================================= */
17829  #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
17830  #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
17831  #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
17832  #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
17833 /* =========================================================  SIMR2  ========================================================= */
17834  #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
17835  #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
17836  #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
17837  #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
17838  #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
17839  #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
17840 /* =========================================================  SIMR3  ========================================================= */
17841  #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
17842  #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
17843  #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
17844  #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
17845  #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
17846  #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
17847  #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
17848  #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
17849  #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
17850  #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
17851  #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
17852  #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
17853 /* =========================================================  SISR  ========================================================== */
17854  #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
17855  #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
17856 /* =========================================================  SPMR  ========================================================== */
17857  #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
17858  #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
17859  #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
17860  #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
17861  #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
17862  #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
17863  #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
17864  #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
17865  #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
17866  #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
17867  #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
17868  #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
17869  #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
17870  #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
17871 /* =========================================================  TDRHL  ========================================================= */
17872  #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
17873  #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
17874 /* ========================================================  FTDRHL  ========================================================= */
17875  #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
17876  #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
17877  #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
17878  #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
17879 /* =========================================================  FTDRH  ========================================================= */
17880  #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
17881  #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
17882  #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
17883  #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
17884 /* =========================================================  FTDRL  ========================================================= */
17885  #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
17886  #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
17887 /* =========================================================  RDRHL  ========================================================= */
17888  #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
17889  #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
17890 /* ========================================================  FRDRHL  ========================================================= */
17891  #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
17892  #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
17893  #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
17894  #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
17895  #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
17896  #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
17897  #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
17898  #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
17899  #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
17900  #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
17901  #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
17902  #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
17903  #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
17904  #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
17905 /* =========================================================  FRDRH  ========================================================= */
17906  #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
17907  #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
17908  #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
17909  #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
17910  #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
17911  #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
17912  #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
17913  #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
17914  #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
17915  #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
17916  #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
17917  #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
17918  #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
17919  #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
17920 /* =========================================================  FRDRL  ========================================================= */
17921  #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
17922  #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
17923 /* =========================================================  MDDR  ========================================================== */
17924  #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
17925  #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
17926 /* =========================================================  DCCR  ========================================================== */
17927  #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
17928  #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
17929  #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
17930  #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
17931  #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
17932  #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
17933  #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
17934  #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
17935  #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
17936  #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
17937 /* ==========================================================  FCR  ========================================================== */
17938  #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
17939  #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
17940  #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
17941  #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
17942  #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
17943  #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
17944  #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
17945  #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
17946  #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
17947  #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
17948  #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
17949  #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
17950  #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
17951  #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
17952 /* ==========================================================  FDR  ========================================================== */
17953  #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
17954  #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
17955  #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
17956  #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
17957 /* ==========================================================  LSR  ========================================================== */
17958  #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
17959  #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
17960  #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
17961  #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
17962  #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
17963  #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
17964 /* ==========================================================  CDR  ========================================================== */
17965  #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
17966  #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
17967 /* =========================================================  SPTR  ========================================================== */
17968  #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
17969  #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
17970  #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
17971  #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
17972  #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
17973  #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
17974  #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
17975  #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
17976  #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
17977  #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
17978  #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
17979  #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
17980  #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
17981  #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
17982 /* =========================================================  ACTR  ========================================================== */
17983  #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
17984  #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
17985  #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
17986  #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
17987  #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
17988  #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
17989  #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
17990  #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
17991 /* =========================================================  ESMER  ========================================================= */
17992  #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
17993  #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
17994 /* ==========================================================  CR0  ========================================================== */
17995  #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
17996  #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
17997  #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
17998  #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
17999  #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
18000  #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
18001 /* ==========================================================  CR1  ========================================================== */
18002  #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
18003  #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
18004  #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
18005  #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
18006  #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
18007  #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
18008  #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
18009  #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
18010  #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
18011  #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
18012 /* ==========================================================  CR2  ========================================================== */
18013  #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
18014  #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
18015  #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
18016  #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
18017  #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
18018  #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
18019 /* ==========================================================  CR3  ========================================================== */
18020  #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
18021  #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
18022 /* ==========================================================  PCR  ========================================================== */
18023  #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
18024  #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
18025  #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
18026  #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
18027  #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
18028  #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
18029 /* ==========================================================  ICR  ========================================================== */
18030  #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
18031  #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
18032  #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
18033  #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
18034  #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
18035  #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
18036  #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
18037  #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
18038  #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
18039  #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
18040  #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
18041  #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
18042 /* ==========================================================  STR  ========================================================== */
18043  #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
18044  #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
18045  #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
18046  #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
18047  #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
18048  #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
18049  #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
18050  #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
18051  #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
18052  #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
18053  #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
18054  #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
18055 /* =========================================================  STCR  ========================================================== */
18056  #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
18057  #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
18058  #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
18059  #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
18060  #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
18061  #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
18062  #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
18063  #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
18064  #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
18065  #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
18066  #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
18067  #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
18068 /* =========================================================  CF0DR  ========================================================= */
18069 /* =========================================================  CF0CR  ========================================================= */
18070  #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
18071  #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
18072  #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
18073  #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
18074  #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
18075  #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
18076  #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
18077  #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
18078  #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
18079  #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
18080  #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
18081  #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
18082  #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
18083  #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
18084  #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
18085  #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
18086 /* =========================================================  CF0RR  ========================================================= */
18087 /* ========================================================  PCF1DR  ========================================================= */
18088 /* ========================================================  SCF1DR  ========================================================= */
18089 /* =========================================================  CF1CR  ========================================================= */
18090  #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
18091  #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
18092  #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
18093  #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
18094  #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
18095  #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
18096  #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
18097  #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
18098  #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
18099  #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
18100  #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
18101  #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
18102  #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
18103  #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
18104  #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
18105  #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
18106 /* =========================================================  CF1RR  ========================================================= */
18107 /* ==========================================================  TCR  ========================================================== */
18108  #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
18109  #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
18110 /* ==========================================================  TMR  ========================================================== */
18111  #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
18112  #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
18113  #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
18114  #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
18115  #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
18116  #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
18117 /* =========================================================  TPRE  ========================================================== */
18118 /* =========================================================  TCNT  ========================================================== */
18119 
18120 /* =========================================================================================================================== */
18121 /* ================                                         R_SDADC0                                          ================ */
18122 /* =========================================================================================================================== */
18123 
18124 /* =========================================================  STC1  ========================================================== */
18125  #define R_SDADC0_STC1_VSBIAS_Pos     (8UL)          /*!< VSBIAS (Bit 8)                                        */
18126  #define R_SDADC0_STC1_VSBIAS_Msk     (0xf00UL)      /*!< VSBIAS (Bitfield-Mask: 0x0f)                          */
18127  #define R_SDADC0_STC1_CLKDIV_Pos     (0UL)          /*!< CLKDIV (Bit 0)                                        */
18128  #define R_SDADC0_STC1_CLKDIV_Msk     (0xfUL)        /*!< CLKDIV (Bitfield-Mask: 0x0f)                          */
18129  #define R_SDADC0_STC1_SDADLPM_Pos    (7UL)          /*!< SDADLPM (Bit 7)                                       */
18130  #define R_SDADC0_STC1_SDADLPM_Msk    (0x80UL)       /*!< SDADLPM (Bitfield-Mask: 0x01)                         */
18131  #define R_SDADC0_STC1_VREFSEL_Pos    (15UL)         /*!< VREFSEL (Bit 15)                                      */
18132  #define R_SDADC0_STC1_VREFSEL_Msk    (0x8000UL)     /*!< VREFSEL (Bitfield-Mask: 0x01)                         */
18133 /* =========================================================  STC2  ========================================================== */
18134  #define R_SDADC0_STC2_BGRPON_Pos     (0UL)          /*!< BGRPON (Bit 0)                                        */
18135  #define R_SDADC0_STC2_BGRPON_Msk     (0x1UL)        /*!< BGRPON (Bitfield-Mask: 0x01)                          */
18136  #define R_SDADC0_STC2_ADFPWDS_Pos    (2UL)          /*!< ADFPWDS (Bit 2)                                       */
18137  #define R_SDADC0_STC2_ADFPWDS_Msk    (0x4UL)        /*!< ADFPWDS (Bitfield-Mask: 0x01)                         */
18138  #define R_SDADC0_STC2_ADCPON_Pos     (1UL)          /*!< ADCPON (Bit 1)                                        */
18139  #define R_SDADC0_STC2_ADCPON_Msk     (0x2UL)        /*!< ADCPON (Bitfield-Mask: 0x01)                          */
18140 /* =========================================================  PGAC  ========================================================== */
18141  #define R_SDADC0_PGAC_PGAASN_Pos     (31UL)         /*!< PGAASN (Bit 31)                                       */
18142  #define R_SDADC0_PGAC_PGAASN_Msk     (0x80000000UL) /*!< PGAASN (Bitfield-Mask: 0x01)                          */
18143  #define R_SDADC0_PGAC_PGACVE_Pos     (30UL)         /*!< PGACVE (Bit 30)                                       */
18144  #define R_SDADC0_PGAC_PGACVE_Msk     (0x40000000UL) /*!< PGACVE (Bitfield-Mask: 0x01)                          */
18145  #define R_SDADC0_PGAC_PGAREV_Pos     (28UL)         /*!< PGAREV (Bit 28)                                       */
18146  #define R_SDADC0_PGAC_PGAREV_Msk     (0x10000000UL) /*!< PGAREV (Bitfield-Mask: 0x01)                          */
18147  #define R_SDADC0_PGAC_PGAAVE_Pos     (26UL)         /*!< PGAAVE (Bit 26)                                       */
18148  #define R_SDADC0_PGAC_PGAAVE_Msk     (0xc000000UL)  /*!< PGAAVE (Bitfield-Mask: 0x03)                          */
18149  #define R_SDADC0_PGAC_PGAAVN_Pos     (24UL)         /*!< PGAAVN (Bit 24)                                       */
18150  #define R_SDADC0_PGAC_PGAAVN_Msk     (0x3000000UL)  /*!< PGAAVN (Bitfield-Mask: 0x03)                          */
18151  #define R_SDADC0_PGAC_PGACTN_Pos     (21UL)         /*!< PGACTN (Bit 21)                                       */
18152  #define R_SDADC0_PGAC_PGACTN_Msk     (0xe00000UL)   /*!< PGACTN (Bitfield-Mask: 0x07)                          */
18153  #define R_SDADC0_PGAC_PGACTM_Pos     (16UL)         /*!< PGACTM (Bit 16)                                       */
18154  #define R_SDADC0_PGAC_PGACTM_Msk     (0x1f0000UL)   /*!< PGACTM (Bitfield-Mask: 0x1f)                          */
18155  #define R_SDADC0_PGAC_PGASEL_Pos     (15UL)         /*!< PGASEL (Bit 15)                                       */
18156  #define R_SDADC0_PGAC_PGASEL_Msk     (0x8000UL)     /*!< PGASEL (Bitfield-Mask: 0x01)                          */
18157  #define R_SDADC0_PGAC_PGAPOL_Pos     (14UL)         /*!< PGAPOL (Bit 14)                                       */
18158  #define R_SDADC0_PGAC_PGAPOL_Msk     (0x4000UL)     /*!< PGAPOL (Bitfield-Mask: 0x01)                          */
18159  #define R_SDADC0_PGAC_PGAOFS_Pos     (8UL)          /*!< PGAOFS (Bit 8)                                        */
18160  #define R_SDADC0_PGAC_PGAOFS_Msk     (0x1f00UL)     /*!< PGAOFS (Bitfield-Mask: 0x1f)                          */
18161  #define R_SDADC0_PGAC_PGAOSR_Pos     (5UL)          /*!< PGAOSR (Bit 5)                                        */
18162  #define R_SDADC0_PGAC_PGAOSR_Msk     (0xe0UL)       /*!< PGAOSR (Bitfield-Mask: 0x07)                          */
18163  #define R_SDADC0_PGAC_PGAGC_Pos      (0UL)          /*!< PGAGC (Bit 0)                                         */
18164  #define R_SDADC0_PGAC_PGAGC_Msk      (0x1fUL)       /*!< PGAGC (Bitfield-Mask: 0x1f)                           */
18165 /* =========================================================  ADC1  ========================================================== */
18166  #define R_SDADC0_ADC1_PGASLFT_Pos    (20UL)         /*!< PGASLFT (Bit 20)                                      */
18167  #define R_SDADC0_ADC1_PGASLFT_Msk    (0x100000UL)   /*!< PGASLFT (Bitfield-Mask: 0x01)                         */
18168  #define R_SDADC0_ADC1_PGADISC_Pos    (17UL)         /*!< PGADISC (Bit 17)                                      */
18169  #define R_SDADC0_ADC1_PGADISC_Msk    (0x20000UL)    /*!< PGADISC (Bitfield-Mask: 0x01)                         */
18170  #define R_SDADC0_ADC1_PGADISA_Pos    (16UL)         /*!< PGADISA (Bit 16)                                      */
18171  #define R_SDADC0_ADC1_PGADISA_Msk    (0x10000UL)    /*!< PGADISA (Bitfield-Mask: 0x01)                         */
18172  #define R_SDADC0_ADC1_SDADBMP_Pos    (8UL)          /*!< SDADBMP (Bit 8)                                       */
18173  #define R_SDADC0_ADC1_SDADBMP_Msk    (0x1f00UL)     /*!< SDADBMP (Bitfield-Mask: 0x1f)                         */
18174  #define R_SDADC0_ADC1_SDADTMD_Pos    (4UL)          /*!< SDADTMD (Bit 4)                                       */
18175  #define R_SDADC0_ADC1_SDADTMD_Msk    (0x10UL)       /*!< SDADTMD (Bitfield-Mask: 0x01)                         */
18176  #define R_SDADC0_ADC1_SDADSCM_Pos    (0UL)          /*!< SDADSCM (Bit 0)                                       */
18177  #define R_SDADC0_ADC1_SDADSCM_Msk    (0x1UL)        /*!< SDADSCM (Bitfield-Mask: 0x01)                         */
18178 /* =========================================================  ADC2  ========================================================== */
18179  #define R_SDADC0_ADC2_SDADST_Pos     (0UL)          /*!< SDADST (Bit 0)                                        */
18180  #define R_SDADC0_ADC2_SDADST_Msk     (0x1UL)        /*!< SDADST (Bitfield-Mask: 0x01)                          */
18181 /* =========================================================  ADCR  ========================================================== */
18182  #define R_SDADC0_ADCR_SDADCRC_Pos    (25UL)         /*!< SDADCRC (Bit 25)                                      */
18183  #define R_SDADC0_ADCR_SDADCRC_Msk    (0xe000000UL)  /*!< SDADCRC (Bitfield-Mask: 0x07)                         */
18184  #define R_SDADC0_ADCR_SDADCRS_Pos    (24UL)         /*!< SDADCRS (Bit 24)                                      */
18185  #define R_SDADC0_ADCR_SDADCRS_Msk    (0x1000000UL)  /*!< SDADCRS (Bitfield-Mask: 0x01)                         */
18186  #define R_SDADC0_ADCR_SDADCRD_Pos    (0UL)          /*!< SDADCRD (Bit 0)                                       */
18187  #define R_SDADC0_ADCR_SDADCRD_Msk    (0xffffffUL)   /*!< SDADCRD (Bitfield-Mask: 0xffffff)                     */
18188 /* =========================================================  ADAR  ========================================================== */
18189  #define R_SDADC0_ADAR_SDADMVC_Pos    (25UL)         /*!< SDADMVC (Bit 25)                                      */
18190  #define R_SDADC0_ADAR_SDADMVC_Msk    (0xe000000UL)  /*!< SDADMVC (Bitfield-Mask: 0x07)                         */
18191  #define R_SDADC0_ADAR_SDADMVS_Pos    (24UL)         /*!< SDADMVS (Bit 24)                                      */
18192  #define R_SDADC0_ADAR_SDADMVS_Msk    (0x1000000UL)  /*!< SDADMVS (Bitfield-Mask: 0x01)                         */
18193  #define R_SDADC0_ADAR_SDADMVD_Pos    (0UL)          /*!< SDADMVD (Bit 0)                                       */
18194  #define R_SDADC0_ADAR_SDADMVD_Msk    (0xffffffUL)   /*!< SDADMVD (Bitfield-Mask: 0xffffff)                     */
18195 /* =========================================================  CLBC  ========================================================== */
18196  #define R_SDADC0_CLBC_CLBMD_Pos      (0UL)          /*!< CLBMD (Bit 0)                                         */
18197  #define R_SDADC0_CLBC_CLBMD_Msk      (0x3UL)        /*!< CLBMD (Bitfield-Mask: 0x03)                           */
18198 /* ========================================================  CLBSTR  ========================================================= */
18199  #define R_SDADC0_CLBSTR_CLBST_Pos    (0UL)          /*!< CLBST (Bit 0)                                         */
18200  #define R_SDADC0_CLBSTR_CLBST_Msk    (0x1UL)        /*!< CLBST (Bitfield-Mask: 0x01)                           */
18201 /* ========================================================  CLBSSR  ========================================================= */
18202  #define R_SDADC0_CLBSSR_CLBSS_Pos    (0UL)          /*!< CLBSS (Bit 0)                                         */
18203  #define R_SDADC0_CLBSSR_CLBSS_Msk    (0x1UL)        /*!< CLBSS (Bitfield-Mask: 0x01)                           */
18204 
18205 /* =========================================================================================================================== */
18206 /* ================                                          R_SPI0                                           ================ */
18207 /* =========================================================================================================================== */
18208 
18209 /* =========================================================  SPCR  ========================================================== */
18210  #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
18211  #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
18212  #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
18213  #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
18214  #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
18215  #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
18216  #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
18217  #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
18218  #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
18219  #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
18220  #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
18221  #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
18222  #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
18223  #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
18224  #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
18225  #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
18226 /* =========================================================  SSLP  ========================================================== */
18227  #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
18228  #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
18229  #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
18230  #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
18231  #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
18232  #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
18233  #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
18234  #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
18235  #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
18236  #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
18237  #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
18238  #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
18239  #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
18240  #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
18241  #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
18242  #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
18243 /* =========================================================  SPPCR  ========================================================= */
18244  #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
18245  #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
18246  #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
18247  #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
18248  #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
18249  #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
18250  #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
18251  #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
18252 /* =========================================================  SPSR  ========================================================== */
18253  #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
18254  #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
18255  #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
18256  #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
18257  #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
18258  #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
18259  #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
18260  #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
18261  #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
18262  #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
18263  #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
18264  #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
18265  #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
18266  #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
18267  #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
18268  #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
18269 /* =========================================================  SPDR  ========================================================== */
18270 /* ========================================================  SPDR_HA  ======================================================== */
18271 /* ========================================================  SPDR_BY  ======================================================== */
18272 /* =========================================================  SPSCR  ========================================================= */
18273  #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
18274  #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
18275 /* =========================================================  SPBR  ========================================================== */
18276  #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
18277  #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
18278 /* =========================================================  SPDCR  ========================================================= */
18279  #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
18280  #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
18281  #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
18282  #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
18283  #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
18284  #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
18285  #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
18286  #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
18287  #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
18288  #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
18289 /* =========================================================  SPCKD  ========================================================= */
18290  #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
18291  #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
18292 /* =========================================================  SSLND  ========================================================= */
18293  #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
18294  #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
18295 /* =========================================================  SPND  ========================================================== */
18296  #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
18297  #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
18298 /* =========================================================  SPCR2  ========================================================= */
18299  #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
18300  #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
18301  #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
18302  #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
18303  #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
18304  #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
18305  #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
18306  #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
18307  #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
18308  #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
18309  #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
18310  #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
18311 /* =========================================================  SPCMD  ========================================================= */
18312  #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
18313  #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
18314  #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
18315  #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
18316  #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
18317  #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
18318  #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
18319  #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
18320  #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
18321  #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
18322  #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
18323  #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
18324  #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
18325  #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
18326  #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
18327  #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
18328  #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
18329  #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
18330  #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
18331  #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
18332 /* ========================================================  SPDCR2  ========================================================= */
18333  #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
18334  #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
18335  #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
18336  #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
18337 /* =========================================================  SPSSR  ========================================================= */
18338  #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
18339  #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
18340  #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
18341  #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
18342 /* =========================================================  SPCR3  ========================================================= */
18343  #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
18344  #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
18345  #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
18346  #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
18347  #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
18348  #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
18349 /* =========================================================  SPPR  ========================================================== */
18350  #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
18351  #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
18352  #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
18353  #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
18354  #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
18355  #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
18356 
18357 /* =========================================================================================================================== */
18358 /* ================                                          R_SRAM                                           ================ */
18359 /* =========================================================================================================================== */
18360 
18361 /* ========================================================  PARIOAD  ======================================================== */
18362  #define R_SRAM_PARIOAD_OAD_Pos            (0UL)    /*!< OAD (Bit 0)                                           */
18363  #define R_SRAM_PARIOAD_OAD_Msk            (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
18364 /* =======================================================  SRAMPRCR  ======================================================== */
18365  #define R_SRAM_SRAMPRCR_KW_Pos            (1UL)    /*!< KW (Bit 1)                                            */
18366  #define R_SRAM_SRAMPRCR_KW_Msk            (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
18367  #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos      (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
18368  #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk      (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
18369 /* =======================================================  SRAMWTSC  ======================================================== */
18370 /* ========================================================  ECCMODE  ======================================================== */
18371  #define R_SRAM_ECCMODE_ECCMOD_Pos         (0UL)    /*!< ECCMOD (Bit 0)                                        */
18372  #define R_SRAM_ECCMODE_ECCMOD_Msk         (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
18373 /* ========================================================  ECC2STS  ======================================================== */
18374  #define R_SRAM_ECC2STS_ECC2ERR_Pos        (0UL)    /*!< ECC2ERR (Bit 0)                                       */
18375  #define R_SRAM_ECC2STS_ECC2ERR_Msk        (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
18376 /* =======================================================  ECC1STSEN  ======================================================= */
18377  #define R_SRAM_ECC1STSEN_E1STSEN_Pos      (0UL)    /*!< E1STSEN (Bit 0)                                       */
18378  #define R_SRAM_ECC1STSEN_E1STSEN_Msk      (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
18379 /* ========================================================  ECC1STS  ======================================================== */
18380  #define R_SRAM_ECC1STS_ECC1ERR_Pos        (0UL)    /*!< ECC1ERR (Bit 0)                                       */
18381  #define R_SRAM_ECC1STS_ECC1ERR_Msk        (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
18382 /* ========================================================  ECCPRCR  ======================================================== */
18383  #define R_SRAM_ECCPRCR_KW_Pos             (1UL)    /*!< KW (Bit 1)                                            */
18384  #define R_SRAM_ECCPRCR_KW_Msk             (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
18385  #define R_SRAM_ECCPRCR_ECCPRCR_Pos        (0UL)    /*!< ECCPRCR (Bit 0)                                       */
18386  #define R_SRAM_ECCPRCR_ECCPRCR_Msk        (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
18387 /* =======================================================  ECCPRCR2  ======================================================== */
18388  #define R_SRAM_ECCPRCR2_KW2_Pos           (1UL)    /*!< KW2 (Bit 1)                                           */
18389  #define R_SRAM_ECCPRCR2_KW2_Msk           (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
18390  #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos      (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
18391  #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk      (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
18392 /* ========================================================  ECCETST  ======================================================== */
18393  #define R_SRAM_ECCETST_TSTBYP_Pos         (0UL)    /*!< TSTBYP (Bit 0)                                        */
18394  #define R_SRAM_ECCETST_TSTBYP_Msk         (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
18395 /* ========================================================  ECCOAD  ========================================================= */
18396  #define R_SRAM_ECCOAD_OAD_Pos             (0UL)    /*!< OAD (Bit 0)                                           */
18397  #define R_SRAM_ECCOAD_OAD_Msk             (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
18398 /* =======================================================  SRAMPRCR2  ======================================================= */
18399  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos    (0UL)    /*!< SRAMPRCR2 (Bit 0)                                     */
18400  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk    (0x1UL)  /*!< SRAMPRCR2 (Bitfield-Mask: 0x01)                       */
18401  #define R_SRAM_SRAMPRCR2_KW_Pos           (1UL)    /*!< KW (Bit 1)                                            */
18402  #define R_SRAM_SRAMPRCR2_KW_Msk           (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
18403 
18404 /* =========================================================================================================================== */
18405 /* ================                                         R_SYSTEM                                          ================ */
18406 /* =========================================================================================================================== */
18407 
18408 /* =========================================================  SBYCR  ========================================================= */
18409  #define R_SYSTEM_SBYCR_SSBY_Pos                   (15UL)         /*!< SSBY (Bit 15)                                         */
18410  #define R_SYSTEM_SBYCR_SSBY_Msk                   (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
18411  #define R_SYSTEM_SBYCR_OPE_Pos                    (14UL)         /*!< OPE (Bit 14)                                          */
18412  #define R_SYSTEM_SBYCR_OPE_Msk                    (0x4000UL)     /*!< OPE (Bitfield-Mask: 0x01)                             */
18413 /* ========================================================  MSTPCRA  ======================================================== */
18414  #define R_SYSTEM_MSTPCRA_MSTPA_Pos                (0UL)          /*!< MSTPA (Bit 0)                                         */
18415  #define R_SYSTEM_MSTPCRA_MSTPA_Msk                (0x1UL)        /*!< MSTPA (Bitfield-Mask: 0x01)                           */
18416 /* =======================================================  SCKDIVCR  ======================================================== */
18417  #define R_SYSTEM_SCKDIVCR_FCK_Pos                 (28UL)         /*!< FCK (Bit 28)                                          */
18418  #define R_SYSTEM_SCKDIVCR_FCK_Msk                 (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
18419  #define R_SYSTEM_SCKDIVCR_ICK_Pos                 (24UL)         /*!< ICK (Bit 24)                                          */
18420  #define R_SYSTEM_SCKDIVCR_ICK_Msk                 (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
18421  #define R_SYSTEM_SCKDIVCR_BCK_Pos                 (16UL)         /*!< BCK (Bit 16)                                          */
18422  #define R_SYSTEM_SCKDIVCR_BCK_Msk                 (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
18423  #define R_SYSTEM_SCKDIVCR_PCKA_Pos                (12UL)         /*!< PCKA (Bit 12)                                         */
18424  #define R_SYSTEM_SCKDIVCR_PCKA_Msk                (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
18425  #define R_SYSTEM_SCKDIVCR_PCKB_Pos                (8UL)          /*!< PCKB (Bit 8)                                          */
18426  #define R_SYSTEM_SCKDIVCR_PCKB_Msk                (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
18427  #define R_SYSTEM_SCKDIVCR_PCKC_Pos                (4UL)          /*!< PCKC (Bit 4)                                          */
18428  #define R_SYSTEM_SCKDIVCR_PCKC_Msk                (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
18429  #define R_SYSTEM_SCKDIVCR_PCKD_Pos                (0UL)          /*!< PCKD (Bit 0)                                          */
18430  #define R_SYSTEM_SCKDIVCR_PCKD_Msk                (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
18431 /* =======================================================  SCKDIVCR2  ======================================================= */
18432  #define R_SYSTEM_SCKDIVCR2_UCK_Pos                (4UL)          /*!< UCK (Bit 4)                                           */
18433  #define R_SYSTEM_SCKDIVCR2_UCK_Msk                (0x70UL)       /*!< UCK (Bitfield-Mask: 0x07)                             */
18434 /* ========================================================  SCKSCR  ========================================================= */
18435  #define R_SYSTEM_SCKSCR_CKSEL_Pos                 (0UL)          /*!< CKSEL (Bit 0)                                         */
18436  #define R_SYSTEM_SCKSCR_CKSEL_Msk                 (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
18437 /* ========================================================  PLLCCR  ========================================================= */
18438  #define R_SYSTEM_PLLCCR_PLLMUL_Pos                (8UL)          /*!< PLLMUL (Bit 8)                                        */
18439  #define R_SYSTEM_PLLCCR_PLLMUL_Msk                (0x3f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x3f)                          */
18440  #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos              (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
18441  #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk              (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
18442  #define R_SYSTEM_PLLCCR_PLIDIV_Pos                (0UL)          /*!< PLIDIV (Bit 0)                                        */
18443  #define R_SYSTEM_PLLCCR_PLIDIV_Msk                (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
18444 /* =========================================================  PLLCR  ========================================================= */
18445  #define R_SYSTEM_PLLCR_PLLSTP_Pos                 (0UL)          /*!< PLLSTP (Bit 0)                                        */
18446  #define R_SYSTEM_PLLCR_PLLSTP_Msk                 (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
18447 /* ========================================================  PLLCCR2  ======================================================== */
18448  #define R_SYSTEM_PLLCCR2_PLODIV_Pos               (6UL)          /*!< PLODIV (Bit 6)                                        */
18449  #define R_SYSTEM_PLLCCR2_PLODIV_Msk               (0xc0UL)       /*!< PLODIV (Bitfield-Mask: 0x03)                          */
18450  #define R_SYSTEM_PLLCCR2_PLLMUL_Pos               (0UL)          /*!< PLLMUL (Bit 0)                                        */
18451  #define R_SYSTEM_PLLCCR2_PLLMUL_Msk               (0x1fUL)       /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
18452 /* =========================================================  BCKCR  ========================================================= */
18453  #define R_SYSTEM_BCKCR_BCLKDIV_Pos                (0UL)          /*!< BCLKDIV (Bit 0)                                       */
18454  #define R_SYSTEM_BCKCR_BCLKDIV_Msk                (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
18455 /* ========================================================  MEMWAIT  ======================================================== */
18456  #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos              (0UL)          /*!< MEMWAIT (Bit 0)                                       */
18457  #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk              (0x1UL)        /*!< MEMWAIT (Bitfield-Mask: 0x01)                         */
18458 /* ========================================================  MOSCCR  ========================================================= */
18459  #define R_SYSTEM_MOSCCR_MOSTP_Pos                 (0UL)          /*!< MOSTP (Bit 0)                                         */
18460  #define R_SYSTEM_MOSCCR_MOSTP_Msk                 (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
18461 /* ========================================================  HOCOCR  ========================================================= */
18462  #define R_SYSTEM_HOCOCR_HCSTP_Pos                 (0UL)          /*!< HCSTP (Bit 0)                                         */
18463  #define R_SYSTEM_HOCOCR_HCSTP_Msk                 (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
18464 /* ========================================================  HOCOCR2  ======================================================== */
18465  #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos               (0UL)          /*!< HCFRQ0 (Bit 0)                                        */
18466  #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk               (0x3UL)        /*!< HCFRQ0 (Bitfield-Mask: 0x03)                          */
18467  #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos               (3UL)          /*!< HCFRQ1 (Bit 3)                                        */
18468  #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk               (0x38UL)       /*!< HCFRQ1 (Bitfield-Mask: 0x07)                          */
18469 /* ========================================================  MOCOCR  ========================================================= */
18470  #define R_SYSTEM_MOCOCR_MCSTP_Pos                 (0UL)          /*!< MCSTP (Bit 0)                                         */
18471  #define R_SYSTEM_MOCOCR_MCSTP_Msk                 (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
18472 /* ========================================================  FLLCR1  ========================================================= */
18473  #define R_SYSTEM_FLLCR1_FLLEN_Pos                 (0UL)          /*!< FLLEN (Bit 0)                                         */
18474  #define R_SYSTEM_FLLCR1_FLLEN_Msk                 (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
18475 /* ========================================================  FLLCR2  ========================================================= */
18476  #define R_SYSTEM_FLLCR2_FLLCNTL_Pos               (0UL)          /*!< FLLCNTL (Bit 0)                                       */
18477  #define R_SYSTEM_FLLCR2_FLLCNTL_Msk               (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
18478 /* =========================================================  OSCSF  ========================================================= */
18479  #define R_SYSTEM_OSCSF_PLLSF_Pos                  (5UL)          /*!< PLLSF (Bit 5)                                         */
18480  #define R_SYSTEM_OSCSF_PLLSF_Msk                  (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
18481  #define R_SYSTEM_OSCSF_MOSCSF_Pos                 (3UL)          /*!< MOSCSF (Bit 3)                                        */
18482  #define R_SYSTEM_OSCSF_MOSCSF_Msk                 (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
18483  #define R_SYSTEM_OSCSF_HOCOSF_Pos                 (0UL)          /*!< HOCOSF (Bit 0)                                        */
18484  #define R_SYSTEM_OSCSF_HOCOSF_Msk                 (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
18485  #define R_SYSTEM_OSCSF_PLL2SF_Pos                 (6UL)          /*!< PLL2SF (Bit 6)                                        */
18486  #define R_SYSTEM_OSCSF_PLL2SF_Msk                 (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
18487 /* =========================================================  CKOCR  ========================================================= */
18488  #define R_SYSTEM_CKOCR_CKOEN_Pos                  (7UL)          /*!< CKOEN (Bit 7)                                         */
18489  #define R_SYSTEM_CKOCR_CKOEN_Msk                  (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
18490  #define R_SYSTEM_CKOCR_CKODIV_Pos                 (4UL)          /*!< CKODIV (Bit 4)                                        */
18491  #define R_SYSTEM_CKOCR_CKODIV_Msk                 (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
18492  #define R_SYSTEM_CKOCR_CKOSEL_Pos                 (0UL)          /*!< CKOSEL (Bit 0)                                        */
18493  #define R_SYSTEM_CKOCR_CKOSEL_Msk                 (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
18494 /* ========================================================  TRCKCR  ========================================================= */
18495  #define R_SYSTEM_TRCKCR_TRCKEN_Pos                (7UL)          /*!< TRCKEN (Bit 7)                                        */
18496  #define R_SYSTEM_TRCKCR_TRCKEN_Msk                (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
18497  #define R_SYSTEM_TRCKCR_TRCK_Pos                  (0UL)          /*!< TRCK (Bit 0)                                          */
18498  #define R_SYSTEM_TRCKCR_TRCK_Msk                  (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
18499 /* ========================================================  OSTDCR  ========================================================= */
18500  #define R_SYSTEM_OSTDCR_OSTDE_Pos                 (7UL)          /*!< OSTDE (Bit 7)                                         */
18501  #define R_SYSTEM_OSTDCR_OSTDE_Msk                 (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
18502  #define R_SYSTEM_OSTDCR_OSTDIE_Pos                (0UL)          /*!< OSTDIE (Bit 0)                                        */
18503  #define R_SYSTEM_OSTDCR_OSTDIE_Msk                (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
18504 /* ========================================================  OSTDSR  ========================================================= */
18505  #define R_SYSTEM_OSTDSR_OSTDF_Pos                 (0UL)          /*!< OSTDF (Bit 0)                                         */
18506  #define R_SYSTEM_OSTDSR_OSTDF_Msk                 (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
18507 /* =========================================================  LPOPT  ========================================================= */
18508  #define R_SYSTEM_LPOPT_LPOPTEN_Pos                (7UL)          /*!< LPOPTEN (Bit 7)                                       */
18509  #define R_SYSTEM_LPOPT_LPOPTEN_Msk                (0x80UL)       /*!< LPOPTEN (Bitfield-Mask: 0x01)                         */
18510  #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos              (3UL)          /*!< BPFCLKDIS (Bit 3)                                     */
18511  #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk              (0x8UL)        /*!< BPFCLKDIS (Bitfield-Mask: 0x01)                       */
18512  #define R_SYSTEM_LPOPT_DCLKDIS_Pos                (1UL)          /*!< DCLKDIS (Bit 1)                                       */
18513  #define R_SYSTEM_LPOPT_DCLKDIS_Msk                (0x6UL)        /*!< DCLKDIS (Bitfield-Mask: 0x03)                         */
18514  #define R_SYSTEM_LPOPT_MPUDIS_Pos                 (0UL)          /*!< MPUDIS (Bit 0)                                        */
18515  #define R_SYSTEM_LPOPT_MPUDIS_Msk                 (0x1UL)        /*!< MPUDIS (Bitfield-Mask: 0x01)                          */
18516 /* =======================================================  SLCDSCKCR  ======================================================= */
18517  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos           (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
18518  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk           (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
18519  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos          (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
18520  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk          (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
18521 /* ========================================================  EBCKOCR  ======================================================== */
18522  #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos              (0UL)          /*!< EBCKOEN (Bit 0)                                       */
18523  #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk              (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
18524 /* ========================================================  SDCKOCR  ======================================================== */
18525  #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos              (0UL)          /*!< SDCKOEN (Bit 0)                                       */
18526  #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk              (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
18527 /* =======================================================  MOCOUTCR  ======================================================== */
18528  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos            (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
18529  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk            (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
18530 /* =======================================================  HOCOUTCR  ======================================================== */
18531  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos            (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
18532  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk            (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
18533 /* =========================================================  SNZCR  ========================================================= */
18534  #define R_SYSTEM_SNZCR_SNZE_Pos                   (7UL)          /*!< SNZE (Bit 7)                                          */
18535  #define R_SYSTEM_SNZCR_SNZE_Msk                   (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
18536  #define R_SYSTEM_SNZCR_SNZDTCEN_Pos               (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
18537  #define R_SYSTEM_SNZCR_SNZDTCEN_Msk               (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
18538  #define R_SYSTEM_SNZCR_RXDREQEN_Pos               (0UL)          /*!< RXDREQEN (Bit 0)                                      */
18539  #define R_SYSTEM_SNZCR_RXDREQEN_Msk               (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
18540 /* ========================================================  SNZEDCR  ======================================================== */
18541  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos            (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
18542  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk            (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
18543  #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos             (6UL)          /*!< AD1UMTED (Bit 6)                                      */
18544  #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk             (0x40UL)       /*!< AD1UMTED (Bitfield-Mask: 0x01)                        */
18545  #define R_SYSTEM_SNZEDCR_AD1MATED_Pos             (5UL)          /*!< AD1MATED (Bit 5)                                      */
18546  #define R_SYSTEM_SNZEDCR_AD1MATED_Msk             (0x20UL)       /*!< AD1MATED (Bitfield-Mask: 0x01)                        */
18547  #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos             (4UL)          /*!< AD0UMTED (Bit 4)                                      */
18548  #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk             (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
18549  #define R_SYSTEM_SNZEDCR_AD0MATED_Pos             (3UL)          /*!< AD0MATED (Bit 3)                                      */
18550  #define R_SYSTEM_SNZEDCR_AD0MATED_Msk             (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
18551  #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos             (2UL)          /*!< DTCNZRED (Bit 2)                                      */
18552  #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk             (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
18553  #define R_SYSTEM_SNZEDCR_DTCZRED_Pos              (1UL)          /*!< DTCZRED (Bit 1)                                       */
18554  #define R_SYSTEM_SNZEDCR_DTCZRED_Msk              (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
18555  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos            (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
18556  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk            (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
18557 /* =======================================================  SNZREQCR  ======================================================== */
18558  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos          (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
18559  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk          (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
18560  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos          (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
18561  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk          (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
18562  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos          (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
18563  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk          (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
18564  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos          (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
18565  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk          (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
18566  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos          (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
18567  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk          (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
18568  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos          (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
18569  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk          (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
18570  #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos          (22UL)         /*!< SNZREQEN22 (Bit 22)                                   */
18571  #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk          (0x400000UL)   /*!< SNZREQEN22 (Bitfield-Mask: 0x01)                      */
18572  #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos          (17UL)         /*!< SNZREQEN17 (Bit 17)                                   */
18573  #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk          (0x20000UL)    /*!< SNZREQEN17 (Bitfield-Mask: 0x01)                      */
18574  #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos            (0UL)          /*!< SNZREQEN (Bit 0)                                      */
18575  #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk            (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
18576 /* ========================================================  FLSTOP  ========================================================= */
18577  #define R_SYSTEM_FLSTOP_FLSTPF_Pos                (4UL)          /*!< FLSTPF (Bit 4)                                        */
18578  #define R_SYSTEM_FLSTOP_FLSTPF_Msk                (0x10UL)       /*!< FLSTPF (Bitfield-Mask: 0x01)                          */
18579  #define R_SYSTEM_FLSTOP_FLSTOP_Pos                (0UL)          /*!< FLSTOP (Bit 0)                                        */
18580  #define R_SYSTEM_FLSTOP_FLSTOP_Msk                (0x1UL)        /*!< FLSTOP (Bitfield-Mask: 0x01)                          */
18581 /* =========================================================  PSMCR  ========================================================= */
18582  #define R_SYSTEM_PSMCR_PSMC_Pos                   (0UL)          /*!< PSMC (Bit 0)                                          */
18583  #define R_SYSTEM_PSMCR_PSMC_Msk                   (0x3UL)        /*!< PSMC (Bitfield-Mask: 0x03)                            */
18584 /* =========================================================  OPCCR  ========================================================= */
18585  #define R_SYSTEM_OPCCR_OPCMTSF_Pos                (4UL)          /*!< OPCMTSF (Bit 4)                                       */
18586  #define R_SYSTEM_OPCCR_OPCMTSF_Msk                (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
18587  #define R_SYSTEM_OPCCR_OPCM_Pos                   (0UL)          /*!< OPCM (Bit 0)                                          */
18588  #define R_SYSTEM_OPCCR_OPCM_Msk                   (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
18589 /* ========================================================  SOPCCR  ========================================================= */
18590  #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos              (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
18591  #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk              (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
18592  #define R_SYSTEM_SOPCCR_SOPCM_Pos                 (0UL)          /*!< SOPCM (Bit 0)                                         */
18593  #define R_SYSTEM_SOPCCR_SOPCM_Msk                 (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
18594 /* =======================================================  MOSCWTCR  ======================================================== */
18595  #define R_SYSTEM_MOSCWTCR_MSTS_Pos                (0UL)          /*!< MSTS (Bit 0)                                          */
18596  #define R_SYSTEM_MOSCWTCR_MSTS_Msk                (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
18597 /* =======================================================  HOCOWTCR  ======================================================== */
18598  #define R_SYSTEM_HOCOWTCR_HSTS_Pos                (0UL)          /*!< HSTS (Bit 0)                                          */
18599  #define R_SYSTEM_HOCOWTCR_HSTS_Msk                (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
18600 /* ========================================================  RSTSR1  ========================================================= */
18601  #define R_SYSTEM_RSTSR1_SPERF_Pos                 (12UL)         /*!< SPERF (Bit 12)                                        */
18602  #define R_SYSTEM_RSTSR1_SPERF_Msk                 (0x1000UL)     /*!< SPERF (Bitfield-Mask: 0x01)                           */
18603  #define R_SYSTEM_RSTSR1_BUSMRF_Pos                (11UL)         /*!< BUSMRF (Bit 11)                                       */
18604  #define R_SYSTEM_RSTSR1_BUSMRF_Msk                (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
18605  #define R_SYSTEM_RSTSR1_BUSSRF_Pos                (10UL)         /*!< BUSSRF (Bit 10)                                       */
18606  #define R_SYSTEM_RSTSR1_BUSSRF_Msk                (0x400UL)      /*!< BUSSRF (Bitfield-Mask: 0x01)                          */
18607  #define R_SYSTEM_RSTSR1_REERF_Pos                 (9UL)          /*!< REERF (Bit 9)                                         */
18608  #define R_SYSTEM_RSTSR1_REERF_Msk                 (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
18609  #define R_SYSTEM_RSTSR1_RPERF_Pos                 (8UL)          /*!< RPERF (Bit 8)                                         */
18610  #define R_SYSTEM_RSTSR1_RPERF_Msk                 (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
18611  #define R_SYSTEM_RSTSR1_SWRF_Pos                  (2UL)          /*!< SWRF (Bit 2)                                          */
18612  #define R_SYSTEM_RSTSR1_SWRF_Msk                  (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
18613  #define R_SYSTEM_RSTSR1_WDTRF_Pos                 (1UL)          /*!< WDTRF (Bit 1)                                         */
18614  #define R_SYSTEM_RSTSR1_WDTRF_Msk                 (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
18615  #define R_SYSTEM_RSTSR1_IWDTRF_Pos                (0UL)          /*!< IWDTRF (Bit 0)                                        */
18616  #define R_SYSTEM_RSTSR1_IWDTRF_Msk                (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
18617  #define R_SYSTEM_RSTSR1_TZERF_Pos                 (13UL)         /*!< TZERF (Bit 13)                                        */
18618  #define R_SYSTEM_RSTSR1_TZERF_Msk                 (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
18619  #define R_SYSTEM_RSTSR1_CPERF_Pos                 (15UL)         /*!< CPERF (Bit 15)                                        */
18620  #define R_SYSTEM_RSTSR1_CPERF_Msk                 (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
18621 /* ========================================================  STCONR  ========================================================= */
18622  #define R_SYSTEM_STCONR_STCON_Pos                 (0UL)          /*!< STCON (Bit 0)                                         */
18623  #define R_SYSTEM_STCONR_STCON_Msk                 (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
18624 /* ========================================================  LVD1CR1  ======================================================== */
18625  #define R_SYSTEM_LVD1CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
18626  #define R_SYSTEM_LVD1CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
18627  #define R_SYSTEM_LVD1CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
18628  #define R_SYSTEM_LVD1CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
18629 /* ========================================================  LVD2CR1  ======================================================== */
18630  #define R_SYSTEM_LVD2CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
18631  #define R_SYSTEM_LVD2CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
18632  #define R_SYSTEM_LVD2CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
18633  #define R_SYSTEM_LVD2CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
18634 /* ======================================================  USBCKCR_ALT  ====================================================== */
18635  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos        (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
18636  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk        (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
18637 /* =======================================================  SDADCCKCR  ======================================================= */
18638  #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos         (0UL)          /*!< SDADCCKSEL (Bit 0)                                    */
18639  #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk         (0x1UL)        /*!< SDADCCKSEL (Bitfield-Mask: 0x01)                      */
18640  #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos          (7UL)          /*!< SDADCCKEN (Bit 7)                                     */
18641  #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk          (0x80UL)       /*!< SDADCCKEN (Bitfield-Mask: 0x01)                       */
18642 /* ========================================================  LVD1SR  ========================================================= */
18643  #define R_SYSTEM_LVD1SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
18644  #define R_SYSTEM_LVD1SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
18645  #define R_SYSTEM_LVD1SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
18646  #define R_SYSTEM_LVD1SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
18647 /* ========================================================  LVD2SR  ========================================================= */
18648  #define R_SYSTEM_LVD2SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
18649  #define R_SYSTEM_LVD2SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
18650  #define R_SYSTEM_LVD2SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
18651  #define R_SYSTEM_LVD2SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
18652 /* =========================================================  PRCR  ========================================================== */
18653  #define R_SYSTEM_PRCR_PRKEY_Pos                   (8UL)          /*!< PRKEY (Bit 8)                                         */
18654  #define R_SYSTEM_PRCR_PRKEY_Msk                   (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
18655  #define R_SYSTEM_PRCR_PRC3_Pos                    (3UL)          /*!< PRC3 (Bit 3)                                          */
18656  #define R_SYSTEM_PRCR_PRC3_Msk                    (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
18657  #define R_SYSTEM_PRCR_PRC1_Pos                    (1UL)          /*!< PRC1 (Bit 1)                                          */
18658  #define R_SYSTEM_PRCR_PRC1_Msk                    (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
18659  #define R_SYSTEM_PRCR_PRC0_Pos                    (0UL)          /*!< PRC0 (Bit 0)                                          */
18660  #define R_SYSTEM_PRCR_PRC0_Msk                    (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
18661  #define R_SYSTEM_PRCR_PRC4_Pos                    (4UL)          /*!< PRC4 (Bit 4)                                          */
18662  #define R_SYSTEM_PRCR_PRC4_Msk                    (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
18663 /* ========================================================  DPSIER0  ======================================================== */
18664  #define R_SYSTEM_DPSIER0_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
18665  #define R_SYSTEM_DPSIER0_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
18666 /* ========================================================  DPSIER1  ======================================================== */
18667  #define R_SYSTEM_DPSIER1_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
18668  #define R_SYSTEM_DPSIER1_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
18669 /* ========================================================  DPSIER2  ======================================================== */
18670  #define R_SYSTEM_DPSIER2_DNMIE_Pos                (4UL)          /*!< DNMIE (Bit 4)                                         */
18671  #define R_SYSTEM_DPSIER2_DNMIE_Msk                (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
18672  #define R_SYSTEM_DPSIER2_DRTCAIE_Pos              (3UL)          /*!< DRTCAIE (Bit 3)                                       */
18673  #define R_SYSTEM_DPSIER2_DRTCAIE_Msk              (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
18674  #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos             (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
18675  #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk             (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
18676  #define R_SYSTEM_DPSIER2_DLVD2IE_Pos              (1UL)          /*!< DLVD2IE (Bit 1)                                       */
18677  #define R_SYSTEM_DPSIER2_DLVD2IE_Msk              (0x2UL)        /*!< DLVD2IE (Bitfield-Mask: 0x01)                         */
18678  #define R_SYSTEM_DPSIER2_DLVD1IE_Pos              (0UL)          /*!< DLVD1IE (Bit 0)                                       */
18679  #define R_SYSTEM_DPSIER2_DLVD1IE_Msk              (0x1UL)        /*!< DLVD1IE (Bitfield-Mask: 0x01)                         */
18680 /* ========================================================  DPSIER3  ======================================================== */
18681  #define R_SYSTEM_DPSIER3_DAGT1IE_Pos              (2UL)          /*!< DAGT1IE (Bit 2)                                       */
18682  #define R_SYSTEM_DPSIER3_DAGT1IE_Msk              (0x4UL)        /*!< DAGT1IE (Bitfield-Mask: 0x01)                         */
18683  #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos             (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
18684  #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk             (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
18685  #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos             (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
18686  #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk             (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
18687  #define R_SYSTEM_DPSIER3_DAGT3IE_Pos              (3UL)          /*!< DAGT3IE (Bit 3)                                       */
18688  #define R_SYSTEM_DPSIER3_DAGT3IE_Msk              (0x8UL)        /*!< DAGT3IE (Bitfield-Mask: 0x01)                         */
18689 /* ========================================================  DPSIFR0  ======================================================== */
18690  #define R_SYSTEM_DPSIFR0_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
18691  #define R_SYSTEM_DPSIFR0_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
18692 /* ========================================================  DPSIFR1  ======================================================== */
18693  #define R_SYSTEM_DPSIFR1_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
18694  #define R_SYSTEM_DPSIFR1_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
18695 /* ========================================================  DPSIFR2  ======================================================== */
18696  #define R_SYSTEM_DPSIFR2_DNMIF_Pos                (4UL)          /*!< DNMIF (Bit 4)                                         */
18697  #define R_SYSTEM_DPSIFR2_DNMIF_Msk                (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
18698  #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos              (3UL)          /*!< DRTCAIF (Bit 3)                                       */
18699  #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk              (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
18700  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos             (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
18701  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk             (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
18702  #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos              (1UL)          /*!< DLVD2IF (Bit 1)                                       */
18703  #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk              (0x2UL)        /*!< DLVD2IF (Bitfield-Mask: 0x01)                         */
18704  #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos              (0UL)          /*!< DLVD1IF (Bit 0)                                       */
18705  #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk              (0x1UL)        /*!< DLVD1IF (Bitfield-Mask: 0x01)                         */
18706 /* ========================================================  DPSIFR3  ======================================================== */
18707  #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos              (2UL)          /*!< DAGT1IF (Bit 2)                                       */
18708  #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk              (0x4UL)        /*!< DAGT1IF (Bitfield-Mask: 0x01)                         */
18709  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos             (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
18710  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk             (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
18711  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos             (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
18712  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk             (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
18713  #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos              (3UL)          /*!< DAGT3IF (Bit 3)                                       */
18714  #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk              (0x8UL)        /*!< DAGT3IF (Bitfield-Mask: 0x01)                         */
18715 /* =======================================================  DPSIEGR0  ======================================================== */
18716  #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
18717  #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
18718 /* =======================================================  DPSIEGR1  ======================================================== */
18719  #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
18720  #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
18721 /* =======================================================  DPSIEGR2  ======================================================== */
18722  #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos              (4UL)          /*!< DNMIEG (Bit 4)                                        */
18723  #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk              (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
18724  #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos            (1UL)          /*!< DLVD2IEG (Bit 1)                                      */
18725  #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk            (0x2UL)        /*!< DLVD2IEG (Bitfield-Mask: 0x01)                        */
18726  #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos            (0UL)          /*!< DLVD1IEG (Bit 0)                                      */
18727  #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk            (0x1UL)        /*!< DLVD1IEG (Bitfield-Mask: 0x01)                        */
18728 /* ========================================================  DPSBYCR  ======================================================== */
18729  #define R_SYSTEM_DPSBYCR_DPSBY_Pos                (7UL)          /*!< DPSBY (Bit 7)                                         */
18730  #define R_SYSTEM_DPSBYCR_DPSBY_Msk                (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
18731  #define R_SYSTEM_DPSBYCR_IOKEEP_Pos               (6UL)          /*!< IOKEEP (Bit 6)                                        */
18732  #define R_SYSTEM_DPSBYCR_IOKEEP_Msk               (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
18733  #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos              (0UL)          /*!< DEEPCUT (Bit 0)                                       */
18734  #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk              (0x3UL)        /*!< DEEPCUT (Bitfield-Mask: 0x03)                         */
18735 /* ========================================================  SYOCDCR  ======================================================== */
18736  #define R_SYSTEM_SYOCDCR_DBGEN_Pos                (7UL)          /*!< DBGEN (Bit 7)                                         */
18737  #define R_SYSTEM_SYOCDCR_DBGEN_Msk                (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
18738  #define R_SYSTEM_SYOCDCR_DOCDF_Pos                (0UL)          /*!< DOCDF (Bit 0)                                         */
18739  #define R_SYSTEM_SYOCDCR_DOCDF_Msk                (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
18740 /* =========================================================  MOMCR  ========================================================= */
18741  #define R_SYSTEM_MOMCR_AUTODRVEN_Pos              (7UL)          /*!< AUTODRVEN (Bit 7)                                     */
18742  #define R_SYSTEM_MOMCR_AUTODRVEN_Msk              (0x80UL)       /*!< AUTODRVEN (Bitfield-Mask: 0x01)                       */
18743  #define R_SYSTEM_MOMCR_MOSEL_Pos                  (6UL)          /*!< MOSEL (Bit 6)                                         */
18744  #define R_SYSTEM_MOMCR_MOSEL_Msk                  (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
18745  #define R_SYSTEM_MOMCR_MODRV0_Pos                 (4UL)          /*!< MODRV0 (Bit 4)                                        */
18746  #define R_SYSTEM_MOMCR_MODRV0_Msk                 (0x30UL)       /*!< MODRV0 (Bitfield-Mask: 0x03)                          */
18747  #define R_SYSTEM_MOMCR_MODRV1_Pos                 (3UL)          /*!< MODRV1 (Bit 3)                                        */
18748  #define R_SYSTEM_MOMCR_MODRV1_Msk                 (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
18749 /* ========================================================  RSTSR0  ========================================================= */
18750  #define R_SYSTEM_RSTSR0_DPSRSTF_Pos               (7UL)          /*!< DPSRSTF (Bit 7)                                       */
18751  #define R_SYSTEM_RSTSR0_DPSRSTF_Msk               (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
18752  #define R_SYSTEM_RSTSR0_LVD2RF_Pos                (3UL)          /*!< LVD2RF (Bit 3)                                        */
18753  #define R_SYSTEM_RSTSR0_LVD2RF_Msk                (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
18754  #define R_SYSTEM_RSTSR0_LVD1RF_Pos                (2UL)          /*!< LVD1RF (Bit 2)                                        */
18755  #define R_SYSTEM_RSTSR0_LVD1RF_Msk                (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
18756  #define R_SYSTEM_RSTSR0_LVD0RF_Pos                (1UL)          /*!< LVD0RF (Bit 1)                                        */
18757  #define R_SYSTEM_RSTSR0_LVD0RF_Msk                (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
18758  #define R_SYSTEM_RSTSR0_PORF_Pos                  (0UL)          /*!< PORF (Bit 0)                                          */
18759  #define R_SYSTEM_RSTSR0_PORF_Msk                  (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
18760 /* ========================================================  RSTSR2  ========================================================= */
18761  #define R_SYSTEM_RSTSR2_CWSF_Pos                  (0UL)          /*!< CWSF (Bit 0)                                          */
18762  #define R_SYSTEM_RSTSR2_CWSF_Msk                  (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
18763 /* ========================================================  LVCMPCR  ======================================================== */
18764  #define R_SYSTEM_LVCMPCR_LVD2E_Pos                (6UL)          /*!< LVD2E (Bit 6)                                         */
18765  #define R_SYSTEM_LVCMPCR_LVD2E_Msk                (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
18766  #define R_SYSTEM_LVCMPCR_LVD1E_Pos                (5UL)          /*!< LVD1E (Bit 5)                                         */
18767  #define R_SYSTEM_LVCMPCR_LVD1E_Msk                (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
18768 /* =======================================================  LVD1CMPCR  ======================================================= */
18769  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos            (0UL)          /*!< LVD1LVL (Bit 0)                                       */
18770  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk            (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
18771  #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos              (7UL)          /*!< LVD1E (Bit 7)                                         */
18772  #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk              (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
18773 /* ========================================================  LVDLVLR  ======================================================== */
18774  #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos              (5UL)          /*!< LVD2LVL (Bit 5)                                       */
18775  #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk              (0xe0UL)       /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
18776  #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos              (0UL)          /*!< LVD1LVL (Bit 0)                                       */
18777  #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk              (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
18778 /* =======================================================  LVD2CMPCR  ======================================================= */
18779  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos            (0UL)          /*!< LVD2LVL (Bit 0)                                       */
18780  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk            (0x7UL)        /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
18781  #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos              (7UL)          /*!< LVD2E (Bit 7)                                         */
18782  #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk              (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
18783 /* ========================================================  LVD1CR0  ======================================================== */
18784  #define R_SYSTEM_LVD1CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
18785  #define R_SYSTEM_LVD1CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
18786  #define R_SYSTEM_LVD1CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
18787  #define R_SYSTEM_LVD1CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
18788  #define R_SYSTEM_LVD1CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
18789  #define R_SYSTEM_LVD1CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
18790  #define R_SYSTEM_LVD1CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
18791  #define R_SYSTEM_LVD1CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
18792  #define R_SYSTEM_LVD1CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
18793  #define R_SYSTEM_LVD1CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
18794  #define R_SYSTEM_LVD1CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
18795  #define R_SYSTEM_LVD1CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
18796 /* ========================================================  LVD2CR0  ======================================================== */
18797  #define R_SYSTEM_LVD2CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
18798  #define R_SYSTEM_LVD2CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
18799  #define R_SYSTEM_LVD2CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
18800  #define R_SYSTEM_LVD2CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
18801  #define R_SYSTEM_LVD2CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
18802  #define R_SYSTEM_LVD2CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
18803  #define R_SYSTEM_LVD2CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
18804  #define R_SYSTEM_LVD2CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
18805  #define R_SYSTEM_LVD2CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
18806  #define R_SYSTEM_LVD2CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
18807  #define R_SYSTEM_LVD2CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
18808  #define R_SYSTEM_LVD2CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
18809 /* ========================================================  VBTCR1  ========================================================= */
18810  #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos              (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
18811  #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk              (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
18812 /* ========================================================  DCDCCTL  ======================================================== */
18813  #define R_SYSTEM_DCDCCTL_PD_Pos                   (7UL)          /*!< PD (Bit 7)                                            */
18814  #define R_SYSTEM_DCDCCTL_PD_Msk                   (0x80UL)       /*!< PD (Bitfield-Mask: 0x01)                              */
18815  #define R_SYSTEM_DCDCCTL_FST_Pos                  (6UL)          /*!< FST (Bit 6)                                           */
18816  #define R_SYSTEM_DCDCCTL_FST_Msk                  (0x40UL)       /*!< FST (Bitfield-Mask: 0x01)                             */
18817  #define R_SYSTEM_DCDCCTL_LCBOOST_Pos              (5UL)          /*!< LCBOOST (Bit 5)                                       */
18818  #define R_SYSTEM_DCDCCTL_LCBOOST_Msk              (0x20UL)       /*!< LCBOOST (Bitfield-Mask: 0x01)                         */
18819  #define R_SYSTEM_DCDCCTL_STOPZA_Pos               (4UL)          /*!< STOPZA (Bit 4)                                        */
18820  #define R_SYSTEM_DCDCCTL_STOPZA_Msk               (0x10UL)       /*!< STOPZA (Bitfield-Mask: 0x01)                          */
18821  #define R_SYSTEM_DCDCCTL_OCPEN_Pos                (1UL)          /*!< OCPEN (Bit 1)                                         */
18822  #define R_SYSTEM_DCDCCTL_OCPEN_Msk                (0x2UL)        /*!< OCPEN (Bitfield-Mask: 0x01)                           */
18823  #define R_SYSTEM_DCDCCTL_DCDCON_Pos               (0UL)          /*!< DCDCON (Bit 0)                                        */
18824  #define R_SYSTEM_DCDCCTL_DCDCON_Msk               (0x1UL)        /*!< DCDCON (Bitfield-Mask: 0x01)                          */
18825 /* ========================================================  VCCSEL  ========================================================= */
18826  #define R_SYSTEM_VCCSEL_VCCSEL_Pos                (0UL)          /*!< VCCSEL (Bit 0)                                        */
18827  #define R_SYSTEM_VCCSEL_VCCSEL_Msk                (0x3UL)        /*!< VCCSEL (Bitfield-Mask: 0x03)                          */
18828 /* ========================================================  LDOSCR  ========================================================= */
18829  #define R_SYSTEM_LDOSCR_LDOSTP0_Pos               (0UL)          /*!< LDOSTP0 (Bit 0)                                       */
18830  #define R_SYSTEM_LDOSCR_LDOSTP0_Msk               (0x1UL)        /*!< LDOSTP0 (Bitfield-Mask: 0x01)                         */
18831  #define R_SYSTEM_LDOSCR_LDOSTP1_Pos               (1UL)          /*!< LDOSTP1 (Bit 1)                                       */
18832  #define R_SYSTEM_LDOSCR_LDOSTP1_Msk               (0x2UL)        /*!< LDOSTP1 (Bitfield-Mask: 0x01)                         */
18833 /* =======================================================  PL2LDOSCR  ======================================================= */
18834  #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos          (0UL)          /*!< PL2LDOSTP (Bit 0)                                     */
18835  #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk          (0x1UL)        /*!< PL2LDOSTP (Bitfield-Mask: 0x01)                       */
18836 /* ========================================================  SOSCCR  ========================================================= */
18837  #define R_SYSTEM_SOSCCR_SOSTP_Pos                 (0UL)          /*!< SOSTP (Bit 0)                                         */
18838  #define R_SYSTEM_SOSCCR_SOSTP_Msk                 (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
18839 /* =========================================================  SOMCR  ========================================================= */
18840  #define R_SYSTEM_SOMCR_SODRV_Pos                  (0UL)          /*!< SODRV (Bit 0)                                         */
18841  #define R_SYSTEM_SOMCR_SODRV_Msk                  (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
18842 /* =========================================================  SOMRG  ========================================================= */
18843  #define R_SYSTEM_SOMRG_SOSCMRG_Pos                (0UL)          /*!< SOSCMRG (Bit 0)                                       */
18844  #define R_SYSTEM_SOMRG_SOSCMRG_Msk                (0x3UL)        /*!< SOSCMRG (Bitfield-Mask: 0x03)                         */
18845 /* ========================================================  LOCOCR  ========================================================= */
18846  #define R_SYSTEM_LOCOCR_LCSTP_Pos                 (0UL)          /*!< LCSTP (Bit 0)                                         */
18847  #define R_SYSTEM_LOCOCR_LCSTP_Msk                 (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
18848 /* =======================================================  LOCOUTCR  ======================================================== */
18849  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos            (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
18850  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk            (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
18851 /* ========================================================  VBTCR2  ========================================================= */
18852  #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos             (6UL)          /*!< VBTLVDLVL (Bit 6)                                     */
18853  #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk             (0xc0UL)       /*!< VBTLVDLVL (Bitfield-Mask: 0x03)                       */
18854  #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos              (4UL)          /*!< VBTLVDEN (Bit 4)                                      */
18855  #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk              (0x10UL)       /*!< VBTLVDEN (Bitfield-Mask: 0x01)                        */
18856 /* =========================================================  VBTSR  ========================================================= */
18857  #define R_SYSTEM_VBTSR_VBTRVLD_Pos                (4UL)          /*!< VBTRVLD (Bit 4)                                       */
18858  #define R_SYSTEM_VBTSR_VBTRVLD_Msk                (0x10UL)       /*!< VBTRVLD (Bitfield-Mask: 0x01)                         */
18859  #define R_SYSTEM_VBTSR_VBTBLDF_Pos                (1UL)          /*!< VBTBLDF (Bit 1)                                       */
18860  #define R_SYSTEM_VBTSR_VBTBLDF_Msk                (0x2UL)        /*!< VBTBLDF (Bitfield-Mask: 0x01)                         */
18861  #define R_SYSTEM_VBTSR_VBTRDF_Pos                 (0UL)          /*!< VBTRDF (Bit 0)                                        */
18862  #define R_SYSTEM_VBTSR_VBTRDF_Msk                 (0x1UL)        /*!< VBTRDF (Bitfield-Mask: 0x01)                          */
18863 /* =======================================================  VBTCMPCR  ======================================================== */
18864  #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos             (0UL)          /*!< VBTCMPE (Bit 0)                                       */
18865  #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk             (0x1UL)        /*!< VBTCMPE (Bitfield-Mask: 0x01)                         */
18866 /* =======================================================  VBTLVDICR  ======================================================= */
18867  #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos         (1UL)          /*!< VBTLVDISEL (Bit 1)                                    */
18868  #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk         (0x2UL)        /*!< VBTLVDISEL (Bitfield-Mask: 0x01)                      */
18869  #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos           (0UL)          /*!< VBTLVDIE (Bit 0)                                      */
18870  #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk           (0x1UL)        /*!< VBTLVDIE (Bitfield-Mask: 0x01)                        */
18871 /* =======================================================  VBTWCTLR  ======================================================== */
18872  #define R_SYSTEM_VBTWCTLR_VWEN_Pos                (0UL)          /*!< VWEN (Bit 0)                                          */
18873  #define R_SYSTEM_VBTWCTLR_VWEN_Msk                (0x1UL)        /*!< VWEN (Bitfield-Mask: 0x01)                            */
18874 /* ======================================================  VBTWCH0OTSR  ====================================================== */
18875  #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos       (5UL)          /*!< CH0VAGTUTE (Bit 5)                                    */
18876  #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk       (0x20UL)       /*!< CH0VAGTUTE (Bitfield-Mask: 0x01)                      */
18877  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos       (4UL)          /*!< CH0VRTCATE (Bit 4)                                    */
18878  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk       (0x10UL)       /*!< CH0VRTCATE (Bitfield-Mask: 0x01)                      */
18879  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos        (3UL)          /*!< CH0VRTCTE (Bit 3)                                     */
18880  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk        (0x8UL)        /*!< CH0VRTCTE (Bitfield-Mask: 0x01)                       */
18881  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos        (2UL)          /*!< CH0VCH2TE (Bit 2)                                     */
18882  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk        (0x4UL)        /*!< CH0VCH2TE (Bitfield-Mask: 0x01)                       */
18883  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos        (1UL)          /*!< CH0VCH1TE (Bit 1)                                     */
18884  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk        (0x2UL)        /*!< CH0VCH1TE (Bitfield-Mask: 0x01)                       */
18885 /* ======================================================  VBTWCH1OTSR  ====================================================== */
18886  #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos       (5UL)          /*!< CH1VAGTUTE (Bit 5)                                    */
18887  #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk       (0x20UL)       /*!< CH1VAGTUTE (Bitfield-Mask: 0x01)                      */
18888  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos       (4UL)          /*!< CH1VRTCATE (Bit 4)                                    */
18889  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk       (0x10UL)       /*!< CH1VRTCATE (Bitfield-Mask: 0x01)                      */
18890  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos        (3UL)          /*!< CH1VRTCTE (Bit 3)                                     */
18891  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk        (0x8UL)        /*!< CH1VRTCTE (Bitfield-Mask: 0x01)                       */
18892  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos        (2UL)          /*!< CH1VCH2TE (Bit 2)                                     */
18893  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk        (0x4UL)        /*!< CH1VCH2TE (Bitfield-Mask: 0x01)                       */
18894  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos        (0UL)          /*!< CH1VCH0TE (Bit 0)                                     */
18895  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk        (0x1UL)        /*!< CH1VCH0TE (Bitfield-Mask: 0x01)                       */
18896 /* ======================================================  VBTWCH2OTSR  ====================================================== */
18897  #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos       (5UL)          /*!< CH2VAGTUTE (Bit 5)                                    */
18898  #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk       (0x20UL)       /*!< CH2VAGTUTE (Bitfield-Mask: 0x01)                      */
18899  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos       (4UL)          /*!< CH2VRTCATE (Bit 4)                                    */
18900  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk       (0x10UL)       /*!< CH2VRTCATE (Bitfield-Mask: 0x01)                      */
18901  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos        (3UL)          /*!< CH2VRTCTE (Bit 3)                                     */
18902  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk        (0x8UL)        /*!< CH2VRTCTE (Bitfield-Mask: 0x01)                       */
18903  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos        (1UL)          /*!< CH2VCH1TE (Bit 1)                                     */
18904  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk        (0x2UL)        /*!< CH2VCH1TE (Bitfield-Mask: 0x01)                       */
18905  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos        (0UL)          /*!< CH2VCH0TE (Bit 0)                                     */
18906  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk        (0x1UL)        /*!< CH2VCH0TE (Bitfield-Mask: 0x01)                       */
18907 /* =======================================================  VBTICTLR  ======================================================== */
18908  #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos            (2UL)          /*!< VCH2INEN (Bit 2)                                      */
18909  #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk            (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
18910  #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos            (1UL)          /*!< VCH1INEN (Bit 1)                                      */
18911  #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk            (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
18912  #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos            (0UL)          /*!< VCH0INEN (Bit 0)                                      */
18913  #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk            (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
18914 /* =======================================================  VBTOCTLR  ======================================================== */
18915  #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos           (5UL)          /*!< VOUT2LSEL (Bit 5)                                     */
18916  #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk           (0x20UL)       /*!< VOUT2LSEL (Bitfield-Mask: 0x01)                       */
18917  #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos           (4UL)          /*!< VCOU1LSEL (Bit 4)                                     */
18918  #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk           (0x10UL)       /*!< VCOU1LSEL (Bitfield-Mask: 0x01)                       */
18919  #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos           (3UL)          /*!< VOUT0LSEL (Bit 3)                                     */
18920  #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk           (0x8UL)        /*!< VOUT0LSEL (Bitfield-Mask: 0x01)                       */
18921  #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos             (2UL)          /*!< VCH2OEN (Bit 2)                                       */
18922  #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk             (0x4UL)        /*!< VCH2OEN (Bitfield-Mask: 0x01)                         */
18923  #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos             (1UL)          /*!< VCH1OEN (Bit 1)                                       */
18924  #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk             (0x2UL)        /*!< VCH1OEN (Bitfield-Mask: 0x01)                         */
18925  #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos             (0UL)          /*!< VCH0OEN (Bit 0)                                       */
18926  #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk             (0x1UL)        /*!< VCH0OEN (Bitfield-Mask: 0x01)                         */
18927 /* ========================================================  VBTWTER  ======================================================== */
18928  #define R_SYSTEM_VBTWTER_VAGTUE_Pos               (5UL)          /*!< VAGTUE (Bit 5)                                        */
18929  #define R_SYSTEM_VBTWTER_VAGTUE_Msk               (0x20UL)       /*!< VAGTUE (Bitfield-Mask: 0x01)                          */
18930  #define R_SYSTEM_VBTWTER_VRTCAE_Pos               (4UL)          /*!< VRTCAE (Bit 4)                                        */
18931  #define R_SYSTEM_VBTWTER_VRTCAE_Msk               (0x10UL)       /*!< VRTCAE (Bitfield-Mask: 0x01)                          */
18932  #define R_SYSTEM_VBTWTER_VRTCIE_Pos               (3UL)          /*!< VRTCIE (Bit 3)                                        */
18933  #define R_SYSTEM_VBTWTER_VRTCIE_Msk               (0x8UL)        /*!< VRTCIE (Bitfield-Mask: 0x01)                          */
18934  #define R_SYSTEM_VBTWTER_VCH2E_Pos                (2UL)          /*!< VCH2E (Bit 2)                                         */
18935  #define R_SYSTEM_VBTWTER_VCH2E_Msk                (0x4UL)        /*!< VCH2E (Bitfield-Mask: 0x01)                           */
18936  #define R_SYSTEM_VBTWTER_VCH1E_Pos                (1UL)          /*!< VCH1E (Bit 1)                                         */
18937  #define R_SYSTEM_VBTWTER_VCH1E_Msk                (0x2UL)        /*!< VCH1E (Bitfield-Mask: 0x01)                           */
18938  #define R_SYSTEM_VBTWTER_VCH0E_Pos                (0UL)          /*!< VCH0E (Bit 0)                                         */
18939  #define R_SYSTEM_VBTWTER_VCH0E_Msk                (0x1UL)        /*!< VCH0E (Bitfield-Mask: 0x01)                           */
18940 /* ========================================================  VBTWEGR  ======================================================== */
18941  #define R_SYSTEM_VBTWEGR_VCH2EG_Pos               (2UL)          /*!< VCH2EG (Bit 2)                                        */
18942  #define R_SYSTEM_VBTWEGR_VCH2EG_Msk               (0x4UL)        /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
18943  #define R_SYSTEM_VBTWEGR_VCH1EG_Pos               (1UL)          /*!< VCH1EG (Bit 1)                                        */
18944  #define R_SYSTEM_VBTWEGR_VCH1EG_Msk               (0x2UL)        /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
18945  #define R_SYSTEM_VBTWEGR_VCH0EG_Pos               (0UL)          /*!< VCH0EG (Bit 0)                                        */
18946  #define R_SYSTEM_VBTWEGR_VCH0EG_Msk               (0x1UL)        /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
18947 /* ========================================================  VBTWFR  ========================================================= */
18948  #define R_SYSTEM_VBTWFR_VAGTUF_Pos                (5UL)          /*!< VAGTUF (Bit 5)                                        */
18949  #define R_SYSTEM_VBTWFR_VAGTUF_Msk                (0x20UL)       /*!< VAGTUF (Bitfield-Mask: 0x01)                          */
18950  #define R_SYSTEM_VBTWFR_VRTCAF_Pos                (4UL)          /*!< VRTCAF (Bit 4)                                        */
18951  #define R_SYSTEM_VBTWFR_VRTCAF_Msk                (0x10UL)       /*!< VRTCAF (Bitfield-Mask: 0x01)                          */
18952  #define R_SYSTEM_VBTWFR_VRTCIF_Pos                (3UL)          /*!< VRTCIF (Bit 3)                                        */
18953  #define R_SYSTEM_VBTWFR_VRTCIF_Msk                (0x8UL)        /*!< VRTCIF (Bitfield-Mask: 0x01)                          */
18954  #define R_SYSTEM_VBTWFR_VCH2F_Pos                 (2UL)          /*!< VCH2F (Bit 2)                                         */
18955  #define R_SYSTEM_VBTWFR_VCH2F_Msk                 (0x4UL)        /*!< VCH2F (Bitfield-Mask: 0x01)                           */
18956  #define R_SYSTEM_VBTWFR_VCH1F_Pos                 (1UL)          /*!< VCH1F (Bit 1)                                         */
18957  #define R_SYSTEM_VBTWFR_VCH1F_Msk                 (0x2UL)        /*!< VCH1F (Bitfield-Mask: 0x01)                           */
18958  #define R_SYSTEM_VBTWFR_VCH0F_Pos                 (0UL)          /*!< VCH0F (Bit 0)                                         */
18959  #define R_SYSTEM_VBTWFR_VCH0F_Msk                 (0x1UL)        /*!< VCH0F (Bitfield-Mask: 0x01)                           */
18960 /* ========================================================  VBTBKR  ========================================================= */
18961  #define R_SYSTEM_VBTBKR_VBTBKR_Pos                (0UL)          /*!< VBTBKR (Bit 0)                                        */
18962  #define R_SYSTEM_VBTBKR_VBTBKR_Msk                (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
18963 /* ========================================================  FWEPROR  ======================================================== */
18964  #define R_SYSTEM_FWEPROR_FLWE_Pos                 (0UL)          /*!< FLWE (Bit 0)                                          */
18965  #define R_SYSTEM_FWEPROR_FLWE_Msk                 (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
18966 /* ========================================================  PLL2CCR  ======================================================== */
18967  #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos              (0UL)          /*!< PL2IDIV (Bit 0)                                       */
18968  #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk              (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
18969  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos            (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
18970  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk            (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
18971  #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos              (8UL)          /*!< PLL2MUL (Bit 8)                                       */
18972  #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk              (0x3f00UL)     /*!< PLL2MUL (Bitfield-Mask: 0x3f)                         */
18973 /* ========================================================  PLL2CR  ========================================================= */
18974  #define R_SYSTEM_PLL2CR_PLL2STP_Pos               (0UL)          /*!< PLL2STP (Bit 0)                                       */
18975  #define R_SYSTEM_PLL2CR_PLL2STP_Msk               (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
18976 /* ======================================================  USBCKDIVCR  ======================================================= */
18977  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos          (0UL)          /*!< USBCKDIV (Bit 0)                                      */
18978  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk          (0x7UL)        /*!< USBCKDIV (Bitfield-Mask: 0x07)                        */
18979 /* ======================================================  OCTACKDIVCR  ====================================================== */
18980  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos        (0UL)          /*!< OCTACKDIV (Bit 0)                                     */
18981  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk        (0x7UL)        /*!< OCTACKDIV (Bitfield-Mask: 0x07)                       */
18982 /* =====================================================  SCISPICKDIVCR  ===================================================== */
18983  #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos    (0UL)          /*!< SCISPICKDIV (Bit 0)                                   */
18984  #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk    (0x7UL)        /*!< SCISPICKDIV (Bitfield-Mask: 0x07)                     */
18985 /* =====================================================  CANFDCKDIVCR  ====================================================== */
18986  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos      (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
18987  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk      (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
18988 /* ======================================================  GPTCKDIVCR  ======================================================= */
18989  #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos          (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
18990  #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk          (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
18991 /* =====================================================  USB60CKDIVCR  ====================================================== */
18992  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos      (0UL)          /*!< USB60CKDIV (Bit 0)                                    */
18993  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk      (0x7UL)        /*!< USB60CKDIV (Bitfield-Mask: 0x07)                      */
18994 /* ======================================================  CECCKDIVCR  ======================================================= */
18995  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
18996  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
18997 /* ======================================================  I3CCKDIVCR  ======================================================= */
18998  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
18999  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
19000 /* ======================================================  IICCKDIVCR  ======================================================= */
19001  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
19002  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
19003 /* ========================================================  USBCKCR  ======================================================== */
19004  #define R_SYSTEM_USBCKCR_USBCKSEL_Pos             (0UL)          /*!< USBCKSEL (Bit 0)                                      */
19005  #define R_SYSTEM_USBCKCR_USBCKSEL_Msk             (0x7UL)        /*!< USBCKSEL (Bitfield-Mask: 0x07)                        */
19006  #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos            (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
19007  #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk            (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
19008  #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos            (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
19009  #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk            (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
19010 /* =======================================================  OCTACKCR  ======================================================== */
19011  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos           (0UL)          /*!< OCTACKSEL (Bit 0)                                     */
19012  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk           (0x7UL)        /*!< OCTACKSEL (Bitfield-Mask: 0x07)                       */
19013  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos          (6UL)          /*!< OCTACKSREQ (Bit 6)                                    */
19014  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk          (0x40UL)       /*!< OCTACKSREQ (Bitfield-Mask: 0x01)                      */
19015  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos          (7UL)          /*!< OCTACKSRDY (Bit 7)                                    */
19016  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk          (0x80UL)       /*!< OCTACKSRDY (Bitfield-Mask: 0x01)                      */
19017 /* ======================================================  SCISPICKCR  ======================================================= */
19018  #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos       (0UL)          /*!< SCISPICKSEL (Bit 0)                                   */
19019  #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk       (0x7UL)        /*!< SCISPICKSEL (Bitfield-Mask: 0x07)                     */
19020  #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos      (6UL)          /*!< SCISPICKSREQ (Bit 6)                                  */
19021  #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk      (0x40UL)       /*!< SCISPICKSREQ (Bitfield-Mask: 0x01)                    */
19022  #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos      (7UL)          /*!< SCISPICKSRDY (Bit 7)                                  */
19023  #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk      (0x80UL)       /*!< SCISPICKSRDY (Bitfield-Mask: 0x01)                    */
19024 /* =======================================================  CANFDCKCR  ======================================================= */
19025  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos         (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
19026  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk         (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
19027  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos        (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
19028  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk        (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
19029  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos        (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
19030  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk        (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
19031 /* ========================================================  GPTCKCR  ======================================================== */
19032  #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos             (0UL)          /*!< GPTCKSEL (Bit 0)                                      */
19033  #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk             (0x7UL)        /*!< GPTCKSEL (Bitfield-Mask: 0x07)                        */
19034  #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos            (6UL)          /*!< GPTCKSREQ (Bit 6)                                     */
19035  #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk            (0x40UL)       /*!< GPTCKSREQ (Bitfield-Mask: 0x01)                       */
19036  #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos            (7UL)          /*!< GPTCKSRDY (Bit 7)                                     */
19037  #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk            (0x80UL)       /*!< GPTCKSRDY (Bitfield-Mask: 0x01)                       */
19038 /* =======================================================  USB60CKCR  ======================================================= */
19039  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos         (0UL)          /*!< USB60CKSEL (Bit 0)                                    */
19040  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk         (0xfUL)        /*!< USB60CKSEL (Bitfield-Mask: 0x0f)                      */
19041  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos        (6UL)          /*!< USB60CKSREQ (Bit 6)                                   */
19042  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk        (0x40UL)       /*!< USB60CKSREQ (Bitfield-Mask: 0x01)                     */
19043  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos        (7UL)          /*!< USB60CKSRDY (Bit 7)                                   */
19044  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk        (0x80UL)       /*!< USB60CKSRDY (Bitfield-Mask: 0x01)                     */
19045 /* ========================================================  CECCKCR  ======================================================== */
19046  #define R_SYSTEM_CECCKCR_CECCKSEL_Pos             (0UL)          /*!< CECCKSEL (Bit 0)                                      */
19047  #define R_SYSTEM_CECCKCR_CECCKSEL_Msk             (0x7UL)        /*!< CECCKSEL (Bitfield-Mask: 0x07)                        */
19048  #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos            (6UL)          /*!< CECCKSREQ (Bit 6)                                     */
19049  #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk            (0x40UL)       /*!< CECCKSREQ (Bitfield-Mask: 0x01)                       */
19050  #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos            (7UL)          /*!< CECCKSRDY (Bit 7)                                     */
19051  #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk            (0x80UL)       /*!< CECCKSRDY (Bitfield-Mask: 0x01)                       */
19052 /* ========================================================  IICCKCR  ======================================================== */
19053  #define R_SYSTEM_IICCKCR_IICCKSEL_Pos             (0UL)          /*!< IICCKSEL (Bit 0)                                      */
19054  #define R_SYSTEM_IICCKCR_IICCKSEL_Msk             (0x7UL)        /*!< IICCKSEL (Bitfield-Mask: 0x07)                        */
19055  #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos            (6UL)          /*!< IICCKSREQ (Bit 6)                                     */
19056  #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk            (0x40UL)       /*!< IICCKSREQ (Bitfield-Mask: 0x01)                       */
19057  #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos            (7UL)          /*!< IICCKSRDY (Bit 7)                                     */
19058  #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk            (0x80UL)       /*!< IICCKSRDY (Bitfield-Mask: 0x01)                       */
19059 /* ========================================================  I3CCKCR  ======================================================== */
19060  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos             (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
19061  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk             (0x7UL)        /*!< I3CCKSEL (Bitfield-Mask: 0x07)                        */
19062  #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos            (6UL)          /*!< I3CCKSREQ (Bit 6)                                     */
19063  #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk            (0x40UL)       /*!< I3CCKSREQ (Bitfield-Mask: 0x01)                       */
19064  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos            (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
19065  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk            (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
19066 /* =======================================================  SNZREQCR1  ======================================================= */
19067  #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos          (0UL)          /*!< SNZREQEN0 (Bit 0)                                     */
19068  #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk          (0x1UL)        /*!< SNZREQEN0 (Bitfield-Mask: 0x01)                       */
19069  #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos          (1UL)          /*!< SNZREQEN1 (Bit 1)                                     */
19070  #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk          (0x2UL)        /*!< SNZREQEN1 (Bitfield-Mask: 0x01)                       */
19071  #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos          (2UL)          /*!< SNZREQEN2 (Bit 2)                                     */
19072  #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk          (0x4UL)        /*!< SNZREQEN2 (Bitfield-Mask: 0x01)                       */
19073 /* =======================================================  SNZEDCR1  ======================================================== */
19074  #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos           (0UL)          /*!< AGT3UNFED (Bit 0)                                     */
19075  #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk           (0x1UL)        /*!< AGT3UNFED (Bitfield-Mask: 0x01)                       */
19076 /* ========================================================  CGFSAR  ========================================================= */
19077  #define R_SYSTEM_CGFSAR_NONSEC00_Pos              (0UL)          /*!< NONSEC00 (Bit 0)                                      */
19078  #define R_SYSTEM_CGFSAR_NONSEC00_Msk              (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
19079  #define R_SYSTEM_CGFSAR_NONSEC02_Pos              (2UL)          /*!< NONSEC02 (Bit 2)                                      */
19080  #define R_SYSTEM_CGFSAR_NONSEC02_Msk              (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
19081  #define R_SYSTEM_CGFSAR_NONSEC03_Pos              (3UL)          /*!< NONSEC03 (Bit 3)                                      */
19082  #define R_SYSTEM_CGFSAR_NONSEC03_Msk              (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
19083  #define R_SYSTEM_CGFSAR_NONSEC04_Pos              (4UL)          /*!< NONSEC04 (Bit 4)                                      */
19084  #define R_SYSTEM_CGFSAR_NONSEC04_Msk              (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
19085  #define R_SYSTEM_CGFSAR_NONSEC05_Pos              (5UL)          /*!< NONSEC05 (Bit 5)                                      */
19086  #define R_SYSTEM_CGFSAR_NONSEC05_Msk              (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
19087  #define R_SYSTEM_CGFSAR_NONSEC06_Pos              (6UL)          /*!< NONSEC06 (Bit 6)                                      */
19088  #define R_SYSTEM_CGFSAR_NONSEC06_Msk              (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
19089  #define R_SYSTEM_CGFSAR_NONSEC07_Pos              (7UL)          /*!< NONSEC07 (Bit 7)                                      */
19090  #define R_SYSTEM_CGFSAR_NONSEC07_Msk              (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
19091  #define R_SYSTEM_CGFSAR_NONSEC08_Pos              (8UL)          /*!< NONSEC08 (Bit 8)                                      */
19092  #define R_SYSTEM_CGFSAR_NONSEC08_Msk              (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
19093  #define R_SYSTEM_CGFSAR_NONSEC09_Pos              (9UL)          /*!< NONSEC09 (Bit 9)                                      */
19094  #define R_SYSTEM_CGFSAR_NONSEC09_Msk              (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
19095  #define R_SYSTEM_CGFSAR_NONSEC11_Pos              (11UL)         /*!< NONSEC11 (Bit 11)                                     */
19096  #define R_SYSTEM_CGFSAR_NONSEC11_Msk              (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
19097  #define R_SYSTEM_CGFSAR_NONSEC12_Pos              (12UL)         /*!< NONSEC12 (Bit 12)                                     */
19098  #define R_SYSTEM_CGFSAR_NONSEC12_Msk              (0x1000UL)     /*!< NONSEC12 (Bitfield-Mask: 0x01)                        */
19099  #define R_SYSTEM_CGFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
19100  #define R_SYSTEM_CGFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
19101  #define R_SYSTEM_CGFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
19102  #define R_SYSTEM_CGFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
19103 /* ========================================================  LPMSAR  ========================================================= */
19104  #define R_SYSTEM_LPMSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
19105  #define R_SYSTEM_LPMSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
19106  #define R_SYSTEM_LPMSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
19107  #define R_SYSTEM_LPMSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
19108  #define R_SYSTEM_LPMSAR_NONSEC4_Pos               (4UL)          /*!< NONSEC4 (Bit 4)                                       */
19109  #define R_SYSTEM_LPMSAR_NONSEC4_Msk               (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
19110  #define R_SYSTEM_LPMSAR_NONSEC8_Pos               (8UL)          /*!< NONSEC8 (Bit 8)                                       */
19111  #define R_SYSTEM_LPMSAR_NONSEC8_Msk               (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
19112  #define R_SYSTEM_LPMSAR_NONSEC9_Pos               (9UL)          /*!< NONSEC9 (Bit 9)                                       */
19113  #define R_SYSTEM_LPMSAR_NONSEC9_Msk               (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
19114 /* ========================================================  LVDSAR  ========================================================= */
19115  #define R_SYSTEM_LVDSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
19116  #define R_SYSTEM_LVDSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
19117  #define R_SYSTEM_LVDSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
19118  #define R_SYSTEM_LVDSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
19119 /* ========================================================  RSTSAR  ========================================================= */
19120  #define R_SYSTEM_RSTSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
19121  #define R_SYSTEM_RSTSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
19122  #define R_SYSTEM_RSTSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
19123  #define R_SYSTEM_RSTSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
19124  #define R_SYSTEM_RSTSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
19125  #define R_SYSTEM_RSTSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
19126 /* ========================================================  BBFSAR  ========================================================= */
19127  #define R_SYSTEM_BBFSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
19128  #define R_SYSTEM_BBFSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
19129  #define R_SYSTEM_BBFSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
19130  #define R_SYSTEM_BBFSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
19131  #define R_SYSTEM_BBFSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
19132  #define R_SYSTEM_BBFSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
19133  #define R_SYSTEM_BBFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
19134  #define R_SYSTEM_BBFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
19135  #define R_SYSTEM_BBFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
19136  #define R_SYSTEM_BBFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
19137  #define R_SYSTEM_BBFSAR_NONSEC18_Pos              (18UL)         /*!< NONSEC18 (Bit 18)                                     */
19138  #define R_SYSTEM_BBFSAR_NONSEC18_Msk              (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
19139  #define R_SYSTEM_BBFSAR_NONSEC19_Pos              (19UL)         /*!< NONSEC19 (Bit 19)                                     */
19140  #define R_SYSTEM_BBFSAR_NONSEC19_Msk              (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
19141  #define R_SYSTEM_BBFSAR_NONSEC20_Pos              (20UL)         /*!< NONSEC20 (Bit 20)                                     */
19142  #define R_SYSTEM_BBFSAR_NONSEC20_Msk              (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
19143  #define R_SYSTEM_BBFSAR_NONSEC21_Pos              (21UL)         /*!< NONSEC21 (Bit 21)                                     */
19144  #define R_SYSTEM_BBFSAR_NONSEC21_Msk              (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
19145  #define R_SYSTEM_BBFSAR_NONSEC22_Pos              (22UL)         /*!< NONSEC22 (Bit 22)                                     */
19146  #define R_SYSTEM_BBFSAR_NONSEC22_Msk              (0x400000UL)   /*!< NONSEC22 (Bitfield-Mask: 0x01)                        */
19147  #define R_SYSTEM_BBFSAR_NONSEC23_Pos              (23UL)         /*!< NONSEC23 (Bit 23)                                     */
19148  #define R_SYSTEM_BBFSAR_NONSEC23_Msk              (0x800000UL)   /*!< NONSEC23 (Bitfield-Mask: 0x01)                        */
19149 /* ========================================================  DPFSAR  ========================================================= */
19150  #define R_SYSTEM_DPFSAR_DPFSA0_Pos                (0UL)          /*!< DPFSA0 (Bit 0)                                        */
19151  #define R_SYSTEM_DPFSAR_DPFSA0_Msk                (0x1UL)        /*!< DPFSA0 (Bitfield-Mask: 0x01)                          */
19152  #define R_SYSTEM_DPFSAR_DPFSA1_Pos                (1UL)          /*!< DPFSA1 (Bit 1)                                        */
19153  #define R_SYSTEM_DPFSAR_DPFSA1_Msk                (0x2UL)        /*!< DPFSA1 (Bitfield-Mask: 0x01)                          */
19154  #define R_SYSTEM_DPFSAR_DPFSA2_Pos                (2UL)          /*!< DPFSA2 (Bit 2)                                        */
19155  #define R_SYSTEM_DPFSAR_DPFSA2_Msk                (0x4UL)        /*!< DPFSA2 (Bitfield-Mask: 0x01)                          */
19156  #define R_SYSTEM_DPFSAR_DPFSA3_Pos                (3UL)          /*!< DPFSA3 (Bit 3)                                        */
19157  #define R_SYSTEM_DPFSAR_DPFSA3_Msk                (0x8UL)        /*!< DPFSA3 (Bitfield-Mask: 0x01)                          */
19158  #define R_SYSTEM_DPFSAR_DPFSA4_Pos                (4UL)          /*!< DPFSA4 (Bit 4)                                        */
19159  #define R_SYSTEM_DPFSAR_DPFSA4_Msk                (0x10UL)       /*!< DPFSA4 (Bitfield-Mask: 0x01)                          */
19160  #define R_SYSTEM_DPFSAR_DPFSA5_Pos                (5UL)          /*!< DPFSA5 (Bit 5)                                        */
19161  #define R_SYSTEM_DPFSAR_DPFSA5_Msk                (0x20UL)       /*!< DPFSA5 (Bitfield-Mask: 0x01)                          */
19162  #define R_SYSTEM_DPFSAR_DPFSA6_Pos                (6UL)          /*!< DPFSA6 (Bit 6)                                        */
19163  #define R_SYSTEM_DPFSAR_DPFSA6_Msk                (0x40UL)       /*!< DPFSA6 (Bitfield-Mask: 0x01)                          */
19164  #define R_SYSTEM_DPFSAR_DPFSA7_Pos                (7UL)          /*!< DPFSA7 (Bit 7)                                        */
19165  #define R_SYSTEM_DPFSAR_DPFSA7_Msk                (0x80UL)       /*!< DPFSA7 (Bitfield-Mask: 0x01)                          */
19166  #define R_SYSTEM_DPFSAR_DPFSA8_Pos                (8UL)          /*!< DPFSA8 (Bit 8)                                        */
19167  #define R_SYSTEM_DPFSAR_DPFSA8_Msk                (0x100UL)      /*!< DPFSA8 (Bitfield-Mask: 0x01)                          */
19168  #define R_SYSTEM_DPFSAR_DPFSA9_Pos                (9UL)          /*!< DPFSA9 (Bit 9)                                        */
19169  #define R_SYSTEM_DPFSAR_DPFSA9_Msk                (0x200UL)      /*!< DPFSA9 (Bitfield-Mask: 0x01)                          */
19170  #define R_SYSTEM_DPFSAR_DPFSA10_Pos               (10UL)         /*!< DPFSA10 (Bit 10)                                      */
19171  #define R_SYSTEM_DPFSAR_DPFSA10_Msk               (0x400UL)      /*!< DPFSA10 (Bitfield-Mask: 0x01)                         */
19172  #define R_SYSTEM_DPFSAR_DPFSA11_Pos               (11UL)         /*!< DPFSA11 (Bit 11)                                      */
19173  #define R_SYSTEM_DPFSAR_DPFSA11_Msk               (0x800UL)      /*!< DPFSA11 (Bitfield-Mask: 0x01)                         */
19174  #define R_SYSTEM_DPFSAR_DPFSA12_Pos               (12UL)         /*!< DPFSA12 (Bit 12)                                      */
19175  #define R_SYSTEM_DPFSAR_DPFSA12_Msk               (0x1000UL)     /*!< DPFSA12 (Bitfield-Mask: 0x01)                         */
19176  #define R_SYSTEM_DPFSAR_DPFSA13_Pos               (13UL)         /*!< DPFSA13 (Bit 13)                                      */
19177  #define R_SYSTEM_DPFSAR_DPFSA13_Msk               (0x2000UL)     /*!< DPFSA13 (Bitfield-Mask: 0x01)                         */
19178  #define R_SYSTEM_DPFSAR_DPFSA14_Pos               (14UL)         /*!< DPFSA14 (Bit 14)                                      */
19179  #define R_SYSTEM_DPFSAR_DPFSA14_Msk               (0x4000UL)     /*!< DPFSA14 (Bitfield-Mask: 0x01)                         */
19180  #define R_SYSTEM_DPFSAR_DPFSA15_Pos               (15UL)         /*!< DPFSA15 (Bit 15)                                      */
19181  #define R_SYSTEM_DPFSAR_DPFSA15_Msk               (0x8000UL)     /*!< DPFSA15 (Bitfield-Mask: 0x01)                         */
19182  #define R_SYSTEM_DPFSAR_DPFSA16_Pos               (16UL)         /*!< DPFSA16 (Bit 16)                                      */
19183  #define R_SYSTEM_DPFSAR_DPFSA16_Msk               (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
19184  #define R_SYSTEM_DPFSAR_DPFSA17_Pos               (17UL)         /*!< DPFSA17 (Bit 17)                                      */
19185  #define R_SYSTEM_DPFSAR_DPFSA17_Msk               (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
19186  #define R_SYSTEM_DPFSAR_DPFSA18_Pos               (18UL)         /*!< DPFSA18 (Bit 18)                                      */
19187  #define R_SYSTEM_DPFSAR_DPFSA18_Msk               (0x40000UL)    /*!< DPFSA18 (Bitfield-Mask: 0x01)                         */
19188  #define R_SYSTEM_DPFSAR_DPFSA19_Pos               (19UL)         /*!< DPFSA19 (Bit 19)                                      */
19189  #define R_SYSTEM_DPFSAR_DPFSA19_Msk               (0x80000UL)    /*!< DPFSA19 (Bitfield-Mask: 0x01)                         */
19190  #define R_SYSTEM_DPFSAR_DPFSA20_Pos               (20UL)         /*!< DPFSA20 (Bit 20)                                      */
19191  #define R_SYSTEM_DPFSAR_DPFSA20_Msk               (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
19192  #define R_SYSTEM_DPFSAR_DPFSA24_Pos               (24UL)         /*!< DPFSA24 (Bit 24)                                      */
19193  #define R_SYSTEM_DPFSAR_DPFSA24_Msk               (0x1000000UL)  /*!< DPFSA24 (Bitfield-Mask: 0x01)                         */
19194  #define R_SYSTEM_DPFSAR_DPFSA26_Pos               (26UL)         /*!< DPFSA26 (Bit 26)                                      */
19195  #define R_SYSTEM_DPFSAR_DPFSA26_Msk               (0x4000000UL)  /*!< DPFSA26 (Bitfield-Mask: 0x01)                         */
19196  #define R_SYSTEM_DPFSAR_DPFSA27_Pos               (27UL)         /*!< DPFSA27 (Bit 27)                                      */
19197  #define R_SYSTEM_DPFSAR_DPFSA27_Msk               (0x8000000UL)  /*!< DPFSA27 (Bitfield-Mask: 0x01)                         */
19198 /* ========================================================  DPSWCR  ========================================================= */
19199  #define R_SYSTEM_DPSWCR_WTSTS_Pos                 (0UL)          /*!< WTSTS (Bit 0)                                         */
19200  #define R_SYSTEM_DPSWCR_WTSTS_Msk                 (0x3fUL)       /*!< WTSTS (Bitfield-Mask: 0x3f)                           */
19201 /* ======================================================  VBATTMNSELR  ====================================================== */
19202  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos       (0UL)          /*!< VBATTMNSEL (Bit 0)                                    */
19203  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk       (0x1UL)        /*!< VBATTMNSEL (Bitfield-Mask: 0x01)                      */
19204 /* =======================================================  VBATTMONR  ======================================================= */
19205  #define R_SYSTEM_VBATTMONR_VBATTMON_Pos           (0UL)          /*!< VBATTMON (Bit 0)                                      */
19206  #define R_SYSTEM_VBATTMONR_VBATTMON_Msk           (0x1UL)        /*!< VBATTMON (Bitfield-Mask: 0x01)                        */
19207 /* ========================================================  VBTBER  ========================================================= */
19208  #define R_SYSTEM_VBTBER_VBAE_Pos                  (3UL)          /*!< VBAE (Bit 3)                                          */
19209  #define R_SYSTEM_VBTBER_VBAE_Msk                  (0x8UL)        /*!< VBAE (Bitfield-Mask: 0x01)                            */
19210 
19211 /* =========================================================================================================================== */
19212 /* ================                                          R_TRNG                                           ================ */
19213 /* =========================================================================================================================== */
19214 
19215 /* ========================================================  TRNGSDR  ======================================================== */
19216  #define R_TRNG_TRNGSDR_SDATA_Pos       (0UL)    /*!< SDATA (Bit 0)                                         */
19217  #define R_TRNG_TRNGSDR_SDATA_Msk       (0xffUL) /*!< SDATA (Bitfield-Mask: 0xff)                           */
19218 /* =======================================================  TRNGSCR0  ======================================================== */
19219  #define R_TRNG_TRNGSCR0_RDRDY_Pos      (7UL)    /*!< RDRDY (Bit 7)                                         */
19220  #define R_TRNG_TRNGSCR0_RDRDY_Msk      (0x80UL) /*!< RDRDY (Bitfield-Mask: 0x01)                           */
19221  #define R_TRNG_TRNGSCR0_SGCEN_Pos      (3UL)    /*!< SGCEN (Bit 3)                                         */
19222  #define R_TRNG_TRNGSCR0_SGCEN_Msk      (0x8UL)  /*!< SGCEN (Bitfield-Mask: 0x01)                           */
19223  #define R_TRNG_TRNGSCR0_SGSTART_Pos    (2UL)    /*!< SGSTART (Bit 2)                                       */
19224  #define R_TRNG_TRNGSCR0_SGSTART_Msk    (0x4UL)  /*!< SGSTART (Bitfield-Mask: 0x01)                         */
19225 /* =======================================================  TRNGSCR1  ======================================================== */
19226  #define R_TRNG_TRNGSCR1_INTEN_Pos      (0UL)    /*!< INTEN (Bit 0)                                         */
19227  #define R_TRNG_TRNGSCR1_INTEN_Msk      (0x1UL)  /*!< INTEN (Bitfield-Mask: 0x01)                           */
19228 
19229 /* =========================================================================================================================== */
19230 /* ================                                           R_TSN                                           ================ */
19231 /* =========================================================================================================================== */
19232 
19233 /* =========================================================  TSCDR  ========================================================= */
19234 /* ========================================================  TSCDRH  ========================================================= */
19235  #define R_TSN_TSCDRH_TSCDRH_Pos    (0UL)    /*!< TSCDRH (Bit 0)                                        */
19236  #define R_TSN_TSCDRH_TSCDRH_Msk    (0xffUL) /*!< TSCDRH (Bitfield-Mask: 0xff)                          */
19237 /* ========================================================  TSCDRL  ========================================================= */
19238  #define R_TSN_TSCDRL_TSCDRL_Pos    (0UL)    /*!< TSCDRL (Bit 0)                                        */
19239  #define R_TSN_TSCDRL_TSCDRL_Msk    (0xffUL) /*!< TSCDRL (Bitfield-Mask: 0xff)                          */
19240 
19241 /* =========================================================================================================================== */
19242 /* ================                                         R_USB_FS0                                         ================ */
19243 /* =========================================================================================================================== */
19244 
19245 /* ========================================================  SYSCFG  ========================================================= */
19246  #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
19247  #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
19248  #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
19249  #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
19250  #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
19251  #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
19252  #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
19253  #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
19254  #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
19255  #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
19256  #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
19257  #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
19258  #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
19259  #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
19260 /* ========================================================  BUSWAIT  ======================================================== */
19261  #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
19262  #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
19263 /* ========================================================  SYSSTS0  ======================================================== */
19264  #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
19265  #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
19266  #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
19267  #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
19268  #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
19269  #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
19270  #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
19271  #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
19272  #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
19273  #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
19274 /* ========================================================  PLLSTA  ========================================================= */
19275  #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
19276  #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
19277 /* =======================================================  DVSTCTR0  ======================================================== */
19278  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
19279  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
19280  #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
19281  #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
19282  #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
19283  #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
19284  #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
19285  #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
19286  #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
19287  #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
19288  #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
19289  #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
19290  #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
19291  #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
19292  #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
19293  #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
19294  #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
19295  #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
19296 /* =======================================================  TESTMODE  ======================================================== */
19297  #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
19298  #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
19299 /* ========================================================  CFIFOL  ========================================================= */
19300 /* ========================================================  CFIFOLL  ======================================================== */
19301 /* =========================================================  CFIFO  ========================================================= */
19302 /* ========================================================  CFIFOH  ========================================================= */
19303 /* ========================================================  CFIFOHH  ======================================================== */
19304 /* ========================================================  D0FIFOL  ======================================================== */
19305 /* =======================================================  D0FIFOLL  ======================================================== */
19306 /* ========================================================  D0FIFO  ========================================================= */
19307 /* ========================================================  D0FIFOH  ======================================================== */
19308 /* =======================================================  D0FIFOHH  ======================================================== */
19309 /* ========================================================  D1FIFOL  ======================================================== */
19310 /* =======================================================  D1FIFOLL  ======================================================== */
19311 /* ========================================================  D1FIFO  ========================================================= */
19312 /* ========================================================  D1FIFOH  ======================================================== */
19313 /* =======================================================  D1FIFOHH  ======================================================== */
19314 /* =======================================================  CFIFOSEL  ======================================================== */
19315  #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
19316  #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
19317  #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
19318  #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
19319  #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
19320  #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
19321  #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
19322  #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
19323  #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
19324  #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
19325  #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
19326  #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
19327 /* =======================================================  CFIFOCTR  ======================================================== */
19328  #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
19329  #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
19330  #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
19331  #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
19332  #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
19333  #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
19334  #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
19335  #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
19336 /* =======================================================  D0FIFOSEL  ======================================================= */
19337  #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
19338  #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
19339  #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
19340  #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
19341  #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
19342  #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
19343  #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
19344  #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
19345  #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
19346  #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
19347  #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
19348  #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
19349  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
19350  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
19351 /* =======================================================  D0FIFOCTR  ======================================================= */
19352  #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
19353  #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
19354  #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
19355  #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
19356  #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
19357  #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
19358  #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
19359  #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
19360 /* =======================================================  D1FIFOSEL  ======================================================= */
19361  #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
19362  #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
19363  #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
19364  #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
19365  #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
19366  #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
19367  #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
19368  #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
19369  #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
19370  #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
19371  #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
19372  #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
19373  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
19374  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
19375 /* =======================================================  D1FIFOCTR  ======================================================= */
19376  #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
19377  #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
19378  #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
19379  #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
19380  #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
19381  #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
19382  #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
19383  #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
19384 /* ========================================================  INTENB0  ======================================================== */
19385  #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
19386  #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
19387  #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
19388  #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
19389  #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
19390  #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
19391  #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
19392  #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
19393  #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
19394  #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
19395  #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
19396  #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
19397  #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
19398  #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
19399  #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
19400  #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
19401 /* ========================================================  INTENB1  ======================================================== */
19402  #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
19403  #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
19404  #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
19405  #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
19406  #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
19407  #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
19408  #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
19409  #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
19410  #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
19411  #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
19412  #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
19413  #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
19414  #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
19415  #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
19416  #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
19417  #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
19418 /* ========================================================  BRDYENB  ======================================================== */
19419  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
19420  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
19421 /* ========================================================  NRDYENB  ======================================================== */
19422  #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
19423  #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
19424 /* ========================================================  BEMPENB  ======================================================== */
19425  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
19426  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
19427 /* ========================================================  SOFCFG  ========================================================= */
19428  #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
19429  #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
19430  #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
19431  #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
19432  #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
19433  #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
19434  #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
19435  #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
19436 /* ========================================================  PHYSET  ========================================================= */
19437  #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
19438  #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
19439  #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
19440  #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
19441  #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
19442  #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
19443  #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
19444  #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
19445  #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
19446  #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
19447  #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
19448  #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
19449  #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
19450  #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
19451 /* ========================================================  INTSTS0  ======================================================== */
19452  #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
19453  #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
19454  #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
19455  #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
19456  #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
19457  #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
19458  #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
19459  #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
19460  #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
19461  #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
19462  #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
19463  #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
19464  #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
19465  #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
19466  #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
19467  #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
19468  #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
19469  #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
19470  #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
19471  #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
19472  #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
19473  #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
19474  #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
19475  #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
19476 /* ========================================================  INTSTS1  ======================================================== */
19477  #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
19478  #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
19479  #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
19480  #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
19481  #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
19482  #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
19483  #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
19484  #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
19485  #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
19486  #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
19487  #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
19488  #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
19489  #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
19490  #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
19491  #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
19492  #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
19493  #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
19494  #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
19495  #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
19496  #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
19497 /* ========================================================  BRDYSTS  ======================================================== */
19498  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
19499  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
19500 /* ========================================================  NRDYSTS  ======================================================== */
19501  #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
19502  #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
19503 /* ========================================================  BEMPSTS  ======================================================== */
19504  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
19505  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
19506 /* ========================================================  FRMNUM  ========================================================= */
19507  #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
19508  #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
19509  #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
19510  #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
19511  #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
19512  #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
19513 /* ========================================================  UFRMNUM  ======================================================== */
19514  #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
19515  #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
19516  #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
19517  #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
19518 /* ========================================================  USBADDR  ======================================================== */
19519  #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
19520  #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
19521  #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
19522  #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
19523 /* ========================================================  USBREQ  ========================================================= */
19524  #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
19525  #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
19526  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
19527  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
19528 /* ========================================================  USBVAL  ========================================================= */
19529  #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
19530  #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
19531 /* ========================================================  USBINDX  ======================================================== */
19532  #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
19533  #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
19534 /* ========================================================  USBLENG  ======================================================== */
19535  #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
19536  #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
19537 /* ========================================================  DCPCFG  ========================================================= */
19538  #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
19539  #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
19540  #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
19541  #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
19542  #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
19543  #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
19544 /* ========================================================  DCPMAXP  ======================================================== */
19545  #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
19546  #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
19547  #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
19548  #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
19549 /* ========================================================  DCPCTR  ========================================================= */
19550  #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
19551  #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
19552  #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
19553  #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
19554  #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
19555  #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
19556  #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
19557  #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
19558  #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
19559  #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
19560  #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
19561  #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
19562  #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
19563  #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
19564  #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
19565  #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
19566  #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
19567  #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
19568 /* ========================================================  PIPESEL  ======================================================== */
19569  #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
19570  #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
19571 /* ========================================================  PIPECFG  ======================================================== */
19572  #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
19573  #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
19574  #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
19575  #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
19576  #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
19577  #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
19578  #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
19579  #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
19580  #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
19581  #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
19582  #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
19583  #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
19584 /* =======================================================  PIPEMAXP  ======================================================== */
19585  #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
19586  #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
19587  #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
19588  #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
19589 /* =======================================================  PIPEPERI  ======================================================== */
19590  #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
19591  #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
19592  #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
19593  #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
19594 /* =======================================================  PIPE_CTR  ======================================================== */
19595  #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
19596  #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
19597  #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
19598  #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
19599  #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
19600  #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
19601  #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
19602  #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
19603  #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
19604  #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
19605  #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
19606  #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
19607  #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
19608  #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
19609  #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
19610  #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
19611  #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
19612  #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
19613  #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
19614  #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
19615  #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
19616  #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
19617 /* ========================================================  DEVADD  ========================================================= */
19618  #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
19619  #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
19620  #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
19621  #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
19622  #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
19623  #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
19624 /* ======================================================  USBBCCTRL0  ======================================================= */
19625  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
19626  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
19627  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
19628  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
19629  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
19630  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
19631  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
19632  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
19633  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
19634  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
19635  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
19636  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
19637  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
19638  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
19639  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
19640  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
19641  #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
19642  #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
19643 /* ========================================================  UCKSEL  ========================================================= */
19644  #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
19645  #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
19646 /* =========================================================  USBMC  ========================================================= */
19647  #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
19648  #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
19649  #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
19650  #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
19651 /* ========================================================  PHYSLEW  ======================================================== */
19652  #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
19653  #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
19654  #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
19655  #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
19656  #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
19657  #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
19658  #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
19659  #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
19660 /* ========================================================  LPCTRL  ========================================================= */
19661  #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
19662  #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
19663 /* =========================================================  LPSTS  ========================================================= */
19664  #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
19665  #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
19666 /* ========================================================  BCCTRL  ========================================================= */
19667  #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
19668  #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
19669  #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
19670  #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
19671  #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
19672  #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
19673  #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
19674  #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
19675  #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
19676  #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
19677  #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
19678  #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
19679  #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
19680  #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
19681  #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
19682  #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
19683 /* =======================================================  PL1CTRL1  ======================================================== */
19684  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
19685  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
19686  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
19687  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
19688  #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
19689  #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
19690  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
19691  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
19692  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
19693  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
19694  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
19695  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
19696 /* =======================================================  PL1CTRL2  ======================================================== */
19697  #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
19698  #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
19699  #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
19700  #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
19701 /* =======================================================  HL1CTRL1  ======================================================== */
19702  #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
19703  #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
19704  #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
19705  #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
19706 /* =======================================================  HL1CTRL2  ======================================================== */
19707  #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
19708  #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
19709  #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
19710  #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
19711  #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
19712  #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
19713  #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
19714  #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
19715 /* ========================================================  DPUSR0R  ======================================================== */
19716  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
19717  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
19718  #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
19719  #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
19720  #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
19721  #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
19722 /* ========================================================  DPUSR1R  ======================================================== */
19723  #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
19724  #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
19725  #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
19726  #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
19727  #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
19728  #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
19729  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
19730  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
19731  #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
19732  #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
19733  #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
19734  #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
19735 /* ========================================================  DPUSR2R  ======================================================== */
19736  #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
19737  #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
19738  #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
19739  #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
19740  #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
19741  #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
19742  #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
19743  #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
19744  #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
19745  #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
19746  #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
19747  #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
19748 /* ========================================================  DPUSRCR  ======================================================== */
19749  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
19750  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
19751  #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
19752  #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
19753 /* ======================================================  DPUSR0R_FS  ======================================================= */
19754  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
19755  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
19756  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
19757  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
19758  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
19759  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
19760  #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
19761  #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
19762  #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
19763  #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
19764  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
19765  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
19766  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
19767  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
19768  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
19769  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
19770  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
19771  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
19772 /* ======================================================  DPUSR1R_FS  ======================================================= */
19773  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
19774  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
19775  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
19776  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
19777  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
19778  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
19779  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
19780  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
19781  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
19782  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
19783  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
19784  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
19785  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
19786  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
19787  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
19788  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
19789  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
19790  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
19791  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
19792  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
19793 
19794 /* =========================================================================================================================== */
19795 /* ================                                           R_WDT                                           ================ */
19796 /* =========================================================================================================================== */
19797 
19798 /* =========================================================  WDTRR  ========================================================= */
19799  #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
19800  #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
19801 /* =========================================================  WDTCR  ========================================================= */
19802  #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
19803  #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
19804  #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
19805  #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
19806  #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
19807  #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
19808  #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
19809  #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
19810 /* =========================================================  WDTSR  ========================================================= */
19811  #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
19812  #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
19813  #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
19814  #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
19815  #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
19816  #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
19817 /* ========================================================  WDTRCR  ========================================================= */
19818  #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
19819  #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
19820 /* =======================================================  WDTCSTPR  ======================================================== */
19821  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
19822  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
19823 
19824 /* =========================================================================================================================== */
19825 /* ================                                           R_AES                                           ================ */
19826 /* =========================================================================================================================== */
19827 
19828 /* ========================================================  AESMOD  ========================================================= */
19829  #define R_AES_AESMOD_WRRQEN_Pos      (9UL)          /*!< WRRQEN (Bit 9)                                        */
19830  #define R_AES_AESMOD_WRRQEN_Msk      (0x200UL)      /*!< WRRQEN (Bitfield-Mask: 0x01)                          */
19831  #define R_AES_AESMOD_RDRQEN_Pos      (8UL)          /*!< RDRQEN (Bit 8)                                        */
19832  #define R_AES_AESMOD_RDRQEN_Msk      (0x100UL)      /*!< RDRQEN (Bitfield-Mask: 0x01)                          */
19833  #define R_AES_AESMOD_MODEN_Pos       (0UL)          /*!< MODEN (Bit 0)                                         */
19834  #define R_AES_AESMOD_MODEN_Msk       (0x1UL)        /*!< MODEN (Bitfield-Mask: 0x01)                           */
19835 /* ========================================================  AESCMD  ========================================================= */
19836  #define R_AES_AESCMD_ILOP_Pos        (31UL)         /*!< ILOP (Bit 31)                                         */
19837  #define R_AES_AESCMD_ILOP_Msk        (0x80000000UL) /*!< ILOP (Bitfield-Mask: 0x01)                            */
19838  #define R_AES_AESCMD_KWRDY1_Pos      (30UL)         /*!< KWRDY1 (Bit 30)                                       */
19839  #define R_AES_AESCMD_KWRDY1_Msk      (0x40000000UL) /*!< KWRDY1 (Bitfield-Mask: 0x01)                          */
19840  #define R_AES_AESCMD_KWRDY0_Pos      (29UL)         /*!< KWRDY0 (Bit 29)                                       */
19841  #define R_AES_AESCMD_KWRDY0_Msk      (0x20000000UL) /*!< KWRDY0 (Bitfield-Mask: 0x01)                          */
19842  #define R_AES_AESCMD_IRRDY_Pos       (28UL)         /*!< IRRDY (Bit 28)                                        */
19843  #define R_AES_AESCMD_IRRDY_Msk       (0x10000000UL) /*!< IRRDY (Bitfield-Mask: 0x01)                           */
19844  #define R_AES_AESCMD_IWRDY_Pos       (27UL)         /*!< IWRDY (Bit 27)                                        */
19845  #define R_AES_AESCMD_IWRDY_Msk       (0x8000000UL)  /*!< IWRDY (Bitfield-Mask: 0x01)                           */
19846  #define R_AES_AESCMD_CWRDY_Pos       (26UL)         /*!< CWRDY (Bit 26)                                        */
19847  #define R_AES_AESCMD_CWRDY_Msk       (0x4000000UL)  /*!< CWRDY (Bitfield-Mask: 0x01)                           */
19848  #define R_AES_AESCMD_DRRDY_Pos       (25UL)         /*!< DRRDY (Bit 25)                                        */
19849  #define R_AES_AESCMD_DRRDY_Msk       (0x2000000UL)  /*!< DRRDY (Bitfield-Mask: 0x01)                           */
19850  #define R_AES_AESCMD_DWRDY_Pos       (24UL)         /*!< DWRDY (Bit 24)                                        */
19851  #define R_AES_AESCMD_DWRDY_Msk       (0x1000000UL)  /*!< DWRDY (Bitfield-Mask: 0x01)                           */
19852  #define R_AES_AESCMD_KEYSEL_Pos      (12UL)         /*!< KEYSEL (Bit 12)                                       */
19853  #define R_AES_AESCMD_KEYSEL_Msk      (0x1000UL)     /*!< KEYSEL (Bitfield-Mask: 0x01)                          */
19854  #define R_AES_AESCMD_STORESEL_Pos    (8UL)          /*!< STORESEL (Bit 8)                                      */
19855  #define R_AES_AESCMD_STORESEL_Msk    (0x300UL)      /*!< STORESEL (Bitfield-Mask: 0x03)                        */
19856  #define R_AES_AESCMD_CHAIN_Pos       (4UL)          /*!< CHAIN (Bit 4)                                         */
19857  #define R_AES_AESCMD_CHAIN_Msk       (0x30UL)       /*!< CHAIN (Bitfield-Mask: 0x03)                           */
19858  #define R_AES_AESCMD_KEYLN_Pos       (1UL)          /*!< KEYLN (Bit 1)                                         */
19859  #define R_AES_AESCMD_KEYLN_Msk       (0x2UL)        /*!< KEYLN (Bitfield-Mask: 0x01)                           */
19860  #define R_AES_AESCMD_INVCIP_Pos      (0UL)          /*!< INVCIP (Bit 0)                                        */
19861  #define R_AES_AESCMD_INVCIP_Msk      (0x1UL)        /*!< INVCIP (Bitfield-Mask: 0x01)                          */
19862 /* =========================================================  AESDW  ========================================================= */
19863 /* ========================================================  AESIVW  ========================================================= */
19864 /* ========================================================  AESKW0  ========================================================= */
19865 /* ========================================================  AESKW1  ========================================================= */
19866 
19867 /* =========================================================================================================================== */
19868 /* ================                                          R_AGTX0                                          ================ */
19869 /* =========================================================================================================================== */
19870 
19871 /** @} */ /* End of group PosMask_peripherals */
19872 
19873  #ifdef __cplusplus
19874 }
19875  #endif
19876 
19877 #endif                                 /* R7FA2A1AB_H */
19878 
19879 /** @} */ /* End of group R7FA2A1AB */
19880 
19881 /** @} */ /* End of group Renesas */
19882