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Searched refs:R_SCI0_BASE (Results 1 – 23 of 23) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/r_sci_b_uart/
Dr_sci_b_uart.c79 #define SCI_B_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE)
308 p_ctrl->p_reg = (R_SCI_B0_Type *) (R_SCI0_BASE + (SCI_B_REG_SIZE * p_cfg->channel)); in R_SCI_B_UART_Open()
/hal_renesas-latest/drivers/ra/fsp/src/r_sci_uart/
Dr_sci_uart.c85 #define SCI_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE)
345 p_ctrl->p_reg = ((R_SCI0_Type *) (R_SCI0_BASE + (SCI_REG_SIZE * p_cfg->channel))); in R_SCI_UART_Open()
/hal_renesas-latest/drivers/rz/fsp/src/rzn/r_sci_uart/
Dr_sci_uart.c125 #define SCI_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE)
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA2L1AB.h12308 #define R_SCI0_BASE 0x40070000UL macro
12410 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA2A1AB.h13648 #define R_SCI0_BASE 0x40070000UL macro
13761 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA4E10D.h13510 #define R_SCI0_BASE 0x40118000UL macro
13621 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA4W1AD.h13622 #define R_SCI0_BASE 0x40070000UL macro
13736 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA4M1AB.h13785 #define R_SCI0_BASE 0x40070000UL macro
13900 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA4M2AD.h14503 #define R_SCI0_BASE 0x40118000UL macro
14621 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA4M3AF.h14606 #define R_SCI0_BASE 0x40118000UL macro
14725 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA4E2B9.h15827 #define R_SCI0_BASE 0x40118000UL macro
15947 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA6E10F.h14989 #define R_SCI0_BASE 0x40118000UL macro
15106 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA6M1AD.h15314 #define R_SCI0_BASE 0x40070000UL macro
15441 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA6E2BB.h16032 #define R_SCI0_BASE 0x40118000UL macro
16153 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA6M4AF.h16683 #define R_SCI0_BASE 0x40118000UL macro
16806 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA4L1BD.h17354 #define R_SCI0_BASE 0x40118000UL macro
17483 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA6M2AF.h17300 #define R_SCI0_BASE 0x40070000UL macro
17432 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA6M3AH.h19964 #define R_SCI0_BASE 0x40070000UL macro
20102 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA6M5BH.h19300 #define R_SCI0_BASE 0x40118000UL macro
19425 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA8T1AH.h20146 #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) macro
20288 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA8M1AH.h22115 #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) macro
22260 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
DR7FA8D1BH.h29962 #define R_SCI0_BASE (0x40358000UL + BASE_NS_OFFSET) macro
30111 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h30688 #define R_SCI0_BASE 0x80001000UL macro
30808 #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE)