Searched refs:R_GPIO (Results 1 – 3 of 3) sorted by relevance
40 #define BSP_IO_PRV_P_REG_BASE(base) (&R_GPIO->P ## base)42 #define BSP_IO_PRV_PM_REG_BASE(base) (&R_GPIO->PM ## base)44 #define BSP_IO_PRV_PIN_REG_BASE(base) (&R_GPIO->PIN ## base)527 … R_GPIO->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled in R_BSP_PinAccessEnable()528 …R_GPIO->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled in R_BSP_PinAccessEnable()530 …R_GPIO->PWPR = (uint32_t) ((BSP_IO_PRV_PFCWE_MASK & R_GPIO->PWPR) | (1U << BSP_IO_PWPR_PFSWE_OFFSE… in R_BSP_PinAccessEnable()565 …R_GPIO->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disab… in R_BSP_PinAccessDisable()566 … R_GPIO->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled in R_BSP_PinAccessDisable()568 R_GPIO->PWPR = (uint32_t) (BSP_IO_PRV_PFCWE_MASK & R_GPIO->PWPR); in R_BSP_PinAccessDisable()589 …R_GPIO->PWPR = (uint32_t) ((BSP_IO_PRV_OENWE_MASK & R_GPIO->PWPR) | (1U << BSP_IO_PWPR_OENWE_OFFSE… in R_BSP_OENAccessEnable()[all …]
72 #define IOPORT_PRV_P_REG_BASE(base) (&R_GPIO->P ## base)74 #define IOPORT_PRV_PM_REG_BASE(base) (&R_GPIO->PM ## base)76 #define IOPORT_PRV_PMC_REG_BASE(base) (&R_GPIO->PMC ## base)78 #define IOPORT_PRV_PFC_REG_BASE(base) (&R_GPIO->PFC ## base)80 #define IOPORT_PRV_PIN_REG_BASE(base) (&R_GPIO->PIN ## base)82 #define IOPORT_PRV_IEN_REG_BASE(base) (&R_GPIO->IEN ## base)84 #define IOPORT_PRV_ISEL_REG_BASE(base) (&R_GPIO->ISEL ## base)86 #define IOPORT_PRV_IOLH_REG_BASE(base) (&R_GPIO->IOLH ## base)88 #define IOPORT_PRV_SR_REG_BASE(base) (&R_GPIO->SR ## base)90 #define IOPORT_PRV_PUPD_REG_BASE(base) (&R_GPIO->PUPD ## base)[all …]
6962 #define R_GPIO ((R_GPIO_Type *) R_GPIO_BASE) macro
