1 /*
2  * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * @file     ./out/R7FA8D1BH.h
7  * @brief    CMSIS HeaderFile
8  * @version  1.2
9  */
10 
11 /** @addtogroup Renesas
12  * @{
13  */
14 
15 /** @addtogroup R7FA8D1BH
16  * @{
17  */
18 
19 #ifndef R7FA8D1BH_H
20  #define R7FA8D1BH_H
21 
22  #ifdef __cplusplus
23 extern "C" {
24  #endif
25 
26 /** @addtogroup Configuration_of_CMSIS
27  * @{
28  */
29 
30 /* =========================================================================================================================== */
31 /* ================                                Interrupt Number Definition                                ================ */
32 /* =========================================================================================================================== */
33 
34 /* =========================================================================================================================== */
35 /* ================                           Processor and Core Peripheral Section                           ================ */
36 /* =========================================================================================================================== */
37 
38 /* ==========================  Configuration of the ARM Cortex-M85 Processor and Core Peripherals  =========================== */
39  #define __CM85_REV                0x0000U /*!< CM85 Core Revision                                                        */
40  #define __NVIC_PRIO_BITS          4       /*!< Number of Bits used for Priority Levels                                   */
41  #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
42  #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
43  #define __MPU_PRESENT             1       /*!< MPU present                                                               */
44  #define __FPU_PRESENT             1       /*!< FPU present                                                               */
45  #define __FPU_DP                  0       /*!< Double Precision FPU                                                      */
46  #define __DSP_PRESENT             1       /*!< DSP extension present                                                     */
47  #define __ICACHE_PRESENT          1       /*!< Instruction Cache present                                                 */
48  #define __DCACHE_PRESENT          1       /*!< Data Cache present                                                        */
49  #define __SAUREGION_PRESENT       1       /*!< SAU region present                                                        */
50  #define __PMU_PRESENT             0       /*!< PMU present                                                               */
51  #define __PMU_NUM_EVENTCNT        0       /*!< PMU Event Counters                                                        */
52 
53 /** @} */ /* End of group Configuration_of_CMSIS */
54 
55  #include "core_cm85.h"                    /*!< ARM Cortex-M85 processor and core peripherals                             */
56  #include "system.h"                       /*!< R7FA8D1BH System                                                          */
57 
58  #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
59   #define __IM     __I
60  #endif
61  #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
62   #define __OM     __O
63  #endif
64  #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
65   #define __IOM    __IO
66  #endif
67 
68 /* ========================================  Start of section using anonymous unions  ======================================== */
69  #if defined(__CC_ARM)
70   #pragma push
71   #pragma anon_unions
72  #elif defined(__ICCARM__)
73   #pragma language=extended
74  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
75   #pragma clang diagnostic push
76   #pragma clang diagnostic ignored "-Wc11-extensions"
77   #pragma clang diagnostic ignored "-Wreserved-id-macro"
78   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
79   #pragma clang diagnostic ignored "-Wnested-anon-types"
80  #elif defined(__GNUC__)
81 
82 /* anonymous unions are enabled by default */
83  #elif defined(__TMS470__)
84 
85 /* anonymous unions are enabled by default */
86  #elif defined(__TASKING__)
87   #pragma warning 586
88  #elif defined(__CSMC__)
89 
90 /* anonymous unions are enabled by default */
91  #else
92   #warning Not supported compiler type
93  #endif
94 
95 /* =========================================================================================================================== */
96 /* ================                              Device Specific Cluster Section                              ================ */
97 /* =========================================================================================================================== */
98 
99 /** @addtogroup Device_Peripheral_clusters
100  * @{
101  */
102 
103 /**
104  * @brief R_BUS_CSa [CSa] (CS Registers)
105  */
106 typedef struct
107 {
108     __IM uint16_t RESERVED;
109 
110     union
111     {
112         __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
113 
114         struct
115         {
116             __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
117             uint16_t             : 2;
118             __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
119             uint16_t             : 4;
120             __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
121             __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
122             uint16_t             : 5;
123             __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
124         } MOD_b;
125     };
126 
127     union
128     {
129         __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
130 
131         struct
132         {
133             __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select                                       */
134             uint32_t                : 5;
135             __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select                                       */
136             uint32_t                : 5;
137             __IOM uint32_t CSWWAIT  : 5; /*!< [20..16] Normal Write Cycle Wait Select                                   */
138             uint32_t                : 3;
139             __IOM uint32_t CSRWAIT  : 5; /*!< [28..24] Normal Read Cycle Wait Select                                    */
140             uint32_t                : 3;
141         } WCR1_b;
142     };
143 
144     union
145     {
146         __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
147 
148         struct
149         {
150             __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
151             uint32_t              : 1;
152             __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
153             uint32_t              : 1;
154             __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
155             uint32_t              : 1;
156             __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
157             uint32_t              : 2;
158             __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
159             uint32_t              : 1;
160             __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
161             uint32_t              : 1;
162             __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
163             uint32_t              : 1;
164             __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
165             uint32_t              : 1;
166         } WCR2_b;
167     };
168     __IM uint32_t RESERVED1;
169 } R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
170 
171 /**
172  * @brief R_BUS_CSb [CSb] (CS Registers)
173  */
174 typedef struct
175 {
176     __IM uint16_t RESERVED;
177 
178     union
179     {
180         __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
181 
182         struct
183         {
184             __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
185             uint16_t             : 3;
186             __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
187             uint16_t             : 2;
188             __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
189             uint16_t             : 3;
190             __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
191             uint16_t             : 3;
192         } CR_b;
193     };
194     __IM uint16_t RESERVED1[3];
195 
196     union
197     {
198         __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
199 
200         struct
201         {
202             __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
203             uint16_t            : 4;
204             __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
205             uint16_t            : 4;
206         } REC_b;
207     };
208     __IM uint16_t RESERVED2[2];
209 } R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
210 
211 /**
212  * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
213  */
214 typedef struct
215 {
216     union
217     {
218         __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
219 
220         struct
221         {
222             __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
223             uint8_t             : 3;
224             __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
225             uint8_t             : 2;
226         } SDCCR_b;
227     };
228 
229     union
230     {
231         __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
232 
233         struct
234         {
235             __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
236             uint8_t             : 7;
237         } SDCMOD_b;
238     };
239 
240     union
241     {
242         __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
243 
244         struct
245         {
246             __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
247             uint8_t          : 7;
248         } SDAMOD_b;
249     };
250     __IM uint8_t  RESERVED;
251     __IM uint32_t RESERVED1[3];
252 
253     union
254     {
255         __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
256 
257         struct
258         {
259             __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
260             uint8_t            : 7;
261         } SDSELF_b;
262     };
263     __IM uint8_t  RESERVED2;
264     __IM uint16_t RESERVED3;
265 
266     union
267     {
268         __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
269 
270         struct
271         {
272             __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
273             __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
274                                         *   Setting. ( REFW+1 Cycles )                                                */
275         } SDRFCR_b;
276     };
277 
278     union
279     {
280         __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
281 
282         struct
283         {
284             __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
285             uint8_t            : 7;
286         } SDRFEN_b;
287     };
288     __IM uint8_t  RESERVED4;
289     __IM uint32_t RESERVED5[2];
290 
291     union
292     {
293         __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
294 
295         struct
296         {
297             __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
298             uint8_t             : 7;
299         } SDICR_b;
300     };
301     __IM uint8_t  RESERVED6;
302     __IM uint16_t RESERVED7;
303 
304     union
305     {
306         __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
307 
308         struct
309         {
310             __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
311             __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
312             __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
313                                         *   )                                                                         */
314             uint16_t : 5;
315         } SDIR_b;
316     };
317     __IM uint16_t RESERVED8;
318     __IM uint32_t RESERVED9[6];
319 
320     union
321     {
322         __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
323 
324         struct
325         {
326             __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
327             uint8_t           : 6;
328         } SDADR_b;
329     };
330     __IM uint8_t  RESERVED10;
331     __IM uint16_t RESERVED11;
332 
333     union
334     {
335         __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
336 
337         struct
338         {
339             __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
340             uint32_t           : 5;
341             __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
342             __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
343             __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
344             uint32_t           : 2;
345             __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
346             uint32_t           : 13;
347         } SDTR_b;
348     };
349 
350     union
351     {
352         __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
353 
354         struct
355         {
356             __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register Setting                                             */
357             uint16_t          : 1;
358         } SDMOD_b;
359     };
360     __IM uint16_t RESERVED12;
361     __IM uint32_t RESERVED13;
362 
363     union
364     {
365         __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
366 
367         struct
368         {
369             __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
370             uint8_t            : 2;
371             __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
372             __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
373             uint8_t            : 3;
374         } SDSR_b;
375     };
376     __IM uint8_t  RESERVED14;
377     __IM uint16_t RESERVED15;
378 } R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
379 
380 /**
381  * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers)
382  */
383 typedef struct
384 {
385     union
386     {
387         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
388 
389         struct
390         {
391             __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error Address                                                 */
392         } ADD_b;
393     };
394 
395     union
396     {
397         union
398         {
399             __IM uint8_t STAT;            /*!< (@ 0x00000004) Bus Error Status Register                                  */
400 
401             struct
402             {
403                 __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status                                                */
404                 uint8_t              : 6;
405                 __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status                                                   */
406             } STAT_b;
407         };
408 
409         union
410         {
411             __IM uint8_t RW;             /*!< (@ 0x00000004) Bus Error Read Write                                       */
412 
413             struct
414             {
415                 __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status                                     */
416                 uint8_t             : 7;
417             } RW_b;
418         };
419     };
420     __IM uint8_t  RESERVED;
421     __IM uint16_t RESERVED1;
422     __IM uint32_t RESERVED2[2];
423 } R_BUS_BUSERRa_Type;                  /*!< Size = 16 (0x10)                                                          */
424 
425 /**
426  * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers)
427  */
428 typedef struct
429 {
430     union
431     {
432         __IM uint32_t ADD;               /*!< (@ 0x00000000) BUS TZF Error Address                                      */
433 
434         struct
435         {
436             __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address                                */
437         } ADD_b;
438     };
439 
440     union
441     {
442         __IM uint8_t RW;               /*!< (@ 0x00000004) BUS TZF Error Read Write                                   */
443 
444         struct
445         {
446             __IM uint8_t TRWSTAT : 1;  /*!< [0..0] TrustZone filter error access Read/Write Status                    */
447             uint8_t              : 7;
448         } RW_b;
449     };
450     __IM uint8_t  RESERVED;
451     __IM uint16_t RESERVED1;
452     __IM uint32_t RESERVED2[2];
453 } R_BUS_BTZFERR_Type;                  /*!< Size = 16 (0x10)                                                          */
454 
455 /**
456  * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers)
457  */
458 typedef struct
459 {
460     union
461     {
462         __IM uint8_t STAT;              /*!< (@ 0x00000000) Bus Error Status Register                                  */
463 
464         struct
465         {
466             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status.                                            */
467             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
468             uint8_t                : 1;
469             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status.                                           */
470             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status.                               */
471             __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status.                     */
472             uint8_t                : 2;
473         } STAT_b;
474     };
475     __IM uint8_t RESERVED[7];
476 
477     union
478     {
479         __IOM uint8_t CLR;              /*!< (@ 0x00000008) Bus Error Clear Register                                   */
480 
481         struct
482         {
483             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear.                                             */
484             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
485             uint8_t                : 1;
486             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear.                                            */
487             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear.                                */
488             __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear.                      */
489             uint8_t                : 2;
490         } CLR_b;
491     };
492     __IM uint8_t RESERVED1[7];
493 } R_BUS_BUSERRb_Type;                  /*!< Size = 16 (0x10)                                                          */
494 
495 /**
496  * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers)
497  */
498 typedef struct
499 {
500     __IM uint8_t RESERVED[36];
501 
502     union
503     {
504         __IM uint8_t STAT;              /*!< (@ 0x00000024) DMAC/DTC Error Status Register                             */
505 
506         struct
507         {
508             __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status                               */
509             uint8_t                : 7;
510         } STAT_b;
511     };
512     __IM uint8_t RESERVED1[7];
513 
514     union
515     {
516         __IOM uint8_t CLR;              /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register                              */
517 
518         struct
519         {
520             __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear                                */
521             uint8_t                : 7;
522         } CLR_b;
523     };
524 } R_BUS_DMACDTCERR_Type;                /*!< Size = 45 (0x2d)                                                          */
525 
526 /**
527  * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers)
528  */
529 typedef struct
530 {
531     __IM uint32_t RESERVED[2];
532 
533     union
534     {
535         __IOM uint32_t MRE0BI;         /*!< (@ 0x00000008) Bus Slave Arbitration Control Register                     */
536 
537         struct
538         {
539             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
540             uint32_t            : 31;
541         } MRE0BI_b;
542     };
543     __IM uint32_t RESERVED1;
544 
545     union
546     {
547         __IOM uint32_t FLBI;           /*!< (@ 0x00000010) Bus Slave Arbitration Control Register                     */
548 
549         struct
550         {
551             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
552             uint32_t            : 31;
553         } FLBI_b;
554     };
555     __IM uint32_t RESERVED2[3];
556 
557     union
558     {
559         __IOM uint32_t S0BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
560 
561         struct
562         {
563             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
564             uint32_t            : 31;
565         } S0BI_b;
566     };
567     __IM uint32_t RESERVED3;
568 
569     union
570     {
571         __IOM uint32_t S1BI;           /*!< (@ 0x00000028) Bus Slave Arbitration Control Register                     */
572 
573         struct
574         {
575             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
576             uint32_t            : 31;
577         } S1BI_b;
578     };
579     __IM uint32_t RESERVED4;
580 
581     union
582     {
583         __IOM uint32_t S2BI;           /*!< (@ 0x00000030) Bus Slave Arbitration Control Register                     */
584 
585         struct
586         {
587             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
588             uint32_t            : 31;
589         } S2BI_b;
590     };
591     __IM uint32_t RESERVED5;
592 
593     union
594     {
595         __IOM uint32_t S3BI;           /*!< (@ 0x00000038) Bus Slave Arbitration Control Register                     */
596 
597         struct
598         {
599             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
600             uint32_t            : 31;
601         } S3BI_b;
602     };
603     __IM uint32_t RESERVED6[3];
604 
605     union
606     {
607         __IOM uint32_t STBYSBI;        /*!< (@ 0x00000048) Bus Slave Arbitration Control Register                     */
608 
609         struct
610         {
611             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
612             uint32_t            : 31;
613         } STBYSBI_b;
614     };
615     __IM uint32_t RESERVED7;
616 
617     union
618     {
619         union
620         {
621             __IOM uint32_t ECBI;         /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
622 
623             struct
624             {
625                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
626                 uint32_t            : 31;
627             } ECBI_b;
628         };
629 
630         union
631         {
632             __IOM uint32_t SPI0BI;       /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
633 
634             struct
635             {
636                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
637                 uint32_t            : 31;
638             } SPI0BI_b;
639         };
640     };
641     __IM uint32_t RESERVED8;
642 
643     union
644     {
645         union
646         {
647             __IOM uint32_t EOBI;         /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
648 
649             struct
650             {
651                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
652                 uint32_t            : 31;
653             } EOBI_b;
654         };
655 
656         union
657         {
658             __IOM uint32_t SPI1BI;       /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
659 
660             struct
661             {
662                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
663                 uint32_t            : 31;
664             } SPI1BI_b;
665         };
666     };
667     __IM uint32_t RESERVED9;
668 
669     union
670     {
671         __IOM uint32_t PBBI;           /*!< (@ 0x00000060) Bus Slave Arbitration Control Register                     */
672 
673         struct
674         {
675             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
676             uint32_t            : 31;
677         } PBBI_b;
678     };
679     __IM uint32_t RESERVED10;
680 
681     union
682     {
683         union
684         {
685             __IOM uint32_t PABI;         /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
686 
687             struct
688             {
689                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
690                 uint32_t            : 31;
691             } PABI_b;
692         };
693 
694         union
695         {
696             __IOM uint32_t CPU0SAHBI;    /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
697 
698             struct
699             {
700                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
701                 uint32_t            : 31;
702             } CPU0SAHBI_b;
703         };
704     };
705     __IM uint32_t RESERVED11;
706 
707     union
708     {
709         union
710         {
711             __IOM uint32_t PIBI;         /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
712 
713             struct
714             {
715                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
716                 uint32_t            : 31;
717             } PIBI_b;
718         };
719 
720         union
721         {
722             __IOM uint32_t CPU1TCMBI;    /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
723 
724             struct
725             {
726                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
727                 uint32_t            : 31;
728             } CPU1TCMBI_b;
729         };
730     };
731     __IM uint32_t RESERVED12;
732 
733     union
734     {
735         __IOM uint32_t PSBI;           /*!< (@ 0x00000078) Bus Slave Arbitration Control Register                     */
736 
737         struct
738         {
739             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
740             uint32_t            : 31;
741         } PSBI_b;
742     };
743 } R_BUS_BUSSABT0_Type;                 /*!< Size = 124 (0x7c)                                                         */
744 
745 /**
746  * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers)
747  */
748 typedef struct
749 {
750     union
751     {
752         union
753         {
754             __IOM uint32_t FHBI;         /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
755 
756             struct
757             {
758                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
759                 uint32_t            : 30;
760             } FHBI_b;
761         };
762 
763         union
764         {
765             __IOM uint32_t MRC0BI;       /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
766 
767             struct
768             {
769                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
770                 uint32_t            : 30;
771             } MRC0BI_b;
772         };
773     };
774     __IM uint32_t RESERVED[5];
775 
776     union
777     {
778         __IOM uint32_t S0BI;           /*!< (@ 0x00000018) Bus Slave Arbitration Control Register                     */
779 
780         struct
781         {
782             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
783             uint32_t            : 30;
784         } S0BI_b;
785     };
786     __IM uint32_t RESERVED1;
787 
788     union
789     {
790         __IOM uint32_t S1BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
791 
792         struct
793         {
794             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
795             uint32_t            : 30;
796         } S1BI_b;
797     };
798 } R_BUS_BUSSABT1_Type;                 /*!< Size = 36 (0x24)                                                          */
799 
800 /**
801  * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.)
802  */
803 typedef struct
804 {
805     union
806     {
807         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address.        */
808 
809         struct
810         {
811             __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address.               */
812         } ADD_b;
813     };
814 
815     union
816     {
817         __IM uint8_t RW;                /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read
818                                          *                  Write.                                                     */
819 
820         struct
821         {
822             __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write
823                                          *   Status.                                                                   */
824             uint8_t : 7;
825         } RW_b;
826     };
827     __IM uint8_t  RESERVED;
828     __IM uint16_t RESERVED1;
829     __IM uint32_t RESERVED2[2];
830 } R_BUS_BMSAERR_Type;                  /*!< Size = 16 (0x10)                                                          */
831 
832 /**
833  * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers)
834  */
835 typedef struct
836 {
837     union
838     {
839         __IOM uint16_t BUSOAD;           /*!< (@ 0x00000000) Bus Operation After Detection Register                     */
840 
841         struct
842         {
843             __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection.            */
844             __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection.                         */
845             __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection.                  */
846             uint16_t                : 13;
847         } BUSOAD_b;
848     };
849     __IM uint16_t RESERVED;
850 
851     union
852     {
853         __IOM uint16_t BUSOADPT;        /*!< (@ 0x00000004) BUS Operation After Detection Protect Register.            */
854 
855         struct
856         {
857             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register.                                     */
858             uint16_t               : 7;
859             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
860         } BUSOADPT_b;
861     };
862     __IM uint16_t RESERVED1[5];
863 
864     union
865     {
866         __IOM uint16_t MSAOAD;         /*!< (@ 0x00000010) Master Security Attribution Operation After Detection
867                                         *                  Register.                                                  */
868 
869         struct
870         {
871             __IOM uint16_t OAD : 1;    /*!< [0..0] Master Security Attribution operation after detection.             */
872             uint16_t           : 7;
873             __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code.                                                         */
874         } MSAOAD_b;
875     };
876     __IM uint16_t RESERVED2;
877 
878     union
879     {
880         __IOM uint16_t MSAPT;           /*!< (@ 0x00000014) Master Security Attribution Protect Register.              */
881 
882         struct
883         {
884             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register.                                     */
885             uint16_t               : 7;
886             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
887         } MSAPT_b;
888     };
889 } R_BUS_OAD_Type;                       /*!< Size = 22 (0x16)                                                          */
890 
891 /**
892  * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers)
893  */
894 typedef struct
895 {
896     union
897     {
898         __IM uint32_t STAT;            /*!< (@ 0x00000000) Bufferable Write Error Status Register                     */
899 
900         struct
901         {
902             __IM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error in 0.                                       */
903             __IM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error in 1.                                       */
904             __IM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error in 2.                                       */
905             __IM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error in 3.                                       */
906             __IM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error in 4.                                       */
907             __IM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error in 5.                                       */
908             __IM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error in 6.                                       */
909             __IM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error in 7.                                       */
910             __IM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error in 8.                                       */
911             __IM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error in 9.                                       */
912             __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10.                                    */
913             __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11.                                    */
914             __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12.                                    */
915             __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13.                                    */
916             __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14.                                    */
917             __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15.                                    */
918             __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16.                                    */
919             __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17.                                    */
920             __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18.                                    */
921             __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19.                                    */
922             __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20.                                    */
923             __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21.                                    */
924             __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22.                                    */
925             __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23.                                    */
926             __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24.                                    */
927             __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25.                                    */
928             __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26.                                    */
929             __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27.                                    */
930             __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28.                                    */
931             __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29.                                    */
932             __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30.                                    */
933             __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31.                                    */
934         } STAT_b;
935     };
936     __IM uint32_t RESERVED;
937 
938     union
939     {
940         __IOM uint32_t CLR;             /*!< (@ 0x00000008) Bufferable Write Error Clear Register.                     */
941 
942         struct
943         {
944             __IOM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error Clear for 0.                                */
945             __IOM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error Clear for 1.                                */
946             __IOM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error Clear for 2.                                */
947             __IOM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error Clear for 3.                                */
948             __IOM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error Clear for 4.                                */
949             __IOM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error Clear for 5.                                */
950             __IOM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error Clear for 6.                                */
951             __IOM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error Clear for 7.                                */
952             __IOM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error Clear for 8.                                */
953             __IOM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error Clear for 9.                                */
954             __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10.                             */
955             __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11.                             */
956             __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12.                             */
957             __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13.                             */
958             __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14.                             */
959             __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15.                             */
960             __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16.                             */
961             __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17.                             */
962             __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18.                             */
963             __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19.                             */
964             __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20.                             */
965             __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21.                             */
966             __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22.                             */
967             __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23.                             */
968             __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24.                             */
969             __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25.                             */
970             __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26.                             */
971             __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27.                             */
972             __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28.                             */
973             __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29.                             */
974             __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30.                             */
975             __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31.                             */
976         } CLR_b;
977     };
978 } R_BUS_MBWERR_Type;                    /*!< Size = 12 (0xc)                                                           */
979 
980 /**
981  * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers)
982  */
983 typedef struct
984 {
985     union
986     {
987         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
988 
989         struct
990         {
991             uint16_t             : 15;
992             __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
993         } CNT_b;
994     };
995     __IM uint16_t RESERVED;
996 } R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
997 
998 /**
999  * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
1000  */
1001 typedef struct
1002 {
1003     union
1004     {
1005         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
1006 
1007         struct
1008         {
1009             __IOM uint16_t ARBS   : 2; /*!< [1..0] Arbitration Select                                                 */
1010             uint16_t              : 2;
1011             __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method                                                 */
1012             uint16_t              : 10;
1013         } CNT_b;
1014     };
1015     __IM uint16_t RESERVED;
1016 } R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
1017 
1018 /**
1019  * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
1020  */
1021 typedef struct
1022 {
1023     union
1024     {
1025         __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */
1026 
1027         struct
1028         {
1029             __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
1030             __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
1031             __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
1032             __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
1033         } NCFG_b;
1034     };
1035 
1036     union
1037     {
1038         __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */
1039 
1040         struct
1041         {
1042             __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
1043             __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
1044             __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
1045             uint32_t               : 4;
1046             __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
1047             __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
1048             __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
1049             __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
1050             __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
1051             __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
1052             __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
1053             __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
1054             __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
1055             __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
1056             __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
1057             __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
1058                                          *   enable                                                                    */
1059             uint32_t            : 1;
1060             __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
1061             __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
1062             __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
1063             __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
1064             uint32_t            : 3;
1065             __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
1066             __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
1067         } CTR_b;
1068     };
1069 
1070     union
1071     {
1072         __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */
1073 
1074         struct
1075         {
1076             __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
1077             __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
1078             __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
1079             __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
1080             __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
1081             __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
1082             __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
1083             __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
1084             __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
1085             uint32_t               : 7;
1086             __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
1087             __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
1088         } STS_b;
1089     };
1090 
1091     union
1092     {
1093         __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */
1094 
1095         struct
1096         {
1097             __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
1098             __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
1099             __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
1100             __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
1101             __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
1102             __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
1103             __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
1104             __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
1105             __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
1106             __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
1107             __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
1108             __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
1109             __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
1110             __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
1111             __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
1112             uint32_t             : 1;
1113             __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
1114             uint32_t             : 1;
1115         } ERFL_b;
1116     };
1117 } R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
1118 
1119 /**
1120  * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
1121  */
1122 typedef struct
1123 {
1124     union
1125     {
1126         __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */
1127 
1128         struct
1129         {
1130             __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
1131             __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
1132             uint32_t              : 3;
1133             __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
1134             uint32_t              : 4;
1135             __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
1136             uint32_t              : 4;
1137         } DCFG_b;
1138     };
1139 
1140     union
1141     {
1142         __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */
1143 
1144         struct
1145         {
1146             __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
1147             uint32_t              : 5;
1148             __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
1149             __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
1150             __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
1151             uint32_t              : 5;
1152             __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
1153             uint32_t              : 4;
1154             __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
1155             __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
1156             __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
1157             uint32_t              : 1;
1158         } FDCFG_b;
1159     };
1160 
1161     union
1162     {
1163         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */
1164 
1165         struct
1166         {
1167             __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
1168             __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
1169             uint32_t              : 30;
1170         } FDCTR_b;
1171     };
1172 
1173     union
1174     {
1175         __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */
1176 
1177         struct
1178         {
1179             __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
1180             __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
1181             __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
1182             uint32_t             : 5;
1183             __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
1184             __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
1185             __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
1186         } FDSTS_b;
1187     };
1188 
1189     union
1190     {
1191         __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */
1192 
1193         struct
1194         {
1195             __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
1196             uint32_t             : 3;
1197             __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
1198             uint32_t             : 4;
1199         } FDCRC_b;
1200     };
1201     __IM uint32_t RESERVED[3];
1202 } R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
1203 
1204 /**
1205  * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
1206  */
1207 typedef struct
1208 {
1209     union
1210     {
1211         __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */
1212 
1213         struct
1214         {
1215             __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
1216             __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
1217             __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
1218             __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
1219         } ID_b;
1220     };
1221 
1222     union
1223     {
1224         __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */
1225 
1226         struct
1227         {
1228             __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
1229             __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
1230             __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
1231             __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
1232         } M_b;
1233     };
1234 
1235     union
1236     {
1237         __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */
1238 
1239         struct
1240         {
1241             __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
1242             uint32_t                : 3;
1243             __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
1244             __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
1245                                           *   Pointer                                                                   */
1246             uint32_t               : 2;
1247             __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
1248             __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
1249         } P0_b;
1250     };
1251 
1252     union
1253     {
1254         __IOM uint32_t P1;              /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */
1255 
1256         struct
1257         {
1258             __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer               */
1259             uint32_t               : 23;
1260         } P1_b;
1261     };
1262 } R_CANFD_CFDGAFL_Type;                 /*!< Size = 16 (0x10)                                                          */
1263 
1264 /**
1265  * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
1266  */
1267 typedef struct
1268 {
1269     union
1270     {
1271         __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
1272 
1273         struct
1274         {
1275             __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
1276             __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
1277             uint32_t           : 6;
1278             __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
1279         } ACC0_b;
1280     };
1281 
1282     union
1283     {
1284         __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
1285 
1286         struct
1287         {
1288             __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
1289             __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
1290             uint32_t           : 14;
1291         } ACC1_b;
1292     };
1293 } R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
1294 
1295 /**
1296  * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
1297  */
1298 typedef struct
1299 {
1300     union
1301     {
1302         __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */
1303 
1304         struct
1305         {
1306             __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
1307             uint32_t            : 1;
1308             __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
1309             __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
1310         } ID_b;
1311     };
1312 
1313     union
1314     {
1315         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */
1316 
1317         struct
1318         {
1319             __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
1320             uint32_t            : 12;
1321             __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
1322         } PTR_b;
1323     };
1324 
1325     union
1326     {
1327         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */
1328 
1329         struct
1330         {
1331             __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1332             __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1333             __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1334             uint32_t            : 5;
1335             __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
1336             uint32_t            : 6;
1337             __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
1338         } FDSTS_b;
1339     };
1340 
1341     union
1342     {
1343         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */
1344 
1345         struct
1346         {
1347             __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
1348         } DF_b[64];
1349     };
1350 } R_CANFD_CFDRF_Type;                  /*!< Size = 76 (0x4c)                                                          */
1351 
1352 /**
1353  * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
1354  */
1355 typedef struct
1356 {
1357     union
1358     {
1359         __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
1360 
1361         struct
1362         {
1363             __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
1364             uint32_t             : 1;
1365             __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
1366             __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
1367         } ID_b;
1368     };
1369 
1370     union
1371     {
1372         __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */
1373 
1374         struct
1375         {
1376             __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
1377             uint32_t             : 12;
1378             __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
1379         } PTR_b;
1380     };
1381 
1382     union
1383     {
1384         __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */
1385 
1386         struct
1387         {
1388             __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1389             __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1390             __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1391             uint32_t             : 5;
1392             __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
1393             uint32_t             : 6;
1394             __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
1395         } FDSTS_b;
1396     };
1397 
1398     union
1399     {
1400         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */
1401 
1402         struct
1403         {
1404             __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
1405         } DF_b[64];
1406     };
1407 } R_CANFD_CFDCF_Type;                  /*!< Size = 76 (0x4c)                                                          */
1408 
1409 /**
1410  * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
1411  */
1412 typedef struct
1413 {
1414     union
1415     {
1416         __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */
1417 
1418         struct
1419         {
1420             __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
1421             uint32_t             : 1;
1422             __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
1423             __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
1424         } ID_b;
1425     };
1426 
1427     union
1428     {
1429         __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */
1430 
1431         struct
1432         {
1433             __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
1434             uint32_t             : 12;
1435             __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
1436         } PTR_b;
1437     };
1438 
1439     union
1440     {
1441         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */
1442 
1443         struct
1444         {
1445             __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1446             __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1447             __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1448             uint32_t             : 5;
1449             __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
1450             uint32_t             : 6;
1451             __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
1452         } FDCTR_b;
1453     };
1454 
1455     union
1456     {
1457         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */
1458 
1459         struct
1460         {
1461             __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
1462         } DF_b[64];
1463     };
1464 } R_CANFD_CFDTM_Type;                  /*!< Size = 76 (0x4c)                                                          */
1465 
1466 /**
1467  * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers)
1468  */
1469 typedef struct
1470 {
1471     union
1472     {
1473         __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
1474 
1475         struct
1476         {
1477             __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
1478             uint32_t            : 1;
1479             __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
1480             __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
1481         } ID_b;
1482     };
1483 
1484     union
1485     {
1486         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
1487 
1488         struct
1489         {
1490             __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
1491             uint32_t            : 12;
1492             __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
1493         } PTR_b;
1494     };
1495 
1496     union
1497     {
1498         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
1499 
1500         struct
1501         {
1502             __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1503             __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1504             __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1505             uint32_t            : 5;
1506             __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
1507             uint32_t            : 6;
1508             __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
1509         } FDSTS_b;
1510     };
1511 
1512     union
1513     {
1514         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */
1515 
1516         struct
1517         {
1518             __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
1519         } DF_b[64];
1520     };
1521 } R_CANFD_CFDRM_RM_Type;               /*!< Size = 76 (0x4c)                                                          */
1522 
1523 /**
1524  * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters)
1525  */
1526 typedef struct
1527 {
1528     __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers                         */
1529     __IM uint32_t               RESERVED[104];
1530 } R_CANFD_CFDRM_Type;                  /*!< Size = 1024 (0x400)                                                       */
1531 
1532 /**
1533  * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
1534  */
1535 typedef struct
1536 {
1537     union
1538     {
1539         __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
1540 
1541         struct
1542         {
1543             __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
1544             uint8_t          : 5;
1545             __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
1546             __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
1547         } BY_b;
1548     };
1549     __IM uint8_t RESERVED;
1550 } R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
1551 
1552 /**
1553  * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..30])
1554  */
1555 typedef struct
1556 {
1557     union
1558     {
1559         __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
1560 
1561         struct
1562         {
1563             __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
1564             uint16_t           : 7;
1565         } HA_b;
1566     };
1567     __IM uint16_t RESERVED;
1568 } R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
1569 
1570 /**
1571  * @brief R_GLCDC_BG [BG] (Background Registers)
1572  */
1573 typedef struct
1574 {
1575     union
1576     {
1577         __IOM uint32_t EN;             /*!< (@ 0x00000000) Background Plane Setting Operation Control Register        */
1578 
1579         struct
1580         {
1581             __IOM uint32_t EN  : 1;    /*!< [0..0] Background plane generation module operation enable                */
1582             uint32_t           : 7;
1583             __IOM uint32_t VEN : 1;    /*!< [8..8] Control of LCDC internal register value reflection to
1584                                         *   internal operations                                                       */
1585             uint32_t             : 7;
1586             __IOM uint32_t SWRST : 1;  /*!< [16..16] Entire module SW reset control                                   */
1587             uint32_t             : 15;
1588         } EN_b;
1589     };
1590 
1591     union
1592     {
1593         __IOM uint32_t PERI;           /*!< (@ 0x00000004) Background Plane Setting Free-Running Period
1594                                         *                  Register                                                   */
1595 
1596         struct
1597         {
1598             __IOM uint32_t FH : 11;    /*!< [10..0] Background plane horizontal synchronization signal period
1599                                         *   on the basis of pixel clock (PXCLK).                                      */
1600             uint32_t          : 5;
1601             __IOM uint32_t FV : 11;    /*!< [26..16] Background plane vertical synchronization signal period
1602                                         *   on the basis of line.                                                     */
1603             uint32_t : 5;
1604         } PERI_b;
1605     };
1606 
1607     union
1608     {
1609         __IOM uint32_t SYNC;           /*!< (@ 0x00000008) Background Plane Setting Synchronization Position
1610                                         *                  Register                                                   */
1611 
1612         struct
1613         {
1614             __IOM uint32_t HP : 4;     /*!< [3..0] Background plane horizontal synchronization signal assertion
1615                                         *   position on the basis of pixel clock (PXCLK).                             */
1616             uint32_t          : 12;
1617             __IOM uint32_t VP : 4;     /*!< [19..16] Background plane vertical synchronization signal assertion
1618                                         *   position on the basis of line.                                            */
1619             uint32_t : 12;
1620         } SYNC_b;
1621     };
1622 
1623     union
1624     {
1625         __IOM uint32_t VSIZE;          /*!< (@ 0x0000000C) Background Plane Setting Full Image Vertical
1626                                         *                  Size Register                                              */
1627 
1628         struct
1629         {
1630             __IOM uint32_t VW : 11;    /*!< [10..0] Background plane vertical valid pixel width on the basis
1631                                         *   of line                                                                   */
1632             uint32_t          : 5;
1633             __IOM uint32_t VP : 11;    /*!< [26..16] Background plane vertical valid pixel start position
1634                                         *   on the basis of line                                                      */
1635             uint32_t : 5;
1636         } VSIZE_b;
1637     };
1638 
1639     union
1640     {
1641         __IOM uint32_t HSIZE;          /*!< (@ 0x00000010) Background Plane Setting Full Image Horizontal
1642                                         *                  Size Register                                              */
1643 
1644         struct
1645         {
1646             __IOM uint32_t HW : 11;    /*!< [10..0] Background plane horizontall valid pixel width on the
1647                                         *   basis of pixel clock (PXCLK) Note: When serial RGB is selected
1648                                         *   as the output format for the output control block, add
1649                                         *   two to the horizontal enable signal width and set the resulting
1650                                         *   value to this field.                                                      */
1651             uint32_t          : 5;
1652             __IOM uint32_t HP : 11;    /*!< [26..16] Background plane horizontal valid pixel start position
1653                                         *   on the basis of pixel clock (PXCLK).                                      */
1654             uint32_t : 5;
1655         } HSIZE_b;
1656     };
1657 
1658     union
1659     {
1660         __IOM uint32_t BGC;            /*!< (@ 0x00000014) Background Plane Setting Background Color Register         */
1661 
1662         struct
1663         {
1664             __IOM uint32_t B : 8;      /*!< [7..0] B value for background plane valid pixel area Unsigned;
1665                                         *   8-bit integer                                                             */
1666             __IOM uint32_t G : 8;      /*!< [15..8] G value for background plane valid pixel area Unsigned;
1667                                         *   8-bit integer                                                             */
1668             __IOM uint32_t R : 8;      /*!< [23..16] R value for background plane valid pixel area. Unsigned;
1669                                         *   8-bit integer.                                                            */
1670             uint32_t : 8;
1671         } BGC_b;
1672     };
1673 
1674     union
1675     {
1676         __IM uint32_t MON;             /*!< (@ 0x00000018) Background Plane Setting Status Monitor Register           */
1677 
1678         struct
1679         {
1680             __IM uint32_t EN  : 1;     /*!< [0..0] Background plane generation module operation state monitor.        */
1681             uint32_t          : 7;
1682             __IM uint32_t VEN : 1;     /*!< [8..8] Entire module internal operation reflection control signal
1683                                         *   monitor. The signal state for controlling reflection of
1684                                         *   the register values to the internal operations upon assertion
1685                                         *   of the vertical synchronization signal.                                   */
1686             uint32_t            : 7;
1687             __IM uint32_t SWRST : 1;   /*!< [16..16] Entire module SW reset state monitor.                            */
1688             uint32_t            : 15;
1689         } MON_b;
1690     };
1691 } R_GLCDC_BG_Type;                     /*!< Size = 28 (0x1c)                                                          */
1692 
1693 /**
1694  * @brief R_GLCDC_GR [GR] (Layer Registers)
1695  */
1696 typedef struct
1697 {
1698     union
1699     {
1700         __IOM uint32_t VEN;            /*!< (@ 0x00000000) Graphics Register Update Control Register                  */
1701 
1702         struct
1703         {
1704             __IOM uint32_t PVEN : 1;   /*!< [0..0] Control of graphics n module register value reflection
1705                                         *   to internal operations. Reflection of the register values
1706                                         *   to the internal operation at the assertion of the vertical
1707                                         *   synchronization signal (VS).                                              */
1708             uint32_t : 31;
1709         } VEN_b;
1710     };
1711 
1712     union
1713     {
1714         __IOM uint32_t FLMRD;          /*!< (@ 0x00000004) Graphics Frame Buffer Read Control Register                */
1715 
1716         struct
1717         {
1718             __IOM uint32_t RENB : 1;   /*!< [0..0] Graphics data (frame buffer data) read enable.                     */
1719             uint32_t            : 31;
1720         } FLMRD_b;
1721     };
1722 
1723     union
1724     {
1725         __IM uint32_t FLM1;            /*!< (@ 0x00000008) Graphics Frame Buffer Control Register 1                   */
1726 
1727         struct
1728         {
1729             __IM uint32_t BSTMD : 2;   /*!< [1..0] Burst transfer control for graphics data (frame buffer
1730                                         *   data) access                                                              */
1731             uint32_t : 30;
1732         } FLM1_b;
1733     };
1734 
1735     union
1736     {
1737         __IOM uint32_t FLM2;           /*!< (@ 0x0000000C) Graphics Frame Buffer Control Register 2                   */
1738 
1739         struct
1740         {
1741             __IOM uint32_t BASE : 32;  /*!< [31..0] Base address for accessing graphics data (frame buffer
1742                                         *   data) Set the head address in the frame buffer where graphics
1743                                         *   data is to be stored. GRn_FLM2.BASE[5:0] should be fixed
1744                                         *   to 0 during 64-byte burst transfer.                                       */
1745         } FLM2_b;
1746     };
1747 
1748     union
1749     {
1750         __IOM uint32_t FLM3;           /*!< (@ 0x00000010) Graphics Frame Buffer Control Register 3                   */
1751 
1752         struct
1753         {
1754             uint32_t             : 16;
1755             __IOM uint32_t LNOFF : 16; /*!< [31..16] Macro line offset address for accessing graphics data
1756                                         *   (frame buffer data) Signed; 16-bit integer                                */
1757         } FLM3_b;
1758     };
1759     __IM uint32_t RESERVED;
1760 
1761     union
1762     {
1763         __IOM uint32_t FLM5;             /*!< (@ 0x00000018) Graphics Frame Buffer Control Register 5                   */
1764 
1765         struct
1766         {
1767             __IOM uint32_t DATANUM : 16; /*!< [15..0] Number of data transfer times per line for accessing
1768                                           *   graphics data (frame buffer data), where one transfer is
1769                                           *   defined as 16-beat burst access (64-byte boundary)                        */
1770             __IOM uint32_t LNNUM : 11;   /*!< [26..16] Number of lines per frame for accessing graphics data
1771                                           *   (frame buffer data).                                                      */
1772             uint32_t : 5;
1773         } FLM5_b;
1774     };
1775 
1776     union
1777     {
1778         __IOM uint32_t FLM6;           /*!< (@ 0x0000001C) Graphics Frame Buffer Control Register 6                   */
1779 
1780         struct
1781         {
1782             uint32_t              : 28;
1783             __IOM uint32_t FORMAT : 3; /*!< [30..28] Data format for accessing graphics data (frame buffer
1784                                         *   data).                                                                    */
1785             uint32_t : 1;
1786         } FLM6_b;
1787     };
1788 
1789     union
1790     {
1791         __IOM uint32_t AB1;               /*!< (@ 0x00000020) Graphics Alpha Blending Control Register 1                 */
1792 
1793         struct
1794         {
1795             __IOM uint32_t DISPSEL   : 2; /*!< [1..0] Graphics display plane control.                                    */
1796             uint32_t                 : 2;
1797             __IOM uint32_t GRCDISPON : 1; /*!< [4..4] Graphics image area border display control.                        */
1798             uint32_t                 : 3;
1799             __IOM uint32_t ARCDISPON : 1; /*!< [8..8] Image area border display control for rectangular area
1800                                            *   alpha blending.                                                           */
1801             uint32_t             : 3;
1802             __IOM uint32_t ARCON : 1;     /*!< [12..12] Rectangular area alpha blending control.                         */
1803             uint32_t             : 19;
1804         } AB1_b;
1805     };
1806 
1807     union
1808     {
1809         __IOM uint32_t AB2;            /*!< (@ 0x00000024) Graphics Alpha Blending Control Register 2                 */
1810 
1811         struct
1812         {
1813             __IOM uint32_t GRCVW : 11; /*!< [10..0] Vertical width of graphics image area.                            */
1814             uint32_t             : 5;
1815             __IOM uint32_t GRCVS : 11; /*!< [26..16] Vertical start position of graphics image area.                  */
1816             uint32_t             : 5;
1817         } AB2_b;
1818     };
1819 
1820     union
1821     {
1822         __IOM uint32_t AB3;            /*!< (@ 0x00000028) Graphics Alpha Blending Control Register 3                 */
1823 
1824         struct
1825         {
1826             __IOM uint32_t GRCHW : 11; /*!< [10..0] Horizontal width of graphics image area.                          */
1827             uint32_t             : 5;
1828             __IOM uint32_t GRCHS : 11; /*!< [26..16] Horizontal start position of graphics image area.                */
1829             uint32_t             : 5;
1830         } AB3_b;
1831     };
1832 
1833     union
1834     {
1835         __IOM uint32_t AB4;            /*!< (@ 0x0000002C) Graphics Alpha Blending Control Register 4                 */
1836 
1837         struct
1838         {
1839             __IOM uint32_t ARCVW : 11; /*!< [10..0] Vertical width of rectangular area alpha blending image
1840                                         *   area.                                                                     */
1841             uint32_t             : 5;
1842             __IOM uint32_t ARCVS : 11; /*!< [26..16] Vertical start position of rectangular area alpha blending
1843                                         *   image area                                                                */
1844             uint32_t : 5;
1845         } AB4_b;
1846     };
1847 
1848     union
1849     {
1850         __IOM uint32_t AB5;            /*!< (@ 0x00000030) Graphics Alpha Blending Control Register 5                 */
1851 
1852         struct
1853         {
1854             __IOM uint32_t ARCHW : 11; /*!< [10..0] Horizontal width of rectangular area alpha blending
1855                                         *   image area.                                                               */
1856             uint32_t             : 5;
1857             __IOM uint32_t ARCHS : 11; /*!< [26..16] Horizontal start position of rectangular area alpha
1858                                         *   blending image area.                                                      */
1859             uint32_t : 5;
1860         } AB5_b;
1861     };
1862 
1863     union
1864     {
1865         __IOM uint32_t AB6;             /*!< (@ 0x00000034) Graphics Alpha Blending Control Register 6                 */
1866 
1867         struct
1868         {
1869             __IOM uint32_t ARCRATE : 8; /*!< [7..0] Frame rate for alpha blending in rectangular area.                 */
1870             uint32_t               : 8;
1871             __IOM uint32_t ARCCOEF : 9; /*!< [24..16] Alpha coefficient for alpha blending in rectangular
1872                                          *   area (-255 to 255). [8]: Sign (0: addition, 1: subtraction)
1873                                          *   [7:0]: Variation (absolute value)                                         */
1874             uint32_t : 7;
1875         } AB6_b;
1876     };
1877 
1878     union
1879     {
1880         __IOM uint32_t AB7;            /*!< (@ 0x00000038) Graphics Alpha Blending Control Register 7                 */
1881 
1882         struct
1883         {
1884             __IOM uint32_t CKON   : 1; /*!< [0..0] RGB-index chroma-key processing control.                           */
1885             uint32_t              : 15;
1886             __IOM uint32_t ARCDEF : 8; /*!< [23..16] Initial alpha value for alpha blending in rectangular
1887                                         *   area.                                                                     */
1888             uint32_t : 8;
1889         } AB7_b;
1890     };
1891 
1892     union
1893     {
1894         __IOM uint32_t AB8;            /*!< (@ 0x0000003C) Graphics Alpha Blending Control Register 8                 */
1895 
1896         struct
1897         {
1898             __IOM uint32_t CKKR : 8;   /*!< [7..0] R signal for RGB-index chroma-key processing Unsigned;
1899                                         *   8 bits.                                                                   */
1900             __IOM uint32_t CKKB : 8;   /*!< [15..8] B signal for RGB-index chroma-key processing Unsigned;
1901                                         *   8 bits.                                                                   */
1902             __IOM uint32_t CKKG : 8;   /*!< [23..16] G signal for RGB-index chroma-key processing Unsigned;
1903                                         *   8 bits.                                                                   */
1904             uint32_t : 8;
1905         } AB8_b;
1906     };
1907 
1908     union
1909     {
1910         __IOM uint32_t AB9;            /*!< (@ 0x00000040) Graphics Alpha Blending Control Register 9                 */
1911 
1912         struct
1913         {
1914             __IOM uint32_t CKR : 8;    /*!< [7..0] R value after RGB-index chroma-key processing replacement
1915                                         *   Unsigned; 8 bits.                                                         */
1916             __IOM uint32_t CKB : 8;    /*!< [15..8] B value after RGB-index chroma-key processing replacement
1917                                         *   Unsigned; 8 bits.                                                         */
1918             __IOM uint32_t CKG : 8;    /*!< [23..16] G value after RGB-index chroma-key processing replacement
1919                                         *   Unsigned; 8 bits.                                                         */
1920             __IOM uint32_t CKA : 8;    /*!< [31..24] A value after RGB-index chroma-key processing replacement.       */
1921         } AB9_b;
1922     };
1923     __IM uint32_t RESERVED1[2];
1924 
1925     union
1926     {
1927         __IOM uint32_t BASE;           /*!< (@ 0x0000004C) Graphics Background Color Control Register                 */
1928 
1929         struct
1930         {
1931             __IOM uint32_t R : 8;      /*!< [7..0] Background color R value Unsigned; 8 bits                          */
1932             __IOM uint32_t B : 8;      /*!< [15..8] Background color B value Unsigned; 8 bits                         */
1933             __IOM uint32_t G : 8;      /*!< [23..16] Background color G value Unsigned; 8 bits                        */
1934             uint32_t         : 8;
1935         } BASE_b;
1936     };
1937 
1938     union
1939     {
1940         __IOM uint32_t CLUTINT;        /*!< (@ 0x00000050) Graphics CLUT Table Interrupt Control Register             */
1941 
1942         struct
1943         {
1944             __IOM uint32_t LINE : 11;  /*!< [10..0] Number of detection lines                                         */
1945             uint32_t            : 5;
1946             __IOM uint32_t SEL  : 1;   /*!< [16..16] CLUT table control                                               */
1947             uint32_t            : 15;
1948         } CLUTINT_b;
1949     };
1950 
1951     union
1952     {
1953         __IM uint32_t MON;             /*!< (@ 0x00000054) Graphics Status Monitor Register                           */
1954 
1955         struct
1956         {
1957             __IM uint32_t ARCST   : 1; /*!< [0..0] Status monitor for alpha blending in rectangular area              */
1958             uint32_t              : 15;
1959             __IM uint32_t UNDFLST : 1; /*!< [16..16] Status monitor for underflow                                     */
1960             uint32_t              : 15;
1961         } MON_b;
1962     };
1963     __IM uint32_t RESERVED2[42];
1964 } R_GLCDC_GR_Type;                     /*!< Size = 256 (0x100)                                                        */
1965 
1966 /**
1967  * @brief R_GLCDC_GAM [GAM] (Gamma Settings)
1968  */
1969 typedef struct
1970 {
1971     union
1972     {
1973         __IOM uint32_t LATCH;          /*!< (@ 0x00000000) Gamma Register Update Control Register                     */
1974 
1975         struct
1976         {
1977             __IOM uint32_t VEN : 1;    /*!< [0..0] Control of gamma correction x module register value reflection
1978                                         *   to internal operations. The register values to be reflected
1979                                         *   to the internal operations at the assertion of the vertical
1980                                         *   synchronization signal (VS).                                              */
1981             uint32_t : 31;
1982         } LATCH_b;
1983     };
1984 
1985     union
1986     {
1987         __IOM uint32_t GAM_SW;         /*!< (@ 0x00000004) Gamma Correction Block Function Switch Register            */
1988 
1989         struct
1990         {
1991             __IOM uint32_t GAMON : 1;  /*!< [0..0] Gamma correction on/off control                                    */
1992             uint32_t             : 31;
1993         } GAM_SW_b;
1994     };
1995 
1996     union
1997     {
1998         __IOM uint32_t LUT[8];         /*!< (@ 0x00000008) Gamma Correction Block Table Setting Register              */
1999 
2000         struct
2001         {
2002             __IOM uint32_t _HIGH : 11; /*!< [10..0] Gain value of area 0. Unsigned 11-bit fixed point.                */
2003             uint32_t             : 5;
2004             __IOM uint32_t _LOW  : 11; /*!< [26..16] Gain value of area 0. Unsigned 11-bit fixed point.               */
2005             uint32_t             : 5;
2006         } LUT_b[8];
2007     };
2008 
2009     union
2010     {
2011         __IOM uint32_t AREA[5];        /*!< (@ 0x00000028) Gamma Correction Block Area Setting Register               */
2012 
2013         struct
2014         {
2015             __IOM uint32_t _HIGH : 10; /*!< [9..0] Start threshold of area 1 Unsigned 10-bit integer                  */
2016             __IOM uint32_t _MID  : 10; /*!< [19..10] Start threshold of area 1 Unsigned 10-bit integer                */
2017             __IOM uint32_t _LOW  : 10; /*!< [29..20] Start threshold of area 1 Unsigned 10-bit integer                */
2018             uint32_t             : 2;
2019         } AREA_b[5];
2020     };
2021     __IM uint32_t RESERVED;
2022 } R_GLCDC_GAM_Type;                    /*!< Size = 64 (0x40)                                                          */
2023 
2024 /**
2025  * @brief R_GLCDC_OUT [OUT] (Output Control Registers)
2026  */
2027 typedef struct
2028 {
2029     union
2030     {
2031         __IOM uint32_t VLATCH;         /*!< (@ 0x00000000) Output Control Block Register Update Control
2032                                         *                  Register                                                   */
2033 
2034         struct
2035         {
2036             __IOM uint32_t VEN : 1;    /*!< [0..0] Control of output control module register value reflection
2037                                         *   to internal operations. The register values to be reflected
2038                                         *   to the internal operations at the assertion of the vertical
2039                                         *   synchronization signal (VS).                                              */
2040             uint32_t : 31;
2041         } VLATCH_b;
2042     };
2043 
2044     union
2045     {
2046         __IOM uint32_t SET;              /*!< (@ 0x00000004) Output Control Block Output Interface Register             */
2047 
2048         struct
2049         {
2050             __IOM uint32_t PHASE    : 2; /*!< [1..0] Data delay in serial RGB format (based on OUTCLK)                  */
2051             uint32_t                : 2;
2052             __IOM uint32_t DIRSEL   : 1; /*!< [4..4] Invalid data position control in serial RGB format                 */
2053             uint32_t                : 3;
2054             __IOM uint32_t FRQSEL   : 2; /*!< [9..8] Clock frequency division control                                   */
2055             uint32_t                : 2;
2056             __IOM uint32_t FORMAT   : 2; /*!< [13..12] Output format select                                             */
2057             uint32_t                : 10;
2058             __IOM uint32_t SWAPON   : 1; /*!< [24..24] Pixel order control                                              */
2059             uint32_t                : 3;
2060             __IOM uint32_t ENDIANON : 1; /*!< [28..28] Bit endian change control                                        */
2061             uint32_t                : 3;
2062         } SET_b;
2063     };
2064 
2065     union
2066     {
2067         __IOM uint32_t BRIGHT1;        /*!< (@ 0x00000008) Output Control Block Brightness Correction Register
2068                                         *                  1                                                          */
2069 
2070         struct
2071         {
2072             __IOM uint32_t BRTG : 10;  /*!< [9..0] Brightness (DC) adjustment of G signal Unsigned; 10 bits;
2073                                         +512 with offset; integer                                                 */
2074             uint32_t : 22;
2075         } BRIGHT1_b;
2076     };
2077 
2078     union
2079     {
2080         __IOM uint32_t BRIGHT2;        /*!< (@ 0x0000000C) Output Control Block Brightness Correction Register
2081                                         *                  2                                                          */
2082 
2083         struct
2084         {
2085             __IOM uint32_t BRTR : 10;  /*!< [9..0] Brightness (DC) adjustment of R signal Unsigned; 10 bits;
2086                                         +512 with offset; integer                                                 */
2087             uint32_t            : 6;
2088             __IOM uint32_t BRTB : 10;  /*!< [25..16] Brightness (DC) adjustment of B signal Unsigned; 10
2089                                         *   bits; +512 with offset; integer                                           */
2090             uint32_t : 6;
2091         } BRIGHT2_b;
2092     };
2093 
2094     union
2095     {
2096         __IOM uint32_t CONTRAST;       /*!< (@ 0x00000010) Output Control Block Contrast Correction Register          */
2097 
2098         struct
2099         {
2100             __IOM uint32_t CONTR : 8;  /*!< [7..0] Contrast (GAIN) adjustment of R signal Unsigned; 8 bits
2101                                         *   fixed point                                                               */
2102             __IOM uint32_t CONTB : 8;  /*!< [15..8] Contrast (GAIN) adjustment of B signal Unsigned; 8 bits
2103                                         *   fixed point                                                               */
2104             __IOM uint32_t CONTG : 8;  /*!< [23..16] Contrast (GAIN) adjustment of G signal Unsigned; 8
2105                                         *   bits fixed point.                                                         */
2106             uint32_t : 8;
2107         } CONTRAST_b;
2108     };
2109 
2110     union
2111     {
2112         __IOM uint32_t PDTHA;          /*!< (@ 0x00000014) Output Control Block Panel Dither Correction
2113                                         *                  Register                                                   */
2114 
2115         struct
2116         {
2117             __IOM uint32_t PD : 2;     /*!< [1..0] Pattern value (D) of 2 x 2 pattern dither Unsigned 2-bit
2118                                         *   integer                                                                   */
2119             uint32_t          : 2;
2120             __IOM uint32_t PC : 2;     /*!< [5..4] Pattern value (C) of 2 x 2 pattern dither Unsigned 2-bit
2121                                         *   integer                                                                   */
2122             uint32_t          : 2;
2123             __IOM uint32_t PB : 2;     /*!< [9..8] Pattern value (B) of 2 x 2 pattern dither Unsigned 2-bit
2124                                         *   integer                                                                   */
2125             uint32_t          : 2;
2126             __IOM uint32_t PA : 2;     /*!< [13..12] Pattern value (A) of 2 x 2 pattern dither Unsigned
2127                                         *   2-bit integer                                                             */
2128             uint32_t            : 2;
2129             __IOM uint32_t FORM : 2;   /*!< [17..16] Output format select                                             */
2130             uint32_t            : 2;
2131             __IOM uint32_t SEL  : 2;   /*!< [21..20] Operation mode                                                   */
2132             uint32_t            : 10;
2133         } PDTHA_b;
2134     };
2135     __IM uint32_t RESERVED[3];
2136 
2137     union
2138     {
2139         __IOM uint32_t CLKPHASE;       /*!< (@ 0x00000024) Output Control Block Output Phase Control Register         */
2140 
2141         struct
2142         {
2143             uint32_t                 : 3;
2144             __IOM uint32_t TCON3EDGE : 1; /*!< [3..3] LCD_TCON3 Output Phase Control                                     */
2145             __IOM uint32_t TCON2EDGE : 1; /*!< [4..4] LCD_TCON2 Output Phase Control                                     */
2146             __IOM uint32_t TCON1EDGE : 1; /*!< [5..5] LCD_TCON1 Output Phase Control                                     */
2147             __IOM uint32_t TCON0EDGE : 1; /*!< [6..6] LCD_TCON0 Output Phase Control                                     */
2148             uint32_t                 : 1;
2149             __IOM uint32_t LCDEDGE   : 1; /*!< [8..8] LCD_DATA Output Phase Control                                      */
2150             uint32_t                 : 3;
2151             __IOM uint32_t FRONTGAM  : 1; /*!< [12..12] Correction control                                               */
2152             uint32_t                 : 19;
2153         } CLKPHASE_b;
2154     };
2155 } R_GLCDC_OUT_Type;                       /*!< Size = 40 (0x28)                                                          */
2156 
2157 /**
2158  * @brief R_GLCDC_TCON [TCON] (Timing Control Registers)
2159  */
2160 typedef struct
2161 {
2162     __IM uint32_t RESERVED;
2163 
2164     union
2165     {
2166         __IOM uint32_t TIM;             /*!< (@ 0x00000004) TCON Reference Timing Setting Register                     */
2167 
2168         struct
2169         {
2170             __IOM uint32_t OFFSET : 11; /*!< [10..0] Horizontal synchronization signal generation reference
2171                                          *   timing Sets the offset from the assertion of the internal
2172                                          *   horizontal synchronization signal in terms of pixels.                     */
2173             uint32_t            : 5;
2174             __IOM uint32_t HALF : 11;   /*!< [26..16] Vertical synchronization signal generation change timing
2175                                          *   Sets the delay from the assertion of the internal horizontal
2176                                          *   synchronization signal in terms of pixels.                                */
2177             uint32_t : 5;
2178         } TIM_b;
2179     };
2180 
2181     union
2182     {
2183         __IOM uint32_t STVA1;          /*!< (@ 0x00000008) TCON Vertical Timing Setting Register A1                   */
2184 
2185         struct
2186         {
2187             __IOM uint32_t VW : 11;    /*!< [10..0] STVx1 second change timing Sets the signal assertion
2188                                         *   width.                                                                    */
2189             uint32_t          : 5;
2190             __IOM uint32_t VS : 11;    /*!< [26..16] STVx1 first change timing                                        */
2191             uint32_t          : 5;
2192         } STVA1_b;
2193     };
2194 
2195     union
2196     {
2197         __IOM uint32_t STVA2;          /*!< (@ 0x0000000C) TCON Vertical Timing Setting Register A2                   */
2198 
2199         struct
2200         {
2201             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for VSOUT (controlled by
2202                                         *   TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
2203                                         *   register) pin                                                             */
2204             uint32_t           : 1;
2205             __IOM uint32_t INV : 1;    /*!< [4..4] STVx signal polarity inversion control                             */
2206             uint32_t           : 27;
2207         } STVA2_b;
2208     };
2209 
2210     union
2211     {
2212         __IOM uint32_t STVB1;          /*!< (@ 0x00000010) TCON Vertical Timing Setting Register B1                   */
2213 
2214         struct
2215         {
2216             __IOM uint32_t VW : 11;    /*!< [10..0] STVx1 second change timing Sets the signal assertion
2217                                         *   width.                                                                    */
2218             uint32_t          : 5;
2219             __IOM uint32_t VS : 11;    /*!< [26..16] STVx1 first change timing                                        */
2220             uint32_t          : 5;
2221         } STVB1_b;
2222     };
2223 
2224     union
2225     {
2226         __IOM uint32_t STVB2;          /*!< (@ 0x00000014) TCON Vertical Timing Setting Register B2                   */
2227 
2228         struct
2229         {
2230             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for VSOUT (controlled by
2231                                         *   TCON_STVA2 register)/VEOUT (controlled by the TCON_STVB2
2232                                         *   register) pin                                                             */
2233             uint32_t           : 1;
2234             __IOM uint32_t INV : 1;    /*!< [4..4] STVx signal polarity inversion control                             */
2235             uint32_t           : 27;
2236         } STVB2_b;
2237     };
2238 
2239     union
2240     {
2241         __IOM uint32_t STHA1;          /*!< (@ 0x00000018) TCON Horizontal Timing Setting Register STHA1              */
2242 
2243         struct
2244         {
2245             __IOM uint32_t HW : 11;    /*!< [10..0] STHx1 second change timing. Sets the signal assertion
2246                                         *   width.                                                                    */
2247             uint32_t          : 5;
2248             __IOM uint32_t HS : 11;    /*!< [26..16] STHx1 first change timing                                        */
2249             uint32_t          : 5;
2250         } STHA1_b;
2251     };
2252 
2253     union
2254     {
2255         __IOM uint32_t STHA2;          /*!< (@ 0x0000001C) TCON Horizontal Timing Setting Register STHA2              */
2256 
2257         struct
2258         {
2259             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
2260                                         *   by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
2261                                         *   register) pin.                                                            */
2262             uint32_t             : 1;
2263             __IOM uint32_t INV   : 1;  /*!< [4..4] STVx signal polarity inversion control.                            */
2264             uint32_t             : 3;
2265             __IOM uint32_t HSSEL : 1;  /*!< [8..8] STHx signal generation reference timing control.                   */
2266             uint32_t             : 23;
2267         } STHA2_b;
2268     };
2269 
2270     union
2271     {
2272         __IOM uint32_t STHB1;          /*!< (@ 0x00000020) TCON Horizontal Timing Setting Register STHB1              */
2273 
2274         struct
2275         {
2276             __IOM uint32_t HW : 11;    /*!< [10..0] STHx1 second change timing. Sets the signal assertion
2277                                         *   width.                                                                    */
2278             uint32_t          : 5;
2279             __IOM uint32_t HS : 11;    /*!< [26..16] STHx1 first change timing                                        */
2280             uint32_t          : 5;
2281         } STHB1_b;
2282     };
2283 
2284     union
2285     {
2286         __IOM uint32_t STHB2;          /*!< (@ 0x00000024) TCON Horizontal Timing Setting Register STHB2              */
2287 
2288         struct
2289         {
2290             __IOM uint32_t SEL : 3;    /*!< [2..0] Output signal select control for LCD_TCON2 (controlled
2291                                         *   by TCON_STHA2 register)/LCD_TCON3 (controlled by the TCON_STHB2
2292                                         *   register) pin.                                                            */
2293             uint32_t             : 1;
2294             __IOM uint32_t INV   : 1;  /*!< [4..4] STVx signal polarity inversion control.                            */
2295             uint32_t             : 3;
2296             __IOM uint32_t HSSEL : 1;  /*!< [8..8] STHx signal generation reference timing control.                   */
2297             uint32_t             : 23;
2298         } STHB2_b;
2299     };
2300 
2301     union
2302     {
2303         __IOM uint32_t DE;             /*!< (@ 0x00000028) TCON Data Enable Polarity Setting Register                 */
2304 
2305         struct
2306         {
2307             __IOM uint32_t INV : 1;    /*!< [0..0] DE signal polarity inversion control.                              */
2308             uint32_t           : 31;
2309         } DE_b;
2310     };
2311 } R_GLCDC_TCON_Type;                   /*!< Size = 44 (0x2c)                                                          */
2312 
2313 /**
2314  * @brief R_GLCDC_SYSCNT [SYSCNT] (GLCDC System Control Registers)
2315  */
2316 typedef struct
2317 {
2318     union
2319     {
2320         __IOM uint32_t DTCTEN;            /*!< (@ 0x00000000) System control block State Detection Control
2321                                            *                  Register                                                   */
2322 
2323         struct
2324         {
2325             __IOM uint32_t VPOSDTC   : 1; /*!< [0..0] Specified line detection control                                   */
2326             __IOM uint32_t L1UNDFDTC : 1; /*!< [1..1] Graphics 1 underflow detection control                             */
2327             __IOM uint32_t L2UNDFDTC : 1; /*!< [2..2] Graphics 2 underflow detection control                             */
2328             uint32_t                 : 29;
2329         } DTCTEN_b;
2330     };
2331 
2332     union
2333     {
2334         __IOM uint32_t INTEN;               /*!< (@ 0x00000004) System control block Interrupt Request Enable
2335                                              *                  Control Register                                           */
2336 
2337         struct
2338         {
2339             __IOM uint32_t VPOSINTEN   : 1; /*!< [0..0] Interrupt request signal GLCDC_VPOS enable control.                */
2340             __IOM uint32_t L1UNDFINTEN : 1; /*!< [1..1] Interrupt request signal GLCDC_L1UNDF enable control.              */
2341             __IOM uint32_t L2UNDFINTEN : 1; /*!< [2..2] Interrupt request signal GLCDC_L2UNDF enable control.              */
2342             uint32_t                   : 29;
2343         } INTEN_b;
2344     };
2345 
2346     union
2347     {
2348         __IOM uint32_t STCLR;             /*!< (@ 0x00000008) System control block Status Clear Register                 */
2349 
2350         struct
2351         {
2352             __IOM uint32_t VPOSCLR   : 1; /*!< [0..0] Graphics 2 specified line detection flag clear field               */
2353             __IOM uint32_t L1UNDFCLR : 1; /*!< [1..1] Graphics 1 underflow detection flag clear field                    */
2354             __IOM uint32_t L2UNDFCLR : 1; /*!< [2..2] Graphics 2 underflow detection flag clear field                    */
2355             uint32_t                 : 29;
2356         } STCLR_b;
2357     };
2358 
2359     union
2360     {
2361         __IM uint32_t STMON;           /*!< (@ 0x0000000C) System control block Status Monitor Register               */
2362 
2363         struct
2364         {
2365             __IM uint32_t VPOS   : 1;  /*!< [0..0] Graphics 2 specified line detection flag                           */
2366             __IM uint32_t L1UNDF : 1;  /*!< [1..1] Graphics 1 underflow detection flag                                */
2367             __IM uint32_t L2UNDF : 1;  /*!< [2..2] Graphics 2 underflow detection flag                                */
2368             uint32_t             : 29;
2369         } STMON_b;
2370     };
2371 
2372     union
2373     {
2374         __IOM uint32_t PANEL_CLK;      /*!< (@ 0x00000010) System control block Version and Panel Clock
2375                                         *                  Control Register                                           */
2376 
2377         struct
2378         {
2379             __IOM uint32_t DCDR : 6;   /*!< [5..0] Clock division ratio setting control Refer toTable 2.7.1
2380                                         *   for details about setting value. Note: Settings that are
2381                                         *   not listed in table 2.7.1 are prohibited.                                 */
2382             __IOM uint32_t CLKEN : 1;  /*!< [6..6] Panel clock output enable control Note: Before changing
2383                                         *   the PIXSEL,CLKSEL or DCDR bit, this bit must be set to
2384                                         *   0.                                                                        */
2385             uint32_t              : 1;
2386             __IOM uint32_t CLKSEL : 1; /*!< [8..8] Panel clock supply source select                                   */
2387             uint32_t              : 3;
2388             __IOM uint32_t PIXSEL : 1; /*!< [12..12] Pixel clock select control. Must be set to the same
2389                                         *   value as OUT_SET.FRQSEL[1].                                               */
2390             uint32_t          : 3;
2391             __IM uint32_t VER : 16;    /*!< [31..16] Version information Version information of the GLCDC             */
2392         } PANEL_CLK_b;
2393     };
2394 } R_GLCDC_SYSCNT_Type;                 /*!< Size = 20 (0x14)                                                          */
2395 
2396 /**
2397  * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
2398  */
2399 typedef struct
2400 {
2401     union
2402     {
2403         __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
2404 
2405         struct
2406         {
2407             __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
2408                                         *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
2409         } L_b;
2410     };
2411 
2412     union
2413     {
2414         __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
2415 
2416         struct
2417         {
2418             __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
2419             __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
2420             __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
2421             uint8_t            : 5;
2422         } U_b;
2423     };
2424 } R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
2425 
2426 /**
2427  * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control)
2428  */
2429 typedef struct
2430 {
2431     union
2432     {
2433         __IOM uint16_t AC;             /*!< (@ 0x00000000) Access Control Register                                    */
2434 
2435         struct
2436         {
2437             __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
2438             __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
2439             __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
2440             __IOM uint16_t PP     : 1; /*!< [3..3] Privilege protection                                               */
2441             uint16_t              : 12;
2442         } AC_b;
2443     };
2444     __IM uint16_t RESERVED;
2445 
2446     union
2447     {
2448         __IOM uint32_t S;              /*!< (@ 0x00000004) Start Address Register                                     */
2449 
2450         struct
2451         {
2452             __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination.
2453                                         *   NOTE: Some low-order bits are fixed to 0.                                 */
2454         } S_b;
2455     };
2456 
2457     union
2458     {
2459         __IOM uint32_t E;              /*!< (@ 0x00000008) End Address Register                                       */
2460 
2461         struct
2462         {
2463             __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region
2464                                         *   end, for use in region determination. NOTE: Some low-order
2465                                         *   bits are fixed to 1.                                                      */
2466         } E_b;
2467     };
2468     __IM uint32_t RESERVED1;
2469 } R_MPU_MMPU_GROUP_REGION_Type;        /*!< Size = 16 (0x10)                                                          */
2470 
2471 /**
2472  * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers)
2473  */
2474 typedef struct
2475 {
2476     union
2477     {
2478         __IOM uint16_t EN;             /*!< (@ 0x00000000) MMPU enable register                                       */
2479 
2480         struct
2481         {
2482             __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable                                      */
2483             uint16_t              : 7;
2484             __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2485                                         *   stored.                                                                   */
2486         } EN_b;
2487     };
2488     __IM uint16_t RESERVED;
2489 
2490     union
2491     {
2492         __IOM uint16_t ENPT;            /*!< (@ 0x00000004) MMPU enable protect register                               */
2493 
2494         struct
2495         {
2496             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN                                          */
2497             uint16_t               : 7;
2498             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2499                                          *   stored.                                                                   */
2500         } ENPT_b;
2501     };
2502     __IM uint16_t RESERVED1;
2503 
2504     union
2505     {
2506         __IOM uint16_t RPT;             /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure                   */
2507 
2508         struct
2509         {
2510             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
2511             uint16_t               : 7;
2512             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2513                                          *   stored.                                                                   */
2514         } RPT_b;
2515     };
2516     __IM uint16_t RESERVED2;
2517 
2518     union
2519     {
2520         __IOM uint16_t RPT_SEC;         /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only)           */
2521 
2522         struct
2523         {
2524             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
2525             uint16_t               : 7;
2526             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2527                                          *   stored.                                                                   */
2528         } RPT_SEC_b;
2529     };
2530     __IM uint16_t RESERVED3;
2531     __IM uint32_t RESERVED4[60];
2532     __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control                                     */
2533     __IM uint32_t RESERVED5[32];
2534 } R_MPU_MMPU_GROUP_Type;                          /*!< Size = 512 (0x200)                                                        */
2535 
2536 /**
2537  * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
2538  */
2539 typedef struct
2540 {
2541     union
2542     {
2543         __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
2544                                         *                  Register                                                   */
2545 
2546         struct
2547         {
2548             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
2549             uint16_t           : 7;
2550             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
2551                                         *   stored.                                                                   */
2552         } OAD_b;
2553     };
2554     __IM uint16_t RESERVED;
2555 
2556     union
2557     {
2558         __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
2559 
2560         struct
2561         {
2562             __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
2563             uint16_t              : 7;
2564             __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
2565             uint16_t              : 7;
2566         } CTL_b;
2567     };
2568 
2569     union
2570     {
2571         __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
2572 
2573         struct
2574         {
2575             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
2576             uint16_t               : 7;
2577             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
2578                                          *   stored.                                                                   */
2579         } PT_b;
2580     };
2581 
2582     union
2583     {
2584         __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
2585 
2586         struct
2587         {
2588             __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
2589                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
2590                                            *   The low-order 2 bits are fixed to 0.                                      */
2591         } SA_b;
2592     };
2593 
2594     union
2595     {
2596         __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
2597 
2598         struct
2599         {
2600             __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
2601                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
2602                                            *   The low-order 2 bits are fixed to 1.                                      */
2603         } EA_b;
2604     };
2605 } R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
2606 
2607 /**
2608  * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
2609  */
2610 typedef struct
2611 {
2612     union
2613     {
2614         union
2615         {
2616             __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
2617 
2618             struct
2619             {
2620                 __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2621                 __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2622                 __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2623                 uint32_t             : 1;
2624                 __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
2625                 uint32_t             : 1;
2626                 __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
2627                 uint32_t             : 3;
2628                 __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
2629                 __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Event on Rising.                                */
2630                 __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
2631                 __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
2632                 __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
2633                 uint32_t             : 7;
2634                 __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
2635                                            *   function. For individual pin functions, see the MPC table                 */
2636                 uint32_t : 3;
2637             } PmnPFS_b;
2638         };
2639 
2640         union
2641         {
2642             __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000000) Pin Function Control Register                              */
2643 
2644             struct
2645             {
2646                 __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2647                 __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2648                 __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2649                 uint16_t             : 1;
2650                 __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
2651                 uint16_t             : 1;
2652                 __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
2653                 uint16_t             : 3;
2654                 __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
2655                 __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Event on Rising.                                */
2656                 __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
2657                 __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
2658             } PmnPFS_HA_b;
2659         };
2660 
2661         union
2662         {
2663             __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000000) Pin Function Control Register                              */
2664 
2665             struct
2666             {
2667                 __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
2668                 __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
2669                 __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
2670                 uint8_t             : 1;
2671                 __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
2672                 uint8_t             : 1;
2673                 __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
2674                 uint8_t             : 1;
2675             } PmnPFS_BY_b;
2676         };
2677     };
2678 } R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
2679 
2680 /**
2681  * @brief R_PFS_PORT [PORT] (Port [0..14])
2682  */
2683 typedef struct
2684 {
2685     __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
2686 } R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
2687 
2688 /**
2689  * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
2690  */
2691 typedef struct
2692 {
2693     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
2694     __IM uint16_t  RESERVED;
2695 } R_PMISC_PMSAR_Type;                  /*!< Size = 4 (0x4)                                                            */
2696 
2697 /**
2698  * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
2699  */
2700 typedef struct
2701 {
2702     union
2703     {
2704         __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
2705 
2706         struct
2707         {
2708             __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
2709             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
2710             uint8_t            : 1;
2711             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
2712             uint8_t            : 1;
2713             __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
2714         } RTCCR_b;
2715     };
2716     __IM uint8_t RESERVED;
2717 } R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
2718 
2719 /**
2720  * @brief R_RTC_CP [CP] (Capture registers)
2721  */
2722 typedef struct
2723 {
2724     __IM uint8_t RESERVED[2];
2725 
2726     union
2727     {
2728         union
2729         {
2730             __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
2731 
2732             struct
2733             {
2734                 __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
2735                                          *   seconds                                                                   */
2736                 __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
2737                                          *   seconds                                                                   */
2738                 uint8_t : 1;
2739             } RSEC_b;
2740         };
2741 
2742         union
2743         {
2744             __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
2745 
2746             struct
2747             {
2748                 __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
2749                                            *   value when a time capture event is detected.                              */
2750             } BCNT0_b;
2751         };
2752     };
2753     __IM uint8_t RESERVED1;
2754 
2755     union
2756     {
2757         union
2758         {
2759             __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
2760 
2761             struct
2762             {
2763                 __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
2764                                          *   minutes                                                                   */
2765                 __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
2766                                          *   minutes                                                                   */
2767                 uint8_t : 1;
2768             } RMIN_b;
2769         };
2770 
2771         union
2772         {
2773             __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
2774 
2775             struct
2776             {
2777                 __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
2778                                            *   value when a time capture event is detected.                              */
2779             } BCNT1_b;
2780         };
2781     };
2782     __IM uint8_t RESERVED2;
2783 
2784     union
2785     {
2786         union
2787         {
2788             __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
2789 
2790             struct
2791             {
2792                 __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
2793                                         *   minutes                                                                   */
2794                 __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
2795                                         *   minutes                                                                   */
2796                 __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
2797                 uint8_t         : 1;
2798             } RHR_b;
2799         };
2800 
2801         union
2802         {
2803             __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
2804 
2805             struct
2806             {
2807                 __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
2808                                            *   value when a time capture event is detected.                              */
2809             } BCNT2_b;
2810         };
2811     };
2812     __IM uint8_t RESERVED3[3];
2813 
2814     union
2815     {
2816         union
2817         {
2818             __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
2819 
2820             struct
2821             {
2822                 __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
2823                 __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
2824                 uint8_t             : 2;
2825             } RDAY_b;
2826         };
2827 
2828         union
2829         {
2830             __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
2831 
2832             struct
2833             {
2834                 __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
2835                                            *   value when a time capture event is detected.                              */
2836             } BCNT3_b;
2837         };
2838     };
2839     __IM uint8_t RESERVED4;
2840 
2841     union
2842     {
2843         __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
2844 
2845         struct
2846         {
2847             __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
2848             __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
2849                                         *   months                                                                    */
2850             uint8_t : 3;
2851         } RMON_b;
2852     };
2853     __IM uint8_t RESERVED5[3];
2854 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
2855 
2856 /**
2857  * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
2858  */
2859 typedef struct
2860 {
2861     union
2862     {
2863         __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
2864 
2865         struct
2866         {
2867             uint16_t             : 8;
2868             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
2869             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
2870             uint16_t             : 6;
2871         } E_b;
2872     };
2873 
2874     union
2875     {
2876         __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
2877 
2878         struct
2879         {
2880             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
2881         } N_b;
2882     };
2883 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
2884 
2885 /**
2886  * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
2887  */
2888 typedef struct
2889 {
2890     union
2891     {
2892         __IOM uint16_t E;              /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register                   */
2893 
2894         struct
2895         {
2896             uint16_t             : 8;
2897             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows
2898                                         *   clearing the transaction counter to 0.                                    */
2899             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter EnableEnables or disables the transaction
2900                                         *   counter function.                                                         */
2901             uint16_t : 6;
2902         } E_b;
2903     };
2904 
2905     union
2906     {
2907         __IOM uint16_t N;               /*!< (@ 0x00000002) PIPE Transaction Counter Register                          */
2908 
2909         struct
2910         {
2911             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number
2912                                          *   of total packets (number of transactions) to be received
2913                                          *   by the relevant PIPE.When read from: When TRENB = 0: Indicate
2914                                          *   the specified number of transactions.When TRENB = 1: Indicate
2915                                          *   the number of currently counted transactions.                             */
2916         } N_b;
2917     };
2918 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
2919 
2920 /**
2921  * @brief R_XSPI_CMCFGCS [CMCFGCS] (xSPI Command Map Configuration registers)
2922  */
2923 typedef struct
2924 {
2925     union
2926     {
2927         __IOM uint32_t CMCFG0;          /*!< (@ 0x00000000) xSPI Command Map Configuration register 0                  */
2928 
2929         struct
2930         {
2931             __IOM uint32_t FFMT    : 2; /*!< [1..0] Frame format                                                       */
2932             __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size                                                       */
2933             __IOM uint32_t WPBSTMD : 1; /*!< [4..4] Wrapping burst mode                                                */
2934             __IOM uint32_t ARYAMD  : 1; /*!< [5..5] Array address mode                                                 */
2935             uint32_t               : 10;
2936             __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable                                           */
2937             __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code                                             */
2938         } CMCFG0_b;
2939     };
2940 
2941     union
2942     {
2943         __IOM uint32_t CMCFG1;          /*!< (@ 0x00000004) xSPI Command Map Configuration register 1                  */
2944 
2945         struct
2946         {
2947             __IOM uint32_t RDCMD  : 16; /*!< [15..0] Read command                                                      */
2948             __IOM uint32_t RDLATE : 5;  /*!< [20..16] Read latency cycle                                               */
2949             uint32_t              : 11;
2950         } CMCFG1_b;
2951     };
2952 
2953     union
2954     {
2955         __IOM uint32_t CMCFG2;          /*!< (@ 0x00000008) xSPI Command Map Configuration register 2                  */
2956 
2957         struct
2958         {
2959             __IOM uint32_t WRCMD  : 16; /*!< [15..0] Write command                                                     */
2960             __IOM uint32_t WRLATE : 5;  /*!< [20..16] Write latency cycle                                              */
2961             uint32_t              : 11;
2962         } CMCFG2_b;
2963     };
2964     __IM uint32_t RESERVED;
2965 } R_XSPI_CMCFGCS_Type;                 /*!< Size = 16 (0x10)                                                          */
2966 
2967 /**
2968  * @brief R_XSPI_CDBUF [CDBUF] (xSPI BUF register)
2969  */
2970 typedef struct
2971 {
2972     union
2973     {
2974         __IOM uint32_t CDT;               /*!< (@ 0x00000000) xSPI Command Manual Type buf                               */
2975 
2976         struct
2977         {
2978             __IOM uint32_t CMDSIZE  : 2;  /*!< [1..0] Command Size                                                       */
2979             __IOM uint32_t ADDSIZE  : 3;  /*!< [4..2] Address size                                                       */
2980             __IOM uint32_t DATASIZE : 4;  /*!< [8..5] Write/Read Data Size                                               */
2981             __IOM uint32_t LATE     : 5;  /*!< [13..9] Latency cycle                                                     */
2982             uint32_t                : 1;
2983             __IOM uint32_t TRTYPE   : 1;  /*!< [15..15] Transaction Type                                                 */
2984             __IOM uint32_t CMD      : 16; /*!< [31..16] Command (1-2byte)                                                */
2985         } CDT_b;
2986     };
2987 
2988     union
2989     {
2990         __IOM uint32_t CDA;            /*!< (@ 0x00000004) xSPI Command Manual Address buf                            */
2991 
2992         struct
2993         {
2994             __IOM uint32_t ADD : 32;   /*!< [31..0] Address                                                           */
2995         } CDA_b;
2996     };
2997 
2998     union
2999     {
3000         __IOM uint32_t CDD0;           /*!< (@ 0x00000008) xSPI Command Manual Data 0 buf                             */
3001 
3002         struct
3003         {
3004             __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
3005         } CDD0_b;
3006     };
3007 
3008     union
3009     {
3010         __IOM uint32_t CDD1;           /*!< (@ 0x0000000C) xSPI Command Manual Data 1 buf                             */
3011 
3012         struct
3013         {
3014             __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
3015         } CDD1_b;
3016     };
3017 } R_XSPI_CDBUF_Type;                   /*!< Size = 16 (0x10)                                                          */
3018 
3019 /**
3020  * @brief R_XSPI_CCCTLCS [CCCTLCS] (xSPI CS register)
3021  */
3022 typedef struct
3023 {
3024     union
3025     {
3026         __IOM uint32_t CCCTL0;           /*!< (@ 0x00000000) xSPI Command Calibration Control register 0                */
3027 
3028         struct
3029         {
3030             __IOM uint32_t CAEN     : 1; /*!< [0..0] Automatic Calibration Enable                                       */
3031             __IOM uint32_t CANOWR   : 1; /*!< [1..1] Calibration no write mode                                          */
3032             uint32_t                : 6;
3033             __IOM uint32_t CAITV    : 5; /*!< [12..8] Calibration interval                                              */
3034             uint32_t                : 3;
3035             __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value                                 */
3036             uint32_t                : 3;
3037             __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value                                   */
3038             uint32_t                : 3;
3039         } CCCTL0_b;
3040     };
3041 
3042     union
3043     {
3044         __IOM uint32_t CCCTL1;             /*!< (@ 0x00000004) xSPI Command Calibration Control register 1                */
3045 
3046         struct
3047         {
3048             __IOM uint32_t CACMDSIZE  : 2; /*!< [1..0] Command Size                                                       */
3049             __IOM uint32_t CAADDSIZE  : 3; /*!< [4..2] Address size                                                       */
3050             __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size                                               */
3051             uint32_t                  : 7;
3052             __IOM uint32_t CAWRLATE   : 5; /*!< [20..16] Write Latency cycle                                              */
3053             uint32_t                  : 3;
3054             __IOM uint32_t CARDLATE   : 5; /*!< [28..24] Read Latency cycle                                               */
3055             uint32_t                  : 3;
3056         } CCCTL1_b;
3057     };
3058 
3059     union
3060     {
3061         __IOM uint32_t CCCTL2;           /*!< (@ 0x00000008) xSPI Command Calibration Control register 2                */
3062 
3063         struct
3064         {
3065             __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command                                 */
3066             __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command                                 */
3067         } CCCTL2_b;
3068     };
3069 
3070     union
3071     {
3072         __IOM uint32_t CCCTL3;         /*!< (@ 0x0000000C) xSPI Command Calibration Control register 3                */
3073 
3074         struct
3075         {
3076             __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address                                       */
3077         } CCCTL3_b;
3078     };
3079 
3080     union
3081     {
3082         __IOM uint32_t CCCTL4;          /*!< (@ 0x00000010) xSPI Command Calibration Control register 4                */
3083 
3084         struct
3085         {
3086             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
3087         } CCCTL4_b;
3088     };
3089 
3090     union
3091     {
3092         __IOM uint32_t CCCTL5;          /*!< (@ 0x00000014) xSPI Command Calibration Control register 5                */
3093 
3094         struct
3095         {
3096             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
3097         } CCCTL5_b;
3098     };
3099 
3100     union
3101     {
3102         __IOM uint32_t CCCTL6;          /*!< (@ 0x00000018) xSPI Command Calibration Control register 6                */
3103 
3104         struct
3105         {
3106             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
3107         } CCCTL6_b;
3108     };
3109 
3110     union
3111     {
3112         __IOM uint32_t CCCTL7;          /*!< (@ 0x0000001C) xSPI Command Calibration Control register 7                */
3113 
3114         struct
3115         {
3116             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
3117         } CCCTL7_b;
3118     };
3119 } R_XSPI_CCCTLCS_Type;                  /*!< Size = 32 (0x20)                                                          */
3120 
3121 /**
3122  * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
3123  */
3124 typedef struct
3125 {
3126     union
3127     {
3128         __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
3129 
3130         struct
3131         {
3132             __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
3133             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
3134             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
3135             uint8_t              : 1;
3136             __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
3137             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
3138             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
3139             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
3140         } AGTCR_b;
3141     };
3142 
3143     union
3144     {
3145         __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
3146 
3147         struct
3148         {
3149             __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
3150             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
3151             __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
3152             uint8_t              : 1;
3153         } AGTMR1_b;
3154     };
3155 
3156     union
3157     {
3158         __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
3159 
3160         struct
3161         {
3162             __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
3163                                         *   ratio                                                                     */
3164             uint8_t           : 4;
3165             __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
3166         } AGTMR2_b;
3167     };
3168 
3169     union
3170     {
3171         __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
3172 
3173         struct
3174         {
3175             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
3176             uint8_t            : 2;
3177             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
3178             uint8_t            : 3;
3179         } AGTIOSEL_ALT_b;
3180     };
3181 
3182     union
3183     {
3184         __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
3185 
3186         struct
3187         {
3188             __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
3189                                         *   mode.                                                                     */
3190             uint8_t             : 1;
3191             __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
3192             uint8_t             : 1;
3193             __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
3194             __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
3195         } AGTIOC_b;
3196     };
3197 
3198     union
3199     {
3200         __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
3201 
3202         struct
3203         {
3204             uint8_t            : 2;
3205             __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
3206             uint8_t            : 5;
3207         } AGTISR_b;
3208     };
3209 
3210     union
3211     {
3212         __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
3213 
3214         struct
3215         {
3216             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
3217             __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
3218             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
3219             uint8_t              : 1;
3220             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
3221             __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
3222             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
3223             uint8_t              : 1;
3224         } AGTCMSR_b;
3225     };
3226 
3227     union
3228     {
3229         __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
3230 
3231         struct
3232         {
3233             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
3234             uint8_t            : 2;
3235             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
3236             uint8_t            : 3;
3237         } AGTIOSEL_b;
3238     };
3239 } R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
3240 
3241 /**
3242  * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
3243  */
3244 typedef struct
3245 {
3246     union
3247     {
3248         __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
3249 
3250         struct
3251         {
3252             __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
3253                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
3254                                         *   counter is forcibly stopped and set to FFFFH.                             */
3255         } AGT_b;
3256     };
3257 
3258     union
3259     {
3260         __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
3261 
3262         struct
3263         {
3264             __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
3265                                          *   written to the TSTOP bit in the AGTCRn register, set to
3266                                          *   FFFFH                                                                     */
3267         } AGTCMA_b;
3268     };
3269 
3270     union
3271     {
3272         __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
3273 
3274         struct
3275         {
3276             __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
3277                                          *   written to the TSTOP bit in the AGTCR register, set to
3278                                          *   FFFFH                                                                     */
3279         } AGTCMB_b;
3280     };
3281     __IM uint16_t                 RESERVED;
3282     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
3283 } R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
3284 
3285 /**
3286  * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
3287  */
3288 typedef struct
3289 {
3290     union
3291     {
3292         __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
3293 
3294         struct
3295         {
3296             __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
3297                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
3298                                         *   counter is forcibly stopped and set to FFFFH.                             */
3299         } AGT_b;
3300     };
3301 
3302     union
3303     {
3304         __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
3305 
3306         struct
3307         {
3308             __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
3309                                          *   written to the TSTOP bit in the AGTCRn register, set to
3310                                          *   FFFFH                                                                     */
3311         } AGTCMA_b;
3312     };
3313 
3314     union
3315     {
3316         __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
3317 
3318         struct
3319         {
3320             __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
3321                                          *   written to the TSTOP bit in the AGTCR register, set to
3322                                          *   FFFFH                                                                     */
3323         } AGTCMB_b;
3324     };
3325     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
3326 } R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
3327 
3328 /**
3329  * @brief R_OFS_DATAFLASH_CFGDLOCK_CFGD [CFGD] (Configuration Data [0..1] Lock Bits)
3330  */
3331 typedef struct
3332 {
3333     union
3334     {
3335         __IM uint32_t CFGD_L;          /*!< (@ 0x00000000) Configuration Data Lock Bits Lower Word                    */
3336 
3337         struct
3338         {
3339             __IM uint32_t CDLK0  : 1;  /*!< [0..0] Configuration Data Lock Bit                                        */
3340             __IM uint32_t CDLK1  : 1;  /*!< [1..1] Configuration Data Lock Bit                                        */
3341             __IM uint32_t CDLK2  : 1;  /*!< [2..2] Configuration Data Lock Bit                                        */
3342             __IM uint32_t CDLK3  : 1;  /*!< [3..3] Configuration Data Lock Bit                                        */
3343             __IM uint32_t CDLK4  : 1;  /*!< [4..4] Configuration Data Lock Bit                                        */
3344             __IM uint32_t CDLK5  : 1;  /*!< [5..5] Configuration Data Lock Bit                                        */
3345             __IM uint32_t CDLK6  : 1;  /*!< [6..6] Configuration Data Lock Bit                                        */
3346             __IM uint32_t CDLK7  : 1;  /*!< [7..7] Configuration Data Lock Bit                                        */
3347             __IM uint32_t CDLK8  : 1;  /*!< [8..8] Configuration Data Lock Bit                                        */
3348             __IM uint32_t CDLK9  : 1;  /*!< [9..9] Configuration Data Lock Bit                                        */
3349             __IM uint32_t CDLK10 : 1;  /*!< [10..10] Configuration Data Lock Bit                                      */
3350             __IM uint32_t CDLK11 : 1;  /*!< [11..11] Configuration Data Lock Bit                                      */
3351             __IM uint32_t CDLK12 : 1;  /*!< [12..12] Configuration Data Lock Bit                                      */
3352             __IM uint32_t CDLK13 : 1;  /*!< [13..13] Configuration Data Lock Bit                                      */
3353             __IM uint32_t CDLK14 : 1;  /*!< [14..14] Configuration Data Lock Bit                                      */
3354             __IM uint32_t CDLK15 : 1;  /*!< [15..15] Configuration Data Lock Bit                                      */
3355             __IM uint32_t CDLK16 : 1;  /*!< [16..16] Configuration Data Lock Bit                                      */
3356             __IM uint32_t CDLK17 : 1;  /*!< [17..17] Configuration Data Lock Bit                                      */
3357             __IM uint32_t CDLK18 : 1;  /*!< [18..18] Configuration Data Lock Bit                                      */
3358             __IM uint32_t CDLK19 : 1;  /*!< [19..19] Configuration Data Lock Bit                                      */
3359             __IM uint32_t CDLK20 : 1;  /*!< [20..20] Configuration Data Lock Bit                                      */
3360             __IM uint32_t CDLK21 : 1;  /*!< [21..21] Configuration Data Lock Bit                                      */
3361             __IM uint32_t CDLK22 : 1;  /*!< [22..22] Configuration Data Lock Bit                                      */
3362             __IM uint32_t CDLK23 : 1;  /*!< [23..23] Configuration Data Lock Bit                                      */
3363             __IM uint32_t CDLK24 : 1;  /*!< [24..24] Configuration Data Lock Bit                                      */
3364             __IM uint32_t CDLK25 : 1;  /*!< [25..25] Configuration Data Lock Bit                                      */
3365             __IM uint32_t CDLK26 : 1;  /*!< [26..26] Configuration Data Lock Bit                                      */
3366             __IM uint32_t CDLK27 : 1;  /*!< [27..27] Configuration Data Lock Bit                                      */
3367             __IM uint32_t CDLK28 : 1;  /*!< [28..28] Configuration Data Lock Bit                                      */
3368             __IM uint32_t CDLK29 : 1;  /*!< [29..29] Configuration Data Lock Bit                                      */
3369             __IM uint32_t CDLK30 : 1;  /*!< [30..30] Configuration Data Lock Bit                                      */
3370             __IM uint32_t CDLK31 : 1;  /*!< [31..31] Configuration Data Lock Bit                                      */
3371         } CFGD_L_b;
3372     };
3373 
3374     union
3375     {
3376         __IM uint32_t CFGD_H;          /*!< (@ 0x00000004) Configuration Data Lock Bits Higher Word                   */
3377 
3378         struct
3379         {
3380             __IM uint32_t CDLK32 : 1;  /*!< [0..0] Configuration Data Lock Bit                                        */
3381             __IM uint32_t CDLK33 : 1;  /*!< [1..1] Configuration Data Lock Bit                                        */
3382             __IM uint32_t CDLK34 : 1;  /*!< [2..2] Configuration Data Lock Bit                                        */
3383             __IM uint32_t CDLK35 : 1;  /*!< [3..3] Configuration Data Lock Bit                                        */
3384             __IM uint32_t CDLK36 : 1;  /*!< [4..4] Configuration Data Lock Bit                                        */
3385             __IM uint32_t CDLK37 : 1;  /*!< [5..5] Configuration Data Lock Bit                                        */
3386             __IM uint32_t CDLK38 : 1;  /*!< [6..6] Configuration Data Lock Bit                                        */
3387             __IM uint32_t CDLK39 : 1;  /*!< [7..7] Configuration Data Lock Bit                                        */
3388             __IM uint32_t CDLK40 : 1;  /*!< [8..8] Configuration Data Lock Bit                                        */
3389             __IM uint32_t CDLK41 : 1;  /*!< [9..9] Configuration Data Lock Bit                                        */
3390             __IM uint32_t CDLK42 : 1;  /*!< [10..10] Configuration Data Lock Bit                                      */
3391             __IM uint32_t CDLK43 : 1;  /*!< [11..11] Configuration Data Lock Bit                                      */
3392             __IM uint32_t CDLK44 : 1;  /*!< [12..12] Configuration Data Lock Bit                                      */
3393             __IM uint32_t CDLK45 : 1;  /*!< [13..13] Configuration Data Lock Bit                                      */
3394             __IM uint32_t CDLK46 : 1;  /*!< [14..14] Configuration Data Lock Bit                                      */
3395             __IM uint32_t CDLK47 : 1;  /*!< [15..15] Configuration Data Lock Bit                                      */
3396             __IM uint32_t CDLK48 : 1;  /*!< [16..16] Configuration Data Lock Bit                                      */
3397             __IM uint32_t CDLK49 : 1;  /*!< [17..17] Configuration Data Lock Bit                                      */
3398             __IM uint32_t CDLK50 : 1;  /*!< [18..18] Configuration Data Lock Bit                                      */
3399             __IM uint32_t CDLK51 : 1;  /*!< [19..19] Configuration Data Lock Bit                                      */
3400             __IM uint32_t CDLK52 : 1;  /*!< [20..20] Configuration Data Lock Bit                                      */
3401             __IM uint32_t CDLK53 : 1;  /*!< [21..21] Configuration Data Lock Bit                                      */
3402             __IM uint32_t CDLK54 : 1;  /*!< [22..22] Configuration Data Lock Bit                                      */
3403             __IM uint32_t CDLK55 : 1;  /*!< [23..23] Configuration Data Lock Bit                                      */
3404             __IM uint32_t CDLK56 : 1;  /*!< [24..24] Configuration Data Lock Bit                                      */
3405             __IM uint32_t CDLK57 : 1;  /*!< [25..25] Configuration Data Lock Bit                                      */
3406             __IM uint32_t CDLK58 : 1;  /*!< [26..26] Configuration Data Lock Bit                                      */
3407             __IM uint32_t CDLK59 : 1;  /*!< [27..27] Configuration Data Lock Bit                                      */
3408             __IM uint32_t CDLK60 : 1;  /*!< [28..28] Configuration Data Lock Bit                                      */
3409             __IM uint32_t CDLK61 : 1;  /*!< [29..29] Configuration Data Lock Bit                                      */
3410             __IM uint32_t CDLK62 : 1;  /*!< [30..30] Configuration Data Lock Bit                                      */
3411             __IM uint32_t CDLK63 : 1;  /*!< [31..31] Configuration Data Lock Bit                                      */
3412         } CFGD_H_b;
3413     };
3414 } R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type;  /*!< Size = 8 (0x8)                                                            */
3415 
3416 /**
3417  * @brief R_OFS_DATAFLASH_CFGDLOCK [CFGDLOCK] (Configuration Data Lock Bits)
3418  */
3419 typedef struct
3420 {
3421     __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD0; /*!< (@ 0x00000000) Configuration Data 0 Lock Bits                            */
3422     __IOM R_OFS_DATAFLASH_CFGDLOCK_CFGD_Type CFGD1; /*!< (@ 0x00000008) Configuration Data 1 Lock Bits                            */
3423 
3424     union
3425     {
3426         __IM uint16_t CFGD2;                        /*!< (@ 0x00000010) Configuration Data 2 Lock Bit                              */
3427 
3428         struct
3429         {
3430             __IM uint16_t CDLK0  : 1;               /*!< [0..0] Configuration Data Lock Bit                                        */
3431             __IM uint16_t CDLK1  : 1;               /*!< [1..1] Configuration Data Lock Bit                                        */
3432             __IM uint16_t CDLK2  : 1;               /*!< [2..2] Configuration Data Lock Bit                                        */
3433             __IM uint16_t CDLK3  : 1;               /*!< [3..3] Configuration Data Lock Bit                                        */
3434             __IM uint16_t CDLK4  : 1;               /*!< [4..4] Configuration Data Lock Bit                                        */
3435             __IM uint16_t CDLK5  : 1;               /*!< [5..5] Configuration Data Lock Bit                                        */
3436             __IM uint16_t CDLK6  : 1;               /*!< [6..6] Configuration Data Lock Bit                                        */
3437             __IM uint16_t CDLK7  : 1;               /*!< [7..7] Configuration Data Lock Bit                                        */
3438             __IM uint16_t CDLK8  : 1;               /*!< [8..8] Configuration Data Lock Bit                                        */
3439             __IM uint16_t CDLK9  : 1;               /*!< [9..9] Configuration Data Lock Bit                                        */
3440             __IM uint16_t CDLK10 : 1;               /*!< [10..10] Configuration Data Lock Bit                                      */
3441             __IM uint16_t CDLK11 : 1;               /*!< [11..11] Configuration Data Lock Bit                                      */
3442             __IM uint16_t CDLK12 : 1;               /*!< [12..12] Configuration Data Lock Bit                                      */
3443             __IM uint16_t CDLK13 : 1;               /*!< [13..13] Configuration Data Lock Bit                                      */
3444             __IM uint16_t CDLK14 : 1;               /*!< [14..14] Configuration Data Lock Bit                                      */
3445             __IM uint16_t CDLK15 : 1;               /*!< [15..15] Configuration Data Lock Bit                                      */
3446         } CFGD2_b;
3447     };
3448     __IM uint16_t RESERVED;
3449 } R_OFS_DATAFLASH_CFGDLOCK_Type;                    /*!< Size = 20 (0x14)                                                          */
3450 
3451 /** @} */ /* End of group Device_Peripheral_clusters */
3452 
3453 /* =========================================================================================================================== */
3454 /* ================                            Device Specific Peripheral Section                             ================ */
3455 /* =========================================================================================================================== */
3456 
3457 /** @addtogroup Device_Peripheral_peripherals
3458  * @{
3459  */
3460 
3461 /* =========================================================================================================================== */
3462 /* ================                                         R_ACMPHS0                                         ================ */
3463 /* =========================================================================================================================== */
3464 
3465 /**
3466  * @brief High-Speed Analog Comparator (R_ACMPHS0)
3467  */
3468 
3469 typedef struct                         /*!< (@ 0x40236000) R_ACMPHS0 Structure                                        */
3470 {
3471     union
3472     {
3473         __IOM uint8_t CMPCTL;          /*!< (@ 0x00000000) Comparator Control Register                                */
3474 
3475         struct
3476         {
3477             __IOM uint8_t CINV   : 1;  /*!< [0..0] Comparator output polarity selection                               */
3478             __IOM uint8_t COE    : 1;  /*!< [1..1] Comparator output enable                                           */
3479             __IOM uint8_t CSTEN  : 1;  /*!< [2..2] Interrupt Select                                                   */
3480             __IOM uint8_t CEG    : 2;  /*!< [4..3] Selection of valid edge (Edge selector)                            */
3481             __IOM uint8_t CDFS   : 2;  /*!< [6..5] Noise filter selection                                             */
3482             __IOM uint8_t HCMPON : 1;  /*!< [7..7] Comparator operation control                                       */
3483         } CMPCTL_b;
3484     };
3485     __IM uint8_t RESERVED[3];
3486 
3487     union
3488     {
3489         __IOM uint8_t CMPSEL0;         /*!< (@ 0x00000004) Comparator Input Select Register                           */
3490 
3491         struct
3492         {
3493             __IOM uint8_t CMPSEL : 4;  /*!< [3..0] Comparator Input Selection                                         */
3494             uint8_t              : 4;
3495         } CMPSEL0_b;
3496     };
3497     __IM uint8_t RESERVED1[3];
3498 
3499     union
3500     {
3501         __IOM uint8_t CMPSEL1;         /*!< (@ 0x00000008) Comparator Reference Voltage Select Register               */
3502 
3503         struct
3504         {
3505             __IOM uint8_t CRVS : 6;    /*!< [5..0] Reference Voltage Selection                                        */
3506             uint8_t            : 2;
3507         } CMPSEL1_b;
3508     };
3509     __IM uint8_t RESERVED2[3];
3510 
3511     union
3512     {
3513         __IM uint8_t CMPMON;           /*!< (@ 0x0000000C) Comparator Output Monitor Register                         */
3514 
3515         struct
3516         {
3517             __IM uint8_t CMPMON : 1;   /*!< [0..0] Comparator output monitor                                          */
3518             uint8_t             : 7;
3519         } CMPMON_b;
3520     };
3521     __IM uint8_t RESERVED3[3];
3522 
3523     union
3524     {
3525         __IOM uint8_t CPIOC;           /*!< (@ 0x00000010) Comparator Output Control Register                         */
3526 
3527         struct
3528         {
3529             __IOM uint8_t CPOE   : 1;  /*!< [0..0] Comparator output selection                                        */
3530             uint8_t              : 6;
3531             __IOM uint8_t VREFEN : 1;  /*!< [7..7] Internal Vref enable                                               */
3532         } CPIOC_b;
3533     };
3534 } R_ACMPHS0_Type;                      /*!< Size = 17 (0x11)                                                          */
3535 
3536 /* =========================================================================================================================== */
3537 /* ================                                          R_ADC0                                           ================ */
3538 /* =========================================================================================================================== */
3539 
3540 /**
3541  * @brief A/D Converter (R_ADC0)
3542  */
3543 
3544 typedef struct                         /*!< (@ 0x40332000) R_ADC0 Structure                                           */
3545 {
3546     union
3547     {
3548         __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
3549 
3550         struct
3551         {
3552             __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
3553                                         *   input channel for double triggered operation. The setting
3554                                         *   is only effective while double trigger mode is selected.                  */
3555             uint16_t              : 1;
3556             __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
3557             __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
3558             __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
3559             __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
3560             __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
3561             uint16_t              : 1;
3562             __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
3563             __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
3564             __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
3565         } ADCSR_b;
3566     };
3567 
3568     union
3569     {
3570         __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
3571 
3572         struct
3573         {
3574             __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
3575                                         *   '1' while scanning.                                                       */
3576             uint8_t              : 6;
3577             __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
3578         } ADREF_b;
3579     };
3580 
3581     union
3582     {
3583         __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
3584 
3585         struct
3586         {
3587             __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
3588             uint8_t             : 7;
3589         } ADEXREF_b;
3590     };
3591 
3592     union
3593     {
3594         __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
3595 
3596         struct
3597         {
3598             __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
3599             __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
3600             __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
3601             __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
3602             __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
3603             __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
3604             __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
3605             __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
3606             __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
3607             __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
3608             __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
3609             __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
3610             __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
3611             __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
3612             __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
3613             __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
3614         } ADANSA_b[2];
3615     };
3616 
3617     union
3618     {
3619         __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
3620                                         *                  Select Register                                            */
3621 
3622         struct
3623         {
3624             __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
3625             __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
3626             __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
3627             __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
3628             __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
3629             __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
3630             __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
3631             __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
3632             __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
3633             __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
3634             __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
3635             __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
3636             __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
3637             __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
3638             __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
3639             __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
3640         } ADADS_b[2];
3641     };
3642 
3643     union
3644     {
3645         __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
3646                                         *                  Register                                                   */
3647 
3648         struct
3649         {
3650             __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
3651                                         *   at the only setting of ADC[2:0] bits = 001b or 011b. When
3652                                         *   average mode is selected by setting the ADADC.AVEE bit
3653                                         *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
3654                                         *   = 010b)                                                                   */
3655             uint8_t            : 4;
3656             __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
3657                                         *   by setting the ADADC.AVEE bit to 0, set the addition count
3658                                         *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
3659                                         *   can only be used with 12-bit accuracy selected. NOTE: AVEE
3660                                         *   bit is valid at the only setting of ADC[2:0] bits = 001b
3661                                         *   or 011b. When average mode is selected by setting the ADADC.AVEE
3662                                         *   bit to 1, do not set the addition count to three times
3663                                         *   (ADADC.ADC[2:0] = 010b)                                                   */
3664         } ADADC_b;
3665     };
3666     __IM uint8_t RESERVED;
3667 
3668     union
3669     {
3670         __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
3671 
3672         struct
3673         {
3674             uint16_t               : 1;
3675             __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
3676             uint16_t               : 1;
3677             __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
3678             __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
3679             uint16_t               : 2;
3680             __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
3681             __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
3682             __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
3683             uint16_t               : 2;
3684             __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
3685             __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
3686         } ADCER_b;
3687     };
3688 
3689     union
3690     {
3691         __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
3692 
3693         struct
3694         {
3695             __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
3696                                         *   the A/D conversion start trigger for group B in group scan
3697                                         *   mode.                                                                     */
3698             uint16_t            : 2;
3699             __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
3700                                         *   start trigger in single scan mode and continuous mode.
3701                                         *   In group scan mode, the A/D conversion start trigger for
3702                                         *   group A is selected.                                                      */
3703             uint16_t : 2;
3704         } ADSTRGR_b;
3705     };
3706 
3707     union
3708     {
3709         __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
3710 
3711         struct
3712         {
3713             __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
3714                                         *   Mode Select                                                               */
3715             __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
3716                                         *   Mode Select                                                               */
3717             uint16_t            : 6;
3718             __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
3719             __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
3720             __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
3721                                         *   Group B in group scan mode.                                               */
3722             __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
3723                                         *   Group B in group scan mode.                                               */
3724             uint16_t             : 2;
3725             __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
3726             __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
3727         } ADEXICR_b;
3728     };
3729 
3730     union
3731     {
3732         __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
3733 
3734         struct
3735         {
3736             __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
3737             __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
3738             __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
3739             __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
3740             __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
3741             __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
3742             __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
3743             __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
3744             __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
3745             __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
3746             __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
3747             __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
3748             __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
3749             __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
3750             __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
3751             __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
3752         } ADANSB_b[2];
3753     };
3754 
3755     union
3756     {
3757         __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
3758 
3759         struct
3760         {
3761             __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3762                                          *   result of A/D conversion in response to the second trigger
3763                                          *   in double trigger mode.                                                   */
3764         } ADDBLDR_b;
3765     };
3766 
3767     union
3768     {
3769         __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
3770 
3771         struct
3772         {
3773             __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3774                                         *   A/D conversion result of temperature sensor output.                       */
3775         } ADTSDR_b;
3776     };
3777 
3778     union
3779     {
3780         __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
3781 
3782         struct
3783         {
3784             __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
3785                                         *   A/D result of internal reference voltage.                                 */
3786         } ADOCDR_b;
3787     };
3788 
3789     union
3790     {
3791         union
3792         {
3793             __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
3794 
3795             struct
3796             {
3797                 __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
3798                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
3799                 __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
3800             } ADRD_RIGHT_b;
3801         };
3802 
3803         union
3804         {
3805             __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
3806 
3807             struct
3808             {
3809                 __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
3810                 __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
3811                                             *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
3812             } ADRD_LEFT_b;
3813         };
3814     };
3815 
3816     union
3817     {
3818         __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
3819 
3820         struct
3821         {
3822             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
3823                                         *   storing the result of A/D conversion.                                     */
3824         } ADDR_b[29];
3825     };
3826     __IM uint16_t RESERVED1;
3827     __IM uint32_t RESERVED2;
3828     __IM uint16_t RESERVED3;
3829 
3830     union
3831     {
3832         __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
3833 
3834         struct
3835         {
3836             __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
3837         } ADAMPOFF_b;
3838     };
3839 
3840     union
3841     {
3842         __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
3843 
3844         struct
3845         {
3846             __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
3847             __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
3848             uint8_t            : 6;
3849         } ADTSTPR_b;
3850     };
3851 
3852     union
3853     {
3854         __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
3855 
3856         struct
3857         {
3858             __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
3859             uint16_t              : 3;
3860             __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
3861             uint16_t              : 2;
3862             __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
3863         } ADDDACER_b;
3864     };
3865 
3866     union
3867     {
3868         __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
3869 
3870         struct
3871         {
3872             __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
3873                                         *   Setting Set the sampling time (4 to 255 states)                           */
3874             __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
3875             __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
3876             __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
3877             uint16_t              : 5;
3878         } ADSHCR_b;
3879     };
3880 
3881     union
3882     {
3883         __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
3884 
3885         struct
3886         {
3887             __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
3888                                         *   only for channel.                                                         */
3889             uint16_t             : 1;
3890             __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
3891             uint16_t             : 2;
3892             __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
3893                                         *   for adjustment to hardening of process.                                   */
3894             uint16_t              : 1;
3895             __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
3896                                         *   power save bit for A/D hard macro to hardening of process.                */
3897             __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
3898                                         *   bit for A/D hard macro to hardening of process.                           */
3899             __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
3900                                         *   bit for A/D hard macro to hardening of process.                           */
3901         } ADEXTSTR_b;
3902     };
3903 
3904     union
3905     {
3906         __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
3907 
3908         struct
3909         {
3910             __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
3911             __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
3912                                            *   amplifier test.Refreshing the pressure switch that opens
3913                                            *   for the DAC output voltage charge period when the amplifier
3914                                            *   of the S&H circuit is tested only for the channel is set.                 */
3915             uint16_t            : 1;
3916             __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
3917                                            *   bit.                                                                      */
3918             __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
3919                                            *   bit                                                                       */
3920             uint16_t                 : 1;
3921             __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
3922                                            *   module Details are described to the bit explanation.                      */
3923             __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
3924                                            *   bit explanation.                                                          */
3925         } ADTSTRA_b;
3926     };
3927 
3928     union
3929     {
3930         __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
3931 
3932         struct
3933         {
3934             __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
3935                                         *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
3936             uint16_t : 1;
3937         } ADTSTRB_b;
3938     };
3939 
3940     union
3941     {
3942         __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
3943 
3944         struct
3945         {
3946             __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
3947                                          *   analog module.                                                            */
3948             uint16_t               : 4;
3949             __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
3950             uint16_t               : 3;
3951         } ADTSTRC_b;
3952     };
3953 
3954     union
3955     {
3956         __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
3957 
3958         struct
3959         {
3960             __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
3961                                          *   corresponds to ADVAL 16 input of A/D analog module.                       */
3962             uint16_t : 15;
3963         } ADTSTRD_b;
3964     };
3965 
3966     union
3967     {
3968         __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
3969 
3970         struct
3971         {
3972             __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
3973             __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
3974             __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
3975             __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
3976             __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
3977             __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
3978             uint16_t              : 10;
3979         } ADSWTSTR0_b;
3980     };
3981 
3982     union
3983     {
3984         __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
3985 
3986         struct
3987         {
3988             __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
3989             __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
3990             __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
3991             __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
3992             __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
3993             __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
3994             uint16_t              : 10;
3995         } ADSWTSTR1_b;
3996     };
3997 
3998     union
3999     {
4000         __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
4001 
4002         struct
4003         {
4004             __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
4005                                           *   (ANEX0 switch)                                                            */
4006             __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
4007                                           *   (ANEX1 switch).                                                           */
4008             uint16_t                : 2;
4009             __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
4010             __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
4011             __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
4012             uint16_t                : 1;
4013             __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
4014             __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
4015             __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
4016             __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
4017             __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
4018             uint16_t                : 3;
4019         } ADSWTSTR2_b;
4020     };
4021     __IM uint16_t RESERVED4;
4022 
4023     union
4024     {
4025         __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
4026 
4027         struct
4028         {
4029             __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
4030             __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
4031             uint8_t              : 3;
4032         } ADDISCR_b;
4033     };
4034 
4035     union
4036     {
4037         __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
4038 
4039         struct
4040         {
4041             __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
4042                                         *   the pressure switch in A/D analog module is set.                          */
4043             uint8_t               : 1;
4044             __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
4045             uint8_t               : 1;
4046         } ADSWCR_b;
4047     };
4048 
4049     union
4050     {
4051         __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
4052 
4053         struct
4054         {
4055             __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
4056                                         *   Select                                                                    */
4057             uint8_t : 7;
4058         } ADSHMSR_b;
4059     };
4060 
4061     union
4062     {
4063         __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
4064 
4065         struct
4066         {
4067             __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
4068             uint8_t            : 6;
4069         } ADICR_b;
4070     };
4071 
4072     union
4073     {
4074         __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
4075 
4076         struct
4077         {
4078             uint8_t             : 1;
4079             __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
4080             uint8_t             : 6;
4081         } ADACSR_b;
4082     };
4083     __IM uint8_t RESERVED5;
4084 
4085     union
4086     {
4087         __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
4088 
4089         struct
4090         {
4091             __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
4092                                          *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
4093                                          *   set to 01b (group scan mode). If the bits are set to any
4094                                          *   other values, proper operation is not guaranteed.                         */
4095             __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
4096                                          *   when PGS = 0.)                                                            */
4097             uint16_t               : 6;
4098             __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
4099             uint16_t               : 6;
4100             __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
4101                                          *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
4102                                          *   has been set to 1, single scan is performed continuously
4103                                          *   for group B regardless of the setting of the GBRSCN bit.                  */
4104         } ADGSPCR_b;
4105     };
4106 
4107     union
4108     {
4109         __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
4110                                         *                  Scan)                                                      */
4111 
4112         struct
4113         {
4114             __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
4115             __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
4116         } ADGSCS_b;
4117     };
4118 
4119     union
4120     {
4121         __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
4122 
4123         struct
4124         {
4125             __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
4126                                           *   the result of A/D conversion in response to the respective
4127                                           *   triggers during extended operation in double trigger mode.                */
4128         } ADDBLDRA_b;
4129     };
4130 
4131     union
4132     {
4133         __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
4134 
4135         struct
4136         {
4137             __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
4138                                           *   the result of A/D conversion in response to the respective
4139                                           *   triggers during extended operation in double trigger mode.                */
4140         } ADDBLDRB_b;
4141     };
4142 
4143     union
4144     {
4145         __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
4146 
4147         struct
4148         {
4149             uint8_t             : 7;
4150             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
4151         } ADSER_b;
4152     };
4153     __IM uint8_t RESERVED6;
4154 
4155     union
4156     {
4157         __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
4158                                         *                  Control Register                                           */
4159 
4160         struct
4161         {
4162             __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
4163             uint8_t             : 2;
4164             __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
4165             uint8_t             : 2;
4166             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
4167         } ADHVREFCNT_b;
4168     };
4169     __IM uint8_t RESERVED7;
4170 
4171     union
4172     {
4173         __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
4174                                         *                  Register                                                   */
4175 
4176         struct
4177         {
4178             __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
4179                                         *   result.This bit is valid when both window A operation and
4180                                         *   window B operation are enabled.                                           */
4181             uint8_t              : 3;
4182             __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
4183             __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
4184             uint8_t              : 2;
4185         } ADWINMON_b;
4186     };
4187     __IM uint8_t  RESERVED8;
4188     __IM uint16_t RESERVED9;
4189 
4190     union
4191     {
4192         __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
4193 
4194         struct
4195         {
4196             __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
4197                                         *   are valid when both window A and window B are enabled (CMPAE
4198                                         *   = 1 and CMPBE = 1).                                                       */
4199             uint16_t              : 7;
4200             __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
4201             uint16_t              : 1;
4202             __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
4203             uint16_t              : 1;
4204             __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
4205             __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
4206             __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
4207         } ADCMPCR_b;
4208     };
4209 
4210     union
4211     {
4212         __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
4213                                         *                  Select Register                                            */
4214 
4215         struct
4216         {
4217             __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
4218             __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
4219             uint8_t              : 6;
4220         } ADCMPANSER_b;
4221     };
4222 
4223     union
4224     {
4225         __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
4226                                         *                  Comparison Condition Setting Register                      */
4227 
4228         struct
4229         {
4230             __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
4231                                         *   Condition Select                                                          */
4232             __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
4233                                         *   Select                                                                    */
4234             uint8_t : 6;
4235         } ADCMPLER_b;
4236     };
4237 
4238     union
4239     {
4240         __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
4241                                           *                  Register                                                   */
4242 
4243         struct
4244         {
4245             __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
4246             __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
4247             __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
4248             __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
4249             __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
4250             __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
4251             __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
4252             __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
4253             __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
4254             __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
4255             __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
4256             __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
4257             __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
4258             __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
4259             __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
4260             __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
4261         } ADCMPANSR_b[2];
4262     };
4263 
4264     union
4265     {
4266         __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
4267                                            *                  Setting Register                                           */
4268 
4269         struct
4270         {
4271             __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
4272             __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
4273             __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
4274             __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
4275             __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
4276             __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
4277             __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
4278             __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
4279             __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
4280             __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
4281             __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
4282             __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
4283             __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
4284             __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
4285             __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
4286             __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
4287         } ADCMPLR_b[2];
4288     };
4289 
4290     union
4291     {
4292         __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
4293                                            *                  Setting Register                                           */
4294 
4295         struct
4296         {
4297             __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
4298                                            *   compare window A function is used. ADCMPDR0 sets the lower-side
4299                                            *   level of window A.                                                        */
4300         } ADCMPDR0_b;
4301     };
4302 
4303     union
4304     {
4305         __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
4306                                            *                  Setting Register                                           */
4307 
4308         struct
4309         {
4310             __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
4311                                            *   compare window A function is used. ADCMPDR1 sets the upper-side
4312                                            *   level of window A..                                                       */
4313         } ADCMPDR1_b;
4314     };
4315 
4316     union
4317     {
4318         __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
4319                                             *                  Register                                                   */
4320 
4321         struct
4322         {
4323             __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
4324             __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
4325             __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
4326             __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
4327             __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
4328             __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
4329             __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
4330             __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
4331             __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
4332             __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
4333             __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
4334             __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
4335             __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
4336             __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
4337             __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
4338             __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
4339         } ADCMPSR_b[2];
4340     };
4341 
4342     union
4343     {
4344         __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
4345                                          *                  Channel Status Register                                    */
4346 
4347         struct
4348         {
4349             __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
4350                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
4351                                          *   this bit indicates the temperature sensor output comparison
4352                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
4353                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
4354                                          *   time.                                                                     */
4355             __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
4356                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
4357                                          *   this bit indicates the temperature sensor output comparison
4358                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
4359                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
4360                                          *   time.                                                                     */
4361             uint8_t : 6;
4362         } ADCMPSER_b;
4363     };
4364     __IM uint8_t RESERVED10;
4365 
4366     union
4367     {
4368         __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
4369                                         *                  Register                                                   */
4370 
4371         struct
4372         {
4373             __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
4374                                         *   compares it on the condition of compare window B is selected.             */
4375             uint8_t             : 1;
4376             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
4377         } ADCMPBNSR_b;
4378     };
4379     __IM uint8_t RESERVED11;
4380 
4381     union
4382     {
4383         __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
4384                                            *                  Setting Register                                           */
4385 
4386         struct
4387         {
4388             __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
4389                                            *   used to set the lower level of the window B.                              */
4390         } ADWINLLB_b;
4391     };
4392 
4393     union
4394     {
4395         __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
4396                                            *                  Setting Register                                           */
4397 
4398         struct
4399         {
4400             __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
4401                                            *   used to set the higher level of the window B.                             */
4402         } ADWINULB_b;
4403     };
4404 
4405     union
4406     {
4407         __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
4408 
4409         struct
4410         {
4411             __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
4412                                         *   the comparative result of CH (AN000-AN027, temperature
4413                                         *   sensor, and internal reference voltage) made the object
4414                                         *   of window B relation condition.                                           */
4415             uint8_t : 7;
4416         } ADCMPBSR_b;
4417     };
4418     __IM uint8_t  RESERVED12;
4419     __IM uint16_t RESERVED13;
4420 
4421     union
4422     {
4423         __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
4424 
4425         struct
4426         {
4427             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4428                                         *   registers that sequentially store all A/D converted values.
4429                                         *   The automatic clear function is not applied to these registers.           */
4430         } ADBUF0_b;
4431     };
4432 
4433     union
4434     {
4435         __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
4436 
4437         struct
4438         {
4439             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4440                                         *   registers that sequentially store all A/D converted values.
4441                                         *   The automatic clear function is not applied to these registers.           */
4442         } ADBUF1_b;
4443     };
4444 
4445     union
4446     {
4447         __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
4448 
4449         struct
4450         {
4451             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4452                                         *   registers that sequentially store all A/D converted values.
4453                                         *   The automatic clear function is not applied to these registers.           */
4454         } ADBUF2_b;
4455     };
4456 
4457     union
4458     {
4459         __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
4460 
4461         struct
4462         {
4463             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4464                                         *   registers that sequentially store all A/D converted values.
4465                                         *   The automatic clear function is not applied to these registers.           */
4466         } ADBUF3_b;
4467     };
4468 
4469     union
4470     {
4471         __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
4472 
4473         struct
4474         {
4475             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4476                                         *   registers that sequentially store all A/D converted values.
4477                                         *   The automatic clear function is not applied to these registers.           */
4478         } ADBUF4_b;
4479     };
4480 
4481     union
4482     {
4483         __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
4484 
4485         struct
4486         {
4487             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4488                                         *   registers that sequentially store all A/D converted values.
4489                                         *   The automatic clear function is not applied to these registers.           */
4490         } ADBUF5_b;
4491     };
4492 
4493     union
4494     {
4495         __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
4496 
4497         struct
4498         {
4499             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4500                                         *   registers that sequentially store all A/D converted values.
4501                                         *   The automatic clear function is not applied to these registers.           */
4502         } ADBUF6_b;
4503     };
4504 
4505     union
4506     {
4507         __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
4508 
4509         struct
4510         {
4511             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4512                                         *   registers that sequentially store all A/D converted values.
4513                                         *   The automatic clear function is not applied to these registers.           */
4514         } ADBUF7_b;
4515     };
4516 
4517     union
4518     {
4519         __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
4520 
4521         struct
4522         {
4523             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4524                                         *   registers that sequentially store all A/D converted values.
4525                                         *   The automatic clear function is not applied to these registers.           */
4526         } ADBUF8_b;
4527     };
4528 
4529     union
4530     {
4531         __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
4532 
4533         struct
4534         {
4535             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4536                                         *   registers that sequentially store all A/D converted values.
4537                                         *   The automatic clear function is not applied to these registers.           */
4538         } ADBUF9_b;
4539     };
4540 
4541     union
4542     {
4543         __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
4544 
4545         struct
4546         {
4547             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4548                                         *   registers that sequentially store all A/D converted values.
4549                                         *   The automatic clear function is not applied to these registers.           */
4550         } ADBUF10_b;
4551     };
4552 
4553     union
4554     {
4555         __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
4556 
4557         struct
4558         {
4559             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4560                                         *   registers that sequentially store all A/D converted values.
4561                                         *   The automatic clear function is not applied to these registers.           */
4562         } ADBUF11_b;
4563     };
4564 
4565     union
4566     {
4567         __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
4568 
4569         struct
4570         {
4571             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4572                                         *   registers that sequentially store all A/D converted values.
4573                                         *   The automatic clear function is not applied to these registers.           */
4574         } ADBUF12_b;
4575     };
4576 
4577     union
4578     {
4579         __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
4580 
4581         struct
4582         {
4583             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4584                                         *   registers that sequentially store all A/D converted values.
4585                                         *   The automatic clear function is not applied to these registers.           */
4586         } ADBUF13_b;
4587     };
4588 
4589     union
4590     {
4591         __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
4592 
4593         struct
4594         {
4595             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4596                                         *   registers that sequentially store all A/D converted values.
4597                                         *   The automatic clear function is not applied to these registers.           */
4598         } ADBUF14_b;
4599     };
4600 
4601     union
4602     {
4603         __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
4604 
4605         struct
4606         {
4607             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
4608                                         *   registers that sequentially store all A/D converted values.
4609                                         *   The automatic clear function is not applied to these registers.           */
4610         } ADBUF15_b;
4611     };
4612 
4613     union
4614     {
4615         __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
4616 
4617         struct
4618         {
4619             __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
4620             uint8_t             : 7;
4621         } ADBUFEN_b;
4622     };
4623     __IM uint8_t RESERVED14;
4624 
4625     union
4626     {
4627         __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
4628 
4629         struct
4630         {
4631             __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
4632                                         *   data buffer to which the next A/D converted data is transferred.          */
4633             __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
4634             uint8_t             : 3;
4635         } ADBUFPTR_b;
4636     };
4637     __IM uint8_t  RESERVED15;
4638     __IM uint32_t RESERVED16[2];
4639     __IM uint8_t  RESERVED17;
4640 
4641     union
4642     {
4643         __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
4644 
4645         struct
4646         {
4647             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
4648         } ADSSTRL_b;
4649     };
4650 
4651     union
4652     {
4653         __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
4654 
4655         struct
4656         {
4657             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
4658         } ADSSTRT_b;
4659     };
4660 
4661     union
4662     {
4663         __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
4664 
4665         struct
4666         {
4667             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
4668         } ADSSTRO_b;
4669     };
4670 
4671     union
4672     {
4673         __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
4674 
4675         struct
4676         {
4677             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
4678         } ADSSTR_b[16];
4679     };
4680 
4681     union
4682     {
4683         __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
4684 
4685         struct
4686         {
4687             __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
4688             __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
4689             __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
4690             __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
4691             uint16_t             : 12;
4692         } ADANIM_b;
4693     };
4694 
4695     union
4696     {
4697         __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
4698 
4699         struct
4700         {
4701             uint8_t              : 6;
4702             __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
4703             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
4704         } ADCALEXE_b;
4705     };
4706     __IM uint8_t RESERVED18;
4707 
4708     union
4709     {
4710         __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
4711                                           *                  Register                                                   */
4712 
4713         struct
4714         {
4715             __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
4716             __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
4717             __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
4718             __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
4719             uint8_t                 : 2;
4720             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
4721         } VREFAMPCNT_b;
4722     };
4723     __IM uint8_t  RESERVED19;
4724     __IM uint16_t RESERVED20;
4725 
4726     union
4727     {
4728         __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
4729 
4730         struct
4731         {
4732             __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
4733         } ADRD_b;
4734     };
4735 
4736     union
4737     {
4738         __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
4739 
4740         struct
4741         {
4742             __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
4743             uint8_t             : 6;
4744         } ADRST_b;
4745     };
4746     __IM uint8_t  RESERVED21;
4747     __IM uint32_t RESERVED22[41];
4748 
4749     union
4750     {
4751         __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
4752 
4753         struct
4754         {
4755             __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
4756             __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
4757             __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
4758             __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
4759             __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
4760             __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
4761             __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
4762             __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
4763             __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
4764             __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
4765             __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
4766             __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
4767             __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
4768             __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
4769             __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
4770             __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
4771         } ADPGACR_b;
4772     };
4773 
4774     union
4775     {
4776         __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
4777                                           *                  Register 0                                                 */
4778 
4779         struct
4780         {
4781             __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
4782                                           *   b) when the shingle end is input and each PGA P000 is set.
4783                                           *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
4784                                           *   sets the gain magnification when the differential motion
4785                                           *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
4786             __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
4787                                           *   b) when the shingle end is input and each PGA P001 is set.
4788                                           *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
4789                                           *   sets the gain magnification when the differential motion
4790                                           *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
4791             __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
4792                                           *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
4793                                           *   each PGA P002 is set. When the differential motion is input,
4794                                           *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
4795                                           *   the differential motion is input by the combination with
4796                                           *   ADPGSDCR0.P002DG 1:0.                                                     */
4797             __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
4798                                           *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
4799                                           *   each PGA P003 is set. When the differential motion is input,
4800                                           *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
4801                                           *   the differential motion is input by the combination with
4802                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
4803         } ADPGAGS0_b;
4804     };
4805     __IM uint32_t RESERVED23[3];
4806 
4807     union
4808     {
4809         __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
4810                                          *                  Input Control Register                                     */
4811 
4812         struct
4813         {
4814             __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
4815                                          *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
4816             uint16_t               : 1;
4817             __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
4818             __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
4819                                          *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
4820             uint16_t               : 1;
4821             __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
4822             __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
4823                                          *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
4824             uint16_t               : 1;
4825             __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
4826             __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
4827                                          *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
4828             uint16_t               : 1;
4829             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
4830         } ADPGADCR0_b;
4831     };
4832     __IM uint16_t RESERVED24;
4833 
4834     union
4835     {
4836         __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
4837                                         *                  Input Bias Select Register 0                               */
4838 
4839         struct
4840         {
4841             __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
4842                                         *   SelectNOTE: This bit selects the input bias voltage value
4843                                         *   when differential inputs are used.                                        */
4844             uint8_t : 7;
4845         } ADPGADBS0_b;
4846     };
4847 
4848     union
4849     {
4850         __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
4851                                         *                  Input Bias Select Register 1                               */
4852 
4853         struct
4854         {
4855             __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
4856                                         *   This bit selects the input bias voltage value when differential
4857                                         *   inputs are used.                                                          */
4858             uint8_t : 7;
4859         } ADPGADBS1_b;
4860     };
4861     __IM uint16_t RESERVED25;
4862     __IM uint32_t RESERVED26[10];
4863 
4864     union
4865     {
4866         __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
4867 
4868         struct
4869         {
4870             __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
4871             uint32_t              : 13;
4872             __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
4873             uint32_t              : 12;
4874         } ADREFMON_b;
4875     };
4876 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
4877 
4878 /* =========================================================================================================================== */
4879 /* ================                                          R_PSCU                                           ================ */
4880 /* =========================================================================================================================== */
4881 
4882 /**
4883  * @brief Peripheral Security Control Unit (R_PSCU)
4884  */
4885 
4886 typedef struct                         /*!< (@ 0x40204000) R_PSCU Structure                                           */
4887 {
4888     __IM uint32_t RESERVED;
4889 
4890     union
4891     {
4892         __IOM uint32_t PSARB;          /*!< (@ 0x00000004) Peripheral Security Attribution Register B                 */
4893 
4894         struct
4895         {
4896             uint32_t               : 4;
4897             __IOM uint32_t PSARB4  : 1; /*!< [4..4] I3C Bus Interface 2 Security Attribution                           */
4898             uint32_t               : 3;
4899             __IOM uint32_t PSARB8  : 1; /*!< [8..8] I2C Bus Interface 1 Security Attribution                           */
4900             __IOM uint32_t PSARB9  : 1; /*!< [9..9] I2C Bus Interface 0 Security Attribution                           */
4901             uint32_t               : 1;
4902             __IOM uint32_t PSARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Security Attribution     */
4903             __IOM uint32_t PSARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Security Attribution     */
4904             uint32_t               : 2;
4905             __IOM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Security Attribution                    */
4906             __IOM uint32_t PSARB16 : 1; /*!< [16..16] Octa Memory Controller Security Attribution                      */
4907             uint32_t               : 1;
4908             __IOM uint32_t PSARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Security Attribution               */
4909             __IOM uint32_t PSARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Security Attribution               */
4910             uint32_t               : 2;
4911             __IOM uint32_t PSARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Security Attribution            */
4912             uint32_t               : 4;
4913             __IOM uint32_t PSARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Security Attribution            */
4914             __IOM uint32_t PSARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Security Attribution            */
4915             __IOM uint32_t PSARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Security Attribution            */
4916             __IOM uint32_t PSARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Security Attribution            */
4917             __IOM uint32_t PSARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Security Attribution            */
4918         } PSARB_b;
4919     };
4920 
4921     union
4922     {
4923         __IOM uint32_t PSARC;           /*!< (@ 0x00000008) Peripheral Security Attribution Register C                 */
4924 
4925         struct
4926         {
4927             __IOM uint32_t PSARC0 : 1;  /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Security
4928                                          *   Attribution                                                               */
4929             __IOM uint32_t PSARC1 : 1;  /*!< [1..1] Cyclic Redundancy Check Calculator Security Attribution            */
4930             uint32_t              : 5;
4931             __IOM uint32_t PSARC7 : 1;  /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Security
4932                                          *   Attribution                                                               */
4933             __IOM uint32_t PSARC8 : 1;  /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Security
4934                                          *   Attribution                                                               */
4935             uint32_t               : 2;
4936             __IOM uint32_t PSARC11 : 1; /*!< [11..11] Secure Digital Host IF 1 Security Attribution                    */
4937             __IOM uint32_t PSARC12 : 1; /*!< [12..12] Secure Digital Host IF 0 Security Attribution                    */
4938             __IOM uint32_t PSARC13 : 1; /*!< [13..13] Data Operation Circuit Security Attribution                      */
4939             uint32_t               : 1;
4940             __IOM uint32_t PSARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Security Attribution               */
4941             __IOM uint32_t PSARC16 : 1; /*!< [16..16] CEU Security Attribution                                         */
4942             uint32_t               : 9;
4943             __IOM uint32_t PSARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Security
4944                                          *   Attribution                                                               */
4945             __IOM uint32_t PSARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Security
4946                                          *   Attribution                                                               */
4947             uint32_t               : 3;
4948             __IOM uint32_t PSARC31 : 1; /*!< [31..31] SHIP Security Attribution                                        */
4949         } PSARC_b;
4950     };
4951 
4952     union
4953     {
4954         __IOM uint32_t PSARD;          /*!< (@ 0x0000000C) Peripheral Security Attribution Register D                 */
4955 
4956         struct
4957         {
4958             uint32_t               : 4;
4959             __IOM uint32_t PSARD4  : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Security Attribution          */
4960             __IOM uint32_t PSARD5  : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Security Attribution          */
4961             uint32_t               : 5;
4962             __IOM uint32_t PSARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Security Attribution          */
4963             __IOM uint32_t PSARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Security Attribution          */
4964             __IOM uint32_t PSARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Security Attribution          */
4965             __IOM uint32_t PSARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Security Attribution          */
4966             __IOM uint32_t PSARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Security Attribution                      */
4967             __IOM uint32_t PSARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Security Attribution                      */
4968             uint32_t               : 3;
4969             __IOM uint32_t PSARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Security Attribution                        */
4970             uint32_t               : 1;
4971             __IOM uint32_t PSARD22 : 1; /*!< [22..22] Temperature Sensor Security Attribution                          */
4972             uint32_t               : 4;
4973             __IOM uint32_t PSARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Security Attribution              */
4974             __IOM uint32_t PSARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Security Attribution              */
4975             uint32_t               : 3;
4976         } PSARD_b;
4977     };
4978 
4979     union
4980     {
4981         __IOM uint32_t PSARE;          /*!< (@ 0x00000010) Peripheral Security Attribution Register E                 */
4982 
4983         struct
4984         {
4985             uint32_t               : 1;
4986             __IOM uint32_t PSARE1  : 1; /*!< [1..1] WDT0 Security Attribution                                          */
4987             __IOM uint32_t PSARE2  : 1; /*!< [2..2] Independent Watchdog Timer Security Attribution                    */
4988             __IOM uint32_t PSARE3  : 1; /*!< [3..3] Real Time Clock Security Attribution                               */
4989             uint32_t               : 4;
4990             __IOM uint32_t PSARE8  : 1; /*!< [8..8] ULPT1 Security Attribution                                         */
4991             __IOM uint32_t PSARE9  : 1; /*!< [9..9] ULPT0 Security Attribution                                         */
4992             uint32_t               : 8;
4993             __IOM uint32_t PSARE18 : 1; /*!< [18..18] General PWM Timer channel13 Security Attribution                 */
4994             __IOM uint32_t PSARE19 : 1; /*!< [19..19] General PWM Timer channel12 Security Attribution                 */
4995             __IOM uint32_t PSARE20 : 1; /*!< [20..20] General PWM Timer channel11 Security Attribution                 */
4996             __IOM uint32_t PSARE21 : 1; /*!< [21..21] General PWM Timer channel10 Security Attribution                 */
4997             __IOM uint32_t PSARE22 : 1; /*!< [22..22] General PWM Timer channel9 Security Attribution                  */
4998             __IOM uint32_t PSARE23 : 1; /*!< [23..23] General PWM Timer channel8 Security Attribution                  */
4999             __IOM uint32_t PSARE24 : 1; /*!< [24..24] General PWM Timer channel7 Security Attribution                  */
5000             __IOM uint32_t PSARE25 : 1; /*!< [25..25] General PWM Timer channel6 Security Attribution                  */
5001             __IOM uint32_t PSARE26 : 1; /*!< [26..26] General PWM Timer channel5 Security Attribution                  */
5002             __IOM uint32_t PSARE27 : 1; /*!< [27..27] General PWM Timer channel4 Security Attribution                  */
5003             __IOM uint32_t PSARE28 : 1; /*!< [28..28] General PWM Timer channel3 Security Attribution                  */
5004             __IOM uint32_t PSARE29 : 1; /*!< [29..29] General PWM Timer channel2 Security Attribution                  */
5005             __IOM uint32_t PSARE30 : 1; /*!< [30..30] General PWM Timer channel1 Security Attribution                  */
5006             __IOM uint32_t PSARE31 : 1; /*!< [31..31] General PWM Timer channel0 Security Attribution                  */
5007         } PSARE_b;
5008     };
5009 
5010     union
5011     {
5012         __IOM uint32_t MSSAR;           /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
5013 
5014         struct
5015         {
5016             __IOM uint32_t MSSAR0  : 1; /*!< [0..0] SRAM0 Clock Stop Security Attribution                              */
5017             __IOM uint32_t MSSAR1  : 1; /*!< [1..1] SRAM1 Clock Stop Security Attribution                              */
5018             uint32_t               : 9;
5019             __IOM uint32_t MSSAR11 : 1; /*!< [11..11] CTCM0 Security Attribution                                       */
5020             uint32_t               : 1;
5021             __IOM uint32_t MSSAR13 : 1; /*!< [13..13] STCM0 Security Attribution                                       */
5022             uint32_t               : 1;
5023             __IOM uint32_t MSSAR15 : 1; /*!< [15..15] Standby RAM Clock Stop Security Attribution                      */
5024             uint32_t               : 6;
5025             __IOM uint32_t MSSAR22 : 1; /*!< [22..22] DMAC0/DTC0 Clock Stop Security Attribution                       */
5026             uint32_t               : 8;
5027             __IOM uint32_t MSSAR31 : 1; /*!< [31..31] ELC clock stop Security Attribution                              */
5028         } MSSAR_b;
5029     };
5030     __IM uint32_t RESERVED1;
5031 
5032     union
5033     {
5034         __IOM uint32_t PPARB;          /*!< (@ 0x0000001C) Peripheral Privilege Attribution Register B                */
5035 
5036         struct
5037         {
5038             uint32_t               : 4;
5039             __IOM uint32_t PPARB4  : 1; /*!< [4..4] I3C Bus Interface 2 Privilege Attribution                          */
5040             uint32_t               : 3;
5041             __IOM uint32_t PPARB8  : 1; /*!< [8..8] I2C Bus Interface 1 Privilege Attribution                          */
5042             __IOM uint32_t PPARB9  : 1; /*!< [9..9] I2C Bus Interface 0 Privilege Attribution                          */
5043             uint32_t               : 1;
5044             __IOM uint32_t PPARB11 : 1; /*!< [11..11] Universal Serial Bus 2.0 FS Interface 0 Privilege Attribution    */
5045             __IOM uint32_t PPARB12 : 1; /*!< [12..12] Universal Serial Bus 2.0 HS Interface 0 Privilege Attribution    */
5046             uint32_t               : 2;
5047             __IOM uint32_t PPARB15 : 1; /*!< [15..15] ETHER0/EDMAC0 Controller Privilege Attribution                   */
5048             __IOM uint32_t PPARB16 : 1; /*!< [16..16] Octa Memory Controller Privilege Attribution                     */
5049             uint32_t               : 1;
5050             __IOM uint32_t PPARB18 : 1; /*!< [18..18] Serial Peripheral Interface 1 Privilege Attribution              */
5051             __IOM uint32_t PPARB19 : 1; /*!< [19..19] Serial Peripheral Interface 0 Privilege Attribution              */
5052             uint32_t               : 2;
5053             __IOM uint32_t PPARB22 : 1; /*!< [22..22] Serial Communication Interface 9 Privilege Attribution           */
5054             uint32_t               : 4;
5055             __IOM uint32_t PPARB27 : 1; /*!< [27..27] Serial Communication Interface 4 Privilege Attribution           */
5056             __IOM uint32_t PPARB28 : 1; /*!< [28..28] Serial Communication Interface 3 Privilege Attribution           */
5057             __IOM uint32_t PPARB29 : 1; /*!< [29..29] Serial Communication Interface 2 Privilege Attribution           */
5058             __IOM uint32_t PPARB30 : 1; /*!< [30..30] Serial Communication Interface 1 Privilege Attribution           */
5059             __IOM uint32_t PPARB31 : 1; /*!< [31..31] Serial Communication Interface 0 Privilege Attribution           */
5060         } PPARB_b;
5061     };
5062 
5063     union
5064     {
5065         __IOM uint32_t PPARC;           /*!< (@ 0x00000020) Peripheral Privilege Attribution Register C                */
5066 
5067         struct
5068         {
5069             __IOM uint32_t PPARC0 : 1;  /*!< [0..0] Clock Frequency Accuracy Measurement Circuit Privilege
5070                                          *   Attribution                                                               */
5071             __IOM uint32_t PPARC1 : 1;  /*!< [1..1] Cyclic Redundancy Check Calculator Privilege Attribution           */
5072             uint32_t              : 5;
5073             __IOM uint32_t PPARC7 : 1;  /*!< [7..7] Serial Sound Interface Enhanced (channel 1) Privilege
5074                                          *   Attribution                                                               */
5075             __IOM uint32_t PPARC8 : 1;  /*!< [8..8] Serial Sound Interface Enhanced (channel 0) Privilege
5076                                          *   Attribution                                                               */
5077             uint32_t               : 2;
5078             __IOM uint32_t PPARC11 : 1; /*!< [11..11] Privilege Digital Host IF 1 Privilege Attribution                */
5079             __IOM uint32_t PPARC12 : 1; /*!< [12..12] Privilege Digital Host IF 0 Privilege Attribution                */
5080             __IOM uint32_t PPARC13 : 1; /*!< [13..13] Data Operation Circuit Privilege Attribution                     */
5081             uint32_t               : 1;
5082             __IOM uint32_t PPARC15 : 1; /*!< [15..15] Graph-ic(GLCDC,MIPI,DRW,JPEG) Privilege Attribution              */
5083             __IOM uint32_t PPARC16 : 1; /*!< [16..16] CEU Privilege Attribution                                        */
5084             uint32_t               : 9;
5085             __IOM uint32_t PPARC26 : 1; /*!< [26..26] Controller Area Network with Flexible Data-Rate 1 Privilege
5086                                          *   Attribution                                                               */
5087             __IOM uint32_t PPARC27 : 1; /*!< [27..27] Controller Area Network with Flexible Data-Rate 0 Privilege
5088                                          *   Attribution                                                               */
5089             uint32_t               : 3;
5090             __IOM uint32_t PPARC31 : 1; /*!< [31..31] SHIP Privilege Attribution                                       */
5091         } PPARC_b;
5092     };
5093 
5094     union
5095     {
5096         __IOM uint32_t PPARD;          /*!< (@ 0x00000024) Peripheral Privilege Attribution Register D                */
5097 
5098         struct
5099         {
5100             uint32_t               : 4;
5101             __IOM uint32_t PPARD4  : 1; /*!< [4..4] Asynchronous General Purpose Timer 1 Privilege Attribution         */
5102             __IOM uint32_t PPARD5  : 1; /*!< [5..5] Asynchronous General Purpose Timer 0 Privilege Attribution         */
5103             uint32_t               : 5;
5104             __IOM uint32_t PPARD11 : 1; /*!< [11..11] Port Output Enable for GPT Group 3 Privilege Attribution         */
5105             __IOM uint32_t PPARD12 : 1; /*!< [12..12] Port Output Enable for GPT Group 2 Privilege Attribution         */
5106             __IOM uint32_t PPARD13 : 1; /*!< [13..13] Port Output Enable for GPT Group 1 Privilege Attribution         */
5107             __IOM uint32_t PPARD14 : 1; /*!< [14..14] Port Output Enable for GPT Group 0 Privilege Attribution         */
5108             __IOM uint32_t PPARD15 : 1; /*!< [15..15] 12-Bit A/D 1 Converter Privilege Attribution                     */
5109             __IOM uint32_t PPARD16 : 1; /*!< [16..16] 12-Bit A/D 0 Converter Privilege Attribution                     */
5110             uint32_t               : 3;
5111             __IOM uint32_t PPARD20 : 1; /*!< [20..20] 12-Bit D/A Converter Privilege Attribution                       */
5112             uint32_t               : 1;
5113             __IOM uint32_t PPARD22 : 1; /*!< [22..22] Temperature Sensor Privilege Attribution                         */
5114             uint32_t               : 4;
5115             __IOM uint32_t PPARD27 : 1; /*!< [27..27] High speed analog Comparator 1 Privilege Attribution             */
5116             __IOM uint32_t PPARD28 : 1; /*!< [28..28] High speed analog Comparator 0 Privilege Attribution             */
5117             uint32_t               : 3;
5118         } PPARD_b;
5119     };
5120 
5121     union
5122     {
5123         __IOM uint32_t PPARE;          /*!< (@ 0x00000028) Peripheral Privilege Attribution Register E                */
5124 
5125         struct
5126         {
5127             uint32_t               : 1;
5128             __IOM uint32_t PPARE1  : 1; /*!< [1..1] Watchdog Timer0 Privilege Attribution                              */
5129             __IOM uint32_t PPARE2  : 1; /*!< [2..2] Independent Watchdog Timer Privilege Attribution                   */
5130             __IOM uint32_t PPARE3  : 1; /*!< [3..3] Real Time Clock Privilege Attribution                              */
5131             uint32_t               : 4;
5132             __IOM uint32_t PPARE8  : 1; /*!< [8..8] ULPT1 Privilege Attribution                                        */
5133             __IOM uint32_t PPARE9  : 1; /*!< [9..9] ULPT0 Privilege Attribution                                        */
5134             uint32_t               : 8;
5135             __IOM uint32_t PPARE18 : 1; /*!< [18..18] General PWM Timer channel13 Privilege Attribution                */
5136             __IOM uint32_t PPARE19 : 1; /*!< [19..19] General PWM Timer channel12 Privilege Attribution                */
5137             __IOM uint32_t PPARE20 : 1; /*!< [20..20] General PWM Timer channel11 Privilege Attribution                */
5138             __IOM uint32_t PPARE21 : 1; /*!< [21..21] General PWM Timer channel10 Privilege Attribution                */
5139             __IOM uint32_t PPARE22 : 1; /*!< [22..22] General PWM Timer channel9 Privilege Attribution                 */
5140             __IOM uint32_t PPARE23 : 1; /*!< [23..23] General PWM Timer channel8 Privilege Attribution                 */
5141             __IOM uint32_t PPARE24 : 1; /*!< [24..24] General PWM Timer channel7 Privilege Attribution                 */
5142             __IOM uint32_t PPARE25 : 1; /*!< [25..25] General PWM Timer channel6 Privilege Attribution                 */
5143             __IOM uint32_t PPARE26 : 1; /*!< [26..26] General PWM Timer channel5 Privilege Attribution                 */
5144             __IOM uint32_t PPARE27 : 1; /*!< [27..27] General PWM Timer channel4 Privilege Attribution                 */
5145             __IOM uint32_t PPARE28 : 1; /*!< [28..28] General PWM Timer channel3 Privilege Attribution                 */
5146             __IOM uint32_t PPARE29 : 1; /*!< [29..29] General PWM Timer channel2 Privilege Attribution                 */
5147             __IOM uint32_t PPARE30 : 1; /*!< [30..30] General PWM Timer channel1 Privilege Attribution                 */
5148             __IOM uint32_t PPARE31 : 1; /*!< [31..31] General PWM Timer channel0 Privilege Attribution                 */
5149         } PPARE_b;
5150     };
5151 
5152     union
5153     {
5154         __IOM uint32_t MSPAR;          /*!< (@ 0x0000002C) Module Stop Privilege Attribution Register                 */
5155 
5156         struct
5157         {
5158             uint32_t               : 31;
5159             __IOM uint32_t MSPAR31 : 1; /*!< [31..31] ELC clock stop Privilege Attribution                             */
5160         } MSPAR_b;
5161     };
5162 
5163     union
5164     {
5165         __IM uint32_t CFSAMONA;        /*!< (@ 0x00000030) Code Flash Security Attribution Monitor Register
5166                                         *                  A                                                          */
5167 
5168         struct
5169         {
5170             uint32_t           : 15;
5171             __IM uint32_t CFS2 : 9;    /*!< [23..15] Code Flash Secure area                                           */
5172             uint32_t           : 8;
5173         } CFSAMONA_b;
5174     };
5175 
5176     union
5177     {
5178         __IM uint32_t DFSAMON;         /*!< (@ 0x00000034) Data Flash Security Attribution Monitor Register           */
5179 
5180         struct
5181         {
5182             uint32_t          : 10;
5183             __IM uint32_t DFS : 6;     /*!< [15..10] Data flash Secure area                                           */
5184             uint32_t          : 16;
5185         } DFSAMON_b;
5186     };
5187 
5188     union
5189     {
5190         __IM uint32_t DLMMON;          /*!< (@ 0x00000038) Device Lifecycle Management State Monitor Register         */
5191 
5192         struct
5193         {
5194             __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
5195             uint32_t             : 28;
5196         } DLMMON_b;
5197     };
5198 } R_PSCU_Type;                         /*!< Size = 60 (0x3c)                                                          */
5199 
5200 /* =========================================================================================================================== */
5201 /* ================                                           R_BUS                                           ================ */
5202 /* =========================================================================================================================== */
5203 
5204 /**
5205  * @brief Bus Interface (R_BUS)
5206  */
5207 
5208 typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
5209 {
5210     __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
5211     __IM uint32_t        RESERVED[480];
5212     __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
5213 
5214     union
5215     {
5216         __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
5217 
5218         struct
5219         {
5220             __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
5221             __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
5222             __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
5223             __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
5224             __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
5225             __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
5226             __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
5227             __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
5228             __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
5229             __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
5230             __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5231             __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5232             __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5233             __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5234             __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5235             __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
5236         } CSRECEN_b;
5237     };
5238     __IM uint16_t          RESERVED1;
5239     __IM uint32_t          RESERVED2[223];
5240     __IOM R_BUS_SDRAM_Type SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
5241     __IM uint32_t          RESERVED3[235];
5242 
5243     union
5244     {
5245         __IOM R_BUS_OAD_Type  OAD;     /*!< (@ 0x00001000) Bus Operation After Detection Registers                    */
5246         __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers                               */
5247     };
5248     __IM uint32_t RESERVED4[58];
5249 
5250     union
5251     {
5252         union
5253         {
5254             __IOM uint32_t BUSMABT;      /*!< (@ 0x00001100) Bus Master Arbitration Control Register.                   */
5255 
5256             struct
5257             {
5258                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI.                                     */
5259                 uint32_t            : 31;
5260             } BUSMABT_b;
5261         };
5262         __IOM R_BUS_BUSS_Type BUSS[18];  /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
5263     };
5264     __IM uint32_t RESERVED5[46];
5265 
5266     union
5267     {
5268         __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers                  */
5269         __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers                  */
5270     };
5271     __IM uint32_t RESERVED6[33];
5272 
5273     union
5274     {
5275         __IOM uint32_t BUSDIVBYP;        /*!< (@ 0x00001300) Bus Divider Bypass Register.                               */
5276 
5277         struct
5278         {
5279             __IOM uint32_t EDMABPE  : 1; /*!< [0..0] Divider for EDMACBI bypass enable.                                 */
5280             uint32_t                : 2;
5281             __IOM uint32_t GDSSBPE  : 1; /*!< [3..3] Divider for GDSSBI bypass enable.                                  */
5282             uint32_t                : 12;
5283             __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable.                              */
5284             uint32_t                : 15;
5285         } BUSDIVBYP_b;
5286     };
5287     __IM uint32_t            RESERVED7[319];
5288     __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers                                        */
5289     __IM uint32_t            RESERVED8[16];
5290 
5291     union
5292     {
5293         __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers                                    */
5294         __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address
5295                                               *                  and Read/Write Status registers.                           */
5296     };
5297     __IM uint32_t RESERVED9[28];
5298 
5299     union
5300     {
5301         __IOM R_BUS_BUSERRb_Type    BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers                                        */
5302         __IOM R_BUS_DMACDTCERR_Type DMACDTCERR;  /*!< (@ 0x00001A00) DMAC/DTC Error Registers                                   */
5303     };
5304     __IM uint32_t           RESERVED10[16];
5305     __IOM R_BUS_MBWERR_Type MBWERR;              /*!< (@ 0x00001B00) Master Bufferable Write Error Registers                    */
5306     __IM uint32_t           RESERVED11[5];
5307     __IOM R_BUS_MBWERR_Type SBWERR;              /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers                     */
5308 } R_BUS_Type;                                    /*!< Size = 6956 (0x1b2c)                                                      */
5309 
5310 /* =========================================================================================================================== */
5311 /* ================                                           R_CAC                                           ================ */
5312 /* =========================================================================================================================== */
5313 
5314 /**
5315  * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
5316  */
5317 
5318 typedef struct                         /*!< (@ 0x40202400) R_CAC Structure                                            */
5319 {
5320     union
5321     {
5322         __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
5323 
5324         struct
5325         {
5326             __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
5327             uint8_t            : 7;
5328         } CACR0_b;
5329     };
5330 
5331     union
5332     {
5333         __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
5334 
5335         struct
5336         {
5337             __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
5338             __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
5339             __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
5340             __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
5341         } CACR1_b;
5342     };
5343 
5344     union
5345     {
5346         __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
5347 
5348         struct
5349         {
5350             __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
5351             __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
5352             __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
5353                                         *   Select                                                                    */
5354             __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
5355         } CACR2_b;
5356     };
5357 
5358     union
5359     {
5360         __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
5361 
5362         struct
5363         {
5364             __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
5365             __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
5366             __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
5367             uint8_t              : 1;
5368             __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
5369             __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
5370             __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
5371             uint8_t              : 1;
5372         } CAICR_b;
5373     };
5374 
5375     union
5376     {
5377         __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
5378 
5379         struct
5380         {
5381             __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
5382             __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
5383             __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
5384             uint8_t            : 5;
5385         } CASTR_b;
5386     };
5387     __IM uint8_t RESERVED;
5388 
5389     union
5390     {
5391         __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
5392 
5393         struct
5394         {
5395             __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
5396                                          *   the upper-limit value of the frequency.                                   */
5397         } CAULVR_b;
5398     };
5399 
5400     union
5401     {
5402         __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
5403 
5404         struct
5405         {
5406             __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
5407                                          *   the lower-limit value of the frequency.                                   */
5408         } CALLVR_b;
5409     };
5410 
5411     union
5412     {
5413         __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
5414 
5415         struct
5416         {
5417             __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
5418                                          *   the counter value at the time a valid reference signal
5419                                          *   edge is input                                                             */
5420         } CACNTBR_b;
5421     };
5422 } R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
5423 
5424 /* =========================================================================================================================== */
5425 /* ================                                         R_CANFD0                                          ================ */
5426 /* =========================================================================================================================== */
5427 
5428 /**
5429  * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0)
5430  */
5431 
5432 typedef struct                         /*!< (@ 0x40380000) R_CANFD0 Structure                                         */
5433 {
5434     __IOM R_CANFD_CFDC_Type CFDC[1];   /*!< (@ 0x00000000) Channel Control/Status                                     */
5435     __IM uint32_t           RESERVED;
5436 
5437     union
5438     {
5439         __IOM uint32_t CFDGCFG;        /*!< (@ 0x00000014) Global Configuration Register                              */
5440 
5441         struct
5442         {
5443             __IOM uint32_t TPRI  : 1;  /*!< [0..0] Transmission Priority                                              */
5444             __IOM uint32_t DCE   : 1;  /*!< [1..1] DLC Check Enable                                                   */
5445             __IOM uint32_t DRE   : 1;  /*!< [2..2] DLC Replacement Enable                                             */
5446             __IOM uint32_t MME   : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
5447             __IOM uint32_t DCS   : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
5448             __IOM uint32_t CMPOC : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
5449             uint32_t             : 2;
5450             __IOM uint32_t TSP   : 4;  /*!< [11..8] Timestamp Prescaler                                               */
5451             __IOM uint32_t TSSS  : 1;  /*!< [12..12] Timestamp Source Select                                          */
5452             uint32_t             : 3;
5453             __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
5454         } CFDGCFG_b;
5455     };
5456 
5457     union
5458     {
5459         __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000018) Global Control Register                                    */
5460 
5461         struct
5462         {
5463             __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
5464             __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
5465             uint32_t               : 5;
5466             __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
5467             __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
5468             __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
5469             __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
5470             uint32_t               : 4;
5471             __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
5472             uint32_t               : 15;
5473         } CFDGCTR_b;
5474     };
5475 
5476     union
5477     {
5478         __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000001C) Global Status Register                                     */
5479 
5480         struct
5481         {
5482             __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
5483             __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
5484             __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
5485             __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
5486             uint32_t               : 28;
5487         } CFDGSTS_b;
5488     };
5489 
5490     union
5491     {
5492         __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000020) Global Error Flag Register                                 */
5493 
5494         struct
5495         {
5496             __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
5497             __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
5498             __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
5499             __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD message payload overflow Flag                               */
5500             uint32_t             : 12;
5501             __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
5502             uint32_t             : 15;
5503         } CFDGERFL_b;
5504     };
5505 
5506     union
5507     {
5508         __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000024) Global Timestamp Counter Register                          */
5509 
5510         struct
5511         {
5512             __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
5513             uint32_t         : 16;
5514         } CFDGTSC_b;
5515     };
5516 
5517     union
5518     {
5519         __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000028) Global Acceptance Filter List Entry Control Register       */
5520 
5521         struct
5522         {
5523             __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
5524             uint32_t              : 4;
5525             __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
5526             uint32_t              : 23;
5527         } CFDGAFLECTR_b;
5528     };
5529 
5530     union
5531     {
5532         __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000002C) Global Acceptance Filter List Configuration Register
5533                                         *                  0                                                          */
5534 
5535         struct
5536         {
5537             __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
5538             uint32_t            : 7;
5539             __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
5540             uint32_t            : 7;
5541         } CFDGAFLCFG0_b;
5542     };
5543 
5544     union
5545     {
5546         __IOM uint32_t CFDRMNB;        /*!< (@ 0x00000030) RX Message Buffer Number Register                          */
5547 
5548         struct
5549         {
5550             __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
5551             __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
5552             uint32_t             : 21;
5553         } CFDRMNB_b;
5554     };
5555 
5556     union
5557     {
5558         __IOM uint32_t CFDRMND0;       /*!< (@ 0x00000034) RX Message Buffer New Data Register 0                      */
5559 
5560         struct
5561         {
5562             __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
5563         } CFDRMND0_b;
5564     };
5565 
5566     union
5567     {
5568         __IOM uint32_t CFDRMIEC;       /*!< (@ 0x00000038) RX Message Buffer Interrupt Enable Configuration
5569                                         *                  Register                                                   */
5570 
5571         struct
5572         {
5573             __IOM uint32_t RMIE : 32;  /*!< [31..0] RX Message Buffer Interrupt Enable                                */
5574         } CFDRMIEC_b;
5575     };
5576 
5577     union
5578     {
5579         __IOM uint32_t CFDRFCC[2];     /*!< (@ 0x0000003C) RX FIFO Configuration / Control Registers                  */
5580 
5581         struct
5582         {
5583             __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
5584             __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
5585             uint32_t              : 2;
5586             __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
5587             uint32_t              : 1;
5588             __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
5589             uint32_t              : 1;
5590             __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
5591             __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
5592             uint32_t              : 16;
5593         } CFDRFCC_b[2];
5594     };
5595 
5596     union
5597     {
5598         __IOM uint32_t CFDRFSTS[2];    /*!< (@ 0x00000044) RX FIFO Status Registers                                   */
5599 
5600         struct
5601         {
5602             __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
5603             __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
5604             __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
5605             __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
5606             uint32_t             : 4;
5607             __IM uint32_t RFMC   : 8;  /*!< [15..8] RX FIFO Message Count                                             */
5608             uint32_t             : 16;
5609         } CFDRFSTS_b[2];
5610     };
5611 
5612     union
5613     {
5614         __IOM uint32_t CFDRFPCTR[2];   /*!< (@ 0x0000004C) RX FIFO Pointer Control Registers                          */
5615 
5616         struct
5617         {
5618             __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
5619             uint32_t           : 24;
5620         } CFDRFPCTR_b[2];
5621     };
5622 
5623     union
5624     {
5625         __IOM uint32_t CFDCFCC[1];     /*!< (@ 0x00000054) Common FIFO Configuration / Control Registers              */
5626 
5627         struct
5628         {
5629             __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
5630             __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
5631             __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
5632             uint32_t              : 1;
5633             __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
5634             uint32_t              : 1;
5635             __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
5636             __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
5637             __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
5638             __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
5639             __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
5640             __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
5641             __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
5642             __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
5643         } CFDCFCC_b[1];
5644     };
5645 
5646     union
5647     {
5648         __IOM uint32_t CFDCFSTS[1];    /*!< (@ 0x00000058) Common FIFO Status Registers                               */
5649 
5650         struct
5651         {
5652             __IM uint32_t  CFEMP  : 1; /*!< [0..0] Common FIFO Empty                                                  */
5653             __IM uint32_t  CFFLL  : 1; /*!< [1..1] Common FIFO Full                                                   */
5654             __IOM uint32_t CFMLT  : 1; /*!< [2..2] Common FIFO Message Lost                                           */
5655             __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
5656             __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
5657             uint32_t              : 3;
5658             __IM uint32_t CFMC    : 8; /*!< [15..8] Common FIFO Message Count                                         */
5659             uint32_t              : 16;
5660         } CFDCFSTS_b[1];
5661     };
5662 
5663     union
5664     {
5665         __IOM uint32_t CFDCFPCTR[1];   /*!< (@ 0x0000005C) Common FIFO Pointer Control Registers                      */
5666 
5667         struct
5668         {
5669             __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
5670             uint32_t           : 24;
5671         } CFDCFPCTR_b[1];
5672     };
5673 
5674     union
5675     {
5676         __IM uint32_t CFDFESTS;        /*!< (@ 0x00000060) FIFO Empty Status Register                                 */
5677 
5678         struct
5679         {
5680             __IM uint32_t RFXEMP : 2;  /*!< [1..0] RX FIF0 Empty Status                                               */
5681             uint32_t             : 6;
5682             __IM uint32_t CFXEMP : 1;  /*!< [8..8] Common FIF0 Empty Status                                           */
5683             uint32_t             : 23;
5684         } CFDFESTS_b;
5685     };
5686 
5687     union
5688     {
5689         __IM uint32_t CFDFFSTS;        /*!< (@ 0x00000064) FIFO Full Status Register                                  */
5690 
5691         struct
5692         {
5693             __IM uint32_t RFXFLL : 2;  /*!< [1..0] RX FIF0 Full Status                                                */
5694             uint32_t             : 6;
5695             __IM uint32_t CFXFLL : 1;  /*!< [8..8] Common FIF0 Full Status                                            */
5696             uint32_t             : 23;
5697         } CFDFFSTS_b;
5698     };
5699 
5700     union
5701     {
5702         __IM uint32_t CFDFMSTS;        /*!< (@ 0x00000068) FIFO Message Lost Status Register                          */
5703 
5704         struct
5705         {
5706             __IM uint32_t RFXMLT : 2;  /*!< [1..0] RX FIFO Msg Lost Status                                            */
5707             uint32_t             : 6;
5708             __IM uint32_t CFXMLT : 1;  /*!< [8..8] Common FIFO Msg Lost Status                                        */
5709             uint32_t             : 23;
5710         } CFDFMSTS_b;
5711     };
5712 
5713     union
5714     {
5715         __IOM uint32_t CFDRFISTS;      /*!< (@ 0x0000006C) RX FIFO Interrupt Flag Status Register                     */
5716 
5717         struct
5718         {
5719             __IM uint32_t RFXIF : 1;   /*!< [0..0] RX FIFO[x] Interrupt Flag Status                                   */
5720             uint32_t            : 31;
5721         } CFDRFISTS_b;
5722     };
5723 
5724     union
5725     {
5726         __IOM uint8_t CFDTMC[4];       /*!< (@ 0x00000070) TX Message Buffer Control Registers                        */
5727 
5728         struct
5729         {
5730             __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
5731             __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
5732             __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
5733             uint8_t             : 5;
5734         } CFDTMC_b[4];
5735     };
5736 
5737     union
5738     {
5739         __IOM uint8_t CFDTMSTS[4];     /*!< (@ 0x00000074) TX Message Buffer Status Registers                         */
5740 
5741         struct
5742         {
5743             __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
5744             __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
5745             __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
5746             __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
5747             uint8_t              : 3;
5748         } CFDTMSTS_b[4];
5749     };
5750 
5751     union
5752     {
5753         __IM uint32_t CFDTMTRSTS[1];       /*!< (@ 0x00000078) TX Message Buffer Transmission Request Status
5754                                             *                  Register                                                   */
5755 
5756         struct
5757         {
5758             __IM uint32_t CFDTMTRSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Request Status                      */
5759             uint32_t                  : 28;
5760         } CFDTMTRSTS_b[1];
5761     };
5762 
5763     union
5764     {
5765         __IM uint32_t CFDTMTARSTS[1];       /*!< (@ 0x0000007C) TX Message Buffer Transmission Abort Request
5766                                              *                  Status Register                                            */
5767 
5768         struct
5769         {
5770             __IM uint32_t CFDTMTARSTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Request Status                */
5771             uint32_t                   : 28;
5772         } CFDTMTARSTS_b[1];
5773     };
5774 
5775     union
5776     {
5777         __IM uint32_t CFDTMTCSTS[1];       /*!< (@ 0x00000080) TX Message Buffer Transmission Completion Status
5778                                             *                  Register                                                   */
5779 
5780         struct
5781         {
5782             __IM uint32_t CFDTMTCSTSg : 4; /*!< [3..0] TX Message Buffer Transmission Completion Status                   */
5783             uint32_t                  : 28;
5784         } CFDTMTCSTS_b[1];
5785     };
5786 
5787     union
5788     {
5789         __IM uint32_t CFDTMTASTS[1];       /*!< (@ 0x00000084) TX Message Buffer Transmission Abort Status Register       */
5790 
5791         struct
5792         {
5793             __IM uint32_t CFDTMTASTSg : 4; /*!< [3..0] TX Message Buffer Transmission abort Status                        */
5794             uint32_t                  : 28;
5795         } CFDTMTASTS_b[1];
5796     };
5797 
5798     union
5799     {
5800         __IOM uint32_t CFDTMIEC[1];    /*!< (@ 0x00000088) TX Message Buffer Interrupt Enable Configuration
5801                                         *                  Register                                                   */
5802 
5803         struct
5804         {
5805             __IOM uint32_t TMIEg : 4;  /*!< [3..0] TX Message Buffer Interrupt Enable                                 */
5806             uint32_t             : 28;
5807         } CFDTMIEC_b[1];
5808     };
5809 
5810     union
5811     {
5812         __IOM uint32_t CFDTXQCC0[1];    /*!< (@ 0x0000008C) TX Queue Configuration / Control Registers 0               */
5813 
5814         struct
5815         {
5816             __IOM uint32_t TXQE    : 1; /*!< [0..0] TX Queue Enable                                                    */
5817             uint32_t               : 4;
5818             __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
5819             uint32_t               : 1;
5820             __IOM uint32_t TXQIM   : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
5821             __IOM uint32_t TXQDC   : 2; /*!< [9..8] TX Queue Depth Configuration                                       */
5822             uint32_t               : 22;
5823         } CFDTXQCC0_b[1];
5824     };
5825 
5826     union
5827     {
5828         __IOM uint32_t CFDTXQSTS0[1];   /*!< (@ 0x00000090) TX Queue Status Registers 0                                */
5829 
5830         struct
5831         {
5832             __IM uint32_t  TXQEMP  : 1; /*!< [0..0] TX Queue Empty                                                     */
5833             __IM uint32_t  TXQFLL  : 1; /*!< [1..1] TX Queue Full                                                      */
5834             __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
5835             uint32_t               : 5;
5836             __IM uint32_t TXQMC    : 6; /*!< [13..8] TX Queue Message Count                                            */
5837             uint32_t               : 18;
5838         } CFDTXQSTS0_b[1];
5839     };
5840 
5841     union
5842     {
5843         __IOM uint32_t CFDTXQPCTR0[1]; /*!< (@ 0x00000094) TX Queue Pointer Control Registers 0                       */
5844 
5845         struct
5846         {
5847             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
5848             uint32_t            : 24;
5849         } CFDTXQPCTR0_b[1];
5850     };
5851 
5852     union
5853     {
5854         __IOM uint32_t CFDTHLCC[1];    /*!< (@ 0x00000098) TX History List Configuration / Control Register           */
5855 
5856         struct
5857         {
5858             __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
5859             uint32_t              : 7;
5860             __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
5861             __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
5862             __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
5863             uint32_t              : 21;
5864         } CFDTHLCC_b[1];
5865     };
5866 
5867     union
5868     {
5869         __IOM uint32_t CFDTHLSTS[1];   /*!< (@ 0x0000009C) TX History List Status Register                            */
5870 
5871         struct
5872         {
5873             __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
5874             __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
5875             __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
5876             __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
5877             uint32_t              : 4;
5878             __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
5879             uint32_t              : 18;
5880         } CFDTHLSTS_b[1];
5881     };
5882 
5883     union
5884     {
5885         __IOM uint32_t CFDTHLPCTR[1];  /*!< (@ 0x000000A0) TX History List Pointer Control Registers                  */
5886 
5887         struct
5888         {
5889             __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
5890             uint32_t            : 24;
5891         } CFDTHLPCTR_b[1];
5892     };
5893 
5894     union
5895     {
5896         __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x000000A4) Global TX Interrupt Status Register 0                      */
5897 
5898         struct
5899         {
5900             __IM uint32_t TSIF0  : 1;  /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
5901             __IM uint32_t TAIF0  : 1;  /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
5902             __IM uint32_t TQIF0  : 1;  /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
5903             __IM uint32_t CFTIF0 : 1;  /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
5904             __IM uint32_t THIF0  : 1;  /*!< [4..4] TX History List Interrupt Channel 0                                */
5905             uint32_t             : 27;
5906         } CFDGTINTSTS0_b;
5907     };
5908 
5909     union
5910     {
5911         __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x000000A8) Global Test Configuration Register                         */
5912 
5913         struct
5914         {
5915             uint32_t             : 16;
5916             __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
5917             uint32_t             : 6;
5918         } CFDGTSTCFG_b;
5919     };
5920 
5921     union
5922     {
5923         __IOM uint32_t CFDGTSTCTR;     /*!< (@ 0x000000AC) Global Test Control Register                               */
5924 
5925         struct
5926         {
5927             uint32_t            : 2;
5928             __IOM uint32_t RTME : 1;   /*!< [2..2] RAM Test Mode Enable                                               */
5929             uint32_t            : 29;
5930         } CFDGTSTCTR_b;
5931     };
5932 
5933     union
5934     {
5935         __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x000000B0) Global FD Configuration register                           */
5936 
5937         struct
5938         {
5939             __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
5940             uint32_t              : 7;
5941             __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
5942             uint32_t              : 22;
5943         } CFDGFDCFG_b;
5944     };
5945     __IM uint32_t RESERVED1;
5946 
5947     union
5948     {
5949         __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x000000B8) Global Lock Key Register                                   */
5950 
5951         struct
5952         {
5953             __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
5954             uint32_t           : 16;
5955         } CFDGLOCKK_b;
5956     };
5957     __IM uint32_t RESERVED2;
5958 
5959     union
5960     {
5961         __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x000000C0) Global AFL Ignore Entry Register                           */
5962 
5963         struct
5964         {
5965             __IOM uint32_t IRN : 5;    /*!< [4..0] Ignore Rule Number                                                 */
5966             uint32_t           : 27;
5967         } CFDGAFLIGNENT_b;
5968     };
5969 
5970     union
5971     {
5972         __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x000000C4) Global AFL Ignore Control Register                         */
5973 
5974         struct
5975         {
5976             __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
5977             uint32_t            : 7;
5978             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
5979             uint32_t            : 16;
5980         } CFDGAFLIGNCTR_b;
5981     };
5982 
5983     union
5984     {
5985         __IOM uint32_t CFDCDTCT;        /*!< (@ 0x000000C8) DMA Transfer Control Register                              */
5986 
5987         struct
5988         {
5989             __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
5990             __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
5991             uint32_t               : 6;
5992             __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
5993             uint32_t               : 23;
5994         } CFDCDTCT_b;
5995     };
5996 
5997     union
5998     {
5999         __IM uint32_t CFDCDTSTS;         /*!< (@ 0x000000CC) DMA Transfer Status Register                               */
6000 
6001         struct
6002         {
6003             __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
6004             __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
6005             uint32_t                : 6;
6006             __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
6007                                           *   0                                                                         */
6008             uint32_t : 23;
6009         } CFDCDTSTS_b;
6010     };
6011     __IM uint32_t RESERVED3[2];
6012 
6013     union
6014     {
6015         __IOM uint32_t CFDGRSTC;       /*!< (@ 0x000000D8) Global SW reset Register                                   */
6016 
6017         struct
6018         {
6019             __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
6020             uint32_t            : 7;
6021             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
6022             uint32_t            : 16;
6023         } CFDGRSTC_b;
6024     };
6025     __IM uint32_t              RESERVED4[9];
6026     __IOM R_CANFD_CFDC2_Type   CFDC2[1];    /*!< (@ 0x00000100) Channel Configuration Registers                            */
6027     __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers                    */
6028     __IM uint32_t              RESERVED5[24];
6029 
6030     union
6031     {
6032         __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00000280) RAM Test Page Access Registers                             */
6033 
6034         struct
6035         {
6036             __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
6037         } CFDRPGACC_b[64];
6038     };
6039     __IM uint32_t             RESERVED6[104];
6040     __IOM R_CANFD_CFDRF_Type  CFDRF[2];  /*!< (@ 0x00000520) RX FIFO Access Registers                                   */
6041     __IOM R_CANFD_CFDCF_Type  CFDCF[1];  /*!< (@ 0x000005B8) Common FIFO Access Registers                               */
6042     __IOM R_CANFD_CFDTM_Type  CFDTM[4];  /*!< (@ 0x00000604) TX Message Buffer Access Registers                         */
6043     __IM uint32_t             RESERVED7[3];
6044     __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List                                    */
6045     __IM uint32_t             RESERVED8[118];
6046     __IOM R_CANFD_CFDRM_Type  CFDRM[4];  /*!< (@ 0x00000920) RX Message Buffer Access Clusters                          */
6047 } R_CANFD_Type;                          /*!< Size = 6432 (0x1920)                                                      */
6048 
6049 /* =========================================================================================================================== */
6050 /* ================                                           R_CRC                                           ================ */
6051 /* =========================================================================================================================== */
6052 
6053 /**
6054  * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
6055  */
6056 
6057 typedef struct                         /*!< (@ 0x40310000) R_CRC Structure                                            */
6058 {
6059     union
6060     {
6061         __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
6062 
6063         struct
6064         {
6065             __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
6066             uint8_t              : 3;
6067             __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
6068             __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
6069         } CRCCR0_b;
6070     };
6071 
6072     union
6073     {
6074         __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
6075 
6076         struct
6077         {
6078             uint8_t              : 6;
6079             __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
6080             __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
6081         } CRCCR1_b;
6082     };
6083     __IM uint16_t RESERVED;
6084 
6085     union
6086     {
6087         union
6088         {
6089             __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
6090 
6091             struct
6092             {
6093                 __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
6094             } CRCDIR_b;
6095         };
6096 
6097         union
6098         {
6099             __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
6100 
6101             struct
6102             {
6103                 __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
6104                                               *   )                                                                         */
6105             } CRCDIR_BY_b;
6106         };
6107     };
6108 
6109     union
6110     {
6111         union
6112         {
6113             __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
6114 
6115             struct
6116             {
6117                 __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
6118             } CRCDOR_b;
6119         };
6120 
6121         union
6122         {
6123             __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
6124 
6125             struct
6126             {
6127                 __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
6128                                                 *   )                                                                         */
6129             } CRCDOR_HA_b;
6130         };
6131 
6132         union
6133         {
6134             __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
6135 
6136             struct
6137             {
6138                 __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
6139             } CRCDOR_BY_b;
6140         };
6141     };
6142 
6143     union
6144     {
6145         __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
6146 
6147         struct
6148         {
6149             __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
6150             uint16_t             : 2;
6151         } CRCSAR_b;
6152     };
6153     __IM uint16_t RESERVED1;
6154 } R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
6155 
6156 /* =========================================================================================================================== */
6157 /* ================                                           R_DAC                                           ================ */
6158 /* =========================================================================================================================== */
6159 
6160 /**
6161  * @brief D/A Converter (R_DAC)
6162  */
6163 
6164 typedef struct                         /*!< (@ 0x40333000) R_DAC Structure                                            */
6165 {
6166     union
6167     {
6168         __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
6169 
6170         struct
6171         {
6172             __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
6173                                         *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
6174                                         *   = 1, the low-order 4 bits are fixed to 0: left justified
6175                                         *   format.                                                                   */
6176         } DADR_b[2];
6177     };
6178 
6179     union
6180     {
6181         __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
6182 
6183         struct
6184         {
6185             uint8_t             : 5;
6186             __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
6187             __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
6188             __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
6189         } DACR_b;
6190     };
6191 
6192     union
6193     {
6194         __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
6195 
6196         struct
6197         {
6198             uint8_t             : 7;
6199             __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
6200         } DADPR_b;
6201     };
6202 
6203     union
6204     {
6205         __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
6206 
6207         struct
6208         {
6209             uint8_t              : 7;
6210             __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
6211         } DAADSCR_b;
6212     };
6213 
6214     union
6215     {
6216         __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
6217 
6218         struct
6219         {
6220             __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
6221             uint8_t           : 5;
6222         } DAVREFCR_b;
6223     };
6224 
6225     union
6226     {
6227         __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
6228 
6229         struct
6230         {
6231             uint8_t              : 6;
6232             __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
6233             __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
6234         } DAAMPCR_b;
6235     };
6236 
6237     union
6238     {
6239         __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
6240 
6241         struct
6242         {
6243             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
6244             uint8_t              : 7;
6245         } DAPC_b;
6246     };
6247     __IM uint16_t RESERVED[9];
6248 
6249     union
6250     {
6251         __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
6252 
6253         struct
6254         {
6255             uint8_t              : 6;
6256             __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
6257                                         *   to wait for stabilization of the output amplifier of D/A
6258                                         *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
6259                                         *   but the conversion result D/A is not output from channel
6260                                         *   0. When the DAASW0 bit is 0, the stabilization wait time
6261                                         *   stops, and the D/A conversion result of channel 0 is output
6262                                         *   through the output amplifier.                                             */
6263             __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
6264                                         *   to wait for stabilization of the output amplifier of D/A
6265                                         *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
6266                                         *   but the conversion result D/A is not output from channel
6267                                         *   1. When the DAASW1 bit is 0, the stabilization wait time
6268                                         *   stops, and the D/A conversion result of channel 1 is output
6269                                         *   through the output amplifier.                                             */
6270         } DAASWCR_b;
6271     };
6272     __IM uint8_t  RESERVED1;
6273     __IM uint16_t RESERVED2[2129];
6274 
6275     union
6276     {
6277         __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
6278 
6279         struct
6280         {
6281             __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
6282                                          *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
6283                                          *   select unit 0 as the target synchronous unit for the MCU.
6284                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
6285                                          *   conversions, select the target unit in this register in
6286                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
6287                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
6288                                          *   is set to 0.                                                              */
6289             __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
6290                                          *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
6291                                          *   select unit 1 as the target synchronous unit for the MCU.
6292                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
6293                                          *   conversions, select the target unit in this register in
6294                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
6295                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
6296                                          *   is set to 0.                                                              */
6297             uint8_t : 6;
6298         } DAADUSR_b;
6299     };
6300     __IM uint8_t  RESERVED3;
6301     __IM uint16_t RESERVED4;
6302 } R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
6303 
6304 /* =========================================================================================================================== */
6305 /* ================                                          R_DEBUG                                          ================ */
6306 /* =========================================================================================================================== */
6307 
6308 /**
6309  * @brief Debug Function (R_DEBUG)
6310  */
6311 
6312 typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
6313 {
6314     union
6315     {
6316         __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
6317 
6318         struct
6319         {
6320             uint32_t                   : 28;
6321             __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
6322             __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
6323             uint32_t                   : 2;
6324         } DBGSTR_b;
6325     };
6326     __IM uint32_t RESERVED[3];
6327 
6328     union
6329     {
6330         __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
6331 
6332         struct
6333         {
6334             __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
6335             __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
6336             uint32_t                     : 12;
6337             __IOM uint32_t DBGSTOP_TIM   : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt                            */
6338             __IOM uint32_t DBGSTOP_SIR   : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt              */
6339             __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
6340             __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
6341             __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
6342             uint32_t                     : 5;
6343             __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
6344             __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
6345             uint32_t                     : 5;
6346             __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
6347         } DBGSTOPCR_b;
6348     };
6349     __IM uint32_t RESERVED1[123];
6350 
6351     union
6352     {
6353         __IOM uint32_t FSBLSTAT;       /*!< (@ 0x00000200) First Stage Boot Loader Status Register                    */
6354 
6355         struct
6356         {
6357             __IOM uint32_t CS     : 1; /*!< [0..0] FSBL completion status.                                            */
6358             __IOM uint32_t RS     : 1; /*!< [1..1] FSBL result status.                                                */
6359             uint32_t              : 6;
6360             __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution            */
6361             uint32_t              : 21;
6362         } FSBLSTAT_b;
6363     };
6364 } R_DEBUG_Type;                        /*!< Size = 516 (0x204)                                                        */
6365 
6366 /* =========================================================================================================================== */
6367 /* ================                                           R_DMA                                           ================ */
6368 /* =========================================================================================================================== */
6369 
6370 /**
6371  * @brief DMA Controller Common (R_DMA)
6372  */
6373 
6374 typedef struct                         /*!< (@ 0x4000A800) R_DMA Structure                                            */
6375 {
6376     union
6377     {
6378         __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
6379 
6380         struct
6381         {
6382             __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
6383             uint8_t            : 7;
6384         } DMAST_b;
6385     };
6386     __IM uint8_t  RESERVED;
6387     __IM uint16_t RESERVED1;
6388     __IM uint32_t RESERVED2[15];
6389 
6390     union
6391     {
6392         __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */
6393 
6394         struct
6395         {
6396             __IM uint32_t DMECH    : 3; /*!< [2..0] DMAC Error channel                                                 */
6397             uint32_t               : 5;
6398             __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
6399             uint32_t               : 7;
6400             __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
6401             uint32_t               : 15;
6402         } DMECHR_b;
6403     };
6404     __IM uint32_t RESERVED3[15];
6405 
6406     union
6407     {
6408         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000080) DMAC Event Link Setting Register                           */
6409 
6410         struct
6411         {
6412             __IOM uint32_t DELS : 9;   /*!< [8..0] DMAC Event Link Select                                             */
6413             uint32_t            : 7;
6414             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
6415                                         *   IR flag is prohibited.                                                    */
6416             uint32_t : 15;
6417         } DELSR_b[8];
6418     };
6419 } R_DMA_Type;                          /*!< Size = 160 (0xa0)                                                         */
6420 
6421 /* =========================================================================================================================== */
6422 /* ================                                          R_DMAC0                                          ================ */
6423 /* =========================================================================================================================== */
6424 
6425 /**
6426  * @brief DMA Controller (R_DMAC0)
6427  */
6428 
6429 typedef struct                         /*!< (@ 0x4000A000) R_DMAC0 Structure                                          */
6430 {
6431     union
6432     {
6433         __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
6434 
6435         struct
6436         {
6437             __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
6438         } DMSAR_b;
6439     };
6440 
6441     union
6442     {
6443         __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
6444 
6445         struct
6446         {
6447             __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
6448         } DMDAR_b;
6449     };
6450 
6451     union
6452     {
6453         __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
6454 
6455         struct
6456         {
6457             __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
6458             __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
6459             uint32_t              : 6;
6460         } DMCRA_b;
6461     };
6462 
6463     union
6464     {
6465         __IOM uint32_t DMCRB;           /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
6466 
6467         struct
6468         {
6469             __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
6470                                          *   transfer counter.                                                         */
6471             __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
6472                                          *   repeat transfer operations.                                               */
6473         } DMCRB_b;
6474     };
6475 
6476     union
6477     {
6478         __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
6479 
6480         struct
6481         {
6482             __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
6483             uint16_t            : 6;
6484             __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
6485             __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
6486             uint16_t            : 1;
6487             __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
6488             __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
6489         } DMTMD_b;
6490     };
6491     __IM uint8_t RESERVED;
6492 
6493     union
6494     {
6495         __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
6496 
6497         struct
6498         {
6499             __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
6500                                         *   Enable                                                                    */
6501             __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
6502                                         *   Enable                                                                    */
6503             __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
6504             __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
6505             __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
6506             uint8_t             : 3;
6507         } DMINT_b;
6508     };
6509 
6510     union
6511     {
6512         __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
6513 
6514         struct
6515         {
6516             __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
6517                                         *   extended repeat area on the destination address. For details
6518                                         *   on the settings.                                                          */
6519             __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
6520             __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
6521             __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
6522                                         *   repeat area on the source address. For details on the settings.           */
6523             __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
6524             __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
6525         } DMAMD_b;
6526     };
6527     __IM uint16_t RESERVED1;
6528 
6529     union
6530     {
6531         __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
6532 
6533         struct
6534         {
6535             __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
6536                                         *   as the address update mode for transfer source or destination.            */
6537         } DMOFR_b;
6538     };
6539 
6540     union
6541     {
6542         __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
6543 
6544         struct
6545         {
6546             __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
6547             uint8_t           : 7;
6548         } DMCNT_b;
6549     };
6550 
6551     union
6552     {
6553         __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
6554 
6555         struct
6556         {
6557             __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
6558             uint8_t             : 3;
6559             __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
6560             uint8_t             : 3;
6561         } DMREQ_b;
6562     };
6563 
6564     union
6565     {
6566         __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */
6567 
6568         struct
6569         {
6570             __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
6571             uint8_t            : 3;
6572             __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
6573             uint8_t            : 2;
6574             __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
6575         } DMSTS_b;
6576     };
6577     __IM uint8_t   RESERVED2;
6578     __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
6579     __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */
6580 
6581     union
6582     {
6583         __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */
6584 
6585         struct
6586         {
6587             __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
6588                                          *   mode                                                                      */
6589             __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
6590                                          *   mode                                                                      */
6591         } DMSBS_b;
6592     };
6593 
6594     union
6595     {
6596         __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */
6597 
6598         struct
6599         {
6600             __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
6601                                          *   mode                                                                      */
6602             __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
6603                                          *   mode                                                                      */
6604         } DMDBS_b;
6605     };
6606 
6607     union
6608     {
6609         __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */
6610 
6611         struct
6612         {
6613             __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
6614             uint8_t           : 7;
6615         } DMBWR_b;
6616     };
6617     __IM uint8_t  RESERVED3;
6618     __IM uint16_t RESERVED4;
6619 } R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */
6620 
6621 /* =========================================================================================================================== */
6622 /* ================                                           R_DOC                                           ================ */
6623 /* =========================================================================================================================== */
6624 
6625 /**
6626  * @brief Data Operation Circuit (R_DOC)
6627  */
6628 
6629 typedef struct                         /*!< (@ 0x40311000) R_DOC Structure                                            */
6630 {
6631     union
6632     {
6633         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
6634 
6635         struct
6636         {
6637             __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
6638             __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
6639             uint8_t               : 2;
6640             __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
6641             __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
6642             uint8_t               : 1;
6643         } DOCR_b;
6644     };
6645     __IM uint8_t RESERVED;
6646 
6647     union
6648     {
6649         __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
6650 
6651         struct
6652         {
6653             __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
6654                                         *   use in the operations are stored.                                         */
6655         } DODIR_b;
6656     };
6657 
6658     union
6659     {
6660         __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
6661 
6662         struct
6663         {
6664             __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
6665                                         *   in data comparison mode. This register also stores the
6666                                         *   results of operations in data addition and data subtraction
6667                                         *   modes.                                                                    */
6668         } DODSR_b;
6669     };
6670 } R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
6671 
6672 /* =========================================================================================================================== */
6673 /* ================                                           R_DRW                                           ================ */
6674 /* =========================================================================================================================== */
6675 
6676 /**
6677  * @brief 2D Drawing Engine (R_DRW)
6678  */
6679 
6680 typedef struct                         /*!< (@ 0x40344000) R_DRW Structure                                            */
6681 {
6682     union
6683     {
6684         union
6685         {
6686             __OM uint32_t CONTROL;               /*!< (@ 0x00000000) Geometry Control Register                                  */
6687 
6688             struct
6689             {
6690                 __OM uint32_t LIM1ENABLE    : 1; /*!< [0..0] Enable limiter 1                                                   */
6691                 __OM uint32_t LIM2ENABLE    : 1; /*!< [1..1] Enable limiter 2                                                   */
6692                 __OM uint32_t LIM3ENABLE    : 1; /*!< [2..2] Enable limiter 3                                                   */
6693                 __OM uint32_t LIM4ENABLE    : 1; /*!< [3..3] Enable limiter 4                                                   */
6694                 __OM uint32_t LIM5ENABLE    : 1; /*!< [4..4] Enable limiter 5                                                   */
6695                 __OM uint32_t LIM6ENABLE    : 1; /*!< [5..5] Enable limiter 6                                                   */
6696                 __OM uint32_t QUAD1ENABLE   : 1; /*!< [6..6] Enable quadratic coupling of limiters 1 and 2                      */
6697                 __OM uint32_t QUAD2ENABLE   : 1; /*!< [7..7] Enable quadratic coupling of limiters 3 and 4                      */
6698                 __OM uint32_t QUAD3ENABLE   : 1; /*!< [8..8] Enable quadratic coupling of limiters 5 and 6                      */
6699                 __OM uint32_t LIM1THRESHOLD : 1; /*!< [9..9] Enable limiter 1 threshold mode                                    */
6700                 __OM uint32_t LIM2THRESHOLD : 1; /*!< [10..10] Enable limiter 2 threshold mode                                  */
6701                 __OM uint32_t LIM3THRESHOLD : 1; /*!< [11..11] Enable limiter 3 threshold mode                                  */
6702                 __OM uint32_t LIM4THRESHOLD : 1; /*!< [12..12] Enable limiter 4 threshold mode                                  */
6703                 __OM uint32_t LIM5THRESHOLD : 1; /*!< [13..13] Enable limiter 5 threshold mode                                  */
6704                 __OM uint32_t LIM6THRESHOLD : 1; /*!< [14..14] Enable limiter 6 threshold mode                                  */
6705                 __OM uint32_t BAND1ENABLE   : 1; /*!< [15..15] Enable band postprocess for limiter 1 (see L1BAND)               */
6706                 __OM uint32_t BAND2ENABLE   : 1; /*!< [16..16] Enable band postprocess for limiter 1 (see L1BAND)               */
6707                 __OM uint32_t UNION12       : 1; /*!< [17..17] Combine limter 1 & 2 as union (output is called A)               */
6708                 __OM uint32_t UNION34       : 1; /*!< [18..18] Combine limter 3 & 4 as union (output is called B)               */
6709                 __OM uint32_t UNION56       : 1; /*!< [19..19] Combine limter 5 & 6 as union (output is called D)               */
6710                 __OM uint32_t UNIONAB       : 1; /*!< [20..20] Combine outputs A & B as union (output is called C)              */
6711                 __OM uint32_t UNIONCD       : 1; /*!< [21..21] Combine outputs C & D as union (output is final)                 */
6712                 __OM uint32_t SPANABORT     : 1; /*!< [22..22] Shape is horizontally convex, only a single span per
6713                                                   *   scanline                                                                  */
6714                 __OM uint32_t SPANSTORE : 1;     /*!< [23..23] Nextline span start is always equal or left to current-line
6715                                                   *   span start                                                                */
6716                 uint32_t : 8;
6717             } CONTROL_b;
6718         };
6719 
6720         union
6721         {
6722             __IM uint32_t STATUS;               /*!< (@ 0x00000000) Status Control Register                                    */
6723 
6724             struct
6725             {
6726                 __IM uint32_t BUSYENUM     : 1; /*!< [0..0] Enumeration unit status                                            */
6727                 __IM uint32_t BUSYWRITE    : 1; /*!< [1..1] Framebuffer writeback status                                       */
6728                 __IM uint32_t CACHEDIRTY   : 1; /*!< [2..2] Framebuffer cache status                                           */
6729                 __IM uint32_t DLISTACTIVE  : 1; /*!< [3..3] Display list reader status                                         */
6730                 __IM uint32_t ENUMIRQ      : 1; /*!< [4..4] enumeration finished interrupt triggered                           */
6731                 __IM uint32_t DLISTIRQ     : 1; /*!< [5..5] display list finished interrupt triggered                          */
6732                 __IM uint32_t BUSIRQ       : 1; /*!< [6..6] bus error interrupt triggered                                      */
6733                 uint32_t                   : 1;
6734                 __IM uint32_t BUSERRMFB    : 1; /*!< [8..8] framebuffer bus error interrupt triggered                          */
6735                 __IM uint32_t BUSERRMTXMRL : 1; /*!< [9..9] texture bus error interrupt triggered                              */
6736                 __IM uint32_t BUSERRMDL    : 1; /*!< [10..10] display list bus error interrupt triggered                       */
6737                 uint32_t                   : 21;
6738             } STATUS_b;
6739         };
6740     };
6741 
6742     union
6743     {
6744         union
6745         {
6746             __OM uint32_t CONTROL2;                /*!< (@ 0x00000004) Surface Control Register                                   */
6747 
6748             struct
6749             {
6750                 __OM uint32_t PATTERNENABLE : 1;   /*!< [0..0] Pixel source is a pattern color (blend of COLOR1 and
6751                                                     *   COLOR2 depending on PATTERN and pattern index)                            */
6752                 __OM uint32_t TEXTUREENABLE : 1;   /*!< [1..1] Pixel source is read from texture and used as an alpha
6753                                                     *   to blend between COLOR1 and COLOR2                                        */
6754                 __OM uint32_t PATTERNSOURCEL5 : 1; /*!< [2..2] Limiter 5 is used as pattern index instead of the default
6755                                                     *   U limiter.Limiter 5 can be combined with limiter 6 to form
6756                                                     *   a quadratic limiter which can be used to make quadratic
6757                                                     *   pattern functions to draw radial patterns.                                */
6758                 __OM uint32_t USEACB       : 1;    /*!< [3..3] Alpha blend mode                                                   */
6759                 __OM uint32_t READFORMAT32 : 2;    /*!< [5..4] Bit 4 and 3 of the texture buffer format.See READFORMAT
6760                                                     *   above for description                                                     */
6761                 __OM uint32_t BSFA : 1;            /*!< [6..6] Blend source factor for alpha channel in alpha channel
6762                                                     *   blending mode (USEACB = 1)                                                */
6763                 __OM uint32_t BDFA : 1;            /*!< [7..7] Blend destinetion factor for alpha channel in alpha channel
6764                                                     *   blending mode (USEACB = 1)                                                */
6765                 __OM uint32_t WRITEFORMAT2 : 1;    /*!< [8..8] Bit 3 of framebuffer pixel formatSee WRITEFORMAT above
6766                                                     *   description.                                                              */
6767                 __OM uint32_t BSF : 1;             /*!< [9..9] Blend source factorsrc factor is alpha (factor is 1 per
6768                                                     *   default)                                                                  */
6769                 __OM uint32_t BDF : 1;             /*!< [10..10] Blend destination factordst factor is alpha (factor
6770                                                     *   is 1 per default)                                                         */
6771                 __OM uint32_t BSI : 1;             /*!< [11..11] Blend source factor is invertedsrc factor will be inverted
6772                                                     *   (meaning 1-a or 1-1 depending on BSF)                                     */
6773                 __OM uint32_t BDI : 1;             /*!< [12..12] Blend destination factor is inverteddst factor will
6774                                                     *   be inverted (meaning 1-a or 1-1 depending on BDF)                         */
6775                 __OM uint32_t BC2           : 1;   /*!< [13..13] Blend color 2 instead of framebuffer pixel                       */
6776                 __OM uint32_t TEXTURECLAMPX : 1;   /*!< [14..14] Calculating U limiter outside use textureThe bit describes
6777                                                     *   what happens if the U limiter (x direction in texture space)
6778                                                     *   calculates a U value outside of the used texture                          */
6779                 __OM uint32_t TEXTURECLAMPY : 1;   /*!< [15..15] Calculating V limiter outside use textureThe bit describes
6780                                                     *   what happens if the V limiter (y direction in texture space)
6781                                                     *   calculates a V value outside of the used texture                          */
6782                 __OM uint32_t TEXTUREFILTERX : 1;  /*!< [16..16] Linear filtering on texture U axis                               */
6783                 __OM uint32_t TEXTUREFILTERY : 1;  /*!< [17..17] Linear filtering on texture V axis                               */
6784                 __OM uint32_t READFORMAT10   : 2;  /*!< [19..18] Pixel format of the texture buffer{READFORMAT32,READFORMAT10}0000:
6785                                                     *   8 bpp a(8)0001: 16 bpp RGB(565)0010: 32 bpp aRGB(8888)0011:
6786                                                     *   16 bpp aRGB(4444)0100: 16 bpp aRGB(1555)0101: 8 bpp aCLUT(44)
6787                                                     *   4 bit alpha and 4 bit indexed color1001: 8 bpp CLUT(8)/I(8),
6788                                                     *   8 bit indexed color/luminance1010: 4 bpp CLUT(4)/I(4),
6789                                                     *   4 bit indexed color/luminance1011: 2 bpp CLUT(2)/I(2),
6790                                                     *   2 bit indexed color/luminance 1100: 1 bpp CLUT(1)/I(1),
6791                                                     *   1 bit indexed color/luminance                                             */
6792                 __OM uint32_t WRITEFORMAT10 : 2;   /*!< [21..20] Pixel format of the framebuffer                                  */
6793                 __OM uint32_t WRITEALPHA    : 2;   /*!< [23..22] Writeback alpha source for framebufferSet the 'alpha
6794                                                     *   source' for the framebuffer(USEACB = 0)Blend alpha in color
6795                                                     *   2 instead of framebuffer alpha((USEACB = 1))In not alpha
6796                                                     *   channel blending mode (USEACB = 0):Set the 'alpha source'
6797                                                     *   for the framebuffer.In alpha channel blending mode (USEACB
6798                                                     *   = 1):Blend alpha in color 2 instead of framebuffer alpha00B:
6799                                                     *   BC2A = 1: use alpha from framebuffer as destination (DST_A)else:
6800                                                     *   BC2A = 0: use alpha in color 2 as destination (DST_A)                     */
6801                 __OM uint32_t RLEENABLE    : 1;    /*!< [24..24] RLE enable                                                       */
6802                 __OM uint32_t CLUTENABLE   : 1;    /*!< [25..25] CLUT enable                                                      */
6803                 __OM uint32_t COLKEYENABLE : 1;    /*!< [26..26] color keying enable                                              */
6804                 __OM uint32_t CLUTFORMAT   : 1;    /*!< [27..27] Format of the CLUT                                               */
6805                 __OM uint32_t BSIA         : 1;    /*!< [28..28] Blend source factor inverted in alpha channel (USEACB
6806                                                     *   = 1)                                                                      */
6807                 __OM uint32_t BDIA : 1;            /*!< [29..29] Blend destination factor inverted in alpha channel
6808                                                     *   (USEACB = 1)                                                              */
6809                 __OM uint32_t RLEPIXELWIDTH : 2;   /*!< [31..30] Texel width for RLE unit                                         */
6810             } CONTROL2_b;
6811         };
6812 
6813         union
6814         {
6815             __IM uint32_t HWREVISION;          /*!< (@ 0x00000004) Hardware Version and Feature Set ID Register               */
6816 
6817             struct
6818             {
6819                 __IM uint32_t REV        : 12; /*!< [11..0] Revision number                                                   */
6820                 uint32_t                 : 5;
6821                 __IM uint32_t DLR        : 1;  /*!< [17..17] Display list reader feature                                      */
6822                 __IM uint32_t FBCACHE    : 1;  /*!< [18..18] Framebuffer cache feature                                        */
6823                 __IM uint32_t TXCACHE    : 1;  /*!< [19..19] Texture cache feature                                            */
6824                 __IM uint32_t PERFCOUNT  : 1;  /*!< [20..20] Two performance counter feature                                  */
6825                 __IM uint32_t TEXCLU     : 1;  /*!< [21..21] Texture CLUT with 16 or 256 entries feature                      */
6826                 uint32_t                 : 1;
6827                 __IM uint32_t RLEUNIT    : 1;  /*!< [23..23] RLE unit feature                                                 */
6828                 __IM uint32_t TEXCLUT256 : 1;  /*!< [24..24] Texture CLUT feature                                             */
6829                 __IM uint32_t COLORKEY   : 1;  /*!< [25..25] Colorkey feature                                                 */
6830                 uint32_t                 : 1;
6831                 __IM uint32_t ACBLEND    : 1;  /*!< [27..27] Alpha channel blending feature                                   */
6832                 uint32_t                 : 4;
6833             } HWREVISION_b;
6834         };
6835     };
6836     __IM uint32_t RESERVED[2];
6837 
6838     union
6839     {
6840         __OM uint32_t L1START;         /*!< (@ 0x00000010) Limiter 1 Start Value Register                             */
6841 
6842         struct
6843         {
6844             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6845         } L1START_b;
6846     };
6847 
6848     union
6849     {
6850         __OM uint32_t L2START;         /*!< (@ 0x00000014) Limiter 2 Start Value Register                             */
6851 
6852         struct
6853         {
6854             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6855         } L2START_b;
6856     };
6857 
6858     union
6859     {
6860         __OM uint32_t L3START;         /*!< (@ 0x00000018) Limiter 3 Start Value Register                             */
6861 
6862         struct
6863         {
6864             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6865         } L3START_b;
6866     };
6867 
6868     union
6869     {
6870         __OM uint32_t L4START;         /*!< (@ 0x0000001C) Limiter 4 Start Value Register                             */
6871 
6872         struct
6873         {
6874             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6875         } L4START_b;
6876     };
6877 
6878     union
6879     {
6880         __OM uint32_t L5START;         /*!< (@ 0x00000020) Limiter 5 Start Value Register                             */
6881 
6882         struct
6883         {
6884             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6885         } L5START_b;
6886     };
6887 
6888     union
6889     {
6890         __OM uint32_t L6START;         /*!< (@ 0x00000024) Limiter 6 Start Value Register                             */
6891 
6892         struct
6893         {
6894             __OM uint32_t LSTART : 32; /*!< [31..0] Start value of the n'th limiter(n=1-6)                            */
6895         } L6START_b;
6896     };
6897 
6898     union
6899     {
6900         __OM uint32_t L1XADD;          /*!< (@ 0x00000028) Limiter 1 X-Axis Increment Register                        */
6901 
6902         struct
6903         {
6904             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6905         } L1XADD_b;
6906     };
6907 
6908     union
6909     {
6910         __OM uint32_t L2XADD;          /*!< (@ 0x0000002C) Limiter 2 X-Axis Increment Register                        */
6911 
6912         struct
6913         {
6914             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6915         } L2XADD_b;
6916     };
6917 
6918     union
6919     {
6920         __OM uint32_t L3XADD;          /*!< (@ 0x00000030) Limiter 3 X-Axis Increment Register                        */
6921 
6922         struct
6923         {
6924             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6925         } L3XADD_b;
6926     };
6927 
6928     union
6929     {
6930         __OM uint32_t L4XADD;          /*!< (@ 0x00000034) Limiter 4 X-Axis Increment Register                        */
6931 
6932         struct
6933         {
6934             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6935         } L4XADD_b;
6936     };
6937 
6938     union
6939     {
6940         __OM uint32_t L5XADD;          /*!< (@ 0x00000038) Limiter 5 X-Axis Increment Register                        */
6941 
6942         struct
6943         {
6944             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6945         } L5XADD_b;
6946     };
6947 
6948     union
6949     {
6950         __OM uint32_t L6XADD;          /*!< (@ 0x0000003C) Limiter 6 X-Axis Increment Register                        */
6951 
6952         struct
6953         {
6954             __OM uint32_t LXADD : 32;  /*!< [31..0] X-axis increment                                                  */
6955         } L6XADD_b;
6956     };
6957 
6958     union
6959     {
6960         __OM uint32_t L1YADD;          /*!< (@ 0x00000040) Limiter 1 Y-Axis Increment Register                        */
6961 
6962         struct
6963         {
6964             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6965         } L1YADD_b;
6966     };
6967 
6968     union
6969     {
6970         __OM uint32_t L2YADD;          /*!< (@ 0x00000044) Limiter 2 Y-Axis Increment Register                        */
6971 
6972         struct
6973         {
6974             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6975         } L2YADD_b;
6976     };
6977 
6978     union
6979     {
6980         __OM uint32_t L3YADD;          /*!< (@ 0x00000048) Limiter 3 Y-Axis Increment Register                        */
6981 
6982         struct
6983         {
6984             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6985         } L3YADD_b;
6986     };
6987 
6988     union
6989     {
6990         __OM uint32_t L4YADD;          /*!< (@ 0x0000004C) Limiter 4 Y-Axis Increment Register                        */
6991 
6992         struct
6993         {
6994             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
6995         } L4YADD_b;
6996     };
6997 
6998     union
6999     {
7000         __OM uint32_t L5YADD;          /*!< (@ 0x00000050) Limiter 5 Y-Axis Increment Register                        */
7001 
7002         struct
7003         {
7004             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
7005         } L5YADD_b;
7006     };
7007 
7008     union
7009     {
7010         __OM uint32_t L6YADD;          /*!< (@ 0x00000054) Limiter 6 Y-Axis Increment Register                        */
7011 
7012         struct
7013         {
7014             __OM uint32_t LYADD : 32;  /*!< [31..0] Y-axis increment                                                  */
7015         } L6YADD_b;
7016     };
7017 
7018     union
7019     {
7020         __OM uint32_t L1BAND;          /*!< (@ 0x00000058) Limiter 1 Band Width Parameter Register                    */
7021 
7022         struct
7023         {
7024             __OM uint32_t LBAND : 32;  /*!< [31..0] Limiter m band width parameter                                    */
7025         } L1BAND_b;
7026     };
7027 
7028     union
7029     {
7030         __OM uint32_t L2BAND;          /*!< (@ 0x0000005C) Limiter 2 Band Width Parameter Register                    */
7031 
7032         struct
7033         {
7034             __OM uint32_t LBAND : 32;  /*!< [31..0] Limiter m band width parameter                                    */
7035         } L2BAND_b;
7036     };
7037     __IM uint32_t RESERVED1;
7038 
7039     union
7040     {
7041         __OM uint32_t COLOR1;          /*!< (@ 0x00000064) Base Color Register                                        */
7042 
7043         struct
7044         {
7045             __OM uint32_t COLOR1B : 8; /*!< [7..0] Blue channel of color 1                                            */
7046             __OM uint32_t COLOR1G : 8; /*!< [15..8] Green channel of color 1                                          */
7047             __OM uint32_t COLOR1R : 8; /*!< [23..16] Red channel of color 1                                           */
7048             __OM uint32_t COLOR1A : 8; /*!< [31..24] Alpha channel of color 1(0x00: transparent. . . 0xFF:
7049                                         *   opaque)                                                                   */
7050         } COLOR1_b;
7051     };
7052 
7053     union
7054     {
7055         __OM uint32_t COLOR2;          /*!< (@ 0x00000068) Secondary Color Register                                   */
7056 
7057         struct
7058         {
7059             __OM uint32_t COLOR2B : 8; /*!< [7..0] Blue channel of color 2                                            */
7060             __OM uint32_t COLOR2G : 8; /*!< [15..8] Green channel of color 2                                          */
7061             __OM uint32_t COLOR2R : 8; /*!< [23..16] Red channel of color 2                                           */
7062             __OM uint32_t COLOR2A : 8; /*!< [31..24] Alpha channel of color 2(0x00: transparent. . . 0xFF:
7063                                         *   opaque)                                                                   */
7064         } COLOR2_b;
7065     };
7066     __IM uint32_t RESERVED2[2];
7067 
7068     union
7069     {
7070         __OM uint32_t PATTERN;         /*!< (@ 0x00000074) Pattern Register                                           */
7071 
7072         struct
7073         {
7074             __OM uint32_t PATTERN : 8; /*!< [7..0] Bitmap of the pattern                                              */
7075             uint32_t              : 24;
7076         } PATTERN_b;
7077     };
7078 
7079     union
7080     {
7081         __OM uint32_t SIZE;            /*!< (@ 0x00000078) Bounding Box Dimension Register                            */
7082 
7083         struct
7084         {
7085             __OM uint32_t SIZEX : 16;  /*!< [15..0] Width of the bounding box in pixelsvalid range: 0 to
7086                                         *   1024                                                                      */
7087             __OM uint32_t SIZEY : 16;  /*!< [31..16] Height of the bounding box in pixelsvalid range: 0
7088                                         *   to 1024                                                                   */
7089         } SIZE_b;
7090     };
7091 
7092     union
7093     {
7094         __OM uint32_t PITCH;           /*!< (@ 0x0000007C) Framebuffer Pitch And Spanstore Delay Register             */
7095 
7096         struct
7097         {
7098             __OM uint32_t PITCH : 16;  /*!< [15..0] pitch of the framebuffer. A negative width can be used
7099                                         *   to render bottom-up instead of top-down                                   */
7100             __OM uint32_t SSD : 16;    /*!< [31..16] Spanstore delay                                                  */
7101         } PITCH_b;
7102     };
7103 
7104     union
7105     {
7106         __OM uint32_t ORIGIN;          /*!< (@ 0x00000080) Framebuffer Base Address Register                          */
7107 
7108         struct
7109         {
7110             __OM uint32_t ORIGIN : 32; /*!< [31..0] Address of the first pixel in framebuffer                         */
7111         } ORIGIN_b;
7112     };
7113     __IM uint32_t RESERVED3[3];
7114 
7115     union
7116     {
7117         __OM uint32_t LUSTART;          /*!< (@ 0x00000090) U Limiter Start Value Register                             */
7118 
7119         struct
7120         {
7121             __OM uint32_t LUSTART : 32; /*!< [31..0] U limiter start value                                             */
7122         } LUSTART_b;
7123     };
7124 
7125     union
7126     {
7127         __OM uint32_t LUXADD;          /*!< (@ 0x00000094) U Limiter X-Axis Increment Register                        */
7128 
7129         struct
7130         {
7131             __OM uint32_t LUXADD : 32; /*!< [31..0] U limiter x-axis increment                                        */
7132         } LUXADD_b;
7133     };
7134 
7135     union
7136     {
7137         __OM uint32_t LUYADD;          /*!< (@ 0x00000098) U Limiter Y-Axis Increment Register                        */
7138 
7139         struct
7140         {
7141             __OM uint32_t LUYADD : 32; /*!< [31..0] U limiter y-axis increment                                        */
7142         } LUYADD_b;
7143     };
7144 
7145     union
7146     {
7147         __OM uint32_t LVSTARTI;          /*!< (@ 0x0000009C) V Limiter Start Value Integer Part Register                */
7148 
7149         struct
7150         {
7151             __OM uint32_t LVSTARTI : 32; /*!< [31..0] V limiter start value integer part                                */
7152         } LVSTARTI_b;
7153     };
7154 
7155     union
7156     {
7157         __OM uint32_t LVSTARTF;          /*!< (@ 0x000000A0) V Limiter Start Value Fractional Part Register             */
7158 
7159         struct
7160         {
7161             __OM uint32_t LVSTARTF : 16; /*!< [15..0] V limiter start value fractional part                             */
7162             uint32_t               : 16;
7163         } LVSTARTF_b;
7164     };
7165 
7166     union
7167     {
7168         __OM uint32_t LVXADDI;          /*!< (@ 0x000000A4) V Limiter X-Axis Increment Integer Part Register           */
7169 
7170         struct
7171         {
7172             __OM uint32_t LVXADDI : 32; /*!< [31..0] V limiter x-axis increment integer part                           */
7173         } LVXADDI_b;
7174     };
7175 
7176     union
7177     {
7178         __OM uint32_t LVYADDI;          /*!< (@ 0x000000A8) V Limiter Y-Axis Increment Integer Part Register           */
7179 
7180         struct
7181         {
7182             __OM uint32_t LVYADDI : 32; /*!< [31..0] V limiter y-axis increment integer part                           */
7183         } LVYADDI_b;
7184     };
7185 
7186     union
7187     {
7188         __OM uint32_t LVYXADDF;         /*!< (@ 0x000000AC) V Limiter Increment Fractional Parts Register              */
7189 
7190         struct
7191         {
7192             __OM uint32_t LVXADDF : 16; /*!< [15..0] V xlimiter increment fractional part                              */
7193             __OM uint32_t LVYADDF : 16; /*!< [31..16] V y limiter increment fractional part                            */
7194         } LVYXADDF_b;
7195     };
7196     __IM uint32_t RESERVED4;
7197 
7198     union
7199     {
7200         __OM uint32_t TEXPITCH;          /*!< (@ 0x000000B4) Texels Per Texture Line Register                           */
7201 
7202         struct
7203         {
7204             __OM uint32_t TEXPITCH : 32; /*!< [31..0] Texels per texture linevalid range: 0 to 2048                     */
7205         } TEXPITCH_b;
7206     };
7207 
7208     union
7209     {
7210         __OM uint32_t TEXMASK;           /*!< (@ 0x000000B8) Texture Size or Texture Address Mask Register              */
7211 
7212         struct
7213         {
7214             __OM uint32_t TEXUMASK : 11; /*!< [10..0] U maskSet TEXUMASK[10:0] = texture_width -1In texture
7215                                           *   wrapping mode (CONTROL2.TEXTURECLAMPX = 0): texture_width
7216                                           *   must be a power of 2.In texture clamping mode (CONTROL2.TEXTURECLAMPX
7217                                           *   = 1):all widths up to 2048 are allowed.                                   */
7218             __OM uint32_t TEXVMASK : 21; /*!< [31..11] V maskSet TEXVMASK[20:0] = TEXPITCH * (texture_height
7219                                           *   - 1).In texture wrapping mode (CONTROL2.TEXTURECLAMPY =
7220                                           *   0): texture_height must be a power of 2In texture clamping
7221                                           *   mode (CONTROL2.TEXTURECLAMPY = 1):all heights up to 1024
7222                                           *   are allowed.                                                              */
7223         } TEXMASK_b;
7224     };
7225 
7226     union
7227     {
7228         __OM uint32_t TEXORIGIN;          /*!< (@ 0x000000BC) Texture Base Address Register                              */
7229 
7230         struct
7231         {
7232             __OM uint32_t TEXORIGIN : 32; /*!< [31..0] Texture base address                                              */
7233         } TEXORIGIN_b;
7234     };
7235 
7236     union
7237     {
7238         __OM uint32_t IRQCTL;              /*!< (@ 0x000000C0) Interrupt Control Register                                 */
7239 
7240         struct
7241         {
7242             __OM uint32_t ENUMIRQEN   : 1; /*!< [0..0] ENUMIRQ interrupt mask enable                                      */
7243             __OM uint32_t DLISTIRQEN  : 1; /*!< [1..1] DLISTIRQ interrupt mask enable                                     */
7244             __OM uint32_t ENUMIRQCLR  : 1; /*!< [2..2] Clear enumeration interrupt ENUMIRQ                                */
7245             __OM uint32_t DLISTIRQCLR : 1; /*!< [3..3] Clear display list interrupt DLISTIRQ                              */
7246             __OM uint32_t BUSIRQEN    : 1; /*!< [4..4] BUSIRQ interrupt mask enable                                       */
7247             __OM uint32_t BUSIRQCLR   : 1; /*!< [5..5] Clear bus error interrupt BUSIRQ                                   */
7248             uint32_t                  : 26;
7249         } IRQCTL_b;
7250     };
7251 
7252     union
7253     {
7254         __OM uint32_t CACHECTL;          /*!< (@ 0x000000C4) Cache Control Register                                     */
7255 
7256         struct
7257         {
7258             __OM uint32_t CENABLEFX : 1; /*!< [0..0] Framebuffer cache enable                                           */
7259             __OM uint32_t CFLUSHFX  : 1; /*!< [1..1] Flush framebuffer cache                                            */
7260             __OM uint32_t CENABLETX : 1; /*!< [2..2] Texture cache enable                                               */
7261             __OM uint32_t CFLUSHTX  : 1; /*!< [3..3] Flush texture cache                                                */
7262             uint32_t                : 28;
7263         } CACHECTL_b;
7264     };
7265 
7266     union
7267     {
7268         __OM uint32_t DLISTSTART;          /*!< (@ 0x000000C8) Display List Start Address Register                        */
7269 
7270         struct
7271         {
7272             __OM uint32_t DLISTSTART : 32; /*!< [31..0] Display list start address                                        */
7273         } DLISTSTART_b;
7274     };
7275 
7276     union
7277     {
7278         __IOM uint32_t PERFCOUNT1;         /*!< (@ 0x000000CC) Performance Counter 1                                      */
7279 
7280         struct
7281         {
7282             __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
7283                                             *   = 0000 0000H.                                                             */
7284         } PERFCOUNT1_b;
7285     };
7286 
7287     union
7288     {
7289         __IOM uint32_t PERFCOUNT2;         /*!< (@ 0x000000D0) Performance Counter 2                                      */
7290 
7291         struct
7292         {
7293             __IOM uint32_t PERFCOUNT : 32; /*!< [31..0] Counter value.The counter is reset by writing PERFCOUNT
7294                                             *   = 0000 0000H.                                                             */
7295         } PERFCOUNT2_b;
7296     };
7297 
7298     union
7299     {
7300         __OM uint32_t PERFTRIGGER;           /*!< (@ 0x000000D4) Performance Counters Control Register                      */
7301 
7302         struct
7303         {
7304             __OM uint32_t PERFTRIGGER1 : 16; /*!< [15..0] Selects the internal event that will increment PERFCOUNT1
7305                                               *   register.                                                                 */
7306             __OM uint32_t PERFTRIGGER2 : 16; /*!< [31..16] Selects the internal event that will increment PERFCOUNT2
7307                                               *   register                                                                  */
7308         } PERFTRIGGER_b;
7309     };
7310     __IM uint32_t RESERVED5;
7311 
7312     union
7313     {
7314         __OM uint32_t TEXCLADDR;       /*!< (@ 0x000000DC) CLUT Start Address Register                                */
7315 
7316         struct
7317         {
7318             __OM uint32_t CLADDR : 8;  /*!< [7..0] Texture CLUT start address for indexed texture format              */
7319             uint32_t             : 24;
7320         } TEXCLADDR_b;
7321     };
7322 
7323     union
7324     {
7325         __OM uint32_t TEXCLDATA;       /*!< (@ 0x000000E0) CLUT Data Register                                         */
7326 
7327         struct
7328         {
7329             __OM uint32_t CLDATA : 32; /*!< [31..0] Texture CLUT data for Indexed texture format                      */
7330         } TEXCLDATA_b;
7331     };
7332 
7333     union
7334     {
7335         __OM uint32_t TEXCLOFFSET;      /*!< (@ 0x000000E4) CLUT Offset Register                                       */
7336 
7337         struct
7338         {
7339             __OM uint32_t CLOFFSET : 8; /*!< [7..0] Texture CLUT offset for Indexed texture format. CLOFFSET[7:0]
7340                                          *   is or'ed with the original index                                          */
7341             uint32_t : 24;
7342         } TEXCLOFFSET_b;
7343     };
7344 
7345     union
7346     {
7347         __OM uint32_t COLKEY;          /*!< (@ 0x000000E8) Color Key Register                                         */
7348 
7349         struct
7350         {
7351             __OM uint32_t COLKEYB : 8; /*!< [7..0] Blue channel of color key                                          */
7352             __OM uint32_t COLKEYG : 8; /*!< [15..8] Green channel of color key                                        */
7353             __OM uint32_t COLKEYR : 8; /*!< [23..16] Red channel of color key                                         */
7354             uint32_t              : 8;
7355         } COLKEY_b;
7356     };
7357 } R_DRW_Type;                          /*!< Size = 236 (0xec)                                                         */
7358 
7359 /* =========================================================================================================================== */
7360 /* ================                                           R_DTC                                           ================ */
7361 /* =========================================================================================================================== */
7362 
7363 /**
7364  * @brief Data Transfer Controller (R_DTC)
7365  */
7366 
7367 typedef struct                         /*!< (@ 0x4000AC00) R_DTC Structure                                            */
7368 {
7369     union
7370     {
7371         __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
7372 
7373         struct
7374         {
7375             uint8_t           : 4;
7376             __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
7377             uint8_t           : 3;
7378         } DTCCR_b;
7379     };
7380     __IM uint8_t  RESERVED;
7381     __IM uint16_t RESERVED1;
7382 
7383     union
7384     {
7385         __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
7386 
7387         struct
7388         {
7389             __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
7390                                          *   in the lower-order 10 bits. These bits are fixed to 0.                    */
7391         } DTCVBR_b;
7392     };
7393     __IM uint32_t RESERVED2;
7394 
7395     union
7396     {
7397         __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
7398 
7399         struct
7400         {
7401             __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
7402             uint8_t             : 7;
7403         } DTCST_b;
7404     };
7405     __IM uint8_t RESERVED3;
7406 
7407     union
7408     {
7409         __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
7410 
7411         struct
7412         {
7413             __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
7414                                         *   the vector number for the activating source when DTC transfer
7415                                         *   is in progress.The value is only valid if DTC transfer
7416                                         *   is in progress (the value of the ACT flag is 1)                           */
7417             uint16_t          : 7;
7418             __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
7419         } DTCSTS_b;
7420     };
7421 
7422     union
7423     {
7424         __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
7425 
7426         struct
7427         {
7428             uint8_t            : 4;
7429             __IOM uint8_t RRSS : 1;    /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure               */
7430             uint8_t            : 3;
7431         } DTCCR_SEC_b;
7432     };
7433     __IM uint8_t   RESERVED4;
7434     __IM uint16_t  RESERVED5;
7435     __IOM uint32_t DTCVBR_SEC;         /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
7436     __IM uint32_t  RESERVED6[2];
7437 
7438     union
7439     {
7440         __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
7441 
7442         struct
7443         {
7444             __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
7445             __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
7446             uint32_t              : 7;
7447             __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
7448             uint32_t              : 15;
7449         } DTEVR_b;
7450     };
7451 } R_DTC_Type;                          /*!< Size = 36 (0x24)                                                          */
7452 
7453 /* =========================================================================================================================== */
7454 /* ================                                           R_ELC                                           ================ */
7455 /* =========================================================================================================================== */
7456 
7457 /**
7458  * @brief Event Link Controller (R_ELC)
7459  */
7460 
7461 typedef struct                         /*!< (@ 0x40201000) R_ELC Structure                                            */
7462 {
7463     union
7464     {
7465         __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
7466 
7467         struct
7468         {
7469             uint8_t             : 7;
7470             __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
7471         } ELCR_b;
7472     };
7473     __IM uint8_t            RESERVED;
7474     __IM uint16_t           RESERVED1;
7475     __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000004) Event Link Software Event Generation Register              */
7476     __IM uint32_t           RESERVED2[6];
7477     __IOM R_ELC_ELSR_Type   ELSR[31];  /*!< (@ 0x00000020) Event Link Setting Register [0..30]                        */
7478     __IM uint32_t           RESERVED3[17];
7479 
7480     union
7481     {
7482         __IOM uint32_t ELCSARA;         /*!< (@ 0x000000E0) Event Link Controller Security Attribution Register
7483                                          *                  A                                                          */
7484 
7485         struct
7486         {
7487             __IOM uint32_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
7488             __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
7489                                          *   Attribution                                                               */
7490             __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
7491                                          *   Attribution                                                               */
7492             uint32_t : 29;
7493         } ELCSARA_b;
7494     };
7495 
7496     union
7497     {
7498         __IOM uint32_t ELCSARB;        /*!< (@ 0x000000E4) Event Link Controller Security Attribution Register
7499                                         *                  B                                                          */
7500 
7501         struct
7502         {
7503             __IOM uint32_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0 Security Attribution                 */
7504             __IOM uint32_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1 Security Attribution                 */
7505             __IOM uint32_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2 Security Attribution                 */
7506             __IOM uint32_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3 Security Attribution                 */
7507             __IOM uint32_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4 Security Attribution                 */
7508             __IOM uint32_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5 Security Attribution                 */
7509             __IOM uint32_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6 Security Attribution                 */
7510             __IOM uint32_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7 Security Attribution                 */
7511             __IOM uint32_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8 Security Attribution                 */
7512             __IOM uint32_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9 Security Attribution                 */
7513             __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Security Attribution              */
7514             __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Security Attribution              */
7515             __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Security Attribution              */
7516             __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Security Attribution              */
7517             __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Security Attribution              */
7518             __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Security Attribution              */
7519             __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Security Attribution              */
7520             __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Security Attribution              */
7521             uint32_t              : 12;
7522             __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Security Attribution              */
7523             uint32_t              : 1;
7524         } ELCSARB_b;
7525     };
7526     __IM uint32_t RESERVED4[2];
7527 
7528     union
7529     {
7530         __IOM uint32_t ELCPARA;         /*!< (@ 0x000000F0) Event Link Controller Priviledge Attribution
7531                                          *                  Register A                                                 */
7532 
7533         struct
7534         {
7535             __IOM uint32_t ELCR    : 1; /*!< [0..0] Event Link Controller Register Priviledge Attribution              */
7536             __IOM uint32_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Priviledge
7537                                          *   Attribution                                                               */
7538             __IOM uint32_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1 Priviledge
7539                                          *   Attribution                                                               */
7540             uint32_t : 29;
7541         } ELCPARA_b;
7542     };
7543 
7544     union
7545     {
7546         __IOM uint32_t ELCPARB;        /*!< (@ 0x000000F4) Event Link Controller Priviledge Attribution
7547                                         *                  Register B                                                 */
7548 
7549         struct
7550         {
7551             __IOM uint32_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0 Priviledge Attribution               */
7552             __IOM uint32_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1 Priviledge Attribution               */
7553             __IOM uint32_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2 Priviledge Attribution               */
7554             __IOM uint32_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3 Priviledge Attribution               */
7555             __IOM uint32_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4 Priviledge Attribution               */
7556             __IOM uint32_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5 Priviledge Attribution               */
7557             __IOM uint32_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6 Priviledge Attribution               */
7558             __IOM uint32_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7 Priviledge Attribution               */
7559             __IOM uint32_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8 Priviledge Attribution               */
7560             __IOM uint32_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9 Priviledge Attribution               */
7561             __IOM uint32_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10 Priviledge Attribution            */
7562             __IOM uint32_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11 Priviledge Attribution            */
7563             __IOM uint32_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12 Priviledge Attribution            */
7564             __IOM uint32_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13 Priviledge Attribution            */
7565             __IOM uint32_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14 Priviledge Attribution            */
7566             __IOM uint32_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15 Priviledge Attribution            */
7567             __IOM uint32_t ELSR16 : 1; /*!< [16..16] Event Link Setting Register 16 Priviledge Attribution            */
7568             __IOM uint32_t ELSR17 : 1; /*!< [17..17] Event Link Setting Register 17 Priviledge Attribution            */
7569             uint32_t              : 12;
7570             __IOM uint32_t ELSR30 : 1; /*!< [30..30] Event Link Setting Register 30 Priviledge Attribution            */
7571             uint32_t              : 1;
7572         } ELCPARB_b;
7573     };
7574 } R_ELC_Type;                          /*!< Size = 248 (0xf8)                                                         */
7575 
7576 /* =========================================================================================================================== */
7577 /* ================                                         R_ETHERC0                                         ================ */
7578 /* =========================================================================================================================== */
7579 
7580 /**
7581  * @brief Ethernet MAC Controller (R_ETHERC0)
7582  */
7583 
7584 typedef struct                         /*!< (@ 0x40354100) R_ETHERC0 Structure                                        */
7585 {
7586     union
7587     {
7588         __IOM uint32_t ECMR;           /*!< (@ 0x00000000) ETHERC Mode Register                                       */
7589 
7590         struct
7591         {
7592             __IOM uint32_t PRM   : 1;  /*!< [0..0] Promiscuous Mode                                                   */
7593             __IOM uint32_t DM    : 1;  /*!< [1..1] Duplex Mode                                                        */
7594             __IOM uint32_t RTM   : 1;  /*!< [2..2] Bit Rate                                                           */
7595             __IOM uint32_t ILB   : 1;  /*!< [3..3] Internal Loopback Mode                                             */
7596             uint32_t             : 1;
7597             __IOM uint32_t TE    : 1;  /*!< [5..5] Transmission Enable                                                */
7598             __IOM uint32_t RE    : 1;  /*!< [6..6] Reception Enable                                                   */
7599             uint32_t             : 2;
7600             __IOM uint32_t MPDE  : 1;  /*!< [9..9] Magic Packet Detection Enable                                      */
7601             uint32_t             : 2;
7602             __IOM uint32_t PRCEF : 1;  /*!< [12..12] CRC Error Frame Receive Mode                                     */
7603             uint32_t             : 3;
7604             __IOM uint32_t TXF   : 1;  /*!< [16..16] Transmit Flow Control Operating Mode                             */
7605             __IOM uint32_t RXF   : 1;  /*!< [17..17] Receive Flow Control Operating Mode                              */
7606             __IOM uint32_t PFR   : 1;  /*!< [18..18] PAUSE Frame Receive Mode                                         */
7607             __IOM uint32_t ZPF   : 1;  /*!< [19..19] 0 Time PAUSE Frame Enable                                        */
7608             __IOM uint32_t TPC   : 1;  /*!< [20..20] PAUSE Frame Transmit                                             */
7609             uint32_t             : 11;
7610         } ECMR_b;
7611     };
7612     __IM uint32_t RESERVED;
7613 
7614     union
7615     {
7616         __IOM uint32_t RFLR;           /*!< (@ 0x00000008) Receive Frame Maximum Length Register                      */
7617 
7618         struct
7619         {
7620             __IOM uint32_t RFL : 12;   /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
7621                                         *   maximum frame length. The minimum value that can be set
7622                                         *   is 1,518 bytes, and the maximum value that can be set is
7623                                         *   2,048 bytes. Values that are less than 1,518 bytes are
7624                                         *   regarded as 1,518 bytes, and values larger than 2,048 bytes
7625                                         *   are regarded as 2,048 bytes.                                              */
7626             uint32_t : 20;
7627         } RFLR_b;
7628     };
7629     __IM uint32_t RESERVED1;
7630 
7631     union
7632     {
7633         __IOM uint32_t ECSR;           /*!< (@ 0x00000010) ETHERC Status Register                                     */
7634 
7635         struct
7636         {
7637             __IOM uint32_t ICD   : 1;  /*!< [0..0] False Carrier Detect Flag                                          */
7638             __IOM uint32_t MPD   : 1;  /*!< [1..1] Magic Packet Detect Flag                                           */
7639             __IOM uint32_t LCHNG : 1;  /*!< [2..2] LCHNG Link Signal Change Flag                                      */
7640             uint32_t             : 1;
7641             __IOM uint32_t PSRTO : 1;  /*!< [4..4] PAUSE Frame Retransmit Over Flag                                   */
7642             __IOM uint32_t BFR   : 1;  /*!< [5..5] Continuous Broadcast Frame Reception Flag                          */
7643             uint32_t             : 26;
7644         } ECSR_b;
7645     };
7646     __IM uint32_t RESERVED2;
7647 
7648     union
7649     {
7650         __IOM uint32_t ECSIPR;          /*!< (@ 0x00000018) ETHERC Interrupt Enable Register                           */
7651 
7652         struct
7653         {
7654             __IOM uint32_t ICDIP   : 1; /*!< [0..0] False Carrier Detect Interrupt Enable                              */
7655             __IOM uint32_t MPDIP   : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable                               */
7656             __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable                                */
7657             uint32_t               : 1;
7658             __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable                       */
7659             __IOM uint32_t BFSIPR  : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable              */
7660             uint32_t               : 26;
7661         } ECSIPR_b;
7662     };
7663     __IM uint32_t RESERVED3;
7664 
7665     union
7666     {
7667         __IOM uint32_t PIR;            /*!< (@ 0x00000020) PHY Interface Register                                     */
7668 
7669         struct
7670         {
7671             __IOM uint32_t MDC : 1;    /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
7672                                         *   from the ETn_MDC pin to supply the management data clock
7673                                         *   to the MII or RMII.                                                       */
7674             __IOM uint32_t MMD : 1;    /*!< [1..1] MII/RMII Management Mode                                           */
7675             __IOM uint32_t MDO : 1;    /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
7676                                         *   from the ETn_MDIO pin when the MMD bit is 1 (write). The
7677                                         *   value is not output when the MMD bit is 0 (read).                         */
7678             __IM uint32_t MDI : 1;     /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
7679                                         *   of the ETn_MDIO pin. The write value should be 0.                         */
7680             uint32_t : 28;
7681         } PIR_b;
7682     };
7683     __IM uint32_t RESERVED4;
7684 
7685     union
7686     {
7687         __IM uint32_t PSR;             /*!< (@ 0x00000028) PHY Status Register                                        */
7688 
7689         struct
7690         {
7691             __IM uint32_t LMON : 1;    /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
7692                                         *   by connecting the link signal output from the PHY-LSI to
7693                                         *   the ETn_LINKSTA pin. For details on the polarity, refer
7694                                         *   to the specifications of the connected PHY-LSI.                           */
7695             uint32_t : 31;
7696         } PSR_b;
7697     };
7698     __IM uint32_t RESERVED5[5];
7699 
7700     union
7701     {
7702         __IOM uint32_t RDMLR;          /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
7703                                         *                  Setting Register                                           */
7704 
7705         struct
7706         {
7707             __IOM uint32_t RMD : 20;   /*!< [19..0] Random Number Generation Counter                                  */
7708             uint32_t           : 12;
7709         } RDMLR_b;
7710     };
7711     __IM uint32_t RESERVED6[3];
7712 
7713     union
7714     {
7715         __IOM uint32_t IPGR;           /*!< (@ 0x00000050) IPG Register                                               */
7716 
7717         struct
7718         {
7719             __IOM uint32_t IPG : 5;    /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)'       */
7720             uint32_t           : 27;
7721         } IPGR_b;
7722     };
7723 
7724     union
7725     {
7726         __IOM uint32_t APR;            /*!< (@ 0x00000054) Automatic PAUSE Frame Register                             */
7727 
7728         struct
7729         {
7730             __IOM uint32_t AP : 16;    /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
7731                                         *   of the pause_time parameter for a PAUSE frame that is automatically
7732                                         *   transmitted. Transmission is not performed until the set
7733                                         *   value multiplied by 512 bit time has elapsed.                             */
7734             uint32_t : 16;
7735         } APR_b;
7736     };
7737 
7738     union
7739     {
7740         __OM uint32_t MPR;             /*!< (@ 0x00000058) Manual PAUSE Frame Register                                */
7741 
7742         struct
7743         {
7744             __OM uint32_t MP : 16;     /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
7745                                         *   the pause_time parameter for a PAUSE frame that is manually
7746                                         *   transmitted. Transmission is not performed until the set
7747                                         *   value multiplied by 512 bit time has elapsed. The read
7748                                         *   value is undefined.                                                       */
7749             uint32_t : 16;
7750         } MPR_b;
7751     };
7752     __IM uint32_t RESERVED7;
7753 
7754     union
7755     {
7756         __IM uint32_t RFCF;            /*!< (@ 0x00000060) Received PAUSE Frame Counter                               */
7757 
7758         struct
7759         {
7760             __IM uint32_t RPAUSE : 8;  /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames          */
7761             uint32_t             : 24;
7762         } RFCF_b;
7763     };
7764 
7765     union
7766     {
7767         __IOM uint32_t TPAUSER;         /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register              */
7768 
7769         struct
7770         {
7771             __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting                          */
7772             uint32_t              : 16;
7773         } TPAUSER_b;
7774     };
7775     __IM uint32_t TPAUSECR;             /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter                             */
7776 
7777     union
7778     {
7779         __IOM uint32_t BCFRR;           /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register             */
7780 
7781         struct
7782         {
7783             __IOM uint32_t BCF : 16;    /*!< [15..0] Broadcast Frame Continuous Receive Count Setting                  */
7784             uint32_t           : 16;
7785         } BCFRR_b;
7786     };
7787     __IM uint32_t RESERVED8[20];
7788 
7789     union
7790     {
7791         __IOM uint32_t MAHR;           /*!< (@ 0x000000C0) MAC Address Upper Bit Register                             */
7792 
7793         struct
7794         {
7795             __IOM uint32_t MAHR : 32;  /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
7796                                         *   the upper 32 bits (b47 to b16) of the 48-bit MAC address.                 */
7797         } MAHR_b;
7798     };
7799     __IM uint32_t RESERVED9;
7800 
7801     union
7802     {
7803         __IOM uint32_t MALR;           /*!< (@ 0x000000C8) MAC Address Lower Bit Register                             */
7804 
7805         struct
7806         {
7807             __IOM uint32_t MALR : 16;  /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
7808                                         *   the lower 16 bits of the 48-bit MAC address.                              */
7809             uint32_t : 16;
7810         } MALR_b;
7811     };
7812     __IM uint32_t RESERVED10;
7813 
7814     union
7815     {
7816         __IOM uint32_t TROCR;          /*!< (@ 0x000000D0) Transmit Retry Over Counter Register                       */
7817 
7818         struct
7819         {
7820             __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
7821                                         *   is a counter indicating the number of frames that fail
7822                                         *   to be retransmitted.                                                      */
7823         } TROCR_b;
7824     };
7825     __IOM uint32_t CDCR;               /*!< (@ 0x000000D4) Late Collision Detect Counter Register                     */
7826 
7827     union
7828     {
7829         __IOM uint32_t LCCR;           /*!< (@ 0x000000D8) Lost Carrier Counter Register                              */
7830 
7831         struct
7832         {
7833             __IOM uint32_t LCCR : 32;  /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
7834                                         *   counter indicating the number of times a loss of carrier
7835                                         *   is detected during frame transmission.                                    */
7836         } LCCR_b;
7837     };
7838 
7839     union
7840     {
7841         __IOM uint32_t CNDCR;          /*!< (@ 0x000000DC) Carrier Not Detect Counter Register                        */
7842 
7843         struct
7844         {
7845             __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
7846                                         *   is a counter indicating the number of times a carrier is
7847                                         *   not detected during preamble transmission.                                */
7848         } CNDCR_b;
7849     };
7850     __IM uint32_t RESERVED11;
7851 
7852     union
7853     {
7854         __IOM uint32_t CEFCR;          /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register                   */
7855 
7856         struct
7857         {
7858             __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
7859                                         *   is a counter indicating the number of received frames where
7860                                         *   a CRC error has been detected.                                            */
7861         } CEFCR_b;
7862     };
7863 
7864     union
7865     {
7866         __IOM uint32_t FRECR;          /*!< (@ 0x000000E8) Frame Receive Error Counter Register                       */
7867 
7868         struct
7869         {
7870             __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
7871                                         *   is a counter indicating the number of times a frame receive
7872                                         *   error has occurred.                                                       */
7873         } FRECR_b;
7874     };
7875 
7876     union
7877     {
7878         __IOM uint32_t TSFRCR;          /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register                   */
7879 
7880         struct
7881         {
7882             __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
7883                                          *   is a counter indicating the number of times a short frame
7884                                          *   that is shorter than 64 bytes has been received.                          */
7885         } TSFRCR_b;
7886     };
7887 
7888     union
7889     {
7890         __IOM uint32_t TLFRCR;          /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register                    */
7891 
7892         struct
7893         {
7894             __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
7895                                          *   is a counter indicating the number of times a long frame
7896                                          *   that is longer than the RFLR register value has been received.            */
7897         } TLFRCR_b;
7898     };
7899 
7900     union
7901     {
7902         __IOM uint32_t RFCR;           /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register            */
7903 
7904         struct
7905         {
7906             __IOM uint32_t RFCR : 32;  /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
7907                                         *   register is a counter indicating the number of times a
7908                                         *   frame has been received with the alignment error (frame
7909                                         *   is not an integral number of octets).                                     */
7910         } RFCR_b;
7911     };
7912 
7913     union
7914     {
7915         __IOM uint32_t MAFCR;          /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register           */
7916 
7917         struct
7918         {
7919             __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
7920                                         *   MAFCR register is a counter indicating the number of times
7921                                         *   a frame where the multicast address is set has been received.             */
7922         } MAFCR_b;
7923     };
7924 } R_ETHERC0_Type;                      /*!< Size = 252 (0xfc)                                                         */
7925 
7926 /* =========================================================================================================================== */
7927 /* ================                                      R_ETHERC_EDMAC                                       ================ */
7928 /* =========================================================================================================================== */
7929 
7930 /**
7931  * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
7932  */
7933 
7934 typedef struct                         /*!< (@ 0x40354000) R_ETHERC_EDMAC Structure                                   */
7935 {
7936     union
7937     {
7938         __IOM uint32_t EDMR;           /*!< (@ 0x00000000) EDMAC Mode Register                                        */
7939 
7940         struct
7941         {
7942             __OM uint32_t SWR : 1;     /*!< [0..0] Software Reset                                                     */
7943             uint32_t          : 3;
7944             __IOM uint32_t DL : 2;     /*!< [5..4] Transmit/Receive DescriptorLength                                  */
7945             __IOM uint32_t DE : 1;     /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
7946                                         *   applies to data for the transmit/receive buffer. It does
7947                                         *   not apply to transmit/receive descriptors and registers.                  */
7948             uint32_t : 25;
7949         } EDMR_b;
7950     };
7951     __IM uint32_t RESERVED;
7952 
7953     union
7954     {
7955         __IOM uint32_t EDTRR;          /*!< (@ 0x00000008) EDMAC Transmit Request Register                            */
7956 
7957         struct
7958         {
7959             __OM uint32_t TR : 1;      /*!< [0..0] Transmit Request                                                   */
7960             uint32_t         : 31;
7961         } EDTRR_b;
7962     };
7963     __IM uint32_t RESERVED1;
7964 
7965     union
7966     {
7967         __IOM uint32_t EDRRR;          /*!< (@ 0x00000010) EDMAC Receive Request Register                             */
7968 
7969         struct
7970         {
7971             __IOM uint32_t RR : 1;     /*!< [0..0] Receive Request                                                    */
7972             uint32_t          : 31;
7973         } EDRRR_b;
7974     };
7975     __IM uint32_t RESERVED2;
7976 
7977     union
7978     {
7979         __IOM uint32_t TDLAR;          /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register            */
7980 
7981         struct
7982         {
7983             __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
7984                                         *   set. Set the start address according to the descriptor
7985                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
7986                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
7987                                         *   boundary: Lower 6 bits = 000000b                                          */
7988         } TDLAR_b;
7989     };
7990     __IM uint32_t RESERVED3;
7991 
7992     union
7993     {
7994         __IOM uint32_t RDLAR;          /*!< (@ 0x00000020) Receive Descriptor List Start Address Register             */
7995 
7996         struct
7997         {
7998             __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
7999                                         *   set. Set the start address according to the descriptor
8000                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
8001                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
8002                                         *   boundary: Lower 6 bits = 000000b                                          */
8003         } RDLAR_b;
8004     };
8005     __IM uint32_t RESERVED4;
8006 
8007     union
8008     {
8009         __IOM uint32_t EESR;           /*!< (@ 0x00000028) ETHERC/EDMAC Status Register                               */
8010 
8011         struct
8012         {
8013             __IOM uint32_t CERF : 1;   /*!< [0..0] CRC Error Flag                                                     */
8014             __IOM uint32_t PRE  : 1;   /*!< [1..1] PHY-LSI Receive Error Flag                                         */
8015             __IOM uint32_t RTSF : 1;   /*!< [2..2] Frame-Too-Short Error Flag                                         */
8016             __IOM uint32_t RTLF : 1;   /*!< [3..3] Frame-Too-Long Error Flag                                          */
8017             __IOM uint32_t RRF  : 1;   /*!< [4..4] Alignment Error Flag                                               */
8018             uint32_t            : 2;
8019             __IOM uint32_t RMAF : 1;   /*!< [7..7] Multicast Address Frame Receive Flag                               */
8020             __IOM uint32_t TRO  : 1;   /*!< [8..8] Transmit Retry Over Flag                                           */
8021             __IOM uint32_t CD   : 1;   /*!< [9..9] Late Collision Detect Flag                                         */
8022             __IOM uint32_t DLC  : 1;   /*!< [10..10] Loss of Carrier Detect Flag                                      */
8023             __IOM uint32_t CND  : 1;   /*!< [11..11] Carrier Not Detect Flag                                          */
8024             uint32_t            : 4;
8025             __IOM uint32_t RFOF : 1;   /*!< [16..16] Receive FIFO Overflow Flag                                       */
8026             __IOM uint32_t RDE  : 1;   /*!< [17..17] Receive Descriptor Empty Flag                                    */
8027             __IOM uint32_t FR   : 1;   /*!< [18..18] Frame Receive Flag                                               */
8028             __IOM uint32_t TFUF : 1;   /*!< [19..19] Transmit FIFO Underflow Flag                                     */
8029             __IOM uint32_t TDE  : 1;   /*!< [20..20] Transmit Descriptor Empty Flag                                   */
8030             __IOM uint32_t TC   : 1;   /*!< [21..21] Frame Transfer Complete Flag                                     */
8031             __IM uint32_t  ECI  : 1;   /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
8032                                         *   in the ETHERCn.ECSR register is cleared, the ECI flag is
8033                                         *   also cleared.                                                             */
8034             __IOM uint32_t ADE   : 1;  /*!< [23..23] Address Error Flag                                               */
8035             __IOM uint32_t RFCOF : 1;  /*!< [24..24] Receive Frame Counter Overflow Flag                              */
8036             __IOM uint32_t RABT  : 1;  /*!< [25..25] Receive Abort Detect Flag                                        */
8037             __IOM uint32_t TABT  : 1;  /*!< [26..26] Transmit Abort Detect Flag                                       */
8038             uint32_t             : 3;
8039             __IOM uint32_t TWB   : 1;  /*!< [30..30] Write-Back Complete Flag                                         */
8040             uint32_t             : 1;
8041         } EESR_b;
8042     };
8043     __IM uint32_t RESERVED5;
8044 
8045     union
8046     {
8047         __IOM uint32_t EESIPR;          /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register              */
8048 
8049         struct
8050         {
8051             __IOM uint32_t CERFIP  : 1; /*!< [0..0] CRC Error Interrupt Request Enable                                 */
8052             __IOM uint32_t PREIP   : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable                     */
8053             __IOM uint32_t RTSFIP  : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable                     */
8054             __IOM uint32_t RTLFIP  : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable                      */
8055             __IOM uint32_t RRFIP   : 1; /*!< [4..4] Alignment Error Interrupt Request Enable                           */
8056             uint32_t               : 2;
8057             __IOM uint32_t RMAFIP  : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable           */
8058             __IOM uint32_t TROIP   : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable                       */
8059             __IOM uint32_t CDIP    : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable                     */
8060             __IOM uint32_t DLCIP   : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable                  */
8061             __IOM uint32_t CNDIP   : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable                      */
8062             uint32_t               : 4;
8063             __IOM uint32_t RFOFIP  : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable                   */
8064             __IOM uint32_t RDEIP   : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable                */
8065             __IOM uint32_t FRIP    : 1; /*!< [18..18] Frame Receive Interrupt Request Enable                           */
8066             __IOM uint32_t TFUFIP  : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable                 */
8067             __IOM uint32_t TDEIP   : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable               */
8068             __IOM uint32_t TCIP    : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable                 */
8069             __IOM uint32_t ECIIP   : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable           */
8070             __IOM uint32_t ADEIP   : 1; /*!< [23..23] Address Error Interrupt Request Enable                           */
8071             __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable          */
8072             __IOM uint32_t RABTIP  : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable                    */
8073             __IOM uint32_t TABTIP  : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable                   */
8074             uint32_t               : 3;
8075             __IOM uint32_t TWBIP   : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable                     */
8076             uint32_t               : 1;
8077         } EESIPR_b;
8078     };
8079     __IM uint32_t RESERVED6;
8080 
8081     union
8082     {
8083         __IOM uint32_t TRSCER;         /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
8084                                         *                  Register                                                   */
8085 
8086         struct
8087         {
8088             uint32_t              : 4;
8089             __IOM uint32_t RRFCE  : 1; /*!< [4..4] RRF Flag Copy Enable                                               */
8090             uint32_t              : 2;
8091             __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable                                              */
8092             uint32_t              : 24;
8093         } TRSCER_b;
8094     };
8095     __IM uint32_t RESERVED7;
8096 
8097     union
8098     {
8099         __IOM uint32_t RMFCR;          /*!< (@ 0x00000040) Missed-Frame Counter Register                              */
8100 
8101         struct
8102         {
8103             __IOM uint32_t MFC : 16;   /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
8104                                         *   frames that are discarded and not transferred to the receive
8105                                         *   buffer during reception.                                                  */
8106             uint32_t : 16;
8107         } RMFCR_b;
8108     };
8109     __IM uint32_t RESERVED8;
8110 
8111     union
8112     {
8113         __IOM uint32_t TFTR;           /*!< (@ 0x00000048) Transmit FIFO Threshold Register                           */
8114 
8115         struct
8116         {
8117             __IOM uint32_t TFT : 11;   /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
8118                                         *   the set value multiplied by 4. Example: 00Dh: 52 bytes
8119                                         *   040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes                         */
8120             uint32_t : 21;
8121         } TFTR_b;
8122     };
8123     __IM uint32_t RESERVED9;
8124 
8125     union
8126     {
8127         __IOM uint32_t FDR;            /*!< (@ 0x00000050) Transmit FIFO Threshold Register                           */
8128 
8129         struct
8130         {
8131             __IOM uint32_t RFD : 5;    /*!< [4..0] Transmit FIFO Depth                                                */
8132             uint32_t           : 3;
8133             __IOM uint32_t TFD : 5;    /*!< [12..8] Receive FIFO Depth                                                */
8134             uint32_t           : 19;
8135         } FDR_b;
8136     };
8137     __IM uint32_t RESERVED10;
8138 
8139     union
8140     {
8141         __IOM uint32_t RMCR;           /*!< (@ 0x00000058) Receive Method Control Register                            */
8142 
8143         struct
8144         {
8145             __IOM uint32_t RNR : 1;    /*!< [0..0] Receive Request Reset                                              */
8146             uint32_t           : 31;
8147         } RMCR_b;
8148     };
8149     __IM uint32_t RESERVED11[2];
8150 
8151     union
8152     {
8153         __IOM uint32_t TFUCR;          /*!< (@ 0x00000064) Transmit FIFO Underflow Counter                            */
8154 
8155         struct
8156         {
8157             __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
8158                                         *   many times the transmit FIFO has underflowed. The counter
8159                                         *   stops when the counter value reaches FFFFh.                               */
8160             uint32_t : 16;
8161         } TFUCR_b;
8162     };
8163 
8164     union
8165     {
8166         __IOM uint32_t RFOCR;          /*!< (@ 0x00000068) Receive FIFO Overflow Counter                              */
8167 
8168         struct
8169         {
8170             __IOM uint32_t OVER : 16;  /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
8171                                         *   times the receive FIFO has overflowed. The counter stops
8172                                         *   when the counter value reaches FFFFh.                                     */
8173             uint32_t : 16;
8174         } RFOCR_b;
8175     };
8176 
8177     union
8178     {
8179         __IOM uint32_t IOSR;           /*!< (@ 0x0000006C) Independent Output Signal Setting Register                 */
8180 
8181         struct
8182         {
8183             __IOM uint32_t ELB : 1;    /*!< [0..0] External Loopback Mode                                             */
8184             uint32_t           : 31;
8185         } IOSR_b;
8186     };
8187 
8188     union
8189     {
8190         __IOM uint32_t FCFTR;          /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register         */
8191 
8192         struct
8193         {
8194             __IOM uint32_t RFDO : 3;   /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
8195                                         *   bytes of data is stored in the receive FIFO.)                             */
8196             uint32_t            : 13;
8197             __IOM uint32_t RFFO : 3;   /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
8198                                         *   receive frames have been stored in the receive FIFO.)                     */
8199             uint32_t : 13;
8200         } FCFTR_b;
8201     };
8202     __IM uint32_t RESERVED12;
8203 
8204     union
8205     {
8206         __IOM uint32_t RPADIR;         /*!< (@ 0x00000078) Receive Data Padding Insert Register                       */
8207 
8208         struct
8209         {
8210             __IOM uint32_t PADR : 6;   /*!< [5..0] Padding Slot                                                       */
8211             uint32_t            : 10;
8212             __IOM uint32_t PADS : 2;   /*!< [17..16] Padding Size                                                     */
8213             uint32_t            : 14;
8214         } RPADIR_b;
8215     };
8216 
8217     union
8218     {
8219         __IOM uint32_t TRIMD;          /*!< (@ 0x0000007C) Transmit Interrupt Setting Register                        */
8220 
8221         struct
8222         {
8223             __IOM uint32_t TIS : 1;    /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
8224                                         *   the mode selected by the TIM bit to notify an interrupt.                  */
8225             uint32_t           : 3;
8226             __IOM uint32_t TIM : 1;    /*!< [4..4] Transmit Interrupt Mode                                            */
8227             uint32_t           : 27;
8228         } TRIMD_b;
8229     };
8230     __IM uint32_t RESERVED13[18];
8231 
8232     union
8233     {
8234         __IOM uint32_t RBWAR;          /*!< (@ 0x000000C8) Receive Buffer Write Address Register                      */
8235 
8236         struct
8237         {
8238             __IM uint32_t RBWAR : 32;  /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
8239                                         *   indicates the last address that the EDMAC has written data
8240                                         *   to when writing to the receive buffer.Refer to the address
8241                                         *   indicated by the RBWAR register to recognize which address
8242                                         *   in the receive buffer the EDMAC is writing data to. Note
8243                                         *   that the address that the EDMAC is outputting to the receive
8244                                         *   buffer may not match the read value of the RBWAR register
8245                                         *   during data reception.                                                    */
8246         } RBWAR_b;
8247     };
8248 
8249     union
8250     {
8251         __IOM uint32_t RDFAR;          /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register                  */
8252 
8253         struct
8254         {
8255             __IM uint32_t RDFAR : 32;  /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
8256                                         *   indicates the start address of the last fetched receive
8257                                         *   descriptor when the EDMAC fetches descriptor information
8258                                         *   from the receive descriptor.Refer to the address indicated
8259                                         *   by the RDFAR register to recognize which receive descriptor
8260                                         *   information the EDMAC is using for the current processing.
8261                                         *   Note that the address of the receive descriptor that the
8262                                         *   EDMAC fetches may not match the read value of the RDFAR
8263                                         *   register during data reception.                                           */
8264         } RDFAR_b;
8265     };
8266     __IM uint32_t RESERVED14;
8267 
8268     union
8269     {
8270         __IOM uint32_t TBRAR;          /*!< (@ 0x000000D4) Transmit Buffer Read Address Register                      */
8271 
8272         struct
8273         {
8274             __IM uint32_t TBRAR : 32;  /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
8275                                         *   indicates the last address that the EDMAC has read data
8276                                         *   from when reading data from the transmit buffer.Refer to
8277                                         *   the address indicated by the TBRAR register to recognize
8278                                         *   which address in the transmit buffer the EDMAC is reading
8279                                         *   from. Note that the address that the EDMAC is outputting
8280                                         *   to the transmit buffer may not match the read value of
8281                                         *   the TBRAR register.                                                       */
8282         } TBRAR_b;
8283     };
8284 
8285     union
8286     {
8287         __IM uint32_t TDFAR;           /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register                 */
8288 
8289         struct
8290         {
8291             __IM uint32_t TDFAR : 32;  /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
8292                                         *   register indicates the start address of the last fetched
8293                                         *   transmit descriptor when the EDMAC fetches descriptor information
8294                                         *   from the transmit descriptor.Refer to the address indicated
8295                                         *   by the TDFAR register to recognize which transmit descriptor
8296                                         *   information the EDMAC is using for the current processing.
8297                                         *   Note that the address of the transmit descriptor that the
8298                                         *   EDMAC fetches may not match the read value of the TDFAR
8299                                         *   register.                                                                 */
8300         } TDFAR_b;
8301     };
8302 } R_ETHERC_EDMAC_Type;                 /*!< Size = 220 (0xdc)                                                         */
8303 
8304 /* =========================================================================================================================== */
8305 /* ================                                       R_FACI_HP_CMD                                       ================ */
8306 /* =========================================================================================================================== */
8307 
8308 /**
8309  * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
8310  */
8311 
8312 typedef struct                         /*!< (@ 0x40100000) R_FACI_HP_CMD Structure                                    */
8313 {
8314     union
8315     {
8316         __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
8317         __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
8318     };
8319 } R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
8320 
8321 /* =========================================================================================================================== */
8322 /* ================                                         R_FACI_HP                                         ================ */
8323 /* =========================================================================================================================== */
8324 
8325 /**
8326  * @brief Flash Application Command Interface (R_FACI_HP)
8327  */
8328 
8329 typedef struct                         /*!< (@ 0x4011E000) R_FACI_HP Structure                                        */
8330 {
8331     __IM uint32_t RESERVED[4];
8332 
8333     union
8334     {
8335         __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
8336 
8337         struct
8338         {
8339             uint8_t             : 3;
8340             __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
8341             __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
8342             uint8_t             : 2;
8343             __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
8344         } FASTAT_b;
8345     };
8346     __IM uint8_t  RESERVED1;
8347     __IM uint16_t RESERVED2;
8348 
8349     union
8350     {
8351         __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
8352 
8353         struct
8354         {
8355             uint8_t               : 3;
8356             __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
8357             __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
8358             uint8_t               : 2;
8359             __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
8360         } FAEINT_b;
8361     };
8362     __IM uint8_t  RESERVED3;
8363     __IM uint16_t RESERVED4;
8364 
8365     union
8366     {
8367         __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
8368 
8369         struct
8370         {
8371             __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
8372             uint8_t              : 7;
8373         } FRDYIE_b;
8374     };
8375     __IM uint8_t  RESERVED5;
8376     __IM uint16_t RESERVED6;
8377     __IM uint32_t RESERVED7[5];
8378 
8379     union
8380     {
8381         __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
8382 
8383         struct
8384         {
8385             __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
8386                                         *   These bits can be written when FRDY bit of FSTATR register
8387                                         *   is '1'. Writing to these bits in FRDY = '0' is ignored.                   */
8388         } FSADDR_b;
8389     };
8390 
8391     union
8392     {
8393         __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
8394 
8395         struct
8396         {
8397             __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
8398                                         *   end address of target area in 'Blank Check' command. These
8399                                         *   bits can be written when FRDY bit of FSTATR register is
8400                                         *   '1'. Writing to these bits in FRDY = '0' is ignored.                      */
8401         } FEADDR_b;
8402     };
8403     __IM uint32_t RESERVED8[3];
8404 
8405     union
8406     {
8407         __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */
8408 
8409         struct
8410         {
8411             __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
8412                                         *   is only possible when the FRDY bit in the FSTATR register
8413                                         *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
8414                                         *   to this bit is only possible when 16 bits are written and
8415                                         *   the value written to the KEY bits is D9h.Written values
8416                                         *   are not retained by these bits (always read as 0x00).Only
8417                                         *   secure access can write to this register. Both secure access
8418                                         *   and non-secure read access are allowed. Non-secure writeaccess
8419                                         *   is denied, but TrustZo                                                    */
8420             uint16_t          : 7;
8421             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
8422         } FMEPROT_b;
8423     };
8424     __IM uint16_t RESERVED9;
8425     __IM uint32_t RESERVED10[12];
8426 
8427     union
8428     {
8429         __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */
8430 
8431         struct
8432         {
8433             __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
8434                                         *   written when the FRDY bit in the FSTATR register is 1.
8435                                         *   Writing to this bit is ignored when the FRDY bit is 0.Writing
8436                                         *   to this bit is only possible when 16 bits are written and
8437                                         *   the value written to the KEY[7:0] bits is 0x78.Written
8438                                         *   values are not retained by these bits (always read as 0x00).              */
8439             uint16_t          : 7;
8440             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
8441         } FBPROT0_b;
8442     };
8443     __IM uint16_t RESERVED11;
8444 
8445     union
8446     {
8447         __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */
8448 
8449         struct
8450         {
8451             __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
8452                                         *   is only possible when the FRDY bit in the FSTATR register
8453                                         *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
8454                                         *   to this bit is only possible when 16 bits are written and
8455                                         *   the value written to the KEY[7:0] bits is 0xB1.Written
8456                                         *   values are not retained by these bits (always read as 0x00).              */
8457             uint16_t          : 7;
8458             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
8459         } FBPROT1_b;
8460     };
8461     __IM uint16_t RESERVED12;
8462 
8463     union
8464     {
8465         __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
8466 
8467         struct
8468         {
8469             uint32_t                 : 6;
8470             __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
8471             uint32_t                 : 1;
8472             __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
8473             __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
8474             __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
8475             __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
8476             __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
8477             __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
8478             __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
8479             __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
8480             uint32_t                 : 4;
8481             __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
8482             __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
8483             __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
8484             __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
8485             uint32_t                 : 8;
8486         } FSTATR_b;
8487     };
8488 
8489     union
8490     {
8491         __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
8492 
8493         struct
8494         {
8495             __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
8496                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
8497                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
8498                                          *   only when this register is accessed in 16-bit size and
8499                                          *   H'AA is written to KEY bits                                               */
8500             uint16_t               : 6;
8501             __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
8502                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
8503                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
8504                                          *   only when this register is accessed in 16-bit size and
8505                                          *   H'AA is written to KEY bits.                                              */
8506             __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
8507         } FENTRYR_b;
8508     };
8509     __IM uint16_t RESERVED13;
8510     __IM uint32_t RESERVED14;
8511 
8512     union
8513     {
8514         __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
8515 
8516         struct
8517         {
8518             __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
8519                                         *   bit of FSTATR register is '1'. Writing to this bit in FRDY
8520                                         *   = '0' is ignored. Writing to these bits is enabled only
8521                                         *   when this register is accessed in 16-bit size and H'2D
8522                                         *   is written to KEY bits.                                                   */
8523             uint16_t          : 7;
8524             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
8525         } FSUINITR_b;
8526     };
8527     __IM uint16_t RESERVED15;
8528     __IM uint32_t RESERVED16[4];
8529 
8530     union
8531     {
8532         __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
8533 
8534         struct
8535         {
8536             __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
8537             __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
8538         } FCMDR_b;
8539     };
8540     __IM uint16_t RESERVED17;
8541     __IM uint32_t RESERVED18[11];
8542 
8543     union
8544     {
8545         __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
8546 
8547         struct
8548         {
8549             __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
8550             uint8_t             : 7;
8551         } FBCCNT_b;
8552     };
8553     __IM uint8_t  RESERVED19;
8554     __IM uint16_t RESERVED20;
8555 
8556     union
8557     {
8558         __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
8559 
8560         struct
8561         {
8562             __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
8563             uint8_t           : 7;
8564         } FBCSTAT_b;
8565     };
8566     __IM uint8_t  RESERVED21;
8567     __IM uint16_t RESERVED22;
8568 
8569     union
8570     {
8571         __IM uint32_t FPSADDR;         /*!< (@ 0x000000D8) Programmed Area Start Address                              */
8572 
8573         struct
8574         {
8575             __IM uint32_t PSADR : 19;  /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
8576                                         *   of the first programmed data which is found in 'Blank Check'
8577                                         *   command execution.                                                        */
8578             uint32_t : 13;
8579         } FPSADDR_b;
8580     };
8581 
8582     union
8583     {
8584         __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
8585 
8586         struct
8587         {
8588             __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
8589                                         *   indicate the start sector address for setting the access
8590                                         *   window that is located in the configuration area.                         */
8591             uint32_t           : 4;
8592             __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
8593                                         *   Flag and Temporary Boot Swap Control and 'Config Clear'
8594                                         *   command execution                                                         */
8595             __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
8596                                         *   indicate the end sector address for setting the access
8597                                         *   window that is located in the configuration area.                         */
8598             uint32_t            : 4;
8599             __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
8600         } FAWMON_b;
8601     };
8602 
8603     union
8604     {
8605         __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
8606 
8607         struct
8608         {
8609             __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
8610             uint16_t               : 15;
8611         } FCPSR_b;
8612     };
8613     __IM uint16_t RESERVED23;
8614 
8615     union
8616     {
8617         __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
8618 
8619         struct
8620         {
8621             __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
8622                                         *   can be written when FRDY bit in FSTATR register is '1'.
8623                                         *   Writing to this bit in FRDY = '0' is ignored. Writing to
8624                                         *   these bits is enabled only when this register is accessed
8625                                         *   in 16-bit size and H'1E is written to KEY bits.                           */
8626             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
8627         } FPCKAR_b;
8628     };
8629     __IM uint16_t RESERVED24;
8630 
8631     union
8632     {
8633         __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
8634 
8635         struct
8636         {
8637             __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
8638                                         *   bit in FSTATR register is '1'. Writing to this bit in FRDY
8639                                         *   = '0' is ignored. Writing to these bits is enabled only
8640                                         *   when this register is accessed in 16-bit size and H'66
8641                                         *   is written to KEY bits.                                                   */
8642             uint16_t          : 6;
8643             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
8644         } FSUACR_b;
8645     };
8646     __IM uint16_t RESERVED25;
8647 } R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
8648 
8649 /* =========================================================================================================================== */
8650 /* ================                                         R_FCACHE                                          ================ */
8651 /* =========================================================================================================================== */
8652 
8653 /**
8654  * @brief Flash Cache (R_FCACHE)
8655  */
8656 
8657 typedef struct                           /*!< (@ 0x4001C100) R_FCACHE Structure                                         */
8658 {
8659     union
8660     {
8661         __IOM uint16_t FCACHEE;          /*!< (@ 0x00000000) Flash Cache Enable Register                                */
8662 
8663         struct
8664         {
8665             __IOM uint16_t FCACHEEN : 1; /*!< [0..0] Flash Cache Enable                                                 */
8666             uint16_t                : 15;
8667         } FCACHEE_b;
8668     };
8669     __IM uint16_t RESERVED;
8670 
8671     union
8672     {
8673         __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000004) Flash Cache Invalidate Register                            */
8674 
8675         struct
8676         {
8677             __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate                                             */
8678             uint16_t                : 15;
8679         } FCACHEIV_b;
8680     };
8681     __IM uint16_t RESERVED1[11];
8682 
8683     union
8684     {
8685         __IOM uint8_t FLWT;            /*!< (@ 0x0000001C) Flash Wait Cycle Register                                  */
8686 
8687         struct
8688         {
8689             __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
8690             uint8_t            : 5;
8691         } FLWT_b;
8692     };
8693     __IM uint8_t  RESERVED2;
8694     __IM uint16_t RESERVED3[17];
8695 
8696     union
8697     {
8698         __IOM uint16_t FSAR;               /*!< (@ 0x00000040) Flash Security Attribution Register                        */
8699 
8700         struct
8701         {
8702             __IOM uint16_t FLWTSA     : 1; /*!< [0..0] FLWT Security Attribution                                          */
8703             __IOM uint16_t FCACHEENSA : 1; /*!< [1..1] FCHACHEEN Security Attribution                                     */
8704             uint16_t                  : 6;
8705             __IOM uint16_t FCKMHZSA   : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
8706             __IOM uint16_t FACICOMISA : 1; /*!< [9..9] FACI command Issuing Security Attribution                          */
8707             __IOM uint16_t FACICOMRSA : 1; /*!< [10..10] FACI command Registers Security Attribution                      */
8708             __IOM uint16_t FACITRSA   : 1; /*!< [11..11] FACI transfer Security Attribution                               */
8709             uint16_t                  : 4;
8710         } FSAR_b;
8711     };
8712 } R_FCACHE_Type;                           /*!< Size = 66 (0x42)                                                          */
8713 
8714 /* =========================================================================================================================== */
8715 /* ================                                          R_GLCDC                                          ================ */
8716 /* =========================================================================================================================== */
8717 
8718 /**
8719  * @brief Graphics LCD Controller (R_GLCDC)
8720  */
8721 
8722 typedef struct                         /*!< (@ 0x40342000) R_GLCDC Structure                                          */
8723 {
8724     union
8725     {
8726         __IOM uint32_t GR1_CLUT0[256]; /*!< (@ 0x00000000) Color Palette 0 Plane for Graphics 1 Plane                 */
8727 
8728         struct
8729         {
8730             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
8731             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
8732             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
8733             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
8734                                         *   m Plane                                                                   */
8735         } GR1_CLUT0_b[256];
8736     };
8737 
8738     union
8739     {
8740         __IOM uint32_t GR1_CLUT1[256]; /*!< (@ 0x00000400) Color Palette 1 Plane for Graphics 1 Plane                 */
8741 
8742         struct
8743         {
8744             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
8745             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
8746             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
8747             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
8748                                         *   m Plane                                                                   */
8749         } GR1_CLUT1_b[256];
8750     };
8751 
8752     union
8753     {
8754         __IOM uint32_t GR2_CLUT0[256]; /*!< (@ 0x00000800) Color Palette 0 Plane for Graphics 2 Plane                 */
8755 
8756         struct
8757         {
8758             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
8759             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
8760             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
8761             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
8762                                         *   m Plane                                                                   */
8763         } GR2_CLUT0_b[256];
8764     };
8765 
8766     union
8767     {
8768         __IOM uint32_t GR2_CLUT1[256]; /*!< (@ 0x00000C00) Color Palette 1 Plane for Graphics 2 Plane                 */
8769 
8770         struct
8771         {
8772             __IOM uint32_t B : 8;      /*!< [7..0] B Value of Color Palette n Plane for Graphics m Plane              */
8773             __IOM uint32_t G : 8;      /*!< [15..8] G Value of Color Palette n Plane for Graphics m Plane             */
8774             __IOM uint32_t R : 8;      /*!< [23..16] R Value of Color Palette n Plane for Graphics m Plane            */
8775             __IOM uint32_t A : 8;      /*!< [31..24] Alpha Blending Value of Color Palette n Plane for Graphics
8776                                         *   m Plane                                                                   */
8777         } GR2_CLUT1_b[256];
8778     };
8779     __IOM R_GLCDC_BG_Type     BG;      /*!< (@ 0x00001000) Background Registers                                       */
8780     __IM uint32_t             RESERVED[57];
8781     __IOM R_GLCDC_GR_Type     GR[2];   /*!< (@ 0x00001100) Layer Registers                                            */
8782     __IOM R_GLCDC_GAM_Type    GAM[3];  /*!< (@ 0x00001300) Gamma Settings                                             */
8783     __IOM R_GLCDC_OUT_Type    OUT;     /*!< (@ 0x000013C0) Output Control Registers                                   */
8784     __IM uint32_t             RESERVED1[6];
8785     __IOM R_GLCDC_TCON_Type   TCON;    /*!< (@ 0x00001400) Timing Control Registers                                   */
8786     __IM uint32_t             RESERVED2[5];
8787     __IOM R_GLCDC_SYSCNT_Type SYSCNT;  /*!< (@ 0x00001440) GLCDC System Control Registers                             */
8788 } R_GLCDC_Type;                        /*!< Size = 5204 (0x1454)                                                      */
8789 
8790 /* =========================================================================================================================== */
8791 /* ================                                          R_GPT0                                           ================ */
8792 /* =========================================================================================================================== */
8793 
8794 /**
8795  * @brief General PWM Timer (R_GPT0)
8796  */
8797 
8798 typedef struct                         /*!< (@ 0x40322000) R_GPT0 Structure                                           */
8799 {
8800     union
8801     {
8802         __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
8803 
8804         struct
8805         {
8806             __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
8807             __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
8808             __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
8809             __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
8810             __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
8811             uint32_t             : 3;
8812             __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
8813             uint32_t             : 16;
8814         } GTWP_b;
8815     };
8816 
8817     union
8818     {
8819         __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
8820 
8821         struct
8822         {
8823             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
8824                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8825                                          *   means counter running.                                                    */
8826             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
8827                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8828                                          *   means counter running.                                                    */
8829             __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
8830                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8831                                          *   means counter running.                                                    */
8832             __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
8833                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8834                                          *   means counter running.                                                    */
8835             __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
8836                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8837                                          *   means counter running.                                                    */
8838             __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
8839                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8840                                          *   means counter running.                                                    */
8841             __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
8842                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8843                                          *   means counter running.                                                    */
8844             __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
8845                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8846                                          *   means counter running.                                                    */
8847             __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
8848                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8849                                          *   means counter running.                                                    */
8850             __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
8851                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8852                                          *   means counter running.                                                    */
8853             __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
8854                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8855                                          *   means counter running.                                                    */
8856             __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
8857                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8858                                          *   means counter running.                                                    */
8859             __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
8860                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8861                                          *   means counter running.                                                    */
8862             __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
8863                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8864                                          *   means counter running.                                                    */
8865             __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
8866                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8867                                          *   means counter running.                                                    */
8868             __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
8869                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8870                                          *   means counter running.                                                    */
8871             __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
8872                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8873                                          *   means counter running.                                                    */
8874             __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
8875                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8876                                          *   means counter running.                                                    */
8877             __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
8878                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8879                                          *   means counter running.                                                    */
8880             __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
8881                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8882                                          *   means counter running.                                                    */
8883             __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
8884                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8885                                          *   means counter running.                                                    */
8886             __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
8887                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8888                                          *   means counter running.                                                    */
8889             __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
8890                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8891                                          *   means counter running.                                                    */
8892             __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
8893                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8894                                          *   means counter running.                                                    */
8895             __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
8896                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8897                                          *   means counter running.                                                    */
8898             __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
8899                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8900                                          *   means counter running.                                                    */
8901             __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
8902                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8903                                          *   means counter running.                                                    */
8904             __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
8905                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8906                                          *   means counter running.                                                    */
8907             __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
8908                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8909                                          *   means counter running.                                                    */
8910             __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
8911                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8912                                          *   means counter running.                                                    */
8913             __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
8914                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8915                                          *   means counter running.                                                    */
8916             __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
8917                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
8918                                          *   means counter running.                                                    */
8919         } GTSTR_b;
8920     };
8921 
8922     union
8923     {
8924         __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
8925 
8926         struct
8927         {
8928             __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
8929                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8930                                          *   1 means counter stop.                                                     */
8931             __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
8932                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8933                                          *   1 means counter stop.                                                     */
8934             __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
8935                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8936                                          *   1 means counter stop.                                                     */
8937             __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
8938                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8939                                          *   1 means counter stop.                                                     */
8940             __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
8941                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8942                                          *   1 means counter stop.                                                     */
8943             __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
8944                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8945                                          *   1 means counter stop.                                                     */
8946             __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
8947                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8948                                          *   1 means counter stop.                                                     */
8949             __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
8950                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8951                                          *   1 means counter stop.                                                     */
8952             __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
8953                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8954                                          *   1 means counter stop.                                                     */
8955             __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
8956                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8957                                          *   1 means counter stop.                                                     */
8958             __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
8959                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8960                                          *   1 means counter stop.                                                     */
8961             __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
8962                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8963                                          *   1 means counter stop.                                                     */
8964             __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
8965                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8966                                          *   1 means counter stop.                                                     */
8967             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
8968                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8969                                          *   1 means counter stop.                                                     */
8970             __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
8971                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8972                                          *   1 means counter stop.                                                     */
8973             __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
8974                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8975                                          *   1 means counter stop.                                                     */
8976             __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
8977                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8978                                          *   1 means counter stop.                                                     */
8979             __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
8980                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8981                                          *   1 means counter stop.                                                     */
8982             __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
8983                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8984                                          *   1 means counter stop.                                                     */
8985             __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
8986                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8987                                          *   1 means counter stop.                                                     */
8988             __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
8989                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8990                                          *   1 means counter stop.                                                     */
8991             __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
8992                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8993                                          *   1 means counter stop.                                                     */
8994             __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
8995                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8996                                          *   1 means counter stop.                                                     */
8997             __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
8998                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
8999                                          *   1 means counter stop.                                                     */
9000             __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
9001                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9002                                          *   1 means counter stop.                                                     */
9003             __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
9004                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9005                                          *   1 means counter stop.                                                     */
9006             __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
9007                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9008                                          *   1 means counter stop.                                                     */
9009             __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
9010                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9011                                          *   1 means counter stop.                                                     */
9012             __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
9013                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9014                                          *   1 means counter stop.                                                     */
9015             __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
9016                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9017                                          *   1 means counter stop.                                                     */
9018             __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
9019                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9020                                          *   1 means counter stop.                                                     */
9021             __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
9022                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
9023                                          *   1 means counter stop.                                                     */
9024         } GTSTP_b;
9025     };
9026 
9027     union
9028     {
9029         __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
9030 
9031         struct
9032         {
9033             __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
9034             __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
9035             __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
9036             __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
9037             __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
9038             __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
9039             __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
9040             __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
9041             __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
9042             __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
9043             __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
9044             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
9045             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
9046             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
9047             __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
9048             __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
9049             __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
9050             __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
9051             __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
9052             __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
9053             __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
9054             __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
9055             __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
9056             __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
9057             __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
9058             __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
9059             __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
9060             __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
9061             __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
9062             __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
9063             __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
9064             __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
9065         } GTCLR_b;
9066     };
9067 
9068     union
9069     {
9070         __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
9071 
9072         struct
9073         {
9074             __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
9075             __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
9076             __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
9077             __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
9078             __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
9079             __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
9080             __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
9081             __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
9082             __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9083                                           *   Counter Start Enable                                                      */
9084             __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9085                                           *   Counter Start Enable                                                      */
9086             __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9087                                           *   Counter Start Enable                                                      */
9088             __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9089                                           *   Counter Start Enable                                                      */
9090             __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9091                                           *   Counter Start Enable                                                      */
9092             __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9093                                           *   Counter Start Enable                                                      */
9094             __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9095                                           *   Counter Start Enable                                                      */
9096             __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9097                                           *   Counter Start Enable                                                      */
9098             __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
9099             __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
9100             __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
9101             __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
9102             __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
9103             __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
9104             __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
9105             __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
9106             uint32_t              : 7;
9107             __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
9108         } GTSSR_b;
9109     };
9110 
9111     union
9112     {
9113         __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
9114 
9115         struct
9116         {
9117             __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
9118             __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
9119             __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
9120             __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
9121             __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
9122             __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
9123             __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
9124             __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
9125             __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9126                                           *   Counter Stop Enable                                                       */
9127             __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9128                                           *   Counter Stop Enable                                                       */
9129             __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9130                                           *   Counter Stop Enable                                                       */
9131             __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9132                                           *   Counter Stop Enable                                                       */
9133             __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9134                                           *   Counter Stop Enable                                                       */
9135             __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9136                                           *   Counter Stop Enable                                                       */
9137             __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9138                                           *   Counter Stop Enable                                                       */
9139             __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9140                                           *   Counter Stop Enable                                                       */
9141             __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
9142             __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
9143             __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
9144             __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
9145             __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
9146             __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
9147             __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
9148             __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
9149             uint32_t              : 7;
9150             __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
9151         } GTPSR_b;
9152     };
9153 
9154     union
9155     {
9156         __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
9157 
9158         struct
9159         {
9160             __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
9161             __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
9162             __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
9163             __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
9164             __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
9165             __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
9166             __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
9167             __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
9168             __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9169                                           *   Counter Clear Enable                                                      */
9170             __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9171                                           *   Counter Clear Enable                                                      */
9172             __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9173                                           *   Counter Clear Enable                                                      */
9174             __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9175                                           *   Counter Clear Enable                                                      */
9176             __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9177                                           *   Counter Clear Enable                                                      */
9178             __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9179                                           *   Counter Clear Enable                                                      */
9180             __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9181                                           *   Counter Clear Enable                                                      */
9182             __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9183                                           *   Counter Clear Enable                                                      */
9184             __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
9185             __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
9186             __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
9187             __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
9188             __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
9189             __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
9190             __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
9191             __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
9192             __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
9193                                           *   Source Counter Clear Enable.                                              */
9194             __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
9195                                           *   Enable (This bit is only available in GPT324 to GPT329.
9196                                           *   In GPT320 to GPT323, this bit is read as 0. The write value
9197                                           *   should be 0.)                                                             */
9198             uint32_t            : 3;
9199             __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
9200         } GTCSR_b;
9201     };
9202 
9203     union
9204     {
9205         __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
9206 
9207         struct
9208         {
9209             __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
9210             __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
9211             __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
9212             __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
9213             __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
9214             __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
9215             __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
9216             __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
9217             __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9218                                           *   Counter Count Up Enable                                                   */
9219             __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9220                                           *   Counter Count Up Enable                                                   */
9221             __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9222                                           *   Counter Count Up Enable                                                   */
9223             __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9224                                           *   Counter Count Up Enable                                                   */
9225             __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9226                                           *   Counter Count Up Enable                                                   */
9227             __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9228                                           *   Counter Count Up Enable                                                   */
9229             __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9230                                           *   Counter Count Up Enable                                                   */
9231             __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9232                                           *   Counter Count Up Enable                                                   */
9233             __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
9234             __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
9235             __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
9236             __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
9237             __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
9238             __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
9239             __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
9240             __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
9241             __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
9242             uint32_t              : 4;
9243         } GTUPSR_b;
9244     };
9245 
9246     union
9247     {
9248         __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
9249 
9250         struct
9251         {
9252             __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
9253             __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
9254             __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
9255             __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
9256             __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
9257             __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
9258             __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
9259             __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
9260             __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9261                                           *   Counter Count Down Enable                                                 */
9262             __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9263                                           *   Counter Count Down Enable                                                 */
9264             __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9265                                           *   Counter Count Down Enable                                                 */
9266             __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9267                                           *   Counter Count Down Enable                                                 */
9268             __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9269                                           *   Counter Count Down Enable                                                 */
9270             __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9271                                           *   Counter Count Down Enable                                                 */
9272             __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9273                                           *   Counter Count Down Enable                                                 */
9274             __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9275                                           *   Counter Count Down Enable                                                 */
9276             __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
9277             __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
9278             __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
9279             __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
9280             __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
9281             __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
9282             __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
9283             __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
9284             __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
9285             uint32_t              : 4;
9286         } GTDNSR_b;
9287     };
9288 
9289     union
9290     {
9291         __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
9292                                           *                  Register A                                                 */
9293 
9294         struct
9295         {
9296             __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
9297             __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
9298                                           *   Enable                                                                    */
9299             __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
9300             __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
9301                                           *   Enable                                                                    */
9302             __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
9303             __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
9304                                           *   Enable                                                                    */
9305             __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
9306             __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
9307                                           *   Enable                                                                    */
9308             __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9309                                           *   GTCCRA Input Capture Enable                                               */
9310             __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9311                                           *   GTCCRA Input Capture Enable                                               */
9312             __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9313                                           *   GTCCRA Input Capture Enable                                               */
9314             __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9315                                           *   GTCCRA Input Capture Enable                                               */
9316             __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9317                                           *   GTCCRA Input Capture Enable                                               */
9318             __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9319                                           *   GTCCRA Input Capture Enable                                               */
9320             __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9321                                           *   GTCCRA Input Capture Enable                                               */
9322             __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9323                                           *   GTCCRA Input Capture Enable                                               */
9324             __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
9325             __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
9326             __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
9327             __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
9328             __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
9329             __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
9330             __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
9331             __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
9332             uint32_t              : 8;
9333         } GTICASR_b;
9334     };
9335 
9336     union
9337     {
9338         __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
9339                                           *                  Register B                                                 */
9340 
9341         struct
9342         {
9343             __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
9344             __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
9345                                           *   Enable                                                                    */
9346             __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
9347             __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
9348                                           *   Enable                                                                    */
9349             __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
9350             __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
9351                                           *   Enable                                                                    */
9352             __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
9353             __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
9354                                           *   Enable                                                                    */
9355             __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
9356                                           *   GTCCRB Input Capture Enable                                               */
9357             __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
9358                                           *   GTCCRB Input Capture Enable                                               */
9359             __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
9360                                           *   GTCCRB Input Capture Enable                                               */
9361             __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
9362                                           *   GTCCRB Input Capture Enable                                               */
9363             __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
9364                                           *   GTCCRB Input Capture Enable                                               */
9365             __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
9366                                           *   GTCCRB Input Capture Enable                                               */
9367             __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
9368                                           *   GTCCRB Input Capture Enable                                               */
9369             __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
9370                                           *   GTCCRB Input Capture Enable                                               */
9371             __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
9372             __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
9373             __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
9374             __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
9375             __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
9376             __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
9377             __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
9378             __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
9379             uint32_t              : 8;
9380         } GTICBSR_b;
9381     };
9382 
9383     union
9384     {
9385         __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
9386 
9387         struct
9388         {
9389             __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
9390             uint32_t               : 7;
9391             __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
9392             __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
9393             __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
9394             __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
9395             uint32_t               : 2;
9396             __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
9397             __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
9398             uint32_t               : 3;
9399             __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
9400             __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
9401             uint32_t               : 3;
9402         } GTCR_b;
9403     };
9404 
9405     union
9406     {
9407         __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
9408                                         *                  Register                                                   */
9409 
9410         struct
9411         {
9412             __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
9413             __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
9414             uint32_t              : 14;
9415             __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
9416             __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
9417             __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
9418                                         *   percent Duty Setting                                                      */
9419             uint32_t              : 4;
9420             __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
9421             __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
9422             __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
9423                                         *   percent Duty Setting                                                      */
9424             uint32_t : 4;
9425         } GTUDDTYC_b;
9426     };
9427 
9428     union
9429     {
9430         __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
9431 
9432         struct
9433         {
9434             __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
9435             __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
9436                                         *   Clear Disable.(This bit is only available in GPT324 to
9437                                         *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
9438                                         *   write value should be 0.)                                                 */
9439             __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
9440             __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
9441             __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
9442             __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
9443             __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
9444                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
9445                                         *   GPT323, this bit is read as 0. The write value should be
9446                                         *   0.)                                                                       */
9447             __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
9448             __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
9449             __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
9450             __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
9451             uint32_t              : 1;
9452             __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
9453             __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
9454             __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
9455             __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
9456             __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
9457                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
9458                                         *   GPT323, this bit is read as 0. The write value should be
9459                                         *   0.)                                                                       */
9460             uint32_t             : 1;
9461             __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
9462             __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
9463         } GTIOR_b;
9464     };
9465 
9466     union
9467     {
9468         __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
9469 
9470         struct
9471         {
9472             uint32_t            : 8;
9473             __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
9474                                           *   Clear Enable                                                              */
9475             __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
9476                                           *   Clear Enable                                                              */
9477             __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
9478                                           *   Synchronous Clear Enable                                                  */
9479             __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
9480                                           *   Synchronous Clear Enable                                                  */
9481             __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
9482                                           *   Synchronous Clear Enable                                                  */
9483             __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
9484                                           *   Synchronous Clear Enable                                                  */
9485             __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
9486             __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
9487             __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
9488                                           *   Start Request Enable                                                      */
9489             __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
9490                                           *   Conversion Start Request Enable                                           */
9491             __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
9492                                           *   Start Request Enable                                                      */
9493             __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
9494                                           *   Conversion Start Request Enable                                           */
9495             uint32_t               : 4;
9496             __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
9497             uint32_t               : 2;
9498             __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
9499             __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
9500             __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
9501             __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
9502         } GTINTAD_b;
9503     };
9504 
9505     union
9506     {
9507         __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
9508 
9509         struct
9510         {
9511             __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
9512             __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
9513             __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
9514             __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
9515             __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
9516             __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
9517             __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
9518             __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
9519             __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
9520                                          *   for counting the number of times a timer interrupt has
9521                                          *   been skipped.)                                                            */
9522             uint32_t               : 4;
9523             __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
9524             __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
9525                                          *   Request Interrupt Enable                                                  */
9526             __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
9527                                          *   Start Request Flag                                                        */
9528             __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
9529                                          *   Request Flag                                                              */
9530             __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
9531                                          *   Start Request Flag                                                        */
9532             uint32_t             : 4;
9533             __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
9534             uint32_t             : 3;
9535             __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
9536             __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
9537             __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
9538             __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
9539         } GTST_b;
9540     };
9541 
9542     union
9543     {
9544         __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
9545 
9546         struct
9547         {
9548             __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
9549             __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
9550             __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
9551             __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
9552             uint32_t               : 4;
9553             __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
9554             uint32_t               : 1;
9555             __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
9556             uint32_t               : 5;
9557             __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
9558             __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
9559             __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
9560             __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
9561                                          *   is read as 0.                                                             */
9562             uint32_t             : 1;
9563             __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
9564                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
9565                                          *   at an underflow (in down-counting) or overflow (in up-counting)
9566                                          *   is performed.                                                             */
9567             __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
9568             uint32_t             : 1;
9569             __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
9570                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
9571                                          *   at an underflow (in down-counting) or overflow (in up-counting)
9572                                          *   is performed.                                                             */
9573             __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
9574             uint32_t             : 1;
9575         } GTBER_b;
9576     };
9577 
9578     union
9579     {
9580         __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
9581                                         *                  Start Request Skipping Setting Register                    */
9582 
9583         struct
9584         {
9585             __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
9586             __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
9587             __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
9588             __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
9589             __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
9590             __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
9591             __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
9592             __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
9593             uint32_t             : 1;
9594             __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
9595             uint32_t             : 1;
9596             __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
9597             uint32_t             : 17;
9598         } GTITC_b;
9599     };
9600 
9601     union
9602     {
9603         __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
9604 
9605         struct
9606         {
9607             __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
9608         } GTCNT_b;
9609     };
9610 
9611     union
9612     {
9613         __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
9614 
9615         struct
9616         {
9617             __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
9618         } GTCCR_b[6];
9619     };
9620 
9621     union
9622     {
9623         __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
9624 
9625         struct
9626         {
9627             __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
9628         } GTPR_b;
9629     };
9630 
9631     union
9632     {
9633         __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
9634 
9635         struct
9636         {
9637             __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
9638         } GTPBR_b;
9639     };
9640 
9641     union
9642     {
9643         __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
9644                                          *                  Register                                                   */
9645 
9646         struct
9647         {
9648             __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
9649         } GTPDBR_b;
9650     };
9651 
9652     union
9653     {
9654         __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
9655 
9656         struct
9657         {
9658             __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
9659         } GTADTRA_b;
9660     };
9661 
9662     union
9663     {
9664         __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
9665                                            *                  A                                                          */
9666 
9667         struct
9668         {
9669             __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
9670         } GTADTBRA_b;
9671     };
9672 
9673     union
9674     {
9675         __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
9676                                             *                  Register A                                                 */
9677 
9678         struct
9679         {
9680             __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
9681                                             *   A                                                                         */
9682         } GTADTDBRA_b;
9683     };
9684 
9685     union
9686     {
9687         __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
9688 
9689         struct
9690         {
9691             __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
9692         } GTADTRB_b;
9693     };
9694 
9695     union
9696     {
9697         __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
9698                                            *                  B                                                          */
9699 
9700         struct
9701         {
9702             __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
9703         } GTADTBRB_b;
9704     };
9705 
9706     union
9707     {
9708         __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
9709                                             *                  Register B                                                 */
9710 
9711         struct
9712         {
9713             __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
9714                                             *   B                                                                         */
9715         } GTADTDBRB_b;
9716     };
9717 
9718     union
9719     {
9720         __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
9721 
9722         struct
9723         {
9724             __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
9725             uint32_t             : 3;
9726             __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
9727             __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
9728             uint32_t             : 2;
9729             __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
9730             uint32_t             : 23;
9731         } GTDTCR_b;
9732     };
9733 
9734     union
9735     {
9736         __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
9737 
9738         struct
9739         {
9740             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
9741         } GTDVU_b;
9742     };
9743 
9744     union
9745     {
9746         __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
9747 
9748         struct
9749         {
9750             __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
9751         } GTDVD_b;
9752     };
9753 
9754     union
9755     {
9756         __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
9757 
9758         struct
9759         {
9760             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
9761         } GTDBU_b;
9762     };
9763 
9764     union
9765     {
9766         __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
9767 
9768         struct
9769         {
9770             __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
9771         } GTDBD_b;
9772     };
9773 
9774     union
9775     {
9776         __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
9777                                         *                  Status Register                                            */
9778 
9779         struct
9780         {
9781             __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
9782             uint32_t          : 30;
9783         } GTSOS_b;
9784     };
9785 
9786     union
9787     {
9788         __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
9789                                         *                  Temporary Release Register                                 */
9790 
9791         struct
9792         {
9793             __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
9794             uint32_t            : 31;
9795         } GTSOTR_b;
9796     };
9797 
9798     union
9799     {
9800         __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
9801                                          *                  Signal Monitoring Register                                 */
9802 
9803         struct
9804         {
9805             __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
9806             uint32_t               : 6;
9807             __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
9808                                          *   Enabling                                                                  */
9809             uint32_t               : 7;
9810             __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
9811             uint32_t               : 6;
9812             __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
9813                                          *   Enabling                                                                  */
9814             uint32_t : 7;
9815         } GTADSMR_b;
9816     };
9817 
9818     union
9819     {
9820         __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
9821                                            *                  Counter Control Register                                   */
9822 
9823         struct
9824         {
9825             __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
9826             uint32_t               : 2;
9827             __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
9828             uint32_t               : 4;
9829             __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
9830             __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
9831                                            *   select                                                                    */
9832             uint32_t                 : 2;
9833             __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
9834             __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
9835             __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
9836         } GTEITC_b;
9837     };
9838 
9839     union
9840     {
9841         __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
9842                                         *                  Setting Register 1                                         */
9843 
9844         struct
9845         {
9846             __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
9847                                         *   Extended Skipping Function Select                                         */
9848             uint32_t             : 1;
9849             __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
9850                                         *   Extended Skipping Function Select                                         */
9851             uint32_t             : 1;
9852             __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
9853                                         *   Function Select                                                           */
9854             uint32_t             : 1;
9855             __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
9856                                         *   Function Select                                                           */
9857             uint32_t             : 1;
9858             __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
9859                                         *   Function Select                                                           */
9860             uint32_t             : 1;
9861             __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
9862                                         *   Function Select                                                           */
9863             uint32_t             : 1;
9864             __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
9865             uint32_t             : 1;
9866             __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
9867             uint32_t             : 1;
9868         } GTEITLI1_b;
9869     };
9870 
9871     union
9872     {
9873         __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
9874                                         *                  Setting Register 2                                         */
9875 
9876         struct
9877         {
9878             __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
9879                                         *   Skipping Function Select                                                  */
9880             uint32_t              : 1;
9881             __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
9882                                         *   Skipping Function Select                                                  */
9883             uint32_t : 25;
9884         } GTEITLI2_b;
9885     };
9886 
9887     union
9888     {
9889         __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
9890                                          *                  Setting Register                                           */
9891 
9892         struct
9893         {
9894             __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
9895                                          *   Select                                                                    */
9896             uint32_t              : 1;
9897             __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
9898                                          *   Select                                                                    */
9899             uint32_t              : 1;
9900             __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
9901                                          *   Select                                                                    */
9902             uint32_t               : 5;
9903             __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
9904                                          *   Function Select                                                           */
9905             uint32_t               : 1;
9906             __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
9907                                          *   Function Select                                                           */
9908             uint32_t               : 1;
9909             __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
9910                                          *   Select                                                                    */
9911             uint32_t               : 1;
9912             __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
9913                                          *   Select                                                                    */
9914             uint32_t : 1;
9915         } GTEITLB_b;
9916     };
9917 
9918     union
9919     {
9920         __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
9921                                           *                  Function Setting Register                                  */
9922 
9923         struct
9924         {
9925             __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
9926             uint32_t                : 1;
9927             __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
9928             uint32_t                : 6;
9929             __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
9930             uint32_t                : 1;
9931             __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
9932             uint32_t                : 6;
9933         } GTICLF_b;
9934     };
9935 
9936     union
9937     {
9938         __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
9939 
9940         struct
9941         {
9942             __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
9943             uint32_t            : 7;
9944             __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
9945             uint32_t            : 7;
9946             __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
9947             uint32_t            : 4;
9948         } GTPC_b;
9949     };
9950     __IM uint32_t RESERVED[4];
9951 
9952     union
9953     {
9954         __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
9955                                          *                  Control Channel Select Register                            */
9956 
9957         struct
9958         {
9959             __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
9960                                          *   Select                                                                    */
9961             __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
9962                                          *   Select                                                                    */
9963             __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
9964                                          *   Select                                                                    */
9965             __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
9966                                          *   Select                                                                    */
9967             __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
9968                                          *   Select                                                                    */
9969             __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
9970                                          *   Select                                                                    */
9971             __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
9972                                          *   Select                                                                    */
9973             __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
9974                                          *   Select                                                                    */
9975             __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
9976                                          *   Select                                                                    */
9977             __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
9978                                          *   Select                                                                    */
9979             uint32_t : 22;
9980         } GTSECSR_b;
9981     };
9982 
9983     union
9984     {
9985         __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
9986                                         *                  Control Register                                           */
9987 
9988         struct
9989         {
9990             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
9991             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
9992             __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
9993             __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
9994             uint32_t             : 4;
9995             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
9996             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
9997             __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
9998             __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
9999             uint32_t             : 4;
10000             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
10001             __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
10002             uint32_t             : 6;
10003             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
10004             __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
10005             uint32_t             : 6;
10006         } GTSECR_b;
10007     };
10008     __IM uint32_t RESERVED1[2];
10009 
10010     union
10011     {
10012         __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
10013 
10014         struct
10015         {
10016             __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
10017                                         *   Disable                                                                   */
10018             __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
10019                                         *   Disable                                                                   */
10020             __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
10021             __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
10022                                         *   Disable                                                                   */
10023             __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
10024                                         *   Disable                                                                   */
10025             __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
10026                                         *   Disable                                                                   */
10027             uint32_t             : 2;
10028             __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
10029                                         *   Enable                                                                    */
10030             __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
10031                                         *   Enable                                                                    */
10032             uint32_t              : 1;
10033             __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
10034                                         *   Enable                                                                    */
10035             __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
10036                                         *   Enable                                                                    */
10037             uint32_t             : 1;
10038             __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
10039                                         *   Disable                                                                   */
10040             __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
10041                                         *   Disable                                                                   */
10042             __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
10043                                         *   Disable                                                                   */
10044             __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
10045                                         *   Disable                                                                   */
10046             __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
10047                                         *   Disable                                                                   */
10048             __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
10049                                         *   Transfer Disable                                                          */
10050             uint32_t             : 2;
10051             __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
10052             __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
10053             __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
10054             __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
10055             uint32_t             : 2;
10056         } GTBER2_b;
10057     };
10058 
10059     union
10060     {
10061         __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
10062 
10063         struct
10064         {
10065             __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
10066             uint32_t              : 11;
10067             __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
10068             uint32_t              : 11;
10069         } GTOLBR_b;
10070     };
10071     __IM uint32_t RESERVED2;
10072 
10073     union
10074     {
10075         __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
10076                                         *                  Capture Control Register                                   */
10077 
10078         struct
10079         {
10080             __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
10081                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
10082             __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
10083                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
10084             __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
10085                                         *   Channel GTCCRA Input Capture Source Enable                                */
10086             __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
10087                                         *   Channel GTCCRA Input Capture Source Enable                                */
10088             __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
10089                                         *   Channel GTCCRA Input Capture Source Enable                                */
10090             __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
10091                                         *   Channel GTCCRA Input Capture Source Enable                                */
10092             __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
10093                                         *   Source Enable                                                             */
10094             __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
10095                                         *   Source Enable                                                             */
10096             __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
10097                                         *   Capture Source Enable                                                     */
10098             uint32_t              : 5;
10099             __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
10100             __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
10101                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
10102             __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
10103                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
10104             __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
10105                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
10106             __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
10107                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
10108             __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
10109                                         *   Other Channel GTCCRb Input Capture Source Enable                          */
10110             __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
10111                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
10112             __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
10113                                         *   Source Enable                                                             */
10114             __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
10115                                         *   Capture Source Enable                                                     */
10116             __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
10117                                         *   Capture Source Enable                                                     */
10118             uint32_t              : 5;
10119             __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
10120         } GTICCR_b;
10121     };
10122 } R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
10123 
10124 /* =========================================================================================================================== */
10125 /* ================                                         R_GPT_OPS                                         ================ */
10126 /* =========================================================================================================================== */
10127 
10128 /**
10129  * @brief Output Phase Switching for GPT (R_GPT_OPS)
10130  */
10131 
10132 typedef struct                         /*!< (@ 0x40323F00) R_GPT_OPS Structure                                        */
10133 {
10134     union
10135     {
10136         __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
10137 
10138         struct
10139         {
10140             __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
10141                                         *   by the software settings.This bit setting is valid when
10142                                         *   the OPSCR.FB bit = 1.                                                     */
10143             __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
10144                                         *   by the software settings.This bit setting is valid when
10145                                         *   the OPSCR.FB bit = 1.                                                     */
10146             __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
10147                                         *   by the software settings.This bit setting is valid when
10148                                         *   the OPSCR.FB bit = 1.                                                     */
10149             uint32_t        : 1;
10150             __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
10151                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
10152                                         *   e settings (UF/VF/WF)                                                     */
10153             __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
10154                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
10155                                         *   e settings (UF/VF/WF)                                                     */
10156             __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
10157                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
10158                                         *   e settings (UF/VF/WF)                                                     */
10159             uint32_t          : 1;
10160             __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
10161             uint32_t          : 7;
10162             __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
10163                                         *   input phase from the software settings and external input.                */
10164             __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
10165             __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
10166             __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
10167             __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
10168             __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
10169             uint32_t             : 2;
10170             __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
10171             __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
10172             uint32_t             : 2;
10173             __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
10174             __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
10175                                         *   sampling clock setting of the external input.                             */
10176         } OPSCR_b;
10177     };
10178 } R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
10179 
10180 /* =========================================================================================================================== */
10181 /* ================                                        R_GPT_POEG0                                        ================ */
10182 /* =========================================================================================================================== */
10183 
10184 /**
10185  * @brief Port Output Enable for GPT (R_GPT_POEG0)
10186  */
10187 
10188 typedef struct                          /*!< (@ 0x40212000) R_GPT_POEG0 Structure                                      */
10189 {
10190     union
10191     {
10192         __IOM uint32_t POEGG;           /*!< (@ 0x00000000) POEG Group Setting Register                                */
10193 
10194         struct
10195         {
10196             __IOM uint32_t PIDF  : 1;   /*!< [0..0] Port Input Detection Flag                                          */
10197             __IOM uint32_t IOCF  : 1;   /*!< [1..1] Real Time Overcurrent Detection Flag                               */
10198             __IOM uint32_t OSTPF : 1;   /*!< [2..2] Oscillation Stop Detection Flag                                    */
10199             __IOM uint32_t SSF   : 1;   /*!< [3..3] Software Stop Flag                                                 */
10200             __IOM uint32_t PIDE  : 1;   /*!< [4..4] Port Input Detection Enable. Note: Can be modified only
10201                                          *   once after a reset.                                                       */
10202             __IOM uint32_t IOCE : 1;    /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified
10203                                          *   only once after a reset.                                                  */
10204             __IOM uint32_t OSTPE : 1;   /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified
10205                                          *   only once after a reset.                                                  */
10206             uint32_t             : 1;
10207             __IOM uint32_t CDRE0 : 1;   /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
10208                                          *   only once after a reset.                                                  */
10209             __IOM uint32_t CDRE1 : 1;   /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
10210                                          *   only once after a reset.                                                  */
10211             __IOM uint32_t CDRE2 : 1;   /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
10212                                          *   only once after a reset.                                                  */
10213             __IOM uint32_t CDRE3 : 1;   /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
10214                                          *   only once after a reset.                                                  */
10215             __IOM uint32_t CDRE4 : 1;   /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
10216                                          *   only once after a reset.                                                  */
10217             __IOM uint32_t CDRE5 : 1;   /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
10218                                          *   only once after a reset.                                                  */
10219             uint32_t               : 2;
10220             __IM uint32_t ST       : 1; /*!< [16..16] GTETRG Input Status Flag                                         */
10221             uint32_t               : 7;
10222             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag                                      */
10223             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag                                      */
10224             __IOM uint32_t DERR0E  : 1; /*!< [26..26] DSMIF0 Error Detection Enable                                    */
10225             __IOM uint32_t DERR1E  : 1; /*!< [27..27] DSMIF1 Error Detection Enable                                    */
10226             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRG Input Reverse                                             */
10227             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise Filter Enable                                              */
10228             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise Filter Clock Select                                        */
10229         } POEGG_b;
10230     };
10231     __IM uint32_t RESERVED[15];
10232 
10233     union
10234     {
10235         __IOM uint16_t GTONCWP;        /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection
10236                                         *                  Register                                                   */
10237 
10238         struct
10239         {
10240             __IOM uint16_t WP    : 1;  /*!< [0..0] Register Writing Disable                                           */
10241             uint16_t             : 7;
10242             __IOM uint16_t PRKEY : 8;  /*!< [15..8] Key Code                                                          */
10243         } GTONCWP_b;
10244     };
10245     __IM uint16_t RESERVED1;
10246 
10247     union
10248     {
10249         __IOM uint16_t GTONCCR;        /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling
10250                                         *                  Register                                                   */
10251 
10252         struct
10253         {
10254             __IOM uint16_t NE  : 1;    /*!< [0..0] Direct Stopping Request Setting                                    */
10255             uint16_t           : 3;
10256             __IOM uint16_t NFS : 4;    /*!< [7..4] Direct Stopping Request Selection                                  */
10257             __IOM uint16_t NFV : 1;    /*!< [8..8] Direct Stopping Request Active Sense                               */
10258             uint16_t           : 7;
10259         } GTONCCR_b;
10260     };
10261     __IM uint16_t RESERVED2;
10262 } R_GPT_POEG0_Type;                    /*!< Size = 72 (0x48)                                                          */
10263 
10264 /* =========================================================================================================================== */
10265 /* ================                                           R_ICU                                           ================ */
10266 /* =========================================================================================================================== */
10267 
10268 /**
10269  * @brief Interrupt Controller Unit (R_ICU)
10270  */
10271 
10272 typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
10273 {
10274     union
10275     {
10276         __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
10277 
10278         struct
10279         {
10280             __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
10281             uint8_t               : 2;
10282             __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
10283             uint8_t               : 1;
10284             __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
10285         } IRQCR_b[16];
10286     };
10287 
10288     union
10289     {
10290         __IM uint8_t NMICR;             /*!< (@ 0x00000010) NMI Pin Interrupt Control Register                         */
10291 
10292         struct
10293         {
10294             __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
10295             uint8_t                : 3;
10296             __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock                                  */
10297             uint8_t                : 1;
10298             __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
10299         } NMICR_b;
10300     };
10301     __IM uint8_t  RESERVED;
10302     __IM uint16_t RESERVED1;
10303     __IM uint32_t RESERVED2[6143];
10304 
10305     union
10306     {
10307         __IOM uint8_t SWIRQ_S;         /*!< (@ 0x00006010) Software Interrupt Request Register for Secure
10308                                         *                  Interrupt                                                  */
10309 
10310         struct
10311         {
10312             __IOM uint8_t SWIRQS : 1;  /*!< [0..0] Generates an interrupt for the other CPU subsystem.                */
10313             uint8_t              : 7;
10314         } SWIRQ_S_b;
10315     };
10316     __IM uint8_t  RESERVED3;
10317     __IM uint16_t RESERVED4;
10318     __IM uint32_t RESERVED5[3];
10319 
10320     union
10321     {
10322         __IOM uint8_t SWIRQ_NS;        /*!< (@ 0x00006020) Software Interrupt Request Register for Non-secure
10323                                         *                  Interrupt                                                  */
10324 
10325         struct
10326         {
10327             __IOM uint8_t SWIRQNS : 1; /*!< [0..0] Generates an interrupt for the other CPU subsystem.                */
10328             uint8_t               : 7;
10329         } SWIRQ_NS_b;
10330     };
10331     __IM uint8_t  RESERVED6;
10332     __IM uint16_t RESERVED7;
10333     __IM uint32_t RESERVED8[15];
10334 
10335     union
10336     {
10337         __IOM uint16_t IENMIER;        /*!< (@ 0x00006060) Integrated Error NMI Interrupt Enable Registe
10338                                         *                  for CPU                                                    */
10339 
10340         struct
10341         {
10342             __IOM uint16_t CMEN  : 1;  /*!< [0..0] Integrated Common Memory error nmi Enable                          */
10343             __IOM uint16_t LMEN  : 1;  /*!< [1..1] Integrated Local Memory error nmi Enable                           */
10344             __IOM uint16_t BUSEN : 1;  /*!< [2..2] Integrated BUS error nmi Enable                                    */
10345             uint16_t             : 13;
10346         } IENMIER_b;
10347     };
10348     __IM uint16_t RESERVED9;
10349     __IM uint32_t RESERVED10[39];
10350 
10351     union
10352     {
10353         __IOM uint16_t NMIER;          /*!< (@ 0x00006100) Non-Maskable Interrupt Enable Register                     */
10354 
10355         struct
10356         {
10357             __IOM uint16_t IWDTEN : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
10358             __IOM uint16_t WDTEN  : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
10359             __IOM uint16_t LVD1EN : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
10360             __IOM uint16_t LVD2EN : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
10361             uint16_t              : 2;
10362             __IOM uint16_t OSTEN  : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
10363             __IOM uint16_t NMIEN  : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
10364             uint16_t              : 4;
10365             __IOM uint16_t BUSEN  : 1; /*!< [12..12] BUS error Interrupt Enable                                       */
10366             __IOM uint16_t CMEN   : 1; /*!< [13..13] Common Memory error Interrupt Enable                             */
10367             uint16_t              : 1;
10368             __IOM uint16_t LUEN   : 1; /*!< [15..15] LockUp Interrupt Enable                                          */
10369         } NMIER_b;
10370     };
10371     __IM uint16_t RESERVED11;
10372     __IM uint32_t RESERVED12[3];
10373 
10374     union
10375     {
10376         __IOM uint16_t NMICLR;          /*!< (@ 0x00006110) Non-Maskable Interrupt Status Clear Register               */
10377 
10378         struct
10379         {
10380             __IOM uint16_t IWDTCLR : 1; /*!< [0..0] IWDT Clear                                                         */
10381             __IOM uint16_t WDTCLR  : 1; /*!< [1..1] WDT Clear                                                          */
10382             __IOM uint16_t LVD1CLR : 1; /*!< [2..2] PVD1 Clear                                                         */
10383             __IOM uint16_t LVD2CLR : 1; /*!< [3..3] PVD2 Clear                                                         */
10384             uint16_t               : 2;
10385             __IOM uint16_t OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
10386             __IOM uint16_t NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
10387             uint16_t               : 4;
10388             __IOM uint16_t BUSCLR  : 1; /*!< [12..12] Bus Clear                                                        */
10389             __IOM uint16_t CMCLR   : 1; /*!< [13..13] CM Clear                                                         */
10390             uint16_t               : 1;
10391             __IOM uint16_t LUCLR   : 1; /*!< [15..15] LU Clear                                                         */
10392         } NMICLR_b;
10393     };
10394     __IM uint16_t RESERVED13;
10395     __IM uint32_t RESERVED14[3];
10396 
10397     union
10398     {
10399         __IM uint16_t NMISR;           /*!< (@ 0x00006120) Non-Maskable Interrupt Status Register                     */
10400 
10401         struct
10402         {
10403             __IM uint16_t IWDTST : 1;  /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
10404             __IM uint16_t WDTST  : 1;  /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
10405             __IM uint16_t LVD1ST : 1;  /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
10406             __IM uint16_t LVD2ST : 1;  /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
10407             uint16_t             : 2;
10408             __IM uint16_t OSTST  : 1;  /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
10409             __IM uint16_t NMIST  : 1;  /*!< [7..7] NMI Status Flag                                                    */
10410             uint16_t             : 4;
10411             __IM uint16_t BUSST  : 1;  /*!< [12..12] BUS error Interrupt Status Flag                                  */
10412             __IM uint16_t CMST   : 1;  /*!< [13..13] Common Memory error Interrupt Status Flag                        */
10413             uint16_t             : 1;
10414             __IM uint16_t LUST   : 1;  /*!< [15..15] LockUp Interrupt Status Flag                                     */
10415         } NMISR_b;
10416     };
10417     __IM uint16_t RESERVED15;
10418     __IM uint32_t RESERVED16[31];
10419 
10420     union
10421     {
10422         __IOM uint32_t WUPEN;               /*!< (@ 0x000061A0) Wake Up Interrupt Enable Register                          */
10423 
10424         struct
10425         {
10426             __IOM uint32_t IRQWUPEN0 : 1;   /*!< [0..0] IRQ0 Interrupt Deep Sleep/Software Standby Returns Enable
10427                                              *   bit                                                                       */
10428             __IOM uint32_t IRQWUPEN1 : 1;   /*!< [1..1] IRQ1 Interrupt Deep Sleep/Software Standby Returns Enable
10429                                              *   bit                                                                       */
10430             __IOM uint32_t IRQWUPEN2 : 1;   /*!< [2..2] IRQ2 Interrupt Deep Sleep/Software Standby Returns Enable
10431                                              *   bit                                                                       */
10432             __IOM uint32_t IRQWUPEN3 : 1;   /*!< [3..3] IRQ3 Interrupt Deep Sleep/Software Standby Returns Enable
10433                                              *   bit                                                                       */
10434             __IOM uint32_t IRQWUPEN4 : 1;   /*!< [4..4] IRQ4 Interrupt Deep Sleep/Software Standby Returns Enable
10435                                              *   bit                                                                       */
10436             __IOM uint32_t IRQWUPEN5 : 1;   /*!< [5..5] IRQ5 Interrupt Deep Sleep/Software Standby Returns Enable
10437                                              *   bit                                                                       */
10438             __IOM uint32_t IRQWUPEN6 : 1;   /*!< [6..6] IRQ6 Interrupt Deep Sleep/Software Standby Returns Enable
10439                                              *   bit                                                                       */
10440             __IOM uint32_t IRQWUPEN7 : 1;   /*!< [7..7] IRQ7 Interrupt Deep Sleep/Software Standby Returns Enable
10441                                              *   bit                                                                       */
10442             __IOM uint32_t IRQWUPEN8 : 1;   /*!< [8..8] IRQ8 Interrupt Deep Sleep/Software Standby Returns Enable
10443                                              *   bit                                                                       */
10444             __IOM uint32_t IRQWUPEN9 : 1;   /*!< [9..9] IRQ9 Interrupt Deep Sleep/Software Standby Returns Enable
10445                                              *   bit                                                                       */
10446             __IOM uint32_t IRQWUPEN10 : 1;  /*!< [10..10] IRQ10 Interrupt Deep Sleep/Software Standby Returns
10447                                              *   Enable bit                                                                */
10448             __IOM uint32_t IRQWUPEN11 : 1;  /*!< [11..11] IRQ11 Interrupt Deep Sleep/Software Standby Returns
10449                                              *   Enable bit                                                                */
10450             __IOM uint32_t IRQWUPEN12 : 1;  /*!< [12..12] IRQ12 Interrupt Deep Sleep/Software Standby Returns
10451                                              *   Enable bit                                                                */
10452             __IOM uint32_t IRQWUPEN13 : 1;  /*!< [13..13] IRQ13 Interrupt Deep Sleep/Software Standby Returns
10453                                              *   Enable bit                                                                */
10454             __IOM uint32_t IRQWUPEN14 : 1;  /*!< [14..14] IRQ14 Interrupt Deep Sleep/Software Standby Returns
10455                                              *   Enable bit                                                                */
10456             __IOM uint32_t IRQWUPEN15 : 1;  /*!< [15..15] IRQ15 Interrupt Deep Sleep/Software Standby Returns
10457                                              *   Enable bit                                                                */
10458             __IOM uint32_t IWDTWUPEN : 1;   /*!< [16..16] IWDT Interrupt Deep Sleep/Software Standby Returns
10459                                              *   Enable bit                                                                */
10460             uint32_t                 : 1;
10461             __IOM uint32_t LVD1WUPEN : 1;   /*!< [18..18] PVD1 Interrupt Deep Sleep/Software Standby Returns
10462                                              *   Enable bit                                                                */
10463             __IOM uint32_t LVD2WUPEN : 1;   /*!< [19..19] PVD2 Interrupt Deep Sleep/Software Standby Returns
10464                                              *   Enable bit                                                                */
10465             __IOM uint32_t VBATTWUPEN : 1;  /*!< [20..20] VBATT Monitor Interrupt Deep Sleep/Software Standby
10466                                              *   Returns Enable bit                                                        */
10467             uint32_t                   : 3;
10468             __IOM uint32_t RTCALMWUPEN : 1; /*!< [24..24] RTC Alarm Interrupt Deep Sleep/Software Standby Returns
10469                                              *   Enable bit                                                                */
10470             __IOM uint32_t RTCPRDWUPEN : 1; /*!< [25..25] RCT Period Interrupt Deep Sleep/Software Standby Returns
10471                                              *   Enable bit                                                                */
10472             __IOM uint32_t USBHSWUPEN : 1;  /*!< [26..26] USBHS Interrupt Deep Sleep/Software Standby Returns
10473                                              *   Enable bit                                                                */
10474             __IOM uint32_t USBFSWUPEN : 1;  /*!< [27..27] USBFS0 Interrupt Deep Sleep/Software Standby Returns
10475                                              *   Enable bit                                                                */
10476             __IOM uint32_t AGT1UDWUPEN : 1; /*!< [28..28] AGT1 Underflow Interrupt Deep Sleep/Software Standby
10477                                              *   Returns Enable bit                                                        */
10478             __IOM uint32_t AGT1CAWUPEN : 1; /*!< [29..29] AGT1 Compare Match A Interrupt Deep Sleep/Software
10479                                              *   Standby Returns Enable bit                                                */
10480             __IOM uint32_t AGT1CBWUPEN : 1; /*!< [30..30] AGT1 Compare Match B Interrupt Deep Sleep/Software
10481                                              *   Standby Returns Enable bit                                                */
10482             __IOM uint32_t RIIC0WUPEN : 1;  /*!< [31..31] RIIC0 Address Match Interrupt Deep Sleep/Software Standby
10483                                              *   Returns Enable bit                                                        */
10484         } WUPEN_b;
10485     };
10486 
10487     union
10488     {
10489         __IOM uint32_t WUPEN1;         /*!< (@ 0x000061A4) Wake Up Interrupt Enable Register 1                        */
10490 
10491         struct
10492         {
10493             uint32_t                    : 3;
10494             __IOM uint32_t COMPHS0WUPEN : 1; /*!< [3..3] Comparator-HS0 Interrupt Deep Sleep/Software Standby
10495                                               *   Returns Enable bit                                                        */
10496             uint32_t                  : 4;
10497             __IOM uint32_t ULP0UWUPEN : 1;   /*!< [8..8] ULPT0 Underflow Interrupt Deep Sleep/Software Standby
10498                                               *   Returns Enable bit                                                        */
10499             __IOM uint32_t ULP0AWUPEN : 1;   /*!< [9..9] ULPT0 Compare Match A Interrupt Deep Sleep/Software Standby
10500                                               *   Returns Enable bit                                                        */
10501             __IOM uint32_t ULP0BWUPEN : 1;   /*!< [10..10] ULPT0 Compare Match B Interrupt Deep Sleep/Software
10502                                               *   Standby Returns Enable bit                                                */
10503             __IOM uint32_t I3CWUPEN : 1;     /*!< [11..11] I3C Wakeup Condition Detection Interrupt Deep Sleep/Software
10504                                               *   Standby Returns Enable bit                                                */
10505             __IOM uint32_t ULP1UWUPEN : 1;   /*!< [12..12] ULPT1 Underflow Interrupt Deep Sleep/Software Standby
10506                                               *   Returns Enable bit                                                        */
10507             __IOM uint32_t ULP1AWUPEN : 1;   /*!< [13..13] ULPT1 Compare Match A Interrupt Deep Sleep/Software
10508                                               *   Standby Returns Enable bit                                                */
10509             __IOM uint32_t ULP1BWUPEN : 1;   /*!< [14..14] ULPT1 Compare Match B Interrupt Deep Sleep/Software
10510                                               *   Standby Returns Enable bit                                                */
10511             uint32_t : 17;
10512         } WUPEN1_b;
10513     };
10514     __IM uint32_t RESERVED17[86];
10515 
10516     union
10517     {
10518         __IOM uint32_t IELSR[96];      /*!< (@ 0x00006300) ICU Event Link Setting Register [0..95]                    */
10519 
10520         struct
10521         {
10522             __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
10523                                         *   signal to be linked .                                                     */
10524             uint32_t            : 7;
10525             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
10526             uint32_t            : 7;
10527             __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
10528             uint32_t            : 7;
10529         } IELSR_b[96];
10530     };
10531 } R_ICU_Type;                          /*!< Size = 25728 (0x6480)                                                     */
10532 
10533 /* =========================================================================================================================== */
10534 /* ================                                          R_IIC0                                           ================ */
10535 /* =========================================================================================================================== */
10536 
10537 /**
10538  * @brief I2C Bus Interface (R_IIC0)
10539  */
10540 
10541 typedef struct                         /*!< (@ 0x4025E000) R_IIC0 Structure                                           */
10542 {
10543     union
10544     {
10545         __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
10546 
10547         struct
10548         {
10549             __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
10550             __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
10551             __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
10552             __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
10553             __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
10554             __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
10555             __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
10556                                         *   is initiated using the IICRST bit for a bus hang-up occurred
10557                                         *   during communication with the master device in slave mode,
10558                                         *   the states may become different between the slave device
10559                                         *   and the master device (due to the difference in the bit
10560                                         *   counter information).                                                     */
10561             __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
10562         } ICCR1_b;
10563     };
10564 
10565     union
10566     {
10567         __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
10568 
10569         struct
10570         {
10571             uint8_t          : 1;
10572             __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
10573                                         *   condition issuance request) when the BBSY flag is set to
10574                                         *   0 (bus free state).                                                       */
10575             __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
10576                                         *   RS bit to 1 while issuing a stop condition.                               */
10577             __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
10578                                         *   bit is not possible while the setting of the BBSY flag
10579                                         *   is 0 (bus free state).Note: Do not set the SP bit to 1
10580                                         *   while a restart condition is being issued.                                */
10581             uint8_t            : 1;
10582             __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
10583             __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
10584             __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
10585         } ICCR2_b;
10586     };
10587 
10588     union
10589     {
10590         __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
10591 
10592         struct
10593         {
10594             __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
10595             __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
10596             __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
10597                                         *   / 2^CKS )                                                                 */
10598             __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
10599         } ICMR1_b;
10600     };
10601 
10602     union
10603     {
10604         __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
10605 
10606         struct
10607         {
10608             __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
10609             __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
10610             __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
10611             uint8_t            : 1;
10612             __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
10613             __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
10614         } ICMR2_b;
10615     };
10616 
10617     union
10618     {
10619         __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
10620 
10621         struct
10622         {
10623             __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
10624             __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
10625             __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
10626             __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
10627             __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
10628             __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
10629                                         *   be sure to read the ICDRR beforehand.                                     */
10630             __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
10631         } ICMR3_b;
10632     };
10633 
10634     union
10635     {
10636         __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
10637 
10638         struct
10639         {
10640             __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
10641             __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
10642             __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
10643             __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
10644             __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
10645             __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
10646             __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
10647             __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
10648         } ICFER_b;
10649     };
10650 
10651     union
10652     {
10653         __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
10654 
10655         struct
10656         {
10657             __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
10658             __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
10659             __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
10660             __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
10661             uint8_t             : 1;
10662             __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
10663             uint8_t             : 1;
10664             __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
10665         } ICSER_b;
10666     };
10667 
10668     union
10669     {
10670         __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
10671 
10672         struct
10673         {
10674             __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
10675             __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
10676             __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
10677             __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
10678             __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
10679             __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
10680             __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
10681             __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
10682         } ICIER_b;
10683     };
10684 
10685     union
10686     {
10687         __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
10688 
10689         struct
10690         {
10691             __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
10692             __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
10693             __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
10694             __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
10695             uint8_t            : 1;
10696             __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
10697             uint8_t            : 1;
10698             __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
10699         } ICSR1_b;
10700     };
10701 
10702     union
10703     {
10704         __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
10705 
10706         struct
10707         {
10708             __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
10709             __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
10710             __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
10711             __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
10712             __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
10713             __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
10714             __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
10715             __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
10716         } ICSR2_b;
10717     };
10718     __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
10719 
10720     union
10721     {
10722         __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
10723 
10724         struct
10725         {
10726             __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
10727             uint8_t           : 3;
10728         } ICBRL_b;
10729     };
10730 
10731     union
10732     {
10733         __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
10734 
10735         struct
10736         {
10737             __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
10738             uint8_t           : 3;
10739         } ICBRH_b;
10740     };
10741 
10742     union
10743     {
10744         __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
10745 
10746         struct
10747         {
10748             __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
10749         } ICDRT_b;
10750     };
10751 
10752     union
10753     {
10754         __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
10755 
10756         struct
10757         {
10758             __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
10759         } ICDRR_b;
10760     };
10761     __IM uint8_t RESERVED[2];
10762 
10763     union
10764     {
10765         __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
10766 
10767         struct
10768         {
10769             __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
10770             uint8_t             : 3;
10771             __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
10772             __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
10773             __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
10774             __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
10775         } ICWUR_b;
10776     };
10777 
10778     union
10779     {
10780         __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
10781 
10782         struct
10783         {
10784             __IOM uint8_t WUSEN  : 1;  /*!< [0..0] Wake-up Function Synchronous Enable                                */
10785             __IM uint8_t  WUASYF : 1;  /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
10786             __IM uint8_t  WUSYF  : 1;  /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
10787             uint8_t              : 5;
10788         } ICWUR2_b;
10789     };
10790 } R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
10791 
10792 /* =========================================================================================================================== */
10793 /* ================                                          R_IWDT                                           ================ */
10794 /* =========================================================================================================================== */
10795 
10796 /**
10797  * @brief Independent Watchdog Timer (R_IWDT)
10798  */
10799 
10800 typedef struct                         /*!< (@ 0x40202200) R_IWDT Structure                                           */
10801 {
10802     union
10803     {
10804         __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
10805 
10806         struct
10807         {
10808             __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
10809                                         *   0xFF to this register.                                                    */
10810         } IWDTRR_b;
10811     };
10812     __IM uint8_t RESERVED;
10813 
10814     union
10815     {
10816         __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */
10817 
10818         struct
10819         {
10820             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
10821             uint16_t            : 2;
10822             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
10823             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
10824             uint16_t            : 2;
10825             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
10826             uint16_t            : 2;
10827         } IWDTCR_b;
10828     };
10829 
10830     union
10831     {
10832         __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
10833 
10834         struct
10835         {
10836             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
10837             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
10838             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
10839         } IWDTSR_b;
10840     };
10841 
10842     union
10843     {
10844         __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */
10845 
10846         struct
10847         {
10848             uint8_t               : 7;
10849             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
10850         } IWDTRCR_b;
10851     };
10852     __IM uint8_t RESERVED1;
10853 
10854     union
10855     {
10856         __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */
10857 
10858         struct
10859         {
10860             uint8_t              : 7;
10861             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
10862         } IWDTCSTPR_b;
10863     };
10864     __IM uint8_t  RESERVED2;
10865     __IM uint16_t RESERVED3;
10866 } R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */
10867 
10868 /* =========================================================================================================================== */
10869 /* ================                                          R_I3C0                                           ================ */
10870 /* =========================================================================================================================== */
10871 
10872 /**
10873  * @brief I3C Bus Interface (R_I3C0)
10874  */
10875 
10876 typedef struct                         /*!< (@ 0x4035F000) R_I3C0 Structure                                           */
10877 {
10878     union
10879     {
10880         __IOM uint32_t PRTS;           /*!< (@ 0x00000000) Protocol Selection Register                                */
10881 
10882         struct
10883         {
10884             __IOM uint32_t PRTMD : 1;  /*!< [0..0] Protocol Mode                                                      */
10885             uint32_t             : 31;
10886         } PRTS_b;
10887     };
10888     __IM uint32_t RESERVED[3];
10889 
10890     union
10891     {
10892         __IOM uint32_t CECTL;          /*!< (@ 0x00000010) Clock Enable Control Resisters                             */
10893 
10894         struct
10895         {
10896             __IOM uint32_t CLKE : 1;   /*!< [0..0] Clock Enable                                                       */
10897             uint32_t            : 31;
10898         } CECTL_b;
10899     };
10900 
10901     union
10902     {
10903         __IOM uint32_t BCTL;             /*!< (@ 0x00000014) Bus Control Register                                       */
10904 
10905         struct
10906         {
10907             __IOM uint32_t INCBA    : 1; /*!< [0..0] Include I3C Broadcast Address                                      */
10908             uint32_t                : 6;
10909             __IOM uint32_t BMDS     : 1; /*!< [7..7] Bus Mode Selection                                                 */
10910             __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control                                       */
10911             uint32_t                : 20;
10912             __IOM uint32_t ABT      : 1; /*!< [29..29] Abort                                                            */
10913             __IOM uint32_t RSM      : 1; /*!< [30..30] Resume                                                           */
10914             __IOM uint32_t BUSE     : 1; /*!< [31..31] Bus Enable                                                       */
10915         } BCTL_b;
10916     };
10917 
10918     union
10919     {
10920         __IOM uint32_t MSDVAD;         /*!< (@ 0x00000018) Master Device Address Register                             */
10921 
10922         struct
10923         {
10924             uint32_t              : 16;
10925             __IOM uint32_t MDYAD  : 7; /*!< [22..16] Master Dynamic Address                                           */
10926             uint32_t              : 8;
10927             __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid                                     */
10928         } MSDVAD_b;
10929     };
10930     __IM uint32_t RESERVED1;
10931 
10932     union
10933     {
10934         __IOM uint32_t RSTCTL;          /*!< (@ 0x00000020) Reset Control Register                                     */
10935 
10936         struct
10937         {
10938             __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset                                                 */
10939             __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset                                       */
10940             __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset                                      */
10941             __IOM uint32_t TDBRST  : 1; /*!< [3..3] Transmit Data Buffer Software Reset                                */
10942             __IOM uint32_t RDBRST  : 1; /*!< [4..4] Receive Data Buffer Software Reset                                 */
10943             __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset                                           */
10944             __IOM uint32_t RSQRST  : 1; /*!< [6..6] Receive Status Queue Software Reset                                */
10945             uint32_t               : 9;
10946             __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset                                          */
10947             uint32_t               : 15;
10948         } RSTCTL_b;
10949     };
10950 
10951     union
10952     {
10953         __IOM uint32_t PRSST;          /*!< (@ 0x00000024) Present State Register                                     */
10954 
10955         struct
10956         {
10957             uint32_t              : 2;
10958             __IOM uint32_t CRMS   : 1; /*!< [2..2] Current Master                                                     */
10959             uint32_t              : 1;
10960             __IM uint32_t TRMD    : 1; /*!< [4..4] Transmit/Receive Mode                                              */
10961             uint32_t              : 2;
10962             __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect                                        */
10963             uint32_t              : 24;
10964         } PRSST_b;
10965     };
10966     __IM uint32_t RESERVED2[2];
10967 
10968     union
10969     {
10970         __IOM uint32_t INST;           /*!< (@ 0x00000030) Internal Status Register                                   */
10971 
10972         struct
10973         {
10974             uint32_t            : 10;
10975             __IOM uint32_t INEF : 1;   /*!< [10..10] Internal Error Flag                                              */
10976             uint32_t            : 21;
10977         } INST_b;
10978     };
10979 
10980     union
10981     {
10982         __IOM uint32_t INSTE;          /*!< (@ 0x00000034) Internal Status Enable Register                            */
10983 
10984         struct
10985         {
10986             uint32_t            : 10;
10987             __IOM uint32_t INEE : 1;   /*!< [10..10] Internal Error Enable                                            */
10988             uint32_t            : 21;
10989         } INSTE_b;
10990     };
10991 
10992     union
10993     {
10994         __IOM uint32_t INIE;           /*!< (@ 0x00000038) Internal Interrupt Enable Register                         */
10995 
10996         struct
10997         {
10998             uint32_t             : 10;
10999             __IOM uint32_t INEIE : 1;  /*!< [10..10] Internal Error Interrupt Enable                                  */
11000             uint32_t             : 21;
11001         } INIE_b;
11002     };
11003 
11004     union
11005     {
11006         __IOM uint32_t INSTFC;         /*!< (@ 0x0000003C) Internal Status Force Register                             */
11007 
11008         struct
11009         {
11010             uint32_t            : 10;
11011             __OM uint32_t INEFC : 1;   /*!< [10..10] Internal Error Force                                             */
11012             uint32_t            : 21;
11013         } INSTFC_b;
11014     };
11015     __IM uint32_t RESERVED3;
11016 
11017     union
11018     {
11019         __IM uint32_t DVCT;            /*!< (@ 0x00000044) Device Characteristic Table Register                       */
11020 
11021         struct
11022         {
11023             uint32_t          : 19;
11024             __IM uint32_t IDX : 5;     /*!< [23..19] DCT Table Index                                                  */
11025             uint32_t          : 8;
11026         } DVCT_b;
11027     };
11028     __IM uint32_t RESERVED4[4];
11029 
11030     union
11031     {
11032         __IOM uint32_t IBINCTL;          /*!< (@ 0x00000058) IBI Notify Control Register                                */
11033 
11034         struct
11035         {
11036             __IOM uint32_t NRHJCTL  : 1; /*!< [0..0] Notify Rejected Hot-Join Control                                   */
11037             __IOM uint32_t NRMRCTL  : 1; /*!< [1..1] Notify Rejected Master Request Control                             */
11038             uint32_t                : 1;
11039             __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control                    */
11040             uint32_t                : 28;
11041         } IBINCTL_b;
11042     };
11043     __IM uint32_t RESERVED5;
11044 
11045     union
11046     {
11047         __IOM uint32_t BFCTL;          /*!< (@ 0x00000060) Bus Function Control Register                              */
11048 
11049         struct
11050         {
11051             __IOM uint32_t MALE   : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable                           */
11052             __IOM uint32_t NALE   : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable                */
11053             __IOM uint32_t SALE   : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable                            */
11054             uint32_t              : 5;
11055             __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable                                     */
11056             uint32_t              : 3;
11057             __IOM uint32_t SMBS   : 1; /*!< [12..12] SMBus/I2C Bus Selection                                          */
11058             uint32_t              : 1;
11059             __IOM uint32_t FMPE   : 1; /*!< [14..14] Fast-mode Plus Enable                                            */
11060             __IOM uint32_t HSME   : 1; /*!< [15..15] High Speed Mode Enable                                           */
11061             uint32_t              : 16;
11062         } BFCTL_b;
11063     };
11064 
11065     union
11066     {
11067         __IOM uint32_t SVCTL;          /*!< (@ 0x00000064) Slave Control Register                                     */
11068 
11069         struct
11070         {
11071             __IOM uint32_t GCAE  : 1;  /*!< [0..0] General Call Address Enable                                        */
11072             uint32_t             : 4;
11073             __IOM uint32_t HSMCE : 1;  /*!< [5..5] Hs-mode Master Code Enable                                         */
11074             __IOM uint32_t DVIDE : 1;  /*!< [6..6] Device-ID Address Enable                                           */
11075             uint32_t             : 8;
11076             __IOM uint32_t HOAE  : 1;  /*!< [15..15] Host Address Enable                                              */
11077             __IOM uint32_t SVAEn : 1;  /*!< [16..16] Slave Address Enable n (n = 0)                                   */
11078             uint32_t             : 15;
11079         } SVCTL_b;
11080     };
11081     __IM uint32_t RESERVED6[2];
11082 
11083     union
11084     {
11085         __IOM uint32_t REFCKCTL;        /*!< (@ 0x00000070) Reference Clock Control Register                           */
11086 
11087         struct
11088         {
11089             __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection                                 */
11090             uint32_t               : 29;
11091         } REFCKCTL_b;
11092     };
11093 
11094     union
11095     {
11096         __IOM uint32_t STDBR;          /*!< (@ 0x00000074) Standard Bit Rate Register                                 */
11097 
11098         struct
11099         {
11100             __IOM uint32_t SBRLO  : 8; /*!< [7..0] Count value of the Low-level period of SCL clock                   */
11101             __IOM uint32_t SBRHO  : 8; /*!< [15..8] Count value of the High-level period of SCL clock                 */
11102             __IOM uint32_t SBRLP  : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull                     */
11103             uint32_t              : 2;
11104             __IOM uint32_t SBRHP  : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull                    */
11105             uint32_t              : 1;
11106             __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain               */
11107         } STDBR_b;
11108     };
11109 
11110     union
11111     {
11112         __IOM uint32_t EXTBR;          /*!< (@ 0x00000078) Extended Bit Rate Register                                 */
11113 
11114         struct
11115         {
11116             __IOM uint32_t EBRLO : 8;  /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain                      */
11117             __IOM uint32_t EBRHO : 8;  /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain                    */
11118             __IOM uint32_t EBRLP : 6;  /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull                     */
11119             uint32_t             : 2;
11120             __IOM uint32_t EBRHP : 6;  /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull                     */
11121             uint32_t             : 2;
11122         } EXTBR_b;
11123     };
11124 
11125     union
11126     {
11127         __IOM uint32_t BFRECDT;        /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register                 */
11128 
11129         struct
11130         {
11131             __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle                                 */
11132             uint32_t              : 23;
11133         } BFRECDT_b;
11134     };
11135 
11136     union
11137     {
11138         __IOM uint32_t BAVLCDT;        /*!< (@ 0x00000080) Bus Available Condition Detection Time Register            */
11139 
11140         struct
11141         {
11142             __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle                            */
11143             uint32_t              : 23;
11144         } BAVLCDT_b;
11145     };
11146 
11147     union
11148     {
11149         __IOM uint32_t BIDLCDT;         /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register                 */
11150 
11151         struct
11152         {
11153             __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle                                */
11154             uint32_t              : 14;
11155         } BIDLCDT_b;
11156     };
11157 
11158     union
11159     {
11160         __IOM uint32_t OUTCTL;         /*!< (@ 0x00000088) Output Control Register                                    */
11161 
11162         struct
11163         {
11164             __IOM uint32_t SDOC   : 1; /*!< [0..0] SDA Output Control                                                 */
11165             __IOM uint32_t SCOC   : 1; /*!< [1..1] SCL Output Control                                                 */
11166             __OM uint32_t  SOCWP  : 1; /*!< [2..2] SCL/SDA Output Control Write Protect                               */
11167             uint32_t              : 1;
11168             __IOM uint32_t EXCYC  : 1; /*!< [4..4] Extra SCL Clock Cycle Output                                       */
11169             uint32_t              : 3;
11170             __IOM uint32_t SDOD   : 3; /*!< [10..8] SDA Output Delay                                                  */
11171             uint32_t              : 4;
11172             __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection                          */
11173             uint32_t              : 16;
11174         } OUTCTL_b;
11175     };
11176 
11177     union
11178     {
11179         __IOM uint32_t INCTL;          /*!< (@ 0x0000008C) Input Control Register                                     */
11180 
11181         struct
11182         {
11183             __IOM uint32_t DNFS : 4;   /*!< [3..0] Digital Noise Filter Stage Selection                               */
11184             __IOM uint32_t DNFE : 1;   /*!< [4..4] Digital Noise Filter Circuit Enable                                */
11185             uint32_t            : 27;
11186         } INCTL_b;
11187     };
11188 
11189     union
11190     {
11191         __IOM uint32_t TMOCTL;         /*!< (@ 0x00000090) Timeout Control Register                                   */
11192 
11193         struct
11194         {
11195             __IOM uint32_t TODTS  : 2; /*!< [1..0] Timeout Detection Time Selection                                   */
11196             uint32_t              : 2;
11197             __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control                                            */
11198             __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control                                            */
11199             __IOM uint32_t TOMDS  : 2; /*!< [7..6] Timeout Operation Mode Selection                                   */
11200             uint32_t              : 24;
11201         } TMOCTL_b;
11202     };
11203     __IM uint32_t RESERVED7;
11204 
11205     union
11206     {
11207         __IOM uint32_t WUCTL;           /*!< (@ 0x00000098) Wake Up Unit Control Register                              */
11208 
11209         struct
11210         {
11211             __IOM uint32_t WUACKS  : 1; /*!< [0..0] Wake-Up Acknowledge Selection                                      */
11212             uint32_t               : 3;
11213             __IOM uint32_t WUANFS  : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection                              */
11214             uint32_t               : 1;
11215             __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable                          */
11216             __IOM uint32_t WUFE    : 1; /*!< [7..7] Wake-Up function Enable.                                           */
11217             uint32_t               : 24;
11218         } WUCTL_b;
11219     };
11220     __IM uint32_t RESERVED8;
11221 
11222     union
11223     {
11224         __IOM uint32_t ACKCTL;         /*!< (@ 0x000000A0) Acknowledge Control Register                               */
11225 
11226         struct
11227         {
11228             __IM uint32_t  ACKR   : 1; /*!< [0..0] Acknowledge Reception                                              */
11229             __IOM uint32_t ACKT   : 1; /*!< [1..1] Acknowledge Transmission                                           */
11230             __OM uint32_t  ACKTWP : 1; /*!< [2..2] ACKT Write Protect                                                 */
11231             uint32_t              : 29;
11232         } ACKCTL_b;
11233     };
11234 
11235     union
11236     {
11237         __IOM uint32_t SCSTRCTL;       /*!< (@ 0x000000A4) SCL Stretch Control Register                               */
11238 
11239         struct
11240         {
11241             __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable                               */
11242             __IOM uint32_t RWE    : 1; /*!< [1..1] Receive Wait Enable                                                */
11243             uint32_t              : 30;
11244         } SCSTRCTL_b;
11245     };
11246     __IM uint32_t RESERVED9[2];
11247 
11248     union
11249     {
11250         __IOM uint32_t SCSTLCTL;        /*!< (@ 0x000000B0) SCL Stalling Control Register                              */
11251 
11252         struct
11253         {
11254             __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle                                                    */
11255             uint32_t              : 12;
11256             __IOM uint32_t AAPE   : 1;  /*!< [28..28] Assigend Address Phase Enable                                    */
11257             __IOM uint32_t TRAPE  : 1;  /*!< [29..29] Transition Phase Enable                                          */
11258             __IOM uint32_t PARPE  : 1;  /*!< [30..30] Parity Phase Enable                                              */
11259             __IOM uint32_t ACKPE  : 1;  /*!< [31..31] ACK phase Enable                                                 */
11260         } SCSTLCTL_b;
11261     };
11262     __IM uint32_t RESERVED10[3];
11263 
11264     union
11265     {
11266         __IOM uint32_t SVTDLG0;        /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0                      */
11267 
11268         struct
11269         {
11270             uint32_t             : 16;
11271             __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length                                       */
11272         } SVTDLG0_b;
11273     };
11274     __IM uint32_t RESERVED11[31];
11275 
11276     union
11277     {
11278         __IOM uint32_t CNDCTL;         /*!< (@ 0x00000140) Condition Control Register                                 */
11279 
11280         struct
11281         {
11282             __IOM uint32_t STCND : 1;  /*!< [0..0] START (S) Condition Issuance                                       */
11283             __IOM uint32_t SRCND : 1;  /*!< [1..1] Repeated START (Sr) Condition Issuance                             */
11284             __IOM uint32_t SPCND : 1;  /*!< [2..2] STOP (P) Condition Issuance                                        */
11285             uint32_t             : 29;
11286         } CNDCTL_b;
11287     };
11288     __IM uint32_t  RESERVED12[3];
11289     __OM uint32_t  NCMDQP;             /*!< (@ 0x00000150) Normal Command Queue Port Register                         */
11290     __IM uint32_t  NRSPQP;             /*!< (@ 0x00000154) Normal Response Queue Port Register                        */
11291     __IOM uint32_t NTDTBP0;            /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0                */
11292     __IM uint32_t  RESERVED13[8];
11293     __IOM uint32_t NIBIQP;             /*!< (@ 0x0000017C) Normal IBI Queue Port Register                             */
11294     __IM uint32_t  NRSQP;              /*!< (@ 0x00000180) Normal Receive Status Queue Port Register                  */
11295     __IM uint32_t  RESERVED14[3];
11296 
11297     union
11298     {
11299         __IOM uint32_t NQTHCTL;         /*!< (@ 0x00000190) Normal Queue Threshold Control Register                    */
11300 
11301         struct
11302         {
11303             __IOM uint32_t CMDQTH  : 8; /*!< [7..0] Normal Command Ready Queue Threshold                               */
11304             __IOM uint32_t RSPQTH  : 8; /*!< [15..8] Normal Response Queue Threshold                                   */
11305             __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size                                     */
11306             __IOM uint32_t IBIQTH  : 8; /*!< [31..24] Normal IBI Queue Threshold                                       */
11307         } NQTHCTL_b;
11308     };
11309 
11310     union
11311     {
11312         __IOM uint32_t NTBTHCTL0;      /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
11313                                         *                  Register 0                                                 */
11314 
11315         struct
11316         {
11317             __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold                              */
11318             uint32_t              : 5;
11319             __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold                              */
11320             uint32_t              : 5;
11321             __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold                                        */
11322             uint32_t              : 5;
11323             __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold                                        */
11324             uint32_t              : 5;
11325         } NTBTHCTL0_b;
11326     };
11327     __IM uint32_t RESERVED15[10];
11328 
11329     union
11330     {
11331         __IOM uint32_t NRQTHCTL;       /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
11332                                         *                  Register                                                   */
11333 
11334         struct
11335         {
11336             __IOM uint32_t RSQTH : 8;  /*!< [7..0] Normal Receive Status Queue Threshold                              */
11337             uint32_t             : 24;
11338         } NRQTHCTL_b;
11339     };
11340     __IM uint32_t RESERVED16[3];
11341 
11342     union
11343     {
11344         __IOM uint32_t BST;             /*!< (@ 0x000001D0) Bus Status Register                                        */
11345 
11346         struct
11347         {
11348             __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag                                     */
11349             __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag                                      */
11350             __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag                                    */
11351             uint32_t               : 1;
11352             __IOM uint32_t NACKDF  : 1; /*!< [4..4] NACK Detection Flag                                                */
11353             uint32_t               : 3;
11354             __IOM uint32_t TENDF   : 1; /*!< [8..8] Transmit End Flag                                                  */
11355             uint32_t               : 7;
11356             __IOM uint32_t ALF     : 1; /*!< [16..16] Arbitration Lost Flag                                            */
11357             uint32_t               : 3;
11358             __IOM uint32_t TODF    : 1; /*!< [20..20] Timeout Detection Flag                                           */
11359             uint32_t               : 11;
11360         } BST_b;
11361     };
11362 
11363     union
11364     {
11365         __IOM uint32_t BSTE;            /*!< (@ 0x000001D4) Bus Status Enable Register                                 */
11366 
11367         struct
11368         {
11369             __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable                                   */
11370             __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable                                    */
11371             __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable                                  */
11372             uint32_t               : 1;
11373             __IOM uint32_t NACKDE  : 1; /*!< [4..4] NACK Detection Enable                                              */
11374             uint32_t               : 3;
11375             __IOM uint32_t TENDE   : 1; /*!< [8..8] Transmit End Enable                                                */
11376             uint32_t               : 7;
11377             __IOM uint32_t ALE     : 1; /*!< [16..16] Arbitration Lost Enable                                          */
11378             uint32_t               : 3;
11379             __IOM uint32_t TODE    : 1; /*!< [20..20] Timeout Detection Enable                                         */
11380             uint32_t               : 11;
11381         } BSTE_b;
11382     };
11383 
11384     union
11385     {
11386         __IOM uint32_t BIE;              /*!< (@ 0x000001D8) Bus Interrupt Enable Register                              */
11387 
11388         struct
11389         {
11390             __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable                         */
11391             __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable                          */
11392             __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable                        */
11393             uint32_t                : 1;
11394             __IOM uint32_t NACKDIE  : 1; /*!< [4..4] NACK Detection Interrupt Enable                                    */
11395             uint32_t                : 3;
11396             __IOM uint32_t TENDIE   : 1; /*!< [8..8] Transmit End Interrupt Enable                                      */
11397             uint32_t                : 7;
11398             __IOM uint32_t ALIE     : 1; /*!< [16..16] Arbitration Lost Interrupt Enable                                */
11399             uint32_t                : 3;
11400             __IOM uint32_t TODIE    : 1; /*!< [20..20] Timeout Detection Interrupt Enable                               */
11401             uint32_t                : 11;
11402         } BIE_b;
11403     };
11404 
11405     union
11406     {
11407         __IOM uint32_t BSTFC;           /*!< (@ 0x000001DC) Bus Status Force Register                                  */
11408 
11409         struct
11410         {
11411             __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force                                    */
11412             __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force                                     */
11413             __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force                                   */
11414             uint32_t               : 1;
11415             __OM uint32_t NACKDFC  : 1; /*!< [4..4] NACK Detection Force                                               */
11416             uint32_t               : 3;
11417             __OM uint32_t TENDFC   : 1; /*!< [8..8] Transmit End Force                                                 */
11418             uint32_t               : 7;
11419             __OM uint32_t ALFC     : 1; /*!< [16..16] Arbitration Lost Force                                           */
11420             uint32_t               : 3;
11421             __OM uint32_t TODFC    : 1; /*!< [20..20] Timeout Detection Force                                          */
11422             uint32_t               : 11;
11423         } BSTFC_b;
11424     };
11425 
11426     union
11427     {
11428         __IOM uint32_t NTST;            /*!< (@ 0x000001E0) Normal Transfer Status Register                            */
11429 
11430         struct
11431         {
11432             __IOM uint32_t TDBEF0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0                           */
11433             __IOM uint32_t RDBFF0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0                             */
11434             __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag                                   */
11435             __IOM uint32_t CMDQEF  : 1; /*!< [3..3] Normal Command Queue Empty Flag                                    */
11436             __IOM uint32_t RSPQFF  : 1; /*!< [4..4] Normal Response Queue Full Flag                                    */
11437             __IOM uint32_t TABTF   : 1; /*!< [5..5] Normal Transfer Abort Flag                                         */
11438             uint32_t               : 3;
11439             __IOM uint32_t TEF     : 1; /*!< [9..9] Normal Transfer Error Flag                                         */
11440             uint32_t               : 10;
11441             __IOM uint32_t RSQFF   : 1; /*!< [20..20] Normal Receive Status Queue Full Flag                            */
11442             uint32_t               : 11;
11443         } NTST_b;
11444     };
11445 
11446     union
11447     {
11448         __IOM uint32_t NTSTE;           /*!< (@ 0x000001E4) Normal Transfer Status Enable Register                     */
11449 
11450         struct
11451         {
11452             __IOM uint32_t TDBEE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0                         */
11453             __IOM uint32_t RDBFE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0                           */
11454             __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable                                 */
11455             __IOM uint32_t CMDQEE  : 1; /*!< [3..3] Normal Command Queue Empty Enable                                  */
11456             __IOM uint32_t RSPQFE  : 1; /*!< [4..4] Normal Response Queue Full Enable                                  */
11457             __IOM uint32_t TABTE   : 1; /*!< [5..5] Normal Transfer Abort Enable                                       */
11458             uint32_t               : 3;
11459             __IOM uint32_t TEE     : 1; /*!< [9..9] Normal Transfer Error Enable                                       */
11460             uint32_t               : 10;
11461             __IOM uint32_t RSQFE   : 1; /*!< [20..20] Normal Receive Status Queue Full Enable                          */
11462             uint32_t               : 11;
11463         } NTSTE_b;
11464     };
11465 
11466     union
11467     {
11468         __IOM uint32_t NTIE;             /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register                  */
11469 
11470         struct
11471         {
11472             __IOM uint32_t TDBEIE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0               */
11473             __IOM uint32_t RDBFIE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0                 */
11474             __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable                       */
11475             __IOM uint32_t CMDQEIE  : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable                        */
11476             __IOM uint32_t RSPQFIE  : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable                        */
11477             __IOM uint32_t TABTIE   : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable                             */
11478             uint32_t                : 3;
11479             __IOM uint32_t TEIE     : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable                             */
11480             uint32_t                : 10;
11481             __IOM uint32_t RSQFIE   : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable                */
11482             uint32_t                : 11;
11483         } NTIE_b;
11484     };
11485 
11486     union
11487     {
11488         __IOM uint32_t NTSTFC;          /*!< (@ 0x000001EC) Normal Transfer Status Force Register                      */
11489 
11490         struct
11491         {
11492             __OM uint32_t TDBEFC0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0                          */
11493             __OM uint32_t RDBFFC0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0                            */
11494             __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force                                  */
11495             __OM uint32_t CMDQEFC  : 1; /*!< [3..3] Normal Command Queue Empty Force                                   */
11496             __OM uint32_t RSPQFFC  : 1; /*!< [4..4] Normal Response Queue Full Force                                   */
11497             __OM uint32_t TABTFC   : 1; /*!< [5..5] Normal Transfer Abort Force                                        */
11498             uint32_t               : 3;
11499             __OM uint32_t TEFC     : 1; /*!< [9..9] Normal Transfer Error Force                                        */
11500             uint32_t               : 10;
11501             __OM uint32_t RSQFFC   : 1; /*!< [20..20] Normal Receive Status Queue Full Force                           */
11502             uint32_t               : 11;
11503         } NTSTFC_b;
11504     };
11505     __IM uint32_t RESERVED17[8];
11506 
11507     union
11508     {
11509         __IM uint32_t BCST;            /*!< (@ 0x00000210) Bus Condition Status Register                              */
11510 
11511         struct
11512         {
11513             __IM uint32_t BFREF : 1;   /*!< [0..0] Bus Free Detection Flag                                            */
11514             __IM uint32_t BAVLF : 1;   /*!< [1..1] Bus Available Detection Flag                                       */
11515             __IM uint32_t BIDLF : 1;   /*!< [2..2] Bus Idle Detection Flag                                            */
11516             uint32_t            : 29;
11517         } BCST_b;
11518     };
11519 
11520     union
11521     {
11522         __IOM uint32_t SVST;           /*!< (@ 0x00000214) Slave Status Register                                      */
11523 
11524         struct
11525         {
11526             __IOM uint32_t GCAF  : 1;  /*!< [0..0] General Call Address Detection Flag                                */
11527             uint32_t             : 4;
11528             __IOM uint32_t HSMCF : 1;  /*!< [5..5] Hs-mode Master Code Detection Flag                                 */
11529             __IOM uint32_t DVIDF : 1;  /*!< [6..6] Device-ID Address Detection Flag                                   */
11530             uint32_t             : 8;
11531             __IOM uint32_t HOAF  : 1;  /*!< [15..15] Host Address Detection Flag                                      */
11532             __IOM uint32_t SVAFn : 1;  /*!< [16..16] Slave Address Detection Flag n (n = 0)                           */
11533             uint32_t             : 15;
11534         } SVST_b;
11535     };
11536 
11537     union
11538     {
11539         __IOM uint32_t WUST;            /*!< (@ 0x00000218) Wake Up Unit Control Register                              */
11540 
11541         struct
11542         {
11543             __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag.               */
11544             uint32_t               : 31;
11545         } WUST_b;
11546     };
11547     __IM uint32_t RESERVED18[2];
11548 
11549     union
11550     {
11551         __IOM uint32_t DATBAS0;         /*!< (@ 0x00000224) Device Address Table Basic Register 0                      */
11552 
11553         struct
11554         {
11555             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
11556             uint32_t               : 5;
11557             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
11558             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
11559             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
11560             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
11561             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
11562             uint32_t               : 5;
11563             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
11564             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
11565         } DATBAS0_b;
11566     };
11567     __IM uint32_t RESERVED19;
11568 
11569     union
11570     {
11571         __IOM uint32_t DATBAS1;         /*!< (@ 0x0000022C) Device Address Table Basic Register 1                      */
11572 
11573         struct
11574         {
11575             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
11576             uint32_t               : 5;
11577             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
11578             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
11579             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
11580             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
11581             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
11582             uint32_t               : 5;
11583             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
11584             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
11585         } DATBAS1_b;
11586     };
11587     __IM uint32_t RESERVED20;
11588 
11589     union
11590     {
11591         __IOM uint32_t DATBAS2;         /*!< (@ 0x00000234) Device Address Table Basic Register 2                      */
11592 
11593         struct
11594         {
11595             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
11596             uint32_t               : 5;
11597             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
11598             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
11599             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
11600             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
11601             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
11602             uint32_t               : 5;
11603             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
11604             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
11605         } DATBAS2_b;
11606     };
11607     __IM uint32_t RESERVED21;
11608 
11609     union
11610     {
11611         __IOM uint32_t DATBAS3;         /*!< (@ 0x0000023C) Device Address Table Basic Register 3                      */
11612 
11613         struct
11614         {
11615             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
11616             uint32_t               : 5;
11617             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
11618             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
11619             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
11620             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
11621             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
11622             uint32_t               : 5;
11623             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
11624             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
11625         } DATBAS3_b;
11626     };
11627     __IM uint32_t RESERVED22[24];
11628 
11629     union
11630     {
11631         __IOM uint32_t EXDATBAS;       /*!< (@ 0x000002A0) Extended Device Address Table Basic Register               */
11632 
11633         struct
11634         {
11635             __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address                                     */
11636             uint32_t              : 9;
11637             __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address                              */
11638             uint32_t              : 5;
11639             __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count                                 */
11640             __IOM uint32_t EDTYP  : 1; /*!< [31..31] Extended Device Type                                             */
11641         } EXDATBAS_b;
11642     };
11643     __IM uint32_t RESERVED23[3];
11644 
11645     union
11646     {
11647         __IOM uint32_t SDATBAS0;         /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0                */
11648 
11649         struct
11650         {
11651             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
11652             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
11653             uint32_t               : 1;
11654             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
11655             uint32_t               : 3;
11656             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
11657             uint32_t               : 9;
11658         } SDATBAS0_b;
11659     };
11660 
11661     union
11662     {
11663         __IOM uint32_t SDATBAS1;         /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1                */
11664 
11665         struct
11666         {
11667             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
11668             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
11669             uint32_t               : 1;
11670             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
11671             uint32_t               : 3;
11672             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
11673             uint32_t               : 9;
11674         } SDATBAS1_b;
11675     };
11676 
11677     union
11678     {
11679         __IOM uint32_t SDATBAS2;         /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2                */
11680 
11681         struct
11682         {
11683             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
11684             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
11685             uint32_t               : 1;
11686             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
11687             uint32_t               : 3;
11688             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
11689             uint32_t               : 9;
11690         } SDATBAS2_b;
11691     };
11692     __IM uint32_t RESERVED24[5];
11693 
11694     union
11695     {
11696         __IOM uint32_t MSDCT0;         /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0              */
11697 
11698         struct
11699         {
11700             uint32_t              : 8;
11701             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
11702             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
11703             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
11704             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
11705             uint32_t              : 2;
11706             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
11707             uint32_t              : 16;
11708         } MSDCT0_b;
11709     };
11710 
11711     union
11712     {
11713         __IOM uint32_t MSDCT1;         /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1              */
11714 
11715         struct
11716         {
11717             uint32_t              : 8;
11718             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
11719             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
11720             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
11721             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
11722             uint32_t              : 2;
11723             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
11724             uint32_t              : 16;
11725         } MSDCT1_b;
11726     };
11727 
11728     union
11729     {
11730         __IOM uint32_t MSDCT2;         /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2              */
11731 
11732         struct
11733         {
11734             uint32_t              : 8;
11735             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
11736             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
11737             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
11738             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
11739             uint32_t              : 2;
11740             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
11741             uint32_t              : 16;
11742         } MSDCT2_b;
11743     };
11744 
11745     union
11746     {
11747         __IOM uint32_t MSDCT3;         /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3              */
11748 
11749         struct
11750         {
11751             uint32_t              : 8;
11752             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
11753             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
11754             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
11755             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
11756             uint32_t              : 2;
11757             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
11758             uint32_t              : 16;
11759         } MSDCT3_b;
11760     };
11761     __IM uint32_t RESERVED25[16];
11762 
11763     union
11764     {
11765         __IOM uint32_t SVDCT;          /*!< (@ 0x00000320) Slave Device Characteristic Table Register                 */
11766 
11767         struct
11768         {
11769             __IOM uint32_t TDCR   : 8; /*!< [7..0] Transfar Device Characteristic Register                            */
11770             __IOM uint32_t TBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
11771             __IOM uint32_t TBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
11772             __IOM uint32_t TBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
11773             __IOM uint32_t TBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
11774             uint32_t              : 2;
11775             __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role                                                      */
11776             uint32_t              : 16;
11777         } SVDCT_b;
11778     };
11779     __IOM uint32_t SDCTPIDL;           /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
11780                                         *                  ID Low Register                                            */
11781     __IOM uint32_t SDCTPIDH;           /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
11782                                         *                  ID High Register                                           */
11783     __IM uint32_t RESERVED26;
11784 
11785     union
11786     {
11787         __IM uint32_t SVDVAD0;         /*!< (@ 0x00000330) Slave Device Address Register 0                            */
11788 
11789         struct
11790         {
11791             uint32_t             : 16;
11792             __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
11793             uint32_t             : 1;
11794             __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
11795             uint32_t             : 2;
11796             __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
11797             __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
11798         } SVDVAD0_b;
11799     };
11800     __IM uint32_t RESERVED27[7];
11801 
11802     union
11803     {
11804         __IOM uint32_t CSECMD;         /*!< (@ 0x00000350) CCC Slave Events Command Register                          */
11805 
11806         struct
11807         {
11808             __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable                                    */
11809             __IOM uint32_t MSRQE  : 1; /*!< [1..1] Mastership Requests Enable                                         */
11810             uint32_t              : 1;
11811             __IOM uint32_t HJEVE  : 1; /*!< [3..3] Hot-Join Event Enable                                              */
11812             uint32_t              : 28;
11813         } CSECMD_b;
11814     };
11815 
11816     union
11817     {
11818         __IOM uint32_t CEACTST;        /*!< (@ 0x00000354) CCC Enter Activity State Register                          */
11819 
11820         struct
11821         {
11822             __IOM uint32_t ACTST : 4;  /*!< [3..0] Activity State                                                     */
11823             uint32_t             : 28;
11824         } CEACTST_b;
11825     };
11826 
11827     union
11828     {
11829         __IOM uint32_t CMWLG;          /*!< (@ 0x00000358) CCC Max Write Length Register                              */
11830 
11831         struct
11832         {
11833             __IOM uint32_t MWLG : 16;  /*!< [15..0] Max Write Length                                                  */
11834             uint32_t            : 16;
11835         } CMWLG_b;
11836     };
11837 
11838     union
11839     {
11840         __IOM uint32_t CMRLG;           /*!< (@ 0x0000035C) CCC Max Read Length Register                               */
11841 
11842         struct
11843         {
11844             __IOM uint32_t MRLG   : 16; /*!< [15..0] Max Read Length                                                   */
11845             __IOM uint32_t IBIPSZ : 8;  /*!< [23..16] IBI Payload Size                                                 */
11846             uint32_t              : 8;
11847         } CMRLG_b;
11848     };
11849 
11850     union
11851     {
11852         __IM uint32_t CETSTMD;         /*!< (@ 0x00000360) CCC Enter Test Mode Register                               */
11853 
11854         struct
11855         {
11856             __IM uint32_t TSTMD : 8;   /*!< [7..0] Test Mode                                                          */
11857             uint32_t            : 24;
11858         } CETSTMD_b;
11859     };
11860 
11861     union
11862     {
11863         __IOM uint32_t CGDVST;         /*!< (@ 0x00000364) CCC Get Device Status Register                             */
11864 
11865         struct
11866         {
11867             __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt                                                  */
11868             uint32_t              : 1;
11869             __IOM uint32_t PRTE   : 1; /*!< [5..5] Protocol Error                                                     */
11870             __IOM uint32_t ACTMD  : 2; /*!< [7..6] Slave Device's current Activity Mode                               */
11871             __IOM uint32_t VDRSV  : 8; /*!< [15..8] Vendor Reserved                                                   */
11872             uint32_t              : 16;
11873         } CGDVST_b;
11874     };
11875 
11876     union
11877     {
11878         __IOM uint32_t CMDSPW;         /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register                      */
11879 
11880         struct
11881         {
11882             __IOM uint32_t MSWDR : 3;  /*!< [2..0] Maximum Sustained Write Data Rate                                  */
11883             uint32_t             : 29;
11884         } CMDSPW_b;
11885     };
11886 
11887     union
11888     {
11889         __IOM uint32_t CMDSPR;         /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register                       */
11890 
11891         struct
11892         {
11893             __IOM uint32_t MSRDR  : 3; /*!< [2..0] Maximum Sustained Read Data Rate                                   */
11894             __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO)                               */
11895             uint32_t              : 26;
11896         } CMDSPR_b;
11897     };
11898 
11899     union
11900     {
11901         __IOM uint32_t CMDSPT;          /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register                 */
11902 
11903         struct
11904         {
11905             __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time                                      */
11906             uint32_t              : 7;
11907             __IOM uint32_t MRTE   : 1;  /*!< [31..31] Maximum Read Turnaround Time Enable                              */
11908         } CMDSPT_b;
11909     };
11910 
11911     union
11912     {
11913         __IOM uint32_t CETSM;          /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
11914                                         *                  Register                                                   */
11915 
11916         struct
11917         {
11918             uint32_t            : 8;
11919             __IOM uint32_t FREQ : 8;   /*!< [15..8] Frequency Byte                                                    */
11920             __IOM uint32_t INAC : 8;   /*!< [23..16] Inaccuracy Byte                                                  */
11921             uint32_t            : 8;
11922         } CETSM_b;
11923     };
11924     __IM uint32_t RESERVED28[2];
11925 
11926     union
11927     {
11928         __IOM uint32_t BITCNT;         /*!< (@ 0x00000380) Bit Count Register                                         */
11929 
11930         struct
11931         {
11932             __IOM uint32_t BCNT  : 5;  /*!< [4..0] Bit Counter                                                        */
11933             uint32_t             : 2;
11934             __OM uint32_t BCNTWP : 1;  /*!< [7..7] BCNT Write Protect                                                 */
11935             uint32_t             : 24;
11936         } BITCNT_b;
11937     };
11938     __IM uint32_t RESERVED29[4];
11939 
11940     union
11941     {
11942         __IM uint32_t NQSTLV;          /*!< (@ 0x00000394) Normal Queue Status Level Register                         */
11943 
11944         struct
11945         {
11946             __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level                                    */
11947             __IM uint32_t RSPQLV  : 8; /*!< [15..8] Normal Response Queue Level                                       */
11948             __IM uint32_t IBIQLV  : 8; /*!< [23..16] Normal IBI Queue Level                                           */
11949             __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count                                          */
11950             uint32_t              : 3;
11951         } NQSTLV_b;
11952     };
11953 
11954     union
11955     {
11956         __IM uint32_t NDBSTLV0;        /*!< (@ 0x00000398) Normal Data Buffer Status Level Register                   */
11957 
11958         struct
11959         {
11960             __IM uint32_t TDBFLV : 8;  /*!< [7..0] Normal Transmit Data Buffer Free Level                             */
11961             __IM uint32_t RDBLV  : 8;  /*!< [15..8] Normal Receive Data Buffer Level                                  */
11962             uint32_t             : 16;
11963         } NDBSTLV0_b;
11964     };
11965     __IM uint32_t RESERVED30[9];
11966 
11967     union
11968     {
11969         __IM uint32_t NRSQSTLV;        /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register          */
11970 
11971         struct
11972         {
11973             __IM uint32_t RSQLV : 8;   /*!< [7..0] Normal Receive Status Queue Level                                  */
11974             uint32_t            : 24;
11975         } NRSQSTLV_b;
11976     };
11977     __IM uint32_t RESERVED31[2];
11978 
11979     union
11980     {
11981         __IM uint32_t PRSTDBG;         /*!< (@ 0x000003CC) Present State Debug Register                               */
11982 
11983         struct
11984         {
11985             __IM uint32_t SCILV : 1;   /*!< [0..0] SCL Line Signal Level                                              */
11986             __IM uint32_t SDILV : 1;   /*!< [1..1] SDA Line Signal Level                                              */
11987             __IM uint32_t SCOLV : 1;   /*!< [2..2] SCL Output Level                                                   */
11988             __IM uint32_t SDOLV : 1;   /*!< [3..3] SDA Output Level                                                   */
11989             uint32_t            : 28;
11990         } PRSTDBG_b;
11991     };
11992 
11993     union
11994     {
11995         __IM uint32_t MSERRCNT;        /*!< (@ 0x000003D0) Master Error Counters Register                             */
11996 
11997         struct
11998         {
11999             __IM uint32_t M2ECNT : 8;  /*!< [7..0] M2 Error Counter                                                   */
12000             uint32_t             : 24;
12001         } MSERRCNT_b;
12002     };
12003 } R_I3C0_Type;                         /*!< Size = 980 (0x3d4)                                                        */
12004 
12005 /* =========================================================================================================================== */
12006 /* ================                                        R_MPU_MMPU                                         ================ */
12007 /* =========================================================================================================================== */
12008 
12009 /**
12010  * @brief Bus Master MPU (R_MPU_MMPU)
12011  */
12012 
12013 typedef struct                         /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
12014 {
12015     union
12016     {
12017         __IOM uint16_t OAD;            /*!< (@ 0x00000000) MMPU Operation After Detection Register                    */
12018 
12019         struct
12020         {
12021             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
12022             uint16_t           : 7;
12023             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
12024                                         *   stored.                                                                   */
12025         } OAD_b;
12026     };
12027     __IM uint16_t RESERVED;
12028 
12029     union
12030     {
12031         __IOM uint16_t OADPT;           /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register            */
12032 
12033         struct
12034         {
12035             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
12036             uint16_t               : 7;
12037             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
12038                                          *   stored.                                                                   */
12039         } OADPT_b;
12040     };
12041     __IM uint16_t               RESERVED1;
12042     __IM uint32_t               RESERVED2[62];
12043     __IOM R_MPU_MMPU_GROUP_Type DMAC0;    /*!< (@ 0x00000100) DMAC0 MMPU Registers                                       */
12044     __IOM R_MPU_MMPU_GROUP_Type DMAC1;    /*!< (@ 0x00000300) DMAC1 MMPU Registers                                       */
12045     __IOM R_MPU_MMPU_GROUP_Type EDMAC;    /*!< (@ 0x00000500) EDMAC MMPU Registers                                       */
12046     __IOM R_MPU_MMPU_GROUP_Type GLCDC;    /*!< (@ 0x00000700) GLCDC MMPU Registers                                       */
12047     __IOM R_MPU_MMPU_GROUP_Type DRW;      /*!< (@ 0x00000900) DRW MMPU Registers                                         */
12048     __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers                                    */
12049     __IOM R_MPU_MMPU_GROUP_Type CEU;      /*!< (@ 0x00000D00) CEU MMPU Registers                                         */
12050     __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers                                    */
12051     __IOM R_MPU_MMPU_GROUP_Type NPU;      /*!< (@ 0x00001100) NPU MMPU Registers                                         */
12052 } R_MPU_MMPU_Type;                        /*!< Size = 4864 (0x1300)                                                      */
12053 
12054 /* =========================================================================================================================== */
12055 /* ================                                        R_MPU_SPMON                                        ================ */
12056 /* =========================================================================================================================== */
12057 
12058 /**
12059  * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
12060  */
12061 
12062 typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
12063 {
12064     __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
12065 } R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
12066 
12067 /* =========================================================================================================================== */
12068 /* ================                                          R_MSTP                                           ================ */
12069 /* =========================================================================================================================== */
12070 
12071 /**
12072  * @brief System-Module Stop (R_MSTP)
12073  */
12074 
12075 typedef struct                          /*!< (@ 0x40203000) R_MSTP Structure                                           */
12076 {
12077     union
12078     {
12079         __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
12080 
12081         struct
12082         {
12083             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12084             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12085             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12086             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12087             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12088             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12089             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12090             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12091             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12092             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12093             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12094                                          *   usage.                                                                    */
12095             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12096                                          *   usage.                                                                    */
12097             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12098                                          *   usage.                                                                    */
12099             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12100                                          *   usage.                                                                    */
12101             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12102                                          *   usage.                                                                    */
12103             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12104                                          *   usage.                                                                    */
12105             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12106                                          *   usage.                                                                    */
12107             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12108                                          *   usage.                                                                    */
12109             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12110                                          *   usage.                                                                    */
12111             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12112                                          *   usage.                                                                    */
12113             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12114                                          *   usage.                                                                    */
12115             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12116                                          *   usage.                                                                    */
12117             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12118                                          *   usage.                                                                    */
12119             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12120                                          *   usage.                                                                    */
12121             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12122                                          *   usage.                                                                    */
12123             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12124                                          *   usage.                                                                    */
12125             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12126                                          *   usage.                                                                    */
12127             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12128                                          *   usage.                                                                    */
12129             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12130                                          *   usage.                                                                    */
12131             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12132                                          *   usage.                                                                    */
12133             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12134                                          *   usage.                                                                    */
12135             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12136                                          *   usage.                                                                    */
12137         } MSTPCRA_b;
12138     };
12139 
12140     union
12141     {
12142         __IOM uint32_t MSTPCRB;         /*!< (@ 0x00000004) Module Stop Control Register B                             */
12143 
12144         struct
12145         {
12146             __IOM uint32_t MSTPB0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12147             __IOM uint32_t MSTPB1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12148             __IOM uint32_t MSTPB2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12149             __IOM uint32_t MSTPB3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12150             __IOM uint32_t MSTPB4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12151             __IOM uint32_t MSTPB5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12152             __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12153             __IOM uint32_t MSTPB7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12154             __IOM uint32_t MSTPB8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12155             __IOM uint32_t MSTPB9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12156             __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12157                                          *   usage.                                                                    */
12158             __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12159                                          *   usage.                                                                    */
12160             __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12161                                          *   usage.                                                                    */
12162             __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12163                                          *   usage.                                                                    */
12164             __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12165                                          *   usage.                                                                    */
12166             __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12167                                          *   usage.                                                                    */
12168             __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12169                                          *   usage.                                                                    */
12170             __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12171                                          *   usage.                                                                    */
12172             __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12173                                          *   usage.                                                                    */
12174             __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12175                                          *   usage.                                                                    */
12176             __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12177                                          *   usage.                                                                    */
12178             __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12179                                          *   usage.                                                                    */
12180             __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12181                                          *   usage.                                                                    */
12182             __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12183                                          *   usage.                                                                    */
12184             __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12185                                          *   usage.                                                                    */
12186             __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12187                                          *   usage.                                                                    */
12188             __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12189                                          *   usage.                                                                    */
12190             __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12191                                          *   usage.                                                                    */
12192             __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12193                                          *   usage.                                                                    */
12194             __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12195                                          *   usage.                                                                    */
12196             __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12197                                          *   usage.                                                                    */
12198             __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12199                                          *   usage.                                                                    */
12200         } MSTPCRB_b;
12201     };
12202 
12203     union
12204     {
12205         __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
12206 
12207         struct
12208         {
12209             __IOM uint32_t MSTPC0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12210             __IOM uint32_t MSTPC1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12211             __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12212             __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12213             __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12214             __IOM uint32_t MSTPC5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12215             __IOM uint32_t MSTPC6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12216             __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12217             __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12218             __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12219             __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12220                                          *   usage.                                                                    */
12221             __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12222                                          *   usage.                                                                    */
12223             __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12224                                          *   usage.                                                                    */
12225             __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12226                                          *   usage.                                                                    */
12227             __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12228                                          *   usage.                                                                    */
12229             __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12230                                          *   usage.                                                                    */
12231             __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12232                                          *   usage.                                                                    */
12233             __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12234                                          *   usage.                                                                    */
12235             __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12236                                          *   usage.                                                                    */
12237             __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12238                                          *   usage.                                                                    */
12239             __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12240                                          *   usage.                                                                    */
12241             __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12242                                          *   usage.                                                                    */
12243             __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12244                                          *   usage.                                                                    */
12245             __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12246                                          *   usage.                                                                    */
12247             __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12248                                          *   usage.                                                                    */
12249             __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12250                                          *   usage.                                                                    */
12251             __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12252                                          *   usage.                                                                    */
12253             __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12254                                          *   usage.                                                                    */
12255             __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12256                                          *   usage.                                                                    */
12257             __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12258                                          *   usage.                                                                    */
12259             __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12260                                          *   usage.                                                                    */
12261             __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12262                                          *   usage.                                                                    */
12263         } MSTPCRC_b;
12264     };
12265 
12266     union
12267     {
12268         __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
12269 
12270         struct
12271         {
12272             __IOM uint32_t MSTPD0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12273             __IOM uint32_t MSTPD1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12274             __IOM uint32_t MSTPD2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12275             __IOM uint32_t MSTPD3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12276             __IOM uint32_t MSTPD4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12277             __IOM uint32_t MSTPD5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12278             __IOM uint32_t MSTPD6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12279             __IOM uint32_t MSTPD7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12280             __IOM uint32_t MSTPD8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12281             __IOM uint32_t MSTPD9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12282             __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12283                                          *   usage.                                                                    */
12284             __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12285                                          *   usage.                                                                    */
12286             __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12287                                          *   usage.                                                                    */
12288             __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12289                                          *   usage.                                                                    */
12290             __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12291                                          *   usage.                                                                    */
12292             __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12293                                          *   usage.                                                                    */
12294             __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12295                                          *   usage.                                                                    */
12296             __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12297                                          *   usage.                                                                    */
12298             __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12299                                          *   usage.                                                                    */
12300             __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12301                                          *   usage.                                                                    */
12302             __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12303                                          *   usage.                                                                    */
12304             __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12305                                          *   usage.                                                                    */
12306             __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12307                                          *   usage.                                                                    */
12308             __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12309                                          *   usage.                                                                    */
12310             __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12311                                          *   usage.                                                                    */
12312             __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12313                                          *   usage.                                                                    */
12314             __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12315                                          *   usage.                                                                    */
12316             __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12317                                          *   usage.                                                                    */
12318             __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12319                                          *   usage.                                                                    */
12320             __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12321                                          *   usage.                                                                    */
12322             __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12323                                          *   usage.                                                                    */
12324             __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12325                                          *   usage.                                                                    */
12326         } MSTPCRD_b;
12327     };
12328 
12329     union
12330     {
12331         union
12332         {
12333             __IOM uint32_t MSTPCRE;         /*!< (@ 0x00000010) Module Stop Control Register E                             */
12334 
12335             struct
12336             {
12337                 __IOM uint32_t MSTPE0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
12338                 __IOM uint32_t MSTPE1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
12339                 __IOM uint32_t MSTPE2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
12340                 __IOM uint32_t MSTPE3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
12341                 __IOM uint32_t MSTPE4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
12342                 __IOM uint32_t MSTPE5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
12343                 __IOM uint32_t MSTPE6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
12344                 __IOM uint32_t MSTPE7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
12345                 __IOM uint32_t MSTPE8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
12346                 __IOM uint32_t MSTPE9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
12347                 __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
12348                                              *   usage.                                                                    */
12349                 __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
12350                                              *   usage.                                                                    */
12351                 __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
12352                                              *   usage.                                                                    */
12353                 __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
12354                                              *   usage.                                                                    */
12355                 __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
12356                                              *   usage.                                                                    */
12357                 __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
12358                                              *   usage.                                                                    */
12359                 __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
12360                                              *   usage.                                                                    */
12361                 __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
12362                                              *   usage.                                                                    */
12363                 __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
12364                                              *   usage.                                                                    */
12365                 __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
12366                                              *   usage.                                                                    */
12367                 __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
12368                                              *   usage.                                                                    */
12369                 __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
12370                                              *   usage.                                                                    */
12371                 __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
12372                                              *   usage.                                                                    */
12373                 __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
12374                                              *   usage.                                                                    */
12375                 __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
12376                                              *   usage.                                                                    */
12377                 __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
12378                                              *   usage.                                                                    */
12379                 __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
12380                                              *   usage.                                                                    */
12381                 __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
12382                                              *   usage.                                                                    */
12383                 __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
12384                                              *   usage.                                                                    */
12385                 __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
12386                                              *   usage.                                                                    */
12387                 __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
12388                                              *   usage.                                                                    */
12389                 __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
12390                                              *   usage.                                                                    */
12391             } MSTPCRE_b;
12392         };
12393 
12394         union
12395         {
12396             __IOM uint16_t LSMRWDIS;         /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register              */
12397 
12398             struct
12399             {
12400                 __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control                                    */
12401                 __IOM uint16_t WDTDIS   : 1; /*!< [1..1] WDT Operate Clock Control                                          */
12402                 __IOM uint16_t IWDTIDS  : 1; /*!< [2..2] IWDT Register Clock Control                                        */
12403                 uint16_t                : 4;
12404                 __IOM uint16_t WREN     : 1; /*!< [7..7] Write Enable for bits [2:0]                                        */
12405                 __OM uint16_t  PRKEY    : 8; /*!< [15..8] LSMRWDIS Key Code                                                 */
12406             } LSMRWDIS_b;
12407         };
12408     };
12409 } R_MSTP_Type;                               /*!< Size = 20 (0x14)                                                          */
12410 
12411 /* =========================================================================================================================== */
12412 /* ================                                          R_PORT0                                          ================ */
12413 /* =========================================================================================================================== */
12414 
12415 /**
12416  * @brief I/O Ports (R_PORT0)
12417  */
12418 
12419 typedef struct                         /*!< (@ 0x40400000) R_PORT0 Structure                                          */
12420 {
12421     union
12422     {
12423         union
12424         {
12425             __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
12426 
12427             struct
12428             {
12429                 __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
12430                 __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
12431             } PCNTR1_b;
12432         };
12433 
12434         struct
12435         {
12436             union
12437             {
12438                 __IOM uint16_t PDR;           /*!< (@ 0x00000000) Data direction register                                    */
12439 
12440                 struct
12441                 {
12442                     __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
12443                     __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
12444                     __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
12445                     __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
12446                     __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
12447                     __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
12448                     __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
12449                     __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
12450                     __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
12451                     __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
12452                     __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
12453                     __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
12454                     __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
12455                     __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
12456                     __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
12457                     __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
12458                 } PDR_b;
12459             };
12460 
12461             union
12462             {
12463                 __IOM uint16_t PODR;           /*!< (@ 0x00000002) Output data register                                       */
12464 
12465                 struct
12466                 {
12467                     __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
12468                     __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
12469                     __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
12470                     __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
12471                     __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
12472                     __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
12473                     __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
12474                     __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
12475                     __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
12476                     __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
12477                     __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
12478                     __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
12479                     __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
12480                     __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
12481                     __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
12482                     __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
12483                 } PODR_b;
12484             };
12485         };
12486     };
12487 
12488     union
12489     {
12490         union
12491         {
12492             __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
12493 
12494             struct
12495             {
12496                 __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
12497                 __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
12498             } PCNTR2_b;
12499         };
12500 
12501         struct
12502         {
12503             union
12504             {
12505                 __IM uint16_t PIDR;           /*!< (@ 0x00000004) Input data register                                        */
12506 
12507                 struct
12508                 {
12509                     __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
12510                     __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
12511                     __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
12512                     __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
12513                     __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
12514                     __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
12515                     __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
12516                     __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
12517                     __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
12518                     __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
12519                     __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
12520                     __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
12521                     __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
12522                     __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
12523                     __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
12524                     __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
12525                 } PIDR_b;
12526             };
12527 
12528             union
12529             {
12530                 __IM uint16_t EIDR;           /*!< (@ 0x00000006) Event input data register                                  */
12531 
12532                 struct
12533                 {
12534                     __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
12535                     __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
12536                     __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
12537                     __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
12538                     __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
12539                     __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
12540                     __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
12541                     __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
12542                     __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
12543                     __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
12544                     __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
12545                     __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
12546                     __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
12547                     __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
12548                     __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
12549                     __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
12550                 } EIDR_b;
12551             };
12552         };
12553     };
12554 
12555     union
12556     {
12557         union
12558         {
12559             __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
12560 
12561             struct
12562             {
12563                 __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
12564                 __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
12565             } PCNTR3_b;
12566         };
12567 
12568         struct
12569         {
12570             union
12571             {
12572                 __OM uint16_t POSR;           /*!< (@ 0x00000008) Output reset register                                      */
12573 
12574                 struct
12575                 {
12576                     __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
12577                     __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
12578                     __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
12579                     __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
12580                     __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
12581                     __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
12582                     __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
12583                     __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
12584                     __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
12585                     __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
12586                     __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
12587                     __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
12588                     __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
12589                     __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
12590                     __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
12591                     __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
12592                 } POSR_b;
12593             };
12594 
12595             union
12596             {
12597                 __OM uint16_t PORR;           /*!< (@ 0x0000000A) Output set register                                        */
12598 
12599                 struct
12600                 {
12601                     __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
12602                     __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
12603                     __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
12604                     __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
12605                     __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
12606                     __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
12607                     __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
12608                     __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
12609                     __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
12610                     __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
12611                     __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
12612                     __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
12613                     __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
12614                     __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
12615                     __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
12616                     __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
12617                 } PORR_b;
12618             };
12619         };
12620     };
12621 
12622     union
12623     {
12624         union
12625         {
12626             __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
12627 
12628             struct
12629             {
12630                 __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
12631                 __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
12632             } PCNTR4_b;
12633         };
12634 
12635         struct
12636         {
12637             union
12638             {
12639                 __IOM uint16_t EOSR;           /*!< (@ 0x0000000C) Event output reset register                                */
12640 
12641                 struct
12642                 {
12643                     __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
12644                     __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
12645                     __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
12646                     __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
12647                     __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
12648                     __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
12649                     __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
12650                     __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
12651                     __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
12652                     __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
12653                     __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
12654                     __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
12655                     __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
12656                     __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
12657                     __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
12658                     __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
12659                 } EOSR_b;
12660             };
12661 
12662             union
12663             {
12664                 __IOM uint16_t EORR;           /*!< (@ 0x0000000E) Event output set register                                  */
12665 
12666                 struct
12667                 {
12668                     __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
12669                     __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
12670                     __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
12671                     __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
12672                     __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
12673                     __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
12674                     __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
12675                     __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
12676                     __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
12677                     __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
12678                     __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
12679                     __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
12680                     __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
12681                     __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
12682                     __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
12683                     __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
12684                 } EORR_b;
12685             };
12686         };
12687     };
12688 } R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
12689 
12690 /* =========================================================================================================================== */
12691 /* ================                                           R_PFS                                           ================ */
12692 /* =========================================================================================================================== */
12693 
12694 /**
12695  * @brief I/O Ports-PFS (R_PFS)
12696  */
12697 
12698 typedef struct                         /*!< (@ 0x40400800) R_PFS Structure                                            */
12699 {
12700     __IOM R_PFS_PORT_Type PORT[15];    /*!< (@ 0x00000000) Port [0..14]                                               */
12701 } R_PFS_Type;                          /*!< Size = 960 (0x3c0)                                                        */
12702 
12703 /* =========================================================================================================================== */
12704 /* ================                                          R_PMISC                                          ================ */
12705 /* =========================================================================================================================== */
12706 
12707 /**
12708  * @brief I/O Ports-MISC (R_PMISC)
12709  */
12710 
12711 typedef struct                         /*!< (@ 0x40400D00) R_PMISC Structure                                          */
12712 {
12713     union
12714     {
12715         __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
12716 
12717         struct
12718         {
12719             uint8_t                : 4;
12720             __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
12721             uint8_t                : 3;
12722         } PFENET_b;
12723     };
12724     __IM uint8_t  RESERVED;
12725     __IM uint16_t RESERVED1[5];
12726 
12727     union
12728     {
12729         __IOM uint8_t PWPR;            /*!< (@ 0x0000000C) Write-Protect Register                                     */
12730 
12731         struct
12732         {
12733             uint8_t             : 6;
12734             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
12735             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
12736         } PWPR_b;
12737     };
12738     __IM uint8_t  RESERVED2;
12739     __IM uint16_t RESERVED3[3];
12740 
12741     union
12742     {
12743         __IOM uint8_t PWPRS;           /*!< (@ 0x00000014) Write-Protect Register for Secure                          */
12744 
12745         struct
12746         {
12747             uint8_t             : 6;
12748             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
12749             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
12750         } PWPRS_b;
12751     };
12752     __IM uint8_t             RESERVED4;
12753     __IM uint16_t            RESERVED5[13];
12754     __IOM R_PMISC_PMSAR_Type PMSAR[15]; /*!< (@ 0x00000030) Port Security Attribution Register                         */
12755 } R_PMISC_Type;                         /*!< Size = 108 (0x6c)                                                         */
12756 
12757 /* =========================================================================================================================== */
12758 /* ================                                           R_RTC                                           ================ */
12759 /* =========================================================================================================================== */
12760 
12761 /**
12762  * @brief Realtime Clock (R_RTC)
12763  */
12764 
12765 typedef struct                         /*!< (@ 0x40202000) R_RTC Structure                                            */
12766 {
12767     union
12768     {
12769         __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
12770 
12771         struct
12772         {
12773             __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
12774             __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
12775             __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
12776             __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
12777             __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
12778             __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
12779             __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
12780             uint8_t            : 1;
12781         } R64CNT_b;
12782     };
12783     __IM uint8_t RESERVED;
12784 
12785     union
12786     {
12787         union
12788         {
12789             __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
12790 
12791             struct
12792             {
12793                 __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
12794                                           *   counter b7 to b0.                                                         */
12795             } BCNT0_b;
12796         };
12797 
12798         union
12799         {
12800             __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
12801 
12802             struct
12803             {
12804                 __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
12805                                           *   a carry is generated, 1 is added to the tens place.                       */
12806                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
12807                 uint8_t             : 1;
12808             } RSECCNT_b;
12809         };
12810     };
12811     __IM uint8_t RESERVED1;
12812 
12813     union
12814     {
12815         union
12816         {
12817             __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
12818 
12819             struct
12820             {
12821                 __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
12822                                           *   counter b15 to b8.                                                        */
12823             } BCNT1_b;
12824         };
12825 
12826         union
12827         {
12828             __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
12829 
12830             struct
12831             {
12832                 __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
12833                                           *   a carry is generated, 1 is added to the tens place.                       */
12834                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
12835                 uint8_t             : 1;
12836             } RMINCNT_b;
12837         };
12838     };
12839     __IM uint8_t RESERVED2;
12840 
12841     union
12842     {
12843         union
12844         {
12845             __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
12846 
12847             struct
12848             {
12849                 __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
12850                                           *   counter b23 to b16.                                                       */
12851             } BCNT2_b;
12852         };
12853 
12854         union
12855         {
12856             __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
12857 
12858             struct
12859             {
12860                 __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
12861                                          *   carry is generated, 1 is added to the tens place.                         */
12862                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
12863                                          *   the ones place.                                                           */
12864                 __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
12865                 uint8_t          : 1;
12866             } RHRCNT_b;
12867         };
12868     };
12869     __IM uint8_t RESERVED3;
12870 
12871     union
12872     {
12873         union
12874         {
12875             __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
12876 
12877             struct
12878             {
12879                 __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
12880                                           *   counter b31 to b24.                                                       */
12881             } BCNT3_b;
12882         };
12883 
12884         union
12885         {
12886             __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
12887 
12888             struct
12889             {
12890                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
12891                 uint8_t            : 5;
12892             } RWKCNT_b;
12893         };
12894     };
12895     __IM uint8_t RESERVED4;
12896 
12897     union
12898     {
12899         __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
12900 
12901         struct
12902         {
12903             __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
12904                                         *   is generated, 1 is added to the tens place.                               */
12905             __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
12906                                         *   ones place.                                                               */
12907             uint8_t : 2;
12908         } RDAYCNT_b;
12909     };
12910     __IM uint8_t RESERVED5;
12911 
12912     union
12913     {
12914         __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
12915 
12916         struct
12917         {
12918             __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
12919                                         *   a carry is generated, 1 is added to the tens place.                       */
12920             __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
12921                                         *   the ones place.                                                           */
12922             uint8_t : 3;
12923         } RMONCNT_b;
12924     };
12925     __IM uint8_t RESERVED6;
12926 
12927     union
12928     {
12929         __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
12930 
12931         struct
12932         {
12933             __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
12934                                         *   carry is generated, 1 is added to the tens place.                         */
12935             __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
12936                                         *   ones place. When a carry is generated in the tens place,
12937                                         *   1 is added to the hundreds place.                                         */
12938             uint16_t : 8;
12939         } RYRCNT_b;
12940     };
12941 
12942     union
12943     {
12944         union
12945         {
12946             __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
12947 
12948             struct
12949             {
12950                 __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
12951                                             *   corresponding to 32-bit binary counter b7 to b0.                          */
12952             } BCNT0AR_b;
12953         };
12954 
12955         union
12956         {
12957             __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
12958 
12959             struct
12960             {
12961                 __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
12962                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
12963                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
12964             } RSECAR_b;
12965         };
12966     };
12967     __IM uint8_t RESERVED7;
12968 
12969     union
12970     {
12971         union
12972         {
12973             __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
12974 
12975             struct
12976             {
12977                 __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
12978                                             *   corresponding to 32-bit binary counter b15 to b8.                         */
12979             } BCNT1AR_b;
12980         };
12981 
12982         union
12983         {
12984             __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
12985 
12986             struct
12987             {
12988                 __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
12989                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
12990                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
12991             } RMINAR_b;
12992         };
12993     };
12994     __IM uint8_t RESERVED8;
12995 
12996     union
12997     {
12998         union
12999         {
13000             __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
13001 
13002             struct
13003             {
13004                 __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
13005                                             *   counter b23 to b16.                                                       */
13006             } BCNT2AR_b;
13007         };
13008 
13009         union
13010         {
13011             __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
13012 
13013             struct
13014             {
13015                 __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
13016                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
13017                 __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
13018                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
13019             } RHRAR_b;
13020         };
13021     };
13022     __IM uint8_t RESERVED9;
13023 
13024     union
13025     {
13026         union
13027         {
13028             __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
13029 
13030             struct
13031             {
13032                 __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
13033                                             *   counter b31 to b24.                                                       */
13034             } BCNT3AR_b;
13035         };
13036 
13037         union
13038         {
13039             __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
13040 
13041             struct
13042             {
13043                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
13044                 uint8_t            : 4;
13045                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
13046             } RWKAR_b;
13047         };
13048     };
13049     __IM uint8_t RESERVED10;
13050 
13051     union
13052     {
13053         union
13054         {
13055             __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
13056 
13057             struct
13058             {
13059                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
13060                                         *   for setting the alarm enable corresponding to 32-bit binary
13061                                         *   counter b7 to b0.                                                         */
13062             } BCNT0AER_b;
13063         };
13064 
13065         union
13066         {
13067             __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
13068 
13069             struct
13070             {
13071                 __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
13072                 __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
13073                 uint8_t              : 1;
13074                 __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
13075             } RDAYAR_b;
13076         };
13077     };
13078     __IM uint8_t RESERVED11;
13079 
13080     union
13081     {
13082         union
13083         {
13084             __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
13085 
13086             struct
13087             {
13088                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
13089                                         *   for setting the alarm enable corresponding to 32-bit binary
13090                                         *   counter b15 to b8.                                                        */
13091             } BCNT1AER_b;
13092         };
13093 
13094         union
13095         {
13096             __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
13097 
13098             struct
13099             {
13100                 __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
13101                 __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
13102                 uint8_t             : 2;
13103                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
13104             } RMONAR_b;
13105         };
13106     };
13107     __IM uint8_t RESERVED12;
13108 
13109     union
13110     {
13111         union
13112         {
13113             __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
13114 
13115             struct
13116             {
13117                 __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
13118                                          *   for setting the alarm enable corresponding to 32-bit binary
13119                                          *   counter b23 to b16.                                                       */
13120                 uint16_t : 8;
13121             } BCNT2AER_b;
13122         };
13123 
13124         union
13125         {
13126             __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
13127 
13128             struct
13129             {
13130                 __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
13131                 __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
13132                 uint16_t            : 8;
13133             } RYRAR_b;
13134         };
13135     };
13136 
13137     union
13138     {
13139         union
13140         {
13141             __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
13142 
13143             struct
13144             {
13145                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
13146                                         *   for setting the alarm enable corresponding to 32-bit binary
13147                                         *   counter b31 to b24.                                                       */
13148             } BCNT3AER_b;
13149         };
13150 
13151         union
13152         {
13153             __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
13154 
13155             struct
13156             {
13157                 uint8_t           : 7;
13158                 __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
13159             } RYRAREN_b;
13160         };
13161     };
13162     __IM uint8_t  RESERVED13;
13163     __IM uint16_t RESERVED14;
13164 
13165     union
13166     {
13167         __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
13168 
13169         struct
13170         {
13171             __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
13172             __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
13173             __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
13174             __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
13175             __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
13176         } RCR1_b;
13177     };
13178     __IM uint8_t RESERVED15;
13179 
13180     union
13181     {
13182         __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
13183 
13184         struct
13185         {
13186             __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
13187             __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
13188             __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
13189             __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
13190             __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
13191                                         *   the setting of this bit is disabled.)                                     */
13192             __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
13193                                         *   is selected, the setting of this bit is disabled.)                        */
13194             __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
13195             __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
13196         } RCR2_b;
13197     };
13198     __IM uint8_t  RESERVED16;
13199     __IM uint16_t RESERVED17;
13200 
13201     union
13202     {
13203         __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
13204 
13205         struct
13206         {
13207             __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
13208             uint8_t              : 6;
13209             __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
13210         } RCR4_b;
13211     };
13212     __IM uint8_t RESERVED18;
13213 
13214     union
13215     {
13216         __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
13217 
13218         struct
13219         {
13220             __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
13221                                         *   clock from the LOCOclock, this bit sets the comparison
13222                                         *   value of the 128-Hz clock cycle.                                          */
13223             uint16_t : 15;
13224         } RFRH_b;
13225     };
13226 
13227     union
13228     {
13229         __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
13230 
13231         struct
13232         {
13233             __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
13234                                         *   clock from the main clock, this bit sets the comparison
13235                                         *   value of the 128-Hz clock cycle.                                          */
13236         } RFRL_b;
13237     };
13238 
13239     union
13240     {
13241         __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
13242 
13243         struct
13244         {
13245             __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
13246                                         *   from the prescaler.                                                       */
13247             __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
13248         } RADJ_b;
13249     };
13250     __IM uint8_t           RESERVED19;
13251     __IM uint16_t          RESERVED20[8];
13252     __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
13253     __IM uint16_t          RESERVED21[5];
13254     __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
13255 } R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
13256 
13257 /* =========================================================================================================================== */
13258 /* ================                                          R_SCI0                                           ================ */
13259 /* =========================================================================================================================== */
13260 
13261 /**
13262  * @brief Serial Communications Interface (R_SCI0)
13263  */
13264 
13265 typedef struct                         /*!< (@ 0x40358000) R_SCI0 Structure                                           */
13266 {
13267     union
13268     {
13269         union
13270         {
13271             __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
13272 
13273             struct
13274             {
13275                 __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
13276                 __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
13277                 __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
13278                 __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
13279                 __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
13280                 __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
13281                 __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
13282             } SMR_b;
13283         };
13284 
13285         union
13286         {
13287             __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
13288 
13289             struct
13290             {
13291                 __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
13292                 __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
13293                 __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
13294                 __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
13295                 __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
13296                 __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
13297             } SMR_SMCI_b;
13298         };
13299     };
13300 
13301     union
13302     {
13303         __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
13304 
13305         struct
13306         {
13307             __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
13308         } BRR_b;
13309     };
13310 
13311     union
13312     {
13313         union
13314         {
13315             __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
13316 
13317             struct
13318             {
13319                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
13320                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
13321                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
13322                                          *   mode when SMR.MP = 1)                                                     */
13323                 __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
13324                 __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
13325                 __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
13326                 __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
13327             } SCR_b;
13328         };
13329 
13330         union
13331         {
13332             __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
13333 
13334             struct
13335             {
13336                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
13337                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
13338                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
13339                 __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
13340                 __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
13341                 __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
13342                 __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
13343             } SCR_SMCI_b;
13344         };
13345     };
13346 
13347     union
13348     {
13349         __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
13350 
13351         struct
13352         {
13353             __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
13354         } TDR_b;
13355     };
13356 
13357     union
13358     {
13359         union
13360         {
13361             __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
13362 
13363             struct
13364             {
13365                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
13366                 __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
13367                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
13368                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
13369                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
13370                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
13371                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
13372                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
13373             } SSR_b;
13374         };
13375 
13376         union
13377         {
13378             __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
13379 
13380             struct
13381             {
13382                 __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
13383                                          *   multi-processor) and FIFO selected)                                       */
13384                 uint8_t            : 1;
13385                 __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
13386                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
13387                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
13388                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
13389                 __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
13390                 __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
13391             } SSR_FIFO_b;
13392         };
13393 
13394         union
13395         {
13396             __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
13397 
13398             struct
13399             {
13400                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
13401                                          *   card interface mode.                                                      */
13402                 __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
13403                                          *   mode.                                                                     */
13404                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
13405                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
13406                 __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
13407                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
13408                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
13409                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
13410             } SSR_SMCI_b;
13411         };
13412     };
13413 
13414     union
13415     {
13416         __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
13417 
13418         struct
13419         {
13420             __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
13421         } RDR_b;
13422     };
13423 
13424     union
13425     {
13426         __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
13427 
13428         struct
13429         {
13430             __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
13431             uint8_t            : 1;
13432             __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
13433                                         *   operation is to be in simple I2C mode.                                    */
13434             __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
13435                                         *   setting is invalid and a fixed data length of 8 bits is
13436                                         *   used in modes other than asynchronous mode.Set this bit
13437                                         *   to 1 if operation is to be in simple I2C mode.                            */
13438             __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
13439             uint8_t            : 2;
13440             __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
13441                                         *   in combination with the SMR.BCP[1:0] bits                                 */
13442         } SCMR_b;
13443     };
13444 
13445     union
13446     {
13447         __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
13448 
13449         struct
13450         {
13451             __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
13452                                         *   asynchronous mode).                                                       */
13453             __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
13454                                         *   mode).                                                                    */
13455             __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
13456             __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
13457                                         *   only in asynchronous mode and SCR.CKE[1]=0)                               */
13458             __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
13459                                         *   mode)                                                                     */
13460             __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
13461                                         *   be 0 without simple I2C mode and asynchronous mode.)In
13462                                         *   asynchronous mode, for RXDn input only. In simple I2C mode,
13463                                         *   for RXDn/TxDn input.                                                      */
13464             __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
13465                                         *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
13466             __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
13467                                         *   in asynchronous mode)                                                     */
13468         } SEMR_b;
13469     };
13470 
13471     union
13472     {
13473         __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
13474 
13475         struct
13476         {
13477             __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
13478             uint8_t            : 5;
13479         } SNFR_b;
13480     };
13481 
13482     union
13483     {
13484         __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
13485 
13486         struct
13487         {
13488             __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
13489             uint8_t             : 2;
13490             __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
13491                                         *   signal from the on-chip baud rate generator.                              */
13492         } SIMR1_b;
13493     };
13494 
13495     union
13496     {
13497         __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
13498 
13499         struct
13500         {
13501             __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
13502             __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
13503             uint8_t               : 3;
13504             __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
13505             uint8_t               : 2;
13506         } SIMR2_b;
13507     };
13508 
13509     union
13510     {
13511         __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
13512 
13513         struct
13514         {
13515             __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
13516             __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
13517             __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
13518             __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
13519                                            *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
13520             __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
13521             __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
13522         } SIMR3_b;
13523     };
13524 
13525     union
13526     {
13527         __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
13528 
13529         struct
13530         {
13531             __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
13532             uint8_t              : 7;
13533         } SISR_b;
13534     };
13535 
13536     union
13537     {
13538         __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
13539 
13540         struct
13541         {
13542             __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
13543             __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
13544             __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
13545             __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
13546             __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
13547             uint8_t              : 1;
13548             __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
13549             __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
13550         } SPMR_b;
13551     };
13552 
13553     union
13554     {
13555         union
13556         {
13557             __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
13558 
13559             struct
13560             {
13561                 __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
13562             } TDRHL_b;
13563         };
13564 
13565         union
13566         {
13567             __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
13568 
13569             struct
13570             {
13571                 __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
13572                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
13573                 __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
13574                                          *   mode and SMR.MP=1 and FIFO selected)                                      */
13575                 uint16_t : 6;
13576             } FTDRHL_b;
13577         };
13578 
13579         struct
13580         {
13581             union
13582             {
13583                 __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
13584 
13585                 struct
13586                 {
13587                     __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
13588                                              *   mode(including multi-processor) or clock synchronous mode,
13589                                              *   and FIFO selected)                                                        */
13590                     __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
13591                                              *   mode and SMR.MP=1 and FIFO selected)                                      */
13592                     uint8_t : 6;
13593                 } FTDRH_b;
13594             };
13595 
13596             union
13597             {
13598                 __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
13599 
13600                 struct
13601                 {
13602                     __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
13603                                              *   mode(including multi-processor) or clock synchronous mode,
13604                                              *   and FIFO selected)                                                        */
13605                 } FTDRL_b;
13606             };
13607         };
13608     };
13609 
13610     union
13611     {
13612         union
13613         {
13614             __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
13615 
13616             struct
13617             {
13618                 __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
13619             } RDRHL_b;
13620         };
13621 
13622         union
13623         {
13624             __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
13625 
13626             struct
13627             {
13628                 __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
13629                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
13630                 __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
13631                                          *   with SMR.MP=1 and FIFO selected) It can read multi-processor
13632                                          *   bit corresponded to serial receive data(RDATA[8:0])                       */
13633                 __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
13634                 __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
13635                 __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
13636                 __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
13637                 __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
13638                 uint16_t           : 1;
13639             } FRDRHL_b;
13640         };
13641 
13642         struct
13643         {
13644             union
13645             {
13646                 __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
13647 
13648                 struct
13649                 {
13650                     __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
13651                                              *   multi-processor) or clock synchronous mode, and FIFO selected)            */
13652                     __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
13653                                              *   with SMR.MP=1 and FIFO selected) It can read multi-processor
13654                                              *   bit corresponded to serial receive data(RDATA[8:0])                       */
13655                     __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
13656                     __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
13657                     __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
13658                     __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
13659                     __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
13660                     uint8_t           : 1;
13661                 } FRDRH_b;
13662             };
13663 
13664             union
13665             {
13666                 __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
13667 
13668                 struct
13669                 {
13670                     __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
13671                                              *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
13672                                              *   When reading both of FRDRH register and FRDRL register,
13673                                              *   please read by an order of the FRDRH register and the FRDRL
13674                                              *   register.                                                                 */
13675                 } FRDRL_b;
13676             };
13677         };
13678     };
13679 
13680     union
13681     {
13682         __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
13683 
13684         struct
13685         {
13686             __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
13687         } MDDR_b;
13688     };
13689 
13690     union
13691     {
13692         __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
13693 
13694         struct
13695         {
13696             __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
13697             uint8_t             : 2;
13698             __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
13699             __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
13700             uint8_t             : 1;
13701             __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
13702                                         *   multi-processor)                                                          */
13703             __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
13704                                         *   mode(including multi-processor)                                           */
13705         } DCCR_b;
13706     };
13707 
13708     union
13709     {
13710         __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
13711 
13712         struct
13713         {
13714             __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
13715                                         *   multi-processor) or clock synchronous mode)                               */
13716             __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
13717             __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
13718             __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
13719                                         *   reception data ready, the interrupt request is selected.)                 */
13720             __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
13721                                         *   mode(including multi-processor) or clock synchronous mode)                */
13722             __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
13723                                         *   mode(including multi-processor) or clock synchronous mode)                */
13724             __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
13725                                         *   in asynchronous mode(including multi-processor) or clock
13726                                         *   synchronous mode)                                                         */
13727         } FCR_b;
13728     };
13729 
13730     union
13731     {
13732         __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
13733 
13734         struct
13735         {
13736             __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
13737                                         *   data stored in FRDRH and FRDRL(Valid only in asynchronous
13738                                         *   mode(including multi-processor) or clock synchronous mode,
13739                                         *   while FCR.FM=1)                                                           */
13740             uint16_t        : 3;
13741             __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
13742                                         *   data stored in FTDRH and FTDRL(Valid only in asynchronous
13743                                         *   mode(including multi-processor) or clock synchronous mode,
13744                                         *   while FCR.FM=1)                                                           */
13745             uint16_t : 3;
13746         } FDR_b;
13747     };
13748 
13749     union
13750     {
13751         __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
13752 
13753         struct
13754         {
13755             __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
13756                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
13757             uint16_t           : 1;
13758             __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
13759                                         *   a framing error among the receive data stored in the receive
13760                                         *   FIFO data register (FRDRH and FRDRL).                                     */
13761             uint16_t           : 1;
13762             __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
13763                                         *   a parity error among the receive data stored in the receive
13764                                         *   FIFO data register (FRDRH and FRDRL).                                     */
13765             uint16_t : 3;
13766         } LSR_b;
13767     };
13768 
13769     union
13770     {
13771         __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
13772 
13773         struct
13774         {
13775             __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
13776                                         *   wake-up function                                                          */
13777             uint16_t : 7;
13778         } CDR_b;
13779     };
13780 
13781     union
13782     {
13783         __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
13784 
13785         struct
13786         {
13787             __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
13788                                         *   is shown.)                                                                */
13789             __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
13790                                         *   TxD terminal is selected when SCR.TE = 0.)                                */
13791             __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
13792                                         *   of SPB2DT is output to TxD terminal.)                                     */
13793             uint8_t            : 1;
13794             __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
13795             __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
13796             __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
13797             __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
13798         } SPTR_b;
13799     };
13800 
13801     union
13802     {
13803         __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
13804 
13805         struct
13806         {
13807             __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
13808             __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
13809             __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
13810             __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
13811         } ACTR_b;
13812     };
13813     __IM uint16_t RESERVED;
13814 
13815     union
13816     {
13817         __IOM uint8_t ESMER;           /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
13818 
13819         struct
13820         {
13821             __IOM uint8_t ESME : 1;    /*!< [0..0] Extended Serial Mode Enable                                        */
13822             uint8_t            : 7;
13823         } ESMER_b;
13824     };
13825 
13826     union
13827     {
13828         __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
13829 
13830         struct
13831         {
13832             uint8_t             : 1;
13833             __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
13834             __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
13835             __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
13836             uint8_t             : 4;
13837         } CR0_b;
13838     };
13839 
13840     union
13841     {
13842         __IOM uint8_t CR1;             /*!< (@ 0x00000022) Control Register 1                                         */
13843 
13844         struct
13845         {
13846             __IOM uint8_t BFE   : 1;   /*!< [0..0] Break Field Enable                                                 */
13847             __IOM uint8_t CF0RE : 1;   /*!< [1..1] Control Field 0 Reception Enable                                   */
13848             __IOM uint8_t CF1DS : 2;   /*!< [3..2] Control Field 1 Data Register Select                               */
13849             __IOM uint8_t PIBE  : 1;   /*!< [4..4] Priority Interrupt Bit Enable                                      */
13850             __IOM uint8_t PIBS  : 3;   /*!< [7..5] Priority Interrupt Bit Select                                      */
13851         } CR1_b;
13852     };
13853 
13854     union
13855     {
13856         __IOM uint8_t CR2;             /*!< (@ 0x00000023) Control Register 2                                         */
13857 
13858         struct
13859         {
13860             __IOM uint8_t DFCS : 3;    /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
13861             uint8_t            : 1;
13862             __IOM uint8_t BCCS : 2;    /*!< [5..4] Bus Collision Detection Clock Select                               */
13863             __IOM uint8_t RTS  : 2;    /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
13864         } CR2_b;
13865     };
13866 
13867     union
13868     {
13869         __IOM uint8_t CR3;             /*!< (@ 0x00000024) Control Register 3                                         */
13870 
13871         struct
13872         {
13873             __IOM uint8_t SDST : 1;    /*!< [0..0] Start Frame Detection Start                                        */
13874             uint8_t            : 7;
13875         } CR3_b;
13876     };
13877 
13878     union
13879     {
13880         __IOM uint8_t PCR;             /*!< (@ 0x00000025) Port Control Register                                      */
13881 
13882         struct
13883         {
13884             __IOM uint8_t TXDXPS : 1;  /*!< [0..0] TXDXn Signal Polarity Select                                       */
13885             __IOM uint8_t RXDXPS : 1;  /*!< [1..1] RXDXn Signal Polarity Select                                       */
13886             uint8_t              : 2;
13887             __IOM uint8_t SHARPS : 1;  /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
13888             uint8_t              : 3;
13889         } PCR_b;
13890     };
13891 
13892     union
13893     {
13894         __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
13895 
13896         struct
13897         {
13898             __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
13899             __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
13900             __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
13901             __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
13902             __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
13903             __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
13904             uint8_t              : 2;
13905         } ICR_b;
13906     };
13907 
13908     union
13909     {
13910         __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
13911 
13912         struct
13913         {
13914             __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
13915             __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
13916             __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
13917             __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
13918             __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
13919             __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
13920             uint8_t            : 2;
13921         } STR_b;
13922     };
13923 
13924     union
13925     {
13926         __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
13927 
13928         struct
13929         {
13930             __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
13931             __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
13932             __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
13933             __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
13934             __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
13935             __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
13936             uint8_t              : 2;
13937         } STCR_b;
13938     };
13939     __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
13940 
13941     union
13942     {
13943         __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
13944 
13945         struct
13946         {
13947             __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
13948             __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
13949             __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
13950             __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
13951             __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
13952             __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
13953             __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
13954             __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
13955         } CF0CR_b;
13956     };
13957     __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
13958     __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
13959     __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
13960 
13961     union
13962     {
13963         __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
13964 
13965         struct
13966         {
13967             __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
13968             __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
13969             __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
13970             __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
13971             __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
13972             __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
13973             __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
13974             __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
13975         } CF1CR_b;
13976     };
13977     __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
13978 
13979     union
13980     {
13981         __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
13982 
13983         struct
13984         {
13985             __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
13986             uint8_t            : 7;
13987         } TCR_b;
13988     };
13989 
13990     union
13991     {
13992         __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
13993 
13994         struct
13995         {
13996             __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
13997             uint8_t            : 1;
13998             __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
13999             __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
14000             uint8_t            : 1;
14001         } TMR_b;
14002     };
14003     __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
14004     __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
14005 } R_SCI0_Type;                         /*!< Size = 52 (0x34)                                                          */
14006 
14007 /* =========================================================================================================================== */
14008 /* ================                                          R_SDHI0                                          ================ */
14009 /* =========================================================================================================================== */
14010 
14011 /**
14012  * @brief SD/MMC Host Interface (R_SDHI0)
14013  */
14014 
14015 typedef struct                          /*!< (@ 0x40252000) R_SDHI0 Structure                                          */
14016 {
14017     union
14018     {
14019         __IOM uint32_t SD_CMD;          /*!< (@ 0x00000000) Command Type Register                                      */
14020 
14021         struct
14022         {
14023             __IOM uint32_t CMDIDX : 6;  /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
14024                                          *   (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
14025                                          *   SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101              */
14026             __IOM uint32_t ACMD  : 2;   /*!< [7..6] Command Type Select                                                */
14027             __IOM uint32_t RSPTP : 3;   /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
14028                                          *   in normal mode, see section 1.4.10, Example of SD_CMD Register
14029                                          *   Setting to select mode/response type.                                     */
14030             __IOM uint32_t CMDTP : 1;   /*!< [11..11] Data Mode (Command Type)                                         */
14031             __IOM uint32_t CMDRW : 1;   /*!< [12..12] Write/Read Mode (enabled when the command with data
14032                                          *   is handled)                                                               */
14033             __IOM uint32_t TRSTP : 1;   /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
14034                                          *   with data is handled)                                                     */
14035             __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
14036                                          *   transfer)                                                                 */
14037             uint32_t : 16;
14038         } SD_CMD_b;
14039     };
14040     __IM uint32_t RESERVED;
14041 
14042     union
14043     {
14044         __IOM uint32_t SD_ARG;          /*!< (@ 0x00000008) SD Command Argument Register                               */
14045 
14046         struct
14047         {
14048             __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument)              */
14049         } SD_ARG_b;
14050     };
14051 
14052     union
14053     {
14054         __IOM uint32_t SD_ARG1;          /*!< (@ 0x0000000C) SD Command Argument Register 1                             */
14055 
14056         struct
14057         {
14058             __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument)           */
14059             uint32_t               : 16;
14060         } SD_ARG1_b;
14061     };
14062 
14063     union
14064     {
14065         __IOM uint32_t SD_STOP;        /*!< (@ 0x00000010) Data Stop Register                                         */
14066 
14067         struct
14068         {
14069             __IOM uint32_t STP : 1;    /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
14070                                         *   CMD12 is issued to halt the transfer through the SD host
14071                                         *   interface.However, if a command sequence is halted because
14072                                         *   of a communications error or timeout, CMD12 is not issued.
14073                                         *   Although continued buffer access is possible even after
14074                                         *   STP has been set to 1, the buffer access error bit (ERR5
14075                                         *   or ERR4) in SD_INFO2 will be set accordingly.- When STP
14076                                         *   has been set to 1 during transfer for single block write,
14077                                         *   the access end flag is set when SD_BUF becomes emp                        */
14078             uint32_t           : 7;
14079             __IOM uint32_t SEC : 1;    /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
14080                                         *   SD_CMD is set as follows to start the command sequence
14081                                         *   while SEC is set to 1, CMD12 is automatically issued to
14082                                         *   stop multi-block transfer with the number of blocks which
14083                                         *   is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
14084                                         *   = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
14085                                         *   automatically issued, multiple block transfer)When the
14086                                         *   command sequence is halted because of a communications
14087                                         *   error or timeout, CMD12 is not automatically i                            */
14088             uint32_t : 23;
14089         } SD_STOP_b;
14090     };
14091 
14092     union
14093     {
14094         __IOM uint32_t SD_SECCNT;          /*!< (@ 0x00000014) Block Count Register                                       */
14095 
14096         struct
14097         {
14098             __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
14099                                             *   of this bit when the CBSY bit in SD_INFO2 is set to 1.                    */
14100         } SD_SECCNT_b;
14101     };
14102 
14103     union
14104     {
14105         __IM uint32_t SD_RSP10;          /*!< (@ 0x00000018) SD Card Response Register 10                               */
14106 
14107         struct
14108         {
14109             __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
14110         } SD_RSP10_b;
14111     };
14112 
14113     union
14114     {
14115         __IM uint32_t SD_RSP1;          /*!< (@ 0x0000001C) SD Card Response Register 1                                */
14116 
14117         struct
14118         {
14119             __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
14120             uint32_t              : 16;
14121         } SD_RSP1_b;
14122     };
14123 
14124     union
14125     {
14126         __IM uint32_t SD_RSP32;          /*!< (@ 0x00000020) SD Card Response Register 32                               */
14127 
14128         struct
14129         {
14130             __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
14131         } SD_RSP32_b;
14132     };
14133 
14134     union
14135     {
14136         __IM uint32_t SD_RSP3;          /*!< (@ 0x00000024) SD Card Response Register 3                                */
14137 
14138         struct
14139         {
14140             __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
14141             uint32_t              : 16;
14142         } SD_RSP3_b;
14143     };
14144 
14145     union
14146     {
14147         __IM uint32_t SD_RSP54;          /*!< (@ 0x00000028) SD Card Response Register 54                               */
14148 
14149         struct
14150         {
14151             __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
14152         } SD_RSP54_b;
14153     };
14154 
14155     union
14156     {
14157         __IM uint32_t SD_RSP5;          /*!< (@ 0x0000002C) SD Card Response Register 5                                */
14158 
14159         struct
14160         {
14161             __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
14162             uint32_t              : 16;
14163         } SD_RSP5_b;
14164     };
14165 
14166     union
14167     {
14168         __IM uint32_t SD_RSP76;          /*!< (@ 0x00000030) SD Card Response Register 76                               */
14169 
14170         struct
14171         {
14172             __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC                           */
14173             uint32_t               : 8;
14174         } SD_RSP76_b;
14175     };
14176 
14177     union
14178     {
14179         __IM uint32_t SD_RSP7;         /*!< (@ 0x00000034) SD Card Response Register 7                                */
14180 
14181         struct
14182         {
14183             __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC                            */
14184             uint32_t              : 24;
14185         } SD_RSP7_b;
14186     };
14187 
14188     union
14189     {
14190         __IOM uint32_t SD_INFO1;        /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1                          */
14191 
14192         struct
14193         {
14194             __IOM uint32_t RSPEND  : 1; /*!< [0..0] Response End Detection                                             */
14195             uint32_t               : 1;
14196             __IOM uint32_t ACEND   : 1; /*!< [2..2] Access End                                                         */
14197             __IOM uint32_t SDCDRM  : 1; /*!< [3..3] SDnCD Card Removal                                                 */
14198             __IOM uint32_t SDCDIN  : 1; /*!< [4..4] SDnCD Card Insertion                                               */
14199             __IM uint32_t  SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state                                          */
14200             uint32_t               : 1;
14201             __IM uint32_t  SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state                                          */
14202             __IOM uint32_t SDD3RM  : 1; /*!< [8..8] SDnDAT3 Card Removal                                               */
14203             __IOM uint32_t SDD3IN  : 1; /*!< [9..9] SDnDAT3 Card Insertion                                             */
14204             __IM uint32_t  SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State                                      */
14205             uint32_t               : 21;
14206         } SD_INFO1_b;
14207     };
14208 
14209     union
14210     {
14211         __IOM uint32_t SD_INFO2;             /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2                          */
14212 
14213         struct
14214         {
14215             __IOM uint32_t CMDE    : 1;      /*!< [0..0] Command Error                                                      */
14216             __IOM uint32_t CRCE    : 1;      /*!< [1..1] CRC Error                                                          */
14217             __IOM uint32_t ENDE    : 1;      /*!< [2..2] END Error                                                          */
14218             __IOM uint32_t DTO     : 1;      /*!< [3..3] Data Timeout                                                       */
14219             __IOM uint32_t ILW     : 1;      /*!< [4..4] SD_BUF Illegal Write Access                                        */
14220             __IOM uint32_t ILR     : 1;      /*!< [5..5] SD_BUF Illegal Read Access                                         */
14221             __IOM uint32_t RSPTO   : 1;      /*!< [6..6] Response Timeout                                                   */
14222             __IM uint32_t  SDD0MON : 1;      /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
14223                                               *   by SD_PORTSEL.                                                            */
14224             __IOM uint32_t BRE          : 1; /*!< [8..8] SD_BUF Read Enable                                                 */
14225             __IOM uint32_t BWE          : 1; /*!< [9..9] SD_BUF Write Enable                                                */
14226             uint32_t                    : 3;
14227             __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
14228                                               *   the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
14229                                               *   bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
14230                                               *   cycles of SDCLK have elapsed after setting of the CBSY
14231                                               *   bit to 0 due to completion of the command sequence.                       */
14232             __IM uint32_t  CBSY : 1;         /*!< [14..14] Command Type Register Busy                                       */
14233             __IOM uint32_t ILA  : 1;         /*!< [15..15] Illegal Access Error                                             */
14234             uint32_t            : 16;
14235         } SD_INFO2_b;
14236     };
14237 
14238     union
14239     {
14240         __IOM uint32_t SD_INFO1_MASK;   /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register                           */
14241 
14242         struct
14243         {
14244             __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask                                */
14245             uint32_t               : 1;
14246             __IOM uint32_t ACENDM  : 1; /*!< [2..2] Access End Interrupt Request Mask                                  */
14247             __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask                          */
14248             __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask                        */
14249             uint32_t               : 3;
14250             __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask                        */
14251             __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask                      */
14252             uint32_t               : 22;
14253         } SD_INFO1_MASK_b;
14254     };
14255 
14256     union
14257     {
14258         __IOM uint32_t SD_INFO2_MASK;  /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register                           */
14259 
14260         struct
14261         {
14262             __IOM uint32_t CMDEM  : 1; /*!< [0..0] Command Error Interrupt Request Mask                               */
14263             __IOM uint32_t CRCEM  : 1; /*!< [1..1] CRC Error Interrupt Request Mask                                   */
14264             __IOM uint32_t ENDEM  : 1; /*!< [2..2] End Bit Error Interrupt Request Mask                               */
14265             __IOM uint32_t DTOM   : 1; /*!< [3..3] Data Timeout Interrupt Request Mask                                */
14266             __IOM uint32_t ILWM   : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask               */
14267             __IOM uint32_t ILRM   : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask                */
14268             __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask                            */
14269             uint32_t              : 1;
14270             __IOM uint32_t BREM   : 1; /*!< [8..8] BRE Interrupt Request Mask                                         */
14271             __IOM uint32_t BWEM   : 1; /*!< [9..9] BWE Interrupt Request Mask                                         */
14272             uint32_t              : 5;
14273             __IOM uint32_t ILAM   : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask                      */
14274             uint32_t              : 16;
14275         } SD_INFO2_MASK_b;
14276     };
14277 
14278     union
14279     {
14280         __IOM uint32_t SD_CLK_CTRL;       /*!< (@ 0x00000048) SD Clock Control Register                                  */
14281 
14282         struct
14283         {
14284             __IOM uint32_t CLKSEL    : 8; /*!< [7..0] SDHI Clock Frequency Select                                        */
14285             __IOM uint32_t CLKEN     : 1; /*!< [8..8] SD/MMC Clock Output Control Enable                                 */
14286             __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable                       */
14287             uint32_t                 : 22;
14288         } SD_CLK_CTRL_b;
14289     };
14290 
14291     union
14292     {
14293         __IOM uint32_t SD_SIZE;        /*!< (@ 0x0000004C) Transfer Data Length Register                              */
14294 
14295         struct
14296         {
14297             __IOM uint32_t LEN : 10;   /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
14298                                         *   and 512 bytes for the transfer of single blocks.In cases
14299                                         *   of multiple block transfer with automatic issuing of CMD12
14300                                         *   (CMD18 and CMD25), the only specifiable transfer data size
14301                                         *   is 512 bytes. Furthermore, in cases of multiple block transfer
14302                                         *   without automatic issuing of CMD12, as well as 512 bytes,
14303                                         *   32, 64, 128, and 256 bytes are specifiable. However, in
14304                                         *   the reading of 32, 64, 128, and 256 bytes for the transfer
14305                                         *   of multiple blocks, this is restricted to mult                            */
14306             uint32_t : 22;
14307         } SD_SIZE_b;
14308     };
14309 
14310     union
14311     {
14312         __IOM uint32_t SD_OPTION;        /*!< (@ 0x00000050) SD Card Access Control Option Register                     */
14313 
14314         struct
14315         {
14316             __IOM uint32_t CTOP     : 4; /*!< [3..0] Card Detect Time Counter                                           */
14317             __IOM uint32_t TOP      : 4; /*!< [7..4] Timeout Counter                                                    */
14318             __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
14319                                           *   timeout, software reset should be executed to terminate
14320                                           *   command sequence.                                                         */
14321             uint32_t              : 4;
14322             __IOM uint32_t WIDTH8 : 1;   /*!< [13..13] Bus Widthsee b15, WIDTH bit                                      */
14323             uint32_t              : 1;
14324             __IOM uint32_t WIDTH  : 1;   /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
14325                                           *   and when the SOFT_RST.SDRST flag is 0.                                    */
14326             uint32_t : 16;
14327         } SD_OPTION_b;
14328     };
14329     __IM uint32_t RESERVED1;
14330 
14331     union
14332     {
14333         __IM uint32_t SD_ERR_STS1;      /*!< (@ 0x00000058) SD Error Status Register 1                                 */
14334 
14335         struct
14336         {
14337             __IM uint32_t CMDE0 : 1;    /*!< [0..0] Command Error 0NOTE: other than a response to a command
14338                                          *   issued within a command sequence                                          */
14339             __IM uint32_t CMDE1 : 1;    /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
14340                                          *   setting a command index in SD_CMD, this is Indicated in
14341                                          *   CMDE0.                                                                    */
14342             __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
14343                                          *   a command issued within a command sequence                                */
14344             __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
14345                                          *   issued by setting a command index in SD_CMD, this is indicated
14346                                          *   in RSPLENE0.                                                              */
14347             __IM uint32_t RDLENE   : 1; /*!< [4..4] Read Data Length Error                                             */
14348             __IM uint32_t CRCLENE  : 1; /*!< [5..5] CRC Status Token Length Error                                      */
14349             uint32_t               : 2;
14350             __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
14351                                          *   command issued within a command sequence                                  */
14352             __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
14353                                          *   by setting a command index in SD_CMD, this is indicated
14354                                          *   in RSPCRCE0.                                                              */
14355             __IM uint32_t RDCRCE : 1;   /*!< [10..10] Read Data CRC Error                                              */
14356             __IM uint32_t CRCTKE : 1;   /*!< [11..11] CRC Status Token Error                                           */
14357             __IM uint32_t CRCTK  : 3;   /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
14358                                          *   value is 010b)                                                            */
14359             uint32_t : 17;
14360         } SD_ERR_STS1_b;
14361     };
14362 
14363     union
14364     {
14365         __IM uint32_t SD_ERR_STS2;      /*!< (@ 0x0000005C) SD Error Status Register 2                                 */
14366 
14367         struct
14368         {
14369             __IM uint32_t RSPTO0   : 1; /*!< [0..0] Response Timeout 0                                                 */
14370             __IM uint32_t RSPTO1   : 1; /*!< [1..1] Response Timeout 1                                                 */
14371             __IM uint32_t BSYTO0   : 1; /*!< [2..2] Busy Timeout 0                                                     */
14372             __IM uint32_t BSYTO1   : 1; /*!< [3..3] Busy Timeout 1                                                     */
14373             __IM uint32_t RDTO     : 1; /*!< [4..4] Read Data Timeout                                                  */
14374             __IM uint32_t CRCTO    : 1; /*!< [5..5] CRC Status Token Timeout                                           */
14375             __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout                                      */
14376             uint32_t               : 25;
14377         } SD_ERR_STS2_b;
14378     };
14379 
14380     union
14381     {
14382         __IOM uint32_t SD_BUF0;         /*!< (@ 0x00000060) SD Buffer Register                                         */
14383 
14384         struct
14385         {
14386             __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
14387                                          *   data is written to this register. When reading from the
14388                                          *   SD card, the read data is read from this register. This
14389                                          *   register is internally connected to two 512-byte buffers.If
14390                                          *   both buffers are not empty when executing multiple block
14391                                          *   read, SD/MMC clock is stopped to suspend receiving data.
14392                                          *   When one of buffers is empty, SD/MMC clock is supplied
14393                                          *   to resume receiving data.                                                 */
14394         } SD_BUF0_b;
14395     };
14396     __IM uint32_t RESERVED2;
14397 
14398     union
14399     {
14400         __IOM uint32_t SDIO_MODE;      /*!< (@ 0x00000068) SDIO Mode Control Register                                 */
14401 
14402         struct
14403         {
14404             __IOM uint32_t INTEN  : 1; /*!< [0..0] SDIO Mode                                                          */
14405             uint32_t              : 1;
14406             __IOM uint32_t RWREQ  : 1; /*!< [2..2] Read Wait Request                                                  */
14407             uint32_t              : 5;
14408             __IOM uint32_t IOABT  : 1; /*!< [8..8] SDIO AbortNOTE: See manual                                         */
14409             __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual                                    */
14410             uint32_t              : 22;
14411         } SDIO_MODE_b;
14412     };
14413 
14414     union
14415     {
14416         __IOM uint32_t SDIO_INFO1;      /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1                             */
14417 
14418         struct
14419         {
14420             __IOM uint32_t IOIRQ   : 1; /*!< [0..0] SDIO Interrupt Status                                              */
14421             uint32_t               : 13;
14422             __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual                              */
14423             __IOM uint32_t EXWT    : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual                                 */
14424             uint32_t               : 16;
14425         } SDIO_INFO1_b;
14426     };
14427 
14428     union
14429     {
14430         __IOM uint32_t SDIO_INFO1_MASK;  /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register                         */
14431 
14432         struct
14433         {
14434             __IOM uint32_t IOIRQM   : 1; /*!< [0..0] IOIRQ Interrupt Mask Control                                       */
14435             uint32_t                : 13;
14436             __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control                           */
14437             __IOM uint32_t EXWTM    : 1; /*!< [15..15] EXWT Interrupt Request Mask Control                              */
14438             uint32_t                : 16;
14439         } SDIO_INFO1_MASK_b;
14440     };
14441     __IM uint32_t RESERVED3[79];
14442 
14443     union
14444     {
14445         __IOM uint32_t SD_DMAEN;       /*!< (@ 0x000001B0) DMA Mode Enable Register                                   */
14446 
14447         struct
14448         {
14449             uint32_t             : 1;
14450             __IOM uint32_t DMAEN : 1;  /*!< [1..1] SD_BUF Read/Write DMA Transfer                                     */
14451             uint32_t             : 30;
14452         } SD_DMAEN_b;
14453     };
14454     __IM uint32_t RESERVED4[3];
14455 
14456     union
14457     {
14458         __IOM uint32_t SOFT_RST;       /*!< (@ 0x000001C0) Software Reset Register                                    */
14459 
14460         struct
14461         {
14462             __IOM uint32_t SDRST : 1;  /*!< [0..0] Software Reset of SD I/F Unit                                      */
14463             uint32_t             : 31;
14464         } SOFT_RST_b;
14465     };
14466     __IM uint32_t RESERVED5[2];
14467 
14468     union
14469     {
14470         __IOM uint32_t SDIF_MODE;      /*!< (@ 0x000001CC) SD Interface Mode Setting Register                         */
14471 
14472         struct
14473         {
14474             uint32_t               : 8;
14475             __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands)                             */
14476             uint32_t               : 23;
14477         } SDIF_MODE_b;
14478     };
14479     __IM uint32_t RESERVED6[4];
14480 
14481     union
14482     {
14483         __IOM uint32_t EXT_SWAP;       /*!< (@ 0x000001E0) Swap Control Register                                      */
14484 
14485         struct
14486         {
14487             uint32_t             : 6;
14488             __IOM uint32_t BWSWP : 1;  /*!< [6..6] SD_BUF0 Swap Write                                                 */
14489             __IOM uint32_t BRSWP : 1;  /*!< [7..7] SD_BUF0 Swap Read                                                  */
14490             uint32_t             : 24;
14491         } EXT_SWAP_b;
14492     };
14493 } R_SDHI0_Type;                        /*!< Size = 484 (0x1e4)                                                        */
14494 
14495 /* =========================================================================================================================== */
14496 /* ================                                          R_SPI0                                           ================ */
14497 /* =========================================================================================================================== */
14498 
14499 /**
14500  * @brief Serial Peripheral Interface (R_SPI0)
14501  */
14502 
14503 typedef struct                         /*!< (@ 0x4035C000) R_SPI0 Structure                                           */
14504 {
14505     union
14506     {
14507         __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
14508 
14509         struct
14510         {
14511             __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
14512             __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
14513             __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
14514             __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
14515             __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
14516             __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
14517             __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
14518             __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
14519         } SPCR_b;
14520     };
14521 
14522     union
14523     {
14524         __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
14525 
14526         struct
14527         {
14528             __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
14529             __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
14530             __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
14531             __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
14532             __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
14533             __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
14534             __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
14535             __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
14536         } SSLP_b;
14537     };
14538 
14539     union
14540     {
14541         __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
14542 
14543         struct
14544         {
14545             __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
14546             __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
14547             uint8_t             : 2;
14548             __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
14549             __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
14550             uint8_t             : 2;
14551         } SPPCR_b;
14552     };
14553 
14554     union
14555     {
14556         __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
14557 
14558         struct
14559         {
14560             __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
14561             __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
14562             __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
14563             __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
14564             __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
14565             __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
14566             __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
14567             __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
14568         } SPSR_b;
14569     };
14570 
14571     union
14572     {
14573         __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
14574         __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
14575         __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
14576     };
14577 
14578     union
14579     {
14580         __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
14581 
14582         struct
14583         {
14584             __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
14585                                         *   the SPCMD0 to SPCMD07 registers are to be referenced is
14586                                         *   changed in accordance with the sequence length that is
14587                                         *   set in these bits. The relationship among the setting of
14588                                         *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
14589                                         *   referenced by the RSPI is shown above. However, the RSPI
14590                                         *   in slave mode always references SPCMD0.                                   */
14591             uint8_t : 5;
14592         } SPSCR_b;
14593     };
14594 
14595     union
14596     {
14597         __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
14598 
14599         struct
14600         {
14601             __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
14602             uint8_t            : 1;
14603             __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
14604             uint8_t            : 1;
14605         } SPSSR_b;
14606     };
14607 
14608     union
14609     {
14610         __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
14611 
14612         struct
14613         {
14614             __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
14615         } SPBR_b;
14616     };
14617 
14618     union
14619     {
14620         __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
14621 
14622         struct
14623         {
14624             __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
14625             __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
14626             __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
14627             __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
14628             __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
14629             uint8_t              : 1;
14630         } SPDCR_b;
14631     };
14632 
14633     union
14634     {
14635         __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
14636 
14637         struct
14638         {
14639             __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
14640             uint8_t             : 5;
14641         } SPCKD_b;
14642     };
14643 
14644     union
14645     {
14646         __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
14647 
14648         struct
14649         {
14650             __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
14651             uint8_t             : 5;
14652         } SSLND_b;
14653     };
14654 
14655     union
14656     {
14657         __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
14658 
14659         struct
14660         {
14661             __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
14662             uint8_t             : 5;
14663         } SPND_b;
14664     };
14665 
14666     union
14667     {
14668         __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
14669 
14670         struct
14671         {
14672             __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
14673             __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
14674             __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
14675             __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
14676             __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
14677             __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
14678         } SPCR2_b;
14679     };
14680 
14681     union
14682     {
14683         __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
14684 
14685         struct
14686         {
14687             __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
14688             __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
14689             __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
14690             __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
14691             __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
14692             __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
14693             __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
14694             __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
14695             __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
14696             __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
14697         } SPCMD_b[8];
14698     };
14699 
14700     union
14701     {
14702         __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
14703 
14704         struct
14705         {
14706             __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
14707             __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
14708             uint8_t            : 6;
14709         } SPDCR2_b;
14710     };
14711 
14712     union
14713     {
14714         __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
14715 
14716         struct
14717         {
14718             __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
14719             __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
14720             uint8_t              : 2;
14721             __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
14722             uint8_t              : 3;
14723         } SPCR3_b;
14724     };
14725     __IM uint16_t RESERVED;
14726     __IM uint32_t RESERVED1[6];
14727     __IM uint16_t RESERVED2;
14728 
14729     union
14730     {
14731         __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
14732 
14733         struct
14734         {
14735             uint16_t              : 4;
14736             __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
14737             uint16_t              : 3;
14738             __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
14739             uint16_t              : 1;
14740             __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
14741         } SPPR_b;
14742     };
14743 } R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
14744 
14745 /* =========================================================================================================================== */
14746 /* ================                                          R_SRAM                                           ================ */
14747 /* =========================================================================================================================== */
14748 
14749 /**
14750  * @brief SRAM (R_SRAM)
14751  */
14752 
14753 typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
14754 {
14755     union
14756     {
14757         __IOM uint16_t SRAMPRCR;       /*!< (@ 0x00000000) SRAM Protection Control Register for Secure                */
14758 
14759         struct
14760         {
14761             __IOM uint16_t PR : 1;     /*!< [0..0] Register Write Control                                             */
14762             uint16_t          : 7;
14763             __OM uint16_t KW  : 8;     /*!< [15..8] Write Key Code                                                    */
14764         } SRAMPRCR_b;
14765     };
14766     __IM uint16_t RESERVED;
14767 
14768     union
14769     {
14770         __IOM uint16_t SRAMPRCR_NS;    /*!< (@ 0x00000004) SRAM Protection Control Register for Non-Secure            */
14771 
14772         struct
14773         {
14774             __IOM uint16_t PR : 1;     /*!< [0..0] Register Write Control                                             */
14775             uint16_t          : 7;
14776             __OM uint16_t KW  : 8;     /*!< [15..8] Write Key Code                                                    */
14777         } SRAMPRCR_NS_b;
14778     };
14779     __IM uint16_t RESERVED1;
14780 
14781     union
14782     {
14783         __IOM uint8_t SRAMWTSC;        /*!< (@ 0x00000008) SRAM Wait State Control Register                           */
14784 
14785         struct
14786         {
14787             __IOM uint8_t WTEN : 1;    /*!< [0..0] Wait enable                                                        */
14788             uint8_t            : 7;
14789         } SRAMWTSC_b;
14790     };
14791     __IM uint8_t  RESERVED2;
14792     __IM uint16_t RESERVED3;
14793     __IM uint32_t RESERVED4;
14794 
14795     union
14796     {
14797         __IOM uint8_t SRAMCR0;         /*!< (@ 0x00000010) SRAM Control Register 0                                    */
14798 
14799         struct
14800         {
14801             __IOM uint8_t OAD     : 1; /*!< [0..0] Operation after detection for 1-bit ECC error detection            */
14802             uint8_t               : 1;
14803             __IOM uint8_t ECCMOD  : 2; /*!< [3..2] ECC Operating Mode Select                                          */
14804             __IOM uint8_t E1STSEN : 1; /*!< [4..4] ECC 1-Bit Error Information Update Enable                          */
14805             uint8_t               : 2;
14806             __IOM uint8_t TSTBYP  : 1; /*!< [7..7] ECC Test Enable / ECC Bypass Select                                */
14807         } SRAMCR0_b;
14808     };
14809     __IM uint8_t  RESERVED5;
14810     __IM uint16_t RESERVED6;
14811 
14812     union
14813     {
14814         __IOM uint8_t SRAMCR1;         /*!< (@ 0x00000014) SRAM Control Register 1                                    */
14815 
14816         struct
14817         {
14818             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after detection for parity error detection               */
14819             uint8_t           : 7;
14820         } SRAMCR1_b;
14821     };
14822     __IM uint8_t  RESERVED7;
14823     __IM uint16_t RESERVED8;
14824     __IM uint32_t RESERVED9[6];
14825 
14826     union
14827     {
14828         __IOM uint8_t SRAMECCRGN0;     /*!< (@ 0x00000030) SRAM0 ECC Region Control Register                          */
14829 
14830         struct
14831         {
14832             __IOM uint8_t ECCRGN : 2;  /*!< [1..0] ECC Region                                                         */
14833             uint8_t              : 6;
14834         } SRAMECCRGN0_b;
14835     };
14836     __IM uint8_t  RESERVED10;
14837     __IM uint16_t RESERVED11;
14838     __IM uint32_t RESERVED12[3];
14839 
14840     union
14841     {
14842         __IM uint16_t SRAMESR;         /*!< (@ 0x00000040) SRAM Error Status Register                                 */
14843 
14844         struct
14845         {
14846             __IM uint16_t ERR00 : 1;   /*!< [0..0] SRAM0 1-bit ECC Error Status                                       */
14847             __IM uint16_t ERR01 : 1;   /*!< [1..1] SRAM0 2-bit ECC Error Status                                       */
14848             __IM uint16_t ERR1  : 1;   /*!< [2..2] SRAM1 Parity Error Status                                          */
14849             uint16_t            : 11;
14850             __IM uint16_t ERRS  : 1;   /*!< [14..14] Standby SRAM Parity Error status                                 */
14851             uint16_t            : 1;
14852         } SRAMESR_b;
14853     };
14854     __IM uint16_t RESERVED13;
14855     __IM uint32_t RESERVED14;
14856 
14857     union
14858     {
14859         __IOM uint16_t SRAMESCLR;      /*!< (@ 0x00000048) SRAM Error Status Clear Register                           */
14860 
14861         struct
14862         {
14863             __IOM uint16_t CLR00 : 1;  /*!< [0..0] SRAM0 1-bit ECC Error Status Clear                                 */
14864             __IOM uint16_t CLR01 : 1;  /*!< [1..1] SRAM0 2-bit ECC Error Status Clear                                 */
14865             __IOM uint16_t CLR1  : 1;  /*!< [2..2] SRAM1 Parity Error Status Clear                                    */
14866             uint16_t             : 11;
14867             __IOM uint16_t CLRS  : 1;  /*!< [14..14] Standby SRAM Parity Error Status Clear                           */
14868             uint16_t             : 1;
14869         } SRAMESCLR_b;
14870     };
14871     __IM uint16_t RESERVED15;
14872     __IM uint32_t RESERVED16;
14873 
14874     union
14875     {
14876         __IM uint32_t SRAMEAR0;        /*!< (@ 0x00000050) SRAM Error Address Register                                */
14877 
14878         struct
14879         {
14880             uint32_t         : 3;
14881             __IM uint32_t EA : 17;     /*!< [19..3] SRAM Error Address                                                */
14882             uint32_t         : 12;
14883         } SRAMEAR0_b;
14884     };
14885 
14886     union
14887     {
14888         __IM uint32_t SRAMEAR1;        /*!< (@ 0x00000054) SRAM Error Address Register                                */
14889 
14890         struct
14891         {
14892             uint32_t         : 3;
14893             __IM uint32_t EA : 17;     /*!< [19..3] SRAM Error Address                                                */
14894             uint32_t         : 12;
14895         } SRAMEAR1_b;
14896     };
14897 
14898     union
14899     {
14900         __IM uint32_t SRAMEAR2;        /*!< (@ 0x00000058) SRAM Error Address Register                                */
14901 
14902         struct
14903         {
14904             uint32_t         : 3;
14905             __IM uint32_t EA : 17;     /*!< [19..3] SRAM Error Address                                                */
14906             uint32_t         : 12;
14907         } SRAMEAR2_b;
14908     };
14909     __IM uint32_t RESERVED17[45];
14910 
14911     union
14912     {
14913         __IOM uint8_t STBRAMCR;        /*!< (@ 0x00000110) Standby SRAM Control Register                              */
14914 
14915         struct
14916         {
14917             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after detection                                          */
14918             uint8_t           : 7;
14919         } STBRAMCR_b;
14920     };
14921     __IM uint8_t  RESERVED18;
14922     __IM uint16_t RESERVED19;
14923     __IM uint32_t RESERVED20[15];
14924 
14925     union
14926     {
14927         __IM uint32_t STBRAMEAR;       /*!< (@ 0x00000150) Standby SRAM Error Address Register                        */
14928 
14929         struct
14930         {
14931             uint32_t         : 2;
14932             __IM uint32_t EA : 8;      /*!< [9..2] SRAM Error Address                                                 */
14933             uint32_t         : 22;
14934         } STBRAMEAR_b;
14935     };
14936 } R_SRAM_Type;                         /*!< Size = 340 (0x154)                                                        */
14937 
14938 /* =========================================================================================================================== */
14939 /* ================                                          R_SSI0                                           ================ */
14940 /* =========================================================================================================================== */
14941 
14942 /**
14943  * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
14944  */
14945 
14946 typedef struct                         /*!< (@ 0x4025D000) R_SSI0 Structure                                           */
14947 {
14948     union
14949     {
14950         __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
14951 
14952         struct
14953         {
14954             __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
14955             __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
14956             uint32_t            : 1;
14957             __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
14958                                         *   of outputting serial data is rewritten to 0 but data transmission
14959                                         *   is not stopped. Write dummy data to the SSIFTDR not to
14960                                         *   generate a transmit underflow because the number of data
14961                                         *   in the transmit FIFO is decreasing.                                       */
14962             __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
14963             __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
14964             __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
14965             __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
14966             __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
14967             __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
14968             __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
14969             __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
14970                                         *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
14971                                         *   are prohibited.                                                           */
14972             uint32_t           : 1;
14973             __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
14974                                         *   bit clock frequency/2 fs.                                                 */
14975             __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
14976             __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
14977             uint32_t             : 1;
14978             __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
14979             __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
14980             __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
14981             __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
14982             __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
14983             __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
14984             uint32_t             : 1;
14985         } SSICR_b;
14986     };
14987 
14988     union
14989     {
14990         __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
14991 
14992         struct
14993         {
14994             __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
14995             __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
14996             __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
14997             __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
14998             __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
14999             uint32_t             : 18;
15000             __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
15001             __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
15002                                         *   Writable only to clear the flag. Confirm the value is 1
15003                                         *   and then write 0.                                                         */
15004             __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
15005                                         *   Writable only to clear the flag. Confirm the value is 1
15006                                         *   and then write 0.                                                         */
15007             __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
15008                                         *   Writable only to clear the flag. Confirm the value is 1
15009                                         *   and then write 0.                                                         */
15010             __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
15011                                         *   Writable only to clear the flag. Confirm the value is 1
15012                                         *   and then write 0.                                                         */
15013             uint32_t : 2;
15014         } SSISR_b;
15015     };
15016     __IM uint32_t RESERVED[2];
15017 
15018     union
15019     {
15020         __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
15021 
15022         struct
15023         {
15024             __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
15025             __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
15026             __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
15027                                         *   clearing either the RDF flag (see the description of the
15028                                         *   RDF bit for details) or RIE bit.                                          */
15029             __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
15030                                         *   clearing either the TDE flag (see the description of the
15031                                         *   TDE bit for details) or TIE bit.                                          */
15032             __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
15033             __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
15034                                         *   are the number of empty stages in SSIFTDR at which the
15035                                         *   TDE flag is set.                                                          */
15036             uint32_t              : 3;
15037             __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
15038             uint32_t              : 4;
15039             __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
15040             uint32_t              : 14;
15041             __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
15042         } SSIFCR_b;
15043     };
15044 
15045     union
15046     {
15047         __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
15048 
15049         struct
15050         {
15051             __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
15052                                         *   is a 32-byte FIFO register, the maximum number of data
15053                                         *   bytes that can be read from it while the RDF flag is 1
15054                                         *   is indicated in the RDC[3:0] flags. If reading data from
15055                                         *   the SSIFRDR register is continued after all the data is
15056                                         *   read, undefined values will be read.                                      */
15057             uint32_t          : 7;
15058             __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
15059                                         *   units stored in SSIFRDR)                                                  */
15060             uint32_t           : 2;
15061             __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
15062                                         *   is a 32-byte FIFO register, the maximum number of bytes
15063                                         *   that can be written to it while the TDE flag is 1 is 8
15064                                         *   - TDC[3:0]. If writing data to the SSIFTDR register is
15065                                         *   continued after all the data is written, writing will be
15066                                         *   invalid and an overflow occurs.                                           */
15067             uint32_t          : 7;
15068             __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
15069                                         *   data units stored in SSIFTDR)                                             */
15070             uint32_t : 2;
15071         } SSIFSR_b;
15072     };
15073 
15074     union
15075     {
15076         union
15077         {
15078             __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
15079 
15080             struct
15081             {
15082                 __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
15083                                              *   eight stages of 32-bit registers for storing data to be
15084                                              *   serially transmitted. NOTE: that when the SSIFTDR register
15085                                              *   is full of data (32 bytes), the next data cannot be written
15086                                              *   to it. If writing is attempted, it will be ignored and
15087                                              *   an overflow occurs.                                                       */
15088             } SSIFTDR_b;
15089         };
15090         __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
15091         __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
15092     };
15093 
15094     union
15095     {
15096         union
15097         {
15098             __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
15099 
15100             struct
15101             {
15102                 __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
15103                                              *   stages of 32-bit registers for storing serially received
15104                                              *   data.                                                                     */
15105             } SSIFRDR_b;
15106         };
15107         __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
15108         __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
15109     };
15110 
15111     union
15112     {
15113         __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
15114 
15115         struct
15116         {
15117             __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
15118             uint32_t               : 6;
15119             __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
15120             __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
15121                                          *   Idle Status                                                               */
15122             uint32_t : 22;
15123         } SSIOFR_b;
15124     };
15125 
15126     union
15127     {
15128         __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
15129 
15130         struct
15131         {
15132             __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
15133             uint32_t            : 3;
15134             __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
15135             uint32_t            : 19;
15136         } SSISCR_b;
15137     };
15138 } R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
15139 
15140 /* =========================================================================================================================== */
15141 /* ================                                         R_SYSTEM                                          ================ */
15142 /* =========================================================================================================================== */
15143 
15144 /**
15145  * @brief System Pins (R_SYSTEM)
15146  */
15147 
15148 typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
15149 {
15150     __IM uint32_t RESERVED[3];
15151 
15152     union
15153     {
15154         __IOM uint8_t SBYCR;           /*!< (@ 0x0000000C) Standby Control Register                                   */
15155 
15156         struct
15157         {
15158             uint8_t           : 6;
15159             __IOM uint8_t OPE : 1;     /*!< [6..6] Output Port Enable                                                 */
15160             uint8_t           : 1;
15161         } SBYCR_b;
15162     };
15163     __IM uint8_t RESERVED1;
15164 
15165     union
15166     {
15167         __IOM uint8_t SSCR2;           /*!< (@ 0x0000000E) Software Standby Control Register 2                        */
15168 
15169         struct
15170         {
15171             __IM uint8_t SS1RSF : 1;   /*!< [0..0] Software Standby 1 regulator status flag                           */
15172             uint8_t             : 7;
15173         } SSCR2_b;
15174     };
15175     __IM uint8_t RESERVED2;
15176 
15177     union
15178     {
15179         __IOM uint8_t FLSCR;           /*!< (@ 0x00000010) Flash Standby Control Register                             */
15180 
15181         struct
15182         {
15183             __IOM uint8_t FLSWCF : 1;  /*!< [0..0] Flash Stabilization wait completion flag                           */
15184             uint8_t              : 7;
15185         } FLSCR_b;
15186     };
15187     __IM uint8_t  RESERVED3;
15188     __IM uint16_t RESERVED4;
15189     __IM uint32_t RESERVED5[2];
15190 
15191     union
15192     {
15193         __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
15194 
15195         struct
15196         {
15197             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
15198             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
15199             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
15200             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
15201             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
15202             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
15203             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
15204             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
15205             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
15206             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
15207             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
15208                                          *   usage.                                                                    */
15209             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
15210                                          *   usage.                                                                    */
15211             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
15212                                          *   usage.                                                                    */
15213             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
15214                                          *   usage.                                                                    */
15215             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
15216                                          *   usage.                                                                    */
15217             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
15218                                          *   usage.                                                                    */
15219             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
15220                                          *   usage.                                                                    */
15221             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
15222                                          *   usage.                                                                    */
15223             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
15224                                          *   usage.                                                                    */
15225             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
15226                                          *   usage.                                                                    */
15227             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
15228                                          *   usage.                                                                    */
15229             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
15230                                          *   usage.                                                                    */
15231             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
15232                                          *   usage.                                                                    */
15233             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
15234                                          *   usage.                                                                    */
15235             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
15236                                          *   usage.                                                                    */
15237             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
15238                                          *   usage.                                                                    */
15239             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
15240                                          *   usage.                                                                    */
15241             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
15242                                          *   usage.                                                                    */
15243             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
15244                                          *   usage.                                                                    */
15245             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
15246                                          *   usage.                                                                    */
15247             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
15248                                          *   usage.                                                                    */
15249             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
15250                                          *   usage.                                                                    */
15251         } MSTPCRA_b;
15252     };
15253 
15254     union
15255     {
15256         __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
15257 
15258         struct
15259         {
15260             __IOM uint32_t PCKD : 4;   /*!< [3..0] Peripheral Module Clock D (PCLKD) Select                           */
15261             __IOM uint32_t PCKC : 4;   /*!< [7..4] Peripheral Module Clock C (PCLKC) Select                           */
15262             __IOM uint32_t PCKB : 4;   /*!< [11..8] Peripheral Module Clock B (PCLKB) Select                          */
15263             __IOM uint32_t PCKA : 4;   /*!< [15..12] Peripheral Module Clock A (PCLKA) Select                         */
15264             __IOM uint32_t BCK  : 4;   /*!< [19..16] External Bus Clock (BCLK) Select                                 */
15265             __IOM uint32_t PCKE : 4;   /*!< [23..20] Peripheral Module Clock E (PCLKE) Select                         */
15266             __IOM uint32_t ICK  : 4;   /*!< [27..24] System Clock (ICLK) Select                                       */
15267             __IOM uint32_t FCK  : 4;   /*!< [31..28] Flash IF Clock (FCLK) Select                                     */
15268         } SCKDIVCR_b;
15269     };
15270 
15271     union
15272     {
15273         __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
15274 
15275         struct
15276         {
15277             __IOM uint8_t CPUCK : 4;   /*!< [3..0] CPU Clock (CPUCLK) Select                                          */
15278             uint8_t             : 4;
15279         } SCKDIVCR2_b;
15280     };
15281     __IM uint8_t RESERVED6;
15282 
15283     union
15284     {
15285         __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
15286 
15287         struct
15288         {
15289             __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
15290             uint8_t             : 5;
15291         } SCKSCR_b;
15292     };
15293     __IM uint8_t RESERVED7;
15294 
15295     union
15296     {
15297         __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
15298 
15299         struct
15300         {
15301             __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL1 Input Frequency Division Ratio Select                         */
15302             uint16_t                : 2;
15303             __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL1 Clock Source Select                                           */
15304             uint16_t                : 1;
15305             __IOM uint16_t PLLMULNF : 2; /*!< [7..6] PLL1 Frequency Multiplication Fractional Factor Select             */
15306             __IOM uint16_t PLLMUL   : 8; /*!< [15..8] PLL1 Frequency Multiplication Factor Select                       */
15307         } PLLCCR_b;
15308     };
15309 
15310     union
15311     {
15312         __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
15313 
15314         struct
15315         {
15316             __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
15317             uint8_t              : 7;
15318         } PLLCR_b;
15319     };
15320     __IM uint8_t  RESERVED8;
15321     __IM uint32_t RESERVED9;
15322 
15323     union
15324     {
15325         __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
15326 
15327         struct
15328         {
15329             __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
15330             uint8_t               : 7;
15331         } BCKCR_b;
15332     };
15333     __IM uint8_t RESERVED10;
15334 
15335     union
15336     {
15337         __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
15338 
15339         struct
15340         {
15341             __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
15342             uint8_t             : 7;
15343         } MOSCCR_b;
15344     };
15345     __IM uint8_t  RESERVED11;
15346     __IM uint16_t RESERVED12;
15347 
15348     union
15349     {
15350         __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
15351 
15352         struct
15353         {
15354             __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
15355             uint8_t             : 7;
15356         } HOCOCR_b;
15357     };
15358     __IM uint8_t RESERVED13;
15359 
15360     union
15361     {
15362         __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
15363 
15364         struct
15365         {
15366             __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
15367             uint8_t             : 7;
15368         } MOCOCR_b;
15369     };
15370 
15371     union
15372     {
15373         __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
15374 
15375         struct
15376         {
15377             __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
15378             uint8_t             : 7;
15379         } FLLCR1_b;
15380     };
15381 
15382     union
15383     {
15384         __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
15385 
15386         struct
15387         {
15388             __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication Control                                        */
15389             uint16_t               : 5;
15390         } FLLCR2_b;
15391     };
15392 
15393     union
15394     {
15395         __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
15396 
15397         struct
15398         {
15399             __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
15400                                         *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
15401                                         *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
15402             uint8_t             : 2;
15403             __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
15404             uint8_t             : 1;
15405             __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL1 Clock Oscillation Stabilization Flag                          */
15406             __IM uint8_t PLL2SF : 1;   /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag                          */
15407             uint8_t             : 1;
15408         } OSCSF_b;
15409     };
15410     __IM uint8_t RESERVED14;
15411 
15412     union
15413     {
15414         __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
15415 
15416         struct
15417         {
15418             uint8_t              : 4;
15419             __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
15420             __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
15421         } CKOCR_b;
15422     };
15423 
15424     union
15425     {
15426         __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
15427 
15428         struct
15429         {
15430             __IOM uint8_t TRCK    : 4; /*!< [3..0] Trace Clock operating frequency select                             */
15431             __IOM uint8_t TRCKSEL : 1; /*!< [4..4] Trace Clock source select                                          */
15432             uint8_t               : 2;
15433             __IOM uint8_t TRCKEN  : 1; /*!< [7..7] Trace Clock operating Enable                                       */
15434         } TRCKCR_b;
15435     };
15436 
15437     union
15438     {
15439         __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
15440 
15441         struct
15442         {
15443             __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
15444             uint8_t              : 6;
15445             __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
15446         } OSTDCR_b;
15447     };
15448 
15449     union
15450     {
15451         __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
15452 
15453         struct
15454         {
15455             __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
15456             uint8_t             : 7;
15457         } OSTDSR_b;
15458     };
15459     __IM uint8_t RESERVED15;
15460 
15461     union
15462     {
15463         __IM uint8_t OSCMONR;          /*!< (@ 0x00000043) Oscillator Monitor Register                                */
15464 
15465         struct
15466         {
15467             uint8_t              : 1;
15468             __IM uint8_t MOCOMON : 1;  /*!< [1..1] MOCO operation monitor                                             */
15469             __IM uint8_t LOCOMON : 1;  /*!< [2..2] LOCO operation monitor                                             */
15470             uint8_t              : 5;
15471         } OSCMONR_b;
15472     };
15473     __IM uint32_t RESERVED16;
15474 
15475     union
15476     {
15477         __IOM uint16_t PLL2CCR;           /*!< (@ 0x00000048) PLL2 Clock Control Register                                */
15478 
15479         struct
15480         {
15481             __IOM uint16_t PL2IDIV   : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select                         */
15482             uint16_t                 : 2;
15483             __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
15484             uint16_t                 : 1;
15485             __IOM uint16_t PLL2MULNF : 2; /*!< [7..6] PLL2 Frequency Multiplication Fractional Factor Select             */
15486             __IOM uint16_t PLL2MUL   : 8; /*!< [15..8] PLL2 Frequency Multiplication Factor Select                       */
15487         } PLL2CCR_b;
15488     };
15489 
15490     union
15491     {
15492         __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
15493 
15494         struct
15495         {
15496             __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
15497             uint8_t               : 7;
15498         } PLL2CR_b;
15499     };
15500     __IM uint8_t RESERVED17;
15501 
15502     union
15503     {
15504         __IOM uint16_t PLLCCR2;         /*!< (@ 0x0000004C) PLL Clock Control Register 2                               */
15505 
15506         struct
15507         {
15508             __IOM uint16_t PLODIVP : 4; /*!< [3..0] PLL1 Output Frequency Division Ratio Select for output
15509                                          *   clock P                                                                   */
15510             __IOM uint16_t PLODIVQ : 4; /*!< [7..4] PLL1 Output Frequency Division Ratio Select for output
15511                                          *   clock Q                                                                   */
15512             __IOM uint16_t PLODIVR : 4; /*!< [11..8] PLL1 Output Frequency Division Ratio Select for output
15513                                          *   clock R                                                                   */
15514             uint16_t : 4;
15515         } PLLCCR2_b;
15516     };
15517 
15518     union
15519     {
15520         __IOM uint16_t PLL2CCR2;         /*!< (@ 0x0000004E) PLL2 Clock Control Register 2                              */
15521 
15522         struct
15523         {
15524             __IOM uint16_t PL2ODIVP : 4; /*!< [3..0] PLL2 Output Frequency Division Ratio Select for output
15525                                           *   clock P                                                                   */
15526             __IOM uint16_t PL2ODIVQ : 4; /*!< [7..4] PLL2 Output Frequency Division Ratio Select for output
15527                                           *   clock Q                                                                   */
15528             __IOM uint16_t PL2ODIVR : 4; /*!< [11..8] PLL2 Output Frequency Division Ratio Select for output
15529                                           *   clock R                                                                   */
15530             uint16_t : 4;
15531         } PLL2CCR2_b;
15532     };
15533     __IM uint16_t RESERVED18;
15534 
15535     union
15536     {
15537         __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
15538 
15539         struct
15540         {
15541             __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
15542             uint8_t               : 7;
15543         } EBCKOCR_b;
15544     };
15545 
15546     union
15547     {
15548         __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
15549 
15550         struct
15551         {
15552             __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
15553             uint8_t               : 7;
15554         } SDCKOCR_b;
15555     };
15556 
15557     union
15558     {
15559         __IOM uint8_t SCICKDIVCR;      /*!< (@ 0x00000054) SCI clock Division control register                        */
15560 
15561         struct
15562         {
15563             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
15564             uint8_t             : 5;
15565         } SCICKDIVCR_b;
15566     };
15567 
15568     union
15569     {
15570         __IOM uint8_t SCICKCR;          /*!< (@ 0x00000055) SCI clock control register                                 */
15571 
15572         struct
15573         {
15574             __IOM uint8_t SCICKSEL : 4; /*!< [3..0] Clock Source Select                                                */
15575             uint8_t                : 2;
15576             __IOM uint8_t CKSREQ   : 1; /*!< [6..6] Clock Switching Request                                            */
15577             __IM uint8_t  CKSRDY   : 1; /*!< [7..7] Clock Switching Ready state flag                                   */
15578         } SCICKCR_b;
15579     };
15580 
15581     union
15582     {
15583         __IOM uint8_t SPICKDIVCR;      /*!< (@ 0x00000056) SPI clock Division control register                        */
15584 
15585         struct
15586         {
15587             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
15588             uint8_t             : 5;
15589         } SPICKDIVCR_b;
15590     };
15591 
15592     union
15593     {
15594         __IOM uint8_t SPICKCR;         /*!< (@ 0x00000057) SPI clock control register                                 */
15595 
15596         struct
15597         {
15598             __IOM uint8_t CKSEL  : 4;  /*!< [3..0] Clock Source Select                                                */
15599             uint8_t              : 2;
15600             __IOM uint8_t CKSREQ : 1;  /*!< [6..6] Clock Switching Request                                            */
15601             __IM uint8_t  CKSRDY : 1;  /*!< [7..7] Clock Switching Ready state flag                                   */
15602         } SPICKCR_b;
15603     };
15604     __IM uint16_t RESERVED19;
15605 
15606     union
15607     {
15608         __IOM uint8_t ADCCKDIVCR;      /*!< (@ 0x0000005A) ADC clock Division control register                        */
15609 
15610         struct
15611         {
15612             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
15613             uint8_t             : 5;
15614         } ADCCKDIVCR_b;
15615     };
15616 
15617     union
15618     {
15619         __IOM uint8_t ADCCKCR;         /*!< (@ 0x0000005B) ADC clock control register                                 */
15620 
15621         struct
15622         {
15623             __IOM uint8_t CKSEL  : 4;  /*!< [3..0] Clock Source Select                                                */
15624             uint8_t              : 2;
15625             __IOM uint8_t CKSREQ : 1;  /*!< [6..6] Clock Switching Request                                            */
15626             __IM uint8_t  CKSRDY : 1;  /*!< [7..7] Clock Switching Ready state flag                                   */
15627         } ADCCKCR_b;
15628     };
15629 
15630     union
15631     {
15632         __IOM uint8_t GPTCKDIVCR;      /*!< (@ 0x0000005C) GPT clock Division control register                        */
15633 
15634         struct
15635         {
15636             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
15637             uint8_t             : 5;
15638         } GPTCKDIVCR_b;
15639     };
15640 
15641     union
15642     {
15643         __IOM uint8_t GPTCKCR;         /*!< (@ 0x0000005D) GPT clock control register                                 */
15644 
15645         struct
15646         {
15647             __IOM uint8_t CKSEL  : 4;  /*!< [3..0] Clock Source Select                                                */
15648             uint8_t              : 2;
15649             __IOM uint8_t CKSREQ : 1;  /*!< [6..6] Clock Switching Request                                            */
15650             __IM uint8_t  CKSRDY : 1;  /*!< [7..7] Clock Switching Ready state flag                                   */
15651         } GPTCKCR_b;
15652     };
15653 
15654     union
15655     {
15656         __IOM uint8_t LCDCKDIVCR;      /*!< (@ 0x0000005E) LCD clock Division control register                        */
15657 
15658         struct
15659         {
15660             __IOM uint8_t CKDIV : 3;   /*!< [2..0] Clock Division Select                                              */
15661             uint8_t             : 5;
15662         } LCDCKDIVCR_b;
15663     };
15664 
15665     union
15666     {
15667         __IOM uint8_t LCDCKCR;         /*!< (@ 0x0000005F) LCD clock control register                                 */
15668 
15669         struct
15670         {
15671             __IOM uint8_t CKSEL  : 4;  /*!< [3..0] Clock Source Select                                                */
15672             uint8_t              : 2;
15673             __IOM uint8_t CKSREQ : 1;  /*!< [6..6] Clock Switching Request                                            */
15674             __IM uint8_t  CKSRDY : 1;  /*!< [7..7] Clock Switching Ready state flag                                   */
15675         } LCDCKCR_b;
15676     };
15677     __IM uint8_t RESERVED20;
15678 
15679     union
15680     {
15681         __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
15682 
15683         struct
15684         {
15685             __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
15686                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
15687                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
15688                                          +126 0111_1111 : +127These bits are added to original MOCO
15689                                          *   trimming bits                                                             */
15690         } MOCOUTCR_b;
15691     };
15692 
15693     union
15694     {
15695         __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
15696 
15697         struct
15698         {
15699             __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
15700                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
15701                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
15702                                          +126 0111_1111 : +127These bits are added to original HOCO
15703                                          *   trimming bits                                                             */
15704         } HOCOUTCR_b;
15705     };
15706     __IM uint8_t  RESERVED21;
15707     __IM uint32_t RESERVED22[2];
15708 
15709     union
15710     {
15711         __IOM uint8_t USBCKDIVCR;       /*!< (@ 0x0000006C) USB clock Division control register                        */
15712 
15713         struct
15714         {
15715             __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB clock (USBCLK) Division Select                                 */
15716             uint8_t                : 5;
15717         } USBCKDIVCR_b;
15718     };
15719 
15720     union
15721     {
15722         __IOM uint8_t OCTACKDIVCR;       /*!< (@ 0x0000006D) Octal-SPI clock Division control register                  */
15723 
15724         struct
15725         {
15726             __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI clock (OCTACLK) Division Select                          */
15727             uint8_t                 : 5;
15728         } OCTACKDIVCR_b;
15729     };
15730 
15731     union
15732     {
15733         __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Core clock Division control register                 */
15734 
15735         struct
15736         {
15737             __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Core clock (CANFDCLK) Division Select                        */
15738             uint8_t                  : 5;
15739         } CANFDCKDIVCR_b;
15740     };
15741 
15742     union
15743     {
15744         __IOM uint8_t USB60CKDIVCR;       /*!< (@ 0x0000006F) USB60 clock Division control register                      */
15745 
15746         struct
15747         {
15748             __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select                               */
15749             uint8_t                  : 5;
15750         } USB60CKDIVCR_b;
15751     };
15752 
15753     union
15754     {
15755         __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000070) I3C clock Division control register                        */
15756 
15757         struct
15758         {
15759             __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
15760             uint8_t                : 5;
15761         } I3CCKDIVCR_b;
15762     };
15763     __IM uint8_t  RESERVED23;
15764     __IM uint16_t RESERVED24;
15765 
15766     union
15767     {
15768         __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB clock control register                                 */
15769 
15770         struct
15771         {
15772             __IOM uint8_t USBCKSEL  : 4; /*!< [3..0] USB clock (USBCLK) Source Select                                   */
15773             uint8_t                 : 2;
15774             __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB clock (USBCLK) Switching Request                               */
15775             __IOM uint8_t USBCKSRDY : 1; /*!< [7..7] USB clock (USBCLK) Switching Ready state flag                      */
15776         } USBCKCR_b;
15777     };
15778 
15779     union
15780     {
15781         __IOM uint8_t OCTACKCR;           /*!< (@ 0x00000075) Octal-SPI clock control register                           */
15782 
15783         struct
15784         {
15785             __IOM uint8_t OCTACKSEL  : 4; /*!< [3..0] Octal-SPI clock (OCTACLK) Source Select                            */
15786             uint8_t                  : 2;
15787             __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI clock (OCTACLK) Switching Request                        */
15788             __IOM uint8_t OCTACKSRDY : 1; /*!< [7..7] Octal-SPI clock (OCTACLK) Switching Ready state flag               */
15789         } OCTACKCR_b;
15790     };
15791 
15792     union
15793     {
15794         __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Core clock control register                          */
15795 
15796         struct
15797         {
15798             __IOM uint8_t CANFDCKSEL  : 4; /*!< [3..0] CANFD Core clock (CANFDCLK) Source Select                          */
15799             uint8_t                   : 2;
15800             __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Core clock (CANFDCLK) Switching Request                      */
15801             __IOM uint8_t CANFDCKSRDY : 1; /*!< [7..7] CANFD Core clock (CANFDCLK) Switching Ready state flag             */
15802         } CANFDCKCR_b;
15803     };
15804 
15805     union
15806     {
15807         __IOM uint8_t USB60CKCR;           /*!< (@ 0x00000077) USB60 clock control register                               */
15808 
15809         struct
15810         {
15811             __IOM uint8_t USB60CKSEL  : 4; /*!< [3..0] USB clock (USB60CLK) Source Select                                 */
15812             uint8_t                   : 2;
15813             __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request                             */
15814             __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag                    */
15815         } USB60CKCR_b;
15816     };
15817 
15818     union
15819     {
15820         __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000078) I3C clock control register                                 */
15821 
15822         struct
15823         {
15824             __IOM uint8_t I3CCKSEL  : 4; /*!< [3..0] I3C clock (I3CCLK) Source Select                                   */
15825             uint8_t                 : 2;
15826             __IOM uint8_t I3CCKREQ  : 1; /*!< [6..6] I3C clock (I3CCLK) Switching Request                               */
15827             __IOM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) Switching Ready state flag                      */
15828         } I3CCKCR_b;
15829     };
15830     __IM uint8_t  RESERVED25;
15831     __IM uint16_t RESERVED26;
15832 
15833     union
15834     {
15835         __IOM uint8_t MOSCSCR;          /*!< (@ 0x0000007C) Main Clock Oscillator Standby Control Register             */
15836 
15837         struct
15838         {
15839             __IOM uint8_t MOSCSOKP : 1; /*!< [0..0] Main Clock Oscillator Standby Oscillation Keep select              */
15840             uint8_t                : 7;
15841         } MOSCSCR_b;
15842     };
15843 
15844     union
15845     {
15846         __IOM uint8_t HOCOSCR;          /*!< (@ 0x0000007D) High-Speed On-Chip Oscillator Standby Control
15847                                          *                  Register                                                   */
15848 
15849         struct
15850         {
15851             __IOM uint8_t HOCOSOKP : 1; /*!< [0..0] HOCO Standby Oscillation Keep select                               */
15852             uint8_t                : 7;
15853         } HOCOSCR_b;
15854     };
15855     __IM uint16_t RESERVED27;
15856     __IM uint32_t RESERVED28[8];
15857 
15858     union
15859     {
15860         __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
15861 
15862         struct
15863         {
15864             __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
15865             uint8_t              : 2;
15866             __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
15867             uint8_t              : 3;
15868         } OPCCR_b;
15869     };
15870     __IM uint8_t RESERVED29;
15871 
15872     union
15873     {
15874         __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
15875 
15876         struct
15877         {
15878             __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
15879             uint8_t            : 4;
15880         } MOSCWTCR_b;
15881     };
15882     __IM uint8_t RESERVED30[2];
15883 
15884     union
15885     {
15886         __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
15887 
15888         struct
15889         {
15890             __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
15891                                         *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
15892             uint8_t : 5;
15893         } HOCOWTCR_b;
15894     };
15895     __IM uint16_t RESERVED31[2];
15896 
15897     union
15898     {
15899         __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
15900 
15901         struct
15902         {
15903             __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
15904             uint8_t               : 3;
15905             __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
15906             uint8_t               : 3;
15907         } SOPCCR_b;
15908     };
15909     __IM uint8_t  RESERVED32;
15910     __IM uint32_t RESERVED33[5];
15911 
15912     union
15913     {
15914         __IOM uint32_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
15915 
15916         struct
15917         {
15918             __IOM uint32_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect Flag. NOTE: Writable
15919                                         *   only to clear the flag. Confirm the value is 1 and then
15920                                         *   write 0.                                                                  */
15921             __IOM uint32_t WDTRF : 1;  /*!< [1..1] Watchdog Timer0 Reset Detect Flag. NOTE: Writable only
15922                                         *   to clear the flag. Confirm the value is 1 and then write
15923                                         *   0.                                                                        */
15924             __IOM uint32_t SWRF : 1;   /*!< [2..2] Software Reset Detect Flag. NOTE: Writable only to clear
15925                                         *   the flag. Confirm the value is 1 and then write 0.                        */
15926             uint32_t              : 1;
15927             __IOM uint32_t CLU0RF : 1; /*!< [4..4] CPU0 Lockup Reset Detect Flag. NOTE: Writable only to
15928                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
15929             __IOM uint32_t LM0RF : 1;  /*!< [5..5] Local memory 0 error Reset Detect Flag. NOTE: Writable
15930                                         *   only to clear the flag. Confirm the value is 1 and then
15931                                         *   write 0.                                                                  */
15932             uint32_t             : 4;
15933             __IOM uint32_t BUSRF : 1;  /*!< [10..10] Bus error Reset Detect Flag. NOTE: Writable only to
15934                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
15935             uint32_t            : 3;
15936             __IOM uint32_t CMRF : 1;   /*!< [14..14] Common memory error Reset Detect Flag. NOTE: Writable
15937                                         *   only to clear the flag. Confirm the value is 1 and then
15938                                         *   write 0.                                                                  */
15939             uint32_t              : 2;
15940             __IOM uint32_t WDT1RF : 1; /*!< [17..17] Watchdog Timer1 Reset Detect Flag. NOTE: Writable only
15941                                         *   to clear the flag. Confirm the value is 1 and then write
15942                                         *   0.                                                                        */
15943             uint32_t              : 2;
15944             __IOM uint32_t CLU1RF : 1; /*!< [20..20] CPU1 Lockup Reset Detect Flag. NOTE: Writable only
15945                                         *   to clear the flag. Confirm the value is 1 and then write
15946                                         *   0.                                                                        */
15947             __IOM uint32_t LM1RF : 1;  /*!< [21..21] Local memory 1 error Reset Detect Flag. NOTE: Writable
15948                                         *   only to clear the flag. Confirm the value is 1 and then
15949                                         *   write 0.                                                                  */
15950             __IOM uint32_t NWRF : 1;   /*!< [22..22] Network Reset Detect Flag. NOTE: Writable only to clear
15951                                         *   the flag. Confirm the value is 1 and then write 0.                        */
15952             uint32_t : 9;
15953         } RSTSR1_b;
15954     };
15955     __IM uint32_t RESERVED34[2];
15956 
15957     union
15958     {
15959         __IOM uint8_t SYRACCR;         /*!< (@ 0x000000CC) System Register Access Control Register                    */
15960 
15961         struct
15962         {
15963             __IOM uint8_t BUSY : 1;    /*!< [0..0] Access Ready monitor                                               */
15964             uint8_t            : 7;
15965         } SYRACCR_b;
15966     };
15967     __IM uint8_t  RESERVED35;
15968     __IM uint16_t RESERVED36;
15969     __IM uint32_t RESERVED37[4];
15970 
15971     union
15972     {
15973         __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
15974 
15975         struct
15976         {
15977             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
15978             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
15979             uint8_t              : 5;
15980         } LVD1CR1_b;
15981     };
15982 
15983     union
15984     {
15985         __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
15986 
15987         struct
15988         {
15989             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
15990                                         *   0 can be written to this bit. After writing 0 to this bit,
15991                                         *   it takes 2 system clock cycles for the bit to be read as
15992                                         *   0.                                                                        */
15993             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor Signal Monitor Flag                                */
15994             uint8_t          : 6;
15995         } LVD1SR_b;
15996     };
15997 
15998     union
15999     {
16000         __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
16001 
16002         struct
16003         {
16004             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
16005             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
16006             uint8_t              : 5;
16007         } LVD2CR1_b;
16008     };
16009 
16010     union
16011     {
16012         __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
16013 
16014         struct
16015         {
16016             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
16017                                         *   0 can be written to this bit. After writing 0 to this bit,
16018                                         *   it takes 2 system clock cycles for the bit to be read as
16019                                         *   0.                                                                        */
16020             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor Signal Monitor Flag                                */
16021             uint8_t          : 6;
16022         } LVD2SR_b;
16023     };
16024     __IM uint32_t RESERVED38[3];
16025 
16026     union
16027     {
16028         __IOM uint8_t CRVSYSCR;        /*!< (@ 0x000000F0) Clock Recovery System Control Register                     */
16029 
16030         struct
16031         {
16032             __IOM uint8_t CRVEN : 1;   /*!< [0..0] Clock Recovery Enable                                              */
16033             uint8_t             : 7;
16034         } CRVSYSCR_b;
16035     };
16036     __IM uint8_t  RESERVED39;
16037     __IM uint16_t RESERVED40;
16038     __IM uint32_t RESERVED41[7];
16039 
16040     union
16041     {
16042         __IOM uint8_t PDCTRGD;         /*!< (@ 0x00000110) Graphics Power Domain Control Register                     */
16043 
16044         struct
16045         {
16046             __IOM uint8_t PDDE  : 1;   /*!< [0..0] Power control enable                                               */
16047             uint8_t             : 5;
16048             __IM uint8_t PDCSF  : 1;   /*!< [6..6] Power control status flag                                          */
16049             __IM uint8_t PDPGSF : 1;   /*!< [7..7] Power gating status flag                                           */
16050         } PDCTRGD_b;
16051     };
16052     __IM uint8_t   RESERVED42;
16053     __IM uint16_t  RESERVED43;
16054     __IM uint32_t  RESERVED44[11];
16055     __IOM uint16_t PDRAMSCR0;          /*!< (@ 0x00000140) SRAM power domain Standby Control Register 0               */
16056     __IOM uint8_t  PDRAMSCR1;          /*!< (@ 0x00000142) SRAM power domain Standby Control Register 1               */
16057     __IM uint8_t   RESERVED45;
16058     __IM uint32_t  RESERVED46[155];
16059 
16060     union
16061     {
16062         __IOM uint16_t VBRSABAR;       /*!< (@ 0x000003B0) VBATT Backup Register Security Attribute Boundary
16063                                         *                  Address Register                                           */
16064 
16065         struct
16066         {
16067             __IOM uint16_t SABA : 16;  /*!< [15..0] Security Attribute Boundary Address                               */
16068         } VBRSABAR_b;
16069     };
16070     __IM uint16_t RESERVED47;
16071 
16072     union
16073     {
16074         __IOM uint16_t VBRPABARS;      /*!< (@ 0x000003B4) VBATT Backup Register Privilege Attribute Boundary
16075                                         *                  Address Register for Secure Region                         */
16076 
16077         struct
16078         {
16079             __IOM uint16_t PABAS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Secure Region            */
16080         } VBRPABARS_b;
16081     };
16082     __IM uint16_t RESERVED48;
16083 
16084     union
16085     {
16086         __IOM uint16_t VBRPABARNS;      /*!< (@ 0x000003B8) VBATT Backup Register Privilege Attribute Boundary
16087                                          *                  Address Register for Non-secure Region                     */
16088 
16089         struct
16090         {
16091             __IOM uint16_t PABANS : 16; /*!< [15..0] Privilege Attribute Boundary Address for Non-secure
16092                                          *   Region                                                                    */
16093         } VBRPABARNS_b;
16094     };
16095     __IM uint16_t RESERVED49;
16096     __IM uint32_t RESERVED50;
16097 
16098     union
16099     {
16100         __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
16101                                           *                  Register                                                   */
16102 
16103         struct
16104         {
16105             __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non-secure Attribute bit 0                                         */
16106             uint32_t                : 1;
16107             __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non-secure Attribute bit 2                                         */
16108             __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non-secure Attribute bit 3                                         */
16109             __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non-secure Attribute bit 4                                         */
16110             __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non-secure Attribute bit 5                                         */
16111             __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non-secure Attribute bit 6                                         */
16112             __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non-secure Attribute bit 7                                         */
16113             __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non-secure Attribute bit 8                                         */
16114             __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non-secure Attribute bit 9                                         */
16115             uint32_t                : 1;
16116             __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non-secure Attribute bit 11                                      */
16117             __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non-secure Attribute bit 12                                      */
16118             __IOM uint32_t NONSEC13 : 1; /*!< [13..13] Non-secure Attribute bit 13                                      */
16119             uint32_t                : 2;
16120             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16                                      */
16121             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17                                      */
16122             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18                                      */
16123             __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19                                      */
16124             __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non-secure Attribute bit 20                                      */
16125             __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21                                      */
16126             __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non-secure Attribute bit 22                                      */
16127             uint32_t                : 1;
16128             __IOM uint32_t NONSEC24 : 1; /*!< [24..24] Non-secure Attribute bit 24                                      */
16129             __IOM uint32_t NONSEC25 : 1; /*!< [25..25] Non-secure Attribute bit 25                                      */
16130             __IOM uint32_t NONSEC26 : 1; /*!< [26..26] Non-secure Attribute bit 26                                      */
16131             uint32_t                : 5;
16132         } CGFSAR_b;
16133     };
16134 
16135     union
16136     {
16137         __IOM uint32_t RSTSAR;          /*!< (@ 0x000003C4) Reset Security Attribution Register                        */
16138 
16139         struct
16140         {
16141             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0                                         */
16142             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1                                         */
16143             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2                                         */
16144             __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3                                         */
16145             uint32_t               : 28;
16146         } RSTSAR_b;
16147     };
16148 
16149     union
16150     {
16151         __IOM uint32_t LPMSAR;           /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
16152 
16153         struct
16154         {
16155             __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non-secure Attribute bit 00                                        */
16156             __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non-secure Attribute bit 01                                        */
16157             __IOM uint32_t NONSEC2  : 1; /*!< [2..2] Non-secure Attribute bit 02                                        */
16158             __IOM uint32_t NONSEC3  : 1; /*!< [3..3] Non-secure Attribute bit 03                                        */
16159             uint32_t                : 4;
16160             __IOM uint32_t NONSEC8  : 1; /*!< [8..8] Non-secure Attribute bit 08                                        */
16161             uint32_t                : 7;
16162             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non-secure Attribute bit 16                                      */
16163             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non-secure Attribute bit 17                                      */
16164             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non-secure Attribute bit 18                                      */
16165             __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non-secure Attribute bit 19                                      */
16166             uint32_t                : 1;
16167             __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non-secure Attribute bit 21                                      */
16168             uint32_t                : 10;
16169         } LPMSAR_b;
16170     };
16171 
16172     union
16173     {
16174         __IOM uint32_t LVDSAR;          /*!< (@ 0x000003CC) Programable Voltage Detection Security Attribution
16175                                          *                  Register                                                   */
16176 
16177         struct
16178         {
16179             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0                                         */
16180             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1                                         */
16181             uint32_t               : 30;
16182         } LVDSAR_b;
16183     };
16184 
16185     union
16186     {
16187         __IOM uint32_t BBFSAR;          /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register        */
16188 
16189         struct
16190         {
16191             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non-secure Attribute bit 0                                         */
16192             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 1                                         */
16193             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 2                                         */
16194             __IOM uint32_t NONSEC3 : 1; /*!< [3..3] Non-secure Attribute bit 3                                         */
16195             __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non-secure Attribute bit 4                                         */
16196             uint32_t               : 27;
16197         } BBFSAR_b;
16198     };
16199     __IM uint32_t RESERVED51;
16200 
16201     union
16202     {
16203         __IOM uint32_t PGCSAR;         /*!< (@ 0x000003D8) Power Gating Control Security Attribution Register         */
16204 
16205         struct
16206         {
16207             uint32_t               : 1;
16208             __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non-secure Attribute bit 01                                        */
16209             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non-secure Attribute bit 02                                        */
16210             uint32_t               : 29;
16211         } PGCSAR_b;
16212     };
16213     __IM uint32_t RESERVED52;
16214 
16215     union
16216     {
16217         __IOM uint32_t DPFSAR;         /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
16218                                         *                  Register                                                   */
16219 
16220         struct
16221         {
16222             uint32_t               : 16;
16223             __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
16224                                          *   16                                                                        */
16225             __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
16226                                          *   17                                                                        */
16227             __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
16228                                          *   18                                                                        */
16229             __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
16230                                          *   19                                                                        */
16231             __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
16232                                          *   20                                                                        */
16233             uint32_t               : 3;
16234             __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
16235                                          *   24                                                                        */
16236             __IOM uint32_t DPFSA25 : 1; /*!< [25..25] Deep Standby Interrupt Factor Security Attribute bit
16237                                          *   25                                                                        */
16238             __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
16239                                          *   26                                                                        */
16240             __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
16241                                          *   27                                                                        */
16242             uint32_t               : 1;
16243             __IOM uint32_t DPFSA29 : 1; /*!< [29..29] Deep Standby Interrupt Factor Security Attribute bit
16244                                          *   29                                                                        */
16245             uint32_t               : 1;
16246             __IOM uint32_t DPFSA31 : 1; /*!< [31..31] Deep Standby Interrupt Factor Security Attribute bit
16247                                          *   31                                                                        */
16248         } DPFSAR_b;
16249     };
16250 
16251     union
16252     {
16253         __IOM uint32_t RSCSAR;          /*!< (@ 0x000003E4) RAM Standby Control Security Attribution Register          */
16254 
16255         struct
16256         {
16257             __IOM uint32_t RSCSA0  : 1; /*!< [0..0] RAM Standby Control Security Attribute bit 00                      */
16258             __IOM uint32_t RSCSA1  : 1; /*!< [1..1] RAM Standby Control Security Attribute bit 01                      */
16259             __IOM uint32_t RSCSA2  : 1; /*!< [2..2] RAM Standby Control Security Attribute bit 02                      */
16260             __IOM uint32_t RSCSA3  : 1; /*!< [3..3] RAM Standby Control Security Attribute bit 03                      */
16261             __IOM uint32_t RSCSA4  : 1; /*!< [4..4] RAM Standby Control Security Attribute bit 04                      */
16262             __IOM uint32_t RSCSA5  : 1; /*!< [5..5] RAM Standby Control Security Attribute bit 05                      */
16263             __IOM uint32_t RSCSA6  : 1; /*!< [6..6] RAM Standby Control Security Attribute bit 06                      */
16264             __IOM uint32_t RSCSA7  : 1; /*!< [7..7] RAM Standby Control Security Attribute bit 07                      */
16265             __IOM uint32_t RSCSA8  : 1; /*!< [8..8] RAM Standby Control Security Attribute bit 08                      */
16266             __IOM uint32_t RSCSA9  : 1; /*!< [9..9] RAM Standby Control Security Attribute bit 09                      */
16267             __IOM uint32_t RSCSA10 : 1; /*!< [10..10] RAM Standby Control Security Attribute bit 10                    */
16268             __IOM uint32_t RSCSA11 : 1; /*!< [11..11] RAM Standby Control Security Attribute bit 11                    */
16269             __IOM uint32_t RSCSA12 : 1; /*!< [12..12] RAM Standby Control Security Attribute bit 12                    */
16270             __IOM uint32_t RSCSA13 : 1; /*!< [13..13] RAM Standby Control Security Attribute bit 13                    */
16271             __IOM uint32_t RSCSA14 : 1; /*!< [14..14] RAM Standby Control Security Attribute bit 14                    */
16272             uint32_t               : 1;
16273             __IOM uint32_t RSCSA16 : 1; /*!< [16..16] RAM Standby Control Security Attribute bit 16                    */
16274             __IOM uint32_t RSCSA17 : 1; /*!< [17..17] RAM Standby Control Security Attribute bit 17                    */
16275             uint32_t               : 14;
16276         } RSCSAR_b;
16277     };
16278     __IM uint32_t RESERVED53[4];
16279     __IM uint16_t RESERVED54;
16280 
16281     union
16282     {
16283         __IOM uint16_t PRCR;           /*!< (@ 0x000003FA) Protect Register for Secure Register                       */
16284 
16285         struct
16286         {
16287             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
16288                                         *   generation circuit.                                                       */
16289             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
16290                                         *   modes, the low power modes, and the battery backup function.              */
16291             uint16_t            : 1;
16292             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the PVD.               */
16293             __IOM uint16_t PRC4 : 1;   /*!< [4..4] Enables writing to the registers related to the security
16294                                         *   and privilege setting registers.                                          */
16295             __IOM uint16_t PRC5 : 1;   /*!< [5..5] Enables writing to the registers related the reset control.        */
16296             uint16_t            : 2;
16297             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
16298         } PRCR_b;
16299     };
16300     __IM uint16_t RESERVED55;
16301 
16302     union
16303     {
16304         __IOM uint16_t PRCR_NS;        /*!< (@ 0x000003FE) Protect Register for Non-secure Register                   */
16305 
16306         struct
16307         {
16308             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
16309                                         *   generation circuit.                                                       */
16310             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
16311                                         *   modes, the low power modes, and the battery backup function.              */
16312             uint16_t            : 1;
16313             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the PVD.               */
16314             __IOM uint16_t PRC4 : 1;   /*!< [4..4] Enables writing to the registers related to the privilege
16315                                         *   setting registers.                                                        */
16316             uint16_t            : 3;
16317             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
16318         } PRCR_NS_b;
16319     };
16320 
16321     union
16322     {
16323         __IOM uint8_t LOCOCR;          /*!< (@ 0x00000400) Low-Speed On-Chip Oscillator Control Register              */
16324 
16325         struct
16326         {
16327             __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
16328             uint8_t             : 7;
16329         } LOCOCR_b;
16330     };
16331     __IM uint8_t RESERVED56;
16332 
16333     union
16334     {
16335         __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000402) LOCO User Trimming Control Register                        */
16336 
16337         struct
16338         {
16339             __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming                                                 */
16340         } LOCOUTCR_b;
16341     };
16342     __IM uint8_t  RESERVED57;
16343     __IM uint32_t RESERVED58[2];
16344     __IM uint16_t RESERVED59;
16345     __IM uint8_t  RESERVED60;
16346 
16347     union
16348     {
16349         __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
16350 
16351         struct
16352         {
16353             __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
16354             uint8_t             : 6;
16355         } STCONR_b;
16356     };
16357     __IM uint32_t RESERVED61[380];
16358 
16359     union
16360     {
16361         __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000A00) Deep Standby Control Register                              */
16362 
16363         struct
16364         {
16365             uint8_t                : 2;
16366             __IOM uint8_t DCSSMODE : 1; /*!< [2..2] DCDC SSMODE                                                        */
16367             uint8_t                : 1;
16368             __IOM uint8_t SRKEEP   : 1; /*!< [4..4] Standby RAM Retention                                              */
16369             uint8_t                : 1;
16370             __IOM uint8_t IOKEEP   : 1; /*!< [6..6] I/O Port Retention                                                 */
16371             __IOM uint8_t DPSBY    : 1; /*!< [7..7] Deep Software Standby                                              */
16372         } DPSBYCR_b;
16373     };
16374     __IM uint8_t  RESERVED62;
16375     __IM uint16_t RESERVED63;
16376 
16377     union
16378     {
16379         __IOM uint8_t DPSWCR;          /*!< (@ 0x00000A04) Deep Standby Wait Control Register                         */
16380 
16381         struct
16382         {
16383             __IOM uint8_t WTSTS : 8;   /*!< [7..0] Deep Software Wait Standby Time Setting Bit                        */
16384         } DPSWCR_b;
16385     };
16386     __IM uint8_t  RESERVED64;
16387     __IM uint16_t RESERVED65;
16388 
16389     union
16390     {
16391         __IOM uint8_t DPSIER0;         /*!< (@ 0x00000A08) Deep Standby Interrupt Enable Register 0                   */
16392 
16393         struct
16394         {
16395             __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ0-DS Pin Enable                                                 */
16396             __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ1-DS Pin Enable                                                 */
16397             __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ2-DS Pin Enable                                                 */
16398             __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ3-DS Pin Enable                                                 */
16399             __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ4-DS Pin Enable                                                 */
16400             __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ5-DS Pin Enable                                                 */
16401             __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ6-DS Pin Enable                                                 */
16402             __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ7-DS Pin Enable                                                 */
16403         } DPSIER0_b;
16404     };
16405     __IM uint8_t  RESERVED66;
16406     __IM uint16_t RESERVED67;
16407 
16408     union
16409     {
16410         __IOM uint8_t DPSIER1;         /*!< (@ 0x00000A0C) Deep Standby Interrupt Enable Register 1                   */
16411 
16412         struct
16413         {
16414             __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ8-DS Pin Enable                                                 */
16415             __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ9-DS Pin Enable                                                 */
16416             __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ10-DS Pin Enable                                                */
16417             __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ11-DS Pin Enable                                                */
16418             __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ12-DS Pin Enable                                                */
16419             __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ13-DS Pin Enable                                                */
16420             __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ14-DS Pin Enable                                                */
16421             __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ15-DS Pin Enable                                                */
16422         } DPSIER1_b;
16423     };
16424     __IM uint8_t  RESERVED68;
16425     __IM uint16_t RESERVED69;
16426 
16427     union
16428     {
16429         __IOM uint8_t DPSIER2;          /*!< (@ 0x00000A10) Deep Standby Interrupt Enable Register 2                   */
16430 
16431         struct
16432         {
16433             __IOM uint8_t DPVD1IE  : 1; /*!< [0..0] PVD1 Deep Standby Cancel Signal Enable                             */
16434             __IOM uint8_t DPVD2IE  : 1; /*!< [1..1] PVD2 Deep Standby Cancel Signal Enable                             */
16435             __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
16436             __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
16437             __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
16438             uint8_t                : 3;
16439         } DPSIER2_b;
16440     };
16441     __IM uint8_t  RESERVED70;
16442     __IM uint16_t RESERVED71;
16443 
16444     union
16445     {
16446         __IOM uint8_t DPSIER3;            /*!< (@ 0x00000A14) Deep Standby Interrupt Enable Register 3                   */
16447 
16448         struct
16449         {
16450             __IOM uint8_t DUSBFSIE   : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
16451             __IOM uint8_t DUSBHSIE   : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
16452             __IOM uint8_t DULPT0IE   : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Signal Enable                   */
16453             __IOM uint8_t DULPT1IE   : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Signal Enable                   */
16454             uint8_t                  : 1;
16455             __IOM uint8_t DIWDTIE    : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Signal Enable                    */
16456             uint8_t                  : 1;
16457             __IOM uint8_t DVBATTADIE : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Signal Enable           */
16458         } DPSIER3_b;
16459     };
16460     __IM uint8_t  RESERVED72;
16461     __IM uint16_t RESERVED73;
16462 
16463     union
16464     {
16465         __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000A18) Deep Standby Interrupt Flag Register 0                     */
16466 
16467         struct
16468         {
16469             __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ0-DS Pin Deep Standby Cancel Flag                               */
16470             __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ1-DS Pin Deep Standby Cancel Flag                               */
16471             __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ2-DS Pin Deep Standby Cancel Flag                               */
16472             __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ3-DS Pin Deep Standby Cancel Flag                               */
16473             __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ4-DS Pin Deep Standby Cancel Flag                               */
16474             __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ5-DS Pin Deep Standby Cancel Flag                               */
16475             __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ6-DS Pin Deep Standby Cancel Flag                               */
16476             __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ7-DS Pin Deep Standby Cancel Flag                               */
16477         } DPSIFR0_b;
16478     };
16479     __IM uint8_t  RESERVED74;
16480     __IM uint16_t RESERVED75;
16481 
16482     union
16483     {
16484         __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000A1C) Deep Standby Interrupt Flag Register 1                     */
16485 
16486         struct
16487         {
16488             __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ8-DS Pin Deep Standby Cancel Flag                               */
16489             __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ9-DS Pin Deep Standby Cancel Flag                               */
16490             __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ10-DS Pin Deep Standby Cancel Flag                              */
16491             __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ11-DS Pin Deep Standby Cancel Flag                              */
16492             __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ12-DS Pin Deep Standby Cancel Flag                              */
16493             __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ13-DS Pin Deep Standby Cancel Flag                              */
16494             __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ14-DS Pin Deep Standby Cancel Flag                              */
16495             __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ15-DS Pin Deep Standby Cancel Flag                              */
16496         } DPSIFR1_b;
16497     };
16498     __IM uint8_t  RESERVED76;
16499     __IM uint16_t RESERVED77;
16500 
16501     union
16502     {
16503         __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000A20) Deep Standby Interrupt Flag Register 2                     */
16504 
16505         struct
16506         {
16507             __IOM uint8_t DPVD1IF  : 1; /*!< [0..0] PVD1 Deep Standby Cancel Flag                                      */
16508             __IOM uint8_t DPVD2IF  : 1; /*!< [1..1] PVD2 Deep Standby Cancel Flag                                      */
16509             __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
16510             __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
16511             __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
16512             uint8_t                : 3;
16513         } DPSIFR2_b;
16514     };
16515     __IM uint8_t  RESERVED78;
16516     __IM uint16_t RESERVED79;
16517 
16518     union
16519     {
16520         __IOM uint8_t DPSIFR3;            /*!< (@ 0x00000A24) Deep Standby Interrupt Flag Register 3                     */
16521 
16522         struct
16523         {
16524             __IOM uint8_t DUSBFSIF   : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
16525             __IOM uint8_t DUSBHSIF   : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
16526             __IOM uint8_t DULPT0IF   : 1; /*!< [2..2] ULPT0 Overflow Deep Standby Cancel Flag                            */
16527             __IOM uint8_t DULPT1IF   : 1; /*!< [3..3] ULPT1 Overflow Deep Standby Cancel Flag                            */
16528             uint8_t                  : 1;
16529             __IOM uint8_t DIWDTIF    : 1; /*!< [5..5] IWDT Overflow Deep Standby Cancel Flag                             */
16530             uint8_t                  : 1;
16531             __IOM uint8_t DVBATTADIF : 1; /*!< [7..7] VBATT Tamper Detection Deep Standby Cancel Flag                    */
16532         } DPSIFR3_b;
16533     };
16534     __IM uint8_t  RESERVED80;
16535     __IM uint16_t RESERVED81;
16536 
16537     union
16538     {
16539         __IOM uint8_t DPSIEGR0;        /*!< (@ 0x00000A28) Deep Standby Interrupt Edge Register 0                     */
16540 
16541         struct
16542         {
16543             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ0-DS Pin Edge Select                                            */
16544             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ1-DS Pin Edge Select                                            */
16545             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ2-DS Pin Edge Select                                            */
16546             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ3-DS Pin Edge Select                                            */
16547             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ4-DS Pin Edge Select                                            */
16548             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ5-DS Pin Edge Select                                            */
16549             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ6-DS Pin Edge Select                                            */
16550             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ7-DS Pin Edge Select                                            */
16551         } DPSIEGR0_b;
16552     };
16553     __IM uint8_t  RESERVED82;
16554     __IM uint16_t RESERVED83;
16555 
16556     union
16557     {
16558         __IOM uint8_t DPSIEGR1;         /*!< (@ 0x00000A2C) Deep Standby Interrupt Edge Register 1                     */
16559 
16560         struct
16561         {
16562             __IOM uint8_t DIRQ8EG  : 1; /*!< [0..0] IRQ8-DS Pin Edge Select                                            */
16563             __IOM uint8_t DIRQ9EG  : 1; /*!< [1..1] IRQ9-DS Pin Edge Select                                            */
16564             __IOM uint8_t DIRQ10EG : 1; /*!< [2..2] IRQ10-DS Pin Edge Select                                           */
16565             __IOM uint8_t DIRQ11EG : 1; /*!< [3..3] IRQ11-DS Pin Edge Select                                           */
16566             __IOM uint8_t DIRQ12EG : 1; /*!< [4..4] IRQ12-DS Pin Edge Select                                           */
16567             __IOM uint8_t DIRQ13EG : 1; /*!< [5..5] IRQ13-DS Pin Edge Select                                           */
16568             __IOM uint8_t DIRQ14EG : 1; /*!< [6..6] IRQ14-DS Pin Edge Select                                           */
16569             __IOM uint8_t DIRQ15EG : 1; /*!< [7..7] IRQ15-DS Pin Edge Select                                           */
16570         } DPSIEGR1_b;
16571     };
16572     __IM uint8_t  RESERVED84;
16573     __IM uint16_t RESERVED85;
16574 
16575     union
16576     {
16577         __IOM uint8_t DPSIEGR2;        /*!< (@ 0x00000A30) Deep Standby Interrupt Edge Register 2                     */
16578 
16579         struct
16580         {
16581             __IOM uint8_t DPVD1EG : 1; /*!< [0..0] PVD1 Edge Select                                                   */
16582             __IOM uint8_t DPVD2EG : 1; /*!< [1..1] PVD2 Edge Select                                                   */
16583             uint8_t               : 2;
16584             __IOM uint8_t DNMIEG  : 1; /*!< [4..4] NMI Pin Edge Select                                                */
16585             uint8_t               : 3;
16586         } DPSIEGR2_b;
16587     };
16588     __IM uint8_t  RESERVED86;
16589     __IM uint16_t RESERVED87;
16590     __IM uint32_t RESERVED88;
16591 
16592     union
16593     {
16594         __IOM uint8_t SYOCDCR;         /*!< (@ 0x00000A38) System Control OCD Control Register                        */
16595 
16596         struct
16597         {
16598             __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
16599             uint8_t             : 6;
16600             __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
16601         } SYOCDCR_b;
16602     };
16603     __IM uint8_t  RESERVED89;
16604     __IM uint16_t RESERVED90;
16605     __IM uint32_t RESERVED91;
16606 
16607     union
16608     {
16609         __IOM uint8_t RSTSR0;          /*!< (@ 0x00000A40) Reset Status Register 0                                    */
16610 
16611         struct
16612         {
16613             __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect Flag. NOTE: Writable only to clear
16614                                         *   the flag. Confirm the value is 1 and then write 0.                        */
16615             __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect Flag. NOTE: Writable only
16616                                         *   to clear the flag. Confirm the value is 1 and then write
16617                                         *   0.                                                                        */
16618             __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect Flag. NOTE: Writable only
16619                                         *   to clear the flag. Confirm the value is 1 and then write
16620                                         *   0.                                                                        */
16621             __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect Flag. NOTE: Writable only
16622                                         *   to clear the flag. Confirm the value is 1 and then write
16623                                         *   0.                                                                        */
16624             __IOM uint8_t LVD3RF : 1;  /*!< [4..4] Voltage Monitor 3 Reset Detect Flag. NOTE: Writable only
16625                                         *   to clear the flag. Confirm the value is 1 and then write
16626                                         *   0.                                                                        */
16627             __IOM uint8_t LVD4RF : 1;  /*!< [5..5] Voltage Monitor 4 Reset Detect Flag. NOTE: Writable only
16628                                         *   to clear the flag. Confirm the value is 1 and then write
16629                                         *   0.                                                                        */
16630             __IOM uint8_t LVD5RF : 1;  /*!< [6..6] Voltage Monitor 5 Reset Detect Flag. NOTE: Writable only
16631                                         *   to clear the flag. Confirm the value is 1 and then write
16632                                         *   0.                                                                        */
16633             __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset Flag. NOTE: Writable only
16634                                         *   to clear the flag. Confirm the value is 1 and then write
16635                                         *   0.                                                                        */
16636         } RSTSR0_b;
16637     };
16638     __IM uint8_t  RESERVED92;
16639     __IM uint16_t RESERVED93;
16640 
16641     union
16642     {
16643         __IOM uint8_t RSTSR2;          /*!< (@ 0x00000A44) Reset Status Register 2                                    */
16644 
16645         struct
16646         {
16647             __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
16648             uint8_t            : 7;
16649         } RSTSR2_b;
16650     };
16651     __IM uint8_t  RESERVED94;
16652     __IM uint16_t RESERVED95;
16653 
16654     union
16655     {
16656         __IOM uint8_t RSTSR3;          /*!< (@ 0x00000A48) Reset Status Register 3                                    */
16657 
16658         struct
16659         {
16660             uint8_t             : 4;
16661             __IOM uint8_t OCPRF : 1;   /*!< [4..4] Overcurrent protection reset Detect Flag                           */
16662             uint8_t             : 3;
16663         } RSTSR3_b;
16664     };
16665     __IM uint8_t  RESERVED96;
16666     __IM uint16_t RESERVED97;
16667     __IM uint32_t RESERVED98;
16668 
16669     union
16670     {
16671         __IOM uint8_t MOMCR;           /*!< (@ 0x00000A50) Main Clock Oscillator Mode Oscillation Control
16672                                         *                  Register                                                   */
16673 
16674         struct
16675         {
16676             uint8_t              : 1;
16677             __IOM uint8_t MODRV0 : 3;  /*!< [3..1] Main Clock Oscillator Drive Capability 0 Switching                 */
16678             uint8_t              : 2;
16679             __IOM uint8_t MOSEL  : 1;  /*!< [6..6] Main Clock Oscillator Switching                                    */
16680             uint8_t              : 1;
16681         } MOMCR_b;
16682     };
16683     __IM uint8_t  RESERVED99;
16684     __IM uint16_t RESERVED100;
16685 
16686     union
16687     {
16688         __IOM uint8_t FWEPROR;         /*!< (@ 0x00000A54) Flash Write Erase Protect Register                         */
16689 
16690         struct
16691         {
16692             __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programing and Erasure                                       */
16693             uint8_t            : 6;
16694         } FWEPROR_b;
16695     };
16696     __IM uint8_t  RESERVED101;
16697     __IM uint16_t RESERVED102;
16698 
16699     union
16700     {
16701         union
16702         {
16703             __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000A58) Voltage Monitor Circuit Control Register                   */
16704 
16705             struct
16706             {
16707                 uint8_t             : 5;
16708                 __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
16709                 __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
16710                 uint8_t             : 1;
16711             } LVCMPCR_b;
16712         };
16713 
16714         union
16715         {
16716             __IOM uint8_t LVD1CMPCR;       /*!< (@ 0x00000A58) Voltage Monitor 1 Comparator Control Register              */
16717 
16718             struct
16719             {
16720                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Detection Voltage 1 Level Select(Standard voltage during
16721                                             *   drop in voltage)                                                          */
16722                 uint8_t             : 2;
16723                 __IOM uint8_t LVD1E : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
16724             } LVD1CMPCR_b;
16725         };
16726     };
16727     __IM uint8_t  RESERVED103;
16728     __IM uint16_t RESERVED104;
16729 
16730     union
16731     {
16732         __IOM uint8_t LVD2CMPCR;       /*!< (@ 0x00000A5C) Voltage Monitor 2 Comparator Control Register              */
16733 
16734         struct
16735         {
16736             __IOM uint8_t LVD2LVL : 5; /*!< [4..0] Detection Voltage 2 Level Select(Standard voltage during
16737                                         *   drop in voltage)                                                          */
16738             uint8_t             : 2;
16739             __IOM uint8_t LVD2E : 1;   /*!< [7..7] Voltage Detection 2 Enable                                         */
16740         } LVD2CMPCR_b;
16741     };
16742     __IM uint8_t  RESERVED105;
16743     __IM uint16_t RESERVED106;
16744     __IM uint32_t RESERVED107[4];
16745 
16746     union
16747     {
16748         __IOM uint8_t LVD1CR0;         /*!< (@ 0x00000A70) Voltage Monitor 1 Circuit Control Register 0               */
16749 
16750         struct
16751         {
16752             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
16753             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
16754             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
16755             uint8_t             : 1;
16756             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
16757             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
16758             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
16759         } LVD1CR0_b;
16760     };
16761     __IM uint8_t  RESERVED108;
16762     __IM uint16_t RESERVED109;
16763 
16764     union
16765     {
16766         __IOM uint8_t LVD2CR0;         /*!< (@ 0x00000A74) Voltage Monitor 2 Circuit Control Register 0               */
16767 
16768         struct
16769         {
16770             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
16771             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
16772             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
16773             uint8_t             : 1;
16774             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
16775             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
16776             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
16777         } LVD2CR0_b;
16778     };
16779     __IM uint8_t  RESERVED110;
16780     __IM uint16_t RESERVED111;
16781     __IM uint32_t RESERVED112[3];
16782 
16783     union
16784     {
16785         __IOM uint8_t VBATTMNSELR;        /*!< (@ 0x00000A84) Battery Backup Voltage Monitor Function Select
16786                                            *                  Register                                                   */
16787 
16788         struct
16789         {
16790             __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Voltage Monitor Function Select Bit                          */
16791             uint8_t                  : 7;
16792         } VBATTMNSELR_b;
16793     };
16794     __IM uint8_t  RESERVED113;
16795     __IM uint16_t RESERVED114;
16796 
16797     union
16798     {
16799         __IOM uint8_t VBTBPCR1;         /*!< (@ 0x00000A88) VBATT Battery Power Supply Control Register 1              */
16800 
16801         struct
16802         {
16803             __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power Supply Switch Stop                                   */
16804             uint8_t                : 7;
16805         } VBTBPCR1_b;
16806     };
16807     __IM uint8_t  RESERVED115;
16808     __IM uint16_t RESERVED116;
16809     __IM uint32_t RESERVED117;
16810 
16811     union
16812     {
16813         __IOM uint8_t LPSCR;           /*!< (@ 0x00000A90) Low Power State Control Register                           */
16814 
16815         struct
16816         {
16817             __IOM uint8_t LPMD : 4;    /*!< [3..0] Low power mode setting bit                                         */
16818             uint8_t            : 4;
16819         } LPSCR_b;
16820     };
16821     __IM uint8_t  RESERVED118;
16822     __IM uint16_t RESERVED119;
16823     __IM uint32_t RESERVED120;
16824 
16825     union
16826     {
16827         __IOM uint8_t SSCR1;           /*!< (@ 0x00000A98) Software Standby Control Register 1                        */
16828 
16829         struct
16830         {
16831             __IOM uint8_t SS1FR : 1;   /*!< [0..0] Software Standby 1 Fast Return                                     */
16832             uint8_t             : 7;
16833         } SSCR1_b;
16834     };
16835     __IM uint8_t  RESERVED121;
16836     __IM uint16_t RESERVED122;
16837     __IM uint32_t RESERVED123[5];
16838 
16839     union
16840     {
16841         __IOM uint8_t LVOCR;           /*!< (@ 0x00000AB0) Low Power State Control Register                           */
16842 
16843         struct
16844         {
16845             __IOM uint8_t LVO0E : 1;   /*!< [0..0] Low Voltage Operation 0 Enable                                     */
16846             __IOM uint8_t LVO1E : 1;   /*!< [1..1] Low Voltage Operation 1 Enable                                     */
16847             uint8_t             : 6;
16848         } LVOCR_b;
16849     };
16850     __IM uint8_t  RESERVED124;
16851     __IM uint16_t RESERVED125;
16852     __IM uint32_t RESERVED126[7];
16853 
16854     union
16855     {
16856         __IOM uint8_t SYRSTMSK0;         /*!< (@ 0x00000AD0) System Reset Mask Control Register0                        */
16857 
16858         struct
16859         {
16860             __IOM uint8_t IWDTMASK  : 1; /*!< [0..0] Independent watchdog timer Reset Mask                              */
16861             __IOM uint8_t WDT0MASK  : 1; /*!< [1..1] CPU0 Watchdog timer Reset Mask                                     */
16862             __IOM uint8_t SWMASK    : 1; /*!< [2..2] Software Reset Mask                                                */
16863             uint8_t                 : 1;
16864             __IOM uint8_t CLUP0MASK : 1; /*!< [4..4] CPU0 Lockup Reset Mask                                             */
16865             __IOM uint8_t LM0MASK   : 1; /*!< [5..5] Local memory 0 error Reset Mask                                    */
16866             __IOM uint8_t CMMASK    : 1; /*!< [6..6] Common memory error Reset Mask                                     */
16867             __IOM uint8_t BUSMASK   : 1; /*!< [7..7] BUS error Reset Mask                                               */
16868         } SYRSTMSK0_b;
16869     };
16870     __IM uint8_t  RESERVED127;
16871     __IM uint16_t RESERVED128;
16872 
16873     union
16874     {
16875         __IOM uint8_t SYRSTMSK1;       /*!< (@ 0x00000AD4) System Reset Mask Control Register1                        */
16876 
16877         struct
16878         {
16879             uint8_t                 : 1;
16880             __IOM uint8_t WDT1MASK  : 1; /*!< [1..1] CPU1 Watchdog timer Reset Mask                                     */
16881             uint8_t                 : 2;
16882             __IOM uint8_t CLUP1MASK : 1; /*!< [4..4] CPU1 Lockup Reset Mask                                             */
16883             __IOM uint8_t LM1MASK   : 1; /*!< [5..5] Local memory 1 error Reset Mask                                    */
16884             uint8_t                 : 1;
16885             __IOM uint8_t NWMASK    : 1; /*!< [7..7] Network Reset Mask                                                 */
16886         } SYRSTMSK1_b;
16887     };
16888     __IM uint8_t  RESERVED129;
16889     __IM uint16_t RESERVED130;
16890 
16891     union
16892     {
16893         __IOM uint8_t SYRSTMSK2;        /*!< (@ 0x00000AD8) System Reset Mask Control Register2                        */
16894 
16895         struct
16896         {
16897             __IOM uint8_t LVD1MASK : 1; /*!< [0..0] Voltage Monitor 1 Reset Mask                                       */
16898             __IOM uint8_t LVD2MASK : 1; /*!< [1..1] Voltage Monitor 2 Reset Mask                                       */
16899             __IOM uint8_t LVD3MASK : 1; /*!< [2..2] Voltage Monitor 3 Reset Mask                                       */
16900             __IOM uint8_t LVD4MASK : 1; /*!< [3..3] Voltage Monitor 4 Reset Mask                                       */
16901             __IOM uint8_t LVD5MASK : 1; /*!< [4..4] Voltage Monitor 5 Reset Mask                                       */
16902             uint8_t                : 3;
16903         } SYRSTMSK2_b;
16904     };
16905     __IM uint8_t  RESERVED131;
16906     __IM uint16_t RESERVED132;
16907     __IM uint32_t RESERVED133[10];
16908 
16909     union
16910     {
16911         __IOM uint8_t PLL1LDOCR;       /*!< (@ 0x00000B04) PLL1-LDO Control Register                                  */
16912 
16913         struct
16914         {
16915             __IOM uint8_t LDOSTP : 1;  /*!< [0..0] LDO Stop                                                           */
16916             __IOM uint8_t SKEEP  : 1;  /*!< [1..1] STBY Keep                                                          */
16917             uint8_t              : 6;
16918         } PLL1LDOCR_b;
16919     };
16920     __IM uint8_t  RESERVED134;
16921     __IM uint16_t RESERVED135;
16922 
16923     union
16924     {
16925         __IOM uint8_t PLL2LDOCR;       /*!< (@ 0x00000B08) PLL2-LDO Control Register                                  */
16926 
16927         struct
16928         {
16929             __IOM uint8_t LDOSTP : 1;  /*!< [0..0] LDO Stop                                                           */
16930             __IOM uint8_t SKEEP  : 1;  /*!< [1..1] STBY Keep                                                          */
16931             uint8_t              : 6;
16932         } PLL2LDOCR_b;
16933     };
16934     __IM uint8_t  RESERVED136;
16935     __IM uint16_t RESERVED137;
16936 
16937     union
16938     {
16939         __IOM uint8_t HOCOLDOCR;       /*!< (@ 0x00000B0C) HOCO-LDO Control Register                                  */
16940 
16941         struct
16942         {
16943             __IOM uint8_t LDOSTP : 1;  /*!< [0..0] LDO Stop                                                           */
16944             __IOM uint8_t SKEEP  : 1;  /*!< [1..1] STBY Keep                                                          */
16945             uint8_t              : 6;
16946         } HOCOLDOCR_b;
16947     };
16948     __IM uint8_t  RESERVED138;
16949     __IM uint16_t RESERVED139;
16950     __IM uint32_t RESERVED140[4];
16951 
16952     union
16953     {
16954         __IOM uint8_t LVD1FCR;         /*!< (@ 0x00000B20) Voltage Monitor % Function Control Register                */
16955 
16956         struct
16957         {
16958             __IOM uint8_t RHSEL : 1;   /*!< [0..0] Rise Hysteresis Select                                             */
16959             uint8_t             : 7;
16960         } LVD1FCR_b;
16961     };
16962     __IM uint8_t  RESERVED141;
16963     __IM uint16_t RESERVED142;
16964 
16965     union
16966     {
16967         __IOM uint8_t LVD2FCR;         /*!< (@ 0x00000B24) Voltage Monitor % Function Control Register                */
16968 
16969         struct
16970         {
16971             __IOM uint8_t RHSEL : 1;   /*!< [0..0] Rise Hysteresis Select                                             */
16972             uint8_t             : 7;
16973         } LVD2FCR_b;
16974     };
16975     __IM uint8_t  RESERVED143;
16976     __IM uint16_t RESERVED144;
16977     __IM uint32_t RESERVED145[54];
16978 
16979     union
16980     {
16981         __IOM uint8_t SOSCCR;          /*!< (@ 0x00000C00) Sub-clock oscillator control register                      */
16982 
16983         struct
16984         {
16985             __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
16986             uint8_t             : 7;
16987         } SOSCCR_b;
16988     };
16989 
16990     union
16991     {
16992         __IOM uint8_t SOMCR;           /*!< (@ 0x00000C01) Sub Clock Oscillator Mode Control Register                 */
16993 
16994         struct
16995         {
16996             __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub Clock Oscillator Drive Capability Switching                    */
16997             uint8_t             : 4;
16998             __IOM uint8_t SOSEL : 1;   /*!< [6..6] Sub Clock Oscillator Switching                                     */
16999             uint8_t             : 1;
17000         } SOMCR_b;
17001     };
17002     __IM uint16_t RESERVED146;
17003     __IM uint32_t RESERVED147[15];
17004 
17005     union
17006     {
17007         __IOM uint8_t VBTBER;          /*!< (@ 0x00000C40) VBATT Backup Enable Register                               */
17008 
17009         struct
17010         {
17011             uint8_t            : 3;
17012             __IOM uint8_t VBAE : 1;    /*!< [3..3] VBATT backup register access enable bit                            */
17013             uint8_t            : 4;
17014         } VBTBER_b;
17015     };
17016     __IM uint8_t  RESERVED148;
17017     __IM uint16_t RESERVED149;
17018     __IM uint8_t  RESERVED150;
17019 
17020     union
17021     {
17022         __IOM uint8_t VBTBPCR2;        /*!< (@ 0x00000C45) VBATT Battery Power Supply Control Register 2              */
17023 
17024         struct
17025         {
17026             __IOM uint8_t VDETLVL : 3; /*!< [2..0] VDETBAT Level Select                                               */
17027             uint8_t               : 1;
17028             __IOM uint8_t VDETE   : 1; /*!< [4..4] Voltage drop detection enable                                      */
17029             uint8_t               : 3;
17030         } VBTBPCR2_b;
17031     };
17032 
17033     union
17034     {
17035         __IOM uint8_t VBTBPSR;         /*!< (@ 0x00000C46) VBATT Battery Power Supply Status Register                 */
17036 
17037         struct
17038         {
17039             __IOM uint8_t VBPORF : 1;  /*!< [0..0] VBATT_POR Flag                                                     */
17040             uint8_t              : 3;
17041             __IOM uint8_t VBPORM : 1;  /*!< [4..4] VBATT_POR Monitor                                                  */
17042             __IOM uint8_t BPWSWM : 1;  /*!< [5..5] Battery Power Supply Switch Status Monitor                         */
17043             uint8_t              : 2;
17044         } VBTBPSR_b;
17045     };
17046     __IM uint8_t RESERVED151;
17047 
17048     union
17049     {
17050         __IOM uint8_t VBTADSR;         /*!< (@ 0x00000C48) VBATT Tamper detection Status Register                     */
17051 
17052         struct
17053         {
17054             __IOM uint8_t VBTADF0 : 1; /*!< [0..0] VBATT Tamper Detection flag 0                                      */
17055             __IOM uint8_t VBTADF1 : 1; /*!< [1..1] VBATT Tamper Detection flag 1                                      */
17056             __IOM uint8_t VBTADF2 : 1; /*!< [2..2] VBATT Tamper Detection flag 2                                      */
17057             uint8_t               : 5;
17058         } VBTADSR_b;
17059     };
17060 
17061     union
17062     {
17063         __IOM uint8_t VBTADCR1;          /*!< (@ 0x00000C49) VBATT Tamper detection Control Register 1                  */
17064 
17065         struct
17066         {
17067             __IOM uint8_t VBTADIE0  : 1; /*!< [0..0] VBATT Tamper Detection Interrupt Enable 0                          */
17068             __IOM uint8_t VBTADIE1  : 1; /*!< [1..1] VBATT Tamper Detection Interrupt Enable 1                          */
17069             __IOM uint8_t VBTADIE2  : 1; /*!< [2..2] VBATT Tamper Detection Interrupt Enable 2                          */
17070             uint8_t                 : 1;
17071             __IOM uint8_t VBTADCLE0 : 1; /*!< [4..4] VBATT Tamper Detection Backup Register Clear Enable 0              */
17072             __IOM uint8_t VBTADCLE1 : 1; /*!< [5..5] VBATT Tamper Detection Backup Register Clear Enable 1              */
17073             __IOM uint8_t VBTADCLE2 : 1; /*!< [6..6] VBATT Tamper Detection Backup Register Clear Enable 2              */
17074             uint8_t                 : 1;
17075         } VBTADCR1_b;
17076     };
17077 
17078     union
17079     {
17080         __IOM uint8_t VBTADCR2;         /*!< (@ 0x00000C4A) VBATT Tamper detection Control Register 2                  */
17081 
17082         struct
17083         {
17084             __IOM uint8_t VBRTCES0 : 1; /*!< [0..0] VBATT RTC Time Capture Event Source Select 0                       */
17085             __IOM uint8_t VBRTCES1 : 1; /*!< [1..1] VBATT RTC Time Capture Event Source Select 1                       */
17086             __IOM uint8_t VBRTCES2 : 1; /*!< [2..2] VBATT RTC Time Capture Event Source Select 2                       */
17087             uint8_t                : 5;
17088         } VBTADCR2_b;
17089     };
17090     __IM uint8_t RESERVED152;
17091 
17092     union
17093     {
17094         __IOM uint8_t VBTICTLR;         /*!< (@ 0x00000C4C) VBATT Input Control Register                               */
17095 
17096         struct
17097         {
17098             __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
17099             __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
17100             __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
17101             uint8_t                : 5;
17102         } VBTICTLR_b;
17103     };
17104 
17105     union
17106     {
17107         __IOM uint8_t VBTICTLR2;       /*!< (@ 0x00000C4D) VBATT Input Control Register 2                             */
17108 
17109         struct
17110         {
17111             __IOM uint8_t VCH0NCE : 1; /*!< [0..0] VBATT CH0 Input Noise Canceler Enable                              */
17112             __IOM uint8_t VCH1NCE : 1; /*!< [1..1] VBATT CH1 Input Noise Canceler Enable                              */
17113             __IOM uint8_t VCH2NCE : 1; /*!< [2..2] VBATT CH2 Input Noise Canceler Enable                              */
17114             uint8_t               : 1;
17115             __IOM uint8_t VCH0EG  : 1; /*!< [4..4] VBATT CH0 Input Edge Select                                        */
17116             __IOM uint8_t VCH1EG  : 1; /*!< [5..5] VBATT CH1 Input Edge Select                                        */
17117             __IOM uint8_t VCH2EG  : 1; /*!< [6..6] VBATT CH2 Input Edge Select                                        */
17118             uint8_t               : 1;
17119         } VBTICTLR2_b;
17120     };
17121 
17122     union
17123     {
17124         __IOM uint8_t VBTIMONR;        /*!< (@ 0x00000C4E) VBATT Input Monitor Register                               */
17125 
17126         struct
17127         {
17128             __IOM uint8_t VCH0MON : 1; /*!< [0..0] VBATT CH0 Input monitor                                            */
17129             __IOM uint8_t VCH1MON : 1; /*!< [1..1] VBATT CH1 Input monitor                                            */
17130             __IOM uint8_t VCH2MON : 1; /*!< [2..2] VBATT CH2 Input monitor                                            */
17131             uint8_t               : 5;
17132         } VBTIMONR_b;
17133     };
17134     __IM uint8_t  RESERVED153;
17135     __IM uint32_t RESERVED154[44];
17136 
17137     union
17138     {
17139         __IOM uint8_t VBTBKR0;         /*!< (@ 0x00000D00) VBATT Backup Register 0                                    */
17140 
17141         struct
17142         {
17143             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17144         } VBTBKR0_b;
17145     };
17146 
17147     union
17148     {
17149         __IOM uint8_t VBTBKR1;         /*!< (@ 0x00000D01) VBATT Backup Register 1                                    */
17150 
17151         struct
17152         {
17153             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17154         } VBTBKR1_b;
17155     };
17156 
17157     union
17158     {
17159         __IOM uint8_t VBTBKR2;         /*!< (@ 0x00000D02) VBATT Backup Register 2                                    */
17160 
17161         struct
17162         {
17163             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17164         } VBTBKR2_b;
17165     };
17166 
17167     union
17168     {
17169         __IOM uint8_t VBTBKR3;         /*!< (@ 0x00000D03) VBATT Backup Register 3                                    */
17170 
17171         struct
17172         {
17173             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17174         } VBTBKR3_b;
17175     };
17176 
17177     union
17178     {
17179         __IOM uint8_t VBTBKR4;         /*!< (@ 0x00000D04) VBATT Backup Register 4                                    */
17180 
17181         struct
17182         {
17183             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17184         } VBTBKR4_b;
17185     };
17186 
17187     union
17188     {
17189         __IOM uint8_t VBTBKR5;         /*!< (@ 0x00000D05) VBATT Backup Register 5                                    */
17190 
17191         struct
17192         {
17193             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17194         } VBTBKR5_b;
17195     };
17196 
17197     union
17198     {
17199         __IOM uint8_t VBTBKR6;         /*!< (@ 0x00000D06) VBATT Backup Register 6                                    */
17200 
17201         struct
17202         {
17203             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17204         } VBTBKR6_b;
17205     };
17206 
17207     union
17208     {
17209         __IOM uint8_t VBTBKR7;         /*!< (@ 0x00000D07) VBATT Backup Register 7                                    */
17210 
17211         struct
17212         {
17213             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17214         } VBTBKR7_b;
17215     };
17216 
17217     union
17218     {
17219         __IOM uint8_t VBTBKR8;         /*!< (@ 0x00000D08) VBATT Backup Register 8                                    */
17220 
17221         struct
17222         {
17223             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17224         } VBTBKR8_b;
17225     };
17226 
17227     union
17228     {
17229         __IOM uint8_t VBTBKR9;         /*!< (@ 0x00000D09) VBATT Backup Register 9                                    */
17230 
17231         struct
17232         {
17233             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17234         } VBTBKR9_b;
17235     };
17236 
17237     union
17238     {
17239         __IOM uint8_t VBTBKR10;        /*!< (@ 0x00000D0A) VBATT Backup Register 10                                   */
17240 
17241         struct
17242         {
17243             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17244         } VBTBKR10_b;
17245     };
17246 
17247     union
17248     {
17249         __IOM uint8_t VBTBKR11;        /*!< (@ 0x00000D0B) VBATT Backup Register 11                                   */
17250 
17251         struct
17252         {
17253             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17254         } VBTBKR11_b;
17255     };
17256 
17257     union
17258     {
17259         __IOM uint8_t VBTBKR12;        /*!< (@ 0x00000D0C) VBATT Backup Register 12                                   */
17260 
17261         struct
17262         {
17263             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17264         } VBTBKR12_b;
17265     };
17266 
17267     union
17268     {
17269         __IOM uint8_t VBTBKR13;        /*!< (@ 0x00000D0D) VBATT Backup Register 13                                   */
17270 
17271         struct
17272         {
17273             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17274         } VBTBKR13_b;
17275     };
17276 
17277     union
17278     {
17279         __IOM uint8_t VBTBKR14;        /*!< (@ 0x00000D0E) VBATT Backup Register 14                                   */
17280 
17281         struct
17282         {
17283             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17284         } VBTBKR14_b;
17285     };
17286 
17287     union
17288     {
17289         __IOM uint8_t VBTBKR15;        /*!< (@ 0x00000D0F) VBATT Backup Register 15                                   */
17290 
17291         struct
17292         {
17293             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17294         } VBTBKR15_b;
17295     };
17296 
17297     union
17298     {
17299         __IOM uint8_t VBTBKR16;        /*!< (@ 0x00000D10) VBATT Backup Register 16                                   */
17300 
17301         struct
17302         {
17303             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17304         } VBTBKR16_b;
17305     };
17306 
17307     union
17308     {
17309         __IOM uint8_t VBTBKR17;        /*!< (@ 0x00000D11) VBATT Backup Register 17                                   */
17310 
17311         struct
17312         {
17313             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17314         } VBTBKR17_b;
17315     };
17316 
17317     union
17318     {
17319         __IOM uint8_t VBTBKR18;        /*!< (@ 0x00000D12) VBATT Backup Register 18                                   */
17320 
17321         struct
17322         {
17323             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17324         } VBTBKR18_b;
17325     };
17326 
17327     union
17328     {
17329         __IOM uint8_t VBTBKR19;        /*!< (@ 0x00000D13) VBATT Backup Register 19                                   */
17330 
17331         struct
17332         {
17333             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17334         } VBTBKR19_b;
17335     };
17336 
17337     union
17338     {
17339         __IOM uint8_t VBTBKR20;        /*!< (@ 0x00000D14) VBATT Backup Register 20                                   */
17340 
17341         struct
17342         {
17343             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17344         } VBTBKR20_b;
17345     };
17346 
17347     union
17348     {
17349         __IOM uint8_t VBTBKR21;        /*!< (@ 0x00000D15) VBATT Backup Register 21                                   */
17350 
17351         struct
17352         {
17353             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17354         } VBTBKR21_b;
17355     };
17356 
17357     union
17358     {
17359         __IOM uint8_t VBTBKR22;        /*!< (@ 0x00000D16) VBATT Backup Register 22                                   */
17360 
17361         struct
17362         {
17363             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17364         } VBTBKR22_b;
17365     };
17366 
17367     union
17368     {
17369         __IOM uint8_t VBTBKR23;        /*!< (@ 0x00000D17) VBATT Backup Register 23                                   */
17370 
17371         struct
17372         {
17373             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17374         } VBTBKR23_b;
17375     };
17376 
17377     union
17378     {
17379         __IOM uint8_t VBTBKR24;        /*!< (@ 0x00000D18) VBATT Backup Register 24                                   */
17380 
17381         struct
17382         {
17383             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17384         } VBTBKR24_b;
17385     };
17386 
17387     union
17388     {
17389         __IOM uint8_t VBTBKR25;        /*!< (@ 0x00000D19) VBATT Backup Register 25                                   */
17390 
17391         struct
17392         {
17393             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17394         } VBTBKR25_b;
17395     };
17396 
17397     union
17398     {
17399         __IOM uint8_t VBTBKR26;        /*!< (@ 0x00000D1A) VBATT Backup Register 26                                   */
17400 
17401         struct
17402         {
17403             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17404         } VBTBKR26_b;
17405     };
17406 
17407     union
17408     {
17409         __IOM uint8_t VBTBKR27;        /*!< (@ 0x00000D1B) VBATT Backup Register 27                                   */
17410 
17411         struct
17412         {
17413             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17414         } VBTBKR27_b;
17415     };
17416 
17417     union
17418     {
17419         __IOM uint8_t VBTBKR28;        /*!< (@ 0x00000D1C) VBATT Backup Register 28                                   */
17420 
17421         struct
17422         {
17423             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17424         } VBTBKR28_b;
17425     };
17426 
17427     union
17428     {
17429         __IOM uint8_t VBTBKR29;        /*!< (@ 0x00000D1D) VBATT Backup Register 29                                   */
17430 
17431         struct
17432         {
17433             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17434         } VBTBKR29_b;
17435     };
17436 
17437     union
17438     {
17439         __IOM uint8_t VBTBKR30;        /*!< (@ 0x00000D1E) VBATT Backup Register 30                                   */
17440 
17441         struct
17442         {
17443             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17444         } VBTBKR30_b;
17445     };
17446 
17447     union
17448     {
17449         __IOM uint8_t VBTBKR31;        /*!< (@ 0x00000D1F) VBATT Backup Register 31                                   */
17450 
17451         struct
17452         {
17453             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17454         } VBTBKR31_b;
17455     };
17456 
17457     union
17458     {
17459         __IOM uint8_t VBTBKR32;        /*!< (@ 0x00000D20) VBATT Backup Register 32                                   */
17460 
17461         struct
17462         {
17463             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17464         } VBTBKR32_b;
17465     };
17466 
17467     union
17468     {
17469         __IOM uint8_t VBTBKR33;        /*!< (@ 0x00000D21) VBATT Backup Register 33                                   */
17470 
17471         struct
17472         {
17473             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17474         } VBTBKR33_b;
17475     };
17476 
17477     union
17478     {
17479         __IOM uint8_t VBTBKR34;        /*!< (@ 0x00000D22) VBATT Backup Register 34                                   */
17480 
17481         struct
17482         {
17483             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17484         } VBTBKR34_b;
17485     };
17486 
17487     union
17488     {
17489         __IOM uint8_t VBTBKR35;        /*!< (@ 0x00000D23) VBATT Backup Register 35                                   */
17490 
17491         struct
17492         {
17493             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17494         } VBTBKR35_b;
17495     };
17496 
17497     union
17498     {
17499         __IOM uint8_t VBTBKR36;        /*!< (@ 0x00000D24) VBATT Backup Register 36                                   */
17500 
17501         struct
17502         {
17503             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17504         } VBTBKR36_b;
17505     };
17506 
17507     union
17508     {
17509         __IOM uint8_t VBTBKR37;        /*!< (@ 0x00000D25) VBATT Backup Register 37                                   */
17510 
17511         struct
17512         {
17513             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17514         } VBTBKR37_b;
17515     };
17516 
17517     union
17518     {
17519         __IOM uint8_t VBTBKR38;        /*!< (@ 0x00000D26) VBATT Backup Register 38                                   */
17520 
17521         struct
17522         {
17523             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17524         } VBTBKR38_b;
17525     };
17526 
17527     union
17528     {
17529         __IOM uint8_t VBTBKR39;        /*!< (@ 0x00000D27) VBATT Backup Register 39                                   */
17530 
17531         struct
17532         {
17533             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17534         } VBTBKR39_b;
17535     };
17536 
17537     union
17538     {
17539         __IOM uint8_t VBTBKR40;        /*!< (@ 0x00000D28) VBATT Backup Register 40                                   */
17540 
17541         struct
17542         {
17543             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17544         } VBTBKR40_b;
17545     };
17546 
17547     union
17548     {
17549         __IOM uint8_t VBTBKR41;        /*!< (@ 0x00000D29) VBATT Backup Register 41                                   */
17550 
17551         struct
17552         {
17553             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17554         } VBTBKR41_b;
17555     };
17556 
17557     union
17558     {
17559         __IOM uint8_t VBTBKR42;        /*!< (@ 0x00000D2A) VBATT Backup Register 42                                   */
17560 
17561         struct
17562         {
17563             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17564         } VBTBKR42_b;
17565     };
17566 
17567     union
17568     {
17569         __IOM uint8_t VBTBKR43;        /*!< (@ 0x00000D2B) VBATT Backup Register 43                                   */
17570 
17571         struct
17572         {
17573             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17574         } VBTBKR43_b;
17575     };
17576 
17577     union
17578     {
17579         __IOM uint8_t VBTBKR44;        /*!< (@ 0x00000D2C) VBATT Backup Register 44                                   */
17580 
17581         struct
17582         {
17583             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17584         } VBTBKR44_b;
17585     };
17586 
17587     union
17588     {
17589         __IOM uint8_t VBTBKR45;        /*!< (@ 0x00000D2D) VBATT Backup Register 45                                   */
17590 
17591         struct
17592         {
17593             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17594         } VBTBKR45_b;
17595     };
17596 
17597     union
17598     {
17599         __IOM uint8_t VBTBKR46;        /*!< (@ 0x00000D2E) VBATT Backup Register 46                                   */
17600 
17601         struct
17602         {
17603             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17604         } VBTBKR46_b;
17605     };
17606 
17607     union
17608     {
17609         __IOM uint8_t VBTBKR47;        /*!< (@ 0x00000D2F) VBATT Backup Register 47                                   */
17610 
17611         struct
17612         {
17613             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17614         } VBTBKR47_b;
17615     };
17616 
17617     union
17618     {
17619         __IOM uint8_t VBTBKR48;        /*!< (@ 0x00000D30) VBATT Backup Register 48                                   */
17620 
17621         struct
17622         {
17623             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17624         } VBTBKR48_b;
17625     };
17626 
17627     union
17628     {
17629         __IOM uint8_t VBTBKR49;        /*!< (@ 0x00000D31) VBATT Backup Register 49                                   */
17630 
17631         struct
17632         {
17633             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17634         } VBTBKR49_b;
17635     };
17636 
17637     union
17638     {
17639         __IOM uint8_t VBTBKR50;        /*!< (@ 0x00000D32) VBATT Backup Register 50                                   */
17640 
17641         struct
17642         {
17643             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17644         } VBTBKR50_b;
17645     };
17646 
17647     union
17648     {
17649         __IOM uint8_t VBTBKR51;        /*!< (@ 0x00000D33) VBATT Backup Register 51                                   */
17650 
17651         struct
17652         {
17653             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17654         } VBTBKR51_b;
17655     };
17656 
17657     union
17658     {
17659         __IOM uint8_t VBTBKR52;        /*!< (@ 0x00000D34) VBATT Backup Register 52                                   */
17660 
17661         struct
17662         {
17663             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17664         } VBTBKR52_b;
17665     };
17666 
17667     union
17668     {
17669         __IOM uint8_t VBTBKR53;        /*!< (@ 0x00000D35) VBATT Backup Register 53                                   */
17670 
17671         struct
17672         {
17673             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17674         } VBTBKR53_b;
17675     };
17676 
17677     union
17678     {
17679         __IOM uint8_t VBTBKR54;        /*!< (@ 0x00000D36) VBATT Backup Register 54                                   */
17680 
17681         struct
17682         {
17683             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17684         } VBTBKR54_b;
17685     };
17686 
17687     union
17688     {
17689         __IOM uint8_t VBTBKR55;        /*!< (@ 0x00000D37) VBATT Backup Register 55                                   */
17690 
17691         struct
17692         {
17693             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17694         } VBTBKR55_b;
17695     };
17696 
17697     union
17698     {
17699         __IOM uint8_t VBTBKR56;        /*!< (@ 0x00000D38) VBATT Backup Register 56                                   */
17700 
17701         struct
17702         {
17703             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17704         } VBTBKR56_b;
17705     };
17706 
17707     union
17708     {
17709         __IOM uint8_t VBTBKR57;        /*!< (@ 0x00000D39) VBATT Backup Register 57                                   */
17710 
17711         struct
17712         {
17713             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17714         } VBTBKR57_b;
17715     };
17716 
17717     union
17718     {
17719         __IOM uint8_t VBTBKR58;        /*!< (@ 0x00000D3A) VBATT Backup Register 58                                   */
17720 
17721         struct
17722         {
17723             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17724         } VBTBKR58_b;
17725     };
17726 
17727     union
17728     {
17729         __IOM uint8_t VBTBKR59;        /*!< (@ 0x00000D3B) VBATT Backup Register 59                                   */
17730 
17731         struct
17732         {
17733             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17734         } VBTBKR59_b;
17735     };
17736 
17737     union
17738     {
17739         __IOM uint8_t VBTBKR60;        /*!< (@ 0x00000D3C) VBATT Backup Register 60                                   */
17740 
17741         struct
17742         {
17743             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17744         } VBTBKR60_b;
17745     };
17746 
17747     union
17748     {
17749         __IOM uint8_t VBTBKR61;        /*!< (@ 0x00000D3D) VBATT Backup Register 61                                   */
17750 
17751         struct
17752         {
17753             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17754         } VBTBKR61_b;
17755     };
17756 
17757     union
17758     {
17759         __IOM uint8_t VBTBKR62;        /*!< (@ 0x00000D3E) VBATT Backup Register 62                                   */
17760 
17761         struct
17762         {
17763             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17764         } VBTBKR62_b;
17765     };
17766 
17767     union
17768     {
17769         __IOM uint8_t VBTBKR63;        /*!< (@ 0x00000D3F) VBATT Backup Register 63                                   */
17770 
17771         struct
17772         {
17773             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17774         } VBTBKR63_b;
17775     };
17776 
17777     union
17778     {
17779         __IOM uint8_t VBTBKR64;        /*!< (@ 0x00000D40) VBATT Backup Register 64                                   */
17780 
17781         struct
17782         {
17783             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17784         } VBTBKR64_b;
17785     };
17786 
17787     union
17788     {
17789         __IOM uint8_t VBTBKR65;        /*!< (@ 0x00000D41) VBATT Backup Register 65                                   */
17790 
17791         struct
17792         {
17793             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17794         } VBTBKR65_b;
17795     };
17796 
17797     union
17798     {
17799         __IOM uint8_t VBTBKR66;        /*!< (@ 0x00000D42) VBATT Backup Register 66                                   */
17800 
17801         struct
17802         {
17803             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17804         } VBTBKR66_b;
17805     };
17806 
17807     union
17808     {
17809         __IOM uint8_t VBTBKR67;        /*!< (@ 0x00000D43) VBATT Backup Register 67                                   */
17810 
17811         struct
17812         {
17813             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17814         } VBTBKR67_b;
17815     };
17816 
17817     union
17818     {
17819         __IOM uint8_t VBTBKR68;        /*!< (@ 0x00000D44) VBATT Backup Register 68                                   */
17820 
17821         struct
17822         {
17823             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17824         } VBTBKR68_b;
17825     };
17826 
17827     union
17828     {
17829         __IOM uint8_t VBTBKR69;        /*!< (@ 0x00000D45) VBATT Backup Register 69                                   */
17830 
17831         struct
17832         {
17833             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17834         } VBTBKR69_b;
17835     };
17836 
17837     union
17838     {
17839         __IOM uint8_t VBTBKR70;        /*!< (@ 0x00000D46) VBATT Backup Register 70                                   */
17840 
17841         struct
17842         {
17843             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17844         } VBTBKR70_b;
17845     };
17846 
17847     union
17848     {
17849         __IOM uint8_t VBTBKR71;        /*!< (@ 0x00000D47) VBATT Backup Register 71                                   */
17850 
17851         struct
17852         {
17853             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17854         } VBTBKR71_b;
17855     };
17856 
17857     union
17858     {
17859         __IOM uint8_t VBTBKR72;        /*!< (@ 0x00000D48) VBATT Backup Register 72                                   */
17860 
17861         struct
17862         {
17863             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17864         } VBTBKR72_b;
17865     };
17866 
17867     union
17868     {
17869         __IOM uint8_t VBTBKR73;        /*!< (@ 0x00000D49) VBATT Backup Register 73                                   */
17870 
17871         struct
17872         {
17873             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17874         } VBTBKR73_b;
17875     };
17876 
17877     union
17878     {
17879         __IOM uint8_t VBTBKR74;        /*!< (@ 0x00000D4A) VBATT Backup Register 74                                   */
17880 
17881         struct
17882         {
17883             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17884         } VBTBKR74_b;
17885     };
17886 
17887     union
17888     {
17889         __IOM uint8_t VBTBKR75;        /*!< (@ 0x00000D4B) VBATT Backup Register 75                                   */
17890 
17891         struct
17892         {
17893             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17894         } VBTBKR75_b;
17895     };
17896 
17897     union
17898     {
17899         __IOM uint8_t VBTBKR76;        /*!< (@ 0x00000D4C) VBATT Backup Register 76                                   */
17900 
17901         struct
17902         {
17903             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17904         } VBTBKR76_b;
17905     };
17906 
17907     union
17908     {
17909         __IOM uint8_t VBTBKR77;        /*!< (@ 0x00000D4D) VBATT Backup Register 77                                   */
17910 
17911         struct
17912         {
17913             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17914         } VBTBKR77_b;
17915     };
17916 
17917     union
17918     {
17919         __IOM uint8_t VBTBKR78;        /*!< (@ 0x00000D4E) VBATT Backup Register 78                                   */
17920 
17921         struct
17922         {
17923             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17924         } VBTBKR78_b;
17925     };
17926 
17927     union
17928     {
17929         __IOM uint8_t VBTBKR79;        /*!< (@ 0x00000D4F) VBATT Backup Register 79                                   */
17930 
17931         struct
17932         {
17933             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17934         } VBTBKR79_b;
17935     };
17936 
17937     union
17938     {
17939         __IOM uint8_t VBTBKR80;        /*!< (@ 0x00000D50) VBATT Backup Register 80                                   */
17940 
17941         struct
17942         {
17943             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17944         } VBTBKR80_b;
17945     };
17946 
17947     union
17948     {
17949         __IOM uint8_t VBTBKR81;        /*!< (@ 0x00000D51) VBATT Backup Register 81                                   */
17950 
17951         struct
17952         {
17953             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17954         } VBTBKR81_b;
17955     };
17956 
17957     union
17958     {
17959         __IOM uint8_t VBTBKR82;        /*!< (@ 0x00000D52) VBATT Backup Register 82                                   */
17960 
17961         struct
17962         {
17963             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17964         } VBTBKR82_b;
17965     };
17966 
17967     union
17968     {
17969         __IOM uint8_t VBTBKR83;        /*!< (@ 0x00000D53) VBATT Backup Register 83                                   */
17970 
17971         struct
17972         {
17973             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17974         } VBTBKR83_b;
17975     };
17976 
17977     union
17978     {
17979         __IOM uint8_t VBTBKR84;        /*!< (@ 0x00000D54) VBATT Backup Register 84                                   */
17980 
17981         struct
17982         {
17983             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17984         } VBTBKR84_b;
17985     };
17986 
17987     union
17988     {
17989         __IOM uint8_t VBTBKR85;        /*!< (@ 0x00000D55) VBATT Backup Register 85                                   */
17990 
17991         struct
17992         {
17993             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
17994         } VBTBKR85_b;
17995     };
17996 
17997     union
17998     {
17999         __IOM uint8_t VBTBKR86;        /*!< (@ 0x00000D56) VBATT Backup Register 86                                   */
18000 
18001         struct
18002         {
18003             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18004         } VBTBKR86_b;
18005     };
18006 
18007     union
18008     {
18009         __IOM uint8_t VBTBKR87;        /*!< (@ 0x00000D57) VBATT Backup Register 87                                   */
18010 
18011         struct
18012         {
18013             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18014         } VBTBKR87_b;
18015     };
18016 
18017     union
18018     {
18019         __IOM uint8_t VBTBKR88;        /*!< (@ 0x00000D58) VBATT Backup Register 88                                   */
18020 
18021         struct
18022         {
18023             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18024         } VBTBKR88_b;
18025     };
18026 
18027     union
18028     {
18029         __IOM uint8_t VBTBKR89;        /*!< (@ 0x00000D59) VBATT Backup Register 89                                   */
18030 
18031         struct
18032         {
18033             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18034         } VBTBKR89_b;
18035     };
18036 
18037     union
18038     {
18039         __IOM uint8_t VBTBKR90;        /*!< (@ 0x00000D5A) VBATT Backup Register 90                                   */
18040 
18041         struct
18042         {
18043             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18044         } VBTBKR90_b;
18045     };
18046 
18047     union
18048     {
18049         __IOM uint8_t VBTBKR91;        /*!< (@ 0x00000D5B) VBATT Backup Register 91                                   */
18050 
18051         struct
18052         {
18053             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18054         } VBTBKR91_b;
18055     };
18056 
18057     union
18058     {
18059         __IOM uint8_t VBTBKR92;        /*!< (@ 0x00000D5C) VBATT Backup Register 92                                   */
18060 
18061         struct
18062         {
18063             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18064         } VBTBKR92_b;
18065     };
18066 
18067     union
18068     {
18069         __IOM uint8_t VBTBKR93;        /*!< (@ 0x00000D5D) VBATT Backup Register 93                                   */
18070 
18071         struct
18072         {
18073             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18074         } VBTBKR93_b;
18075     };
18076 
18077     union
18078     {
18079         __IOM uint8_t VBTBKR94;        /*!< (@ 0x00000D5E) VBATT Backup Register 94                                   */
18080 
18081         struct
18082         {
18083             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18084         } VBTBKR94_b;
18085     };
18086 
18087     union
18088     {
18089         __IOM uint8_t VBTBKR95;        /*!< (@ 0x00000D5F) VBATT Backup Register 95                                   */
18090 
18091         struct
18092         {
18093             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18094         } VBTBKR95_b;
18095     };
18096 
18097     union
18098     {
18099         __IOM uint8_t VBTBKR96;        /*!< (@ 0x00000D60) VBATT Backup Register 96                                   */
18100 
18101         struct
18102         {
18103             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18104         } VBTBKR96_b;
18105     };
18106 
18107     union
18108     {
18109         __IOM uint8_t VBTBKR97;        /*!< (@ 0x00000D61) VBATT Backup Register 97                                   */
18110 
18111         struct
18112         {
18113             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18114         } VBTBKR97_b;
18115     };
18116 
18117     union
18118     {
18119         __IOM uint8_t VBTBKR98;        /*!< (@ 0x00000D62) VBATT Backup Register 98                                   */
18120 
18121         struct
18122         {
18123             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18124         } VBTBKR98_b;
18125     };
18126 
18127     union
18128     {
18129         __IOM uint8_t VBTBKR99;        /*!< (@ 0x00000D63) VBATT Backup Register 99                                   */
18130 
18131         struct
18132         {
18133             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18134         } VBTBKR99_b;
18135     };
18136 
18137     union
18138     {
18139         __IOM uint8_t VBTBKR100;       /*!< (@ 0x00000D64) VBATT Backup Register 100                                  */
18140 
18141         struct
18142         {
18143             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18144         } VBTBKR100_b;
18145     };
18146 
18147     union
18148     {
18149         __IOM uint8_t VBTBKR101;       /*!< (@ 0x00000D65) VBATT Backup Register 101                                  */
18150 
18151         struct
18152         {
18153             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18154         } VBTBKR101_b;
18155     };
18156 
18157     union
18158     {
18159         __IOM uint8_t VBTBKR102;       /*!< (@ 0x00000D66) VBATT Backup Register 102                                  */
18160 
18161         struct
18162         {
18163             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18164         } VBTBKR102_b;
18165     };
18166 
18167     union
18168     {
18169         __IOM uint8_t VBTBKR103;       /*!< (@ 0x00000D67) VBATT Backup Register 103                                  */
18170 
18171         struct
18172         {
18173             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18174         } VBTBKR103_b;
18175     };
18176 
18177     union
18178     {
18179         __IOM uint8_t VBTBKR104;       /*!< (@ 0x00000D68) VBATT Backup Register 104                                  */
18180 
18181         struct
18182         {
18183             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18184         } VBTBKR104_b;
18185     };
18186 
18187     union
18188     {
18189         __IOM uint8_t VBTBKR105;       /*!< (@ 0x00000D69) VBATT Backup Register 105                                  */
18190 
18191         struct
18192         {
18193             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18194         } VBTBKR105_b;
18195     };
18196 
18197     union
18198     {
18199         __IOM uint8_t VBTBKR106;       /*!< (@ 0x00000D6A) VBATT Backup Register 106                                  */
18200 
18201         struct
18202         {
18203             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18204         } VBTBKR106_b;
18205     };
18206 
18207     union
18208     {
18209         __IOM uint8_t VBTBKR107;       /*!< (@ 0x00000D6B) VBATT Backup Register 107                                  */
18210 
18211         struct
18212         {
18213             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18214         } VBTBKR107_b;
18215     };
18216 
18217     union
18218     {
18219         __IOM uint8_t VBTBKR108;       /*!< (@ 0x00000D6C) VBATT Backup Register 108                                  */
18220 
18221         struct
18222         {
18223             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18224         } VBTBKR108_b;
18225     };
18226 
18227     union
18228     {
18229         __IOM uint8_t VBTBKR109;       /*!< (@ 0x00000D6D) VBATT Backup Register 109                                  */
18230 
18231         struct
18232         {
18233             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18234         } VBTBKR109_b;
18235     };
18236 
18237     union
18238     {
18239         __IOM uint8_t VBTBKR110;       /*!< (@ 0x00000D6E) VBATT Backup Register 110                                  */
18240 
18241         struct
18242         {
18243             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18244         } VBTBKR110_b;
18245     };
18246 
18247     union
18248     {
18249         __IOM uint8_t VBTBKR111;       /*!< (@ 0x00000D6F) VBATT Backup Register 111                                  */
18250 
18251         struct
18252         {
18253             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18254         } VBTBKR111_b;
18255     };
18256 
18257     union
18258     {
18259         __IOM uint8_t VBTBKR112;       /*!< (@ 0x00000D70) VBATT Backup Register 112                                  */
18260 
18261         struct
18262         {
18263             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18264         } VBTBKR112_b;
18265     };
18266 
18267     union
18268     {
18269         __IOM uint8_t VBTBKR113;       /*!< (@ 0x00000D71) VBATT Backup Register 113                                  */
18270 
18271         struct
18272         {
18273             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18274         } VBTBKR113_b;
18275     };
18276 
18277     union
18278     {
18279         __IOM uint8_t VBTBKR114;       /*!< (@ 0x00000D72) VBATT Backup Register 114                                  */
18280 
18281         struct
18282         {
18283             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18284         } VBTBKR114_b;
18285     };
18286 
18287     union
18288     {
18289         __IOM uint8_t VBTBKR115;       /*!< (@ 0x00000D73) VBATT Backup Register 115                                  */
18290 
18291         struct
18292         {
18293             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18294         } VBTBKR115_b;
18295     };
18296 
18297     union
18298     {
18299         __IOM uint8_t VBTBKR116;       /*!< (@ 0x00000D74) VBATT Backup Register 116                                  */
18300 
18301         struct
18302         {
18303             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18304         } VBTBKR116_b;
18305     };
18306 
18307     union
18308     {
18309         __IOM uint8_t VBTBKR117;       /*!< (@ 0x00000D75) VBATT Backup Register 117                                  */
18310 
18311         struct
18312         {
18313             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18314         } VBTBKR117_b;
18315     };
18316 
18317     union
18318     {
18319         __IOM uint8_t VBTBKR118;       /*!< (@ 0x00000D76) VBATT Backup Register 118                                  */
18320 
18321         struct
18322         {
18323             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18324         } VBTBKR118_b;
18325     };
18326 
18327     union
18328     {
18329         __IOM uint8_t VBTBKR119;       /*!< (@ 0x00000D77) VBATT Backup Register 119                                  */
18330 
18331         struct
18332         {
18333             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18334         } VBTBKR119_b;
18335     };
18336 
18337     union
18338     {
18339         __IOM uint8_t VBTBKR120;       /*!< (@ 0x00000D78) VBATT Backup Register 120                                  */
18340 
18341         struct
18342         {
18343             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18344         } VBTBKR120_b;
18345     };
18346 
18347     union
18348     {
18349         __IOM uint8_t VBTBKR121;       /*!< (@ 0x00000D79) VBATT Backup Register 121                                  */
18350 
18351         struct
18352         {
18353             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18354         } VBTBKR121_b;
18355     };
18356 
18357     union
18358     {
18359         __IOM uint8_t VBTBKR122;       /*!< (@ 0x00000D7A) VBATT Backup Register 122                                  */
18360 
18361         struct
18362         {
18363             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18364         } VBTBKR122_b;
18365     };
18366 
18367     union
18368     {
18369         __IOM uint8_t VBTBKR123;       /*!< (@ 0x00000D7B) VBATT Backup Register 123                                  */
18370 
18371         struct
18372         {
18373             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18374         } VBTBKR123_b;
18375     };
18376 
18377     union
18378     {
18379         __IOM uint8_t VBTBKR124;       /*!< (@ 0x00000D7C) VBATT Backup Register 124                                  */
18380 
18381         struct
18382         {
18383             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18384         } VBTBKR124_b;
18385     };
18386 
18387     union
18388     {
18389         __IOM uint8_t VBTBKR125;       /*!< (@ 0x00000D7D) VBATT Backup Register 125                                  */
18390 
18391         struct
18392         {
18393             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18394         } VBTBKR125_b;
18395     };
18396 
18397     union
18398     {
18399         __IOM uint8_t VBTBKR126;       /*!< (@ 0x00000D7E) VBATT Backup Register 126                                  */
18400 
18401         struct
18402         {
18403             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18404         } VBTBKR126_b;
18405     };
18406 
18407     union
18408     {
18409         __IOM uint8_t VBTBKR127;       /*!< (@ 0x00000D7F) VBATT Backup Register 127                                  */
18410 
18411         struct
18412         {
18413             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKRn [7:0] (n=0 to 127)                                         */
18414         } VBTBKR127_b;
18415     };
18416 } R_SYSTEM_Type;                       /*!< Size = 3456 (0xd80)                                                       */
18417 
18418 /* =========================================================================================================================== */
18419 /* ================                                         R_TSN_CAL                                         ================ */
18420 /* =========================================================================================================================== */
18421 
18422 /**
18423  * @brief Temperature Sensor (R_TSN_CAL)
18424  */
18425 
18426 typedef struct                         /*!< (@ 0x4011B17C) R_TSN_CAL Structure                                        */
18427 {
18428     union
18429     {
18430         __IM uint32_t TSCDR;           /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register        */
18431 
18432         struct
18433         {
18434             __IM uint32_t TSCDR : 32;  /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
18435                                         *   calibration converted value.                                              */
18436         } TSCDR_b;
18437     };
18438 } R_TSN_CAL_Type;                      /*!< Size = 4 (0x4)                                                            */
18439 
18440 /* =========================================================================================================================== */
18441 /* ================                                        R_TSN_CTRL                                         ================ */
18442 /* =========================================================================================================================== */
18443 
18444 /**
18445  * @brief Temperature Sensor (R_TSN_CTRL)
18446  */
18447 
18448 typedef struct                         /*!< (@ 0x40235000) R_TSN_CTRL Structure                                       */
18449 {
18450     union
18451     {
18452         __IOM uint8_t TSCR;            /*!< (@ 0x00000000) Temperature Sensor Control Register                        */
18453 
18454         struct
18455         {
18456             uint8_t            : 4;
18457             __IOM uint8_t TSOE : 1;    /*!< [4..4] Temperature Sensor Enable                                          */
18458             uint8_t            : 2;
18459             __IOM uint8_t TSEN : 1;    /*!< [7..7] Temperature Sensor Output Enable                                   */
18460         } TSCR_b;
18461     };
18462 } R_TSN_CTRL_Type;                     /*!< Size = 1 (0x1)                                                            */
18463 
18464 /* =========================================================================================================================== */
18465 /* ================                                         R_USB_FS0                                         ================ */
18466 /* =========================================================================================================================== */
18467 
18468 /**
18469  * @brief USB 2.0 Module (R_USB_FS0)
18470  */
18471 
18472 typedef struct                         /*!< (@ 0x40250000) R_USB_FS0 Structure                                        */
18473 {
18474     union
18475     {
18476         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
18477 
18478         struct
18479         {
18480             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
18481             uint16_t             : 2;
18482             __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
18483             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
18484             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
18485             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
18486             uint16_t             : 1;
18487             __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
18488             uint16_t             : 1;
18489             __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
18490             uint16_t             : 5;
18491         } SYSCFG_b;
18492     };
18493 
18494     union
18495     {
18496         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
18497 
18498         struct
18499         {
18500             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
18501                                         *   access cycles)                                                            */
18502             uint16_t : 12;
18503         } BUSWAIT_b;
18504     };
18505 
18506     union
18507     {
18508         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
18509 
18510         struct
18511         {
18512             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
18513             __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
18514             uint16_t            : 2;
18515             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
18516                                         *   Selected.                                                                 */
18517             __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
18518             uint16_t             : 7;
18519             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
18520                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
18521                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
18522                                         *   pin.                                                                      */
18523         } SYSSTS0_b;
18524     };
18525 
18526     union
18527     {
18528         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
18529 
18530         struct
18531         {
18532             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
18533             uint16_t              : 15;
18534         } PLLSTA_b;
18535     };
18536 
18537     union
18538     {
18539         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
18540 
18541         struct
18542         {
18543             __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
18544             uint16_t               : 1;
18545             __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
18546             __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
18547             __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
18548             __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
18549             __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
18550             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
18551             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
18552             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
18553                                          *   used when switching from device B to device A while in
18554                                          *   OTG mode. If the HNPBTOA bit is 1, the internal function
18555                                          *   control keeps the suspended state until the HNP processing
18556                                          *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
18557                                          *   set.                                                                      */
18558             uint16_t : 4;
18559         } DVSTCTR0_b;
18560     };
18561     __IM uint16_t RESERVED;
18562 
18563     union
18564     {
18565         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
18566 
18567         struct
18568         {
18569             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
18570             uint16_t            : 12;
18571         } TESTMODE_b;
18572     };
18573     __IM uint16_t RESERVED1;
18574     __IM uint32_t RESERVED2;
18575 
18576     union
18577     {
18578         __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
18579 
18580         struct
18581         {
18582             union
18583             {
18584                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
18585                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
18586             };
18587 
18588             union
18589             {
18590                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
18591 
18592                 struct
18593                 {
18594                     __IM uint8_t  RESERVED3;
18595                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
18596                 };
18597             };
18598         };
18599     };
18600 
18601     union
18602     {
18603         __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
18604 
18605         struct
18606         {
18607             union
18608             {
18609                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
18610                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
18611             };
18612 
18613             union
18614             {
18615                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
18616 
18617                 struct
18618                 {
18619                     __IM uint8_t  RESERVED4;
18620                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
18621                 };
18622             };
18623         };
18624     };
18625 
18626     union
18627     {
18628         __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
18629 
18630         struct
18631         {
18632             union
18633             {
18634                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
18635                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
18636             };
18637 
18638             union
18639             {
18640                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
18641 
18642                 struct
18643                 {
18644                     __IM uint8_t  RESERVED5;
18645                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
18646                 };
18647             };
18648         };
18649     };
18650 
18651     union
18652     {
18653         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
18654 
18655         struct
18656         {
18657             __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
18658             uint16_t               : 1;
18659             __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
18660             uint16_t               : 2;
18661             __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
18662             uint16_t               : 1;
18663             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
18664             uint16_t               : 2;
18665             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
18666             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
18667         } CFIFOSEL_b;
18668     };
18669 
18670     union
18671     {
18672         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
18673 
18674         struct
18675         {
18676             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
18677                                         *   data.                                                                     */
18678             uint16_t            : 1;
18679             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
18680             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
18681             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
18682         } CFIFOCTR_b;
18683     };
18684     __IM uint32_t RESERVED6;
18685 
18686     union
18687     {
18688         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
18689 
18690         struct
18691         {
18692             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
18693             uint16_t               : 4;
18694             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
18695             uint16_t               : 1;
18696             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
18697             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
18698             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
18699                                          *   Pipe Data is Read                                                         */
18700             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
18701             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
18702         } D0FIFOSEL_b;
18703     };
18704 
18705     union
18706     {
18707         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
18708 
18709         struct
18710         {
18711             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
18712                                         *   data.                                                                     */
18713             uint16_t            : 1;
18714             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
18715             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
18716             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
18717         } D0FIFOCTR_b;
18718     };
18719 
18720     union
18721     {
18722         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
18723 
18724         struct
18725         {
18726             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
18727             uint16_t               : 4;
18728             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
18729             uint16_t               : 1;
18730             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
18731             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
18732             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
18733                                          *   Pipe Data is Read                                                         */
18734             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
18735             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
18736         } D1FIFOSEL_b;
18737     };
18738 
18739     union
18740     {
18741         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
18742 
18743         struct
18744         {
18745             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
18746                                         *   data.                                                                     */
18747             uint16_t            : 1;
18748             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
18749             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
18750             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
18751         } D1FIFOCTR_b;
18752     };
18753 
18754     union
18755     {
18756         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
18757 
18758         struct
18759         {
18760             uint16_t             : 8;
18761             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
18762             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
18763             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
18764             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
18765             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
18766             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
18767             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
18768             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
18769         } INTENB0_b;
18770     };
18771 
18772     union
18773     {
18774         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
18775 
18776         struct
18777         {
18778             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
18779             uint16_t                  : 3;
18780             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
18781             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
18782             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
18783             uint16_t                  : 4;
18784             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
18785             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
18786             uint16_t                  : 1;
18787             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
18788             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
18789         } INTENB1_b;
18790     };
18791     __IM uint16_t RESERVED7;
18792 
18793     union
18794     {
18795         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
18796 
18797         struct
18798         {
18799             __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
18800             __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
18801             __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
18802             __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
18803             __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
18804             __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
18805             __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
18806             __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
18807             __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
18808             __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
18809             uint16_t                  : 6;
18810         } BRDYENB_b;
18811     };
18812 
18813     union
18814     {
18815         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
18816 
18817         struct
18818         {
18819             __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
18820             __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
18821             __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
18822             __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
18823             __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
18824             __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
18825             __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
18826             __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
18827             __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
18828             __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
18829             uint16_t                  : 6;
18830         } NRDYENB_b;
18831     };
18832 
18833     union
18834     {
18835         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
18836 
18837         struct
18838         {
18839             __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
18840             __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
18841             __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
18842             __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
18843             __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
18844             __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
18845             __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
18846             __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
18847             __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
18848             __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
18849             uint16_t                  : 6;
18850         } BEMPENB_b;
18851     };
18852 
18853     union
18854     {
18855         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
18856 
18857         struct
18858         {
18859             uint16_t                : 4;
18860             __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
18861             __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
18862             __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
18863             uint16_t                : 1;
18864             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
18865             uint16_t                : 7;
18866         } SOFCFG_b;
18867     };
18868 
18869     union
18870     {
18871         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
18872 
18873         struct
18874         {
18875             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
18876             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
18877             uint16_t                : 1;
18878             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
18879             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
18880             uint16_t                : 2;
18881             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
18882             uint16_t                : 1;
18883             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
18884             uint16_t                : 3;
18885             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
18886         } PHYSET_b;
18887     };
18888 
18889     union
18890     {
18891         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
18892 
18893         struct
18894         {
18895             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
18896             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
18897             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
18898             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
18899             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
18900             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
18901             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
18902             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
18903             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
18904             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
18905             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
18906             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
18907         } INTSTS0_b;
18908     };
18909 
18910     union
18911     {
18912         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
18913 
18914         struct
18915         {
18916             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
18917             uint16_t                 : 3;
18918             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
18919             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
18920             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
18921             uint16_t                 : 1;
18922             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
18923             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
18924             uint16_t                 : 1;
18925             __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
18926             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
18927             uint16_t                 : 1;
18928             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
18929             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
18930         } INTSTS1_b;
18931     };
18932     __IM uint16_t RESERVED8;
18933 
18934     union
18935     {
18936         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
18937 
18938         struct
18939         {
18940             __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
18941             __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
18942             __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
18943             __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
18944             __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
18945             __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
18946             __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
18947             __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
18948             __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
18949             __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
18950             uint16_t                 : 6;
18951         } BRDYSTS_b;
18952     };
18953 
18954     union
18955     {
18956         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
18957 
18958         struct
18959         {
18960             __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
18961             __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
18962             __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
18963             __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
18964             __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
18965             __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
18966             __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
18967             __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
18968             __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
18969             __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
18970             uint16_t                 : 6;
18971         } NRDYSTS_b;
18972     };
18973 
18974     union
18975     {
18976         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
18977 
18978         struct
18979         {
18980             __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
18981             __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
18982             __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
18983             __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
18984             __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
18985             __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
18986             __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
18987             __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
18988             __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
18989             __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
18990             uint16_t                 : 6;
18991         } BEMPSTS_b;
18992     };
18993 
18994     union
18995     {
18996         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
18997 
18998         struct
18999         {
19000             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
19001             uint16_t            : 3;
19002             __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
19003             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
19004         } FRMNUM_b;
19005     };
19006 
19007     union
19008     {
19009         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
19010 
19011         struct
19012         {
19013             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
19014             uint16_t             : 12;
19015             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
19016         } UFRMNUM_b;
19017     };
19018 
19019     union
19020     {
19021         __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
19022 
19023         struct
19024         {
19025             __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
19026                                            *   the USB address assigned by the host when the USBHS processed
19027                                            *   the SET_ADDRESS request successfully.                                     */
19028             uint16_t                 : 1;
19029             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
19030             uint16_t                 : 5;
19031         } USBADDR_b;
19032     };
19033     __IM uint16_t RESERVED9;
19034 
19035     union
19036     {
19037         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
19038 
19039         struct
19040         {
19041             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
19042                                                *   value.                                                                    */
19043             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
19044         } USBREQ_b;
19045     };
19046 
19047     union
19048     {
19049         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
19050 
19051         struct
19052         {
19053             __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
19054         } USBVAL_b;
19055     };
19056 
19057     union
19058     {
19059         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
19060 
19061         struct
19062         {
19063             __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
19064         } USBINDX_b;
19065     };
19066 
19067     union
19068     {
19069         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
19070 
19071         struct
19072         {
19073             __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
19074         } USBLENG_b;
19075     };
19076 
19077     union
19078     {
19079         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
19080 
19081         struct
19082         {
19083             uint16_t              : 4;
19084             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
19085             uint16_t              : 2;
19086             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
19087             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
19088             uint16_t              : 7;
19089         } DCPCFG_b;
19090     };
19091 
19092     union
19093     {
19094         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
19095 
19096         struct
19097         {
19098             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
19099                                         *   of data (maximum packet size) in payloads for the DCP.                    */
19100             uint16_t              : 5;
19101             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
19102         } DCPMAXP_b;
19103     };
19104 
19105     union
19106     {
19107         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
19108 
19109         struct
19110         {
19111             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
19112             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
19113             uint16_t                : 2;
19114             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
19115             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
19116             __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
19117             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
19118             uint16_t                : 2;
19119             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
19120             uint16_t                : 2;
19121             __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
19122             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
19123         } DCPCTR_b;
19124     };
19125     __IM uint16_t RESERVED10;
19126 
19127     union
19128     {
19129         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
19130 
19131         struct
19132         {
19133             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
19134             uint16_t               : 12;
19135         } PIPESEL_b;
19136     };
19137     __IM uint16_t RESERVED11;
19138 
19139     union
19140     {
19141         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
19142 
19143         struct
19144         {
19145             __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
19146                                         *   for the selected pipe.Setting 0000b means unused pipe.                    */
19147             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
19148             uint16_t              : 2;
19149             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
19150             uint16_t              : 1;
19151             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
19152             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
19153             uint16_t              : 3;
19154             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
19155         } PIPECFG_b;
19156     };
19157     __IM uint16_t RESERVED12;
19158 
19159     union
19160     {
19161         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
19162 
19163         struct
19164         {
19165             __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
19166                                         *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
19167                                         *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
19168                                         *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
19169                                         *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
19170             uint16_t              : 3;
19171             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
19172         } PIPEMAXP_b;
19173     };
19174 
19175     union
19176     {
19177         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
19178 
19179         struct
19180         {
19181             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
19182                                         *   error detection timing for the selected pipe in terms of
19183                                         *   frames, which is expressed as nth power of 2.                             */
19184             uint16_t            : 9;
19185             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
19186             uint16_t            : 3;
19187         } PIPEPERI_b;
19188     };
19189 
19190     union
19191     {
19192         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
19193 
19194         struct
19195         {
19196             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
19197             uint16_t              : 3;
19198             __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
19199             __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
19200             __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
19201             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
19202             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
19203             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
19204             uint16_t              : 1;
19205             __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
19206                                         *   Split Transaction of the relevant pipe                                    */
19207             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
19208                                         *   the CSSTS bit of the relevant pipe                                        */
19209             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
19210             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
19211         } PIPE_CTR_b[9];
19212     };
19213     __IM uint16_t                RESERVED13;
19214     __IM uint32_t                RESERVED14[3];
19215     __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
19216     __IM uint32_t                RESERVED15[3];
19217 
19218     union
19219     {
19220         __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
19221 
19222         struct
19223         {
19224             __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
19225             __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
19226             __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
19227             __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
19228             __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
19229             __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
19230             uint16_t                  : 1;
19231             __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
19232             __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
19233             __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
19234             uint16_t                  : 6;
19235         } USBBCCTRL0_b;
19236     };
19237     __IM uint16_t RESERVED16;
19238     __IM uint32_t RESERVED17[4];
19239 
19240     union
19241     {
19242         __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
19243 
19244         struct
19245         {
19246             __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
19247             uint16_t               : 15;
19248         } UCKSEL_b;
19249     };
19250     __IM uint16_t RESERVED18;
19251     __IM uint32_t RESERVED19;
19252 
19253     union
19254     {
19255         __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
19256 
19257         struct
19258         {
19259             __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
19260             uint16_t               : 6;
19261             __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
19262             uint16_t               : 8;
19263         } USBMC_b;
19264     };
19265     __IM uint16_t RESERVED20;
19266 
19267     union
19268     {
19269         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
19270 
19271         struct
19272         {
19273             uint16_t               : 6;
19274             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
19275             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
19276             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
19277             uint16_t               : 1;
19278         } DEVADD_b[10];
19279     };
19280     __IM uint32_t RESERVED21[3];
19281 
19282     union
19283     {
19284         __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
19285 
19286         struct
19287         {
19288             __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
19289             __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
19290             __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
19291             __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
19292             uint32_t               : 28;
19293         } PHYSLEW_b;
19294     };
19295     __IM uint32_t RESERVED22[3];
19296 
19297     union
19298     {
19299         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
19300 
19301         struct
19302         {
19303             uint16_t             : 7;
19304             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
19305             uint16_t             : 8;
19306         } LPCTRL_b;
19307     };
19308 
19309     union
19310     {
19311         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
19312 
19313         struct
19314         {
19315             uint16_t                : 14;
19316             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
19317             uint16_t                : 1;
19318         } LPSTS_b;
19319     };
19320     __IM uint32_t RESERVED23[15];
19321 
19322     union
19323     {
19324         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
19325 
19326         struct
19327         {
19328             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
19329             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
19330             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
19331             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
19332             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
19333             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
19334             uint16_t                : 2;
19335             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
19336             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
19337             uint16_t                : 6;
19338         } BCCTRL_b;
19339     };
19340     __IM uint16_t RESERVED24;
19341 
19342     union
19343     {
19344         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
19345 
19346         struct
19347         {
19348             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
19349             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
19350             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
19351                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
19352             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
19353                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
19354             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
19355                                           *   value used for L1NEGOMD.The format is the same as the HIRD
19356                                           *   field in HL1CTRL.                                                         */
19357             uint16_t               : 2;
19358             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
19359             uint16_t               : 1;
19360         } PL1CTRL1_b;
19361     };
19362 
19363     union
19364     {
19365         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
19366 
19367         struct
19368         {
19369             uint16_t               : 8;
19370             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
19371             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
19372             uint16_t               : 3;
19373         } PL1CTRL2_b;
19374     };
19375 
19376     union
19377     {
19378         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
19379 
19380         struct
19381         {
19382             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
19383             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
19384             uint16_t                : 13;
19385         } HL1CTRL1_b;
19386     };
19387 
19388     union
19389     {
19390         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
19391 
19392         struct
19393         {
19394             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
19395                                         *   be set in the ADDR field of LPM token.                                    */
19396             uint16_t             : 4;
19397             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
19398             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
19399                                         *   value to be set in the RWE field of LPM token.                            */
19400             uint16_t            : 2;
19401             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
19402                                         *   period at the time of L1 Resume.                                          */
19403         } HL1CTRL2_b;
19404     };
19405     __IM uint32_t RESERVED25[5];
19406 
19407     union
19408     {
19409         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
19410                                         *                  Register                                                   */
19411 
19412         struct
19413         {
19414             uint32_t              : 20;
19415             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
19416                                          *   HS side of USB port.                                                      */
19417             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
19418                                          *   HS side of USB port.                                                      */
19419             uint32_t               : 1;
19420             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
19421                                          *   of USB port.                                                              */
19422             uint32_t : 8;
19423         } DPUSR0R_b;
19424     };
19425 
19426     union
19427     {
19428         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
19429 
19430         struct
19431         {
19432             uint32_t                : 4;
19433             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
19434             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
19435             uint32_t                : 1;
19436             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
19437             uint32_t                : 12;
19438             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
19439             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
19440             uint32_t                : 1;
19441             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
19442             uint32_t                : 8;
19443         } DPUSR1R_b;
19444     };
19445 
19446     union
19447     {
19448         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
19449 
19450         struct
19451         {
19452             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
19453             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
19454             uint16_t            : 2;
19455             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
19456                                         *   port.                                                                     */
19457             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
19458                                         *   port.                                                                     */
19459             uint16_t              : 2;
19460             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
19461             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
19462             uint16_t              : 6;
19463         } DPUSR2R_b;
19464     };
19465 
19466     union
19467     {
19468         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
19469 
19470         struct
19471         {
19472             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
19473             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
19474             uint16_t                : 14;
19475         } DPUSRCR_b;
19476     };
19477     __IM uint32_t RESERVED26[165];
19478 
19479     union
19480     {
19481         __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
19482                                          *                  Monitor Register                                           */
19483 
19484         struct
19485         {
19486             __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
19487             __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
19488             uint32_t               : 1;
19489             __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
19490             __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
19491             uint32_t               : 11;
19492             __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
19493             __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
19494             uint32_t               : 2;
19495             __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
19496                                          *   of the USB.                                                               */
19497             __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
19498                                          *   of the USB.                                                               */
19499             uint32_t              : 1;
19500             __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
19501                                          *   USB.                                                                      */
19502             uint32_t : 8;
19503         } DPUSR0R_FS_b;
19504     };
19505 
19506     union
19507     {
19508         __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
19509                                            *                  Register                                                   */
19510 
19511         struct
19512         {
19513             __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
19514             __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
19515             uint32_t                 : 2;
19516             __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
19517             __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
19518             uint32_t                 : 1;
19519             __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
19520             uint32_t                 : 8;
19521             __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
19522             __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
19523             uint32_t                 : 2;
19524             __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
19525             __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
19526             uint32_t                 : 1;
19527             __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
19528             uint32_t                 : 8;
19529         } DPUSR1R_FS_b;
19530     };
19531 } R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
19532 
19533 /* =========================================================================================================================== */
19534 /* ================                                           R_WDT                                           ================ */
19535 /* =========================================================================================================================== */
19536 
19537 /**
19538  * @brief Watchdog Timer (R_WDT)
19539  */
19540 
19541 typedef struct                         /*!< (@ 0x40202600) R_WDT Structure                                            */
19542 {
19543     union
19544     {
19545         __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
19546 
19547         struct
19548         {
19549             __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
19550                                         *   of the WDT.                                                               */
19551         } WDTRR_b;
19552     };
19553     __IM uint8_t RESERVED;
19554 
19555     union
19556     {
19557         __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
19558 
19559         struct
19560         {
19561             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
19562             uint16_t            : 2;
19563             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
19564             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
19565             uint16_t            : 2;
19566             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
19567             uint16_t            : 2;
19568         } WDTCR_b;
19569     };
19570 
19571     union
19572     {
19573         __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
19574 
19575         struct
19576         {
19577             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
19578             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
19579             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
19580         } WDTSR_b;
19581     };
19582 
19583     union
19584     {
19585         __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
19586 
19587         struct
19588         {
19589             uint8_t               : 7;
19590             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
19591         } WDTRCR_b;
19592     };
19593     __IM uint8_t RESERVED1;
19594 
19595     union
19596     {
19597         __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
19598 
19599         struct
19600         {
19601             uint8_t              : 7;
19602             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
19603         } WDTCSTPR_b;
19604     };
19605     __IM uint8_t  RESERVED2;
19606     __IM uint16_t RESERVED3;
19607 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
19608 
19609 /* =========================================================================================================================== */
19610 /* ================                                           R_TZF                                           ================ */
19611 /* =========================================================================================================================== */
19612 
19613 /**
19614  * @brief TrustZone Filter (R_TZF)
19615  */
19616 
19617 typedef struct                         /*!< (@ 0x40004000) R_TZF Structure                                            */
19618 {
19619     __IM uint16_t RESERVED[8];
19620 
19621     union
19622     {
19623         __IOM uint16_t TZFOAD;         /*!< (@ 0x00000010) TrustZone Filter Operation After Detection register        */
19624 
19625         struct
19626         {
19627             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
19628             uint16_t           : 7;
19629             __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code                                                          */
19630         } TZFOAD_b;
19631     };
19632     __IM uint16_t RESERVED1;
19633 
19634     union
19635     {
19636         __IOM uint16_t TZFPT;           /*!< (@ 0x00000014) TrustZone Filter Protect register                          */
19637 
19638         struct
19639         {
19640             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
19641             uint16_t               : 7;
19642             __OM uint16_t KEY      : 8; /*!< [15..8] Key Code                                                          */
19643         } TZFPT_b;
19644     };
19645 } R_TZF_Type;                           /*!< Size = 22 (0x16)                                                          */
19646 
19647 /* =========================================================================================================================== */
19648 /* ================                                          R_CPSCU                                          ================ */
19649 /* =========================================================================================================================== */
19650 
19651 /**
19652  * @brief CPU System Security Control Unit (R_CPSCU)
19653  */
19654 
19655 typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure                                          */
19656 {
19657     union
19658     {
19659         __IOM uint32_t CSAR;             /*!< (@ 0x00000000) Cache Security Attribution Register                        */
19660 
19661         struct
19662         {
19663             __IOM uint32_t CACHESA  : 1; /*!< [0..0] Security Attributes of Registers for Cache Control                 */
19664             __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration      */
19665             __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error                   */
19666             uint32_t                : 29;
19667         } CSAR_b;
19668     };
19669     __IM uint32_t RESERVED[3];
19670 
19671     union
19672     {
19673         __IOM uint32_t SRAMSAR;         /*!< (@ 0x00000010) SRAM Security Attribution Register                         */
19674 
19675         struct
19676         {
19677             __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection               */
19678             __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
19679                                          *   2                                                                         */
19680             __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation                  */
19681             uint32_t               : 29;
19682         } SRAMSAR_b;
19683     };
19684 
19685     union
19686     {
19687         __IOM uint32_t STBRAMSAR;       /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register           */
19688 
19689         struct
19690         {
19691             __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM                 */
19692             uint32_t               : 28;
19693         } STBRAMSAR_b;
19694     };
19695     __IM uint32_t RESERVED1[6];
19696 
19697     union
19698     {
19699         __IOM uint32_t DTCSAR;          /*!< (@ 0x00000030) DTC Controller Security Attribution Register               */
19700 
19701         struct
19702         {
19703             __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution                                           */
19704             uint32_t               : 31;
19705         } DTCSAR_b;
19706     };
19707 
19708     union
19709     {
19710         __IOM uint32_t DMACSAR;         /*!< (@ 0x00000034) DMAC Controller Security Attribution Register              */
19711 
19712         struct
19713         {
19714             __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution                                         */
19715             uint32_t               : 31;
19716         } DMACSAR_b;
19717     };
19718     __IM uint32_t RESERVED2[2];
19719 
19720     union
19721     {
19722         __IOM uint32_t ICUSARA;           /*!< (@ 0x00000040) ICU Security Attribution Register A                        */
19723 
19724         struct
19725         {
19726             __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers         */
19727             uint32_t                : 16;
19728         } ICUSARA_b;
19729     };
19730 
19731     union
19732     {
19733         __IOM uint32_t ICUSARB;        /*!< (@ 0x00000044) ICU Security Attribution Register B                        */
19734 
19735         struct
19736         {
19737             __IOM uint32_t SANMI : 1;  /*!< [0..0] Security Attributes of nonmaskable interrupt                       */
19738             uint32_t             : 31;
19739         } ICUSARB_b;
19740     };
19741 
19742     union
19743     {
19744         __IOM uint32_t ICUSARC;         /*!< (@ 0x00000048) ICU Security Attribution Register C                        */
19745 
19746         struct
19747         {
19748             __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel                  */
19749             uint32_t               : 24;
19750         } ICUSARC_b;
19751     };
19752 
19753     union
19754     {
19755         __IOM uint32_t ICUSARD;          /*!< (@ 0x0000004C) ICU Security Attribution Register D                        */
19756 
19757         struct
19758         {
19759             __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0                        */
19760             uint32_t                : 31;
19761         } ICUSARD_b;
19762     };
19763 
19764     union
19765     {
19766         __IOM uint32_t ICUSARE;        /*!< (@ 0x00000050) ICU Security Attribution Register E                        */
19767 
19768         struct
19769         {
19770             uint32_t                   : 16;
19771             __IOM uint32_t SAIWDTWUP   : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16                 */
19772             uint32_t                   : 1;
19773             __IOM uint32_t SALVD1WUP   : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18                 */
19774             __IOM uint32_t SALVD2WUP   : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19                 */
19775             __IOM uint32_t SAVBATTWUP  : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20                 */
19776             uint32_t                   : 3;
19777             __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24                 */
19778             __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25                 */
19779             uint32_t                   : 1;
19780             __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27                 */
19781             __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28                 */
19782             __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29                 */
19783             __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30                 */
19784             __IOM uint32_t SAIIC0WUP   : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31                 */
19785         } ICUSARE_b;
19786     };
19787 
19788     union
19789     {
19790         __IOM uint32_t ICUSARF;              /*!< (@ 0x00000054) ICU Security Attribution Register F                        */
19791 
19792         struct
19793         {
19794             __IOM uint32_t SAAGT3UDWUP  : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0                    */
19795             __IOM uint32_t SAAGT3CAWUP  : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1                    */
19796             __IOM uint32_t SAAGT3CBWUP  : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2                    */
19797             __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3                    */
19798             uint32_t                    : 4;
19799             __IOM uint32_t SAULP0UWUP   : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8                    */
19800             __IOM uint32_t SAULP0AWUP   : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9                    */
19801             __IOM uint32_t SAULP0BWUP   : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10                 */
19802             __IOM uint32_t SAI3CWUP     : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11                 */
19803             __IOM uint32_t SAULP1UWUP   : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12                 */
19804             __IOM uint32_t SAULP1AWUP   : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13                 */
19805             __IOM uint32_t SAULP1BWUP   : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14                 */
19806             uint32_t                    : 17;
19807         } ICUSARF_b;
19808     };
19809     __IM uint32_t RESERVED3[6];
19810 
19811     union
19812     {
19813         __IOM uint32_t ICUSARG;           /*!< (@ 0x00000070) ICU Security Attribution Register G                        */
19814 
19815         struct
19816         {
19817             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0            */
19818         } ICUSARG_b;
19819     };
19820 
19821     union
19822     {
19823         __IOM uint32_t ICUSARH;           /*!< (@ 0x00000074) ICU Security Attribution Register H                        */
19824 
19825         struct
19826         {
19827             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32           */
19828         } ICUSARH_b;
19829     };
19830 
19831     union
19832     {
19833         __IOM uint32_t ICUSARI;           /*!< (@ 0x00000078) ICU Security Attribution Register I                        */
19834 
19835         struct
19836         {
19837             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64           */
19838         } ICUSARI_b;
19839     };
19840     __IM uint32_t RESERVED4[33];
19841 
19842     union
19843     {
19844         __IOM uint32_t BUSSARA;        /*!< (@ 0x00000100) Bus Security Attribution Register A                        */
19845 
19846         struct
19847         {
19848             __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0                                        */
19849             uint32_t              : 31;
19850         } BUSSARA_b;
19851     };
19852 
19853     union
19854     {
19855         __IOM uint32_t BUSSARB;        /*!< (@ 0x00000104) Bus Security Attribution Register B                        */
19856 
19857         struct
19858         {
19859             __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0                                        */
19860             uint32_t              : 31;
19861         } BUSSARB_b;
19862     };
19863     __IM uint32_t RESERVED5[10];
19864 
19865     union
19866     {
19867         __IOM uint32_t MMPUSARA;         /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
19868                                           *                  Register A                                                 */
19869 
19870         struct
19871         {
19872             __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7)                           */
19873             uint32_t                : 24;
19874         } MMPUSARA_b;
19875     };
19876 
19877     union
19878     {
19879         __IOM uint32_t MMPUSARB;         /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
19880                                           *                  Register B                                                 */
19881 
19882         struct
19883         {
19884             __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution                                        */
19885             uint32_t                : 31;
19886         } MMPUSARB_b;
19887     };
19888     __IM uint32_t RESERVED6[26];
19889 
19890     union
19891     {
19892         __IOM uint32_t DMACCHSAR;          /*!< (@ 0x000001A0) DMA channel Security Attribution Register                  */
19893 
19894         struct
19895         {
19896             __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
19897                                             *   channel                                                                   */
19898             uint32_t : 24;
19899         } DMACCHSAR_b;
19900     };
19901     __IM uint32_t RESERVED7[3];
19902 
19903     union
19904     {
19905         __IOM uint32_t CPUDSAR;         /*!< (@ 0x000001B0) CPU Debug Security Attribution Register                    */
19906 
19907         struct
19908         {
19909             __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0                                   */
19910             uint32_t               : 31;
19911         } CPUDSAR_b;
19912     };
19913     __IM uint32_t RESERVED8[147];
19914 
19915     union
19916     {
19917         __IOM uint32_t SRAMSABAR0;     /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register
19918                                         *                  0                                                          */
19919 
19920         struct
19921         {
19922             uint32_t                 : 13;
19923             __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
19924                                            *   address of non-secure region).                                            */
19925             uint32_t : 11;
19926         } SRAMSABAR0_b;
19927     };
19928 
19929     union
19930     {
19931         __IOM uint32_t SRAMSABAR1;     /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register
19932                                         *                  1                                                          */
19933 
19934         struct
19935         {
19936             uint32_t                 : 13;
19937             __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
19938                                            *   address of non-secure region).                                            */
19939             uint32_t : 11;
19940         } SRAMSABAR1_b;
19941     };
19942     __IM uint32_t RESERVED9[126];
19943 
19944     union
19945     {
19946         __IOM uint32_t TEVTRCR;        /*!< (@ 0x00000600) Trusted Event Route Control Register                       */
19947 
19948         struct
19949         {
19950             __IOM uint32_t TEVTE : 1;  /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
19951                                         *   and ELCSRn                                                                */
19952             uint32_t : 31;
19953         } TEVTRCR_b;
19954     };
19955 } R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
19956 
19957 /* =========================================================================================================================== */
19958 /* ================                                          R_DOC_B                                          ================ */
19959 /* =========================================================================================================================== */
19960 
19961 /**
19962  * @brief Data Operation Circuit (R_DOC_B)
19963  */
19964 
19965 typedef struct                         /*!< (@ 0x40311000) R_DOC_B Structure                                          */
19966 {
19967     union
19968     {
19969         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
19970 
19971         struct
19972         {
19973             __IOM uint8_t OMS   : 2;   /*!< [1..0] Operating Mode Select                                              */
19974             uint8_t             : 1;
19975             __IOM uint8_t DOBW  : 1;   /*!< [3..3] Data Operation Bit Width Select                                    */
19976             __IOM uint8_t DCSEL : 3;   /*!< [6..4] Detection Condition Select                                         */
19977             uint8_t             : 1;
19978         } DOCR_b;
19979     };
19980     __IM uint8_t  RESERVED;
19981     __IM uint16_t RESERVED1;
19982 
19983     union
19984     {
19985         __IOM uint8_t DOSR;            /*!< (@ 0x00000004) DOC Flag Status Register                                   */
19986 
19987         struct
19988         {
19989             __IM uint8_t DOPCF : 1;    /*!< [0..0] Data Operation Circuit Flag                                        */
19990             uint8_t            : 7;
19991         } DOSR_b;
19992     };
19993     __IM uint8_t  RESERVED2;
19994     __IM uint16_t RESERVED3;
19995 
19996     union
19997     {
19998         __IOM uint8_t DOSCR;           /*!< (@ 0x00000008) DOC Flag Status Clear Register                             */
19999 
20000         struct
20001         {
20002             __OM uint8_t DOPCFCL : 1;  /*!< [0..0] DOPCF Clear                                                        */
20003             uint8_t              : 7;
20004         } DOSCR_b;
20005     };
20006     __IM uint8_t   RESERVED4;
20007     __IM uint16_t  RESERVED5;
20008     __IOM uint32_t DODIR;              /*!< (@ 0x0000000C) DOC Data Input Register                                    */
20009     __IOM uint32_t DODSR0;             /*!< (@ 0x00000010) DOC Data Setting Register 0                                */
20010     __IOM uint32_t DODSR1;             /*!< (@ 0x00000014) DOC Data Setting Register 1                                */
20011 } R_DOC_B_Type;                        /*!< Size = 24 (0x18)                                                          */
20012 
20013 /* =========================================================================================================================== */
20014 /* ================                                         R_SCI_B0                                          ================ */
20015 /* =========================================================================================================================== */
20016 
20017 /**
20018  * @brief Serial Communication Interface 0 (R_SCI_B0)
20019  */
20020 
20021 typedef struct                         /*!< (@ 0x40358000) R_SCI_B0 Structure                                         */
20022 {
20023     union
20024     {
20025         union
20026         {
20027             __IM uint32_t RDR;          /*!< (@ 0x00000000) Receive Data Register                                      */
20028 
20029             struct
20030             {
20031                 __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data                                                */
20032                 __IM uint32_t MPB  : 1; /*!< [9..9] Multi-processor flag                                               */
20033                 __IM uint32_t DR   : 1; /*!< [10..10] Receive data ready flag                                          */
20034                 __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag                                           */
20035                 __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag                                          */
20036                 uint32_t           : 11;
20037                 __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag                                               */
20038                 uint32_t           : 2;
20039                 __IM uint32_t PER  : 1; /*!< [27..27] Parity error flag                                                */
20040                 __IM uint32_t FER  : 1; /*!< [28..28] Framing error flag                                               */
20041                 uint32_t           : 3;
20042             } RDR_b;
20043         };
20044 
20045         union
20046         {
20047             __IOM uint8_t RDR_BY;       /*!< (@ 0x00000000) Receive Data Register (byte access)                        */
20048 
20049             struct
20050             {
20051                 __IOM uint8_t RDAT : 8; /*!< [7..0] Serial receive data                                                */
20052             } RDR_BY_b;
20053         };
20054     };
20055 
20056     union
20057     {
20058         union
20059         {
20060             __IOM uint32_t TDR;           /*!< (@ 0x00000004) Transmit Data Register                                     */
20061 
20062             struct
20063             {
20064                 __IOM uint32_t TDAT  : 9; /*!< [8..0] Serial transmit data                                               */
20065                 __IOM uint32_t MPBT  : 1; /*!< [9..9] Multi-processor transfer bit flag                                  */
20066                 uint32_t             : 2;
20067                 __IOM uint32_t TSYNC : 1; /*!< [12..12] Transmit SYNC data                                               */
20068                 uint32_t             : 19;
20069             } TDR_b;
20070         };
20071 
20072         union
20073         {
20074             __IOM uint8_t TDR_BY;       /*!< (@ 0x00000004) Transmit Data Register (byte access)                       */
20075 
20076             struct
20077             {
20078                 __IOM uint8_t TDAT : 8; /*!< [7..0] Serial transmit data                                               */
20079             } TDR_BY_b;
20080         };
20081     };
20082 
20083     union
20084     {
20085         __IOM uint32_t CCR0;           /*!< (@ 0x00000008) Common Control Register 0                                  */
20086 
20087         struct
20088         {
20089             __IOM uint32_t RE    : 1;  /*!< [0..0] Receive Enable                                                     */
20090             uint32_t             : 3;
20091             __IOM uint32_t TE    : 1;  /*!< [4..4] Transmit Enable                                                    */
20092             uint32_t             : 3;
20093             __IOM uint32_t MPIE  : 1;  /*!< [8..8] Multi-Processor Interrupt Enable                                   */
20094             __IOM uint32_t DCME  : 1;  /*!< [9..9] Data Compare Match Enable                                          */
20095             __IOM uint32_t IDSEL : 1;  /*!< [10..10] ID frame select                                                  */
20096             uint32_t             : 5;
20097             __IOM uint32_t RIE   : 1;  /*!< [16..16] Receive Interrupt Enable                                         */
20098             uint32_t             : 3;
20099             __IOM uint32_t TIE   : 1;  /*!< [20..20] Transmit Interrupt Enable                                        */
20100             __IOM uint32_t TEIE  : 1;  /*!< [21..21] Transmit End Interrupt Enable                                    */
20101             uint32_t             : 2;
20102             __IOM uint32_t SSE   : 1;  /*!< [24..24] SSn Pin Function Enable                                          */
20103             uint32_t             : 7;
20104         } CCR0_b;
20105     };
20106 
20107     union
20108     {
20109         __IOM uint32_t CCR1;           /*!< (@ 0x0000000C) Common Control Register 1                                  */
20110 
20111         struct
20112         {
20113             __IOM uint32_t CTSE   : 1; /*!< [0..0] CTS Enable                                                         */
20114             __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable                                            */
20115             uint32_t              : 2;
20116             __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select                                      */
20117             __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O                                              */
20118             uint32_t              : 2;
20119             __IOM uint32_t PE     : 1; /*!< [8..8] Parity Enable                                                      */
20120             __IOM uint32_t PM     : 1; /*!< [9..9] Parity Mode                                                        */
20121             uint32_t              : 2;
20122             __IOM uint32_t TINV   : 1; /*!< [12..12] TXD invert                                                       */
20123             __IOM uint32_t RINV   : 1; /*!< [13..13] RXD invert                                                       */
20124             uint32_t              : 2;
20125             __IOM uint32_t SPLP   : 1; /*!< [16..16] Loopback Control                                                 */
20126             uint32_t              : 3;
20127             __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select                                 */
20128             uint32_t              : 3;
20129             __IOM uint32_t NFCS   : 3; /*!< [26..24] Noise Filter Clock Select                                        */
20130             uint32_t              : 1;
20131             __IOM uint32_t NFEN   : 1; /*!< [28..28] Digital Noise Filter Function Enable                             */
20132             uint32_t              : 3;
20133         } CCR1_b;
20134     };
20135 
20136     union
20137     {
20138         __IOM uint32_t CCR2;           /*!< (@ 0x00000010) Common Control Register 2                                  */
20139 
20140         struct
20141         {
20142             __IOM uint32_t BCP   : 3;  /*!< [2..0] Base Clock Pulse                                                   */
20143             uint32_t             : 1;
20144             __IOM uint32_t BGDM  : 1;  /*!< [4..4] Baud Rate Generator Double-Speed Mode Select                       */
20145             __IOM uint32_t ABCS  : 1;  /*!< [5..5] Asynchronous Mode Base Clock Select                                */
20146             __IOM uint32_t ABCSE : 1;  /*!< [6..6] Asynchronous Mode Extended Base Clock Select                       */
20147             uint32_t             : 1;
20148             __IOM uint32_t BRR   : 8;  /*!< [15..8] Bit rate setting                                                  */
20149             __IOM uint32_t BRME  : 1;  /*!< [16..16] Bit Modulation Enable                                            */
20150             uint32_t             : 3;
20151             __IOM uint32_t CKS   : 2;  /*!< [21..20] Clock Select                                                     */
20152             uint32_t             : 2;
20153             __IOM uint32_t MDDR  : 8;  /*!< [31..24] Modulation Duty Setting                                          */
20154         } CCR2_b;
20155     };
20156 
20157     union
20158     {
20159         __IOM uint32_t CCR3;            /*!< (@ 0x00000014) Common Control Register 3                                  */
20160 
20161         struct
20162         {
20163             __IOM uint32_t CPHA    : 1; /*!< [0..0] Clock Phase Select                                                 */
20164             __IOM uint32_t CPOL    : 1; /*!< [1..1] Clock Polarity Select                                              */
20165             uint32_t               : 5;
20166             __IOM uint32_t BPEN    : 1; /*!< [7..7] Synchronizer bypass enable                                         */
20167             __IOM uint32_t CHR     : 2; /*!< [9..8] Character Length                                                   */
20168             uint32_t               : 2;
20169             __IOM uint32_t LSBF    : 1; /*!< [12..12] LSB First select                                                 */
20170             __IOM uint32_t SINV    : 1; /*!< [13..13] Transmitted/Received Data Invert                                 */
20171             __IOM uint32_t STP     : 1; /*!< [14..14] Stop Bit Length                                                  */
20172             __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select                     */
20173             __IOM uint32_t MOD     : 3; /*!< [18..16] Communication mode select                                        */
20174             __IOM uint32_t MP      : 1; /*!< [19..19] Multi-Processor Mode                                             */
20175             __IOM uint32_t FM      : 1; /*!< [20..20] FIFO Mode select                                                 */
20176             __IOM uint32_t DEN     : 1; /*!< [21..21] Driver enable                                                    */
20177             uint32_t               : 2;
20178             __IOM uint32_t CKE     : 2; /*!< [25..24] Clock enable                                                     */
20179             uint32_t               : 2;
20180             __IOM uint32_t GM      : 1; /*!< [28..28] GSM Mode                                                         */
20181             __IOM uint32_t BLK     : 1; /*!< [29..29] Block Transfer Mode                                              */
20182             uint32_t               : 2;
20183         } CCR3_b;
20184     };
20185 
20186     union
20187     {
20188         __IOM uint32_t CCR4;           /*!< (@ 0x00000018) Common Control Register 4                                  */
20189 
20190         struct
20191         {
20192             __IOM uint32_t CMPD   : 9; /*!< [8..0] Compare Match Data                                                 */
20193             uint32_t              : 7;
20194             __IOM uint32_t ASEN   : 1; /*!< [16..16] Adjust receive sampling timing enable                            */
20195             __IOM uint32_t ATEN   : 1; /*!< [17..17] Adjust transmit timing enable                                    */
20196             uint32_t              : 1;
20197             __IOM uint32_t SCKSEL : 1; /*!< [19..19] Master receive clock selection bit.                              */
20198             uint32_t              : 4;
20199             __IOM uint32_t AST    : 3; /*!< [26..24] Adjustment value for receive Sampling Timing                     */
20200             __IOM uint32_t AJD    : 1; /*!< [27..27] Adjustment Direction for receive sampling timing                 */
20201             __IOM uint32_t ATT    : 3; /*!< [30..28] Adjustment value for Transmit timing                             */
20202             __IOM uint32_t AET    : 1; /*!< [31..31] Adjustment edge for transmit timing                              */
20203         } CCR4_b;
20204     };
20205 
20206     union
20207     {
20208         __IM uint8_t CESR;             /*!< (@ 0x0000001C) Communication Enable Status Register                       */
20209 
20210         struct
20211         {
20212             __IM uint8_t RIST : 1;     /*!< [0..0] RE Internal status                                                 */
20213             uint8_t           : 3;
20214             __IM uint8_t TIST : 1;     /*!< [4..4] TE Internal status                                                 */
20215             uint8_t           : 3;
20216         } CESR_b;
20217     };
20218     __IM uint8_t  RESERVED;
20219     __IM uint16_t RESERVED1;
20220 
20221     union
20222     {
20223         __IOM uint32_t ICR;                /*!< (@ 0x00000020) Simple I2C Control Register                                */
20224 
20225         struct
20226         {
20227             __IOM uint32_t IICDL      : 5; /*!< [4..0] SDA Delay Output Select                                            */
20228             uint32_t                  : 3;
20229             __IOM uint32_t IICINTM    : 1; /*!< [8..8] IIC Interrupt Mode Select                                          */
20230             __IOM uint32_t IICCSC     : 1; /*!< [9..9] Clock Synchronization                                              */
20231             uint32_t                  : 3;
20232             __IOM uint32_t IICACKT    : 1; /*!< [13..13] ACK Transmission Data                                            */
20233             uint32_t                  : 2;
20234             __IOM uint32_t IICSTAREQ  : 1; /*!< [16..16] Start Condition Generation                                       */
20235             __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] Restart Condition Generation                                     */
20236             __IOM uint32_t IICSTPREQ  : 1; /*!< [18..18] Stop Condition Generation                                        */
20237             uint32_t                  : 1;
20238             __IOM uint32_t IICSDAS    : 2; /*!< [21..20] SDA Output Select                                                */
20239             __IOM uint32_t IICSCLS    : 2; /*!< [23..22] SCL Output Select                                                */
20240             uint32_t                  : 8;
20241         } ICR_b;
20242     };
20243 
20244     union
20245     {
20246         __IOM uint32_t FCR;            /*!< (@ 0x00000024) FIFO Control Register                                      */
20247 
20248         struct
20249         {
20250             __IOM uint32_t DRES  : 1;  /*!< [0..0] Receive data ready error select bit                                */
20251             uint32_t             : 7;
20252             __IOM uint32_t TTRG  : 5;  /*!< [12..8] Transmit FIFO data trigger number                                 */
20253             uint32_t             : 2;
20254             __OM uint32_t  TFRST : 1;  /*!< [15..15] Transmit FIFO Data Register Reset                                */
20255             __IOM uint32_t RTRG  : 5;  /*!< [20..16] Receive FIFO data trigger number                                 */
20256             uint32_t             : 2;
20257             __OM uint32_t  RFRST : 1;  /*!< [23..23] Receive FIFO Data Register Reset                                 */
20258             __IOM uint32_t RSTRG : 5;  /*!< [28..24] RTS Output Active Trigger Number Select                          */
20259             uint32_t             : 3;
20260         } FCR_b;
20261     };
20262     __IM uint32_t RESERVED2;
20263 
20264     union
20265     {
20266         __IOM uint32_t MCR;            /*!< (@ 0x0000002C) Manchester Control Register                                */
20267 
20268         struct
20269         {
20270             __IOM uint32_t RMPOL  : 1; /*!< [0..0] Polarity of Received Manchester Code                               */
20271             __IOM uint32_t TMPOL  : 1; /*!< [1..1] Polarity of Transmit Manchester Code                               */
20272             __IOM uint32_t ERTEN  : 1; /*!< [2..2] Manchester Edge Retiming Enable                                    */
20273             uint32_t              : 1;
20274             __IOM uint32_t SYNVAL : 1; /*!< [4..4] SYNC value Setting                                                 */
20275             __IOM uint32_t SYNSEL : 1; /*!< [5..5] SYNC Select                                                        */
20276             __IOM uint32_t SBSEL  : 1; /*!< [6..6] Start Bit Select                                                   */
20277             uint32_t              : 1;
20278             __IOM uint32_t TPLEN  : 4; /*!< [11..8] Transmit preface length                                           */
20279             __IOM uint32_t TPPAT  : 2; /*!< [13..12] Transmit preface pattern                                         */
20280             uint32_t              : 2;
20281             __IOM uint32_t RPLEN  : 4; /*!< [19..16] Receive Preface Length                                           */
20282             __IOM uint32_t RPPAT  : 2; /*!< [21..20] Receive Preface Pattern                                          */
20283             uint32_t              : 2;
20284             __IOM uint32_t PFEREN : 1; /*!< [24..24] Preface Error Enable                                             */
20285             __IOM uint32_t SYEREN : 1; /*!< [25..25] Receive SYNC Error Enable                                        */
20286             __IOM uint32_t SBEREN : 1; /*!< [26..26] Start Bit Error Enable                                           */
20287             uint32_t              : 5;
20288         } MCR_b;
20289     };
20290 
20291     union
20292     {
20293         __IOM uint32_t DCR;            /*!< (@ 0x00000030) Driver Control Register                                    */
20294 
20295         struct
20296         {
20297             __IOM uint32_t DEPOL : 1;  /*!< [0..0] Driver effective polarity select                                   */
20298             uint32_t             : 7;
20299             __IOM uint32_t DEAST : 5;  /*!< [12..8] Driver Assertion Time                                             */
20300             uint32_t             : 3;
20301             __IOM uint32_t DENGT : 5;  /*!< [20..16] Driver negate time                                               */
20302             uint32_t             : 11;
20303         } DCR_b;
20304     };
20305 
20306     union
20307     {
20308         __IOM uint32_t XCR0;           /*!< (@ 0x00000034) Simple LIN(SCIX) Control Register 0                        */
20309 
20310         struct
20311         {
20312             __IOM uint32_t TCSS  : 2;  /*!< [1..0] Timer count clock source selection                                 */
20313             uint32_t             : 6;
20314             __IOM uint32_t BFE   : 1;  /*!< [8..8] Break Field enable                                                 */
20315             __IOM uint32_t CF0RE : 1;  /*!< [9..9] Control Field 0 enable                                             */
20316             __IOM uint32_t CF1DS : 2;  /*!< [11..10] Control Field1 compare data select                               */
20317             __IOM uint32_t PIBE  : 1;  /*!< [12..12] Priority interrupt bit enable                                    */
20318             __IOM uint32_t PIBS  : 3;  /*!< [15..13] Priority interrupt bit select                                    */
20319             __IOM uint32_t BFOIE : 1;  /*!< [16..16] Break Field output completion interrupt enable                   */
20320             __IOM uint32_t BCDIE : 1;  /*!< [17..17] Bus conflict detection interrupt enable                          */
20321             uint32_t             : 2;
20322             __IOM uint32_t BFDIE : 1;  /*!< [20..20] Break Field detection interrupt enable                           */
20323             __IOM uint32_t COFIE : 1;  /*!< [21..21] Counter overflow interrupt enable                                */
20324             __IOM uint32_t AEDIE : 1;  /*!< [22..22] Active edge detection interrupt enable                           */
20325             uint32_t             : 1;
20326             __IOM uint32_t BCCS  : 2;  /*!< [25..24] Bus conflict detection clock selection                           */
20327             uint32_t             : 6;
20328         } XCR0_b;
20329     };
20330 
20331     union
20332     {
20333         __IOM uint32_t XCR1;           /*!< (@ 0x00000038) Simple LIN(SCIX) Control Register 1                        */
20334 
20335         struct
20336         {
20337             __IOM uint32_t TCST  : 1;  /*!< [0..0] Break Field output timer count start trigger                       */
20338             uint32_t             : 3;
20339             __IOM uint32_t SDST  : 1;  /*!< [4..4] Start Frame detection enable                                       */
20340             __IOM uint32_t BMEN  : 1;  /*!< [5..5] Bit rate measurement enable                                        */
20341             uint32_t             : 2;
20342             __IOM uint32_t PCF1D : 8;  /*!< [15..8] Priority compare data for Control Field 1                         */
20343             __IOM uint32_t SCF1D : 8;  /*!< [23..16] Secondary compare data for Control Field 1                       */
20344             __IOM uint32_t CF1CE : 8;  /*!< [31..24] Control Field 1 compare bit enable                               */
20345         } XCR1_b;
20346     };
20347 
20348     union
20349     {
20350         __IOM uint32_t XCR2;           /*!< (@ 0x0000003C) Simple LIN(SCIX) Control Register 2                        */
20351 
20352         struct
20353         {
20354             __IOM uint32_t CF0D  : 8;  /*!< [7..0] Control Field 0compare data                                        */
20355             __IOM uint32_t CF0CE : 8;  /*!< [15..8] Control Field 0 compare bit enable                                */
20356             __IOM uint32_t BFLW  : 16; /*!< [31..16] Break Field length setting                                       */
20357         } XCR2_b;
20358     };
20359     __IM uint32_t RESERVED3[2];
20360 
20361     union
20362     {
20363         __IM uint32_t CSR;             /*!< (@ 0x00000048) Common Status Register                                     */
20364 
20365         struct
20366         {
20367             uint32_t             : 4;
20368             __IM uint32_t ERS    : 1;  /*!< [4..4] Error Signal Status Flag                                           */
20369             uint32_t             : 10;
20370             __IM uint32_t RXDMON : 1;  /*!< [15..15] Serial input data monitor bit                                    */
20371             __IM uint32_t DCMF   : 1;  /*!< [16..16] Data Compare Match Flag                                          */
20372             __IM uint32_t DPER   : 1;  /*!< [17..17] Data Compare Match Parity Error Flag                             */
20373             __IM uint32_t DFER   : 1;  /*!< [18..18] Data Compare Match Framing Error Flag                            */
20374             uint32_t             : 5;
20375             __IM uint32_t ORER   : 1;  /*!< [24..24] Overrun Error Flag                                               */
20376             uint32_t             : 1;
20377             __IM uint32_t MFF    : 1;  /*!< [26..26] Mode Fault Flag                                                  */
20378             __IM uint32_t PER    : 1;  /*!< [27..27] Parity Error Flag                                                */
20379             __IM uint32_t FER    : 1;  /*!< [28..28] Framing Error Flag                                               */
20380             __IM uint32_t TDRE   : 1;  /*!< [29..29] Transmit Data Empty Flag                                         */
20381             __IM uint32_t TEND   : 1;  /*!< [30..30] Transmit End Flag                                                */
20382             __IM uint32_t RDRF   : 1;  /*!< [31..31] Receive Data Full Flag                                           */
20383         } CSR_b;
20384     };
20385 
20386     union
20387     {
20388         __IM uint32_t ISR;             /*!< (@ 0x0000004C) Simple I2C Status Register                                 */
20389 
20390         struct
20391         {
20392             __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag                                            */
20393             uint32_t              : 2;
20394             __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
20395                                         *   Flag                                                                      */
20396             uint32_t : 28;
20397         } ISR_b;
20398     };
20399 
20400     union
20401     {
20402         __IM uint32_t FRSR;            /*!< (@ 0x00000050) FIFO Receive Status Register                               */
20403 
20404         struct
20405         {
20406             __IM uint32_t DR   : 1;    /*!< [0..0] Receive Data Ready flag                                            */
20407             uint32_t           : 7;
20408             __IM uint32_t R    : 6;    /*!< [13..8] Receive-FIFO Data Count                                           */
20409             uint32_t           : 2;
20410             __IM uint32_t PNUM : 6;    /*!< [21..16] Parity Error Count                                               */
20411             uint32_t           : 2;
20412             __IM uint32_t FNUM : 6;    /*!< [29..24] Framing Error Count                                              */
20413             uint32_t           : 2;
20414         } FRSR_b;
20415     };
20416 
20417     union
20418     {
20419         __IM uint32_t FTSR;            /*!< (@ 0x00000054) FIFO Transmit Status Register                              */
20420 
20421         struct
20422         {
20423             __IM uint32_t T : 6;       /*!< [5..0] Transmit-FIFO Data Count                                           */
20424             uint32_t        : 26;
20425         } FTSR_b;
20426     };
20427 
20428     union
20429     {
20430         __IM uint32_t MSR;             /*!< (@ 0x00000058) Manchester Status Register                                 */
20431 
20432         struct
20433         {
20434             __IM uint32_t PFER  : 1;   /*!< [0..0] Preface Error flag                                                 */
20435             __IM uint32_t SYER  : 1;   /*!< [1..1] SYNC Error flag                                                    */
20436             __IM uint32_t SBER  : 1;   /*!< [2..2] Start Bit Error flag                                               */
20437             uint32_t            : 1;
20438             __IM uint32_t MER   : 1;   /*!< [4..4] Manchester Error Flag                                              */
20439             uint32_t            : 1;
20440             __IM uint32_t RSYNC : 1;   /*!< [6..6] Receive SYNC data bit                                              */
20441             uint32_t            : 25;
20442         } MSR_b;
20443     };
20444 
20445     union
20446     {
20447         __IM uint32_t XSR0;            /*!< (@ 0x0000005C) Simple LIN (SCIX) Status Register 0                        */
20448 
20449         struct
20450         {
20451             __IM uint32_t SFSF  : 1;   /*!< [0..0] Start Frame Status flag                                            */
20452             __IM uint32_t RXDSF : 1;   /*!< [1..1] RXDn input status flag                                             */
20453             uint32_t            : 6;
20454             __IM uint32_t BFOF  : 1;   /*!< [8..8] Break Field Output completion flag                                 */
20455             __IM uint32_t BCDF  : 1;   /*!< [9..9] Bus Conflict detection flag                                        */
20456             __IM uint32_t BFDF  : 1;   /*!< [10..10] Break Field detection flag                                       */
20457             __IM uint32_t CF0MF : 1;   /*!< [11..11] Control Field 0 compare match flag                               */
20458             __IM uint32_t CF1MF : 1;   /*!< [12..12] Control Field 1 compare match flag                               */
20459             __IM uint32_t PIBDF : 1;   /*!< [13..13] Priority interrupt bit detection flag                            */
20460             __IM uint32_t COF   : 1;   /*!< [14..14] Counter Overflow flag                                            */
20461             __IM uint32_t AEDF  : 1;   /*!< [15..15] Active Edge detection flag                                       */
20462             __IM uint32_t CF0RD : 8;   /*!< [23..16] Control Field 0 received data                                    */
20463             __IM uint32_t CF1RD : 8;   /*!< [31..24] Control Field 1 received data                                    */
20464         } XSR0_b;
20465     };
20466 
20467     union
20468     {
20469         __IM uint32_t XSR1;            /*!< (@ 0x00000060) Simple LIN(SCIX) Status Register 1                         */
20470 
20471         struct
20472         {
20473             __IM uint32_t TCNT : 16;   /*!< [15..0] Timer Count Capture value                                         */
20474             uint32_t           : 16;
20475         } XSR1_b;
20476     };
20477     __IM uint32_t RESERVED4;
20478 
20479     union
20480     {
20481         __OM uint32_t CFCLR;           /*!< (@ 0x00000068) Common Flag Clear Register                                 */
20482 
20483         struct
20484         {
20485             uint32_t            : 4;
20486             __OM uint32_t ERSC  : 1;   /*!< [4..4] ERS clear bit                                                      */
20487             uint32_t            : 11;
20488             __OM uint32_t DCMFC : 1;   /*!< [16..16] DCMF clear bit                                                   */
20489             __OM uint32_t DPERC : 1;   /*!< [17..17] DPER clear bit                                                   */
20490             __OM uint32_t DFERC : 1;   /*!< [18..18] DFER clear bit                                                   */
20491             uint32_t            : 5;
20492             __OM uint32_t ORERC : 1;   /*!< [24..24] ORER clear bit                                                   */
20493             uint32_t            : 1;
20494             __OM uint32_t MFFC  : 1;   /*!< [26..26] MFF clear bit                                                    */
20495             __OM uint32_t PERC  : 1;   /*!< [27..27] PER clear bit                                                    */
20496             __OM uint32_t FERC  : 1;   /*!< [28..28] FER clear bit                                                    */
20497             __OM uint32_t TDREC : 1;   /*!< [29..29] TDRE clear bit                                                   */
20498             uint32_t            : 1;
20499             __OM uint32_t RDRFC : 1;   /*!< [31..31] RDRF clear bit                                                   */
20500         } CFCLR_b;
20501     };
20502 
20503     union
20504     {
20505         __OM uint32_t ICFCLR;          /*!< (@ 0x0000006C) Simple I2C Flag Clear Register                             */
20506 
20507         struct
20508         {
20509             uint32_t               : 3;
20510             __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIF clear bit                                                  */
20511             uint32_t               : 28;
20512         } ICFCLR_b;
20513     };
20514 
20515     union
20516     {
20517         __OM uint32_t FFCLR;           /*!< (@ 0x00000070) FIFO Flag Clear Register                                   */
20518 
20519         struct
20520         {
20521             __OM uint32_t DRC : 1;     /*!< [0..0] DR clear bit                                                       */
20522             uint32_t          : 31;
20523         } FFCLR_b;
20524     };
20525 
20526     union
20527     {
20528         __OM uint32_t MFCLR;           /*!< (@ 0x00000074) Manchester Flag Clear Register                             */
20529 
20530         struct
20531         {
20532             __OM uint32_t PFERC : 1;   /*!< [0..0] PFER clear bit                                                     */
20533             __OM uint32_t SYERC : 1;   /*!< [1..1] SYER clear bit                                                     */
20534             __OM uint32_t SBERC : 1;   /*!< [2..2] SBER clear bit                                                     */
20535             uint32_t            : 1;
20536             __OM uint32_t MERC  : 1;   /*!< [4..4] MER clear bit                                                      */
20537             uint32_t            : 27;
20538         } MFCLR_b;
20539     };
20540 
20541     union
20542     {
20543         __OM uint32_t XFCLR;           /*!< (@ 0x00000078) Simple LIN(SCIX) Flag Clear Register                       */
20544 
20545         struct
20546         {
20547             uint32_t            : 8;
20548             __OM uint32_t BFOC  : 1;   /*!< [8..8] BFOF clear bit                                                     */
20549             __OM uint32_t BCDC  : 1;   /*!< [9..9] BCDF clear bit                                                     */
20550             __OM uint32_t BFDC  : 1;   /*!< [10..10] BFDF clear bit                                                   */
20551             __OM uint32_t CF0MC : 1;   /*!< [11..11] CF0MF clear bit                                                  */
20552             __OM uint32_t CF1MC : 1;   /*!< [12..12] CF1MF clear bit                                                  */
20553             __OM uint32_t PIBDC : 1;   /*!< [13..13] PIBDF clear bit                                                  */
20554             __OM uint32_t COFC  : 1;   /*!< [14..14] COFF clear bit                                                   */
20555             __OM uint32_t AEDC  : 1;   /*!< [15..15] AEDF clear bit                                                   */
20556             uint32_t            : 16;
20557         } XFCLR_b;
20558     };
20559 } R_SCI_B0_Type;                       /*!< Size = 124 (0x7c)                                                         */
20560 
20561 /* =========================================================================================================================== */
20562 /* ================                                         R_SPI_B0                                          ================ */
20563 /* =========================================================================================================================== */
20564 
20565 /**
20566  * @brief Serial Peripheral Interface 0 (R_SPI_B0)
20567  */
20568 
20569 typedef struct                         /*!< (@ 0x4035C000) R_SPI_B0 Structure                                         */
20570 {
20571     __IOM uint32_t SPDR;               /*!< (@ 0x00000000) RSPI Data Register                                         */
20572 
20573     union
20574     {
20575         __IOM uint32_t SPDECR;         /*!< (@ 0x00000004) RSPI Delay Control Register                                */
20576 
20577         struct
20578         {
20579             __IOM uint32_t SCKDL : 3;  /*!< [2..0] RSPCK Delay                                                        */
20580             uint32_t             : 5;
20581             __IOM uint32_t SLNDL : 3;  /*!< [10..8] SSL Negation Delay                                                */
20582             uint32_t             : 5;
20583             __IOM uint32_t SPNDL : 3;  /*!< [18..16] RSPI Next-Access Delay                                           */
20584             uint32_t             : 5;
20585             __IOM uint32_t ARST  : 3;  /*!< [26..24] Receive Sampling Timing Adjustment bits                          */
20586             uint32_t             : 5;
20587         } SPDECR_b;
20588     };
20589 
20590     union
20591     {
20592         __IOM uint32_t SPCR;             /*!< (@ 0x00000008) RSPI Control Register                                      */
20593 
20594         struct
20595         {
20596             __IOM uint32_t SPE      : 1; /*!< [0..0] RSPI Function Enable                                               */
20597             uint32_t                : 6;
20598             __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] RSPI Master Receive Clock Select                                   */
20599             __IOM uint32_t SPPE     : 1; /*!< [8..8] Parity Enable                                                      */
20600             __IOM uint32_t SPOE     : 1; /*!< [9..9] Parity Mode                                                        */
20601             uint32_t                : 1;
20602             __IOM uint32_t PTE      : 1; /*!< [11..11] Parity Self-Diagnosis Enable                                     */
20603             __IOM uint32_t SCKASE   : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable                                  */
20604             __IOM uint32_t BFDS     : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select                       */
20605             __IOM uint32_t MODFEN   : 1; /*!< [14..14] Mode Fault Error Detection Enable                                */
20606             uint32_t                : 1;
20607             __IOM uint32_t SPEIE    : 1; /*!< [16..16] RSPI Error Interrupt Enable                                      */
20608             __IOM uint32_t SPRIE    : 1; /*!< [17..17] RSPI Receive Buffer Full Interrupt Enable                        */
20609             __IOM uint32_t SPIIE    : 1; /*!< [18..18] RSPI Idle Interrupt Enable                                       */
20610             __IOM uint32_t SPDRES   : 1; /*!< [19..19] RSPI receive data ready error select                             */
20611             __IOM uint32_t SPTIE    : 1; /*!< [20..20] RSPI Transmit Buffer Empty Interrupt Enable                      */
20612             __IOM uint32_t CENDIE   : 1; /*!< [21..21] RSPI Communication End Interrupt Enable                          */
20613             uint32_t                : 2;
20614             __IOM uint32_t SPMS     : 1; /*!< [24..24] RSPI Mode Select                                                 */
20615             __IOM uint32_t SPFRF    : 1; /*!< [25..25] RSPI Frame Format Select                                         */
20616             uint32_t                : 2;
20617             __IOM uint32_t TXMD     : 2; /*!< [29..28] Communication Mode Select                                        */
20618             __IOM uint32_t MSTR     : 1; /*!< [30..30] RSPI Master/Slave Mode Select                                    */
20619             __IOM uint32_t BPEN     : 1; /*!< [31..31] Synchronization Circuit Bypass Enable                            */
20620         } SPCR_b;
20621     };
20622 
20623     union
20624     {
20625         __IOM uint32_t SPCR2;          /*!< (@ 0x0000000C) RSPI Control Register 2                                    */
20626 
20627         struct
20628         {
20629             __IOM uint32_t RMFM   : 5; /*!< [4..0] Frame processing count setting in Master Receive only              */
20630             uint32_t              : 1;
20631             __OM uint32_t  RMEDTG : 1; /*!< [6..6] End Trigger in Master Receive only                                 */
20632             __OM uint32_t  RMSTTG : 1; /*!< [7..7] Start Trigger in Master Receive only                               */
20633             __IOM uint32_t SPDRC  : 8; /*!< [15..8] RSPI received data ready detect adjustment                        */
20634             __IOM uint32_t SPLP   : 1; /*!< [16..16] RSPI Loopback                                                    */
20635             __IOM uint32_t SPLP2  : 1; /*!< [17..17] RSPI Loopback 2                                                  */
20636             uint32_t              : 2;
20637             __IOM uint32_t MOIFV  : 1; /*!< [20..20] MOSI Idle Fixed Value                                            */
20638             __IOM uint32_t MOIFE  : 1; /*!< [21..21] MOSI Idle Fixed Value Enable                                     */
20639             uint32_t              : 10;
20640         } SPCR2_b;
20641     };
20642 
20643     union
20644     {
20645         __IOM uint32_t SPCR3;          /*!< (@ 0x00000010) RSPI Control Register 3                                    */
20646 
20647         struct
20648         {
20649             __IOM uint32_t SSL0P : 1;  /*!< [0..0] SSL0 Signal Polarity                                               */
20650             __IOM uint32_t SSL1P : 1;  /*!< [1..1] SSL1 Signal Polarity                                               */
20651             __IOM uint32_t SSL2P : 1;  /*!< [2..2] SSL2 Signal Polarity                                               */
20652             __IOM uint32_t SSL3P : 1;  /*!< [3..3] SSL3 Signal Polarity                                               */
20653             uint32_t             : 4;
20654             __IOM uint32_t SPBR  : 8;  /*!< [15..8] SPI Bit Rate                                                      */
20655             uint32_t             : 8;
20656             __IOM uint32_t SPSLN : 3;  /*!< [26..24] RSPI Sequence Length                                             */
20657             uint32_t             : 5;
20658         } SPCR3_b;
20659     };
20660 
20661     union
20662     {
20663         __IOM uint32_t SPCMD0;         /*!< (@ 0x00000014) RSPI Command Register                                      */
20664 
20665         struct
20666         {
20667             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
20668             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
20669             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
20670             uint32_t              : 3;
20671             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
20672             uint32_t              : 4;
20673             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
20674             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
20675             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20676             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20677             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
20678             uint32_t              : 3;
20679             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
20680             uint32_t              : 5;
20681         } SPCMD0_b;
20682     };
20683 
20684     union
20685     {
20686         __IOM uint32_t SPCMD1;         /*!< (@ 0x00000018) RSPI Command Register                                      */
20687 
20688         struct
20689         {
20690             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
20691             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
20692             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
20693             uint32_t              : 3;
20694             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
20695             uint32_t              : 4;
20696             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
20697             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
20698             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20699             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20700             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
20701             uint32_t              : 3;
20702             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
20703             uint32_t              : 5;
20704         } SPCMD1_b;
20705     };
20706 
20707     union
20708     {
20709         __IOM uint32_t SPCMD2;         /*!< (@ 0x0000001C) RSPI Command Register                                      */
20710 
20711         struct
20712         {
20713             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
20714             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
20715             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
20716             uint32_t              : 3;
20717             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
20718             uint32_t              : 4;
20719             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
20720             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
20721             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20722             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20723             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
20724             uint32_t              : 3;
20725             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
20726             uint32_t              : 5;
20727         } SPCMD2_b;
20728     };
20729 
20730     union
20731     {
20732         __IOM uint32_t SPCMD3;         /*!< (@ 0x00000020) RSPI Command Register                                      */
20733 
20734         struct
20735         {
20736             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
20737             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
20738             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
20739             uint32_t              : 3;
20740             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
20741             uint32_t              : 4;
20742             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
20743             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
20744             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20745             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20746             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
20747             uint32_t              : 3;
20748             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
20749             uint32_t              : 5;
20750         } SPCMD3_b;
20751     };
20752 
20753     union
20754     {
20755         __IOM uint32_t SPCMD4;         /*!< (@ 0x00000024) RSPI Command Register                                      */
20756 
20757         struct
20758         {
20759             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
20760             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
20761             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
20762             uint32_t              : 3;
20763             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
20764             uint32_t              : 4;
20765             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
20766             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
20767             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20768             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20769             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
20770             uint32_t              : 3;
20771             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
20772             uint32_t              : 5;
20773         } SPCMD4_b;
20774     };
20775 
20776     union
20777     {
20778         __IOM uint32_t SPCMD5;         /*!< (@ 0x00000028) RSPI Command Register                                      */
20779 
20780         struct
20781         {
20782             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
20783             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
20784             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
20785             uint32_t              : 3;
20786             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
20787             uint32_t              : 4;
20788             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
20789             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
20790             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20791             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20792             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
20793             uint32_t              : 3;
20794             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
20795             uint32_t              : 5;
20796         } SPCMD5_b;
20797     };
20798 
20799     union
20800     {
20801         __IOM uint32_t SPCMD6;         /*!< (@ 0x0000002C) RSPI Command Register                                      */
20802 
20803         struct
20804         {
20805             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
20806             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
20807             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
20808             uint32_t              : 3;
20809             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
20810             uint32_t              : 4;
20811             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
20812             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
20813             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20814             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20815             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
20816             uint32_t              : 3;
20817             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
20818             uint32_t              : 5;
20819         } SPCMD6_b;
20820     };
20821 
20822     union
20823     {
20824         __IOM uint32_t SPCMD7;         /*!< (@ 0x00000030) RSPI Command Register                                      */
20825 
20826         struct
20827         {
20828             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
20829             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
20830             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
20831             uint32_t              : 3;
20832             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
20833             uint32_t              : 4;
20834             __IOM uint32_t LSBF   : 1; /*!< [12..12] RSPI LSB First                                                   */
20835             __IOM uint32_t SPNDEN : 1; /*!< [13..13] RSPI Next-Access Delay Enable                                    */
20836             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
20837             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
20838             __IOM uint32_t SPB    : 5; /*!< [20..16] RSPI Data Length                                                 */
20839             uint32_t              : 3;
20840             __IOM uint32_t SSLA   : 3; /*!< [26..24] SSL Signal Assertion                                             */
20841             uint32_t              : 5;
20842         } SPCMD7_b;
20843     };
20844     __IM uint32_t RESERVED[3];
20845 
20846     union
20847     {
20848         __IOM uint32_t SPDCR;          /*!< (@ 0x00000040) RSPI Data Control Register                                 */
20849 
20850         struct
20851         {
20852             __IOM uint32_t BYSW   : 1; /*!< [0..0] Byte Swap Operating Mode Select                                    */
20853             uint32_t              : 2;
20854             __IOM uint32_t SPRDTD : 1; /*!< [3..3] RSPI Receive Data or Transmit Data Select                          */
20855             __IOM uint32_t SINV   : 1; /*!< [4..4] Serial data invert bit                                             */
20856             uint32_t              : 3;
20857             __IOM uint32_t SPFC   : 2; /*!< [9..8] Frame Count                                                        */
20858             uint32_t              : 22;
20859         } SPDCR_b;
20860     };
20861 
20862     union
20863     {
20864         __IOM uint32_t SPDCR2;         /*!< (@ 0x00000044) RSPI Data Control Register 2                               */
20865 
20866         struct
20867         {
20868             __IOM uint32_t RTRG : 2;   /*!< [1..0] Receive FIFO threshold setting                                     */
20869             uint32_t            : 6;
20870             __IOM uint32_t TTRG : 2;   /*!< [9..8] Transmission FIFO threshold setting                                */
20871             uint32_t            : 22;
20872         } SPDCR2_b;
20873     };
20874     __IM uint32_t RESERVED1[2];
20875 
20876     union
20877     {
20878         __IM uint32_t SPSR;            /*!< (@ 0x00000050) SPI Status Register                                        */
20879 
20880         struct
20881         {
20882             uint32_t            : 8;
20883             __IM uint32_t SPCP  : 3;   /*!< [10..8] RSPI Command Pointer                                              */
20884             uint32_t            : 1;
20885             __IM uint32_t SPECM : 3;   /*!< [14..12] RSPI Error Command                                               */
20886             uint32_t            : 8;
20887             __IM uint32_t SPDRF : 1;   /*!< [23..23] RSPI Receive Data Ready Flag                                     */
20888             __IM uint32_t OVRF  : 1;   /*!< [24..24] Overrun Error Flag                                               */
20889             __IM uint32_t IDLNF : 1;   /*!< [25..25] RSPI Idle Flag                                                   */
20890             __IM uint32_t MODF  : 1;   /*!< [26..26] Mode Fault Error Flag                                            */
20891             __IM uint32_t PERF  : 1;   /*!< [27..27] Parity Error Flag                                                */
20892             __IM uint32_t UDRF  : 1;   /*!< [28..28] Underrun Error Flag                                              */
20893             __IM uint32_t SPTEF : 1;   /*!< [29..29] RSPI Transmit Buffer Empty Flag                                  */
20894             __IM uint32_t CENDF : 1;   /*!< [30..30] Communication End Flag                                           */
20895             __IM uint32_t SPRF  : 1;   /*!< [31..31] RSPI Receive Buffer Full Flag                                    */
20896         } SPSR_b;
20897     };
20898     __IM uint32_t RESERVED2;
20899 
20900     union
20901     {
20902         __IM uint32_t SPTFSR;          /*!< (@ 0x00000058) RSPI Transfer FIFO Status Register                         */
20903 
20904         struct
20905         {
20906             __IM uint32_t TFDN : 3;    /*!< [2..0] Transmit FIFO data empty stage number                              */
20907             uint32_t           : 29;
20908         } SPTFSR_b;
20909     };
20910 
20911     union
20912     {
20913         __IM uint32_t SPRFSR;          /*!< (@ 0x0000005C) RSPI Receive FIFO Status Register                          */
20914 
20915         struct
20916         {
20917             __IM uint32_t RFDN : 3;    /*!< [2..0] Receive FIFO data store stage number                               */
20918             uint32_t           : 29;
20919         } SPRFSR_b;
20920     };
20921 
20922     union
20923     {
20924         __IM uint32_t SPPSR;           /*!< (@ 0x00000060) RSPI Poling Register                                       */
20925 
20926         struct
20927         {
20928             __IM uint32_t SPEPS : 1;   /*!< [0..0] RSPI Poling Status                                                 */
20929             uint32_t            : 31;
20930         } SPPSR_b;
20931     };
20932     __IM uint32_t RESERVED3;
20933 
20934     union
20935     {
20936         __IOM uint32_t SPSRC;          /*!< (@ 0x00000068) RSPI Status Clear Register                                 */
20937 
20938         struct
20939         {
20940             uint32_t             : 23;
20941             __OM uint32_t SPDRFC : 1;  /*!< [23..23] RSPI Receive Data Ready Flag Clear                               */
20942             __OM uint32_t OVRFC  : 1;  /*!< [24..24] Overrun Error Flag Clear                                         */
20943             uint32_t             : 1;
20944             __OM uint32_t MODFC  : 1;  /*!< [26..26] Mode Fault Error Flag Clear                                      */
20945             __OM uint32_t PERFC  : 1;  /*!< [27..27] Parity Error Flag Clear                                          */
20946             __OM uint32_t UDRFC  : 1;  /*!< [28..28] Underrun Error Flag Clear                                        */
20947             __OM uint32_t SPTEFC : 1;  /*!< [29..29] RSPI Transmit Buffer Empty Flag Clear                            */
20948             __OM uint32_t CENDFC : 1;  /*!< [30..30] Communication End Flag Clear                                     */
20949             __OM uint32_t SPRFC  : 1;  /*!< [31..31] RSPI Receive Buffer Full Flag Clear                              */
20950         } SPSRC_b;
20951     };
20952 
20953     union
20954     {
20955         __IOM uint32_t SPFCR;          /*!< (@ 0x0000006C) RSPI FIFO Clear Register                                   */
20956 
20957         struct
20958         {
20959             __OM uint32_t SPFRST : 1;  /*!< [0..0] RSPI FIFO clear                                                    */
20960             uint32_t             : 31;
20961         } SPFCR_b;
20962     };
20963 } R_SPI_B0_Type;                       /*!< Size = 112 (0x70)                                                         */
20964 
20965 /* =========================================================================================================================== */
20966 /* ================                                         R_USB_HS0                                         ================ */
20967 /* =========================================================================================================================== */
20968 
20969 /**
20970  * @brief USB 2.0 High-Speed Module (R_USB_HS0)
20971  */
20972 
20973 typedef struct                         /*!< (@ 0x40351000) R_USB_HS0 Structure                                        */
20974 {
20975     union
20976     {
20977         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
20978 
20979         struct
20980         {
20981             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
20982             uint16_t             : 3;
20983             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
20984             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
20985             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
20986             __IOM uint16_t HSE   : 1;  /*!< [7..7] High-Speed Operation Enable                                        */
20987             __IOM uint16_t CNEN  : 1;  /*!< [8..8] Single End Receiver Enable                                         */
20988             uint16_t             : 7;
20989         } SYSCFG_b;
20990     };
20991 
20992     union
20993     {
20994         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
20995 
20996         struct
20997         {
20998             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
20999                                         *   access cycles)                                                            */
21000             uint16_t : 12;
21001         } BUSWAIT_b;
21002     };
21003 
21004     union
21005     {
21006         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register                       */
21007 
21008         struct
21009         {
21010             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
21011             __IM uint16_t IDMON : 1;   /*!< [2..2] ID0 Pin Monitor                                                    */
21012             uint16_t            : 2;
21013             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
21014                                         *   Selected.                                                                 */
21015             __IM uint16_t HTACT  : 1;  /*!< [6..6] Host Sequencer Status Monitor                                      */
21016             uint16_t             : 7;
21017             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe
21018                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
21019                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
21020                                         *   pin.                                                                      */
21021         } SYSSTS0_b;
21022     };
21023 
21024     union
21025     {
21026         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
21027 
21028         struct
21029         {
21030             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
21031             uint16_t              : 15;
21032         } PLLSTA_b;
21033     };
21034 
21035     union
21036     {
21037         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
21038 
21039         struct
21040         {
21041             __IM uint16_t RHST    : 3;  /*!< [2..0] USB Bus Reset Status                                               */
21042             uint16_t              : 1;
21043             __IOM uint16_t UACT   : 1;  /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation         */
21044             __IOM uint16_t RESUME : 1;  /*!< [5..5] Resume Signal Output for the Host Controller Operation             */
21045             __IOM uint16_t USBRST : 1;  /*!< [6..6] USB Bus Reset Output for the Host Controller Operation             */
21046             __IOM uint16_t RWUPE  : 1;  /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller
21047                                          *   Operation                                                                 */
21048             __IOM uint16_t WKUP    : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation           */
21049             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control                                    */
21050             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control                                  */
21051             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit
21052                                          *   when switching from device B to device A in OTGmode. If
21053                                          *   the HNPBTOA bit is 1, the internal function controlremains
21054                                          *   in the Suspend state until the HNP processing endseven
21055                                          *   if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.                            */
21056             uint16_t : 4;
21057         } DVSTCTR0_b;
21058     };
21059     __IM uint16_t RESERVED;
21060 
21061     union
21062     {
21063         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
21064 
21065         struct
21066         {
21067             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
21068             uint16_t            : 12;
21069         } TESTMODE_b;
21070     };
21071     __IM uint16_t RESERVED1;
21072     __IM uint32_t RESERVED2;
21073 
21074     union
21075     {
21076         union
21077         {
21078             __IOM uint32_t CFIFO;             /*!< (@ 0x00000014) CFIFO Port Register                                        */
21079 
21080             struct
21081             {
21082                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or
21083                                                *   write transmit data to the FIFO buffer by accessing these
21084                                                *   bits.                                                                     */
21085             } CFIFO_b;
21086         };
21087 
21088         struct
21089         {
21090             union
21091             {
21092                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
21093                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
21094             };
21095 
21096             union
21097             {
21098                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
21099 
21100                 struct
21101                 {
21102                     __IM uint8_t  RESERVED3;
21103                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
21104                 };
21105             };
21106         };
21107     };
21108 
21109     union
21110     {
21111         union
21112         {
21113             __IOM uint32_t D0FIFO;            /*!< (@ 0x00000018) D0FIFO Port Register                                       */
21114 
21115             struct
21116             {
21117                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or
21118                                                *   write transmit data to the FIFO buffer by accessing these
21119                                                *   bits.                                                                     */
21120             } D0FIFO_b;
21121         };
21122 
21123         struct
21124         {
21125             union
21126             {
21127                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
21128                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
21129             };
21130 
21131             union
21132             {
21133                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
21134 
21135                 struct
21136                 {
21137                     __IM uint8_t  RESERVED4;
21138                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
21139                 };
21140             };
21141         };
21142     };
21143 
21144     union
21145     {
21146         union
21147         {
21148             __IOM uint32_t D1FIFO;            /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
21149 
21150             struct
21151             {
21152                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write
21153                                                *   transmit data to the FIFO buffer by accessing these bits.                 */
21154             } D1FIFO_b;
21155         };
21156 
21157         struct
21158         {
21159             union
21160             {
21161                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
21162                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
21163             };
21164 
21165             union
21166             {
21167                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
21168 
21169                 struct
21170                 {
21171                     __IM uint8_t  RESERVED5;
21172                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
21173                 };
21174             };
21175         };
21176     };
21177 
21178     union
21179     {
21180         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
21181 
21182         struct
21183         {
21184             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
21185             uint16_t               : 1;
21186             __IOM uint16_t ISEL    : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected                    */
21187             uint16_t               : 2;
21188             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
21189             uint16_t               : 1;
21190             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
21191             uint16_t               : 2;
21192             __OM uint16_t  REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
21193             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
21194         } CFIFOSEL_b;
21195     };
21196 
21197     union
21198     {
21199         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
21200 
21201         struct
21202         {
21203             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
21204                                         *   data.                                                                     */
21205             uint16_t           : 1;
21206             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
21207                                         *   be accessed.                                                              */
21208             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
21209             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
21210         } CFIFOCTR_b;
21211     };
21212     __IM uint32_t RESERVED6;
21213 
21214     union
21215     {
21216         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
21217 
21218         struct
21219         {
21220             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
21221             uint16_t               : 4;
21222             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
21223             uint16_t               : 1;
21224             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
21225             __IOM uint16_t DREQE   : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable                                 */
21226             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
21227                                          *   Pipe Data is Read                                                         */
21228             __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
21229             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
21230         } D0FIFOSEL_b;
21231     };
21232 
21233     union
21234     {
21235         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
21236 
21237         struct
21238         {
21239             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
21240                                         *   data.                                                                     */
21241             uint16_t           : 1;
21242             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
21243                                         *   be accessed.                                                              */
21244             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
21245             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
21246         } D0FIFOCTR_b;
21247     };
21248 
21249     union
21250     {
21251         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
21252 
21253         struct
21254         {
21255             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
21256             uint16_t               : 4;
21257             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
21258             uint16_t               : 1;
21259             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
21260             __IOM uint16_t DREQE   : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable                                 */
21261             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
21262                                          *   Pipe Data is Read                                                         */
21263             __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
21264             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
21265         } D1FIFOSEL_b;
21266     };
21267 
21268     union
21269     {
21270         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
21271 
21272         struct
21273         {
21274             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
21275                                         *   data.                                                                     */
21276             uint16_t           : 1;
21277             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
21278                                         *   be accessed.                                                              */
21279             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
21280             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
21281         } D1FIFOCTR_b;
21282     };
21283 
21284     union
21285     {
21286         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
21287 
21288         struct
21289         {
21290             uint16_t             : 8;
21291             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
21292             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
21293             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
21294             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
21295             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
21296             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
21297             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
21298             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
21299         } INTENB0_b;
21300     };
21301 
21302     union
21303     {
21304         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
21305 
21306         struct
21307         {
21308             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
21309             uint16_t                  : 3;
21310             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
21311             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
21312             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
21313             uint16_t                  : 1;
21314             __IOM uint16_t LPMENDE    : 1; /*!< [8..8] LPM Transaction End Interrupt Enable                               */
21315             __IOM uint16_t L1RSMENDE  : 1; /*!< [9..9] L1 Resume End Interrupt Enable                                     */
21316             uint16_t                  : 1;
21317             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
21318             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
21319             uint16_t                  : 1;
21320             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
21321             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] OVRCRE Interrupt Enable                                          */
21322         } INTENB1_b;
21323     };
21324     __IM uint16_t RESERVED7;
21325 
21326     union
21327     {
21328         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
21329 
21330         struct
21331         {
21332             __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe                                */
21333             uint16_t                 : 6;
21334         } BRDYENB_b;
21335     };
21336 
21337     union
21338     {
21339         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
21340 
21341         struct
21342         {
21343             __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe                                */
21344             uint16_t                 : 6;
21345         } NRDYENB_b;
21346     };
21347 
21348     union
21349     {
21350         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
21351 
21352         struct
21353         {
21354             __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe                                */
21355             uint16_t                 : 6;
21356         } BEMPENB_b;
21357     };
21358 
21359     union
21360     {
21361         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Pin Configuration Register                             */
21362 
21363         struct
21364         {
21365             uint16_t               : 4;
21366             __IM uint16_t  EDGESTS : 1;  /*!< [4..4] Interrupt Edge Processing Status Monitor                           */
21367             __IOM uint16_t INTL    : 1;  /*!< [5..5] Interrupt Output Sense Select                                      */
21368             __IOM uint16_t BRDYM   : 1;  /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be
21369                                           *   set only in the initial setting (before communications).The
21370                                           *   setting cannot be changed once communication starts.                      */
21371             uint16_t                : 1;
21372             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency
21373                                           *   can be improved by setting this bit to 1 if no low-speed
21374                                           *   device is connected directly or via FS-HUB to the USB port.               */
21375             uint16_t : 7;
21376         } SOFCFG_b;
21377     };
21378 
21379     union
21380     {
21381         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
21382 
21383         struct
21384         {
21385             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
21386             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
21387             uint16_t                : 1;
21388             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
21389             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
21390             uint16_t                : 2;
21391             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
21392             uint16_t                : 1;
21393             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
21394             uint16_t                : 3;
21395             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
21396         } PHYSET_b;
21397     };
21398 
21399     union
21400     {
21401         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
21402 
21403         struct
21404         {
21405             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
21406             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
21407             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
21408             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
21409             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
21410             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
21411             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
21412             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
21413             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
21414             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
21415             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
21416             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
21417         } INTSTS0_b;
21418     };
21419 
21420     union
21421     {
21422         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
21423 
21424         struct
21425         {
21426             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status                                   */
21427             uint16_t                 : 3;
21428             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
21429             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
21430             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
21431             uint16_t                 : 1;
21432             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
21433             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
21434             uint16_t                 : 1;
21435             __IOM uint16_t ATTCH     : 1; /*!< [11..11] USB Connection Detection Interrupt Status                        */
21436             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
21437             uint16_t                 : 1;
21438             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
21439             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Interrupt Status                                     */
21440         } INTSTS1_b;
21441     };
21442     __IM uint16_t RESERVED8;
21443 
21444     union
21445     {
21446         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
21447 
21448         struct
21449         {
21450             __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe                                */
21451             uint16_t                : 6;
21452         } BRDYSTS_b;
21453     };
21454 
21455     union
21456     {
21457         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
21458 
21459         struct
21460         {
21461             __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe                                */
21462             uint16_t                : 6;
21463         } NRDYSTS_b;
21464     };
21465 
21466     union
21467     {
21468         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
21469 
21470         struct
21471         {
21472             __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe                                */
21473             uint16_t                : 6;
21474         } BEMPSTS_b;
21475     };
21476 
21477     union
21478     {
21479         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
21480 
21481         struct
21482         {
21483             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame Number.Indicate the latest frame number.                    */
21484             uint16_t            : 3;
21485             __IOM uint16_t CRCE : 1;   /*!< [14..14] CRC Error Detection Status                                       */
21486             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
21487         } FRMNUM_b;
21488     };
21489 
21490     union
21491     {
21492         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
21493 
21494         struct
21495         {
21496             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
21497             uint16_t             : 12;
21498             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
21499         } UFRMNUM_b;
21500     };
21501 
21502     union
21503     {
21504         __IOM uint16_t USBADDR;        /*!< (@ 0x00000050) USB Address Register                                       */
21505 
21506         struct
21507         {
21508             uint16_t                 : 8;
21509             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
21510             uint16_t                 : 5;
21511         } USBADDR_b;
21512     };
21513     __IM uint16_t RESERVED9;
21514 
21515     union
21516     {
21517         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
21518 
21519         struct
21520         {
21521             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected
21522                                                *   : read-only Host controller selected : read-write                         */
21523             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] USB request bRequest value Finction controller selected
21524                                                *   : read-only Host controller selected : read-write                         */
21525         } USBREQ_b;
21526     };
21527 
21528     union
21529     {
21530         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
21531 
21532         struct
21533         {
21534             __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected
21535                                          *   : read-only Host controller selected : read-write                         */
21536         } USBVAL_b;
21537     };
21538 
21539     union
21540     {
21541         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
21542 
21543         struct
21544         {
21545             __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected
21546                                          *   : read-only Host controller selected : read-write                         */
21547         } USBINDX_b;
21548     };
21549 
21550     union
21551     {
21552         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
21553 
21554         struct
21555         {
21556             __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected
21557                                           *   : read-only Host controller selected : read-write                         */
21558         } USBLENG_b;
21559     };
21560 
21561     union
21562     {
21563         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
21564 
21565         struct
21566         {
21567             uint16_t              : 4;
21568             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
21569             uint16_t              : 2;
21570             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer                                   */
21571             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
21572             uint16_t              : 7;
21573         } DCPCFG_b;
21574     };
21575 
21576     union
21577     {
21578         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
21579 
21580         struct
21581         {
21582             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data
21583                                         *   payload (maximum packet size) for the DCP.                                */
21584             uint16_t              : 5;
21585             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
21586                                         *   destination function device for control transfer when the
21587                                         *   host controller function is selected.                                     */
21588         } DCPMAXP_b;
21589     };
21590 
21591     union
21592     {
21593         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
21594 
21595         struct
21596         {
21597             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
21598             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
21599             uint16_t                : 1;
21600             __IOM uint16_t PINGE    : 1; /*!< [4..4] PING Token Issue Enable                                            */
21601             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
21602             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
21603             __IOM uint16_t SQSET    : 1; /*!< [7..7] Toggle Bit Set                                                     */
21604             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Toggle Bit Clear                                                   */
21605             uint16_t                : 2;
21606             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
21607             __IM uint16_t  CSSTS    : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status                  */
21608             __IOM uint16_t CSCLR    : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear                            */
21609             __IOM uint16_t SUREQ    : 1; /*!< [14..14] SETUP Token Transmission                                         */
21610             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
21611         } DCPCTR_b;
21612     };
21613     __IM uint16_t  RESERVED10;
21614     __IOM uint16_t PIPESEL;              /*!< (@ 0x00000064) Pipe Window Select Register                                */
21615     __IM uint16_t  RESERVED11;
21616 
21617     union
21618     {
21619         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
21620 
21621         struct
21622         {
21623             __IOM uint16_t EPNUM  : 4; /*!< [3..0] Endpoint Number                                                    */
21624             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
21625             uint16_t              : 2;
21626             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
21627             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
21628             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
21629             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
21630             uint16_t              : 3;
21631             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
21632         } PIPECFG_b;
21633     };
21634 
21635     union
21636     {
21637         __IOM uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Register                                       */
21638 
21639         struct
21640         {
21641             __IOM uint16_t BUFNMB : 8;  /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number
21642                                          *   of the selected pipe (04h to 87h).                                        */
21643             uint16_t               : 2;
21644             __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes         */
21645             uint16_t               : 1;
21646         } PIPEBUF_b;
21647     };
21648 
21649     union
21650     {
21651         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
21652 
21653         struct
21654         {
21655             __IOM uint16_t MXPS : 11;  /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data
21656                                         *   payload (maximum packet size) for the selected pipe.A size
21657                                         *   of 1h to 40h bytes can be set for PIPE6 to PIPE9.                         */
21658             uint16_t              : 1;
21659             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
21660                                         *   peripheral device when the host controller function is
21661                                         *   selected.                                                                 */
21662         } PIPEMAXP_b;
21663     };
21664 
21665     union
21666     {
21667         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
21668 
21669         struct
21670         {
21671             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalThese bits specify the
21672                                         *   transfer interval timing for the selected pipe as n-th
21673                                         *   power of 2 of the frame timing.                                           */
21674             uint16_t            : 9;
21675             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
21676             uint16_t            : 3;
21677         } PIPEPERI_b;
21678     };
21679 
21680     union
21681     {
21682         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) PIPE Control Register                                      */
21683 
21684         struct
21685         {
21686             __IOM uint16_t PID : 2;    /*!< [1..0] Response PIDThese bits specify the response type for
21687                                         *   the next transaction of the relevant pipe.                                */
21688             uint16_t            : 3;
21689             __IM uint16_t PBUSY : 1;   /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe
21690                                         *   is being used for the USB bus                                             */
21691             __IM uint16_t SQMON : 1;   /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected
21692                                         *   value of the sequence toggle bit for the next transaction
21693                                         *   of the relevant pipe                                                      */
21694             __IOM uint16_t SQSET : 1;  /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected
21695                                         *   value of the sequence toggle bit for the next transaction
21696                                         *   of the relevant pipe is set for DATA1                                     */
21697             __IOM uint16_t SQCLR : 1;  /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected
21698                                         *   value of the sequence toggle bit for the next transaction
21699                                         *   of the relevant pipe is cleared to DATA0                                  */
21700             __IOM uint16_t ACLRM : 1;  /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto
21701                                         *   buffer clear mode for the relevant pipe                                   */
21702             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto
21703                                         *   response mode for the relevant pipe.                                      */
21704             uint16_t            : 1;
21705             __IM uint16_t CSSTS : 1;   /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
21706                                         *   Split Transaction of the relevant pipe                                    */
21707             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
21708                                         *   the CSSTS bit of the relevant pipe                                        */
21709             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO
21710                                         *   buffer status for the relevant pipe in the transmitting
21711                                         *   direction.                                                                */
21712             __IM uint16_t BSTS : 1;    /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status
21713                                         *   for the relevant pipe.                                                    */
21714         } PIPE_CTR_b[9];
21715     };
21716     __IM uint16_t                RESERVED12;
21717     __IM uint32_t                RESERVED13[3];
21718     __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
21719     __IM uint32_t                RESERVED14[11];
21720 
21721     union
21722     {
21723         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
21724 
21725         struct
21726         {
21727             uint16_t               : 6;
21728             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
21729             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
21730             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
21731             uint16_t               : 1;
21732         } DEVADD_b[10];
21733     };
21734     __IM uint32_t RESERVED15[7];
21735 
21736     union
21737     {
21738         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
21739 
21740         struct
21741         {
21742             uint16_t             : 7;
21743             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
21744             uint16_t             : 8;
21745         } LPCTRL_b;
21746     };
21747 
21748     union
21749     {
21750         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
21751 
21752         struct
21753         {
21754             uint16_t                : 14;
21755             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
21756             uint16_t                : 1;
21757         } LPSTS_b;
21758     };
21759     __IM uint32_t RESERVED16[15];
21760 
21761     union
21762     {
21763         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
21764 
21765         struct
21766         {
21767             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
21768             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
21769             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
21770             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
21771             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
21772             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
21773             uint16_t                : 2;
21774             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
21775             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
21776             uint16_t                : 6;
21777         } BCCTRL_b;
21778     };
21779     __IM uint16_t RESERVED17;
21780 
21781     union
21782     {
21783         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
21784 
21785         struct
21786         {
21787             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
21788             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
21789             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
21790                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
21791             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
21792                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
21793             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
21794                                           *   value used for L1NEGOMD.The format is the same as the HIRD
21795                                           *   field in HL1CTRL.                                                         */
21796             uint16_t               : 2;
21797             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
21798             uint16_t               : 1;
21799         } PL1CTRL1_b;
21800     };
21801 
21802     union
21803     {
21804         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
21805 
21806         struct
21807         {
21808             uint16_t               : 8;
21809             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
21810             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
21811             uint16_t               : 3;
21812         } PL1CTRL2_b;
21813     };
21814 
21815     union
21816     {
21817         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
21818 
21819         struct
21820         {
21821             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
21822             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
21823             uint16_t                : 13;
21824         } HL1CTRL1_b;
21825     };
21826 
21827     union
21828     {
21829         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
21830 
21831         struct
21832         {
21833             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
21834                                         *   be set in the ADDR field of LPM token.                                    */
21835             uint16_t             : 4;
21836             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
21837             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
21838                                         *   value to be set in the RWE field of LPM token.                            */
21839             uint16_t            : 2;
21840             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
21841                                         *   period at the time of L1 Resume.                                          */
21842         } HL1CTRL2_b;
21843     };
21844     __IM uint32_t RESERVED18;
21845 
21846     union
21847     {
21848         __IOM uint16_t PHYTRIM1;          /*!< (@ 0x00000150) PHY Timing Register 1                                      */
21849 
21850         struct
21851         {
21852             __IOM uint16_t DRISE     : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function              */
21853             __IOM uint16_t DFALL     : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function             */
21854             uint16_t                 : 3;
21855             __IOM uint16_t PCOMPENB  : 1; /*!< [7..7] PVDD Start-up Detection                                            */
21856             __IOM uint16_t HSIUP     : 4; /*!< [11..8] HS Output Level Setting                                           */
21857             __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset
21858                                            *   value for adjusting the terminating resistance.                           */
21859             uint16_t : 1;
21860         } PHYTRIM1_b;
21861     };
21862 
21863     union
21864     {
21865         __IOM uint16_t PHYTRIM2;         /*!< (@ 0x00000152) PHY Timing Register 2                                      */
21866 
21867         struct
21868         {
21869             __IOM uint16_t SQU      : 4; /*!< [3..0] Squelch Detection Level                                            */
21870             uint16_t                : 3;
21871             __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode                                     */
21872             __IOM uint16_t PDR      : 2; /*!< [9..8] HS Output Adjustment Function                                      */
21873             uint16_t                : 2;
21874             __IOM uint16_t DIS      : 3; /*!< [14..12] Disconnect Detection Level                                       */
21875             uint16_t                : 1;
21876         } PHYTRIM2_b;
21877     };
21878     __IM uint32_t RESERVED19[3];
21879 
21880     union
21881     {
21882         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
21883                                         *                  Register                                                   */
21884 
21885         struct
21886         {
21887             uint32_t              : 20;
21888             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
21889                                          *   HS side of USB port.                                                      */
21890             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
21891                                          *   HS side of USB port.                                                      */
21892             uint32_t               : 1;
21893             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
21894                                          *   of USB port.                                                              */
21895             uint32_t : 8;
21896         } DPUSR0R_b;
21897     };
21898 
21899     union
21900     {
21901         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
21902 
21903         struct
21904         {
21905             uint32_t                : 4;
21906             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
21907             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
21908             uint32_t                : 1;
21909             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
21910             uint32_t                : 12;
21911             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
21912             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
21913             uint32_t                : 1;
21914             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
21915             uint32_t                : 8;
21916         } DPUSR1R_b;
21917     };
21918 
21919     union
21920     {
21921         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
21922 
21923         struct
21924         {
21925             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
21926             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
21927             uint16_t            : 2;
21928             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
21929                                         *   port.                                                                     */
21930             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
21931                                         *   port.                                                                     */
21932             uint16_t              : 2;
21933             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
21934             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
21935             uint16_t              : 6;
21936         } DPUSR2R_b;
21937     };
21938 
21939     union
21940     {
21941         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
21942 
21943         struct
21944         {
21945             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
21946             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
21947             uint16_t                : 14;
21948         } DPUSRCR_b;
21949     };
21950 } R_USB_HS0_Type;                        /*!< Size = 364 (0x16c)                                                        */
21951 
21952 /* =========================================================================================================================== */
21953 /* ================                                          R_XSPI                                           ================ */
21954 /* =========================================================================================================================== */
21955 
21956 /**
21957  * @brief eXpanded SPI (R_XSPI)
21958  */
21959 
21960 typedef struct                           /*!< (@ 0x40268000) R_XSPI Structure                                           */
21961 {
21962     union
21963     {
21964         __IOM uint32_t WRAPCFG;          /*!< (@ 0x00000000) xSPI Wrapper Configuration register                        */
21965 
21966         struct
21967         {
21968             __IOM uint32_t CKSFTCS0 : 5; /*!< [4..0] CK shift for slave0                                                */
21969             uint32_t                : 3;
21970             __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0                                               */
21971             uint32_t                : 3;
21972             __IOM uint32_t CKSFTCS1 : 5; /*!< [20..16] CK shift for slave1                                              */
21973             uint32_t                : 3;
21974             __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1                                              */
21975             uint32_t                : 3;
21976         } WRAPCFG_b;
21977     };
21978 
21979     union
21980     {
21981         __IOM uint32_t COMCFG;              /*!< (@ 0x00000004) xSPI Common Configuration register                         */
21982 
21983         struct
21984         {
21985             __IOM uint32_t ARBMD       : 2; /*!< [1..0] Channel arbitration mode                                           */
21986             uint32_t                   : 2;
21987             __IOM uint32_t ECSINTOUTEN : 2; /*!< [5..4] ECS/INT Output Enable                                              */
21988             uint32_t                   : 10;
21989             __IOM uint32_t OEASTEX     : 1; /*!< [16..16] Output Enable Asserting extension                                */
21990             __IOM uint32_t OENEGEX     : 1; /*!< [17..17] Output Enable Negating extension                                 */
21991             uint32_t                   : 14;
21992         } COMCFG_b;
21993     };
21994 
21995     union
21996     {
21997         __IOM uint32_t BMCFGCH[2];        /*!< (@ 0x00000008) xSPI Bridge Map Configuration register                     */
21998 
21999         struct
22000         {
22001             __IOM uint32_t WRMD    : 1;   /*!< [0..0] AHB Write Response mode                                            */
22002             uint32_t               : 6;
22003             __IOM uint32_t MWRCOMB : 1;   /*!< [7..7] Memory Write Combination mode                                      */
22004             __IOM uint32_t MWRSIZE : 8;   /*!< [15..8] Memory Write Size                                                 */
22005             __IOM uint32_t PREEN   : 1;   /*!< [16..16] Prefetch enable                                                  */
22006             uint32_t               : 7;
22007             __IOM uint32_t CMBTIM  : 8;   /*!< [31..24] Combination timer                                                */
22008         } BMCFGCH_b[2];
22009     };
22010     __IOM R_XSPI_CMCFGCS_Type CMCFGCS[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration registers                   */
22011     __IM uint32_t             RESERVED[8];
22012 
22013     union
22014     {
22015         __IOM uint32_t LIOCFGCS[2];        /*!< (@ 0x00000050) xSPI Link I/O Configuration register CS[0..1]              */
22016 
22017         struct
22018         {
22019             __IOM uint32_t PRTMD     : 10; /*!< [9..0] Protocol mode                                                      */
22020             __IOM uint32_t LATEMD    : 1;  /*!< [10..10] Latency mode                                                     */
22021             __IOM uint32_t WRMSKMD   : 1;  /*!< [11..11] Write mask mode                                                  */
22022             uint32_t                 : 4;
22023             __IOM uint32_t CSMIN     : 4;  /*!< [19..16] CS minimum idle term                                             */
22024             __IOM uint32_t CSASTEX   : 1;  /*!< [20..20] CS asserting extension                                           */
22025             __IOM uint32_t CSNEGEX   : 1;  /*!< [21..21] CS negating extension                                            */
22026             __IOM uint32_t SDRDRV    : 1;  /*!< [22..22] SDR driving timing                                               */
22027             __IOM uint32_t SDRSMPMD  : 1;  /*!< [23..23] SDR Sampling mode                                                */
22028             __IOM uint32_t SDRSMPSFT : 4;  /*!< [27..24] SDR Sampling window shift                                        */
22029             __IOM uint32_t DDRSMPEX  : 4;  /*!< [31..28] DDR sampling window extend                                       */
22030         } LIOCFGCS_b[2];
22031     };
22032 
22033     union
22034     {
22035         __IOM uint32_t ABMCFG;         /*!< (@ 0x00000058) xSPI AXI Bridge Map Config                                 */
22036 
22037         struct
22038         {
22039             __IOM uint32_t ODRMD : 2;  /*!< [1..0] AXI Transfer Ordering Mode                                         */
22040             uint32_t             : 14;
22041             __IOM uint32_t CHSEL : 16; /*!< [31..16] AXI ID to Bridge Channel Select                                  */
22042         } ABMCFG_b;
22043     };
22044     __IM uint32_t RESERVED1;
22045 
22046     union
22047     {
22048         __IOM uint32_t BMCTL0;            /*!< (@ 0x00000060) xSPI Bridge Map Control register 0                         */
22049 
22050         struct
22051         {
22052             __IOM uint32_t CH0CS0ACC : 2; /*!< [1..0] System bus ch0 to slave0 memory area access enable                 */
22053             __IOM uint32_t CH0CS1ACC : 2; /*!< [3..2] System bus ch0 to slave1 memory area access enable                 */
22054             __IOM uint32_t CH1CS0ACC : 2; /*!< [5..4] System bus ch1 to slave0 memory area access enable                 */
22055             __IOM uint32_t CH1CS1ACC : 2; /*!< [7..6] System bus ch1 to slave1 memory area access enable                 */
22056             uint32_t                 : 24;
22057         } BMCTL0_b;
22058     };
22059 
22060     union
22061     {
22062         __OM uint32_t BMCTL1;          /*!< (@ 0x00000064) xSPI Bridge Map Control register 1                         */
22063 
22064         struct
22065         {
22066             uint32_t                 : 8;
22067             __OM uint32_t MWRPUSHCH0 : 1; /*!< [8..8] Memory Write Data Push for ch0                                     */
22068             __OM uint32_t MWRPUSHCH1 : 1; /*!< [9..9] Memory Write Data Push for ch1                                     */
22069             __OM uint32_t PBUFCLRCH0 : 1; /*!< [10..10] Prefetch Buffer clear for ch0                                    */
22070             __OM uint32_t PBUFCLRCH1 : 1; /*!< [11..11] Prefetch Buffer clear for ch1                                    */
22071             uint32_t                 : 20;
22072         } BMCTL1_b;
22073     };
22074 
22075     union
22076     {
22077         __IOM uint32_t CMCTLCH[2];        /*!< (@ 0x00000068) xSPI Command Map Control register                          */
22078 
22079         struct
22080         {
22081             __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code                                                */
22082             __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code                                                */
22083             __IOM uint32_t XIPEN     : 1; /*!< [16..16] XiP mode enable                                                  */
22084             uint32_t                 : 15;
22085         } CMCTLCH_b[2];
22086     };
22087 
22088     union
22089     {
22090         __IOM uint32_t CDCTL0;         /*!< (@ 0x00000070) xSPI Command Manual Control register 0                     */
22091 
22092         struct
22093         {
22094             __IOM uint32_t TRREQ  : 1; /*!< [0..0] Transaction request                                                */
22095             __IOM uint32_t PERMD  : 1; /*!< [1..1] Periodic mode                                                      */
22096             uint32_t              : 1;
22097             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
22098             __IOM uint32_t TRNUM  : 2; /*!< [5..4] Transaction number                                                 */
22099             uint32_t              : 10;
22100             __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval                                    */
22101             uint32_t              : 3;
22102             __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat                                      */
22103             uint32_t              : 4;
22104         } CDCTL0_b;
22105     };
22106 
22107     union
22108     {
22109         __IOM uint32_t CDCTL1;          /*!< (@ 0x00000074) xSPI Command Manual Control register 1                     */
22110 
22111         struct
22112         {
22113             __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value                               */
22114         } CDCTL1_b;
22115     };
22116 
22117     union
22118     {
22119         __IOM uint32_t CDCTL2;          /*!< (@ 0x00000078) xSPI Command Manual Control register 2                     */
22120 
22121         struct
22122         {
22123             __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value                                 */
22124         } CDCTL2_b;
22125     };
22126     __IM uint32_t           RESERVED2;
22127     __IOM R_XSPI_CDBUF_Type CDBUF[4];   /*!< (@ 0x00000080) xSPI BUF register                                          */
22128     __IM uint32_t           RESERVED3[16];
22129 
22130     union
22131     {
22132         __IOM uint32_t LPCTL0;         /*!< (@ 0x00000100) xSPI Link Pattern Control register 0                       */
22133 
22134         struct
22135         {
22136             __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request                                                    */
22137             uint32_t              : 2;
22138             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
22139             __IOM uint32_t XDPIN  : 2; /*!< [5..4] XiP Disable pattern pin                                            */
22140             uint32_t              : 10;
22141             __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length                             */
22142             uint32_t              : 2;
22143             __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value                              */
22144             __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length                             */
22145             uint32_t              : 2;
22146             __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value                              */
22147         } LPCTL0_b;
22148     };
22149 
22150     union
22151     {
22152         __IOM uint32_t LPCTL1;         /*!< (@ 0x00000104) xSPI Link Pattern Control register 1                       */
22153 
22154         struct
22155         {
22156             __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request                                                    */
22157             uint32_t              : 1;
22158             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
22159             __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat                                               */
22160             uint32_t              : 2;
22161             __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width                                               */
22162             uint32_t              : 1;
22163             __IOM uint32_t RSTSU  : 3; /*!< [14..12] Reset pattern data output setup time                             */
22164             uint32_t              : 17;
22165         } LPCTL1_b;
22166     };
22167 
22168     union
22169     {
22170         __IOM uint32_t LIOCTL;         /*!< (@ 0x00000108) xSPI Link I/O Control register                             */
22171 
22172         struct
22173         {
22174             __IOM uint32_t WPCS0  : 1; /*!< [0..0] WP drive for slave 0                                               */
22175             __IOM uint32_t WPCS1  : 1; /*!< [1..1] WP drive for slave 1                                               */
22176             uint32_t              : 14;
22177             __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave 0                                          */
22178             __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave 1                                          */
22179             uint32_t              : 14;
22180         } LIOCTL_b;
22181     };
22182     __IM uint32_t             RESERVED4[9];
22183     __IOM R_XSPI_CCCTLCS_Type CCCTLCS[2]; /*!< (@ 0x00000130) xSPI CS register                                           */
22184     __IM uint32_t             RESERVED5[4];
22185 
22186     union
22187     {
22188         __IM uint32_t VERSTT;          /*!< (@ 0x00000180) xSPI Version register                                      */
22189 
22190         struct
22191         {
22192             __IM uint32_t VER : 32;    /*!< [31..0] Version                                                           */
22193         } VERSTT_b;
22194     };
22195 
22196     union
22197     {
22198         __IM uint32_t COMSTT;             /*!< (@ 0x00000184) xSPI Common Status register                                */
22199 
22200         struct
22201         {
22202             __IM uint32_t MEMACCCH0  : 1; /*!< [0..0] Memory access ongoing from ch0                                     */
22203             __IM uint32_t MEMACCCH1  : 1; /*!< [1..1] Memory access ongoing from ch1                                     */
22204             uint32_t                 : 2;
22205             __IM uint32_t PBUFNECH0  : 1; /*!< [4..4] Prefetch Buffer Not Empty for ch0                                  */
22206             __IM uint32_t PBUFNECH1  : 1; /*!< [5..5] Prefetch Buffer Not Empty for ch1                                  */
22207             __IM uint32_t WRBUFNECH0 : 1; /*!< [6..6] Write Buffer Not Empty for ch0                                     */
22208             __IM uint32_t WRBUFNECH1 : 1; /*!< [7..7] Write Buffer Not Empty for ch1                                     */
22209             uint32_t                 : 8;
22210             __IM uint32_t ECSCS0     : 1; /*!< [16..16] ECS monitor for slave0                                           */
22211             __IM uint32_t INTCS0     : 1; /*!< [17..17] INT monitor for slave0                                           */
22212             __IM uint32_t RSTOCS0    : 1; /*!< [18..18] RSTO monitor for slave0                                          */
22213             uint32_t                 : 1;
22214             __IM uint32_t ECSCS1     : 1; /*!< [20..20] ECS monitor for slave1                                           */
22215             __IM uint32_t INTCS1     : 1; /*!< [21..21] INT monitor for slave1                                           */
22216             __IM uint32_t RSTOCS1    : 1; /*!< [22..22] RSTO monitor for slave1                                          */
22217             uint32_t                 : 9;
22218         } COMSTT_b;
22219     };
22220 
22221     union
22222     {
22223         __IM uint32_t CASTTCS[2];      /*!< (@ 0x00000188) xSPI Calibration Status register                           */
22224 
22225         struct
22226         {
22227             __IM uint32_t CASUC : 32;  /*!< [31..0] Calibration Success                                               */
22228         } CASTTCS_b[2];
22229     };
22230 
22231     union
22232     {
22233         __IM uint32_t INTS;              /*!< (@ 0x00000190) xSPI Interrupt Status register                             */
22234 
22235         struct
22236         {
22237             __IM uint32_t CMDCMP    : 1; /*!< [0..0] Command Completed                                                  */
22238             __IM uint32_t PATCMP    : 1; /*!< [1..1] Pattern Completed                                                  */
22239             __IM uint32_t INICMP    : 1; /*!< [2..2] Initial Sequence Completed                                         */
22240             __IM uint32_t PERTO     : 1; /*!< [3..3] Periodic transaction timeout                                       */
22241             __IM uint32_t DSTOCS0   : 1; /*!< [4..4] DS timeout for slave0                                              */
22242             __IM uint32_t DSTOCS1   : 1; /*!< [5..5] DS timeout for slave1                                              */
22243             uint32_t                : 2;
22244             __IM uint32_t ECSCS0    : 1; /*!< [8..8] ECC error detection for slave0                                     */
22245             __IM uint32_t ECSCS1    : 1; /*!< [9..9] ECC error detection for slave1                                     */
22246             uint32_t                : 2;
22247             __IM uint32_t INTCS0    : 1; /*!< [12..12] Interrupt detection for slave0                                   */
22248             __IM uint32_t INTCS1    : 1; /*!< [13..13] Interrupt detection for slave1                                   */
22249             uint32_t                : 2;
22250             __IM uint32_t BRGOFCH0  : 1; /*!< [16..16] Bridge Buffer overflow for CH0                                   */
22251             __IM uint32_t BRGOFCH1  : 1; /*!< [17..17] Bridge Buffer overflow for CH1                                   */
22252             __IM uint32_t BRGUFCH0  : 1; /*!< [18..18] Bridge Buffer underflow for CH0                                  */
22253             __IM uint32_t BRGUFCH1  : 1; /*!< [19..19] Bridge Buffer underflow for CH1                                  */
22254             __IM uint32_t BUSERRCH0 : 1; /*!< [20..20] AHB bus error for CH0                                            */
22255             __IM uint32_t BUSERRCH1 : 1; /*!< [21..21] AHB bus error for CH1                                            */
22256             uint32_t                : 6;
22257             __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0                                    */
22258             __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1                                    */
22259             __IM uint32_t CASUCCS0  : 1; /*!< [30..30] Calibration success for slave0                                   */
22260             __IM uint32_t CASUCCS1  : 1; /*!< [31..31] Calibration success for slave1                                   */
22261         } INTS_b;
22262     };
22263 
22264     union
22265     {
22266         __OM uint32_t INTC;               /*!< (@ 0x00000194) xSPI Interrupt Clear register                              */
22267 
22268         struct
22269         {
22270             __OM uint32_t CMDCMPC    : 1; /*!< [0..0] Command Completed interrupt clear                                  */
22271             __OM uint32_t PATCMPC    : 1; /*!< [1..1] Pattern Completed interrupt clear                                  */
22272             __OM uint32_t INICMPC    : 1; /*!< [2..2] Initial Sequence Completed interrupt clear                         */
22273             __OM uint32_t PERTOC     : 1; /*!< [3..3] Periodic transaction timeout interrupt clear                       */
22274             __OM uint32_t DSTOCS0C   : 1; /*!< [4..4] DS timeout for slave0 interrupt clear                              */
22275             __OM uint32_t DSTOCS1C   : 1; /*!< [5..5] DS timeout for slave1 interrupt clear                              */
22276             uint32_t                 : 2;
22277             __OM uint32_t ECSCS0C    : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear                     */
22278             __OM uint32_t ECSCS1C    : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear                     */
22279             uint32_t                 : 2;
22280             __OM uint32_t INTCS0C    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear                   */
22281             __OM uint32_t INTCS1C    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear                   */
22282             uint32_t                 : 2;
22283             __OM uint32_t BRGOFCH0C  : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt clear                   */
22284             __OM uint32_t BRGOFCH1C  : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt clear                   */
22285             __OM uint32_t BRGUFCH0C  : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt clear                  */
22286             __OM uint32_t BRGUFCH1C  : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt clear                  */
22287             __OM uint32_t BUSERRCH0C : 1; /*!< [20..20] AHB bus error for CH0 interrupt clear                            */
22288             __OM uint32_t BUSERRCH1C : 1; /*!< [21..21] AHB bus error for CH1 interrupt clear                            */
22289             uint32_t                 : 6;
22290             __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear                    */
22291             __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear                    */
22292             __OM uint32_t CASUCCS0C  : 1; /*!< [30..30] Calibration success for slave0 interrupt clear                   */
22293             __OM uint32_t CASUCCS1C  : 1; /*!< [31..31] Calibration success for slave1 interrupt clear                   */
22294         } INTC_b;
22295     };
22296 
22297     union
22298     {
22299         __IOM uint32_t INTE;               /*!< (@ 0x00000198) xSPI Interrupt Enable register                             */
22300 
22301         struct
22302         {
22303             __IOM uint32_t CMDCMPE    : 1; /*!< [0..0] Command Completed interrupt enable                                 */
22304             __IOM uint32_t PATCMPE    : 1; /*!< [1..1] Pattern Completed interrupt enable                                 */
22305             __IOM uint32_t INICMPE    : 1; /*!< [2..2] Initial Sequence Completed interrupt enable                        */
22306             __IOM uint32_t PERTOE     : 1; /*!< [3..3] Periodic transaction timeout interrupt enable                      */
22307             __IOM uint32_t DSTOCS0E   : 1; /*!< [4..4] DS timeout for slave0 interrupt enable                             */
22308             __IOM uint32_t DSTOCS1E   : 1; /*!< [5..5] DS timeout for slave1 interrupt enable                             */
22309             uint32_t                  : 2;
22310             __IOM uint32_t ECSCS0E    : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable                    */
22311             __IOM uint32_t ECSCS1E    : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable                    */
22312             uint32_t                  : 2;
22313             __IOM uint32_t INTCS0E    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable                  */
22314             __IOM uint32_t INTCS1E    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable                  */
22315             uint32_t                  : 2;
22316             __IOM uint32_t BRGOFCH0E  : 1; /*!< [16..16] Bridge Buffer overflow for CH0 interrupt enable                  */
22317             __IOM uint32_t BRGOFCH1E  : 1; /*!< [17..17] Bridge Buffer overflow for CH1 interrupt enable                  */
22318             __IOM uint32_t BRGUFCH0E  : 1; /*!< [18..18] Bridge Buffer underflow for CH0 interrupt enable                 */
22319             __IOM uint32_t BRGUFCH1E  : 1; /*!< [19..19] Bridge Buffer underflow for CH1 interrupt enable                 */
22320             __IOM uint32_t BUSERRCH0E : 1; /*!< [20..20] AHB bus error for CH0 interrupt enable                           */
22321             __IOM uint32_t BUSERRCH1E : 1; /*!< [21..21] AHB bus error for CH1 interrupt enable                           */
22322             uint32_t                  : 6;
22323             __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable                   */
22324             __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable                   */
22325             __IOM uint32_t CASUCCS0E  : 1; /*!< [30..30] Calibration success for slave0 interrupt enable                  */
22326             __IOM uint32_t CASUCCS1E  : 1; /*!< [31..31] Calibration success for slave1 interrupt enable                  */
22327         } INTE_b;
22328     };
22329 } R_XSPI_Type;                             /*!< Size = 412 (0x19c)                                                        */
22330 
22331 /* =========================================================================================================================== */
22332 /* ================                                           R_CEU                                           ================ */
22333 /* =========================================================================================================================== */
22334 
22335 /**
22336  * @brief Capture Engine Unit (R_CEU)
22337  */
22338 
22339 typedef struct                         /*!< (@ 0x40348000) R_CEU Structure                                            */
22340 {
22341     union
22342     {
22343         __IOM uint32_t CAPSR;          /*!< (@ 0x00000000) Capture Start Register                                     */
22344 
22345         struct
22346         {
22347             __IOM uint32_t CE    : 1;  /*!< [0..0] Capture enable                                                     */
22348             uint32_t             : 15;
22349             __IOM uint32_t CPKIL : 1;  /*!< [16..16] Write 1 to this bit to perform a software reset of
22350                                         *   capturing.                                                                */
22351             uint32_t : 15;
22352         } CAPSR_b;
22353     };
22354 
22355     union
22356     {
22357         __IOM uint32_t CAPCR;          /*!< (@ 0x00000004) Capture Control Register                                   */
22358 
22359         struct
22360         {
22361             uint32_t             : 16;
22362             __IOM uint32_t CTNCP : 1;  /*!< [16..16] When capturing is started with this bit set to 1, capturing
22363                                         *   continues until the CE bit in CAPSR is cleared to 0 or
22364                                         *   a software reset is initiated by the CPKIL bit in CAPSR
22365                                         *   (see ). Continuous capture must be set before capturing
22366                                         *   is started.                                                               */
22367             uint32_t            : 3;
22368             __IOM uint32_t MTCM : 2;   /*!< [21..20] Specify the unit for transferring data to a bus bridge
22369                                         *   module.                                                                   */
22370             uint32_t            : 2;
22371             __IOM uint32_t FDRP : 8;   /*!< [31..24] Set the frame drop interval in continuous-frame capture.         */
22372         } CAPCR_b;
22373     };
22374 
22375     union
22376     {
22377         __IOM uint32_t CAMCR;          /*!< (@ 0x00000008) Capture interface control register                         */
22378 
22379         struct
22380         {
22381             __IOM uint32_t HDPOL : 1;  /*!< [0..0] Sets the polarity for detection of the horizontal sync
22382                                         *   signal input from an external module.                                     */
22383             __IOM uint32_t VDPOL : 1;  /*!< [1..1] Sets the polarity for detection of the vertical sync
22384                                         *   signal input from an external module.                                     */
22385             uint32_t             : 2;
22386             __IOM uint32_t JPG   : 2;  /*!< [5..4] These bits select the fetched data type.                           */
22387             uint32_t             : 2;
22388             __IOM uint32_t DTARY : 2;  /*!< [9..8] Set the input order of the luminance component and chrominance
22389                                         *   component.                                                                */
22390             uint32_t            : 2;
22391             __IOM uint32_t DTIF : 1;   /*!< [12..12] Sets the digital image input pins from which data is
22392                                         *   to be captured.                                                           */
22393             uint32_t              : 3;
22394             __IOM uint32_t FLDPOL : 1; /*!< [16..16] Sets the polarity of the field identification signal
22395                                         *   (FLD) from an external module.                                            */
22396             uint32_t            : 7;
22397             __IOM uint32_t DSEL : 1;   /*!< [24..24] Sets the edge for fetching the image data (D7 to D0)
22398                                         *   from an external module.                                                  */
22399             __IOM uint32_t FLDSEL : 1; /*!< [25..25] Sets the edge for capturing the field identification
22400                                         *   signal (FLD) from an external module.                                     */
22401             __IOM uint32_t HDSEL : 1;  /*!< [26..26] Sets the edge for capturing the horizontal sync signal
22402                                         *   (HD) from an external module.                                             */
22403             __IOM uint32_t VDSEL : 1;  /*!< [27..27] Sets the edge for capturing the vertical sync signal
22404                                         *   (VD) from an external module.                                             */
22405             uint32_t : 4;
22406         } CAMCR_b;
22407     };
22408 
22409     union
22410     {
22411         __IOM uint32_t CMCYR;          /*!< (@ 0x0000000C) Capture Interface Cycle Register                           */
22412 
22413         struct
22414         {
22415             __IOM uint32_t HCYL : 14;  /*!< [13..0] Horizontal Cycle Count of External Module                         */
22416             uint32_t            : 2;
22417             __IOM uint32_t VCYL : 14;  /*!< [29..16] Vertical HD Count of External Module                             */
22418             uint32_t            : 2;
22419         } CMCYR_b;
22420     };
22421 
22422     union
22423     {
22424         __IOM uint32_t CAMOR;          /*!< (@ 0x00000010) Capture Interface Offset Register                          */
22425 
22426         struct
22427         {
22428             __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number
22429                                         *   of clock cycles from a horizontal sync signal (1-cycle
22430                                         *   units).                                                                   */
22431             uint32_t             : 3;
22432             __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the
22433                                         *   HD count from a vertical sync signal (1-HD units).                        */
22434             uint32_t : 4;
22435         } CAMOR_b;
22436     };
22437 
22438     union
22439     {
22440         __IOM uint32_t CAPWR;          /*!< (@ 0x00000014) Capture Interface Width Register                           */
22441 
22442         struct
22443         {
22444             __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period.                            */
22445             uint32_t             : 3;
22446             __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units).                */
22447             uint32_t             : 4;
22448         } CAPWR_b;
22449     };
22450 
22451     union
22452     {
22453         __IOM uint32_t CAIFR;          /*!< (@ 0x00000018) Capture Interface Input Format Register                    */
22454 
22455         struct
22456         {
22457             __IOM uint32_t FCI : 2;    /*!< [1..0] Set the timing to start capturing.                                 */
22458             uint32_t           : 2;
22459             __IOM uint32_t CIM : 1;    /*!< [4..4] Sets the images to be captured.                                    */
22460             uint32_t           : 3;
22461             __IOM uint32_t IFS : 1;    /*!< [8..8] Sets the input mode for capturing images.                          */
22462             uint32_t           : 23;
22463         } CAIFR_b;
22464     };
22465     __IM uint32_t RESERVED[3];
22466 
22467     union
22468     {
22469         __IOM uint32_t CRCNTR;         /*!< (@ 0x00000028) CEU Register Control Register                              */
22470 
22471         struct
22472         {
22473             __IOM uint32_t RC : 1;     /*!< [0..0] Specifies switching of the register plane used by the
22474                                         *   CEU in synchronization with VD.                                           */
22475             __IOM uint32_t RS : 1;     /*!< [1..1] Specifies which register plane is used by the CEU in
22476                                         *   synchronization with VD.                                                  */
22477             uint32_t           : 2;
22478             __IOM uint32_t RVS : 1;    /*!< [4..4] Sets the timing to switch the register plane in both-field
22479                                         *   capture.                                                                  */
22480             uint32_t : 27;
22481         } CRCNTR_b;
22482     };
22483 
22484     union
22485     {
22486         __IOM uint32_t CRCMPR;         /*!< (@ 0x0000002C) CEU Register Forcible Control Register                     */
22487 
22488         struct
22489         {
22490             __IOM uint32_t RA : 1;     /*!< [0..0] Indicates the register plane currently specified.                  */
22491             uint32_t          : 31;
22492         } CRCMPR_b;
22493     };
22494 
22495     union
22496     {
22497         __IOM uint32_t CFLCR;          /*!< (@ 0x00000030) Capture Filter Control Register                            */
22498 
22499         struct
22500         {
22501             __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor                     */
22502             __IOM uint32_t HMANT : 4;  /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor                    */
22503             __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor                      */
22504             __IOM uint32_t VMANT : 4;  /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor                      */
22505         } CFLCR_b;
22506     };
22507 
22508     union
22509     {
22510         __IOM uint32_t CFSZR;          /*!< (@ 0x00000034) Capture Filter Size Clip Register                          */
22511 
22512         struct
22513         {
22514             __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter
22515                                         *   output size (4-pixel units).                                              */
22516             uint32_t             : 4;
22517             __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output
22518                                         *   size (4-pixel units).                                                     */
22519             uint32_t : 4;
22520         } CFSZR_b;
22521     };
22522 
22523     union
22524     {
22525         __IOM uint32_t CDWDR;          /*!< (@ 0x00000038) Capture Destination Width Register                         */
22526 
22527         struct
22528         {
22529             __IOM uint32_t CHDW : 13;  /*!< [12..0] Specify the horizontal image size in the memory area
22530                                         *   where the captured image is to be stored (4-byte units).                  */
22531             uint32_t : 19;
22532         } CDWDR_b;
22533     };
22534 
22535     union
22536     {
22537         __IOM uint32_t CDAYR;          /*!< (@ 0x0000003C) Capture Data Address Y Register                            */
22538 
22539         struct
22540         {
22541             __IOM uint32_t CAYR : 32;  /*!< [31..0] Capture Data Address Y                                            */
22542         } CDAYR_b;
22543     };
22544 
22545     union
22546     {
22547         __IOM uint32_t CDACR;          /*!< (@ 0x00000040) Capture Data Address C Register                            */
22548 
22549         struct
22550         {
22551             __IOM uint32_t CACR : 32;  /*!< [31..0] Capture Data Address C                                            */
22552         } CDACR_b;
22553     };
22554 
22555     union
22556     {
22557         __IOM uint32_t CDBYR;          /*!< (@ 0x00000044) Capture Data Bottom-Field Address Y Register               */
22558 
22559         struct
22560         {
22561             __IOM uint32_t CBYR : 32;  /*!< [31..0] Set the address for storing the Y (luminance) component
22562                                         *   data of the captured bottom-field data (4-pixel units).                   */
22563         } CDBYR_b;
22564     };
22565 
22566     union
22567     {
22568         __IOM uint32_t CDBCR;          /*!< (@ 0x00000048) Capture Data Bottom-Field Address C Register               */
22569 
22570         struct
22571         {
22572             __IOM uint32_t CBCR : 32;  /*!< [31..0] Set the address for storing the C (chrominance) component
22573                                         *   data of the captured bottom-field data (4-pixel units).                   */
22574         } CDBCR_b;
22575     };
22576 
22577     union
22578     {
22579         __IOM uint32_t CBDSR;          /*!< (@ 0x0000004C) Capture Bundle Destination Size Register                   */
22580 
22581         struct
22582         {
22583             __IOM uint32_t CBVS : 23;  /*!< [22..0] Select the number of lines or number of bytes for output
22584                                         *   to the memory in a bundle write.                                          */
22585             uint32_t : 9;
22586         } CBDSR_b;
22587     };
22588     __IM uint32_t RESERVED1[3];
22589 
22590     union
22591     {
22592         __IOM uint32_t CFWCR;          /*!< (@ 0x0000005C) Firewall Operation Control Register                        */
22593 
22594         struct
22595         {
22596             __IOM uint32_t FWE : 1;    /*!< [0..0] With the setting of FWE = 1, when an address exceeds
22597                                         *   the value set with FWV, the address is retained and an
22598                                         *   interrupt source FWF is set. After this, the address is
22599                                         *   not incremented and data is overwritten on the upper limit
22600                                         *   address.                                                                  */
22601             uint32_t           : 4;
22602             __IOM uint32_t FWV : 27;   /*!< [31..5] Specify the upper limit of a write address.                       */
22603         } CFWCR_b;
22604     };
22605 
22606     union
22607     {
22608         __IOM uint32_t CLFCR;          /*!< (@ 0x00000060) Capture Low-Pass Filter Control Register                   */
22609 
22610         struct
22611         {
22612             __IOM uint32_t LPF : 1;    /*!< [0..0] Enables or disables operation of the low-pass filter.              */
22613             uint32_t           : 31;
22614         } CLFCR_b;
22615     };
22616 
22617     union
22618     {
22619         __IOM uint32_t CDOCR;          /*!< (@ 0x00000064) Capture Data Output Control Register                       */
22620 
22621         struct
22622         {
22623             __IOM uint32_t COBS : 1;   /*!< [0..0] Controls swapping in 8-bit units for data output from
22624                                         *   the CEU.                                                                  */
22625             __IOM uint32_t COWS : 1;   /*!< [1..1] Controls swapping in 16-bit units for data output from
22626                                         *   the CEU.                                                                  */
22627             __IOM uint32_t COLS : 1;   /*!< [2..2] Controls swapping in 32-bit units for data output from
22628                                         *   the CEU.                                                                  */
22629             uint32_t           : 1;
22630             __IOM uint32_t CDS : 1;    /*!< [4..4] Sets the image format when outputting the image data
22631                                         *   captured in the YCbCr422 format to the memory.                            */
22632             uint32_t           : 11;
22633             __IOM uint32_t CBE : 1;    /*!< [16..16] Controls the number of lines of captured data to be
22634                                         *   written to the memory.                                                    */
22635             uint32_t : 15;
22636         } CDOCR_b;
22637     };
22638     __IM uint32_t RESERVED2[2];
22639 
22640     union
22641     {
22642         __IOM uint32_t CEIER;           /*!< (@ 0x00000070) Capture Event Interrupt Enable Register                    */
22643 
22644         struct
22645         {
22646             __IOM uint32_t CPEIE   : 1; /*!< [0..0] One-Frame Capture End Interrupt Enable                             */
22647             __IOM uint32_t CFEIE   : 1; /*!< [1..1] CFE Interrupt Enable                                               */
22648             uint32_t               : 2;
22649             __IOM uint32_t IGRWIE  : 1; /*!< [4..4] Register-Access-During-Capture Interrupt Enable                    */
22650             uint32_t               : 3;
22651             __IOM uint32_t HDIE    : 1; /*!< [8..8] HD Interrupt Enable                                                */
22652             __IOM uint32_t VDIE    : 1; /*!< [9..9] VD Interrupt Enable                                                */
22653             uint32_t               : 2;
22654             __IOM uint32_t CPBE1IE : 1; /*!< [12..12] CPBE1 Interrupt Enable                                           */
22655             __IOM uint32_t CPBE2IE : 1; /*!< [13..13] CPBE2 Interrupt Enable                                           */
22656             __IOM uint32_t CPBE3IE : 1; /*!< [14..14] CPBE3 Interrupt Enable                                           */
22657             __IOM uint32_t CPBE4IE : 1; /*!< [15..15] CPBE4 Interrupt Enable                                           */
22658             __IOM uint32_t CDTOFIE : 1; /*!< [16..16] CDTOF Interrupt Enable                                           */
22659             __IOM uint32_t IGHSIE  : 1; /*!< [17..17] IGHS Interrupt Enable                                            */
22660             __IOM uint32_t IGVSIE  : 1; /*!< [18..18] IGVS Interrupt Enable                                            */
22661             uint32_t               : 1;
22662             __IOM uint32_t VBPIE   : 1; /*!< [20..20] VBP Interrupt Enable                                             */
22663             uint32_t               : 2;
22664             __IOM uint32_t FWFIE   : 1; /*!< [23..23] FWF Interrupt Enable                                             */
22665             __IOM uint32_t NHDIE   : 1; /*!< [24..24] Non-HD Interrupt Enable                                          */
22666             __IOM uint32_t NVDIE   : 1; /*!< [25..25] Non-VD Interrupt Enable                                          */
22667             uint32_t               : 6;
22668         } CEIER_b;
22669     };
22670 
22671     union
22672     {
22673         __IOM uint32_t CETCR;          /*!< (@ 0x00000074) Capture Event Flag Clear Register                          */
22674 
22675         struct
22676         {
22677             __IOM uint32_t CPE : 1;    /*!< [0..0] An interrupt indicating that capturing of one frame from
22678                                         *   an external module has finished.                                          */
22679             __IOM uint32_t CFE : 1;    /*!< [1..1] An interrupt indicating that capturing of one field from
22680                                         *   an external module has finished.                                          */
22681             uint32_t            : 2;
22682             __IOM uint32_t IGRW : 1;   /*!< [4..4] An interrupt indicating that during capturing, access
22683                                         *   was attempted to a register to which writing during operation
22684                                         *   is prohibited.                                                            */
22685             uint32_t          : 3;
22686             __IOM uint32_t HD : 1;     /*!< [8..8] An interrupt indicating that HD (horizontal sync signal)
22687                                         *   was input from an external module.                                        */
22688             __IOM uint32_t VD : 1;     /*!< [9..9] An interrupt indicating that VD (vertical sync signal)
22689                                         *   was input from an external module.                                        */
22690             uint32_t             : 2;
22691             __IOM uint32_t CPBE1 : 1;  /*!< [12..12] An interrupt indicating that writing to CDAYR and CDACR
22692                                         *   in a bundle write has finished.                                           */
22693             __IOM uint32_t CPBE2 : 1;  /*!< [13..13] An interrupt indicating that writing to CDAYR2 and
22694                                         *   CDACR2 in a bundle write has finished.                                    */
22695             __IOM uint32_t CPBE3 : 1;  /*!< [14..14] An interrupt indicating that writing to CDBYR and CDBCR
22696                                         *   in a bundle write has finished.                                           */
22697             __IOM uint32_t CPBE4 : 1;  /*!< [15..15] An interrupt indicating that writing to CDBYR2 and
22698                                         *   CDBCR2 in a bundle write has finished.                                    */
22699             __IOM uint32_t CDTOF : 1;  /*!< [16..16] An interrupt indicating that data overflowed in the
22700                                         *   CRAM of the write buffer                                                  */
22701             __IOM uint32_t IGHS : 1;   /*!< [17..17] An interrupt generated when the number of HD cycles
22702                                         *   set in CMCYR differ from the number of HD cycles input
22703                                         *   from an external module.                                                  */
22704             __IOM uint32_t IGVS : 1;   /*!< [18..18] An interrupt generated when the number of VD cycles
22705                                         *   set in CMCYR differ from the number of VD cycles input
22706                                         *   from an external module.                                                  */
22707             uint32_t           : 1;
22708             __IOM uint32_t VBP : 1;    /*!< [20..20] An interrupt indicating that VD has been input while
22709                                         *   the CEU holds data (insufficient vertical-sync front porch).              */
22710             uint32_t           : 2;
22711             __IOM uint32_t FWF : 1;    /*!< [23..23] The interrupt is generated when data is written to
22712                                         *   the address that exceeds the value specified with CFWCR.FMV.              */
22713             __IOM uint32_t NHD : 1;    /*!< [24..24] An interrupt indicating that no HD was input.                    */
22714             __IOM uint32_t NVD : 1;    /*!< [25..25] An interrupt indicating that no VD was input.                    */
22715             uint32_t           : 6;
22716         } CETCR_b;
22717     };
22718     __IM uint32_t RESERVED3;
22719 
22720     union
22721     {
22722         __IM uint32_t CSTSR;           /*!< (@ 0x0000007C) Capture Status Register                                    */
22723 
22724         struct
22725         {
22726             __IM uint32_t CPTON : 1;   /*!< [0..0] Indicates that the CEU is operating.                               */
22727             uint32_t            : 15;
22728             __IM uint32_t CPFLD : 1;   /*!< [16..16] Indicates which field is being captured.                         */
22729             uint32_t            : 7;
22730             __IM uint32_t CRST  : 1;   /*!< [24..24] Indicates which register plane is currently used.                */
22731             uint32_t            : 7;
22732         } CSTSR_b;
22733     };
22734     __IM uint32_t RESERVED4;
22735 
22736     union
22737     {
22738         __IM uint32_t CDSSR;           /*!< (@ 0x00000084) Capture Data Size Register                                 */
22739 
22740         struct
22741         {
22742             __IM uint32_t CDSS : 32;   /*!< [31..0] Indicate the size of data written to the memory in data
22743                                         *   enable fetch.                                                             */
22744         } CDSSR_b;
22745     };
22746     __IM uint32_t RESERVED5[2];
22747 
22748     union
22749     {
22750         __IOM uint32_t CDAYR2;         /*!< (@ 0x00000090) Capture Data Address Y Register 2                          */
22751 
22752         struct
22753         {
22754             __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y                                            */
22755         } CDAYR2_b;
22756     };
22757 
22758     union
22759     {
22760         __IOM uint32_t CDACR2;         /*!< (@ 0x00000094) Capture Data Address C Register 2                          */
22761 
22762         struct
22763         {
22764             __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2                                           */
22765         } CDACR2_b;
22766     };
22767 
22768     union
22769     {
22770         __IOM uint32_t CDBYR2;         /*!< (@ 0x00000098) Capture Data Bottom-Field Address Y Register
22771                                         *                  2                                                          */
22772 
22773         struct
22774         {
22775             __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of
22776                                         *   the captured bottom-field data (4-pixel units).                           */
22777         } CDBYR2_b;
22778     };
22779 
22780     union
22781     {
22782         __IOM uint32_t CDBCR2;         /*!< (@ 0x0000009C) Capture Data Bottom-Field Address C Register
22783                                         *                  2                                                          */
22784 
22785         struct
22786         {
22787             __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of
22788                                         *   the captured bottom-field data (4-pixel units).                           */
22789         } CDBCR2_b;
22790     };
22791 
22792     union
22793     {
22794         __IOM uint32_t AXIBUSCTL2;      /*!< (@ 0x000000A0) AXI Bus Control Register 2                                 */
22795 
22796         struct
22797         {
22798             __IOM uint32_t AWCACHE : 4; /*!< [3..0] AWCACHE[3:0] Signals for Capture Engine Unit                       */
22799             uint32_t               : 28;
22800         } AXIBUSCTL2_b;
22801     };
22802     __IM uint32_t RESERVED6[987];
22803 
22804     union
22805     {
22806         __IOM uint32_t CAMOR_B;        /*!< (@ 0x00001010) Capture Interface Offset Register                          */
22807 
22808         struct
22809         {
22810             __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number
22811                                         *   of clock cycles from a horizontal sync signal (1-cycle
22812                                         *   units).                                                                   */
22813             uint32_t             : 3;
22814             __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the
22815                                         *   HD count from a vertical sync signal (1-HD units).                        */
22816             uint32_t : 4;
22817         } CAMOR_B_b;
22818     };
22819 
22820     union
22821     {
22822         __IOM uint32_t CAPWR_B;        /*!< (@ 0x00001014) Capture Interface Width Register                           */
22823 
22824         struct
22825         {
22826             __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period.                            */
22827             uint32_t             : 3;
22828             __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units).                */
22829             uint32_t             : 4;
22830         } CAPWR_B_b;
22831     };
22832     __IM uint32_t RESERVED7[6];
22833 
22834     union
22835     {
22836         __IOM uint32_t CFLCR_B;        /*!< (@ 0x00001030) Capture Filter Control Register                            */
22837 
22838         struct
22839         {
22840             __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor                     */
22841             __IOM uint32_t HMANT : 4;  /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor                    */
22842             __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor                      */
22843             __IOM uint32_t VMANT : 4;  /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor                      */
22844         } CFLCR_B_b;
22845     };
22846 
22847     union
22848     {
22849         __IOM uint32_t CFSZR_B;        /*!< (@ 0x00001034) Capture Filter Size Clip Register                          */
22850 
22851         struct
22852         {
22853             __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter
22854                                         *   output size (4-pixel units).                                              */
22855             uint32_t             : 4;
22856             __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output
22857                                         *   size (4-pixel units).                                                     */
22858             uint32_t : 4;
22859         } CFSZR_B_b;
22860     };
22861 
22862     union
22863     {
22864         __IOM uint32_t CDWDR_B;        /*!< (@ 0x00001038) Capture Destination Width Register                         */
22865 
22866         struct
22867         {
22868             __IOM uint32_t CHDW : 13;  /*!< [12..0] Specify the horizontal image size in the memory area
22869                                         *   where the captured image is to be stored (4-byte units).                  */
22870             uint32_t : 19;
22871         } CDWDR_B_b;
22872     };
22873 
22874     union
22875     {
22876         __IOM uint32_t CDAYR_B;        /*!< (@ 0x0000103C) Capture Data Address Y Register                            */
22877 
22878         struct
22879         {
22880             __IOM uint32_t CAYR : 32;  /*!< [31..0] Capture Data Address Y                                            */
22881         } CDAYR_B_b;
22882     };
22883 
22884     union
22885     {
22886         __IOM uint32_t CDACR_B;        /*!< (@ 0x00001040) Capture Data Address C Register                            */
22887 
22888         struct
22889         {
22890             __IOM uint32_t CACR : 32;  /*!< [31..0] Capture Data Address C                                            */
22891         } CDACR_B_b;
22892     };
22893 
22894     union
22895     {
22896         __IOM uint32_t CDBYR_B;        /*!< (@ 0x00001044) Capture Data Bottom-Field Address Y Register               */
22897 
22898         struct
22899         {
22900             __IOM uint32_t CBYR : 32;  /*!< [31..0] Set the address for storing the Y (luminance) component
22901                                         *   data of the captured bottom-field data (4-pixel units).                   */
22902         } CDBYR_B_b;
22903     };
22904 
22905     union
22906     {
22907         __IOM uint32_t CDBCR_B;        /*!< (@ 0x00001048) Capture Data Bottom-Field Address C Register               */
22908 
22909         struct
22910         {
22911             __IOM uint32_t CBCR : 32;  /*!< [31..0] Set the address for storing the C (chrominance) component
22912                                         *   data of the captured bottom-field data (4-pixel units).                   */
22913         } CDBCR_B_b;
22914     };
22915 
22916     union
22917     {
22918         __IOM uint32_t CBDSR_B;        /*!< (@ 0x0000104C) Capture Bundle Destination Size Register                   */
22919 
22920         struct
22921         {
22922             __IOM uint32_t CBVS : 23;  /*!< [22..0] Select the number of lines or number of bytes for output
22923                                         *   to the memory in a bundle write.                                          */
22924             uint32_t : 9;
22925         } CBDSR_B_b;
22926     };
22927     __IM uint32_t RESERVED8[4];
22928 
22929     union
22930     {
22931         __IOM uint32_t CLFCR_B;        /*!< (@ 0x00001060) Capture Low-Pass Filter Control Register                   */
22932 
22933         struct
22934         {
22935             __IOM uint32_t LPF : 1;    /*!< [0..0] Enables or disables operation of the low-pass filter.              */
22936             uint32_t           : 31;
22937         } CLFCR_B_b;
22938     };
22939 
22940     union
22941     {
22942         __IOM uint32_t CDOCR_B;        /*!< (@ 0x00001064) Capture Data Output Control Register                       */
22943 
22944         struct
22945         {
22946             __IOM uint32_t COBS : 1;   /*!< [0..0] Controls swapping in 8-bit units for data output from
22947                                         *   the CEU.                                                                  */
22948             __IOM uint32_t COWS : 1;   /*!< [1..1] Controls swapping in 16-bit units for data output from
22949                                         *   the CEU.                                                                  */
22950             __IOM uint32_t COLS : 1;   /*!< [2..2] Controls swapping in 32-bit units for data output from
22951                                         *   the CEU.                                                                  */
22952             uint32_t           : 1;
22953             __IOM uint32_t CDS : 1;    /*!< [4..4] Sets the image format when outputting the image data
22954                                         *   captured in the YCbCr422 format to the memory.                            */
22955             uint32_t           : 11;
22956             __IOM uint32_t CBE : 1;    /*!< [16..16] Controls the number of lines of captured data to be
22957                                         *   written to the memory.                                                    */
22958             uint32_t : 15;
22959         } CDOCR_B_b;
22960     };
22961     __IM uint32_t RESERVED9[10];
22962 
22963     union
22964     {
22965         __IOM uint32_t CDAYR2_B;       /*!< (@ 0x00001090) Capture Data Address Y Register 2                          */
22966 
22967         struct
22968         {
22969             __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y                                            */
22970         } CDAYR2_B_b;
22971     };
22972 
22973     union
22974     {
22975         __IOM uint32_t CDACR2_B;       /*!< (@ 0x00001094) Capture Data Address C Register 2                          */
22976 
22977         struct
22978         {
22979             __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2                                           */
22980         } CDACR2_B_b;
22981     };
22982 
22983     union
22984     {
22985         __IOM uint32_t CDBYR2_B;       /*!< (@ 0x00001098) Capture Data Bottom-Field Address Y Register
22986                                         *                  2                                                          */
22987 
22988         struct
22989         {
22990             __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of
22991                                         *   the captured bottom-field data (4-pixel units).                           */
22992         } CDBYR2_B_b;
22993     };
22994 
22995     union
22996     {
22997         __IOM uint32_t CDBCR2_B;       /*!< (@ 0x0000109C) Capture Data Bottom-Field Address C Register
22998                                         *                  2                                                          */
22999 
23000         struct
23001         {
23002             __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of
23003                                         *   the captured bottom-field data (4-pixel units).                           */
23004         } CDBCR2_B_b;
23005     };
23006     __IM uint32_t RESERVED10[988];
23007 
23008     union
23009     {
23010         __IOM uint32_t CAMOR_M;        /*!< (@ 0x00002010) Capture Interface Offset Register                          */
23011 
23012         struct
23013         {
23014             __IOM uint32_t HOFST : 13; /*!< [12..0] Specify the capture start location in terms of the number
23015                                         *   of clock cycles from a horizontal sync signal (1-cycle
23016                                         *   units).                                                                   */
23017             uint32_t             : 3;
23018             __IOM uint32_t VOFST : 12; /*!< [27..16] Specify the capture start location in terms of the
23019                                         *   HD count from a vertical sync signal (1-HD units).                        */
23020             uint32_t : 4;
23021         } CAMOR_M_b;
23022     };
23023 
23024     union
23025     {
23026         __IOM uint32_t CAPWR_M;        /*!< (@ 0x00002014) Capture Interface Width Register                           */
23027 
23028         struct
23029         {
23030             __IOM uint32_t HWDTH : 13; /*!< [12..0] Specify the horizontal capture period.                            */
23031             uint32_t             : 3;
23032             __IOM uint32_t VWDTH : 12; /*!< [27..16] Specify the vertical capture period (4-HD units).                */
23033             uint32_t             : 4;
23034         } CAPWR_M_b;
23035     };
23036     __IM uint32_t RESERVED11[6];
23037 
23038     union
23039     {
23040         __IOM uint32_t CFLCR_M;        /*!< (@ 0x00002030) Capture Filter Control Register                            */
23041 
23042         struct
23043         {
23044             __IOM uint32_t HFRAC : 12; /*!< [11..0] Fraction Part of Horizontal Scale-Down Factor                     */
23045             __IOM uint32_t HMANT : 4;  /*!< [15..12] Mantissa Part of Horizontal Scale-Down Factor                    */
23046             __IOM uint32_t VFRAC : 12; /*!< [27..16] Fraction Part of Vertical Scale-Down Factor                      */
23047             __IOM uint32_t VMANT : 4;  /*!< [31..28] Mantissa Part of Vertical Scale-Down Factor                      */
23048         } CFLCR_M_b;
23049     };
23050 
23051     union
23052     {
23053         __IOM uint32_t CFSZR_M;        /*!< (@ 0x00002034) Capture Filter Size Clip Register                          */
23054 
23055         struct
23056         {
23057             __IOM uint32_t HFCLP : 12; /*!< [11..0] Specify the horizontal clipping value of the filter
23058                                         *   output size (4-pixel units).                                              */
23059             uint32_t             : 4;
23060             __IOM uint32_t VFCLP : 12; /*!< [27..16] Set the vertical clipping value of the filter output
23061                                         *   size (4-pixel units).                                                     */
23062             uint32_t : 4;
23063         } CFSZR_M_b;
23064     };
23065 
23066     union
23067     {
23068         __IOM uint32_t CDWDR_M;        /*!< (@ 0x00002038) Capture Destination Width Register                         */
23069 
23070         struct
23071         {
23072             __IOM uint32_t CHDW : 13;  /*!< [12..0] Specify the horizontal image size in the memory area
23073                                         *   where the captured image is to be stored (4-byte units).                  */
23074             uint32_t : 19;
23075         } CDWDR_M_b;
23076     };
23077 
23078     union
23079     {
23080         __IOM uint32_t CDAYR_M;        /*!< (@ 0x0000203C) Capture Data Address Y Register                            */
23081 
23082         struct
23083         {
23084             __IOM uint32_t CAYR : 32;  /*!< [31..0] Capture Data Address Y                                            */
23085         } CDAYR_M_b;
23086     };
23087 
23088     union
23089     {
23090         __IOM uint32_t CDACR_M;        /*!< (@ 0x00002040) Capture Data Address C Register                            */
23091 
23092         struct
23093         {
23094             __IOM uint32_t CACR : 32;  /*!< [31..0] Capture Data Address C                                            */
23095         } CDACR_M_b;
23096     };
23097 
23098     union
23099     {
23100         __IOM uint32_t CDBYR_M;        /*!< (@ 0x00002044) Capture Data Bottom-Field Address Y Register               */
23101 
23102         struct
23103         {
23104             __IOM uint32_t CBYR : 32;  /*!< [31..0] Set the address for storing the Y (luminance) component
23105                                         *   data of the captured bottom-field data (4-pixel units).                   */
23106         } CDBYR_M_b;
23107     };
23108 
23109     union
23110     {
23111         __IOM uint32_t CDBCR_M;        /*!< (@ 0x00002048) Capture Data Bottom-Field Address C Register               */
23112 
23113         struct
23114         {
23115             __IOM uint32_t CBCR : 32;  /*!< [31..0] Set the address for storing the C (chrominance) component
23116                                         *   data of the captured bottom-field data (4-pixel units).                   */
23117         } CDBCR_M_b;
23118     };
23119 
23120     union
23121     {
23122         __IOM uint32_t CBDSR_M;        /*!< (@ 0x0000204C) Capture Bundle Destination Size Register                   */
23123 
23124         struct
23125         {
23126             __IOM uint32_t CBVS : 23;  /*!< [22..0] Select the number of lines or number of bytes for output
23127                                         *   to the memory in a bundle write.                                          */
23128             uint32_t : 9;
23129         } CBDSR_M_b;
23130     };
23131     __IM uint32_t RESERVED12[4];
23132 
23133     union
23134     {
23135         __IOM uint32_t CLFCR_M;        /*!< (@ 0x00002060) Capture Low-Pass Filter Control Register                   */
23136 
23137         struct
23138         {
23139             __IOM uint32_t LPF : 1;    /*!< [0..0] Enables or disables operation of the low-pass filter.              */
23140             uint32_t           : 31;
23141         } CLFCR_M_b;
23142     };
23143 
23144     union
23145     {
23146         __IOM uint32_t CDOCR_M;        /*!< (@ 0x00002064) Capture Data Output Control Register                       */
23147 
23148         struct
23149         {
23150             __IOM uint32_t COBS : 1;   /*!< [0..0] Controls swapping in 8-bit units for data output from
23151                                         *   the CEU.                                                                  */
23152             __IOM uint32_t COWS : 1;   /*!< [1..1] Controls swapping in 16-bit units for data output from
23153                                         *   the CEU.                                                                  */
23154             __IOM uint32_t COLS : 1;   /*!< [2..2] Controls swapping in 32-bit units for data output from
23155                                         *   the CEU.                                                                  */
23156             uint32_t           : 1;
23157             __IOM uint32_t CDS : 1;    /*!< [4..4] Sets the image format when outputting the image data
23158                                         *   captured in the YCbCr422 format to the memory.                            */
23159             uint32_t           : 11;
23160             __IOM uint32_t CBE : 1;    /*!< [16..16] Controls the number of lines of captured data to be
23161                                         *   written to the memory.                                                    */
23162             uint32_t : 15;
23163         } CDOCR_M_b;
23164     };
23165     __IM uint32_t RESERVED13[10];
23166 
23167     union
23168     {
23169         __IOM uint32_t CDAYR2_M;       /*!< (@ 0x00002090) Capture Data Address Y Register 2                          */
23170 
23171         struct
23172         {
23173             __IOM uint32_t CAYR2 : 32; /*!< [31..0] Capture Data Address Y                                            */
23174         } CDAYR2_M_b;
23175     };
23176 
23177     union
23178     {
23179         __IOM uint32_t CDACR2_M;       /*!< (@ 0x00002094) Capture Data Address C Register 2                          */
23180 
23181         struct
23182         {
23183             __IOM uint32_t CACR2 : 32; /*!< [31..0] Capture Data Address C2                                           */
23184         } CDACR2_M_b;
23185     };
23186 
23187     union
23188     {
23189         __IOM uint32_t CDBYR2_M;       /*!< (@ 0x00002098) Capture Data Bottom-Field Address Y Register
23190                                         *                  2                                                          */
23191 
23192         struct
23193         {
23194             __IOM uint32_t CBYR2 : 32; /*!< [31..0] Set the address for storing the Y component data of
23195                                         *   the captured bottom-field data (4-pixel units).                           */
23196         } CDBYR2_M_b;
23197     };
23198 
23199     union
23200     {
23201         __IOM uint32_t CDBCR2_M;       /*!< (@ 0x0000209C) Capture Data Bottom-Field Address C Register
23202                                         *                  2                                                          */
23203 
23204         struct
23205         {
23206             __IOM uint32_t CBCR2 : 32; /*!< [31..0] Set the address for storing the C component data of
23207                                         *   the captured bottom-field data (4-pixel units).                           */
23208         } CDBCR2_M_b;
23209     };
23210 } R_CEU_Type;                          /*!< Size = 8352 (0x20a0)                                                      */
23211 
23212 /* =========================================================================================================================== */
23213 /* ================                                          R_ULPT0                                          ================ */
23214 /* =========================================================================================================================== */
23215 
23216 /**
23217  * @brief Ultra-Low Power Timer 0 (R_ULPT0)
23218  */
23219 
23220 typedef struct                           /*!< (@ 0x40220000) R_ULPT0 Structure                                          */
23221 {
23222     union
23223     {
23224         __IOM uint32_t ULPTCNT;          /*!< (@ 0x00000000) ULPT Counter Register                                      */
23225 
23226         struct
23227         {
23228             __IOM uint32_t ULPTCNT : 32; /*!< [31..0] 32bit counter and reload registerNOTE : When 1 is written
23229                                           *   to the TSTOP bit in the ULPTCR register, the 32-bit counter
23230                                           *   is forcibly stopped and set to FFFFFFFFH.                                 */
23231         } ULPTCNT_b;
23232     };
23233 
23234     union
23235     {
23236         __IOM uint32_t ULPTCMA;          /*!< (@ 0x00000004) ULPT Compare Match A Register                              */
23237 
23238         struct
23239         {
23240             __IOM uint32_t ULPTCMA : 32; /*!< [31..0] ULPT Compare Match A RegisterNOTE : When 1 is written
23241                                           *   to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH                 */
23242         } ULPTCMA_b;
23243     };
23244 
23245     union
23246     {
23247         __IOM uint32_t ULPTCMB;          /*!< (@ 0x00000008) ULPT Compare Match B Register                              */
23248 
23249         struct
23250         {
23251             __IOM uint32_t ULPTCMB : 32; /*!< [31..0] AGT Compare Match B RegisterNOTE : When 1 is written
23252                                           *   to the TSTOP bit in the ULPTCR register, set to FFFFFFFFH                 */
23253         } ULPTCMB_b;
23254     };
23255 
23256     union
23257     {
23258         __IOM uint8_t ULPTCR;          /*!< (@ 0x0000000C) ULPT Control Register                                      */
23259 
23260         struct
23261         {
23262             __IOM uint8_t TSTART : 1;  /*!< [0..0] ULPT count start                                                   */
23263             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] ULPT count status flag                                             */
23264             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] ULPT count forced stop                                             */
23265             uint8_t              : 2;
23266             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] ULPT underflow flag                                                */
23267             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] ULPT compare match A flag                                          */
23268             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] ULPT compare match B flag                                          */
23269         } ULPTCR_b;
23270     };
23271 
23272     union
23273     {
23274         __IOM uint8_t ULPTMR1;         /*!< (@ 0x0000000D) ULPT Mode Register 1                                       */
23275 
23276         struct
23277         {
23278             uint8_t              : 1;
23279             __IOM uint8_t TMOD1  : 1;  /*!< [1..1] ULPT operating mode select                                         */
23280             uint8_t              : 1;
23281             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] ULPTEVI edge polarity select                                       */
23282             uint8_t              : 1;
23283             __IOM uint8_t TCK1   : 1;  /*!< [5..5] ULPT count source select                                           */
23284             uint8_t              : 2;
23285         } ULPTMR1_b;
23286     };
23287 
23288     union
23289     {
23290         __IOM uint8_t ULPTMR2;         /*!< (@ 0x0000000E) ULPT Mode Register 2                                       */
23291 
23292         struct
23293         {
23294             __IOM uint8_t CKS : 3;     /*!< [2..0] fsub/LOCO count source clock frequency division ratio
23295                                         *   select                                                                    */
23296             uint8_t           : 4;
23297             __IOM uint8_t LPM : 1;     /*!< [7..7] ULPT Low Power Mode                                                */
23298         } ULPTMR2_b;
23299     };
23300 
23301     union
23302     {
23303         __IOM uint8_t ULPTMR3;         /*!< (@ 0x0000000F) ULPT Mode Register 3                                       */
23304 
23305         struct
23306         {
23307             __IOM uint8_t TCNTCTL : 1; /*!< [0..0] ULPT count function select                                         */
23308             __IOM uint8_t TEVPOL  : 1; /*!< [1..1] ULPTEVI polarity switch                                            */
23309             __IOM uint8_t TOPOL   : 1; /*!< [2..2] ULPTO polarity select                                              */
23310             uint8_t               : 1;
23311             __IOM uint8_t TEECTL  : 2; /*!< [5..4] ULPTEE function select                                             */
23312             __IOM uint8_t TEEPOL  : 2; /*!< [7..6] ULPTEE edge polarity select                                        */
23313         } ULPTMR3_b;
23314     };
23315 
23316     union
23317     {
23318         __IOM uint8_t ULPTIOC;         /*!< (@ 0x00000010) ULPT I/O Control Register                                  */
23319 
23320         struct
23321         {
23322             uint8_t              : 2;
23323             __IOM uint8_t TOE    : 1;  /*!< [2..2] ULPTO output enable                                                */
23324             uint8_t              : 1;
23325             __IOM uint8_t TIPF   : 2;  /*!< [5..4] ULPTEVI input filter select                                        */
23326             __IOM uint8_t TIOGT0 : 1;  /*!< [6..6] ULPTEVI count control                                              */
23327             uint8_t              : 1;
23328         } ULPTIOC_b;
23329     };
23330 
23331     union
23332     {
23333         __IOM uint8_t ULPTISR;         /*!< (@ 0x00000011) ULPT Event Pin Select Register                             */
23334 
23335         struct
23336         {
23337             uint8_t                : 2;
23338             __IOM uint8_t RCCPSEL2 : 1; /*!< [2..2] ULPTEE polarty selection                                           */
23339             uint8_t                : 5;
23340         } ULPTISR_b;
23341     };
23342 
23343     union
23344     {
23345         __IOM uint8_t ULPTCMSR;        /*!< (@ 0x00000012) ULPT Compare Match Function Select Register                */
23346 
23347         struct
23348         {
23349             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
23350             __IOM uint8_t TOEA   : 1;  /*!< [1..1] ULPTOA output enable                                               */
23351             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] ULPTOA polarity select                                             */
23352             uint8_t              : 1;
23353             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
23354             __IOM uint8_t TOEB   : 1;  /*!< [5..5] ULPTOB output enable                                               */
23355             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] ULPTOB polarity select                                             */
23356             uint8_t              : 1;
23357         } ULPTCMSR_b;
23358     };
23359     __IM uint8_t RESERVED;
23360 } R_ULPT0_Type;                        /*!< Size = 20 (0x14)                                                          */
23361 
23362 /* =========================================================================================================================== */
23363 /* ================                                        R_DEBUG_OCD                                        ================ */
23364 /* =========================================================================================================================== */
23365 
23366 /**
23367  * @brief On-Chip Debug Function (R_DEBUG_OCD)
23368  */
23369 
23370 typedef struct                         /*!< (@ 0x40011000) R_DEBUG_OCD Structure                                      */
23371 {
23372     __IM uint32_t RESERVED[192];
23373 
23374     union
23375     {
23376         __IM uint32_t FSBLSTATM;       /*!< (@ 0x00000300) First Stage Boot Loader Status Monitor Register            */
23377 
23378         struct
23379         {
23380             __IM uint32_t CS : 1;      /*!< [0..0] FSBL completion status.                                            */
23381             __IM uint32_t RS : 1;      /*!< [1..1] FSBL result status.                                                */
23382             uint32_t         : 30;
23383         } FSBLSTATM_b;
23384     };
23385 } R_DEBUG_OCD_Type;                    /*!< Size = 772 (0x304)                                                        */
23386 
23387 /* =========================================================================================================================== */
23388 /* ================                                          R_DOTF                                           ================ */
23389 /* =========================================================================================================================== */
23390 
23391 /**
23392  * @brief Decryption On The Fly (R_DOTF)
23393  */
23394 
23395 typedef struct                         /*!< (@ 0x40268800) R_DOTF Structure                                           */
23396 {
23397     union
23398     {
23399         __IOM uint32_t CONVAREAST;     /*!< (@ 0x00000000) DOTF Conversion Area Start Address Register                */
23400 
23401         struct
23402         {
23403             uint32_t                  : 12;
23404             __IOM uint32_t CONVAREAST : 20; /*!< [31..12] First address of decryption processing area                      */
23405         } CONVAREAST_b;
23406     };
23407 
23408     union
23409     {
23410         __IOM uint32_t CONVAREAD;      /*!< (@ 0x00000004) DOTF Conversion Area End Address Register                  */
23411 
23412         struct
23413         {
23414             uint32_t                 : 12;
23415             __IOM uint32_t CONVAREAD : 20; /*!< [31..12] End address of decryption processing area                        */
23416         } CONVAREAD_b;
23417     };
23418     __IM uint32_t RESERVED[30];
23419 
23420     union
23421     {
23422         __IOM uint32_t REG00;          /*!< (@ 0x00000080) Register 0                                                 */
23423 
23424         struct
23425         {
23426             uint32_t           : 9;
23427             __IOM uint32_t B09 : 1;    /*!< [9..9] Bit 09                                                             */
23428             uint32_t           : 6;
23429             __IOM uint32_t B16 : 1;    /*!< [16..16] Bit 09                                                           */
23430             __IOM uint32_t B17 : 1;    /*!< [17..17] Bit 17                                                           */
23431             uint32_t           : 2;
23432             __IOM uint32_t B20 : 1;    /*!< [20..20] Bit 20                                                           */
23433             uint32_t           : 3;
23434             __IOM uint32_t B24 : 2;    /*!< [25..24] Bit24-25                                                         */
23435             uint32_t           : 2;
23436             __IOM uint32_t B28 : 2;    /*!< [29..28] Bit28-29                                                         */
23437             uint32_t           : 2;
23438         } REG00_b;
23439     };
23440     __IM uint32_t RESERVED1[2];
23441 
23442     union
23443     {
23444         __IOM uint32_t REG03;          /*!< (@ 0x0000008C) Register 03                                                */
23445 
23446         struct
23447         {
23448             __IOM uint32_t B00 : 32;   /*!< [31..0] Bit 0                                                             */
23449         } REG03_b;
23450     };
23451 } R_DOTF_Type;                         /*!< Size = 144 (0x90)                                                         */
23452 
23453 /* =========================================================================================================================== */
23454 /* ================                                          R_AGTX0                                          ================ */
23455 /* =========================================================================================================================== */
23456 
23457 /**
23458  * @brief Asynchronous General Purpose Timer (R_AGTX0)
23459  */
23460 
23461 typedef struct                          /*!< (@ 0x40221000) R_AGTX0 Structure                                          */
23462 {
23463     union
23464     {
23465         __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
23466         __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
23467     };
23468 } R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
23469 
23470 /* =========================================================================================================================== */
23471 /* ================                                         R_DPHYCNT                                         ================ */
23472 /* =========================================================================================================================== */
23473 
23474 /**
23475  * @brief D-PHY Controller Top (R_DPHYCNT)
23476  */
23477 
23478 typedef struct                         /*!< (@ 0x40346C00) R_DPHYCNT Structure                                        */
23479 {
23480     union
23481     {
23482         __IOM uint32_t DPHYREFCR;      /*!< (@ 0x00000000) D-PHY Reference Clock Setting Register                     */
23483 
23484         struct
23485         {
23486             __IOM uint32_t RFREQ : 8;  /*!< [7..0] Reference Clock Frequency Setting                                  */
23487             uint32_t             : 24;
23488         } DPHYREFCR_b;
23489     };
23490 
23491     union
23492     {
23493         __IOM uint32_t DPHYPLFCR;      /*!< (@ 0x00000004) D-PHY PLL Frequency Control Register                       */
23494 
23495         struct
23496         {
23497             __IOM uint32_t IDIV  : 2;  /*!< [1..0] D-PHY PLL Input Frequency Division Ratio Select                    */
23498             uint32_t             : 6;
23499             __IOM uint32_t NFMUL : 2;  /*!< [9..8] D-PHY PLL Frequency Multiplication Factor Select (Fractional
23500                                         *   Part)                                                                     */
23501             uint32_t            : 6;
23502             __IOM uint32_t NMUL : 8;   /*!< [23..16] D-PHY PLL Frequency Multiplication Factor Select (Integer
23503                                         *   Part)                                                                     */
23504             uint32_t : 8;
23505         } DPHYPLFCR_b;
23506     };
23507 
23508     union
23509     {
23510         __IOM uint32_t DPHYPLOCR;      /*!< (@ 0x00000008) D-PHY PLL Operation Control Register                       */
23511 
23512         struct
23513         {
23514             __IOM uint32_t PLLSTP : 1; /*!< [0..0] D-PHY PLL Operation Control                                        */
23515             uint32_t              : 31;
23516         } DPHYPLOCR_b;
23517     };
23518 
23519     union
23520     {
23521         __IOM uint32_t DPHYESCCR;      /*!< (@ 0x0000000C) D-PHY Escape Mode Clock Control Register                   */
23522 
23523         struct
23524         {
23525             __IOM uint32_t ESCDIV : 5; /*!< [4..0] Escape Mode Transfer Clock Division Ratio                          */
23526             uint32_t              : 27;
23527         } DPHYESCCR_b;
23528     };
23529 
23530     union
23531     {
23532         __IOM uint32_t DPHYPWRCR;      /*!< (@ 0x00000010) D-PHY Power Supplying Control Register                     */
23533 
23534         struct
23535         {
23536             __IOM uint32_t PWRSEN : 1; /*!< [0..0] D-PHY Power Supplying Control                                      */
23537             uint32_t              : 31;
23538         } DPHYPWRCR_b;
23539     };
23540     __IM uint32_t RESERVED[2];
23541 
23542     union
23543     {
23544         __IM uint32_t DPHYSFR;         /*!< (@ 0x0000001C) D-PHY Status Flag Register                                 */
23545 
23546         struct
23547         {
23548             __IM uint32_t PWRSF : 1;   /*!< [0..0] D-PHY LDO Power-on Status Flag                                     */
23549             uint32_t            : 7;
23550             __IM uint32_t PLLSF : 1;   /*!< [8..8] D-PHY PLL Oscillation Stabilization Flag                           */
23551             uint32_t            : 23;
23552         } DPHYSFR_b;
23553     };
23554 
23555     union
23556     {
23557         __IOM uint32_t DPHYOCR;        /*!< (@ 0x00000020) D-PHY Operation Control Register                           */
23558 
23559         struct
23560         {
23561             __IOM uint32_t DPHYEN : 1; /*!< [0..0] D-PHY Operation Control                                            */
23562             uint32_t              : 31;
23563         } DPHYOCR_b;
23564     };
23565 
23566     union
23567     {
23568         __IOM uint32_t DPHYTIM1;       /*!< (@ 0x00000024) D-PHY Timing Control Register 1                            */
23569 
23570         struct
23571         {
23572             __IOM uint32_t TINIT : 19; /*!< [18..0] D-PHY T_INIT Parameter Setting                                    */
23573             uint32_t             : 13;
23574         } DPHYTIM1_b;
23575     };
23576 
23577     union
23578     {
23579         __IOM uint32_t DPHYTIM2;         /*!< (@ 0x00000028) D-PHY Timing Control Register 2                            */
23580 
23581         struct
23582         {
23583             __IOM uint32_t TCLKPREP : 8; /*!< [7..0] D-PHY T_CLK_PREPARE Parameter Setting                              */
23584             uint32_t                : 24;
23585         } DPHYTIM2_b;
23586     };
23587 
23588     union
23589     {
23590         __IOM uint32_t DPHYTIM3;        /*!< (@ 0x0000002C) D-PHY Timing Control Register 3                            */
23591 
23592         struct
23593         {
23594             __IOM uint32_t THSPREP : 8; /*!< [7..0] D-PHY T_THS_PREPARE Parameter Setting                              */
23595             uint32_t               : 24;
23596         } DPHYTIM3_b;
23597     };
23598 
23599     union
23600     {
23601         __IOM uint32_t DPHYTIM4;         /*!< (@ 0x00000030) D-PHY Timing Control Register 4                            */
23602 
23603         struct
23604         {
23605             __IOM uint32_t TCLKZERO : 8; /*!< [7..0] D-PHY T_CLK_ZERO Parameter Setting                                 */
23606             __IOM uint32_t TCLKPRE  : 8; /*!< [15..8] D-PHY T_TCLK_PRE Parameter Setting                                */
23607             __IOM uint32_t TCLKPOST : 8; /*!< [23..16] D-PHY T_TCLK_POST Parameter Setting                              */
23608             __IOM uint32_t TCLKTRL  : 8; /*!< [31..24] D-PHY T_TCLK_TRAIL Parameter Setting                             */
23609         } DPHYTIM4_b;
23610     };
23611 
23612     union
23613     {
23614         __IOM uint32_t DPHYTIM5;        /*!< (@ 0x00000034) D-PHY Timing Control Register 5                            */
23615 
23616         struct
23617         {
23618             __IOM uint32_t THSZERO : 8; /*!< [7..0] D-PHY T_THS_ZERO Parameter Setting                                 */
23619             __IOM uint32_t THSTRL  : 8; /*!< [15..8] D-PHY T_THS_TRAIL Parameter Setting                               */
23620             __IOM uint32_t THSEXIT : 8; /*!< [23..16] D-PHY T_THS_EXIT Parameter Setting                               */
23621             uint32_t               : 8;
23622         } DPHYTIM5_b;
23623     };
23624 
23625     union
23626     {
23627         __IOM uint32_t DPHYTIM6;       /*!< (@ 0x00000038) D-PHY Timing Control Register 6                            */
23628 
23629         struct
23630         {
23631             __IOM uint32_t TLPX : 8;   /*!< [7..0] D-PHY T_TLPX Parameter Setting                                     */
23632             uint32_t            : 24;
23633         } DPHYTIM6_b;
23634     };
23635 } R_DPHYCNT_Type;                      /*!< Size = 60 (0x3c)                                                          */
23636 
23637 /* =========================================================================================================================== */
23638 /* ================                                         R_DSILINK                                         ================ */
23639 /* =========================================================================================================================== */
23640 
23641 /**
23642  * @brief DSI Link (R_DSILINK)
23643  */
23644 
23645 typedef struct                         /*!< (@ 0x40346000) R_DSILINK Structure                                        */
23646 {
23647     union
23648     {
23649         __IM uint32_t ISR;             /*!< (@ 0x00000000) Interrupt Status Register                                  */
23650 
23651         struct
23652         {
23653             __IM uint32_t SQ0  : 1;    /*!< [0..0] Sequence Channel-0 Interrupt Flag                                  */
23654             uint32_t           : 3;
23655             __IM uint32_t SQ1  : 1;    /*!< [4..4] Sequence Channel-1 Interrupt Flag                                  */
23656             uint32_t           : 3;
23657             __IM uint32_t VM   : 1;    /*!< [8..8] Video Mode Interrupt Flag                                          */
23658             uint32_t           : 3;
23659             __IM uint32_t RCV  : 1;    /*!< [12..12] Receive Interrupt Flag                                           */
23660             uint32_t           : 3;
23661             __IM uint32_t FERR : 1;    /*!< [16..16] Fatal Error Interrupt Flag                                       */
23662             uint32_t           : 3;
23663             __IM uint32_t PPI  : 1;    /*!< [20..20] PPI Interrupt Flag                                               */
23664             uint32_t           : 11;
23665         } ISR_b;
23666     };
23667     __IM uint32_t RESERVED[3];
23668 
23669     union
23670     {
23671         __IM uint32_t LINKSR;          /*!< (@ 0x00000010) Link Status Register                                       */
23672 
23673         struct
23674         {
23675             __IM uint32_t SQ0RUN : 1;  /*!< [0..0] Sequence Channel-0 Running Flag                                    */
23676             uint32_t             : 3;
23677             __IM uint32_t SQ1RUN : 1;  /*!< [4..4] Sequence Channel-1 Running Flag                                    */
23678             uint32_t             : 3;
23679             __IM uint32_t VRUN   : 1;  /*!< [8..8] Video Mode Operation Running Flag                                  */
23680             uint32_t             : 3;
23681             __IM uint32_t HSBUSY : 1;  /*!< [12..12] HS Operation Busy Flag                                           */
23682             __IM uint32_t LPBUSY : 1;  /*!< [13..13] LP Operation Busy Flag                                           */
23683             uint32_t             : 18;
23684         } LINKSR_b;
23685     };
23686     __IM uint32_t RESERVED1[59];
23687 
23688     union
23689     {
23690         __IOM uint32_t TXSETR;          /*!< (@ 0x00000100) Transmit Set Register                                      */
23691 
23692         struct
23693         {
23694             __IOM uint32_t NUMLANE : 2; /*!< [1..0] Number of Lane                                                     */
23695             uint32_t               : 6;
23696             __IOM uint32_t CLEN    : 1; /*!< [8..8] Clock Lane Enable                                                  */
23697             __IOM uint32_t DLEN    : 1; /*!< [9..9] Data Lane Enable                                                   */
23698             uint32_t               : 22;
23699         } TXSETR_b;
23700     };
23701 
23702     union
23703     {
23704         __IOM uint32_t HSCLKSETR;      /*!< (@ 0x00000104) HS Clock Set Register                                      */
23705 
23706         struct
23707         {
23708             __IOM uint32_t HSCLST : 1; /*!< [0..0] HS Clock Start                                                     */
23709             __IOM uint32_t HSCLMD : 1; /*!< [1..1] HS Clock Running Mode                                              */
23710             uint32_t              : 30;
23711         } HSCLKSETR_b;
23712     };
23713 
23714     union
23715     {
23716         __IOM uint32_t ULPSSETR;       /*!< (@ 0x00000108) ULPS Set Register                                          */
23717 
23718         struct
23719         {
23720             __IOM uint32_t WKUP : 8;   /*!< [7..0] ULPS Wakeup Period                                                 */
23721             uint32_t            : 24;
23722         } ULPSSETR_b;
23723     };
23724 
23725     union
23726     {
23727         __OM uint32_t ULPSCR;          /*!< (@ 0x0000010C) ULPS Control Register                                      */
23728 
23729         struct
23730         {
23731             uint32_t             : 24;
23732             __OM uint32_t CLENT  : 1;  /*!< [24..24] CL ULPS Enter                                                    */
23733             __OM uint32_t CLEXIT : 1;  /*!< [25..25] CL ULPS Exit                                                     */
23734             uint32_t             : 2;
23735             __OM uint32_t DLENT  : 1;  /*!< [28..28] DL ULPS Enter                                                    */
23736             __OM uint32_t DLEXIT : 1;  /*!< [29..29] DL ULPS Exit                                                     */
23737             uint32_t             : 2;
23738         } ULPSCR_b;
23739     };
23740 
23741     union
23742     {
23743         __IOM uint32_t RSTCR;          /*!< (@ 0x00000110) Reset Control Register                                     */
23744 
23745         struct
23746         {
23747             __IOM uint32_t SWRST  : 1; /*!< [0..0] Software Reset                                                     */
23748             uint32_t              : 15;
23749             __IOM uint32_t FTXSTP : 1; /*!< [16..16] Force Tx Stop Mode                                               */
23750             uint32_t              : 15;
23751         } RSTCR_b;
23752     };
23753 
23754     union
23755     {
23756         __IM uint32_t RSTSR;           /*!< (@ 0x00000114) Reset Status Register                                      */
23757 
23758         struct
23759         {
23760             __IM uint32_t RSTHS  : 1;  /*!< [0..0] HS Software Reset Status                                           */
23761             __IM uint32_t RSTLP  : 1;  /*!< [1..1] LP Software Reset Status                                           */
23762             __IM uint32_t RSTAPB : 1;  /*!< [2..2] APB Software Reset Status                                          */
23763             __IM uint32_t RSTAXI : 1;  /*!< [3..3] AXI Software Reset Status                                          */
23764             __IM uint32_t RSTV   : 1;  /*!< [4..4] Video Software Reset Status                                        */
23765             uint32_t             : 3;
23766             __IM uint32_t DL0STP : 1;  /*!< [8..8] Data Lane-0 Stop Status                                            */
23767             __IM uint32_t DL1STP : 1;  /*!< [9..9] Data Lane-1 Stop Status                                            */
23768             uint32_t             : 5;
23769             __IM uint32_t DL0DIR : 1;  /*!< [15..15] Data Lane-0 Direction                                            */
23770             uint32_t             : 16;
23771         } RSTSR_b;
23772     };
23773     __IM uint32_t RESERVED2[2];
23774 
23775     union
23776     {
23777         __IOM uint32_t DSISETR;           /*!< (@ 0x00000120) DSI Set Register                                           */
23778 
23779         struct
23780         {
23781             __IOM uint32_t MRPSZ    : 16; /*!< [15..0] Maximum Return Packet Size                                        */
23782             __IOM uint32_t ECCEN    : 1;  /*!< [16..16] ECC Check Enable                                                 */
23783             uint32_t                : 3;
23784             __IOM uint32_t VC0CRCEN : 1;  /*!< [20..20] VC-0 CRC Check Enable                                            */
23785             __IOM uint32_t VC1CRCEN : 1;  /*!< [21..21] VC-1 CRC Check Enable                                            */
23786             __IOM uint32_t VC2CRCEN : 1;  /*!< [22..22] VC-2 CRC Check Enable                                            */
23787             __IOM uint32_t VC3CRCEN : 1;  /*!< [23..23] VC-3 CRC Check Enable                                            */
23788             uint32_t                : 5;
23789             __IOM uint32_t SCREN    : 1;  /*!< [29..29] Data Scramble Enable                                             */
23790             __IOM uint32_t EXTEMD   : 1;  /*!< [30..30] External Tearing Effect Detection Sense Select                   */
23791             __IOM uint32_t EOTPEN   : 1;  /*!< [31..31] HS Transfer EoTp Enable                                          */
23792         } DSISETR_b;
23793     };
23794     __IM uint32_t RESERVED3[15];
23795 
23796     union
23797     {
23798         __IOM uint32_t TXPPD0R;        /*!< (@ 0x00000160) Transmit Packet Payload Data 0 Register                    */
23799 
23800         struct
23801         {
23802             __IOM uint32_t DATA0 : 8;  /*!< [7..0] Payload Data 0                                                     */
23803             __IOM uint32_t DATA1 : 8;  /*!< [15..8] Payload Data 1                                                    */
23804             __IOM uint32_t DATA2 : 8;  /*!< [23..16] Payload Data 2                                                   */
23805             __IOM uint32_t DATA3 : 8;  /*!< [31..24] Payload Data 3                                                   */
23806         } TXPPD0R_b;
23807     };
23808 
23809     union
23810     {
23811         __IOM uint32_t TXPPD1R;        /*!< (@ 0x00000164) Transmit Packet Payload Data 1 Register                    */
23812 
23813         struct
23814         {
23815             __IOM uint32_t DATA4 : 8;  /*!< [7..0] Payload Data 4                                                     */
23816             __IOM uint32_t DATA5 : 8;  /*!< [15..8] Payload Data 5                                                    */
23817             __IOM uint32_t DATA6 : 8;  /*!< [23..16] Payload Data 6                                                   */
23818             __IOM uint32_t DATA7 : 8;  /*!< [31..24] Payload Data 7                                                   */
23819         } TXPPD1R_b;
23820     };
23821 
23822     union
23823     {
23824         __IOM uint32_t TXPPD2R;        /*!< (@ 0x00000168) Transmit Packet Payload Data 2 Register                    */
23825 
23826         struct
23827         {
23828             __IOM uint32_t DATA8  : 8; /*!< [7..0] Payload Data 8                                                     */
23829             __IOM uint32_t DATA9  : 8; /*!< [15..8] Payload Data 9                                                    */
23830             __IOM uint32_t DATA10 : 8; /*!< [23..16] Payload Data 10                                                  */
23831             __IOM uint32_t DATA11 : 8; /*!< [31..24] Payload Data 11                                                  */
23832         } TXPPD2R_b;
23833     };
23834 
23835     union
23836     {
23837         __IOM uint32_t TXPPD3R;        /*!< (@ 0x0000016C) Transmit Packet Payload Data 3 Register                    */
23838 
23839         struct
23840         {
23841             __IOM uint32_t DATA12 : 8; /*!< [7..0] Payload Data 12                                                    */
23842             __IOM uint32_t DATA13 : 8; /*!< [15..8] Payload Data 13                                                   */
23843             __IOM uint32_t DATA14 : 8; /*!< [23..16] Payload Data 14                                                  */
23844             __IOM uint32_t DATA15 : 8; /*!< [31..24] Payload Data 15                                                  */
23845         } TXPPD3R_b;
23846     };
23847     __IM uint32_t RESERVED4[36];
23848 
23849     union
23850     {
23851         __IM uint32_t RXSR;             /*!< (@ 0x00000200) Receive Status Register                                    */
23852 
23853         struct
23854         {
23855             __IM uint32_t BTAREND  : 1; /*!< [0..0] BTA Request End Interrupt Flag                                     */
23856             __IM uint32_t LRXHTO   : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag                        */
23857             __IM uint32_t TATO     : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag                      */
23858             uint32_t               : 5;
23859             __IM uint32_t RXRESP   : 1; /*!< [8..8] Response Packet Receive Interrupt Flag                             */
23860             uint32_t               : 1;
23861             __IM uint32_t RXEOTP   : 1; /*!< [10..10] EoTp Receive Interrupt Flag                                      */
23862             uint32_t               : 2;
23863             __IM uint32_t RXTE     : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag                    */
23864             __IM uint32_t RXACK    : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag                               */
23865             __IM uint32_t EXTEDET  : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag                    */
23866             __IM uint32_t MLFERR   : 1; /*!< [16..16] Malform Error Interrupt Flag                                     */
23867             __IM uint32_t ECCERRM  : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag                               */
23868             __IM uint32_t UNEXERR  : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag                           */
23869             uint32_t               : 1;
23870             __IM uint32_t WCERR    : 1; /*!< [20..20] Word Count Error Interrupt Flag                                  */
23871             __IM uint32_t CRCERR   : 1; /*!< [21..21] CRC Error Interrupt Flag                                         */
23872             __IM uint32_t IBERR    : 1; /*!< [22..22] Internal Bus Error Interrupt Flag                                */
23873             __IM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag                     */
23874             __IM uint32_t PRTOERR  : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag                 */
23875             __IM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag                                 */
23876             __IM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag                          */
23877             uint32_t               : 1;
23878             __IM uint32_t ECCERRS  : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag                              */
23879             uint32_t               : 1;
23880             __IM uint32_t RXAKE    : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag              */
23881             uint32_t               : 1;
23882         } RXSR_b;
23883     };
23884 
23885     union
23886     {
23887         __IOM uint32_t RXSCR;            /*!< (@ 0x00000204) Receive Status Clear Register                              */
23888 
23889         struct
23890         {
23891             __IOM uint32_t BTAREND  : 1; /*!< [0..0] BTA Request End Interrupt Flag Clear                               */
23892             __IOM uint32_t LRXHTO   : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear                  */
23893             __IOM uint32_t TATO     : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear                */
23894             uint32_t                : 5;
23895             __IOM uint32_t RXRESP   : 1; /*!< [8..8] Response Packet Receive Interrupt Flag Clear                       */
23896             uint32_t                : 1;
23897             __IOM uint32_t RXEOTP   : 1; /*!< [10..10] EoTp Receive Interrupt Flag Clear                                */
23898             uint32_t                : 2;
23899             __IOM uint32_t RXTE     : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Flag Clear              */
23900             __IOM uint32_t RXACK    : 1; /*!< [14..14] ACK Trigger Receive Interrupt Flag Clear                         */
23901             __IOM uint32_t EXTEDET  : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Flag Clear              */
23902             __IOM uint32_t MLFERR   : 1; /*!< [16..16] Malform Error Interrupt Flag Clear                               */
23903             __IOM uint32_t ECCERRM  : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Flag Clear                         */
23904             __IOM uint32_t UNEXERR  : 1; /*!< [18..18] Unexpected Packet Error Interrupt Flag Clear                     */
23905             uint32_t                : 1;
23906             __IOM uint32_t WCERR    : 1; /*!< [20..20] Word Count Error Interrupt Flag Clear                            */
23907             __IOM uint32_t CRCERR   : 1; /*!< [21..21] CRC Error Interrupt Flag Clear                                   */
23908             __IOM uint32_t IBERR    : 1; /*!< [22..22] Internal Bus Error Interrupt Flag Clear                          */
23909             __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Flag Clear               */
23910             __IOM uint32_t PRTOERR  : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Flag Clear           */
23911             __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Flag Clear                           */
23912             __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Flag Clear                    */
23913             uint32_t                : 1;
23914             __IOM uint32_t ECCERRS  : 1; /*!< [28..28] Single Bit ECC Error Interrupt Flag Clear                        */
23915             uint32_t                : 1;
23916             __IOM uint32_t RXAKE    : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Flag
23917                                           *   Clear                                                                     */
23918             uint32_t : 1;
23919         } RXSCR_b;
23920     };
23921 
23922     union
23923     {
23924         __IOM uint32_t RXIER;            /*!< (@ 0x00000208) Receive Interrupt Enable Register                          */
23925 
23926         struct
23927         {
23928             __IOM uint32_t BTAREND  : 1; /*!< [0..0] BTA Request End Interrupt Enable                                   */
23929             __IOM uint32_t LRXHTO   : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable                      */
23930             __IOM uint32_t TATO     : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable                    */
23931             uint32_t                : 5;
23932             __IOM uint32_t RXRESP   : 1; /*!< [8..8] Response Packet Receive Interrupt Enable                           */
23933             uint32_t                : 1;
23934             __IOM uint32_t RXEOTP   : 1; /*!< [10..10] EoTp Receive Interrupt Enable                                    */
23935             uint32_t                : 2;
23936             __IOM uint32_t RXTE     : 1; /*!< [13..13] Tearing Effect Trigger Receive Interrupt Enable                  */
23937             __IOM uint32_t RXACK    : 1; /*!< [14..14] ACK Trigger Receive Interrupt Enable                             */
23938             __IOM uint32_t EXTEDET  : 1; /*!< [15..15] External Tearing Effect Detect Interrupt Enable                  */
23939             __IOM uint32_t MLFERR   : 1; /*!< [16..16] Malform Error Interrupt Enable                                   */
23940             __IOM uint32_t ECCERRM  : 1; /*!< [17..17] Multi Bit ECC Error Interrupt Enable                             */
23941             __IOM uint32_t UNEXERR  : 1; /*!< [18..18] Unexpected Packet Error Interrupt Enable                         */
23942             uint32_t                : 1;
23943             __IOM uint32_t WCERR    : 1; /*!< [20..20] Word Count Error Interrupt Enable                                */
23944             __IOM uint32_t CRCERR   : 1; /*!< [21..21] CRC Error Interrupt Enable                                       */
23945             __IOM uint32_t IBERR    : 1; /*!< [22..22] Internal Bus Error Interrupt Enable                              */
23946             __IOM uint32_t RXOVFERR : 1; /*!< [23..23] Receive Buffer Overflow Error Interrupt Enable                   */
23947             __IOM uint32_t PRTOERR  : 1; /*!< [24..24] Peripheral Response Timeout Error Interrupt Enable               */
23948             __IOM uint32_t NORESERR : 1; /*!< [25..25] No Response Error Interrupt Enable                               */
23949             __IOM uint32_t RSIZEERR : 1; /*!< [26..26] Return Packet Size Error Interrupt Enable                        */
23950             uint32_t                : 1;
23951             __IOM uint32_t ECCERRS  : 1; /*!< [28..28] Single Bit ECC Error Interrupt Enable                            */
23952             uint32_t                : 1;
23953             __IOM uint32_t RXAKE    : 1; /*!< [30..30] Acknowledge and Error Report Receive Interrupt Enable            */
23954             uint32_t                : 1;
23955         } RXIER_b;
23956     };
23957     __IM uint32_t RESERVED5;
23958 
23959     union
23960     {
23961         __IOM uint32_t PRESPTOBTASETR;  /*!< (@ 0x00000210) Peripheral Response Timeout BTA Set Register               */
23962 
23963         struct
23964         {
23965             __IOM uint32_t PRTBTA : 32; /*!< [31..0] Peripheral Response Timeout Count                                 */
23966         } PRESPTOBTASETR_b;
23967     };
23968 
23969     union
23970     {
23971         __IOM uint32_t PRESPTOLPSETR;  /*!< (@ 0x00000214) Peripheral Response Timeout LP Set Register                */
23972 
23973         struct
23974         {
23975             __IOM uint32_t LPWTO : 16; /*!< [15..0] LPDT WRITE Request Timeout                                        */
23976             __IOM uint32_t LPRTO : 16; /*!< [31..16] LPDT READ Request Timeout                                        */
23977         } PRESPTOLPSETR_b;
23978     };
23979 
23980     union
23981     {
23982         __IOM uint32_t PRESPTOHSSETR;  /*!< (@ 0x00000218) Peripheral Response Timeout HS Set Register                */
23983 
23984         struct
23985         {
23986             __IOM uint32_t HSWTO : 16; /*!< [15..0] HS WRITE Request Timeout                                          */
23987             __IOM uint32_t HSRTO : 16; /*!< [31..16] HS READ Request Timeout                                          */
23988         } PRESPTOHSSETR_b;
23989     };
23990     __IM uint32_t RESERVED6;
23991 
23992     union
23993     {
23994         __IM uint32_t AKEPLATIR;       /*!< (@ 0x00000220) Acknowledge and Error Report Packet Parameter
23995                                         *                  Latest Info Register                                       */
23996 
23997         struct
23998         {
23999             __IM uint32_t EREP : 16;   /*!< [15..0] Error Report                                                      */
24000             __IM uint32_t VC   : 4;    /*!< [19..16] Virtual Channel ID                                               */
24001             uint32_t           : 12;
24002         } AKEPLATIR_b;
24003     };
24004 
24005     union
24006     {
24007         __IM uint32_t AKEPACMSR;       /*!< (@ 0x00000224) Acknowledge and Error Report Packet Parameter
24008                                         *                  Accumulate Status Register                                 */
24009 
24010         struct
24011         {
24012             __IM uint32_t AEREP : 16;  /*!< [15..0] Accumulated Error Report                                          */
24013             __IM uint32_t AVC   : 4;   /*!< [19..16] Virtual Channel ID                                               */
24014             uint32_t            : 12;
24015         } AKEPACMSR_b;
24016     };
24017 
24018     union
24019     {
24020         __IOM uint32_t AKEPSCR;        /*!< (@ 0x00000228) Acknowledge and Error Report Packet Parameter
24021                                         *                  Status Clear Register                                      */
24022 
24023         struct
24024         {
24025             __IOM uint32_t AEREP : 16; /*!< [15..0] Accumulated Error Report Clear                                    */
24026             __IM uint32_t  AVC   : 4;  /*!< [19..16] Virtual Channel ID                                               */
24027             uint32_t             : 12;
24028         } AKEPSCR_b;
24029     };
24030     __IM uint32_t RESERVED7;
24031 
24032     union
24033     {
24034         __IM uint32_t RXRSSR;          /*!< (@ 0x00000230) Receive Result Saved Status Register                       */
24035 
24036         struct
24037         {
24038             __IM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag                                                  */
24039             __IM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag                                                  */
24040             __IM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag                                                  */
24041             __IM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag                                                  */
24042             uint32_t              : 28;
24043         } RXRSSR_b;
24044     };
24045 
24046     union
24047     {
24048         __IOM uint32_t RXRSSCR;         /*!< (@ 0x00000234) Receive Result Saved Status Clear Register                 */
24049 
24050         struct
24051         {
24052             __IOM uint32_t SLT0VLD : 1; /*!< [0..0] Slot-0 Valid Flag Clear                                            */
24053             __IOM uint32_t SLT1VLD : 1; /*!< [1..1] Slot-1 Valid Flag Clear                                            */
24054             __IOM uint32_t SLT2VLD : 1; /*!< [2..2] Slot-2 Valid Flag Clear                                            */
24055             __IOM uint32_t SLT3VLD : 1; /*!< [3..3] Slot-3 Valid Flag Clear                                            */
24056             uint32_t               : 28;
24057         } RXRSSCR_b;
24058     };
24059 
24060     union
24061     {
24062         __IM uint32_t RXRINFOOWSR;     /*!< (@ 0x00000238) Receive Result Info Overwrite Status Register              */
24063 
24064         struct
24065         {
24066             __IM uint32_t SL0OW : 1;   /*!< [0..0] Slot-0 Information Overwrite Flag                                  */
24067             __IM uint32_t SL1OW : 1;   /*!< [1..1] Slot-1 Information Overwrite Flag                                  */
24068             __IM uint32_t SL2OW : 1;   /*!< [2..2] Slot-2 Information Overwrite Flag                                  */
24069             __IM uint32_t SL3OW : 1;   /*!< [3..3] Slot-3 Information Overwrite Flag                                  */
24070             uint32_t            : 28;
24071         } RXRINFOOWSR_b;
24072     };
24073 
24074     union
24075     {
24076         __IOM uint32_t RXRINFOOWSCR;   /*!< (@ 0x0000023C) Receive Result Info Overwrite Status Clear Register        */
24077 
24078         struct
24079         {
24080             __IOM uint32_t SL0OW : 1;  /*!< [0..0] Slot-0 Information Overwrite Flag Clear                            */
24081             __IOM uint32_t SL1OW : 1;  /*!< [1..1] Slot-1 Information Overwrite Flag Clear                            */
24082             __IOM uint32_t SL2OW : 1;  /*!< [2..2] Slot-2 Information Overwrite Flag Clear                            */
24083             __IOM uint32_t SL3OW : 1;  /*!< [3..3] Slot-3 Information Overwrite Flag Clear                            */
24084             uint32_t             : 28;
24085         } RXRINFOOWSCR_b;
24086     };
24087 
24088     union
24089     {
24090         union
24091         {
24092             __IM uint32_t RXRSS0R;         /*!< (@ 0x00000240) Receive Result Save Slot-0 Register                        */
24093 
24094             struct
24095             {
24096                 __IM uint32_t DATA0   : 8; /*!< [7..0] Data 0                                                             */
24097                 __IM uint32_t DATA1   : 8; /*!< [15..8] Data 1                                                            */
24098                 __IM uint32_t DT      : 6; /*!< [21..16] Data Type                                                        */
24099                 __IM uint32_t VC      : 2; /*!< [23..22] Virtual Channel                                                  */
24100                 __IM uint32_t FMT     : 1; /*!< [24..24] Packet Format                                                    */
24101                 __IM uint32_t RXSUC   : 1; /*!< [25..25] Receive Success                                                  */
24102                 __IM uint32_t RXFERR  : 1; /*!< [26..26] Fatal Error                                                      */
24103                 __IM uint32_t RXFAIL  : 1; /*!< [27..27] Receive Fail                                                     */
24104                 __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail                                         */
24105                 __IM uint32_t RXCERR  : 1; /*!< [29..29] Receive Correctable Error                                        */
24106                 __IM uint32_t RXAKE   : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet                      */
24107                 __IM uint32_t INFOOW  : 1; /*!< [31..31] Information Overwrite                                            */
24108             } RXRSS0R_b;
24109         };
24110 
24111         struct
24112         {
24113             union
24114             {
24115                 union
24116                 {
24117                     __IM uint16_t RXRSS0R_L;     /*!< (@ 0x00000240) Receive Result Save Slot-0 Register                        */
24118 
24119                     struct
24120                     {
24121                         __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
24122                         __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
24123                     } RXRSS0R_L_b;
24124                 };
24125 
24126                 struct
24127                 {
24128                     union
24129                     {
24130                         __IM uint8_t RXRSS0R_LL;    /*!< (@ 0x00000240) Receive Result Save Slot-0 Register                        */
24131 
24132                         struct
24133                         {
24134                             __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
24135                         } RXRSS0R_LL_b;
24136                     };
24137 
24138                     union
24139                     {
24140                         __IM uint8_t RXRSS0R_LH;    /*!< (@ 0x00000241) Receive Result Save Slot-0 Register                        */
24141 
24142                         struct
24143                         {
24144                             __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1                                                             */
24145                         } RXRSS0R_LH_b;
24146                     };
24147                 };
24148             };
24149 
24150             union
24151             {
24152                 union
24153                 {
24154                     __IM uint16_t RXRSS0R_H;       /*!< (@ 0x00000242) Receive Result Save Slot-0 Register                        */
24155 
24156                     struct
24157                     {
24158                         __IM uint16_t DT      : 6; /*!< [5..0] Data Type                                                          */
24159                         __IM uint16_t VC      : 2; /*!< [7..6] Virtual Channel                                                    */
24160                         __IM uint16_t FMT     : 1; /*!< [8..8] Packet Format                                                      */
24161                         __IM uint16_t RXSUC   : 1; /*!< [9..9] Receive Success                                                    */
24162                         __IM uint16_t RXFERR  : 1; /*!< [10..10] Fatal Error                                                      */
24163                         __IM uint16_t RXFAIL  : 1; /*!< [11..11] Receive Fail                                                     */
24164                         __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail                                         */
24165                         __IM uint16_t RXCERR  : 1; /*!< [13..13] Receive Correctable Error                                        */
24166                         __IM uint16_t RXAKE   : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet                      */
24167                         __IM uint16_t INFOOW  : 1; /*!< [15..15] Information Overwrite                                            */
24168                     } RXRSS0R_H_b;
24169                 };
24170 
24171                 struct
24172                 {
24173                     union
24174                     {
24175                         __IM uint8_t RXRSS0R_HL; /*!< (@ 0x00000242) Receive Result Save Slot-0 Register                        */
24176 
24177                         struct
24178                         {
24179                             __IM uint8_t DT : 6; /*!< [5..0] Data Type                                                          */
24180                             __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel                                                    */
24181                         } RXRSS0R_HL_b;
24182                     };
24183 
24184                     union
24185                     {
24186                         __IM uint8_t RXRSS0R_HH;      /*!< (@ 0x00000243) Receive Result Save Slot-0 Register                        */
24187 
24188                         struct
24189                         {
24190                             __IM uint8_t FMT     : 1; /*!< [0..0] Packet Format                                                      */
24191                             __IM uint8_t RXSUC   : 1; /*!< [1..1] Receive Success                                                    */
24192                             __IM uint8_t RXFERR  : 1; /*!< [2..2] Fatal Error                                                        */
24193                             __IM uint8_t RXFAIL  : 1; /*!< [3..3] Receive Fail                                                       */
24194                             __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail                                           */
24195                             __IM uint8_t RXCERR  : 1; /*!< [5..5] Receive Correctable Error                                          */
24196                             __IM uint8_t RXAKE   : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet                        */
24197                             __IM uint8_t INFOOW  : 1; /*!< [7..7] Information Overwrite                                              */
24198                         } RXRSS0R_HH_b;
24199                     };
24200                 };
24201             };
24202         };
24203     };
24204 
24205     union
24206     {
24207         union
24208         {
24209             __IM uint32_t RXRSS1R;         /*!< (@ 0x00000244) Receive Result Save Slot-1 Register                        */
24210 
24211             struct
24212             {
24213                 __IM uint32_t DATA0   : 8; /*!< [7..0] Data 0                                                             */
24214                 __IM uint32_t DATA1   : 8; /*!< [15..8] Data 1                                                            */
24215                 __IM uint32_t DT      : 6; /*!< [21..16] Data Type                                                        */
24216                 __IM uint32_t VC      : 2; /*!< [23..22] Virtual Channel                                                  */
24217                 __IM uint32_t FMT     : 1; /*!< [24..24] Packet Format                                                    */
24218                 __IM uint32_t RXSUC   : 1; /*!< [25..25] Receive Success                                                  */
24219                 __IM uint32_t RXFERR  : 1; /*!< [26..26] Fatal Error                                                      */
24220                 __IM uint32_t RXFAIL  : 1; /*!< [27..27] Receive Fail                                                     */
24221                 __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail                                         */
24222                 __IM uint32_t RXCERR  : 1; /*!< [29..29] Receive Correctable Error                                        */
24223                 __IM uint32_t RXAKE   : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet                      */
24224                 __IM uint32_t INFOOW  : 1; /*!< [31..31] Information Overwrite                                            */
24225             } RXRSS1R_b;
24226         };
24227 
24228         struct
24229         {
24230             union
24231             {
24232                 union
24233                 {
24234                     __IM uint16_t RXRSS1R_L;     /*!< (@ 0x00000244) Receive Result Save Slot-1 Register                        */
24235 
24236                     struct
24237                     {
24238                         __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
24239                         __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
24240                     } RXRSS1R_L_b;
24241                 };
24242 
24243                 struct
24244                 {
24245                     union
24246                     {
24247                         __IM uint8_t RXRSS1R_LL;    /*!< (@ 0x00000244) Receive Result Save Slot-1 Register                        */
24248 
24249                         struct
24250                         {
24251                             __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
24252                         } RXRSS1R_LL_b;
24253                     };
24254 
24255                     union
24256                     {
24257                         __IM uint8_t RXRSS1R_LH;    /*!< (@ 0x00000245) Receive Result Save Slot-1 Register                        */
24258 
24259                         struct
24260                         {
24261                             __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1                                                             */
24262                         } RXRSS1R_LH_b;
24263                     };
24264                 };
24265             };
24266 
24267             union
24268             {
24269                 union
24270                 {
24271                     __IM uint16_t RXRSS1R_H;       /*!< (@ 0x00000246) Receive Result Save Slot-1 Register                        */
24272 
24273                     struct
24274                     {
24275                         __IM uint16_t DT      : 6; /*!< [5..0] Data Type                                                          */
24276                         __IM uint16_t VC      : 2; /*!< [7..6] Virtual Channel                                                    */
24277                         __IM uint16_t FMT     : 1; /*!< [8..8] Packet Format                                                      */
24278                         __IM uint16_t RXSUC   : 1; /*!< [9..9] Receive Success                                                    */
24279                         __IM uint16_t RXFERR  : 1; /*!< [10..10] Fatal Error                                                      */
24280                         __IM uint16_t RXFAIL  : 1; /*!< [11..11] Receive Fail                                                     */
24281                         __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail                                         */
24282                         __IM uint16_t RXCERR  : 1; /*!< [13..13] Receive Correctable Error                                        */
24283                         __IM uint16_t RXAKE   : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet                      */
24284                         __IM uint16_t INFOOW  : 1; /*!< [15..15] Information Overwrite                                            */
24285                     } RXRSS1R_H_b;
24286                 };
24287 
24288                 struct
24289                 {
24290                     union
24291                     {
24292                         __IM uint8_t RXRSS1R_HL; /*!< (@ 0x00000246) Receive Result Save Slot-1 Register                        */
24293 
24294                         struct
24295                         {
24296                             __IM uint8_t DT : 6; /*!< [5..0] Data Type                                                          */
24297                             __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel                                                    */
24298                         } RXRSS1R_HL_b;
24299                     };
24300 
24301                     union
24302                     {
24303                         __IM uint8_t RXRSS1R_HH;      /*!< (@ 0x00000247) Receive Result Save Slot-1 Register                        */
24304 
24305                         struct
24306                         {
24307                             __IM uint8_t FMT     : 1; /*!< [0..0] Packet Format                                                      */
24308                             __IM uint8_t RXSUC   : 1; /*!< [1..1] Receive Success                                                    */
24309                             __IM uint8_t RXFERR  : 1; /*!< [2..2] Fatal Error                                                        */
24310                             __IM uint8_t RXFAIL  : 1; /*!< [3..3] Receive Fail                                                       */
24311                             __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail                                           */
24312                             __IM uint8_t RXCERR  : 1; /*!< [5..5] Receive Correctable Error                                          */
24313                             __IM uint8_t RXAKE   : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet                        */
24314                             __IM uint8_t INFOOW  : 1; /*!< [7..7] Information Overwrite                                              */
24315                         } RXRSS1R_HH_b;
24316                     };
24317                 };
24318             };
24319         };
24320     };
24321 
24322     union
24323     {
24324         union
24325         {
24326             __IM uint32_t RXRSS2R;         /*!< (@ 0x00000248) Receive Result Save Slot-2 Register                        */
24327 
24328             struct
24329             {
24330                 __IM uint32_t DATA0   : 8; /*!< [7..0] Data 0                                                             */
24331                 __IM uint32_t DATA1   : 8; /*!< [15..8] Data 1                                                            */
24332                 __IM uint32_t DT      : 6; /*!< [21..16] Data Type                                                        */
24333                 __IM uint32_t VC      : 2; /*!< [23..22] Virtual Channel                                                  */
24334                 __IM uint32_t FMT     : 1; /*!< [24..24] Packet Format                                                    */
24335                 __IM uint32_t RXSUC   : 1; /*!< [25..25] Receive Success                                                  */
24336                 __IM uint32_t RXFERR  : 1; /*!< [26..26] Fatal Error                                                      */
24337                 __IM uint32_t RXFAIL  : 1; /*!< [27..27] Receive Fail                                                     */
24338                 __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail                                         */
24339                 __IM uint32_t RXCERR  : 1; /*!< [29..29] Receive Correctable Error                                        */
24340                 __IM uint32_t RXAKE   : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet                      */
24341                 __IM uint32_t INFOOW  : 1; /*!< [31..31] Information Overwrite                                            */
24342             } RXRSS2R_b;
24343         };
24344 
24345         struct
24346         {
24347             union
24348             {
24349                 union
24350                 {
24351                     __IM uint16_t RXRSS2R_L;     /*!< (@ 0x00000248) Receive Result Save Slot-2 Register                        */
24352 
24353                     struct
24354                     {
24355                         __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
24356                         __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
24357                     } RXRSS2R_L_b;
24358                 };
24359 
24360                 struct
24361                 {
24362                     union
24363                     {
24364                         __IM uint8_t RXRSS2R_LL;    /*!< (@ 0x00000248) Receive Result Save Slot-2 Register                        */
24365 
24366                         struct
24367                         {
24368                             __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
24369                         } RXRSS2R_LL_b;
24370                     };
24371 
24372                     union
24373                     {
24374                         __IM uint8_t RXRSS2R_LH;    /*!< (@ 0x00000249) Receive Result Save Slot-2 Register                        */
24375 
24376                         struct
24377                         {
24378                             __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1                                                             */
24379                         } RXRSS2R_LH_b;
24380                     };
24381                 };
24382             };
24383 
24384             union
24385             {
24386                 union
24387                 {
24388                     __IM uint16_t RXRSS2R_H;       /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register                        */
24389 
24390                     struct
24391                     {
24392                         __IM uint16_t DT      : 6; /*!< [5..0] Data Type                                                          */
24393                         __IM uint16_t VC      : 2; /*!< [7..6] Virtual Channel                                                    */
24394                         __IM uint16_t FMT     : 1; /*!< [8..8] Packet Format                                                      */
24395                         __IM uint16_t RXSUC   : 1; /*!< [9..9] Receive Success                                                    */
24396                         __IM uint16_t RXFERR  : 1; /*!< [10..10] Fatal Error                                                      */
24397                         __IM uint16_t RXFAIL  : 1; /*!< [11..11] Receive Fail                                                     */
24398                         __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail                                         */
24399                         __IM uint16_t RXCERR  : 1; /*!< [13..13] Receive Correctable Error                                        */
24400                         __IM uint16_t RXAKE   : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet                      */
24401                         __IM uint16_t INFOOW  : 1; /*!< [15..15] Information Overwrite                                            */
24402                     } RXRSS2R_H_b;
24403                 };
24404 
24405                 struct
24406                 {
24407                     union
24408                     {
24409                         __IM uint8_t RXRSS2R_HL; /*!< (@ 0x0000024A) Receive Result Save Slot-2 Register                        */
24410 
24411                         struct
24412                         {
24413                             __IM uint8_t DT : 6; /*!< [5..0] Data Type                                                          */
24414                             __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel                                                    */
24415                         } RXRSS2R_HL_b;
24416                     };
24417 
24418                     union
24419                     {
24420                         __IM uint8_t RXRSS2R_HH;      /*!< (@ 0x0000024B) Receive Result Save Slot-2 Register                        */
24421 
24422                         struct
24423                         {
24424                             __IM uint8_t FMT     : 1; /*!< [0..0] Packet Format                                                      */
24425                             __IM uint8_t RXSUC   : 1; /*!< [1..1] Receive Success                                                    */
24426                             __IM uint8_t RXFERR  : 1; /*!< [2..2] Fatal Error                                                        */
24427                             __IM uint8_t RXFAIL  : 1; /*!< [3..3] Receive Fail                                                       */
24428                             __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail                                           */
24429                             __IM uint8_t RXCERR  : 1; /*!< [5..5] Receive Correctable Error                                          */
24430                             __IM uint8_t RXAKE   : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet                        */
24431                             __IM uint8_t INFOOW  : 1; /*!< [7..7] Information Overwrite                                              */
24432                         } RXRSS2R_HH_b;
24433                     };
24434                 };
24435             };
24436         };
24437     };
24438 
24439     union
24440     {
24441         union
24442         {
24443             __IM uint32_t RXRSS3R;         /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register                        */
24444 
24445             struct
24446             {
24447                 __IM uint32_t DATA0   : 8; /*!< [7..0] Data 0                                                             */
24448                 __IM uint32_t DATA1   : 8; /*!< [15..8] Data 1                                                            */
24449                 __IM uint32_t DT      : 6; /*!< [21..16] Data Type                                                        */
24450                 __IM uint32_t VC      : 2; /*!< [23..22] Virtual Channel                                                  */
24451                 __IM uint32_t FMT     : 1; /*!< [24..24] Packet Format                                                    */
24452                 __IM uint32_t RXSUC   : 1; /*!< [25..25] Receive Success                                                  */
24453                 __IM uint32_t RXFERR  : 1; /*!< [26..26] Fatal Error                                                      */
24454                 __IM uint32_t RXFAIL  : 1; /*!< [27..27] Receive Fail                                                     */
24455                 __IM uint32_t RXPFAIL : 1; /*!< [28..28] Receive Packet Data Fail                                         */
24456                 __IM uint32_t RXCERR  : 1; /*!< [29..29] Receive Correctable Error                                        */
24457                 __IM uint32_t RXAKE   : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet                      */
24458                 __IM uint32_t INFOOW  : 1; /*!< [31..31] Information Overwrite                                            */
24459             } RXRSS3R_b;
24460         };
24461 
24462         struct
24463         {
24464             union
24465             {
24466                 union
24467                 {
24468                     __IM uint16_t RXRSS3R_L;     /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register                        */
24469 
24470                     struct
24471                     {
24472                         __IM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
24473                         __IM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
24474                     } RXRSS3R_L_b;
24475                 };
24476 
24477                 struct
24478                 {
24479                     union
24480                     {
24481                         __IM uint8_t RXRSS3R_LL;    /*!< (@ 0x0000024C) Receive Result Save Slot-3 Register                        */
24482 
24483                         struct
24484                         {
24485                             __IM uint8_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
24486                         } RXRSS3R_LL_b;
24487                     };
24488 
24489                     union
24490                     {
24491                         __IM uint8_t RXRSS3R_LH;    /*!< (@ 0x0000024D) Receive Result Save Slot-3 Register                        */
24492 
24493                         struct
24494                         {
24495                             __IM uint8_t DATA1 : 8; /*!< [7..0] Data 1                                                             */
24496                         } RXRSS3R_LH_b;
24497                     };
24498                 };
24499             };
24500 
24501             union
24502             {
24503                 union
24504                 {
24505                     __IM uint16_t RXRSS3R_H;       /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register                        */
24506 
24507                     struct
24508                     {
24509                         __IM uint16_t DT      : 6; /*!< [5..0] Data Type                                                          */
24510                         __IM uint16_t VC      : 2; /*!< [7..6] Virtual Channel                                                    */
24511                         __IM uint16_t FMT     : 1; /*!< [8..8] Packet Format                                                      */
24512                         __IM uint16_t RXSUC   : 1; /*!< [9..9] Receive Success                                                    */
24513                         __IM uint16_t RXFERR  : 1; /*!< [10..10] Fatal Error                                                      */
24514                         __IM uint16_t RXFAIL  : 1; /*!< [11..11] Receive Fail                                                     */
24515                         __IM uint16_t RXPFAIL : 1; /*!< [12..12] Receive Packet Data Fail                                         */
24516                         __IM uint16_t RXCERR  : 1; /*!< [13..13] Receive Correctable Error                                        */
24517                         __IM uint16_t RXAKE   : 1; /*!< [14..14] Receive Acknowledge and Error Report Packet                      */
24518                         __IM uint16_t INFOOW  : 1; /*!< [15..15] Information Overwrite                                            */
24519                     } RXRSS3R_H_b;
24520                 };
24521 
24522                 struct
24523                 {
24524                     union
24525                     {
24526                         __IM uint8_t RXRSS3R_HL; /*!< (@ 0x0000024E) Receive Result Save Slot-3 Register                        */
24527 
24528                         struct
24529                         {
24530                             __IM uint8_t DT : 6; /*!< [5..0] Data Type                                                          */
24531                             __IM uint8_t VC : 2; /*!< [7..6] Virtual Channel                                                    */
24532                         } RXRSS3R_HL_b;
24533                     };
24534 
24535                     union
24536                     {
24537                         __IM uint8_t RXRSS3R_HH;      /*!< (@ 0x0000024F) Receive Result Save Slot-3 Register                        */
24538 
24539                         struct
24540                         {
24541                             __IM uint8_t FMT     : 1; /*!< [0..0] Packet Format                                                      */
24542                             __IM uint8_t RXSUC   : 1; /*!< [1..1] Receive Success                                                    */
24543                             __IM uint8_t RXFERR  : 1; /*!< [2..2] Fatal Error                                                        */
24544                             __IM uint8_t RXFAIL  : 1; /*!< [3..3] Receive Fail                                                       */
24545                             __IM uint8_t RXPFAIL : 1; /*!< [4..4] Receive Packet Data Fail                                           */
24546                             __IM uint8_t RXCERR  : 1; /*!< [5..5] Receive Correctable Error                                          */
24547                             __IM uint8_t RXAKE   : 1; /*!< [6..6] Receive Acknowledge and Error Report Packet                        */
24548                             __IM uint8_t INFOOW  : 1; /*!< [7..7] Information Overwrite                                              */
24549                         } RXRSS3R_HH_b;
24550                     };
24551                 };
24552             };
24553         };
24554     };
24555     __IM uint32_t RESERVED8[28];
24556 
24557     union
24558     {
24559         __IM uint32_t RXPPD0R;         /*!< (@ 0x000002C0) Receive Packet Payload Data 0 Register                     */
24560 
24561         struct
24562         {
24563             __IM uint32_t DATA0 : 8;   /*!< [7..0] Payload Data 0                                                     */
24564             __IM uint32_t DATA1 : 8;   /*!< [15..8] Payload Data 1                                                    */
24565             __IM uint32_t DATA2 : 8;   /*!< [23..16] Payload Data 2                                                   */
24566             __IM uint32_t DATA3 : 8;   /*!< [31..24] Payload Data 3                                                   */
24567         } RXPPD0R_b;
24568     };
24569 
24570     union
24571     {
24572         __IM uint32_t RXPPD1R;         /*!< (@ 0x000002C4) Receive Packet Payload Data 1 Register                     */
24573 
24574         struct
24575         {
24576             __IM uint32_t DATA4 : 8;   /*!< [7..0] Payload Data 0                                                     */
24577             __IM uint32_t DATA5 : 8;   /*!< [15..8] Payload Data 1                                                    */
24578             __IM uint32_t DATA6 : 8;   /*!< [23..16] Payload Data 2                                                   */
24579             __IM uint32_t DATA7 : 8;   /*!< [31..24] Payload Data 3                                                   */
24580         } RXPPD1R_b;
24581     };
24582 
24583     union
24584     {
24585         __IM uint32_t RXPPD2R;         /*!< (@ 0x000002C8) Receive Packet Payload Data 2 Register                     */
24586 
24587         struct
24588         {
24589             __IM uint32_t DATA8  : 8;  /*!< [7..0] Payload Data 8                                                     */
24590             __IM uint32_t DATA9  : 8;  /*!< [15..8] Payload Data 9                                                    */
24591             __IM uint32_t DATA10 : 8;  /*!< [23..16] Payload Data 10                                                  */
24592             __IM uint32_t DATA11 : 8;  /*!< [31..24] Payload Data 11                                                  */
24593         } RXPPD2R_b;
24594     };
24595 
24596     union
24597     {
24598         __IM uint32_t RXPPD3R;         /*!< (@ 0x000002CC) Receive Packet Payload Data 3 Register                     */
24599 
24600         struct
24601         {
24602             __IM uint32_t DATA12 : 8;  /*!< [7..0] Payload Data 12                                                    */
24603             __IM uint32_t DATA13 : 8;  /*!< [15..8] Payload Data 13                                                   */
24604             __IM uint32_t DATA14 : 8;  /*!< [23..16] Payload Data 14                                                  */
24605             __IM uint32_t DATA15 : 8;  /*!< [31..24] Payload Data 15                                                  */
24606         } RXPPD3R_b;
24607     };
24608     __IM uint32_t RESERVED9[4];
24609 
24610     union
24611     {
24612         __IOM uint32_t HSTXTOSETR;     /*!< (@ 0x000002E0) HS TX Timeout Set Register                                 */
24613 
24614         struct
24615         {
24616             __IOM uint32_t HTXTO : 32; /*!< [31..0] HS TX Timeout Count                                               */
24617         } HSTXTOSETR_b;
24618     };
24619 
24620     union
24621     {
24622         __IOM uint32_t LRXHTOSETR;      /*!< (@ 0x000002E4) LRX-H Timeout Set Register                                 */
24623 
24624         struct
24625         {
24626             __IOM uint32_t LRXHTO : 32; /*!< [31..0] LP-RX Host Processor Timeout                                      */
24627         } LRXHTOSETR_b;
24628     };
24629 
24630     union
24631     {
24632         __IOM uint32_t TATOSETR;       /*!< (@ 0x000002E8) TA Timeout Set Register                                    */
24633 
24634         struct
24635         {
24636             __IOM uint32_t TATO : 32;  /*!< [31..0] Turnaround Acknowledge Timeout                                    */
24637         } TATOSETR_b;
24638     };
24639     __IM uint32_t RESERVED10[5];
24640 
24641     union
24642     {
24643         __IM uint32_t FERRSR;          /*!< (@ 0x00000300) Fatal Error Status Register                                */
24644 
24645         struct
24646         {
24647             __IM uint32_t HTXTO   : 1; /*!< [0..0] HS TX Timeout Interrupt Flag                                       */
24648             __IM uint32_t LRXHTO  : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag                        */
24649             __IM uint32_t TATO    : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag                      */
24650             uint32_t              : 13;
24651             __IM uint32_t ESCENT  : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag                           */
24652             __IM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag                                   */
24653             __IM uint32_t CTRL    : 1; /*!< [18..18] Control Error Interrupt Flag                                     */
24654             __IM uint32_t CLP0    : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag                              */
24655             __IM uint32_t CLP1    : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag                              */
24656             uint32_t              : 6;
24657             __IM uint32_t CLP0S   : 1; /*!< [27..27] LP0 Contention Error Status                                      */
24658             __IM uint32_t CLP1S   : 1; /*!< [28..28] LP1 Contention Error Status                                      */
24659             uint32_t              : 3;
24660         } FERRSR_b;
24661     };
24662 
24663     union
24664     {
24665         __IOM uint32_t FERRSCR;         /*!< (@ 0x00000304) Fatal Error Status Clear Register                          */
24666 
24667         struct
24668         {
24669             __IOM uint32_t HTXTO   : 1; /*!< [0..0] HS TX Timeout Interrupt Flag Clear                                 */
24670             __IOM uint32_t LRXHTO  : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Flag Clear                  */
24671             __IOM uint32_t TATO    : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Flag Clear                */
24672             uint32_t               : 13;
24673             __IOM uint32_t ESCENT  : 1; /*!< [16..16] Escape mode Entry Error Interrupt Flag Clear                     */
24674             __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Flag Clear                             */
24675             __IOM uint32_t CTRL    : 1; /*!< [18..18] Control Error Interrupt Flag Clear                               */
24676             __IOM uint32_t CLP0    : 1; /*!< [19..19] LP0 Contention Error Interrupt Flag Clear                        */
24677             __IOM uint32_t CLP1    : 1; /*!< [20..20] LP1 Contention Error Interrupt Flag Clear                        */
24678             uint32_t               : 11;
24679         } FERRSCR_b;
24680     };
24681 
24682     union
24683     {
24684         __IOM uint32_t FERRIER;         /*!< (@ 0x00000308) Fatal Error Interrupt Enable Register                      */
24685 
24686         struct
24687         {
24688             __IOM uint32_t HTXTO   : 1; /*!< [0..0] HS TX Timeout Interrupt Enable                                     */
24689             __IOM uint32_t LRXHTO  : 1; /*!< [1..1] LP-RX Host Processor Timeout Interrupt Enable                      */
24690             __IOM uint32_t TATO    : 1; /*!< [2..2] Turnaround Acknowledge Timeout Interrupt Enable                    */
24691             uint32_t               : 13;
24692             __IOM uint32_t ESCENT  : 1; /*!< [16..16] Escape mode Entry Error Interrupt Enable                         */
24693             __IOM uint32_t SYNCESC : 1; /*!< [17..17] LPDT Sync Error Interrupt Enable                                 */
24694             __IOM uint32_t CTRL    : 1; /*!< [18..18] Control Error Interrupt Enable                                   */
24695             __IOM uint32_t CLP0    : 1; /*!< [19..19] LP0 Contention Error Interrupt Enable                            */
24696             __IOM uint32_t CLP1    : 1; /*!< [20..20] LP1 Contention Error Interrupt Enable                            */
24697             uint32_t               : 11;
24698         } FERRIER_b;
24699     };
24700     __IM uint32_t RESERVED11[2];
24701 
24702     union
24703     {
24704         __IOM uint32_t CLSTPTSETR;     /*!< (@ 0x00000314) Clock Lane Stop Time Set Register                          */
24705 
24706         struct
24707         {
24708             uint32_t               : 2;
24709             __IOM uint32_t CLKSTPT : 10; /*!< [11..2] Clock Stop Time                                                   */
24710             uint32_t               : 4;
24711             __IOM uint32_t CLKBFHT : 8;  /*!< [23..16] Clock Beforehand Time                                            */
24712             __IOM uint32_t CLKKPT  : 8;  /*!< [31..24] Clock Keep Time                                                  */
24713         } CLSTPTSETR_b;
24714     };
24715 
24716     union
24717     {
24718         __IOM uint32_t LPTRNSTSETR;      /*!< (@ 0x00000318) LP Transition Time Set Register                            */
24719 
24720         struct
24721         {
24722             __IOM uint32_t GOLPBKT : 10; /*!< [9..0] Go LP and Back Time                                                */
24723             uint32_t               : 22;
24724         } LPTRNSTSETR_b;
24725     };
24726     __IM uint32_t RESERVED12;
24727 
24728     union
24729     {
24730         __IM uint32_t PLSR;             /*!< (@ 0x00000320) Physical Lane Status Register                              */
24731 
24732         struct
24733         {
24734             __IM uint32_t CLUAN    : 1; /*!< [0..0] Clock Lane UlpsActiveNot Status                                    */
24735             __IM uint32_t CLSTP    : 1; /*!< [1..1] Clock Lane Stop Status                                             */
24736             __IM uint32_t DL0RLE   : 1; /*!< [2..2] Data Lane-0 RxLpdtEsc Status                                       */
24737             __IM uint32_t DL0RUE   : 1; /*!< [3..3] Data Lane-0 RxUlpsEsc Status                                       */
24738             __IM uint32_t DL0UAN   : 1; /*!< [4..4] Data Lane-0 UlpsActiveNot Status                                   */
24739             __IM uint32_t DL1UAN   : 1; /*!< [5..5] Data Lane-1 UlpsActiveNot Status                                   */
24740             uint32_t               : 2;
24741             __IM uint32_t DL0STP   : 1; /*!< [8..8] Data Lane-0 Stop Status                                            */
24742             __IM uint32_t DL1STP   : 1; /*!< [9..9] Data Lane-1 Stop Status                                            */
24743             uint32_t               : 2;
24744             __IM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag                   */
24745             __IM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag                   */
24746             uint32_t               : 1;
24747             __IM uint32_t DL0DIR   : 1; /*!< [15..15] Data Lane-0 Direction                                            */
24748             uint32_t               : 8;
24749             __IM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag                             */
24750             __IM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag                              */
24751             __IM uint32_t CLLP2HS  : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag                    */
24752             __IM uint32_t CLHS2LP  : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag                    */
24753             __IM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag                              */
24754             __IM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag                               */
24755             uint32_t               : 2;
24756         } PLSR_b;
24757     };
24758 
24759     union
24760     {
24761         __IOM uint32_t PLSCR;          /*!< (@ 0x00000324) Physical Lane Status Clear Register                        */
24762 
24763         struct
24764         {
24765             uint32_t                : 12;
24766             __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Flag Clear             */
24767             __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Flag Clear             */
24768             uint32_t                : 10;
24769             __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Flag Clear                       */
24770             __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Flag Clear                        */
24771             __IOM uint32_t CLLP2HS  : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Flag Clear              */
24772             __IOM uint32_t CLHS2LP  : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Flag Clear              */
24773             __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Flag Clear                        */
24774             __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Flag Clear                         */
24775             uint32_t                : 2;
24776         } PLSCR_b;
24777     };
24778 
24779     union
24780     {
24781         __IOM uint32_t PLIER;          /*!< (@ 0x00000328) Physical Lane Interrupt Enable Register                    */
24782 
24783         struct
24784         {
24785             uint32_t                : 12;
24786             __IOM uint32_t DL0RX2TX : 1; /*!< [12..12] Data Lane-0 RX to TX Transition Interrupt Enable                 */
24787             __IOM uint32_t DL0TX2RX : 1; /*!< [13..13] Data Lane-0 TX to RX Transition Interrupt Enable                 */
24788             uint32_t                : 10;
24789             __IOM uint32_t CLULPENT : 1; /*!< [24..24] Clock Lane ULPS Enter Interrupt Enable                           */
24790             __IOM uint32_t CLULPEXT : 1; /*!< [25..25] Clock Lane ULPS Exit Interrupt Enable                            */
24791             __IOM uint32_t CLLP2HS  : 1; /*!< [26..26] Clock Lane LP to HS Transition Interrupt Enable                  */
24792             __IOM uint32_t CLHS2LP  : 1; /*!< [27..27] Clock Lane HS to LP Transition Interrupt Enable                  */
24793             __IOM uint32_t DLULPENT : 1; /*!< [28..28] Data Lane ULPS Enter Interrupt Enable                            */
24794             __IOM uint32_t DLULPEXT : 1; /*!< [29..29] Data Lane ULPS Exit Interrupt Enable                             */
24795             uint32_t                : 2;
24796         } PLIER_b;
24797     };
24798     __IM uint32_t RESERVED13[53];
24799 
24800     union
24801     {
24802         __IOM uint32_t VMSET0R;         /*!< (@ 0x00000400) Video Mode Set 0 Register                                  */
24803 
24804         struct
24805         {
24806             __OM uint32_t VSTART   : 1; /*!< [0..0] Video Mode Operation Start                                         */
24807             __OM uint32_t VSTOP    : 1; /*!< [1..1] Video Mode Operation Stop                                          */
24808             uint32_t               : 6;
24809             __IOM uint32_t HSANOLP : 1; /*!< [8..8] HSA period No LP                                                   */
24810             __IOM uint32_t HBPNOLP : 1; /*!< [9..9] HBP period No LP                                                   */
24811             __IOM uint32_t HFPNOLP : 1; /*!< [10..10] HFP period No LP                                                 */
24812             uint32_t               : 21;
24813         } VMSET0R_b;
24814     };
24815 
24816     union
24817     {
24818         __IOM uint32_t VMSET1R;        /*!< (@ 0x00000404) Video Mode Set 1 Register                                  */
24819 
24820         struct
24821         {
24822             uint32_t           : 2;
24823             __IOM uint32_t DLY : 12;   /*!< [13..2] Delay Value                                                       */
24824             uint32_t           : 18;
24825         } VMSET1R_b;
24826     };
24827     __IM uint32_t RESERVED14[2];
24828 
24829     union
24830     {
24831         __IM uint32_t VMSR;            /*!< (@ 0x00000410) Video Mode Status Register                                 */
24832 
24833         struct
24834         {
24835             __IM uint32_t START   : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag                          */
24836             __IM uint32_t STOP    : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag                           */
24837             __IM uint32_t RUNNING : 1; /*!< [2..2] Video Mode Operation Running Status                                */
24838             __IM uint32_t VIRDY   : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag                          */
24839             uint32_t              : 16;
24840             __IM uint32_t TIMERR  : 1; /*!< [20..20] Timing Error Interrupt Flag                                      */
24841             uint32_t              : 1;
24842             __IM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag                      */
24843             __IM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag                       */
24844             uint32_t              : 8;
24845         } VMSR_b;
24846     };
24847 
24848     union
24849     {
24850         __IOM uint32_t VMSCR;           /*!< (@ 0x00000414) Video Mode Status Clear Register                           */
24851 
24852         struct
24853         {
24854             __IOM uint32_t START   : 1; /*!< [0..0] Video Mode Operation Start Interrupt Flag Clear                    */
24855             __IOM uint32_t STOP    : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Flag Clear                     */
24856             uint32_t               : 1;
24857             __IOM uint32_t VIRDY   : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Flag Clear                    */
24858             uint32_t               : 16;
24859             __IOM uint32_t TIMERR  : 1; /*!< [20..20] Timing Error Interrupt Flag Clear                                */
24860             uint32_t               : 1;
24861             __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Flag Clear                */
24862             __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Flag Clear                 */
24863             uint32_t               : 8;
24864         } VMSCR_b;
24865     };
24866 
24867     union
24868     {
24869         __IOM uint32_t VMIER;           /*!< (@ 0x00000418) Video Mode Interrupt Enable Register                       */
24870 
24871         struct
24872         {
24873             __IOM uint32_t START   : 1; /*!< [0..0] Video Mode Operation Start Interrupt Enable                        */
24874             __IOM uint32_t STOP    : 1; /*!< [1..1] Video Mode Operation Stop Interrupt Enable                         */
24875             uint32_t               : 1;
24876             __IOM uint32_t VIRDY   : 1; /*!< [3..3] Video Mode Operation Ready Interrupt Enable                        */
24877             uint32_t               : 16;
24878             __IOM uint32_t TIMERR  : 1; /*!< [20..20] Timing Error Interrupt Enable                                    */
24879             uint32_t               : 1;
24880             __IOM uint32_t VBUFUDF : 1; /*!< [22..22] Video Buffer Underflow Error Interrupt Enable                    */
24881             __IOM uint32_t VBUFOVF : 1; /*!< [23..23] Video Buffer Overflow Error Interrupt Enable                     */
24882             uint32_t               : 8;
24883         } VMIER_b;
24884     };
24885     __IM uint32_t RESERVED15;
24886 
24887     union
24888     {
24889         __IOM uint32_t VMPPSETR;       /*!< (@ 0x00000420) Video Mode Pixel Packet Set Register                       */
24890 
24891         struct
24892         {
24893             uint32_t               : 15;
24894             __IOM uint32_t TXESYNC : 1; /*!< [15..15] Transmit End of Sync Pulse                                       */
24895             __IOM uint32_t DT      : 6; /*!< [21..16] Video Mode Data Type                                             */
24896             __IOM uint32_t VC      : 2; /*!< [23..22] Video Mode Virtual Channel                                       */
24897             uint32_t               : 8;
24898         } VMPPSETR_b;
24899     };
24900     __IM uint32_t RESERVED16;
24901 
24902     union
24903     {
24904         __IOM uint32_t VMVSSETR;       /*!< (@ 0x00000428) Video Mode Vertical Size Set Register                      */
24905 
24906         struct
24907         {
24908             __IOM uint32_t VSA   : 12; /*!< [11..0] VSA Lines                                                         */
24909             uint32_t             : 3;
24910             __IOM uint32_t VSPOL : 1;  /*!< [15..15] VSYNC Polarity                                                   */
24911             __IOM uint32_t VACT  : 15; /*!< [30..16] Vertical Active Lines                                            */
24912             uint32_t             : 1;
24913         } VMVSSETR_b;
24914     };
24915 
24916     union
24917     {
24918         __IOM uint32_t VMVPSETR;       /*!< (@ 0x0000042C) Video Mode Vertical Porch Set Register                     */
24919 
24920         struct
24921         {
24922             __IOM uint32_t VBP : 13;   /*!< [12..0] VBP Lines                                                         */
24923             uint32_t           : 3;
24924             __IOM uint32_t VFP : 13;   /*!< [28..16] VFP Lines                                                        */
24925             uint32_t           : 3;
24926         } VMVPSETR_b;
24927     };
24928 
24929     union
24930     {
24931         __IOM uint32_t VMHSSETR;       /*!< (@ 0x00000430) Video Mode Horizontal Size Set Register                    */
24932 
24933         struct
24934         {
24935             __IOM uint32_t HSA   : 12; /*!< [11..0] HSA Pixels                                                        */
24936             uint32_t             : 3;
24937             __IOM uint32_t HSPOL : 1;  /*!< [15..15] HSYNC Polarity                                                   */
24938             __IOM uint32_t HACT  : 15; /*!< [30..16] HACT Pixels                                                      */
24939             uint32_t             : 1;
24940         } VMHSSETR_b;
24941     };
24942 
24943     union
24944     {
24945         __IOM uint32_t VMHPSETR;       /*!< (@ 0x00000434) Video Mode Horizontal Porch Set Register                   */
24946 
24947         struct
24948         {
24949             __IOM uint32_t HBP : 13;   /*!< [12..0] HBP Pixels                                                        */
24950             uint32_t           : 3;
24951             __IOM uint32_t HFP : 13;   /*!< [28..16] HFP Pixels                                                       */
24952             uint32_t           : 3;
24953         } VMHPSETR_b;
24954     };
24955     __IM uint32_t RESERVED17[98];
24956 
24957     union
24958     {
24959         __IOM uint32_t SQCH0SET0R;     /*!< (@ 0x000005C0) Sequence Channel 0 Set 0 Register                          */
24960 
24961         struct
24962         {
24963             __OM uint32_t START : 1;   /*!< [0..0] Sequence Operation Start                                           */
24964             uint32_t            : 31;
24965         } SQCH0SET0R_b;
24966     };
24967     __IM uint32_t RESERVED18[3];
24968 
24969     union
24970     {
24971         __IM uint32_t SQCH0SR;         /*!< (@ 0x000005D0) Sequence Channel 0 Status Register                         */
24972 
24973         struct
24974         {
24975             uint32_t               : 2;
24976             __IM uint32_t RUNNING  : 1; /*!< [2..2] Sequence Operation Running Status                                  */
24977             uint32_t               : 1;
24978             __IM uint32_t AACTFIN  : 1; /*!< [4..4] All Actions Finish Interrupt Flag                                  */
24979             uint32_t               : 3;
24980             __IM uint32_t ADESFIN  : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag                              */
24981             uint32_t               : 7;
24982             __IM uint32_t DABORT   : 1; /*!< [16..16] Descriptor Abort Interrupt Flag                                  */
24983             uint32_t               : 2;
24984             __IM uint32_t SIZEERR  : 1; /*!< [19..19] Packet Size Error Interrupt Flag                                 */
24985             uint32_t               : 4;
24986             __IM uint32_t TXIBERR  : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag                             */
24987             uint32_t               : 1;
24988             __IM uint32_t RXFERR   : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag                               */
24989             __IM uint32_t RXFAIL   : 1; /*!< [27..27] Receive Fail Interrupt Flag                                      */
24990             __IM uint32_t RXPFAIL  : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag                          */
24991             __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag                         */
24992             __IM uint32_t RXAKE    : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt
24993                                          *   Flag                                                                      */
24994             uint32_t : 1;
24995         } SQCH0SR_b;
24996     };
24997 
24998     union
24999     {
25000         __IOM uint32_t SQCH0SCR;       /*!< (@ 0x000005D4) Sequence Channel 0 Status Clear Register                   */
25001 
25002         struct
25003         {
25004             uint32_t                : 4;
25005             __IOM uint32_t AACTFIN  : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear                            */
25006             uint32_t                : 3;
25007             __IOM uint32_t ADESFIN  : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear                        */
25008             uint32_t                : 7;
25009             __IOM uint32_t DABORT   : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear                            */
25010             uint32_t                : 2;
25011             __IOM uint32_t SIZEERR  : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear                           */
25012             uint32_t                : 4;
25013             __IOM uint32_t TXIBERR  : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear                       */
25014             uint32_t                : 1;
25015             __IOM uint32_t RXFERR   : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear                         */
25016             __IOM uint32_t RXFAIL   : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear                                */
25017             __IOM uint32_t RXPFAIL  : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear                    */
25018             __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear                   */
25019             __IOM uint32_t RXAKE    : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt
25020                                           *   Flag Clear                                                                */
25021             uint32_t : 1;
25022         } SQCH0SCR_b;
25023     };
25024 
25025     union
25026     {
25027         __IOM uint32_t SQCH0IER;       /*!< (@ 0x000005D8) Sequence Channel 0 Interrupt Enable Register               */
25028 
25029         struct
25030         {
25031             uint32_t                : 4;
25032             __IOM uint32_t AACTFIN  : 1; /*!< [4..4] All Actions Finish Interrupt Enable                                */
25033             uint32_t                : 3;
25034             __IOM uint32_t ADESFIN  : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable                            */
25035             uint32_t                : 7;
25036             __IOM uint32_t DABORT   : 1; /*!< [16..16] Descriptor Abort Interrupt Enable                                */
25037             uint32_t                : 2;
25038             __IOM uint32_t SIZEERR  : 1; /*!< [19..19] Packet Size Error Interrupt Enable                               */
25039             uint32_t                : 4;
25040             __IOM uint32_t TXIBERR  : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable                           */
25041             uint32_t                : 1;
25042             __IOM uint32_t RXFERR   : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable                             */
25043             __IOM uint32_t RXFAIL   : 1; /*!< [27..27] Receive Fail Interrupt Enable                                    */
25044             __IOM uint32_t RXPFAIL  : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable                        */
25045             __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable                       */
25046             __IOM uint32_t RXAKE    : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt
25047                                           *   Enable                                                                    */
25048             uint32_t : 1;
25049         } SQCH0IER_b;
25050     };
25051     __IM uint32_t RESERVED19[9];
25052 
25053     union
25054     {
25055         __IOM uint32_t SQCH1SET0R;     /*!< (@ 0x00000600) Sequence Channel 1 Set 0 Register                          */
25056 
25057         struct
25058         {
25059             __OM uint32_t START : 1;   /*!< [0..0] Sequence Operation Start                                           */
25060             uint32_t            : 31;
25061         } SQCH1SET0R_b;
25062     };
25063     __IM uint32_t RESERVED20[3];
25064 
25065     union
25066     {
25067         __IM uint32_t SQCH1SR;         /*!< (@ 0x00000610) Sequence Channel 1 Status Register                         */
25068 
25069         struct
25070         {
25071             uint32_t               : 2;
25072             __IM uint32_t RUNNING  : 1; /*!< [2..2] Sequence Operation Running Status                                  */
25073             uint32_t               : 1;
25074             __IM uint32_t AACTFIN  : 1; /*!< [4..4] All Actions Finish Interrupt Flag                                  */
25075             uint32_t               : 3;
25076             __IM uint32_t ADESFIN  : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag                              */
25077             uint32_t               : 7;
25078             __IM uint32_t DABORT   : 1; /*!< [16..16] Descriptor Abort Interrupt Flag                                  */
25079             uint32_t               : 2;
25080             __IM uint32_t SIZEERR  : 1; /*!< [19..19] Packet Size Error Interrupt Flag                                 */
25081             uint32_t               : 4;
25082             __IM uint32_t TXIBERR  : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag                             */
25083             uint32_t               : 1;
25084             __IM uint32_t RXFERR   : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag                               */
25085             __IM uint32_t RXFAIL   : 1; /*!< [27..27] Receive Fail Interrupt Flag                                      */
25086             __IM uint32_t RXPFAIL  : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag                          */
25087             __IM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag                         */
25088             __IM uint32_t RXAKE    : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt
25089                                          *   Flag                                                                      */
25090             uint32_t : 1;
25091         } SQCH1SR_b;
25092     };
25093 
25094     union
25095     {
25096         __IOM uint32_t SQCH1SCR;       /*!< (@ 0x00000614) Sequence Channel 1 Status Clear Register                   */
25097 
25098         struct
25099         {
25100             uint32_t                : 4;
25101             __IOM uint32_t AACTFIN  : 1; /*!< [4..4] All Actions Finish Interrupt Flag Clear                            */
25102             uint32_t                : 3;
25103             __IOM uint32_t ADESFIN  : 1; /*!< [8..8] All-Descriptors Finish Interrupt Flag Clear                        */
25104             uint32_t                : 7;
25105             __IOM uint32_t DABORT   : 1; /*!< [16..16] Descriptor Abort Interrupt Flag Clear                            */
25106             uint32_t                : 2;
25107             __IOM uint32_t SIZEERR  : 1; /*!< [19..19] Packet Size Error Interrupt Flag Clear                           */
25108             uint32_t                : 4;
25109             __IOM uint32_t TXIBERR  : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Flag Clear                       */
25110             uint32_t                : 1;
25111             __IOM uint32_t RXFERR   : 1; /*!< [26..26] Receive Fatal Error Interrupt Flag Clear                         */
25112             __IOM uint32_t RXFAIL   : 1; /*!< [27..27] Receive Fail Interrupt Flag Clear                                */
25113             __IOM uint32_t RXPFAIL  : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Flag Clear                    */
25114             __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Flag Clear                   */
25115             __IOM uint32_t RXAKE    : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt
25116                                           *   Flag Clear                                                                */
25117             uint32_t : 1;
25118         } SQCH1SCR_b;
25119     };
25120 
25121     union
25122     {
25123         __IOM uint32_t SQCH1IER;       /*!< (@ 0x00000618) Sequence Channel 1 Interrupt Enable Register               */
25124 
25125         struct
25126         {
25127             uint32_t                : 4;
25128             __IOM uint32_t AACTFIN  : 1; /*!< [4..4] All Actions Finish Interrupt Enable                                */
25129             uint32_t                : 3;
25130             __IOM uint32_t ADESFIN  : 1; /*!< [8..8] All-Descriptors Finish Interrupt Enable                            */
25131             uint32_t                : 7;
25132             __IOM uint32_t DABORT   : 1; /*!< [16..16] Descriptor Abort Interrupt Enable                                */
25133             uint32_t                : 2;
25134             __IOM uint32_t SIZEERR  : 1; /*!< [19..19] Packet Size Error Interrupt Enable                               */
25135             uint32_t                : 4;
25136             __IOM uint32_t TXIBERR  : 1; /*!< [24..24] Tx Internal Bus Error Interrupt Enable                           */
25137             uint32_t                : 1;
25138             __IOM uint32_t RXFERR   : 1; /*!< [26..26] Receive Fatal Error Interrupt Enable                             */
25139             __IOM uint32_t RXFAIL   : 1; /*!< [27..27] Receive Fail Interrupt Enable                                    */
25140             __IOM uint32_t RXPFAIL  : 1; /*!< [28..28] Receive Packet Data Fail Interrupt Enable                        */
25141             __IOM uint32_t RXCORERR : 1; /*!< [29..29] Receive Correctable Error Interrupt Enable                       */
25142             __IOM uint32_t RXAKE    : 1; /*!< [30..30] Receive Acknowledge and Error Report Packet Interrupt
25143                                           *   Enable                                                                    */
25144             uint32_t : 1;
25145         } SQCH1IER_b;
25146     };
25147     __IM uint32_t RESERVED21[89];
25148 
25149     union
25150     {
25151         union
25152         {
25153             __IOM uint32_t SQCH0DSC0AR;   /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register                 */
25154 
25155             struct
25156             {
25157                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
25158                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
25159                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
25160                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
25161                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
25162                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
25163                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
25164                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
25165                 uint32_t             : 2;
25166             } SQCH0DSC0AR_b;
25167         };
25168 
25169         struct
25170         {
25171             union
25172             {
25173                 union
25174                 {
25175                     __IOM uint16_t SQCH0DSC0AR_L; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register                 */
25176 
25177                     struct
25178                     {
25179                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
25180                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
25181                     } SQCH0DSC0AR_L_b;
25182                 };
25183 
25184                 struct
25185                 {
25186                     union
25187                     {
25188                         __IOM uint8_t SQCH0DSC0AR_LL; /*!< (@ 0x00000780) Sequence Channel 0 Descriptor-0 A Register                 */
25189 
25190                         struct
25191                         {
25192                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
25193                         } SQCH0DSC0AR_LL_b;
25194                     };
25195 
25196                     union
25197                     {
25198                         __IOM uint8_t SQCH0DSC0AR_LH; /*!< (@ 0x00000781) Sequence Channel 0 Descriptor-0 A Register                 */
25199 
25200                         struct
25201                         {
25202                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
25203                         } SQCH0DSC0AR_LH_b;
25204                     };
25205                 };
25206             };
25207 
25208             union
25209             {
25210                 union
25211                 {
25212                     __IOM uint16_t SQCH0DSC0AR_H; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register                 */
25213 
25214                     struct
25215                     {
25216                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
25217                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
25218                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
25219                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
25220                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
25221                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
25222                         uint16_t             : 2;
25223                     } SQCH0DSC0AR_H_b;
25224                 };
25225 
25226                 struct
25227                 {
25228                     union
25229                     {
25230                         __IOM uint8_t SQCH0DSC0AR_HL; /*!< (@ 0x00000782) Sequence Channel 0 Descriptor-0 A Register                 */
25231 
25232                         struct
25233                         {
25234                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
25235                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
25236                         } SQCH0DSC0AR_HL_b;
25237                     };
25238 
25239                     union
25240                     {
25241                         __IOM uint8_t SQCH0DSC0AR_HH; /*!< (@ 0x00000783) Sequence Channel 0 Descriptor-0 A Register                 */
25242 
25243                         struct
25244                         {
25245                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
25246                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
25247                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
25248                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
25249                             uint8_t             : 2;
25250                         } SQCH0DSC0AR_HH_b;
25251                     };
25252                 };
25253             };
25254         };
25255     };
25256 
25257     union
25258     {
25259         __IOM uint32_t SQCH0DSC0BR;    /*!< (@ 0x00000784) Sequence Channel 0 Descriptor-0 B Register                 */
25260 
25261         struct
25262         {
25263             uint32_t             : 24;
25264             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
25265             uint32_t             : 6;
25266         } SQCH0DSC0BR_b;
25267     };
25268 
25269     union
25270     {
25271         union
25272         {
25273             __IOM uint32_t SQCH0DSC0CR;     /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register                 */
25274 
25275             struct
25276             {
25277                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
25278                 uint32_t               : 21;
25279                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
25280                 uint32_t               : 1;
25281                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
25282             } SQCH0DSC0CR_b;
25283         };
25284 
25285         struct
25286         {
25287             union
25288             {
25289                 union
25290                 {
25291                     __IOM uint16_t SQCH0DSC0CR_L;  /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register                 */
25292 
25293                     struct
25294                     {
25295                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
25296                         uint16_t              : 15;
25297                     } SQCH0DSC0CR_L_b;
25298                 };
25299 
25300                 union
25301                 {
25302                     __IOM uint8_t SQCH0DSC0CR_LL; /*!< (@ 0x00000788) Sequence Channel 0 Descriptor-0 C Register                 */
25303 
25304                     struct
25305                     {
25306                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
25307                         uint8_t              : 7;
25308                     } SQCH0DSC0CR_LL_b;
25309                 };
25310             };
25311 
25312             union
25313             {
25314                 union
25315                 {
25316                     __IOM uint16_t SQCH0DSC0CR_H; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register                 */
25317 
25318                     struct
25319                     {
25320                         uint16_t               : 6;
25321                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
25322                         uint16_t               : 1;
25323                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
25324                     } SQCH0DSC0CR_H_b;
25325                 };
25326 
25327                 struct
25328                 {
25329                     union
25330                     {
25331                         __IOM uint8_t SQCH0DSC0CR_HL; /*!< (@ 0x0000078A) Sequence Channel 0 Descriptor-0 C Register                 */
25332 
25333                         struct
25334                         {
25335                             uint8_t             : 6;
25336                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
25337                             uint8_t             : 1;
25338                         } SQCH0DSC0CR_HL_b;
25339                     };
25340 
25341                     union
25342                     {
25343                         __IOM uint8_t SQCH0DSC0CR_HH;  /*!< (@ 0x0000078B) Sequence Channel 0 Descriptor-0 C Register                 */
25344 
25345                         struct
25346                         {
25347                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
25348                         } SQCH0DSC0CR_HH_b;
25349                     };
25350                 };
25351             };
25352         };
25353     };
25354 
25355     union
25356     {
25357         union
25358         {
25359             __IOM uint32_t SQCH0DSC0DR;    /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register                 */
25360 
25361             struct
25362             {
25363                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
25364             } SQCH0DSC0DR_b;
25365         };
25366 
25367         struct
25368         {
25369             union
25370             {
25371                 union
25372                 {
25373                     __IOM uint16_t SQCH0DSC0DR_L;  /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register                 */
25374 
25375                     struct
25376                     {
25377                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
25378                     } SQCH0DSC0DR_L_b;
25379                 };
25380 
25381                 struct
25382                 {
25383                     union
25384                     {
25385                         __IOM uint8_t SQCH0DSC0DR_LL; /*!< (@ 0x0000078C) Sequence Channel 0 Descriptor-0 D Register                 */
25386 
25387                         struct
25388                         {
25389                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25390                         } SQCH0DSC0DR_LL_b;
25391                     };
25392 
25393                     union
25394                     {
25395                         __IOM uint8_t SQCH0DSC0DR_LH; /*!< (@ 0x0000078D) Sequence Channel 0 Descriptor-0 D Register                 */
25396 
25397                         struct
25398                         {
25399                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25400                         } SQCH0DSC0DR_LH_b;
25401                     };
25402                 };
25403             };
25404 
25405             union
25406             {
25407                 union
25408                 {
25409                     __IOM uint16_t SQCH0DSC0DR_H;  /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register                 */
25410 
25411                     struct
25412                     {
25413                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
25414                     } SQCH0DSC0DR_H_b;
25415                 };
25416 
25417                 struct
25418                 {
25419                     union
25420                     {
25421                         __IOM uint8_t SQCH0DSC0DR_HL; /*!< (@ 0x0000078E) Sequence Channel 0 Descriptor-0 D Register                 */
25422 
25423                         struct
25424                         {
25425                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25426                         } SQCH0DSC0DR_HL_b;
25427                     };
25428 
25429                     union
25430                     {
25431                         __IOM uint8_t SQCH0DSC0DR_HH; /*!< (@ 0x0000078F) Sequence Channel 0 Descriptor-0 D Register                 */
25432 
25433                         struct
25434                         {
25435                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25436                         } SQCH0DSC0DR_HH_b;
25437                     };
25438                 };
25439             };
25440         };
25441     };
25442 
25443     union
25444     {
25445         union
25446         {
25447             __IOM uint32_t SQCH0DSC1AR;   /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register                 */
25448 
25449             struct
25450             {
25451                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
25452                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
25453                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
25454                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
25455                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
25456                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
25457                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
25458                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
25459                 uint32_t             : 2;
25460             } SQCH0DSC1AR_b;
25461         };
25462 
25463         struct
25464         {
25465             union
25466             {
25467                 union
25468                 {
25469                     __IOM uint16_t SQCH0DSC1AR_L; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register                 */
25470 
25471                     struct
25472                     {
25473                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
25474                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
25475                     } SQCH0DSC1AR_L_b;
25476                 };
25477 
25478                 struct
25479                 {
25480                     union
25481                     {
25482                         __IOM uint8_t SQCH0DSC1AR_LL; /*!< (@ 0x00000790) Sequence Channel 0 Descriptor-1 A Register                 */
25483 
25484                         struct
25485                         {
25486                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
25487                         } SQCH0DSC1AR_LL_b;
25488                     };
25489 
25490                     union
25491                     {
25492                         __IOM uint8_t SQCH0DSC1AR_LH; /*!< (@ 0x00000791) Sequence Channel 0 Descriptor-1 A Register                 */
25493 
25494                         struct
25495                         {
25496                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
25497                         } SQCH0DSC1AR_LH_b;
25498                     };
25499                 };
25500             };
25501 
25502             union
25503             {
25504                 union
25505                 {
25506                     __IOM uint16_t SQCH0DSC1AR_H; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register                 */
25507 
25508                     struct
25509                     {
25510                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
25511                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
25512                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
25513                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
25514                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
25515                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
25516                         uint16_t             : 2;
25517                     } SQCH0DSC1AR_H_b;
25518                 };
25519 
25520                 struct
25521                 {
25522                     union
25523                     {
25524                         __IOM uint8_t SQCH0DSC1AR_HL; /*!< (@ 0x00000792) Sequence Channel 0 Descriptor-1 A Register                 */
25525 
25526                         struct
25527                         {
25528                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
25529                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
25530                         } SQCH0DSC1AR_HL_b;
25531                     };
25532 
25533                     union
25534                     {
25535                         __IOM uint8_t SQCH0DSC1AR_HH; /*!< (@ 0x00000793) Sequence Channel 0 Descriptor-1 A Register                 */
25536 
25537                         struct
25538                         {
25539                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
25540                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
25541                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
25542                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
25543                             uint8_t             : 2;
25544                         } SQCH0DSC1AR_HH_b;
25545                     };
25546                 };
25547             };
25548         };
25549     };
25550 
25551     union
25552     {
25553         __IOM uint32_t SQCH0DSC1BR;    /*!< (@ 0x00000794) Sequence Channel 0 Descriptor-1 B Register                 */
25554 
25555         struct
25556         {
25557             uint32_t             : 24;
25558             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
25559             uint32_t             : 6;
25560         } SQCH0DSC1BR_b;
25561     };
25562 
25563     union
25564     {
25565         union
25566         {
25567             __IOM uint32_t SQCH0DSC1CR;     /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register                 */
25568 
25569             struct
25570             {
25571                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
25572                 uint32_t               : 21;
25573                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
25574                 uint32_t               : 1;
25575                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
25576             } SQCH0DSC1CR_b;
25577         };
25578 
25579         struct
25580         {
25581             union
25582             {
25583                 union
25584                 {
25585                     __IOM uint16_t SQCH0DSC1CR_L;  /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register                 */
25586 
25587                     struct
25588                     {
25589                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
25590                         uint16_t              : 15;
25591                     } SQCH0DSC1CR_L_b;
25592                 };
25593 
25594                 union
25595                 {
25596                     __IOM uint8_t SQCH0DSC1CR_LL; /*!< (@ 0x00000798) Sequence Channel 0 Descriptor-1 C Register                 */
25597 
25598                     struct
25599                     {
25600                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
25601                         uint8_t              : 7;
25602                     } SQCH0DSC1CR_LL_b;
25603                 };
25604             };
25605 
25606             union
25607             {
25608                 union
25609                 {
25610                     __IOM uint16_t SQCH0DSC1CR_H; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register                 */
25611 
25612                     struct
25613                     {
25614                         uint16_t               : 6;
25615                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
25616                         uint16_t               : 1;
25617                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
25618                     } SQCH0DSC1CR_H_b;
25619                 };
25620 
25621                 struct
25622                 {
25623                     union
25624                     {
25625                         __IOM uint8_t SQCH0DSC1CR_HL; /*!< (@ 0x0000079A) Sequence Channel 0 Descriptor-1 C Register                 */
25626 
25627                         struct
25628                         {
25629                             uint8_t             : 6;
25630                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
25631                             uint8_t             : 1;
25632                         } SQCH0DSC1CR_HL_b;
25633                     };
25634 
25635                     union
25636                     {
25637                         __IOM uint8_t SQCH0DSC1CR_HH;  /*!< (@ 0x0000079B) Sequence Channel 0 Descriptor-1 C Register                 */
25638 
25639                         struct
25640                         {
25641                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
25642                         } SQCH0DSC1CR_HH_b;
25643                     };
25644                 };
25645             };
25646         };
25647     };
25648 
25649     union
25650     {
25651         union
25652         {
25653             __IOM uint32_t SQCH0DSC1DR;    /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register                 */
25654 
25655             struct
25656             {
25657                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
25658             } SQCH0DSC1DR_b;
25659         };
25660 
25661         struct
25662         {
25663             union
25664             {
25665                 union
25666                 {
25667                     __IOM uint16_t SQCH0DSC1DR_L;  /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register                 */
25668 
25669                     struct
25670                     {
25671                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
25672                     } SQCH0DSC1DR_L_b;
25673                 };
25674 
25675                 struct
25676                 {
25677                     union
25678                     {
25679                         __IOM uint8_t SQCH0DSC1DR_LL; /*!< (@ 0x0000079C) Sequence Channel 0 Descriptor-1 D Register                 */
25680 
25681                         struct
25682                         {
25683                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25684                         } SQCH0DSC1DR_LL_b;
25685                     };
25686 
25687                     union
25688                     {
25689                         __IOM uint8_t SQCH0DSC1DR_LH; /*!< (@ 0x0000079D) Sequence Channel 0 Descriptor-1 D Register                 */
25690 
25691                         struct
25692                         {
25693                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25694                         } SQCH0DSC1DR_LH_b;
25695                     };
25696                 };
25697             };
25698 
25699             union
25700             {
25701                 union
25702                 {
25703                     __IOM uint16_t SQCH0DSC1DR_H;  /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register                 */
25704 
25705                     struct
25706                     {
25707                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
25708                     } SQCH0DSC1DR_H_b;
25709                 };
25710 
25711                 struct
25712                 {
25713                     union
25714                     {
25715                         __IOM uint8_t SQCH0DSC1DR_HL; /*!< (@ 0x0000079E) Sequence Channel 0 Descriptor-1 D Register                 */
25716 
25717                         struct
25718                         {
25719                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25720                         } SQCH0DSC1DR_HL_b;
25721                     };
25722 
25723                     union
25724                     {
25725                         __IOM uint8_t SQCH0DSC1DR_HH; /*!< (@ 0x0000079F) Sequence Channel 0 Descriptor-1 D Register                 */
25726 
25727                         struct
25728                         {
25729                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25730                         } SQCH0DSC1DR_HH_b;
25731                     };
25732                 };
25733             };
25734         };
25735     };
25736 
25737     union
25738     {
25739         union
25740         {
25741             __IOM uint32_t SQCH0DSC2AR;   /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register                 */
25742 
25743             struct
25744             {
25745                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
25746                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
25747                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
25748                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
25749                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
25750                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
25751                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
25752                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
25753                 uint32_t             : 2;
25754             } SQCH0DSC2AR_b;
25755         };
25756 
25757         struct
25758         {
25759             union
25760             {
25761                 union
25762                 {
25763                     __IOM uint16_t SQCH0DSC2AR_L; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register                 */
25764 
25765                     struct
25766                     {
25767                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
25768                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
25769                     } SQCH0DSC2AR_L_b;
25770                 };
25771 
25772                 struct
25773                 {
25774                     union
25775                     {
25776                         __IOM uint8_t SQCH0DSC2AR_LL; /*!< (@ 0x000007A0) Sequence Channel 0 Descriptor-2 A Register                 */
25777 
25778                         struct
25779                         {
25780                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
25781                         } SQCH0DSC2AR_LL_b;
25782                     };
25783 
25784                     union
25785                     {
25786                         __IOM uint8_t SQCH0DSC2AR_LH; /*!< (@ 0x000007A1) Sequence Channel 0 Descriptor-2 A Register                 */
25787 
25788                         struct
25789                         {
25790                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
25791                         } SQCH0DSC2AR_LH_b;
25792                     };
25793                 };
25794             };
25795 
25796             union
25797             {
25798                 union
25799                 {
25800                     __IOM uint16_t SQCH0DSC2AR_H; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register                 */
25801 
25802                     struct
25803                     {
25804                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
25805                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
25806                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
25807                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
25808                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
25809                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
25810                         uint16_t             : 2;
25811                     } SQCH0DSC2AR_H_b;
25812                 };
25813 
25814                 struct
25815                 {
25816                     union
25817                     {
25818                         __IOM uint8_t SQCH0DSC2AR_HL; /*!< (@ 0x000007A2) Sequence Channel 0 Descriptor-2 A Register                 */
25819 
25820                         struct
25821                         {
25822                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
25823                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
25824                         } SQCH0DSC2AR_HL_b;
25825                     };
25826 
25827                     union
25828                     {
25829                         __IOM uint8_t SQCH0DSC2AR_HH; /*!< (@ 0x000007A3) Sequence Channel 0 Descriptor-2 A Register                 */
25830 
25831                         struct
25832                         {
25833                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
25834                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
25835                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
25836                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
25837                             uint8_t             : 2;
25838                         } SQCH0DSC2AR_HH_b;
25839                     };
25840                 };
25841             };
25842         };
25843     };
25844 
25845     union
25846     {
25847         __IOM uint32_t SQCH0DSC2BR;    /*!< (@ 0x000007A4) Sequence Channel 0 Descriptor-2 B Register                 */
25848 
25849         struct
25850         {
25851             uint32_t             : 24;
25852             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
25853             uint32_t             : 6;
25854         } SQCH0DSC2BR_b;
25855     };
25856 
25857     union
25858     {
25859         union
25860         {
25861             __IOM uint32_t SQCH0DSC2CR;     /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register                 */
25862 
25863             struct
25864             {
25865                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
25866                 uint32_t               : 21;
25867                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
25868                 uint32_t               : 1;
25869                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
25870             } SQCH0DSC2CR_b;
25871         };
25872 
25873         struct
25874         {
25875             union
25876             {
25877                 union
25878                 {
25879                     __IOM uint16_t SQCH0DSC2CR_L;  /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register                 */
25880 
25881                     struct
25882                     {
25883                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
25884                         uint16_t              : 15;
25885                     } SQCH0DSC2CR_L_b;
25886                 };
25887 
25888                 union
25889                 {
25890                     __IOM uint8_t SQCH0DSC2CR_LL; /*!< (@ 0x000007A8) Sequence Channel 0 Descriptor-2 C Register                 */
25891 
25892                     struct
25893                     {
25894                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
25895                         uint8_t              : 7;
25896                     } SQCH0DSC2CR_LL_b;
25897                 };
25898             };
25899 
25900             union
25901             {
25902                 union
25903                 {
25904                     __IOM uint16_t SQCH0DSC2CR_H; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register                 */
25905 
25906                     struct
25907                     {
25908                         uint16_t               : 6;
25909                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
25910                         uint16_t               : 1;
25911                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
25912                     } SQCH0DSC2CR_H_b;
25913                 };
25914 
25915                 struct
25916                 {
25917                     union
25918                     {
25919                         __IOM uint8_t SQCH0DSC2CR_HL; /*!< (@ 0x000007AA) Sequence Channel 0 Descriptor-2 C Register                 */
25920 
25921                         struct
25922                         {
25923                             uint8_t             : 6;
25924                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
25925                             uint8_t             : 1;
25926                         } SQCH0DSC2CR_HL_b;
25927                     };
25928 
25929                     union
25930                     {
25931                         __IOM uint8_t SQCH0DSC2CR_HH;  /*!< (@ 0x000007AB) Sequence Channel 0 Descriptor-2 C Register                 */
25932 
25933                         struct
25934                         {
25935                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
25936                         } SQCH0DSC2CR_HH_b;
25937                     };
25938                 };
25939             };
25940         };
25941     };
25942 
25943     union
25944     {
25945         union
25946         {
25947             __IOM uint32_t SQCH0DSC2DR;    /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register                 */
25948 
25949             struct
25950             {
25951                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
25952             } SQCH0DSC2DR_b;
25953         };
25954 
25955         struct
25956         {
25957             union
25958             {
25959                 union
25960                 {
25961                     __IOM uint16_t SQCH0DSC2DR_L;  /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register                 */
25962 
25963                     struct
25964                     {
25965                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
25966                     } SQCH0DSC2DR_L_b;
25967                 };
25968 
25969                 struct
25970                 {
25971                     union
25972                     {
25973                         __IOM uint8_t SQCH0DSC2DR_LL; /*!< (@ 0x000007AC) Sequence Channel 0 Descriptor-2 D Register                 */
25974 
25975                         struct
25976                         {
25977                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25978                         } SQCH0DSC2DR_LL_b;
25979                     };
25980 
25981                     union
25982                     {
25983                         __IOM uint8_t SQCH0DSC2DR_LH; /*!< (@ 0x000007AD) Sequence Channel 0 Descriptor-2 D Register                 */
25984 
25985                         struct
25986                         {
25987                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
25988                         } SQCH0DSC2DR_LH_b;
25989                     };
25990                 };
25991             };
25992 
25993             union
25994             {
25995                 union
25996                 {
25997                     __IOM uint16_t SQCH0DSC2DR_H;  /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register                 */
25998 
25999                     struct
26000                     {
26001                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
26002                     } SQCH0DSC2DR_H_b;
26003                 };
26004 
26005                 struct
26006                 {
26007                     union
26008                     {
26009                         __IOM uint8_t SQCH0DSC2DR_HL; /*!< (@ 0x000007AE) Sequence Channel 0 Descriptor-2 D Register                 */
26010 
26011                         struct
26012                         {
26013                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26014                         } SQCH0DSC2DR_HL_b;
26015                     };
26016 
26017                     union
26018                     {
26019                         __IOM uint8_t SQCH0DSC2DR_HH; /*!< (@ 0x000007AF) Sequence Channel 0 Descriptor-2 D Register                 */
26020 
26021                         struct
26022                         {
26023                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26024                         } SQCH0DSC2DR_HH_b;
26025                     };
26026                 };
26027             };
26028         };
26029     };
26030 
26031     union
26032     {
26033         union
26034         {
26035             __IOM uint32_t SQCH0DSC3AR;   /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register                 */
26036 
26037             struct
26038             {
26039                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
26040                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
26041                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
26042                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
26043                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
26044                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
26045                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
26046                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
26047                 uint32_t             : 2;
26048             } SQCH0DSC3AR_b;
26049         };
26050 
26051         struct
26052         {
26053             union
26054             {
26055                 union
26056                 {
26057                     __IOM uint16_t SQCH0DSC3AR_L; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register                 */
26058 
26059                     struct
26060                     {
26061                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
26062                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
26063                     } SQCH0DSC3AR_L_b;
26064                 };
26065 
26066                 struct
26067                 {
26068                     union
26069                     {
26070                         __IOM uint8_t SQCH0DSC3AR_LL; /*!< (@ 0x000007B0) Sequence Channel 0 Descriptor-3 A Register                 */
26071 
26072                         struct
26073                         {
26074                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
26075                         } SQCH0DSC3AR_LL_b;
26076                     };
26077 
26078                     union
26079                     {
26080                         __IOM uint8_t SQCH0DSC3AR_LH; /*!< (@ 0x000007B1) Sequence Channel 0 Descriptor-3 A Register                 */
26081 
26082                         struct
26083                         {
26084                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
26085                         } SQCH0DSC3AR_LH_b;
26086                     };
26087                 };
26088             };
26089 
26090             union
26091             {
26092                 union
26093                 {
26094                     __IOM uint16_t SQCH0DSC3AR_H; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register                 */
26095 
26096                     struct
26097                     {
26098                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
26099                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
26100                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
26101                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
26102                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
26103                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
26104                         uint16_t             : 2;
26105                     } SQCH0DSC3AR_H_b;
26106                 };
26107 
26108                 struct
26109                 {
26110                     union
26111                     {
26112                         __IOM uint8_t SQCH0DSC3AR_HL; /*!< (@ 0x000007B2) Sequence Channel 0 Descriptor-3 A Register                 */
26113 
26114                         struct
26115                         {
26116                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
26117                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
26118                         } SQCH0DSC3AR_HL_b;
26119                     };
26120 
26121                     union
26122                     {
26123                         __IOM uint8_t SQCH0DSC3AR_HH; /*!< (@ 0x000007B3) Sequence Channel 0 Descriptor-3 A Register                 */
26124 
26125                         struct
26126                         {
26127                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
26128                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
26129                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
26130                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
26131                             uint8_t             : 2;
26132                         } SQCH0DSC3AR_HH_b;
26133                     };
26134                 };
26135             };
26136         };
26137     };
26138 
26139     union
26140     {
26141         __IOM uint32_t SQCH0DSC3BR;    /*!< (@ 0x000007B4) Sequence Channel 0 Descriptor-3 B Register                 */
26142 
26143         struct
26144         {
26145             uint32_t             : 24;
26146             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
26147             uint32_t             : 6;
26148         } SQCH0DSC3BR_b;
26149     };
26150 
26151     union
26152     {
26153         union
26154         {
26155             __IOM uint32_t SQCH0DSC3CR;     /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register                 */
26156 
26157             struct
26158             {
26159                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
26160                 uint32_t               : 21;
26161                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
26162                 uint32_t               : 1;
26163                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
26164             } SQCH0DSC3CR_b;
26165         };
26166 
26167         struct
26168         {
26169             union
26170             {
26171                 union
26172                 {
26173                     __IOM uint16_t SQCH0DSC3CR_L;  /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register                 */
26174 
26175                     struct
26176                     {
26177                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
26178                         uint16_t              : 15;
26179                     } SQCH0DSC3CR_L_b;
26180                 };
26181 
26182                 union
26183                 {
26184                     __IOM uint8_t SQCH0DSC3CR_LL; /*!< (@ 0x000007B8) Sequence Channel 0 Descriptor-3 C Register                 */
26185 
26186                     struct
26187                     {
26188                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
26189                         uint8_t              : 7;
26190                     } SQCH0DSC3CR_LL_b;
26191                 };
26192             };
26193 
26194             union
26195             {
26196                 union
26197                 {
26198                     __IOM uint16_t SQCH0DSC3CR_H; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register                 */
26199 
26200                     struct
26201                     {
26202                         uint16_t               : 6;
26203                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
26204                         uint16_t               : 1;
26205                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
26206                     } SQCH0DSC3CR_H_b;
26207                 };
26208 
26209                 struct
26210                 {
26211                     union
26212                     {
26213                         __IOM uint8_t SQCH0DSC3CR_HL; /*!< (@ 0x000007BA) Sequence Channel 0 Descriptor-3 C Register                 */
26214 
26215                         struct
26216                         {
26217                             uint8_t             : 6;
26218                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
26219                             uint8_t             : 1;
26220                         } SQCH0DSC3CR_HL_b;
26221                     };
26222 
26223                     union
26224                     {
26225                         __IOM uint8_t SQCH0DSC3CR_HH;  /*!< (@ 0x000007BB) Sequence Channel 0 Descriptor-3 C Register                 */
26226 
26227                         struct
26228                         {
26229                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
26230                         } SQCH0DSC3CR_HH_b;
26231                     };
26232                 };
26233             };
26234         };
26235     };
26236 
26237     union
26238     {
26239         union
26240         {
26241             __IOM uint32_t SQCH0DSC3DR;    /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register                 */
26242 
26243             struct
26244             {
26245                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
26246             } SQCH0DSC3DR_b;
26247         };
26248 
26249         struct
26250         {
26251             union
26252             {
26253                 union
26254                 {
26255                     __IOM uint16_t SQCH0DSC3DR_L;  /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register                 */
26256 
26257                     struct
26258                     {
26259                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
26260                     } SQCH0DSC3DR_L_b;
26261                 };
26262 
26263                 struct
26264                 {
26265                     union
26266                     {
26267                         __IOM uint8_t SQCH0DSC3DR_LL; /*!< (@ 0x000007BC) Sequence Channel 0 Descriptor-3 D Register                 */
26268 
26269                         struct
26270                         {
26271                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26272                         } SQCH0DSC3DR_LL_b;
26273                     };
26274 
26275                     union
26276                     {
26277                         __IOM uint8_t SQCH0DSC3DR_LH; /*!< (@ 0x000007BD) Sequence Channel 0 Descriptor-3 D Register                 */
26278 
26279                         struct
26280                         {
26281                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26282                         } SQCH0DSC3DR_LH_b;
26283                     };
26284                 };
26285             };
26286 
26287             union
26288             {
26289                 union
26290                 {
26291                     __IOM uint16_t SQCH0DSC3DR_H;  /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register                 */
26292 
26293                     struct
26294                     {
26295                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
26296                     } SQCH0DSC3DR_H_b;
26297                 };
26298 
26299                 struct
26300                 {
26301                     union
26302                     {
26303                         __IOM uint8_t SQCH0DSC3DR_HL; /*!< (@ 0x000007BE) Sequence Channel 0 Descriptor-3 D Register                 */
26304 
26305                         struct
26306                         {
26307                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26308                         } SQCH0DSC3DR_HL_b;
26309                     };
26310 
26311                     union
26312                     {
26313                         __IOM uint8_t SQCH0DSC3DR_HH; /*!< (@ 0x000007BF) Sequence Channel 0 Descriptor-3 D Register                 */
26314 
26315                         struct
26316                         {
26317                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26318                         } SQCH0DSC3DR_HH_b;
26319                     };
26320                 };
26321             };
26322         };
26323     };
26324 
26325     union
26326     {
26327         union
26328         {
26329             __IOM uint32_t SQCH0DSC4AR;   /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register                 */
26330 
26331             struct
26332             {
26333                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
26334                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
26335                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
26336                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
26337                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
26338                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
26339                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
26340                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
26341                 uint32_t             : 2;
26342             } SQCH0DSC4AR_b;
26343         };
26344 
26345         struct
26346         {
26347             union
26348             {
26349                 union
26350                 {
26351                     __IOM uint16_t SQCH0DSC4AR_L; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register                 */
26352 
26353                     struct
26354                     {
26355                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
26356                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
26357                     } SQCH0DSC4AR_L_b;
26358                 };
26359 
26360                 struct
26361                 {
26362                     union
26363                     {
26364                         __IOM uint8_t SQCH0DSC4AR_LL; /*!< (@ 0x000007C0) Sequence Channel 0 Descriptor-4 A Register                 */
26365 
26366                         struct
26367                         {
26368                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
26369                         } SQCH0DSC4AR_LL_b;
26370                     };
26371 
26372                     union
26373                     {
26374                         __IOM uint8_t SQCH0DSC4AR_LH; /*!< (@ 0x000007C1) Sequence Channel 0 Descriptor-4 A Register                 */
26375 
26376                         struct
26377                         {
26378                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
26379                         } SQCH0DSC4AR_LH_b;
26380                     };
26381                 };
26382             };
26383 
26384             union
26385             {
26386                 union
26387                 {
26388                     __IOM uint16_t SQCH0DSC4AR_H; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register                 */
26389 
26390                     struct
26391                     {
26392                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
26393                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
26394                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
26395                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
26396                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
26397                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
26398                         uint16_t             : 2;
26399                     } SQCH0DSC4AR_H_b;
26400                 };
26401 
26402                 struct
26403                 {
26404                     union
26405                     {
26406                         __IOM uint8_t SQCH0DSC4AR_HL; /*!< (@ 0x000007C2) Sequence Channel 0 Descriptor-4 A Register                 */
26407 
26408                         struct
26409                         {
26410                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
26411                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
26412                         } SQCH0DSC4AR_HL_b;
26413                     };
26414 
26415                     union
26416                     {
26417                         __IOM uint8_t SQCH0DSC4AR_HH; /*!< (@ 0x000007C3) Sequence Channel 0 Descriptor-4 A Register                 */
26418 
26419                         struct
26420                         {
26421                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
26422                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
26423                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
26424                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
26425                             uint8_t             : 2;
26426                         } SQCH0DSC4AR_HH_b;
26427                     };
26428                 };
26429             };
26430         };
26431     };
26432 
26433     union
26434     {
26435         __IOM uint32_t SQCH0DSC4BR;    /*!< (@ 0x000007C4) Sequence Channel 0 Descriptor-4 B Register                 */
26436 
26437         struct
26438         {
26439             uint32_t             : 24;
26440             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
26441             uint32_t             : 6;
26442         } SQCH0DSC4BR_b;
26443     };
26444 
26445     union
26446     {
26447         union
26448         {
26449             __IOM uint32_t SQCH0DSC4CR;     /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register                 */
26450 
26451             struct
26452             {
26453                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
26454                 uint32_t               : 21;
26455                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
26456                 uint32_t               : 1;
26457                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
26458             } SQCH0DSC4CR_b;
26459         };
26460 
26461         struct
26462         {
26463             union
26464             {
26465                 union
26466                 {
26467                     __IOM uint16_t SQCH0DSC4CR_L;  /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register                 */
26468 
26469                     struct
26470                     {
26471                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
26472                         uint16_t              : 15;
26473                     } SQCH0DSC4CR_L_b;
26474                 };
26475 
26476                 union
26477                 {
26478                     __IOM uint8_t SQCH0DSC4CR_LL; /*!< (@ 0x000007C8) Sequence Channel 0 Descriptor-4 C Register                 */
26479 
26480                     struct
26481                     {
26482                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
26483                         uint8_t              : 7;
26484                     } SQCH0DSC4CR_LL_b;
26485                 };
26486             };
26487 
26488             union
26489             {
26490                 union
26491                 {
26492                     __IOM uint16_t SQCH0DSC4CR_H; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register                 */
26493 
26494                     struct
26495                     {
26496                         uint16_t               : 6;
26497                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
26498                         uint16_t               : 1;
26499                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
26500                     } SQCH0DSC4CR_H_b;
26501                 };
26502 
26503                 struct
26504                 {
26505                     union
26506                     {
26507                         __IOM uint8_t SQCH0DSC4CR_HL; /*!< (@ 0x000007CA) Sequence Channel 0 Descriptor-4 C Register                 */
26508 
26509                         struct
26510                         {
26511                             uint8_t             : 6;
26512                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
26513                             uint8_t             : 1;
26514                         } SQCH0DSC4CR_HL_b;
26515                     };
26516 
26517                     union
26518                     {
26519                         __IOM uint8_t SQCH0DSC4CR_HH;  /*!< (@ 0x000007CB) Sequence Channel 0 Descriptor-4 C Register                 */
26520 
26521                         struct
26522                         {
26523                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
26524                         } SQCH0DSC4CR_HH_b;
26525                     };
26526                 };
26527             };
26528         };
26529     };
26530 
26531     union
26532     {
26533         union
26534         {
26535             __IOM uint32_t SQCH0DSC4DR;    /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register                 */
26536 
26537             struct
26538             {
26539                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
26540             } SQCH0DSC4DR_b;
26541         };
26542 
26543         struct
26544         {
26545             union
26546             {
26547                 union
26548                 {
26549                     __IOM uint16_t SQCH0DSC4DR_L;  /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register                 */
26550 
26551                     struct
26552                     {
26553                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
26554                     } SQCH0DSC4DR_L_b;
26555                 };
26556 
26557                 struct
26558                 {
26559                     union
26560                     {
26561                         __IOM uint8_t SQCH0DSC4DR_LL; /*!< (@ 0x000007CC) Sequence Channel 0 Descriptor-4 D Register                 */
26562 
26563                         struct
26564                         {
26565                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26566                         } SQCH0DSC4DR_LL_b;
26567                     };
26568 
26569                     union
26570                     {
26571                         __IOM uint8_t SQCH0DSC4DR_LH; /*!< (@ 0x000007CD) Sequence Channel 0 Descriptor-4 D Register                 */
26572 
26573                         struct
26574                         {
26575                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26576                         } SQCH0DSC4DR_LH_b;
26577                     };
26578                 };
26579             };
26580 
26581             union
26582             {
26583                 union
26584                 {
26585                     __IOM uint16_t SQCH0DSC4DR_H;  /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register                 */
26586 
26587                     struct
26588                     {
26589                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
26590                     } SQCH0DSC4DR_H_b;
26591                 };
26592 
26593                 struct
26594                 {
26595                     union
26596                     {
26597                         __IOM uint8_t SQCH0DSC4DR_HL; /*!< (@ 0x000007CE) Sequence Channel 0 Descriptor-4 D Register                 */
26598 
26599                         struct
26600                         {
26601                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26602                         } SQCH0DSC4DR_HL_b;
26603                     };
26604 
26605                     union
26606                     {
26607                         __IOM uint8_t SQCH0DSC4DR_HH; /*!< (@ 0x000007CF) Sequence Channel 0 Descriptor-4 D Register                 */
26608 
26609                         struct
26610                         {
26611                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26612                         } SQCH0DSC4DR_HH_b;
26613                     };
26614                 };
26615             };
26616         };
26617     };
26618 
26619     union
26620     {
26621         union
26622         {
26623             __IOM uint32_t SQCH0DSC5AR;   /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register                 */
26624 
26625             struct
26626             {
26627                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
26628                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
26629                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
26630                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
26631                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
26632                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
26633                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
26634                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
26635                 uint32_t             : 2;
26636             } SQCH0DSC5AR_b;
26637         };
26638 
26639         struct
26640         {
26641             union
26642             {
26643                 union
26644                 {
26645                     __IOM uint16_t SQCH0DSC5AR_L; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register                 */
26646 
26647                     struct
26648                     {
26649                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
26650                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
26651                     } SQCH0DSC5AR_L_b;
26652                 };
26653 
26654                 struct
26655                 {
26656                     union
26657                     {
26658                         __IOM uint8_t SQCH0DSC5AR_LL; /*!< (@ 0x000007D0) Sequence Channel 0 Descriptor-5 A Register                 */
26659 
26660                         struct
26661                         {
26662                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
26663                         } SQCH0DSC5AR_LL_b;
26664                     };
26665 
26666                     union
26667                     {
26668                         __IOM uint8_t SQCH0DSC5AR_LH; /*!< (@ 0x000007D1) Sequence Channel 0 Descriptor-5 A Register                 */
26669 
26670                         struct
26671                         {
26672                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
26673                         } SQCH0DSC5AR_LH_b;
26674                     };
26675                 };
26676             };
26677 
26678             union
26679             {
26680                 union
26681                 {
26682                     __IOM uint16_t SQCH0DSC5AR_H; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register                 */
26683 
26684                     struct
26685                     {
26686                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
26687                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
26688                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
26689                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
26690                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
26691                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
26692                         uint16_t             : 2;
26693                     } SQCH0DSC5AR_H_b;
26694                 };
26695 
26696                 struct
26697                 {
26698                     union
26699                     {
26700                         __IOM uint8_t SQCH0DSC5AR_HL; /*!< (@ 0x000007D2) Sequence Channel 0 Descriptor-5 A Register                 */
26701 
26702                         struct
26703                         {
26704                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
26705                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
26706                         } SQCH0DSC5AR_HL_b;
26707                     };
26708 
26709                     union
26710                     {
26711                         __IOM uint8_t SQCH0DSC5AR_HH; /*!< (@ 0x000007D3) Sequence Channel 0 Descriptor-5 A Register                 */
26712 
26713                         struct
26714                         {
26715                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
26716                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
26717                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
26718                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
26719                             uint8_t             : 2;
26720                         } SQCH0DSC5AR_HH_b;
26721                     };
26722                 };
26723             };
26724         };
26725     };
26726 
26727     union
26728     {
26729         __IOM uint32_t SQCH0DSC5BR;    /*!< (@ 0x000007D4) Sequence Channel 0 Descriptor-5 B Register                 */
26730 
26731         struct
26732         {
26733             uint32_t             : 24;
26734             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
26735             uint32_t             : 6;
26736         } SQCH0DSC5BR_b;
26737     };
26738 
26739     union
26740     {
26741         union
26742         {
26743             __IOM uint32_t SQCH0DSC5CR;     /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register                 */
26744 
26745             struct
26746             {
26747                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
26748                 uint32_t               : 21;
26749                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
26750                 uint32_t               : 1;
26751                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
26752             } SQCH0DSC5CR_b;
26753         };
26754 
26755         struct
26756         {
26757             union
26758             {
26759                 union
26760                 {
26761                     __IOM uint16_t SQCH0DSC5CR_L;  /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register                 */
26762 
26763                     struct
26764                     {
26765                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
26766                         uint16_t              : 15;
26767                     } SQCH0DSC5CR_L_b;
26768                 };
26769 
26770                 union
26771                 {
26772                     __IOM uint8_t SQCH0DSC5CR_LL; /*!< (@ 0x000007D8) Sequence Channel 0 Descriptor-5 C Register                 */
26773 
26774                     struct
26775                     {
26776                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
26777                         uint8_t              : 7;
26778                     } SQCH0DSC5CR_LL_b;
26779                 };
26780             };
26781 
26782             union
26783             {
26784                 union
26785                 {
26786                     __IOM uint16_t SQCH0DSC5CR_H; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register                 */
26787 
26788                     struct
26789                     {
26790                         uint16_t               : 6;
26791                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
26792                         uint16_t               : 1;
26793                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
26794                     } SQCH0DSC5CR_H_b;
26795                 };
26796 
26797                 struct
26798                 {
26799                     union
26800                     {
26801                         __IOM uint8_t SQCH0DSC5CR_HL; /*!< (@ 0x000007DA) Sequence Channel 0 Descriptor-5 C Register                 */
26802 
26803                         struct
26804                         {
26805                             uint8_t             : 6;
26806                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
26807                             uint8_t             : 1;
26808                         } SQCH0DSC5CR_HL_b;
26809                     };
26810 
26811                     union
26812                     {
26813                         __IOM uint8_t SQCH0DSC5CR_HH;  /*!< (@ 0x000007DB) Sequence Channel 0 Descriptor-5 C Register                 */
26814 
26815                         struct
26816                         {
26817                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
26818                         } SQCH0DSC5CR_HH_b;
26819                     };
26820                 };
26821             };
26822         };
26823     };
26824 
26825     union
26826     {
26827         union
26828         {
26829             __IOM uint32_t SQCH0DSC5DR;    /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register                 */
26830 
26831             struct
26832             {
26833                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
26834             } SQCH0DSC5DR_b;
26835         };
26836 
26837         struct
26838         {
26839             union
26840             {
26841                 union
26842                 {
26843                     __IOM uint16_t SQCH0DSC5DR_L;  /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register                 */
26844 
26845                     struct
26846                     {
26847                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
26848                     } SQCH0DSC5DR_L_b;
26849                 };
26850 
26851                 struct
26852                 {
26853                     union
26854                     {
26855                         __IOM uint8_t SQCH0DSC5DR_LL; /*!< (@ 0x000007DC) Sequence Channel 0 Descriptor-5 D Register                 */
26856 
26857                         struct
26858                         {
26859                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26860                         } SQCH0DSC5DR_LL_b;
26861                     };
26862 
26863                     union
26864                     {
26865                         __IOM uint8_t SQCH0DSC5DR_LH; /*!< (@ 0x000007DD) Sequence Channel 0 Descriptor-5 D Register                 */
26866 
26867                         struct
26868                         {
26869                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26870                         } SQCH0DSC5DR_LH_b;
26871                     };
26872                 };
26873             };
26874 
26875             union
26876             {
26877                 union
26878                 {
26879                     __IOM uint16_t SQCH0DSC5DR_H;  /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register                 */
26880 
26881                     struct
26882                     {
26883                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
26884                     } SQCH0DSC5DR_H_b;
26885                 };
26886 
26887                 struct
26888                 {
26889                     union
26890                     {
26891                         __IOM uint8_t SQCH0DSC5DR_HL; /*!< (@ 0x000007DE) Sequence Channel 0 Descriptor-5 D Register                 */
26892 
26893                         struct
26894                         {
26895                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26896                         } SQCH0DSC5DR_HL_b;
26897                     };
26898 
26899                     union
26900                     {
26901                         __IOM uint8_t SQCH0DSC5DR_HH; /*!< (@ 0x000007DF) Sequence Channel 0 Descriptor-5 D Register                 */
26902 
26903                         struct
26904                         {
26905                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
26906                         } SQCH0DSC5DR_HH_b;
26907                     };
26908                 };
26909             };
26910         };
26911     };
26912 
26913     union
26914     {
26915         union
26916         {
26917             __IOM uint32_t SQCH0DSC6AR;   /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register                 */
26918 
26919             struct
26920             {
26921                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
26922                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
26923                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
26924                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
26925                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
26926                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
26927                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
26928                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
26929                 uint32_t             : 2;
26930             } SQCH0DSC6AR_b;
26931         };
26932 
26933         struct
26934         {
26935             union
26936             {
26937                 union
26938                 {
26939                     __IOM uint16_t SQCH0DSC6AR_L; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register                 */
26940 
26941                     struct
26942                     {
26943                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
26944                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
26945                     } SQCH0DSC6AR_L_b;
26946                 };
26947 
26948                 struct
26949                 {
26950                     union
26951                     {
26952                         __IOM uint8_t SQCH0DSC6AR_LL; /*!< (@ 0x000007E0) Sequence Channel 0 Descriptor-6 A Register                 */
26953 
26954                         struct
26955                         {
26956                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
26957                         } SQCH0DSC6AR_LL_b;
26958                     };
26959 
26960                     union
26961                     {
26962                         __IOM uint8_t SQCH0DSC6AR_LH; /*!< (@ 0x000007E1) Sequence Channel 0 Descriptor-6 A Register                 */
26963 
26964                         struct
26965                         {
26966                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
26967                         } SQCH0DSC6AR_LH_b;
26968                     };
26969                 };
26970             };
26971 
26972             union
26973             {
26974                 union
26975                 {
26976                     __IOM uint16_t SQCH0DSC6AR_H; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register                 */
26977 
26978                     struct
26979                     {
26980                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
26981                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
26982                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
26983                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
26984                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
26985                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
26986                         uint16_t             : 2;
26987                     } SQCH0DSC6AR_H_b;
26988                 };
26989 
26990                 struct
26991                 {
26992                     union
26993                     {
26994                         __IOM uint8_t SQCH0DSC6AR_HL; /*!< (@ 0x000007E2) Sequence Channel 0 Descriptor-6 A Register                 */
26995 
26996                         struct
26997                         {
26998                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
26999                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
27000                         } SQCH0DSC6AR_HL_b;
27001                     };
27002 
27003                     union
27004                     {
27005                         __IOM uint8_t SQCH0DSC6AR_HH; /*!< (@ 0x000007E3) Sequence Channel 0 Descriptor-6 A Register                 */
27006 
27007                         struct
27008                         {
27009                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
27010                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
27011                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
27012                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
27013                             uint8_t             : 2;
27014                         } SQCH0DSC6AR_HH_b;
27015                     };
27016                 };
27017             };
27018         };
27019     };
27020 
27021     union
27022     {
27023         __IOM uint32_t SQCH0DSC6BR;    /*!< (@ 0x000007E4) Sequence Channel 0 Descriptor-6 B Register                 */
27024 
27025         struct
27026         {
27027             uint32_t             : 24;
27028             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
27029             uint32_t             : 6;
27030         } SQCH0DSC6BR_b;
27031     };
27032 
27033     union
27034     {
27035         union
27036         {
27037             __IOM uint32_t SQCH0DSC6CR;     /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register                 */
27038 
27039             struct
27040             {
27041                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
27042                 uint32_t               : 21;
27043                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
27044                 uint32_t               : 1;
27045                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
27046             } SQCH0DSC6CR_b;
27047         };
27048 
27049         struct
27050         {
27051             union
27052             {
27053                 union
27054                 {
27055                     __IOM uint16_t SQCH0DSC6CR_L;  /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register                 */
27056 
27057                     struct
27058                     {
27059                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
27060                         uint16_t              : 15;
27061                     } SQCH0DSC6CR_L_b;
27062                 };
27063 
27064                 union
27065                 {
27066                     __IOM uint8_t SQCH0DSC6CR_LL; /*!< (@ 0x000007E8) Sequence Channel 0 Descriptor-6 C Register                 */
27067 
27068                     struct
27069                     {
27070                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
27071                         uint8_t              : 7;
27072                     } SQCH0DSC6CR_LL_b;
27073                 };
27074             };
27075 
27076             union
27077             {
27078                 union
27079                 {
27080                     __IOM uint16_t SQCH0DSC6CR_H; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register                 */
27081 
27082                     struct
27083                     {
27084                         uint16_t               : 6;
27085                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
27086                         uint16_t               : 1;
27087                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
27088                     } SQCH0DSC6CR_H_b;
27089                 };
27090 
27091                 struct
27092                 {
27093                     union
27094                     {
27095                         __IOM uint8_t SQCH0DSC6CR_HL; /*!< (@ 0x000007EA) Sequence Channel 0 Descriptor-6 C Register                 */
27096 
27097                         struct
27098                         {
27099                             uint8_t             : 6;
27100                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
27101                             uint8_t             : 1;
27102                         } SQCH0DSC6CR_HL_b;
27103                     };
27104 
27105                     union
27106                     {
27107                         __IOM uint8_t SQCH0DSC6CR_HH;  /*!< (@ 0x000007EB) Sequence Channel 0 Descriptor-6 C Register                 */
27108 
27109                         struct
27110                         {
27111                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
27112                         } SQCH0DSC6CR_HH_b;
27113                     };
27114                 };
27115             };
27116         };
27117     };
27118 
27119     union
27120     {
27121         union
27122         {
27123             __IOM uint32_t SQCH0DSC6DR;    /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register                 */
27124 
27125             struct
27126             {
27127                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
27128             } SQCH0DSC6DR_b;
27129         };
27130 
27131         struct
27132         {
27133             union
27134             {
27135                 union
27136                 {
27137                     __IOM uint16_t SQCH0DSC6DR_L;  /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register                 */
27138 
27139                     struct
27140                     {
27141                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
27142                     } SQCH0DSC6DR_L_b;
27143                 };
27144 
27145                 struct
27146                 {
27147                     union
27148                     {
27149                         __IOM uint8_t SQCH0DSC6DR_LL; /*!< (@ 0x000007EC) Sequence Channel 0 Descriptor-6 D Register                 */
27150 
27151                         struct
27152                         {
27153                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27154                         } SQCH0DSC6DR_LL_b;
27155                     };
27156 
27157                     union
27158                     {
27159                         __IOM uint8_t SQCH0DSC6DR_LH; /*!< (@ 0x000007ED) Sequence Channel 0 Descriptor-6 D Register                 */
27160 
27161                         struct
27162                         {
27163                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27164                         } SQCH0DSC6DR_LH_b;
27165                     };
27166                 };
27167             };
27168 
27169             union
27170             {
27171                 union
27172                 {
27173                     __IOM uint16_t SQCH0DSC6DR_H;  /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register                 */
27174 
27175                     struct
27176                     {
27177                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
27178                     } SQCH0DSC6DR_H_b;
27179                 };
27180 
27181                 struct
27182                 {
27183                     union
27184                     {
27185                         __IOM uint8_t SQCH0DSC6DR_HL; /*!< (@ 0x000007EE) Sequence Channel 0 Descriptor-6 D Register                 */
27186 
27187                         struct
27188                         {
27189                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27190                         } SQCH0DSC6DR_HL_b;
27191                     };
27192 
27193                     union
27194                     {
27195                         __IOM uint8_t SQCH0DSC6DR_HH; /*!< (@ 0x000007EF) Sequence Channel 0 Descriptor-6 D Register                 */
27196 
27197                         struct
27198                         {
27199                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27200                         } SQCH0DSC6DR_HH_b;
27201                     };
27202                 };
27203             };
27204         };
27205     };
27206 
27207     union
27208     {
27209         union
27210         {
27211             __IOM uint32_t SQCH0DSC7AR;   /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register                 */
27212 
27213             struct
27214             {
27215                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
27216                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
27217                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
27218                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
27219                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
27220                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
27221                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
27222                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
27223                 uint32_t             : 2;
27224             } SQCH0DSC7AR_b;
27225         };
27226 
27227         struct
27228         {
27229             union
27230             {
27231                 union
27232                 {
27233                     __IOM uint16_t SQCH0DSC7AR_L; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register                 */
27234 
27235                     struct
27236                     {
27237                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
27238                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
27239                     } SQCH0DSC7AR_L_b;
27240                 };
27241 
27242                 struct
27243                 {
27244                     union
27245                     {
27246                         __IOM uint8_t SQCH0DSC7AR_LL; /*!< (@ 0x000007F0) Sequence Channel 0 Descriptor-7 A Register                 */
27247 
27248                         struct
27249                         {
27250                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
27251                         } SQCH0DSC7AR_LL_b;
27252                     };
27253 
27254                     union
27255                     {
27256                         __IOM uint8_t SQCH0DSC7AR_LH; /*!< (@ 0x000007F1) Sequence Channel 0 Descriptor-7 A Register                 */
27257 
27258                         struct
27259                         {
27260                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
27261                         } SQCH0DSC7AR_LH_b;
27262                     };
27263                 };
27264             };
27265 
27266             union
27267             {
27268                 union
27269                 {
27270                     __IOM uint16_t SQCH0DSC7AR_H; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register                 */
27271 
27272                     struct
27273                     {
27274                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
27275                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
27276                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
27277                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
27278                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
27279                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
27280                         uint16_t             : 2;
27281                     } SQCH0DSC7AR_H_b;
27282                 };
27283 
27284                 struct
27285                 {
27286                     union
27287                     {
27288                         __IOM uint8_t SQCH0DSC7AR_HL; /*!< (@ 0x000007F2) Sequence Channel 0 Descriptor-7 A Register                 */
27289 
27290                         struct
27291                         {
27292                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
27293                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
27294                         } SQCH0DSC7AR_HL_b;
27295                     };
27296 
27297                     union
27298                     {
27299                         __IOM uint8_t SQCH0DSC7AR_HH; /*!< (@ 0x000007F3) Sequence Channel 0 Descriptor-7 A Register                 */
27300 
27301                         struct
27302                         {
27303                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
27304                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
27305                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
27306                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
27307                             uint8_t             : 2;
27308                         } SQCH0DSC7AR_HH_b;
27309                     };
27310                 };
27311             };
27312         };
27313     };
27314 
27315     union
27316     {
27317         __IOM uint32_t SQCH0DSC7BR;    /*!< (@ 0x000007F4) Sequence Channel 0 Descriptor-7 B Register                 */
27318 
27319         struct
27320         {
27321             uint32_t             : 24;
27322             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
27323             uint32_t             : 6;
27324         } SQCH0DSC7BR_b;
27325     };
27326 
27327     union
27328     {
27329         union
27330         {
27331             __IOM uint32_t SQCH0DSC7CR;     /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register                 */
27332 
27333             struct
27334             {
27335                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
27336                 uint32_t               : 21;
27337                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
27338                 uint32_t               : 1;
27339                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
27340             } SQCH0DSC7CR_b;
27341         };
27342 
27343         struct
27344         {
27345             union
27346             {
27347                 union
27348                 {
27349                     __IOM uint16_t SQCH0DSC7CR_L;  /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register                 */
27350 
27351                     struct
27352                     {
27353                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
27354                         uint16_t              : 15;
27355                     } SQCH0DSC7CR_L_b;
27356                 };
27357 
27358                 union
27359                 {
27360                     __IOM uint8_t SQCH0DSC7CR_LL; /*!< (@ 0x000007F8) Sequence Channel 0 Descriptor-7 C Register                 */
27361 
27362                     struct
27363                     {
27364                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
27365                         uint8_t              : 7;
27366                     } SQCH0DSC7CR_LL_b;
27367                 };
27368             };
27369 
27370             union
27371             {
27372                 union
27373                 {
27374                     __IOM uint16_t SQCH0DSC7CR_H; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register                 */
27375 
27376                     struct
27377                     {
27378                         uint16_t               : 6;
27379                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
27380                         uint16_t               : 1;
27381                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
27382                     } SQCH0DSC7CR_H_b;
27383                 };
27384 
27385                 struct
27386                 {
27387                     union
27388                     {
27389                         __IOM uint8_t SQCH0DSC7CR_HL; /*!< (@ 0x000007FA) Sequence Channel 0 Descriptor-7 C Register                 */
27390 
27391                         struct
27392                         {
27393                             uint8_t             : 6;
27394                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
27395                             uint8_t             : 1;
27396                         } SQCH0DSC7CR_HL_b;
27397                     };
27398 
27399                     union
27400                     {
27401                         __IOM uint8_t SQCH0DSC7CR_HH;  /*!< (@ 0x000007FB) Sequence Channel 0 Descriptor-7 C Register                 */
27402 
27403                         struct
27404                         {
27405                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
27406                         } SQCH0DSC7CR_HH_b;
27407                     };
27408                 };
27409             };
27410         };
27411     };
27412 
27413     union
27414     {
27415         union
27416         {
27417             __IOM uint32_t SQCH0DSC7DR;    /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register                 */
27418 
27419             struct
27420             {
27421                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
27422             } SQCH0DSC7DR_b;
27423         };
27424 
27425         struct
27426         {
27427             union
27428             {
27429                 union
27430                 {
27431                     __IOM uint16_t SQCH0DSC7DR_L;  /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register                 */
27432 
27433                     struct
27434                     {
27435                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
27436                     } SQCH0DSC7DR_L_b;
27437                 };
27438 
27439                 struct
27440                 {
27441                     union
27442                     {
27443                         __IOM uint8_t SQCH0DSC7DR_LL; /*!< (@ 0x000007FC) Sequence Channel 0 Descriptor-7 D Register                 */
27444 
27445                         struct
27446                         {
27447                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27448                         } SQCH0DSC7DR_LL_b;
27449                     };
27450 
27451                     union
27452                     {
27453                         __IOM uint8_t SQCH0DSC7DR_LH; /*!< (@ 0x000007FD) Sequence Channel 0 Descriptor-7 D Register                 */
27454 
27455                         struct
27456                         {
27457                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27458                         } SQCH0DSC7DR_LH_b;
27459                     };
27460                 };
27461             };
27462 
27463             union
27464             {
27465                 union
27466                 {
27467                     __IOM uint16_t SQCH0DSC7DR_H;  /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register                 */
27468 
27469                     struct
27470                     {
27471                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
27472                     } SQCH0DSC7DR_H_b;
27473                 };
27474 
27475                 struct
27476                 {
27477                     union
27478                     {
27479                         __IOM uint8_t SQCH0DSC7DR_HL; /*!< (@ 0x000007FE) Sequence Channel 0 Descriptor-7 D Register                 */
27480 
27481                         struct
27482                         {
27483                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27484                         } SQCH0DSC7DR_HL_b;
27485                     };
27486 
27487                     union
27488                     {
27489                         __IOM uint8_t SQCH0DSC7DR_HH; /*!< (@ 0x000007FF) Sequence Channel 0 Descriptor-7 D Register                 */
27490 
27491                         struct
27492                         {
27493                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27494                         } SQCH0DSC7DR_HH_b;
27495                     };
27496                 };
27497             };
27498         };
27499     };
27500 
27501     union
27502     {
27503         union
27504         {
27505             __IOM uint32_t SQCH1DSC0AR;   /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register                 */
27506 
27507             struct
27508             {
27509                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
27510                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
27511                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
27512                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
27513                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
27514                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
27515                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
27516                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
27517                 uint32_t             : 2;
27518             } SQCH1DSC0AR_b;
27519         };
27520 
27521         struct
27522         {
27523             union
27524             {
27525                 union
27526                 {
27527                     __IOM uint16_t SQCH1DSC0AR_L; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register                 */
27528 
27529                     struct
27530                     {
27531                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
27532                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
27533                     } SQCH1DSC0AR_L_b;
27534                 };
27535 
27536                 struct
27537                 {
27538                     union
27539                     {
27540                         __IOM uint8_t SQCH1DSC0AR_LL; /*!< (@ 0x00000800) Sequence Channel 1 Descriptor-0 A Register                 */
27541 
27542                         struct
27543                         {
27544                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
27545                         } SQCH1DSC0AR_LL_b;
27546                     };
27547 
27548                     union
27549                     {
27550                         __IOM uint8_t SQCH1DSC0AR_LH; /*!< (@ 0x00000801) Sequence Channel 1 Descriptor-0 A Register                 */
27551 
27552                         struct
27553                         {
27554                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
27555                         } SQCH1DSC0AR_LH_b;
27556                     };
27557                 };
27558             };
27559 
27560             union
27561             {
27562                 union
27563                 {
27564                     __IOM uint16_t SQCH1DSC0AR_H; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register                 */
27565 
27566                     struct
27567                     {
27568                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
27569                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
27570                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
27571                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
27572                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
27573                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
27574                         uint16_t             : 2;
27575                     } SQCH1DSC0AR_H_b;
27576                 };
27577 
27578                 struct
27579                 {
27580                     union
27581                     {
27582                         __IOM uint8_t SQCH1DSC0AR_HL; /*!< (@ 0x00000802) Sequence Channel 1 Descriptor-0 A Register                 */
27583 
27584                         struct
27585                         {
27586                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
27587                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
27588                         } SQCH1DSC0AR_HL_b;
27589                     };
27590 
27591                     union
27592                     {
27593                         __IOM uint8_t SQCH1DSC0AR_HH; /*!< (@ 0x00000803) Sequence Channel 1 Descriptor-0 A Register                 */
27594 
27595                         struct
27596                         {
27597                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
27598                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
27599                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
27600                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
27601                             uint8_t             : 2;
27602                         } SQCH1DSC0AR_HH_b;
27603                     };
27604                 };
27605             };
27606         };
27607     };
27608 
27609     union
27610     {
27611         __IOM uint32_t SQCH1DSC0BR;    /*!< (@ 0x00000804) Sequence Channel 1 Descriptor-0 B Register                 */
27612 
27613         struct
27614         {
27615             uint32_t             : 24;
27616             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
27617             uint32_t             : 6;
27618         } SQCH1DSC0BR_b;
27619     };
27620 
27621     union
27622     {
27623         union
27624         {
27625             __IOM uint32_t SQCH1DSC0CR;     /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register                 */
27626 
27627             struct
27628             {
27629                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
27630                 uint32_t               : 21;
27631                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
27632                 uint32_t               : 1;
27633                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
27634             } SQCH1DSC0CR_b;
27635         };
27636 
27637         struct
27638         {
27639             union
27640             {
27641                 union
27642                 {
27643                     __IOM uint16_t SQCH1DSC0CR_L;  /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register                 */
27644 
27645                     struct
27646                     {
27647                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
27648                         uint16_t              : 15;
27649                     } SQCH1DSC0CR_L_b;
27650                 };
27651 
27652                 union
27653                 {
27654                     __IOM uint8_t SQCH1DSC0CR_LL; /*!< (@ 0x00000808) Sequence Channel 1 Descriptor-0 C Register                 */
27655 
27656                     struct
27657                     {
27658                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
27659                         uint8_t              : 7;
27660                     } SQCH1DSC0CR_LL_b;
27661                 };
27662             };
27663 
27664             union
27665             {
27666                 union
27667                 {
27668                     __IOM uint16_t SQCH1DSC0CR_H; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register                 */
27669 
27670                     struct
27671                     {
27672                         uint16_t               : 6;
27673                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
27674                         uint16_t               : 1;
27675                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
27676                     } SQCH1DSC0CR_H_b;
27677                 };
27678 
27679                 struct
27680                 {
27681                     union
27682                     {
27683                         __IOM uint8_t SQCH1DSC0CR_HL; /*!< (@ 0x0000080A) Sequence Channel 1 Descriptor-0 C Register                 */
27684 
27685                         struct
27686                         {
27687                             uint8_t             : 6;
27688                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
27689                             uint8_t             : 1;
27690                         } SQCH1DSC0CR_HL_b;
27691                     };
27692 
27693                     union
27694                     {
27695                         __IOM uint8_t SQCH1DSC0CR_HH;  /*!< (@ 0x0000080B) Sequence Channel 1 Descriptor-0 C Register                 */
27696 
27697                         struct
27698                         {
27699                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
27700                         } SQCH1DSC0CR_HH_b;
27701                     };
27702                 };
27703             };
27704         };
27705     };
27706 
27707     union
27708     {
27709         union
27710         {
27711             __IOM uint32_t SQCH1DSC0DR;    /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register                 */
27712 
27713             struct
27714             {
27715                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
27716             } SQCH1DSC0DR_b;
27717         };
27718 
27719         struct
27720         {
27721             union
27722             {
27723                 union
27724                 {
27725                     __IOM uint16_t SQCH1DSC0DR_L;  /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register                 */
27726 
27727                     struct
27728                     {
27729                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
27730                     } SQCH1DSC0DR_L_b;
27731                 };
27732 
27733                 struct
27734                 {
27735                     union
27736                     {
27737                         __IOM uint8_t SQCH1DSC0DR_LL; /*!< (@ 0x0000080C) Sequence Channel 1 Descriptor-0 D Register                 */
27738 
27739                         struct
27740                         {
27741                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27742                         } SQCH1DSC0DR_LL_b;
27743                     };
27744 
27745                     union
27746                     {
27747                         __IOM uint8_t SQCH1DSC0DR_LH; /*!< (@ 0x0000080D) Sequence Channel 1 Descriptor-0 D Register                 */
27748 
27749                         struct
27750                         {
27751                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27752                         } SQCH1DSC0DR_LH_b;
27753                     };
27754                 };
27755             };
27756 
27757             union
27758             {
27759                 __IOM uint8_t SQCH1DSC0DR_HL; /*!< (@ 0x0000080E) Sequence Channel 1 Descriptor-0 D Register                 */
27760 
27761                 struct
27762                 {
27763                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27764                 } SQCH1DSC0DR_HL_b;
27765             };
27766 
27767             union
27768             {
27769                 __IOM uint8_t SQCH1DSC0DR_HH; /*!< (@ 0x0000080F) Sequence Channel 1 Descriptor-0 D Register                 */
27770 
27771                 struct
27772                 {
27773                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
27774                 } SQCH1DSC0DR_HH_b;
27775             };
27776         };
27777     };
27778 
27779     union
27780     {
27781         union
27782         {
27783             __IOM uint32_t SQCH1DSC1AR;   /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register                 */
27784 
27785             struct
27786             {
27787                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
27788                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
27789                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
27790                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
27791                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
27792                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
27793                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
27794                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
27795                 uint32_t             : 2;
27796             } SQCH1DSC1AR_b;
27797         };
27798 
27799         struct
27800         {
27801             union
27802             {
27803                 union
27804                 {
27805                     __IOM uint16_t SQCH1DSC1AR_L; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register                 */
27806 
27807                     struct
27808                     {
27809                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
27810                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
27811                     } SQCH1DSC1AR_L_b;
27812                 };
27813 
27814                 struct
27815                 {
27816                     union
27817                     {
27818                         __IOM uint8_t SQCH1DSC1AR_LL; /*!< (@ 0x00000810) Sequence Channel 1 Descriptor-1 A Register                 */
27819 
27820                         struct
27821                         {
27822                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
27823                         } SQCH1DSC1AR_LL_b;
27824                     };
27825 
27826                     union
27827                     {
27828                         __IOM uint8_t SQCH1DSC1AR_LH; /*!< (@ 0x00000811) Sequence Channel 1 Descriptor-1 A Register                 */
27829 
27830                         struct
27831                         {
27832                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
27833                         } SQCH1DSC1AR_LH_b;
27834                     };
27835                 };
27836             };
27837 
27838             union
27839             {
27840                 union
27841                 {
27842                     __IOM uint16_t SQCH1DSC1AR_H; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register                 */
27843 
27844                     struct
27845                     {
27846                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
27847                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
27848                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
27849                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
27850                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
27851                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
27852                         uint16_t             : 2;
27853                     } SQCH1DSC1AR_H_b;
27854                 };
27855 
27856                 struct
27857                 {
27858                     union
27859                     {
27860                         __IOM uint8_t SQCH1DSC1AR_HL; /*!< (@ 0x00000812) Sequence Channel 1 Descriptor-1 A Register                 */
27861 
27862                         struct
27863                         {
27864                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
27865                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
27866                         } SQCH1DSC1AR_HL_b;
27867                     };
27868 
27869                     union
27870                     {
27871                         __IOM uint8_t SQCH1DSC1AR_HH; /*!< (@ 0x00000813) Sequence Channel 1 Descriptor-1 A Register                 */
27872 
27873                         struct
27874                         {
27875                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
27876                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
27877                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
27878                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
27879                             uint8_t             : 2;
27880                         } SQCH1DSC1AR_HH_b;
27881                     };
27882                 };
27883             };
27884         };
27885     };
27886 
27887     union
27888     {
27889         __IOM uint32_t SQCH1DSC1BR;    /*!< (@ 0x00000814) Sequence Channel 1 Descriptor-1 B Register                 */
27890 
27891         struct
27892         {
27893             uint32_t             : 24;
27894             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
27895             uint32_t             : 6;
27896         } SQCH1DSC1BR_b;
27897     };
27898 
27899     union
27900     {
27901         union
27902         {
27903             __IOM uint32_t SQCH1DSC1CR;     /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register                 */
27904 
27905             struct
27906             {
27907                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
27908                 uint32_t               : 21;
27909                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
27910                 uint32_t               : 1;
27911                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
27912             } SQCH1DSC1CR_b;
27913         };
27914 
27915         struct
27916         {
27917             union
27918             {
27919                 union
27920                 {
27921                     __IOM uint16_t SQCH1DSC1CR_L;  /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register                 */
27922 
27923                     struct
27924                     {
27925                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
27926                         uint16_t              : 15;
27927                     } SQCH1DSC1CR_L_b;
27928                 };
27929 
27930                 union
27931                 {
27932                     __IOM uint8_t SQCH1DSC1CR_LL; /*!< (@ 0x00000818) Sequence Channel 1 Descriptor-1 C Register                 */
27933 
27934                     struct
27935                     {
27936                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
27937                         uint8_t              : 7;
27938                     } SQCH1DSC1CR_LL_b;
27939                 };
27940             };
27941 
27942             union
27943             {
27944                 union
27945                 {
27946                     __IOM uint16_t SQCH1DSC1CR_H; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register                 */
27947 
27948                     struct
27949                     {
27950                         uint16_t               : 6;
27951                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
27952                         uint16_t               : 1;
27953                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
27954                     } SQCH1DSC1CR_H_b;
27955                 };
27956 
27957                 struct
27958                 {
27959                     union
27960                     {
27961                         __IOM uint8_t SQCH1DSC1CR_HL; /*!< (@ 0x0000081A) Sequence Channel 1 Descriptor-1 C Register                 */
27962 
27963                         struct
27964                         {
27965                             uint8_t             : 6;
27966                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
27967                             uint8_t             : 1;
27968                         } SQCH1DSC1CR_HL_b;
27969                     };
27970 
27971                     union
27972                     {
27973                         __IOM uint8_t SQCH1DSC1CR_HH;  /*!< (@ 0x0000081B) Sequence Channel 1 Descriptor-1 C Register                 */
27974 
27975                         struct
27976                         {
27977                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
27978                         } SQCH1DSC1CR_HH_b;
27979                     };
27980                 };
27981             };
27982         };
27983     };
27984 
27985     union
27986     {
27987         union
27988         {
27989             __IOM uint32_t SQCH1DSC1DR;    /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register                 */
27990 
27991             struct
27992             {
27993                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
27994             } SQCH1DSC1DR_b;
27995         };
27996 
27997         struct
27998         {
27999             union
28000             {
28001                 union
28002                 {
28003                     __IOM uint16_t SQCH1DSC1DR_L;  /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register                 */
28004 
28005                     struct
28006                     {
28007                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
28008                     } SQCH1DSC1DR_L_b;
28009                 };
28010 
28011                 struct
28012                 {
28013                     union
28014                     {
28015                         __IOM uint8_t SQCH1DSC1DR_LL; /*!< (@ 0x0000081C) Sequence Channel 1 Descriptor-1 D Register                 */
28016 
28017                         struct
28018                         {
28019                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28020                         } SQCH1DSC1DR_LL_b;
28021                     };
28022 
28023                     union
28024                     {
28025                         __IOM uint8_t SQCH1DSC1DR_LH; /*!< (@ 0x0000081D) Sequence Channel 1 Descriptor-1 D Register                 */
28026 
28027                         struct
28028                         {
28029                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28030                         } SQCH1DSC1DR_LH_b;
28031                     };
28032                 };
28033             };
28034 
28035             union
28036             {
28037                 __IOM uint8_t SQCH1DSC1DR_HL; /*!< (@ 0x0000081E) Sequence Channel 1 Descriptor-1 D Register                 */
28038 
28039                 struct
28040                 {
28041                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28042                 } SQCH1DSC1DR_HL_b;
28043             };
28044 
28045             union
28046             {
28047                 __IOM uint8_t SQCH1DSC1DR_HH; /*!< (@ 0x0000081F) Sequence Channel 1 Descriptor-1 D Register                 */
28048 
28049                 struct
28050                 {
28051                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28052                 } SQCH1DSC1DR_HH_b;
28053             };
28054         };
28055     };
28056 
28057     union
28058     {
28059         union
28060         {
28061             __IOM uint32_t SQCH1DSC2AR;   /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register                 */
28062 
28063             struct
28064             {
28065                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
28066                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
28067                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
28068                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
28069                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
28070                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
28071                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
28072                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
28073                 uint32_t             : 2;
28074             } SQCH1DSC2AR_b;
28075         };
28076 
28077         struct
28078         {
28079             union
28080             {
28081                 union
28082                 {
28083                     __IOM uint16_t SQCH1DSC2AR_L; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register                 */
28084 
28085                     struct
28086                     {
28087                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
28088                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
28089                     } SQCH1DSC2AR_L_b;
28090                 };
28091 
28092                 struct
28093                 {
28094                     union
28095                     {
28096                         __IOM uint8_t SQCH1DSC2AR_LL; /*!< (@ 0x00000820) Sequence Channel 1 Descriptor-2 A Register                 */
28097 
28098                         struct
28099                         {
28100                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
28101                         } SQCH1DSC2AR_LL_b;
28102                     };
28103 
28104                     union
28105                     {
28106                         __IOM uint8_t SQCH1DSC2AR_LH; /*!< (@ 0x00000821) Sequence Channel 1 Descriptor-2 A Register                 */
28107 
28108                         struct
28109                         {
28110                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
28111                         } SQCH1DSC2AR_LH_b;
28112                     };
28113                 };
28114             };
28115 
28116             union
28117             {
28118                 union
28119                 {
28120                     __IOM uint16_t SQCH1DSC2AR_H; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register                 */
28121 
28122                     struct
28123                     {
28124                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
28125                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
28126                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
28127                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
28128                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
28129                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
28130                         uint16_t             : 2;
28131                     } SQCH1DSC2AR_H_b;
28132                 };
28133 
28134                 struct
28135                 {
28136                     union
28137                     {
28138                         __IOM uint8_t SQCH1DSC2AR_HL; /*!< (@ 0x00000822) Sequence Channel 1 Descriptor-2 A Register                 */
28139 
28140                         struct
28141                         {
28142                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
28143                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
28144                         } SQCH1DSC2AR_HL_b;
28145                     };
28146 
28147                     union
28148                     {
28149                         __IOM uint8_t SQCH1DSC2AR_HH; /*!< (@ 0x00000823) Sequence Channel 1 Descriptor-2 A Register                 */
28150 
28151                         struct
28152                         {
28153                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
28154                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
28155                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
28156                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
28157                             uint8_t             : 2;
28158                         } SQCH1DSC2AR_HH_b;
28159                     };
28160                 };
28161             };
28162         };
28163     };
28164 
28165     union
28166     {
28167         __IOM uint32_t SQCH1DSC2BR;    /*!< (@ 0x00000824) Sequence Channel 1 Descriptor-2 B Register                 */
28168 
28169         struct
28170         {
28171             uint32_t             : 24;
28172             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
28173             uint32_t             : 6;
28174         } SQCH1DSC2BR_b;
28175     };
28176 
28177     union
28178     {
28179         union
28180         {
28181             __IOM uint32_t SQCH1DSC2CR;     /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register                 */
28182 
28183             struct
28184             {
28185                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
28186                 uint32_t               : 21;
28187                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
28188                 uint32_t               : 1;
28189                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
28190             } SQCH1DSC2CR_b;
28191         };
28192 
28193         struct
28194         {
28195             union
28196             {
28197                 union
28198                 {
28199                     __IOM uint16_t SQCH1DSC2CR_L;  /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register                 */
28200 
28201                     struct
28202                     {
28203                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
28204                         uint16_t              : 15;
28205                     } SQCH1DSC2CR_L_b;
28206                 };
28207 
28208                 union
28209                 {
28210                     __IOM uint8_t SQCH1DSC2CR_LL; /*!< (@ 0x00000828) Sequence Channel 1 Descriptor-2 C Register                 */
28211 
28212                     struct
28213                     {
28214                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
28215                         uint8_t              : 7;
28216                     } SQCH1DSC2CR_LL_b;
28217                 };
28218             };
28219 
28220             union
28221             {
28222                 union
28223                 {
28224                     __IOM uint16_t SQCH1DSC2CR_H; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register                 */
28225 
28226                     struct
28227                     {
28228                         uint16_t               : 6;
28229                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
28230                         uint16_t               : 1;
28231                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
28232                     } SQCH1DSC2CR_H_b;
28233                 };
28234 
28235                 struct
28236                 {
28237                     union
28238                     {
28239                         __IOM uint8_t SQCH1DSC2CR_HL; /*!< (@ 0x0000082A) Sequence Channel 1 Descriptor-2 C Register                 */
28240 
28241                         struct
28242                         {
28243                             uint8_t             : 6;
28244                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
28245                             uint8_t             : 1;
28246                         } SQCH1DSC2CR_HL_b;
28247                     };
28248 
28249                     union
28250                     {
28251                         __IOM uint8_t SQCH1DSC2CR_HH;  /*!< (@ 0x0000082B) Sequence Channel 1 Descriptor-2 C Register                 */
28252 
28253                         struct
28254                         {
28255                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
28256                         } SQCH1DSC2CR_HH_b;
28257                     };
28258                 };
28259             };
28260         };
28261     };
28262 
28263     union
28264     {
28265         union
28266         {
28267             __IOM uint32_t SQCH1DSC2DR;    /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register                 */
28268 
28269             struct
28270             {
28271                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
28272             } SQCH1DSC2DR_b;
28273         };
28274 
28275         struct
28276         {
28277             union
28278             {
28279                 union
28280                 {
28281                     __IOM uint16_t SQCH1DSC2DR_L;  /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register                 */
28282 
28283                     struct
28284                     {
28285                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
28286                     } SQCH1DSC2DR_L_b;
28287                 };
28288 
28289                 struct
28290                 {
28291                     union
28292                     {
28293                         __IOM uint8_t SQCH1DSC2DR_LL; /*!< (@ 0x0000082C) Sequence Channel 1 Descriptor-2 D Register                 */
28294 
28295                         struct
28296                         {
28297                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28298                         } SQCH1DSC2DR_LL_b;
28299                     };
28300 
28301                     union
28302                     {
28303                         __IOM uint8_t SQCH1DSC2DR_LH; /*!< (@ 0x0000082D) Sequence Channel 1 Descriptor-2 D Register                 */
28304 
28305                         struct
28306                         {
28307                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28308                         } SQCH1DSC2DR_LH_b;
28309                     };
28310                 };
28311             };
28312 
28313             union
28314             {
28315                 __IOM uint8_t SQCH1DSC2DR_HL; /*!< (@ 0x0000082E) Sequence Channel 1 Descriptor-2 D Register                 */
28316 
28317                 struct
28318                 {
28319                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28320                 } SQCH1DSC2DR_HL_b;
28321             };
28322 
28323             union
28324             {
28325                 __IOM uint8_t SQCH1DSC2DR_HH; /*!< (@ 0x0000082F) Sequence Channel 1 Descriptor-2 D Register                 */
28326 
28327                 struct
28328                 {
28329                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28330                 } SQCH1DSC2DR_HH_b;
28331             };
28332         };
28333     };
28334 
28335     union
28336     {
28337         union
28338         {
28339             __IOM uint32_t SQCH1DSC3AR;   /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register                 */
28340 
28341             struct
28342             {
28343                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
28344                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
28345                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
28346                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
28347                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
28348                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
28349                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
28350                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
28351                 uint32_t             : 2;
28352             } SQCH1DSC3AR_b;
28353         };
28354 
28355         struct
28356         {
28357             union
28358             {
28359                 union
28360                 {
28361                     __IOM uint16_t SQCH1DSC3AR_L; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register                 */
28362 
28363                     struct
28364                     {
28365                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
28366                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
28367                     } SQCH1DSC3AR_L_b;
28368                 };
28369 
28370                 struct
28371                 {
28372                     union
28373                     {
28374                         __IOM uint8_t SQCH1DSC3AR_LL; /*!< (@ 0x00000830) Sequence Channel 1 Descriptor-3 A Register                 */
28375 
28376                         struct
28377                         {
28378                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
28379                         } SQCH1DSC3AR_LL_b;
28380                     };
28381 
28382                     union
28383                     {
28384                         __IOM uint8_t SQCH1DSC3AR_LH; /*!< (@ 0x00000831) Sequence Channel 1 Descriptor-3 A Register                 */
28385 
28386                         struct
28387                         {
28388                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
28389                         } SQCH1DSC3AR_LH_b;
28390                     };
28391                 };
28392             };
28393 
28394             union
28395             {
28396                 union
28397                 {
28398                     __IOM uint16_t SQCH1DSC3AR_H; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register                 */
28399 
28400                     struct
28401                     {
28402                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
28403                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
28404                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
28405                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
28406                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
28407                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
28408                         uint16_t             : 2;
28409                     } SQCH1DSC3AR_H_b;
28410                 };
28411 
28412                 struct
28413                 {
28414                     union
28415                     {
28416                         __IOM uint8_t SQCH1DSC3AR_HL; /*!< (@ 0x00000832) Sequence Channel 1 Descriptor-3 A Register                 */
28417 
28418                         struct
28419                         {
28420                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
28421                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
28422                         } SQCH1DSC3AR_HL_b;
28423                     };
28424 
28425                     union
28426                     {
28427                         __IOM uint8_t SQCH1DSC3AR_HH; /*!< (@ 0x00000833) Sequence Channel 1 Descriptor-3 A Register                 */
28428 
28429                         struct
28430                         {
28431                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
28432                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
28433                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
28434                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
28435                             uint8_t             : 2;
28436                         } SQCH1DSC3AR_HH_b;
28437                     };
28438                 };
28439             };
28440         };
28441     };
28442 
28443     union
28444     {
28445         __IOM uint32_t SQCH1DSC3BR;    /*!< (@ 0x00000834) Sequence Channel 1 Descriptor-3 B Register                 */
28446 
28447         struct
28448         {
28449             uint32_t             : 24;
28450             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
28451             uint32_t             : 6;
28452         } SQCH1DSC3BR_b;
28453     };
28454 
28455     union
28456     {
28457         union
28458         {
28459             __IOM uint32_t SQCH1DSC3CR;     /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register                 */
28460 
28461             struct
28462             {
28463                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
28464                 uint32_t               : 21;
28465                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
28466                 uint32_t               : 1;
28467                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
28468             } SQCH1DSC3CR_b;
28469         };
28470 
28471         struct
28472         {
28473             union
28474             {
28475                 union
28476                 {
28477                     __IOM uint16_t SQCH1DSC3CR_L;  /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register                 */
28478 
28479                     struct
28480                     {
28481                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
28482                         uint16_t              : 15;
28483                     } SQCH1DSC3CR_L_b;
28484                 };
28485 
28486                 union
28487                 {
28488                     __IOM uint8_t SQCH1DSC3CR_LL; /*!< (@ 0x00000838) Sequence Channel 1 Descriptor-3 C Register                 */
28489 
28490                     struct
28491                     {
28492                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
28493                         uint8_t              : 7;
28494                     } SQCH1DSC3CR_LL_b;
28495                 };
28496             };
28497 
28498             union
28499             {
28500                 union
28501                 {
28502                     __IOM uint16_t SQCH1DSC3CR_H; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register                 */
28503 
28504                     struct
28505                     {
28506                         uint16_t               : 6;
28507                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
28508                         uint16_t               : 1;
28509                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
28510                     } SQCH1DSC3CR_H_b;
28511                 };
28512 
28513                 struct
28514                 {
28515                     union
28516                     {
28517                         __IOM uint8_t SQCH1DSC3CR_HL; /*!< (@ 0x0000083A) Sequence Channel 1 Descriptor-3 C Register                 */
28518 
28519                         struct
28520                         {
28521                             uint8_t             : 6;
28522                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
28523                             uint8_t             : 1;
28524                         } SQCH1DSC3CR_HL_b;
28525                     };
28526 
28527                     union
28528                     {
28529                         __IOM uint8_t SQCH1DSC3CR_HH;  /*!< (@ 0x0000083B) Sequence Channel 1 Descriptor-3 C Register                 */
28530 
28531                         struct
28532                         {
28533                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
28534                         } SQCH1DSC3CR_HH_b;
28535                     };
28536                 };
28537             };
28538         };
28539     };
28540 
28541     union
28542     {
28543         union
28544         {
28545             __IOM uint32_t SQCH1DSC3DR;    /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register                 */
28546 
28547             struct
28548             {
28549                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
28550             } SQCH1DSC3DR_b;
28551         };
28552 
28553         struct
28554         {
28555             union
28556             {
28557                 union
28558                 {
28559                     __IOM uint16_t SQCH1DSC3DR_L;  /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register                 */
28560 
28561                     struct
28562                     {
28563                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
28564                     } SQCH1DSC3DR_L_b;
28565                 };
28566 
28567                 struct
28568                 {
28569                     union
28570                     {
28571                         __IOM uint8_t SQCH1DSC3DR_LL; /*!< (@ 0x0000083C) Sequence Channel 1 Descriptor-3 D Register                 */
28572 
28573                         struct
28574                         {
28575                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28576                         } SQCH1DSC3DR_LL_b;
28577                     };
28578 
28579                     union
28580                     {
28581                         __IOM uint8_t SQCH1DSC3DR_LH; /*!< (@ 0x0000083D) Sequence Channel 1 Descriptor-3 D Register                 */
28582 
28583                         struct
28584                         {
28585                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28586                         } SQCH1DSC3DR_LH_b;
28587                     };
28588                 };
28589             };
28590 
28591             union
28592             {
28593                 __IOM uint8_t SQCH1DSC3DR_HL; /*!< (@ 0x0000083E) Sequence Channel 1 Descriptor-3 D Register                 */
28594 
28595                 struct
28596                 {
28597                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28598                 } SQCH1DSC3DR_HL_b;
28599             };
28600 
28601             union
28602             {
28603                 __IOM uint8_t SQCH1DSC3DR_HH; /*!< (@ 0x0000083F) Sequence Channel 1 Descriptor-3 D Register                 */
28604 
28605                 struct
28606                 {
28607                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28608                 } SQCH1DSC3DR_HH_b;
28609             };
28610         };
28611     };
28612 
28613     union
28614     {
28615         union
28616         {
28617             __IOM uint32_t SQCH1DSC4AR;   /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register                 */
28618 
28619             struct
28620             {
28621                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
28622                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
28623                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
28624                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
28625                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
28626                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
28627                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
28628                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
28629                 uint32_t             : 2;
28630             } SQCH1DSC4AR_b;
28631         };
28632 
28633         struct
28634         {
28635             union
28636             {
28637                 union
28638                 {
28639                     __IOM uint16_t SQCH1DSC4AR_L; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register                 */
28640 
28641                     struct
28642                     {
28643                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
28644                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
28645                     } SQCH1DSC4AR_L_b;
28646                 };
28647 
28648                 struct
28649                 {
28650                     union
28651                     {
28652                         __IOM uint8_t SQCH1DSC4AR_LL; /*!< (@ 0x00000840) Sequence Channel 1 Descriptor-4 A Register                 */
28653 
28654                         struct
28655                         {
28656                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
28657                         } SQCH1DSC4AR_LL_b;
28658                     };
28659 
28660                     union
28661                     {
28662                         __IOM uint8_t SQCH1DSC4AR_LH; /*!< (@ 0x00000841) Sequence Channel 1 Descriptor-4 A Register                 */
28663 
28664                         struct
28665                         {
28666                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
28667                         } SQCH1DSC4AR_LH_b;
28668                     };
28669                 };
28670             };
28671 
28672             union
28673             {
28674                 union
28675                 {
28676                     __IOM uint16_t SQCH1DSC4AR_H; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register                 */
28677 
28678                     struct
28679                     {
28680                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
28681                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
28682                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
28683                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
28684                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
28685                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
28686                         uint16_t             : 2;
28687                     } SQCH1DSC4AR_H_b;
28688                 };
28689 
28690                 struct
28691                 {
28692                     union
28693                     {
28694                         __IOM uint8_t SQCH1DSC4AR_HL; /*!< (@ 0x00000842) Sequence Channel 1 Descriptor-4 A Register                 */
28695 
28696                         struct
28697                         {
28698                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
28699                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
28700                         } SQCH1DSC4AR_HL_b;
28701                     };
28702 
28703                     union
28704                     {
28705                         __IOM uint8_t SQCH1DSC4AR_HH; /*!< (@ 0x00000843) Sequence Channel 1 Descriptor-4 A Register                 */
28706 
28707                         struct
28708                         {
28709                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
28710                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
28711                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
28712                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
28713                             uint8_t             : 2;
28714                         } SQCH1DSC4AR_HH_b;
28715                     };
28716                 };
28717             };
28718         };
28719     };
28720 
28721     union
28722     {
28723         __IOM uint32_t SQCH1DSC4BR;    /*!< (@ 0x00000844) Sequence Channel 1 Descriptor-4 B Register                 */
28724 
28725         struct
28726         {
28727             uint32_t             : 24;
28728             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
28729             uint32_t             : 6;
28730         } SQCH1DSC4BR_b;
28731     };
28732 
28733     union
28734     {
28735         union
28736         {
28737             __IOM uint32_t SQCH1DSC4CR;     /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register                 */
28738 
28739             struct
28740             {
28741                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
28742                 uint32_t               : 21;
28743                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
28744                 uint32_t               : 1;
28745                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
28746             } SQCH1DSC4CR_b;
28747         };
28748 
28749         struct
28750         {
28751             union
28752             {
28753                 union
28754                 {
28755                     __IOM uint16_t SQCH1DSC4CR_L;  /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register                 */
28756 
28757                     struct
28758                     {
28759                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
28760                         uint16_t              : 15;
28761                     } SQCH1DSC4CR_L_b;
28762                 };
28763 
28764                 union
28765                 {
28766                     __IOM uint8_t SQCH1DSC4CR_LL; /*!< (@ 0x00000848) Sequence Channel 1 Descriptor-4 C Register                 */
28767 
28768                     struct
28769                     {
28770                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
28771                         uint8_t              : 7;
28772                     } SQCH1DSC4CR_LL_b;
28773                 };
28774             };
28775 
28776             union
28777             {
28778                 union
28779                 {
28780                     __IOM uint16_t SQCH1DSC4CR_H; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register                 */
28781 
28782                     struct
28783                     {
28784                         uint16_t               : 6;
28785                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
28786                         uint16_t               : 1;
28787                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
28788                     } SQCH1DSC4CR_H_b;
28789                 };
28790 
28791                 struct
28792                 {
28793                     union
28794                     {
28795                         __IOM uint8_t SQCH1DSC4CR_HL; /*!< (@ 0x0000084A) Sequence Channel 1 Descriptor-4 C Register                 */
28796 
28797                         struct
28798                         {
28799                             uint8_t             : 6;
28800                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
28801                             uint8_t             : 1;
28802                         } SQCH1DSC4CR_HL_b;
28803                     };
28804 
28805                     union
28806                     {
28807                         __IOM uint8_t SQCH1DSC4CR_HH;  /*!< (@ 0x0000084B) Sequence Channel 1 Descriptor-4 C Register                 */
28808 
28809                         struct
28810                         {
28811                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
28812                         } SQCH1DSC4CR_HH_b;
28813                     };
28814                 };
28815             };
28816         };
28817     };
28818 
28819     union
28820     {
28821         union
28822         {
28823             __IOM uint32_t SQCH1DSC4DR;    /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register                 */
28824 
28825             struct
28826             {
28827                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
28828             } SQCH1DSC4DR_b;
28829         };
28830 
28831         struct
28832         {
28833             union
28834             {
28835                 union
28836                 {
28837                     __IOM uint16_t SQCH1DSC4DR_L;  /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register                 */
28838 
28839                     struct
28840                     {
28841                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
28842                     } SQCH1DSC4DR_L_b;
28843                 };
28844 
28845                 struct
28846                 {
28847                     union
28848                     {
28849                         __IOM uint8_t SQCH1DSC4DR_LL; /*!< (@ 0x0000084C) Sequence Channel 1 Descriptor-4 D Register                 */
28850 
28851                         struct
28852                         {
28853                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28854                         } SQCH1DSC4DR_LL_b;
28855                     };
28856 
28857                     union
28858                     {
28859                         __IOM uint8_t SQCH1DSC4DR_LH; /*!< (@ 0x0000084D) Sequence Channel 1 Descriptor-4 D Register                 */
28860 
28861                         struct
28862                         {
28863                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28864                         } SQCH1DSC4DR_LH_b;
28865                     };
28866                 };
28867             };
28868 
28869             union
28870             {
28871                 __IOM uint8_t SQCH1DSC4DR_HL; /*!< (@ 0x0000084E) Sequence Channel 1 Descriptor-4 D Register                 */
28872 
28873                 struct
28874                 {
28875                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28876                 } SQCH1DSC4DR_HL_b;
28877             };
28878 
28879             union
28880             {
28881                 __IOM uint8_t SQCH1DSC4DR_HH; /*!< (@ 0x0000084F) Sequence Channel 1 Descriptor-4 D Register                 */
28882 
28883                 struct
28884                 {
28885                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
28886                 } SQCH1DSC4DR_HH_b;
28887             };
28888         };
28889     };
28890 
28891     union
28892     {
28893         union
28894         {
28895             __IOM uint32_t SQCH1DSC5AR;   /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register                 */
28896 
28897             struct
28898             {
28899                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
28900                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
28901                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
28902                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
28903                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
28904                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
28905                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
28906                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
28907                 uint32_t             : 2;
28908             } SQCH1DSC5AR_b;
28909         };
28910 
28911         struct
28912         {
28913             union
28914             {
28915                 union
28916                 {
28917                     __IOM uint16_t SQCH1DSC5AR_L; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register                 */
28918 
28919                     struct
28920                     {
28921                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
28922                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
28923                     } SQCH1DSC5AR_L_b;
28924                 };
28925 
28926                 struct
28927                 {
28928                     union
28929                     {
28930                         __IOM uint8_t SQCH1DSC5AR_LL; /*!< (@ 0x00000850) Sequence Channel 1 Descriptor-5 A Register                 */
28931 
28932                         struct
28933                         {
28934                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
28935                         } SQCH1DSC5AR_LL_b;
28936                     };
28937 
28938                     union
28939                     {
28940                         __IOM uint8_t SQCH1DSC5AR_LH; /*!< (@ 0x00000851) Sequence Channel 1 Descriptor-5 A Register                 */
28941 
28942                         struct
28943                         {
28944                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
28945                         } SQCH1DSC5AR_LH_b;
28946                     };
28947                 };
28948             };
28949 
28950             union
28951             {
28952                 union
28953                 {
28954                     __IOM uint16_t SQCH1DSC5AR_H; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register                 */
28955 
28956                     struct
28957                     {
28958                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
28959                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
28960                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
28961                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
28962                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
28963                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
28964                         uint16_t             : 2;
28965                     } SQCH1DSC5AR_H_b;
28966                 };
28967 
28968                 struct
28969                 {
28970                     union
28971                     {
28972                         __IOM uint8_t SQCH1DSC5AR_HL; /*!< (@ 0x00000852) Sequence Channel 1 Descriptor-5 A Register                 */
28973 
28974                         struct
28975                         {
28976                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
28977                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
28978                         } SQCH1DSC5AR_HL_b;
28979                     };
28980 
28981                     union
28982                     {
28983                         __IOM uint8_t SQCH1DSC5AR_HH; /*!< (@ 0x00000853) Sequence Channel 1 Descriptor-5 A Register                 */
28984 
28985                         struct
28986                         {
28987                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
28988                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
28989                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
28990                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
28991                             uint8_t             : 2;
28992                         } SQCH1DSC5AR_HH_b;
28993                     };
28994                 };
28995             };
28996         };
28997     };
28998 
28999     union
29000     {
29001         __IOM uint32_t SQCH1DSC5BR;    /*!< (@ 0x00000854) Sequence Channel 1 Descriptor-5 B Register                 */
29002 
29003         struct
29004         {
29005             uint32_t             : 24;
29006             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
29007             uint32_t             : 6;
29008         } SQCH1DSC5BR_b;
29009     };
29010 
29011     union
29012     {
29013         union
29014         {
29015             __IOM uint32_t SQCH1DSC5CR;     /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register                 */
29016 
29017             struct
29018             {
29019                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
29020                 uint32_t               : 21;
29021                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
29022                 uint32_t               : 1;
29023                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
29024             } SQCH1DSC5CR_b;
29025         };
29026 
29027         struct
29028         {
29029             union
29030             {
29031                 union
29032                 {
29033                     __IOM uint16_t SQCH1DSC5CR_L;  /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register                 */
29034 
29035                     struct
29036                     {
29037                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
29038                         uint16_t              : 15;
29039                     } SQCH1DSC5CR_L_b;
29040                 };
29041 
29042                 union
29043                 {
29044                     __IOM uint8_t SQCH1DSC5CR_LL; /*!< (@ 0x00000858) Sequence Channel 1 Descriptor-5 C Register                 */
29045 
29046                     struct
29047                     {
29048                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
29049                         uint8_t              : 7;
29050                     } SQCH1DSC5CR_LL_b;
29051                 };
29052             };
29053 
29054             union
29055             {
29056                 union
29057                 {
29058                     __IOM uint16_t SQCH1DSC5CR_H; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register                 */
29059 
29060                     struct
29061                     {
29062                         uint16_t               : 6;
29063                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
29064                         uint16_t               : 1;
29065                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
29066                     } SQCH1DSC5CR_H_b;
29067                 };
29068 
29069                 struct
29070                 {
29071                     union
29072                     {
29073                         __IOM uint8_t SQCH1DSC5CR_HL; /*!< (@ 0x0000085A) Sequence Channel 1 Descriptor-5 C Register                 */
29074 
29075                         struct
29076                         {
29077                             uint8_t             : 6;
29078                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
29079                             uint8_t             : 1;
29080                         } SQCH1DSC5CR_HL_b;
29081                     };
29082 
29083                     union
29084                     {
29085                         __IOM uint8_t SQCH1DSC5CR_HH;  /*!< (@ 0x0000085B) Sequence Channel 1 Descriptor-5 C Register                 */
29086 
29087                         struct
29088                         {
29089                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
29090                         } SQCH1DSC5CR_HH_b;
29091                     };
29092                 };
29093             };
29094         };
29095     };
29096 
29097     union
29098     {
29099         union
29100         {
29101             __IOM uint32_t SQCH1DSC5DR;    /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register                 */
29102 
29103             struct
29104             {
29105                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
29106             } SQCH1DSC5DR_b;
29107         };
29108 
29109         struct
29110         {
29111             union
29112             {
29113                 union
29114                 {
29115                     __IOM uint16_t SQCH1DSC5DR_L;  /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register                 */
29116 
29117                     struct
29118                     {
29119                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
29120                     } SQCH1DSC5DR_L_b;
29121                 };
29122 
29123                 struct
29124                 {
29125                     union
29126                     {
29127                         __IOM uint8_t SQCH1DSC5DR_LL; /*!< (@ 0x0000085C) Sequence Channel 1 Descriptor-5 D Register                 */
29128 
29129                         struct
29130                         {
29131                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29132                         } SQCH1DSC5DR_LL_b;
29133                     };
29134 
29135                     union
29136                     {
29137                         __IOM uint8_t SQCH1DSC5DR_LH; /*!< (@ 0x0000085D) Sequence Channel 1 Descriptor-5 D Register                 */
29138 
29139                         struct
29140                         {
29141                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29142                         } SQCH1DSC5DR_LH_b;
29143                     };
29144                 };
29145             };
29146 
29147             union
29148             {
29149                 __IOM uint8_t SQCH1DSC5DR_HL; /*!< (@ 0x0000085E) Sequence Channel 1 Descriptor-5 D Register                 */
29150 
29151                 struct
29152                 {
29153                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29154                 } SQCH1DSC5DR_HL_b;
29155             };
29156 
29157             union
29158             {
29159                 __IOM uint8_t SQCH1DSC5DR_HH; /*!< (@ 0x0000085F) Sequence Channel 1 Descriptor-5 D Register                 */
29160 
29161                 struct
29162                 {
29163                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29164                 } SQCH1DSC5DR_HH_b;
29165             };
29166         };
29167     };
29168 
29169     union
29170     {
29171         union
29172         {
29173             __IOM uint32_t SQCH1DSC6AR;   /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register                 */
29174 
29175             struct
29176             {
29177                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
29178                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
29179                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
29180                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
29181                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
29182                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
29183                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
29184                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
29185                 uint32_t             : 2;
29186             } SQCH1DSC6AR_b;
29187         };
29188 
29189         struct
29190         {
29191             union
29192             {
29193                 union
29194                 {
29195                     __IOM uint16_t SQCH1DSC6AR_L; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register                 */
29196 
29197                     struct
29198                     {
29199                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
29200                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
29201                     } SQCH1DSC6AR_L_b;
29202                 };
29203 
29204                 struct
29205                 {
29206                     union
29207                     {
29208                         __IOM uint8_t SQCH1DSC6AR_LL; /*!< (@ 0x00000860) Sequence Channel 1 Descriptor-6 A Register                 */
29209 
29210                         struct
29211                         {
29212                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
29213                         } SQCH1DSC6AR_LL_b;
29214                     };
29215 
29216                     union
29217                     {
29218                         __IOM uint8_t SQCH1DSC6AR_LH; /*!< (@ 0x00000861) Sequence Channel 1 Descriptor-6 A Register                 */
29219 
29220                         struct
29221                         {
29222                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
29223                         } SQCH1DSC6AR_LH_b;
29224                     };
29225                 };
29226             };
29227 
29228             union
29229             {
29230                 union
29231                 {
29232                     __IOM uint16_t SQCH1DSC6AR_H; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register                 */
29233 
29234                     struct
29235                     {
29236                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
29237                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
29238                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
29239                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
29240                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
29241                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
29242                         uint16_t             : 2;
29243                     } SQCH1DSC6AR_H_b;
29244                 };
29245 
29246                 struct
29247                 {
29248                     union
29249                     {
29250                         __IOM uint8_t SQCH1DSC6AR_HL; /*!< (@ 0x00000862) Sequence Channel 1 Descriptor-6 A Register                 */
29251 
29252                         struct
29253                         {
29254                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
29255                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
29256                         } SQCH1DSC6AR_HL_b;
29257                     };
29258 
29259                     union
29260                     {
29261                         __IOM uint8_t SQCH1DSC6AR_HH; /*!< (@ 0x00000863) Sequence Channel 1 Descriptor-6 A Register                 */
29262 
29263                         struct
29264                         {
29265                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
29266                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
29267                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
29268                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
29269                             uint8_t             : 2;
29270                         } SQCH1DSC6AR_HH_b;
29271                     };
29272                 };
29273             };
29274         };
29275     };
29276 
29277     union
29278     {
29279         __IOM uint32_t SQCH1DSC6BR;    /*!< (@ 0x00000864) Sequence Channel 1 Descriptor-6 B Register                 */
29280 
29281         struct
29282         {
29283             uint32_t             : 24;
29284             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
29285             uint32_t             : 6;
29286         } SQCH1DSC6BR_b;
29287     };
29288 
29289     union
29290     {
29291         union
29292         {
29293             __IOM uint32_t SQCH1DSC6CR;     /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register                 */
29294 
29295             struct
29296             {
29297                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
29298                 uint32_t               : 21;
29299                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
29300                 uint32_t               : 1;
29301                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
29302             } SQCH1DSC6CR_b;
29303         };
29304 
29305         struct
29306         {
29307             union
29308             {
29309                 union
29310                 {
29311                     __IOM uint16_t SQCH1DSC6CR_L;  /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register                 */
29312 
29313                     struct
29314                     {
29315                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
29316                         uint16_t              : 15;
29317                     } SQCH1DSC6CR_L_b;
29318                 };
29319 
29320                 union
29321                 {
29322                     __IOM uint8_t SQCH1DSC6CR_LL; /*!< (@ 0x00000868) Sequence Channel 1 Descriptor-6 C Register                 */
29323 
29324                     struct
29325                     {
29326                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
29327                         uint8_t              : 7;
29328                     } SQCH1DSC6CR_LL_b;
29329                 };
29330             };
29331 
29332             union
29333             {
29334                 union
29335                 {
29336                     __IOM uint16_t SQCH1DSC6CR_H; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register                 */
29337 
29338                     struct
29339                     {
29340                         uint16_t               : 6;
29341                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
29342                         uint16_t               : 1;
29343                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
29344                     } SQCH1DSC6CR_H_b;
29345                 };
29346 
29347                 struct
29348                 {
29349                     union
29350                     {
29351                         __IOM uint8_t SQCH1DSC6CR_HL; /*!< (@ 0x0000086A) Sequence Channel 1 Descriptor-6 C Register                 */
29352 
29353                         struct
29354                         {
29355                             uint8_t             : 6;
29356                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
29357                             uint8_t             : 1;
29358                         } SQCH1DSC6CR_HL_b;
29359                     };
29360 
29361                     union
29362                     {
29363                         __IOM uint8_t SQCH1DSC6CR_HH;  /*!< (@ 0x0000086B) Sequence Channel 1 Descriptor-6 C Register                 */
29364 
29365                         struct
29366                         {
29367                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
29368                         } SQCH1DSC6CR_HH_b;
29369                     };
29370                 };
29371             };
29372         };
29373     };
29374 
29375     union
29376     {
29377         union
29378         {
29379             __IOM uint32_t SQCH1DSC6DR;    /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register                 */
29380 
29381             struct
29382             {
29383                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
29384             } SQCH1DSC6DR_b;
29385         };
29386 
29387         struct
29388         {
29389             union
29390             {
29391                 union
29392                 {
29393                     __IOM uint16_t SQCH1DSC6DR_L;  /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register                 */
29394 
29395                     struct
29396                     {
29397                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
29398                     } SQCH1DSC6DR_L_b;
29399                 };
29400 
29401                 struct
29402                 {
29403                     union
29404                     {
29405                         __IOM uint8_t SQCH1DSC6DR_LL; /*!< (@ 0x0000086C) Sequence Channel 1 Descriptor-6 D Register                 */
29406 
29407                         struct
29408                         {
29409                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29410                         } SQCH1DSC6DR_LL_b;
29411                     };
29412 
29413                     union
29414                     {
29415                         __IOM uint8_t SQCH1DSC6DR_LH; /*!< (@ 0x0000086D) Sequence Channel 1 Descriptor-6 D Register                 */
29416 
29417                         struct
29418                         {
29419                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29420                         } SQCH1DSC6DR_LH_b;
29421                     };
29422                 };
29423             };
29424 
29425             union
29426             {
29427                 __IOM uint8_t SQCH1DSC6DR_HL; /*!< (@ 0x0000086E) Sequence Channel 1 Descriptor-6 D Register                 */
29428 
29429                 struct
29430                 {
29431                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29432                 } SQCH1DSC6DR_HL_b;
29433             };
29434 
29435             union
29436             {
29437                 __IOM uint8_t SQCH1DSC6DR_HH; /*!< (@ 0x0000086F) Sequence Channel 1 Descriptor-6 D Register                 */
29438 
29439                 struct
29440                 {
29441                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29442                 } SQCH1DSC6DR_HH_b;
29443             };
29444         };
29445     };
29446 
29447     union
29448     {
29449         union
29450         {
29451             __IOM uint32_t SQCH1DSC7AR;   /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register                 */
29452 
29453             struct
29454             {
29455                 __IOM uint32_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
29456                 __IOM uint32_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
29457                 __IOM uint32_t DT    : 6; /*!< [21..16] Data Type                                                        */
29458                 __IOM uint32_t VC    : 2; /*!< [23..22] Virtual Channel                                                  */
29459                 __IOM uint32_t FMT   : 1; /*!< [24..24] Format                                                           */
29460                 __IOM uint32_t SPD   : 1; /*!< [25..25] Speed                                                            */
29461                 __IOM uint32_t BTA   : 2; /*!< [27..26] Bus Turn Around                                                  */
29462                 __IOM uint32_t NXACT : 2; /*!< [29..28] Next Action                                                      */
29463                 uint32_t             : 2;
29464             } SQCH1DSC7AR_b;
29465         };
29466 
29467         struct
29468         {
29469             union
29470             {
29471                 union
29472                 {
29473                     __IOM uint16_t SQCH1DSC7AR_L; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register                 */
29474 
29475                     struct
29476                     {
29477                         __IOM uint16_t DATA0 : 8; /*!< [7..0] Data 0                                                             */
29478                         __IOM uint16_t DATA1 : 8; /*!< [15..8] Data 1                                                            */
29479                     } SQCH1DSC7AR_L_b;
29480                 };
29481 
29482                 struct
29483                 {
29484                     union
29485                     {
29486                         __IOM uint8_t SQCH1DSC7AR_LL; /*!< (@ 0x00000870) Sequence Channel 1 Descriptor-7 A Register                 */
29487 
29488                         struct
29489                         {
29490                             __IOM uint8_t DATA0 : 8;  /*!< [7..0] Data 0                                                             */
29491                         } SQCH1DSC7AR_LL_b;
29492                     };
29493 
29494                     union
29495                     {
29496                         __IOM uint8_t SQCH1DSC7AR_LH; /*!< (@ 0x00000871) Sequence Channel 1 Descriptor-7 A Register                 */
29497 
29498                         struct
29499                         {
29500                             __IOM uint8_t DATA1 : 8;  /*!< [7..0] Data 1                                                             */
29501                         } SQCH1DSC7AR_LH_b;
29502                     };
29503                 };
29504             };
29505 
29506             union
29507             {
29508                 union
29509                 {
29510                     __IOM uint16_t SQCH1DSC7AR_H; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register                 */
29511 
29512                     struct
29513                     {
29514                         __IOM uint16_t DT    : 6; /*!< [5..0] Data Type                                                          */
29515                         __IOM uint16_t VC    : 2; /*!< [7..6] Virtual Channel                                                    */
29516                         __IOM uint16_t FMT   : 1; /*!< [8..8] Format                                                             */
29517                         __IOM uint16_t SPD   : 1; /*!< [9..9] Speed                                                              */
29518                         __IOM uint16_t BTA   : 2; /*!< [11..10] Bus Turn Around                                                  */
29519                         __IOM uint16_t NXACT : 2; /*!< [13..12] Next Action                                                      */
29520                         uint16_t             : 2;
29521                     } SQCH1DSC7AR_H_b;
29522                 };
29523 
29524                 struct
29525                 {
29526                     union
29527                     {
29528                         __IOM uint8_t SQCH1DSC7AR_HL; /*!< (@ 0x00000872) Sequence Channel 1 Descriptor-7 A Register                 */
29529 
29530                         struct
29531                         {
29532                             __IOM uint8_t DT : 6;     /*!< [5..0] Data Type                                                          */
29533                             __IOM uint8_t VC : 2;     /*!< [7..6] Virtual Channel                                                    */
29534                         } SQCH1DSC7AR_HL_b;
29535                     };
29536 
29537                     union
29538                     {
29539                         __IOM uint8_t SQCH1DSC7AR_HH; /*!< (@ 0x00000873) Sequence Channel 1 Descriptor-7 A Register                 */
29540 
29541                         struct
29542                         {
29543                             __IOM uint8_t FMT   : 1;  /*!< [0..0] Format                                                             */
29544                             __IOM uint8_t SPD   : 1;  /*!< [1..1] Speed                                                              */
29545                             __IOM uint8_t BTA   : 2;  /*!< [3..2] Bus Turn Around                                                    */
29546                             __IOM uint8_t NXACT : 2;  /*!< [5..4] Next Action                                                        */
29547                             uint8_t             : 2;
29548                         } SQCH1DSC7AR_HH_b;
29549                     };
29550                 };
29551             };
29552         };
29553     };
29554 
29555     union
29556     {
29557         __IOM uint32_t SQCH1DSC7BR;    /*!< (@ 0x00000874) Sequence Channel 1 Descriptor-7 B Register                 */
29558 
29559         struct
29560         {
29561             uint32_t             : 24;
29562             __IOM uint32_t DTSEL : 2;  /*!< [25..24] Data Select                                                      */
29563             uint32_t             : 6;
29564         } SQCH1DSC7BR_b;
29565     };
29566 
29567     union
29568     {
29569         union
29570         {
29571             __IOM uint32_t SQCH1DSC7CR;     /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register                 */
29572 
29573             struct
29574             {
29575                 __IOM uint32_t FINACT  : 1; /*!< [0..0] Finish Action                                                      */
29576                 uint32_t               : 21;
29577                 __IOM uint32_t AUXOP   : 1; /*!< [22..22] Auxiliary Operation                                              */
29578                 uint32_t               : 1;
29579                 __IOM uint32_t ACTCODE : 8; /*!< [31..24] Action Code                                                      */
29580             } SQCH1DSC7CR_b;
29581         };
29582 
29583         struct
29584         {
29585             union
29586             {
29587                 union
29588                 {
29589                     __IOM uint16_t SQCH1DSC7CR_L;  /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register                 */
29590 
29591                     struct
29592                     {
29593                         __IOM uint16_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
29594                         uint16_t              : 15;
29595                     } SQCH1DSC7CR_L_b;
29596                 };
29597 
29598                 union
29599                 {
29600                     __IOM uint8_t SQCH1DSC7CR_LL; /*!< (@ 0x00000878) Sequence Channel 1 Descriptor-7 C Register                 */
29601 
29602                     struct
29603                     {
29604                         __IOM uint8_t FINACT : 1; /*!< [0..0] Finish Action                                                      */
29605                         uint8_t              : 7;
29606                     } SQCH1DSC7CR_LL_b;
29607                 };
29608             };
29609 
29610             union
29611             {
29612                 union
29613                 {
29614                     __IOM uint16_t SQCH1DSC7CR_H; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register                 */
29615 
29616                     struct
29617                     {
29618                         uint16_t               : 6;
29619                         __IOM uint16_t AUXOP   : 1; /*!< [6..6] Auxiliary Operation                                                */
29620                         uint16_t               : 1;
29621                         __IOM uint16_t ACTCODE : 8; /*!< [15..8] Action Code                                                       */
29622                     } SQCH1DSC7CR_H_b;
29623                 };
29624 
29625                 struct
29626                 {
29627                     union
29628                     {
29629                         __IOM uint8_t SQCH1DSC7CR_HL; /*!< (@ 0x0000087A) Sequence Channel 1 Descriptor-7 C Register                 */
29630 
29631                         struct
29632                         {
29633                             uint8_t             : 6;
29634                             __IOM uint8_t AUXOP : 1; /*!< [6..6] Auxiliary Operation                                                */
29635                             uint8_t             : 1;
29636                         } SQCH1DSC7CR_HL_b;
29637                     };
29638 
29639                     union
29640                     {
29641                         __IOM uint8_t SQCH1DSC7CR_HH;  /*!< (@ 0x0000087B) Sequence Channel 1 Descriptor-7 C Register                 */
29642 
29643                         struct
29644                         {
29645                             __IOM uint8_t ACTCODE : 8; /*!< [7..0] Action Code                                                        */
29646                         } SQCH1DSC7CR_HH_b;
29647                     };
29648                 };
29649             };
29650         };
29651     };
29652 
29653     union
29654     {
29655         union
29656         {
29657             __IOM uint32_t SQCH1DSC7DR;    /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register                 */
29658 
29659             struct
29660             {
29661                 __IOM uint32_t LADDR : 32; /*!< [31..0] Lower Address                                                     */
29662             } SQCH1DSC7DR_b;
29663         };
29664 
29665         struct
29666         {
29667             union
29668             {
29669                 union
29670                 {
29671                     __IOM uint16_t SQCH1DSC7DR_L;  /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register                 */
29672 
29673                     struct
29674                     {
29675                         __IOM uint16_t LADDR : 16; /*!< [15..0] Lower Address                                                     */
29676                     } SQCH1DSC7DR_L_b;
29677                 };
29678 
29679                 struct
29680                 {
29681                     union
29682                     {
29683                         __IOM uint8_t SQCH1DSC7DR_LL; /*!< (@ 0x0000087C) Sequence Channel 1 Descriptor-7 D Register                 */
29684 
29685                         struct
29686                         {
29687                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29688                         } SQCH1DSC7DR_LL_b;
29689                     };
29690 
29691                     union
29692                     {
29693                         __IOM uint8_t SQCH1DSC7DR_LH; /*!< (@ 0x0000087D) Sequence Channel 1 Descriptor-7 D Register                 */
29694 
29695                         struct
29696                         {
29697                             __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29698                         } SQCH1DSC7DR_LH_b;
29699                     };
29700                 };
29701             };
29702 
29703             union
29704             {
29705                 __IOM uint8_t SQCH1DSC7DR_HL; /*!< (@ 0x0000087E) Sequence Channel 1 Descriptor-7 D Register                 */
29706 
29707                 struct
29708                 {
29709                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29710                 } SQCH1DSC7DR_HL_b;
29711             };
29712 
29713             union
29714             {
29715                 __IOM uint8_t SQCH1DSC7DR_HH; /*!< (@ 0x0000087F) Sequence Channel 1 Descriptor-7 D Register                 */
29716 
29717                 struct
29718                 {
29719                     __IOM uint8_t LADDR : 8;  /*!< [7..0] Lower Address                                                      */
29720                 } SQCH1DSC7DR_HH_b;
29721             };
29722         };
29723     };
29724 } R_DSILINK_Type;                      /*!< Size = 2176 (0x880)                                                       */
29725 
29726 /* =========================================================================================================================== */
29727 /* ================                                          R_FLAD                                           ================ */
29728 /* =========================================================================================================================== */
29729 
29730 /**
29731  * @brief Data Flash (R_FLAD)
29732  */
29733 
29734 typedef struct                         /*!< (@ 0x4011C000) R_FLAD Structure                                           */
29735 {
29736     __IM uint8_t RESERVED[64];
29737 
29738     union
29739     {
29740         __IOM uint8_t FCKMHZ;          /*!< (@ 0x00000040) Data Flash Access Frequency Register                       */
29741 
29742         struct
29743         {
29744             __IOM uint8_t FCKMHZ : 8;  /*!< [7..0] Data Flash Access Frequency Register                               */
29745         } FCKMHZ_b;
29746     };
29747 } R_FLAD_Type;                         /*!< Size = 65 (0x41)                                                          */
29748 
29749 /* =========================================================================================================================== */
29750 /* ================                                      R_OFS_DATAFLASH                                      ================ */
29751 /* =========================================================================================================================== */
29752 
29753 /**
29754  * @brief Data Flash Option-Setting Memory (R_OFS_DATAFLASH)
29755  */
29756 
29757 typedef struct                         /*!< (@ 0x27030000) R_OFS_DATAFLASH Structure                                  */
29758 {
29759     __IM uint32_t RESERVED[32];
29760 
29761     union
29762     {
29763         __IM uint32_t FSBLCTRL0;          /*!< (@ 0x00000080) FSBL Control Register 0                                    */
29764 
29765         struct
29766         {
29767             __IM uint32_t FSBLEN     : 3; /*!< [2..0] FSBL Enable                                                        */
29768             __IM uint32_t FSBLSKIPSW : 3; /*!< [5..3] FSBL Skip Enable for Software Reset                                */
29769             __IM uint32_t FSBLSKIPDS : 3; /*!< [8..6] FSBL Skip Enable for Deep Software Standby Reset                   */
29770             __IM uint32_t FSBLCLK    : 3; /*!< [11..9] Clock Frequency Selection during FSBL Execution                   */
29771             uint32_t                 : 20;
29772         } FSBLCTRL0_b;
29773     };
29774 
29775     union
29776     {
29777         __IM uint32_t FSBLCTRL1;        /*!< (@ 0x00000084) FSBL Control Register 1                                    */
29778 
29779         struct
29780         {
29781             __IM uint32_t FSBLEXMD : 2; /*!< [1..0] FSBL Execution Mode                                                */
29782             uint32_t               : 30;
29783         } FSBLCTRL1_b;
29784     };
29785 
29786     union
29787     {
29788         __IM uint32_t FSBLCTRL2;                  /*!< (@ 0x00000088) FSBL Control Register 2                                    */
29789 
29790         struct
29791         {
29792             __IM uint32_t PORTPN : 4;             /*!< [3..0] FSBL Error Notification Port Pin Number                            */
29793             __IM uint32_t PORTGN : 5;             /*!< [8..4] FSBL Error Notification Port Group Name                            */
29794             uint32_t             : 23;
29795         } FSBLCTRL2_b;
29796     };
29797     __IOM uint32_t SACC0;                         /*!< (@ 0x0000008C) Start Address of Code Certification 0                      */
29798     __IOM uint32_t SACC1;                         /*!< (@ 0x00000090) Start Address of Code Certification 1                      */
29799     __IOM uint32_t SAMR;                          /*!< (@ 0x00000094) Start Address of Measurement Report                        */
29800     __IM uint32_t  RESERVED1[178];
29801     __IM uint32_t  HOEMRTPK;                      /*!< (@ 0x00000360) Hask of OEM_ROOT_PK                                        */
29802     __IM uint32_t  RESERVED2[7];
29803     __IOM R_OFS_DATAFLASH_CFGDLOCK_Type CFGDLOCK; /*!< (@ 0x00000380) Configuration Data Lock Bits                               */
29804     __IM uint32_t RESERVED3[11];
29805 
29806     union
29807     {
29808         __IOM uint16_t ARCLS;            /*!< (@ 0x000003C0) Anti-Rollback Counter Lock Setting                         */
29809 
29810         struct
29811         {
29812             __IOM uint16_t ARCS_LK  : 1; /*!< [0..0] ARC_SEC Lock                                                       */
29813             __IOM uint16_t ARCNS_LK : 4; /*!< [4..1] ARC_NSEC Lock                                                      */
29814             __IOM uint16_t ARCBL_LK : 1; /*!< [5..5] ARC_OEMBL Lock                                                     */
29815             uint16_t                : 10;
29816         } ARCLS_b;
29817     };
29818 
29819     union
29820     {
29821         __IOM uint16_t ARCCS;             /*!< (@ 0x000003C2) ARCCS                                                      */
29822 
29823         struct
29824         {
29825             __IOM uint16_t CNF_ARCNS : 2; /*!< [1..0] Configuation setting for ARC_NSEC                                  */
29826             uint16_t                 : 14;
29827         } ARCCS_b;
29828     };
29829     __IM uint32_t RESERVED4[291];
29830 
29831     union
29832     {
29833         __IOM uint32_t ARC_SEC[2];       /*!< (@ 0x00000850) Anti-Rollback Counter for Secure Application
29834                                           *                  n                                                          */
29835 
29836         struct
29837         {
29838             __IOM uint32_t ARC_SEC : 32; /*!< [31..0] ARC_SEC                                                           */
29839         } ARC_SEC_b[2];
29840     };
29841 
29842     union
29843     {
29844         __IOM uint32_t ARC_NSEC[8];       /*!< (@ 0x00000858) Anti-Rollback Counter for Non-Secure Application           */
29845 
29846         struct
29847         {
29848             __IOM uint32_t ARC_NSEC : 32; /*!< [31..0] Anti-Rollback Counter for Non-secure Application                  */
29849         } ARC_NSEC_b[8];
29850     };
29851 
29852     union
29853     {
29854         __IOM uint32_t ARC_OEMBL[2];       /*!< (@ 0x00000878) Anti-Rollback Counter for OEMBL                            */
29855 
29856         struct
29857         {
29858             __IOM uint32_t ARC_OEMBL : 32; /*!< [31..0] Anti-Rollback Counter for OEM_BL Application                      */
29859         } ARC_OEMBL_b[2];
29860     };
29861 } R_OFS_DATAFLASH_Type;                    /*!< Size = 2176 (0x880)                                                       */
29862 
29863 /** @} */ /* End of group Device_Peripheral_peripherals */
29864 
29865 /* =========================================================================================================================== */
29866 /* ================                          Device Specific Peripheral Address Map                           ================ */
29867 /* =========================================================================================================================== */
29868 
29869 /** @addtogroup Device_Peripheral_peripheralAddr
29870  * @{
29871  */
29872 
29873  #if defined(_RA_TZ_NONSECURE)
29874   #define BASE_NS_OFFSET         (BSP_FEATURE_TZ_NS_OFFSET)
29875  #else
29876   #define BASE_NS_OFFSET         0U
29877  #endif
29878 
29879  #define R_ACMPHS0_BASE          (0x40236000UL + BASE_NS_OFFSET)
29880  #define R_ACMPHS1_BASE          (0x40236100UL + BASE_NS_OFFSET)
29881  #define R_ACMPHS2_BASE          (0x40236200UL + BASE_NS_OFFSET)
29882  #define R_ACMPHS3_BASE          (0x40236300UL + BASE_NS_OFFSET)
29883  #define R_ACMPHS4_BASE          (0x40236400UL + BASE_NS_OFFSET)
29884  #define R_ACMPHS5_BASE          (0x40236500UL + BASE_NS_OFFSET)
29885  #define R_ADC0_BASE             (0x40332000UL + BASE_NS_OFFSET)
29886  #define R_ADC1_BASE             (0x40332200UL + BASE_NS_OFFSET)
29887  #define R_PSCU_BASE             (0x40204000UL + BASE_NS_OFFSET)
29888  #define R_BUS_BASE              (0x40003000UL + BASE_NS_OFFSET)
29889  #define R_CAC_BASE              (0x40202400UL + BASE_NS_OFFSET)
29890  #define R_CANFD_BASE            (0x40380000UL + BASE_NS_OFFSET)
29891  #define R_CANFD1_BASE           (0x40382000UL + BASE_NS_OFFSET)
29892  #define R_CRC_BASE              (0x40310000UL + BASE_NS_OFFSET)
29893  #define R_DAC_BASE              (0x40333000UL + BASE_NS_OFFSET)
29894  #define R_DAC1_BASE             (0x40333100UL + BASE_NS_OFFSET)
29895  #define R_DEBUG_BASE            (0x4001B000UL + BASE_NS_OFFSET)
29896  #define R_DMA_BASE              (0x4000A800UL + BASE_NS_OFFSET)
29897  #define R_DMAC0_BASE            (0x4000A000UL + BASE_NS_OFFSET)
29898  #define R_DMAC1_BASE            (0x4000A040UL + BASE_NS_OFFSET)
29899  #define R_DMAC2_BASE            (0x4000A080UL + BASE_NS_OFFSET)
29900  #define R_DMAC3_BASE            (0x4000A0C0UL + BASE_NS_OFFSET)
29901  #define R_DMAC4_BASE            (0x4000A100UL + BASE_NS_OFFSET)
29902  #define R_DMAC5_BASE            (0x4000A140UL + BASE_NS_OFFSET)
29903  #define R_DMAC6_BASE            (0x4000A180UL + BASE_NS_OFFSET)
29904  #define R_DMAC7_BASE            (0x4000A1C0UL + BASE_NS_OFFSET)
29905  #define R_DOC_BASE              (0x40311000UL + BASE_NS_OFFSET)
29906  #define R_DRW_BASE              (0x40344000UL + BASE_NS_OFFSET)
29907  #define R_DTC_BASE              (0x4000AC00UL + BASE_NS_OFFSET)
29908  #define R_ELC_BASE              (0x40201000UL + BASE_NS_OFFSET)
29909  #define R_ETHERC0_BASE          (0x40354100UL + BASE_NS_OFFSET)
29910  #define R_ETHERC_EDMAC_BASE     (0x40354000UL + BASE_NS_OFFSET)
29911  #define R_FACI_HP_CMD_BASE      (0x40100000UL + BASE_NS_OFFSET)
29912  #define R_FACI_HP_BASE          (0x4011E000UL + BASE_NS_OFFSET)
29913  #define R_FCACHE_BASE           (0x4001C100UL + BASE_NS_OFFSET)
29914  #define R_GLCDC_BASE            (0x40342000UL + BASE_NS_OFFSET)
29915  #define R_GPT0_BASE             (0x40322000UL + BASE_NS_OFFSET)
29916  #define R_GPT1_BASE             (0x40322100UL + BASE_NS_OFFSET)
29917  #define R_GPT2_BASE             (0x40322200UL + BASE_NS_OFFSET)
29918  #define R_GPT3_BASE             (0x40322300UL + BASE_NS_OFFSET)
29919  #define R_GPT4_BASE             (0x40322400UL + BASE_NS_OFFSET)
29920  #define R_GPT5_BASE             (0x40322500UL + BASE_NS_OFFSET)
29921  #define R_GPT6_BASE             (0x40322600UL + BASE_NS_OFFSET)
29922  #define R_GPT7_BASE             (0x40322700UL + BASE_NS_OFFSET)
29923  #define R_GPT8_BASE             (0x40322800UL + BASE_NS_OFFSET)
29924  #define R_GPT9_BASE             (0x40322900UL + BASE_NS_OFFSET)
29925  #define R_GPT10_BASE            (0x40322A00UL + BASE_NS_OFFSET)
29926  #define R_GPT11_BASE            (0x40322B00UL + BASE_NS_OFFSET)
29927  #define R_GPT12_BASE            (0x40322C00UL + BASE_NS_OFFSET)
29928  #define R_GPT13_BASE            (0x40322D00UL + BASE_NS_OFFSET)
29929  #define R_GPT_OPS_BASE          (0x40323F00UL + BASE_NS_OFFSET)
29930  #define R_GPT_POEG0_BASE        (0x40212000UL + BASE_NS_OFFSET)
29931  #define R_GPT_POEG1_BASE        (0x40212100UL + BASE_NS_OFFSET)
29932  #define R_GPT_POEG2_BASE        (0x40212200UL + BASE_NS_OFFSET)
29933  #define R_GPT_POEG3_BASE        (0x40212300UL + BASE_NS_OFFSET)
29934  #define R_ICU_BASE              (0x40006000UL + BASE_NS_OFFSET)
29935  #define R_IIC0_BASE             (0x4025E000UL + BASE_NS_OFFSET)
29936  #define R_IIC1_BASE             (0x4025E100UL + BASE_NS_OFFSET)
29937  #define R_IIC2_BASE             (0x4025E200UL + BASE_NS_OFFSET)
29938  #define R_IWDT_BASE             (0x40202200UL + BASE_NS_OFFSET)
29939  #define R_I3C0_BASE             (0x4035F000UL + BASE_NS_OFFSET)
29940  #define R_I3C1_BASE             (0x4035F100UL + BASE_NS_OFFSET)
29941  #define R_MPU_MMPU_BASE         (0x40000000UL + BASE_NS_OFFSET)
29942  #define R_MPU_SPMON_BASE        (0x40000D00UL + BASE_NS_OFFSET)
29943  #define R_MSTP_BASE             (0x40203000UL + BASE_NS_OFFSET)
29944  #define R_PORT0_BASE            (0x40400000UL + BASE_NS_OFFSET)
29945  #define R_PORT1_BASE            (0x40400020UL + BASE_NS_OFFSET)
29946  #define R_PORT2_BASE            (0x40400040UL + BASE_NS_OFFSET)
29947  #define R_PORT3_BASE            (0x40400060UL + BASE_NS_OFFSET)
29948  #define R_PORT4_BASE            (0x40400080UL + BASE_NS_OFFSET)
29949  #define R_PORT5_BASE            (0x404000A0UL + BASE_NS_OFFSET)
29950  #define R_PORT6_BASE            (0x404000C0UL + BASE_NS_OFFSET)
29951  #define R_PORT7_BASE            (0x404000E0UL + BASE_NS_OFFSET)
29952  #define R_PORT8_BASE            (0x40400100UL + BASE_NS_OFFSET)
29953  #define R_PORT9_BASE            (0x40400120UL + BASE_NS_OFFSET)
29954  #define R_PORT10_BASE           (0x40400140UL + BASE_NS_OFFSET)
29955  #define R_PORT11_BASE           (0x40400160UL + BASE_NS_OFFSET)
29956  #define R_PORT12_BASE           (0x40400180UL + BASE_NS_OFFSET)
29957  #define R_PORT13_BASE           (0x404001A0UL + BASE_NS_OFFSET)
29958  #define R_PORT14_BASE           (0x404001C0UL + BASE_NS_OFFSET)
29959  #define R_PFS_BASE              (0x40400800UL + BASE_NS_OFFSET)
29960  #define R_PMISC_BASE            (0x40400D00UL + BASE_NS_OFFSET)
29961  #define R_RTC_BASE              (0x40202000UL + BASE_NS_OFFSET)
29962  #define R_SCI0_BASE             (0x40358000UL + BASE_NS_OFFSET)
29963  #define R_SCI1_BASE             (0x40358100UL + BASE_NS_OFFSET)
29964  #define R_SCI2_BASE             (0x40358200UL + BASE_NS_OFFSET)
29965  #define R_SCI3_BASE             (0x40358300UL + BASE_NS_OFFSET)
29966  #define R_SCI4_BASE             (0x40358400UL + BASE_NS_OFFSET)
29967  #define R_SCI5_BASE             (0x40358500UL + BASE_NS_OFFSET)
29968  #define R_SCI6_BASE             (0x40358600UL + BASE_NS_OFFSET)
29969  #define R_SCI7_BASE             (0x40358700UL + BASE_NS_OFFSET)
29970  #define R_SCI8_BASE             (0x40358800UL + BASE_NS_OFFSET)
29971  #define R_SCI9_BASE             (0x40358900UL + BASE_NS_OFFSET)
29972  #define R_SDHI0_BASE            (0x40252000UL + BASE_NS_OFFSET)
29973  #define R_SDHI1_BASE            (0x40252400UL + BASE_NS_OFFSET)
29974  #define R_SPI0_BASE             (0x4035C000UL + BASE_NS_OFFSET)
29975  #define R_SPI1_BASE             (0x4035C100UL + BASE_NS_OFFSET)
29976  #define R_SRAM_BASE             (0x40002000UL + BASE_NS_OFFSET)
29977  #define R_SSI0_BASE             (0x4025D000UL + BASE_NS_OFFSET)
29978  #define R_SSI1_BASE             (0x4025D100UL + BASE_NS_OFFSET)
29979  #define R_SYSTEM_BASE           (0x4001E000UL + BASE_NS_OFFSET)
29980  #define R_TSN_CAL_BASE          (0x4011B17CUL + BASE_NS_OFFSET)
29981  #define R_TSN_CTRL_BASE         (0x40235000UL + BASE_NS_OFFSET)
29982  #define R_USB_FS0_BASE          (0x40250000UL + BASE_NS_OFFSET)
29983  #define R_WDT_BASE              (0x40202600UL + BASE_NS_OFFSET)
29984  #define R_TZF_BASE              (0x40004000UL + BASE_NS_OFFSET)
29985  #define R_CPSCU_BASE            (0x40008000UL + BASE_NS_OFFSET)
29986  #define R_DOC_B_BASE            (0x40311000UL + BASE_NS_OFFSET)
29987  #define R_SCI_B0_BASE           (0x40358000UL + BASE_NS_OFFSET)
29988  #define R_SCI_B1_BASE           (0x40358100UL + BASE_NS_OFFSET)
29989  #define R_SCI_B2_BASE           (0x40358200UL + BASE_NS_OFFSET)
29990  #define R_SCI_B3_BASE           (0x40358300UL + BASE_NS_OFFSET)
29991  #define R_SCI_B4_BASE           (0x40358400UL + BASE_NS_OFFSET)
29992  #define R_SCI_B9_BASE           (0x40358900UL + BASE_NS_OFFSET)
29993  #define R_SPI_B0_BASE           (0x4035C000UL + BASE_NS_OFFSET)
29994  #define R_SPI_B1_BASE           (0x4035C100UL + BASE_NS_OFFSET)
29995  #define R_USB_HS0_BASE          (0x40351000UL + BASE_NS_OFFSET)
29996  #define R_XSPI_BASE             (0x40268000UL + BASE_NS_OFFSET)
29997  #define R_CEU_BASE              (0x40348000UL + BASE_NS_OFFSET)
29998  #define R_ULPT0_BASE            (0x40220000UL + BASE_NS_OFFSET)
29999  #define R_ULPT1_BASE            (0x40220100UL + BASE_NS_OFFSET)
30000  #define R_DEBUG_OCD_BASE        (0x40011000UL + BASE_NS_OFFSET)
30001  #define R_DOTF_BASE             (0x40268800UL + BASE_NS_OFFSET)
30002  #define R_AGTX0_BASE            (0x40221000UL + BASE_NS_OFFSET)
30003  #define R_AGTX1_BASE            (0x40221100UL + BASE_NS_OFFSET)
30004  #define R_AGTX2_BASE            (0x40221200UL + BASE_NS_OFFSET)
30005  #define R_AGTX3_BASE            (0x40221300UL + BASE_NS_OFFSET)
30006  #define R_AGTX4_BASE            (0x40221400UL + BASE_NS_OFFSET)
30007  #define R_AGTX5_BASE            (0x40221500UL + BASE_NS_OFFSET)
30008  #define R_AGTX6_BASE            (0x40221600UL + BASE_NS_OFFSET)
30009  #define R_AGTX7_BASE            (0x40221700UL + BASE_NS_OFFSET)
30010  #define R_AGTX8_BASE            (0x40221800UL + BASE_NS_OFFSET)
30011  #define R_AGTX9_BASE            (0x40221900UL + BASE_NS_OFFSET)
30012  #define R_DPHYCNT_BASE          (0x40346C00UL + BASE_NS_OFFSET)
30013  #define R_DSILINK_BASE          (0x40346000UL + BASE_NS_OFFSET)
30014  #define R_FLAD_BASE             (0x4011C000UL + BASE_NS_OFFSET)
30015  #define R_OFS_DATAFLASH_BASE    (0x27030000UL + BASE_NS_OFFSET)
30016 
30017 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
30018 
30019 /* =========================================================================================================================== */
30020 /* ================                                  Peripheral declaration                                   ================ */
30021 /* =========================================================================================================================== */
30022 
30023 /** @addtogroup Device_Peripheral_declaration
30024  * @{
30025  */
30026 
30027  #define R_ACMPHS0          ((R_ACMPHS0_Type *) R_ACMPHS0_BASE)
30028  #define R_ACMPHS1          ((R_ACMPHS0_Type *) R_ACMPHS1_BASE)
30029  #define R_ACMPHS2          ((R_ACMPHS0_Type *) R_ACMPHS2_BASE)
30030  #define R_ACMPHS3          ((R_ACMPHS0_Type *) R_ACMPHS3_BASE)
30031  #define R_ACMPHS4          ((R_ACMPHS0_Type *) R_ACMPHS4_BASE)
30032  #define R_ACMPHS5          ((R_ACMPHS0_Type *) R_ACMPHS5_BASE)
30033  #define R_ADC0             ((R_ADC0_Type *) R_ADC0_BASE)
30034  #define R_ADC1             ((R_ADC0_Type *) R_ADC1_BASE)
30035  #define R_PSCU             ((R_PSCU_Type *) R_PSCU_BASE)
30036  #define R_BUS              ((R_BUS_Type *) R_BUS_BASE)
30037  #define R_CAC              ((R_CAC_Type *) R_CAC_BASE)
30038  #define R_CANFD            ((R_CANFD_Type *) R_CANFD_BASE)
30039  #define R_CANFD0           ((R_CANFD_Type *) R_CANFD_BASE)
30040  #define R_CANFD1           ((R_CANFD_Type *) R_CANFD1_BASE)
30041  #define R_CRC              ((R_CRC_Type *) R_CRC_BASE)
30042  #define R_DAC              ((R_DAC_Type *) R_DAC_BASE)
30043  #define R_DAC1             ((R_DAC_Type *) R_DAC1_BASE)
30044  #define R_DEBUG            ((R_DEBUG_Type *) R_DEBUG_BASE)
30045  #define R_DMA              ((R_DMA_Type *) R_DMA_BASE)
30046  #define R_DMAC0            ((R_DMAC0_Type *) R_DMAC0_BASE)
30047  #define R_DMAC1            ((R_DMAC0_Type *) R_DMAC1_BASE)
30048  #define R_DMAC2            ((R_DMAC0_Type *) R_DMAC2_BASE)
30049  #define R_DMAC3            ((R_DMAC0_Type *) R_DMAC3_BASE)
30050  #define R_DMAC4            ((R_DMAC0_Type *) R_DMAC4_BASE)
30051  #define R_DMAC5            ((R_DMAC0_Type *) R_DMAC5_BASE)
30052  #define R_DMAC6            ((R_DMAC0_Type *) R_DMAC6_BASE)
30053  #define R_DMAC7            ((R_DMAC0_Type *) R_DMAC7_BASE)
30054  #define R_DOC              ((R_DOC_Type *) R_DOC_BASE)
30055  #define R_DRW              ((R_DRW_Type *) R_DRW_BASE)
30056  #define R_DTC              ((R_DTC_Type *) R_DTC_BASE)
30057  #define R_ELC              ((R_ELC_Type *) R_ELC_BASE)
30058  #define R_ETHERC0          ((R_ETHERC0_Type *) R_ETHERC0_BASE)
30059  #define R_ETHERC_EDMAC     ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
30060  #define R_FACI_HP_CMD      ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
30061  #define R_FACI_HP          ((R_FACI_HP_Type *) R_FACI_HP_BASE)
30062  #define R_FCACHE           ((R_FCACHE_Type *) R_FCACHE_BASE)
30063  #define R_GLCDC            ((R_GLCDC_Type *) R_GLCDC_BASE)
30064  #define R_GPT0             ((R_GPT0_Type *) R_GPT0_BASE)
30065  #define R_GPT1             ((R_GPT0_Type *) R_GPT1_BASE)
30066  #define R_GPT2             ((R_GPT0_Type *) R_GPT2_BASE)
30067  #define R_GPT3             ((R_GPT0_Type *) R_GPT3_BASE)
30068  #define R_GPT4             ((R_GPT0_Type *) R_GPT4_BASE)
30069  #define R_GPT5             ((R_GPT0_Type *) R_GPT5_BASE)
30070  #define R_GPT6             ((R_GPT0_Type *) R_GPT6_BASE)
30071  #define R_GPT7             ((R_GPT0_Type *) R_GPT7_BASE)
30072  #define R_GPT8             ((R_GPT0_Type *) R_GPT8_BASE)
30073  #define R_GPT9             ((R_GPT0_Type *) R_GPT9_BASE)
30074  #define R_GPT10            ((R_GPT0_Type *) R_GPT10_BASE)
30075  #define R_GPT11            ((R_GPT0_Type *) R_GPT11_BASE)
30076  #define R_GPT12            ((R_GPT0_Type *) R_GPT12_BASE)
30077  #define R_GPT13            ((R_GPT0_Type *) R_GPT13_BASE)
30078  #define R_GPT_OPS          ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
30079  #define R_GPT_POEG0        ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
30080  #define R_GPT_POEG1        ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
30081  #define R_GPT_POEG2        ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
30082  #define R_GPT_POEG3        ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
30083  #define R_ICU              ((R_ICU_Type *) R_ICU_BASE)
30084  #define R_IIC0             ((R_IIC0_Type *) R_IIC0_BASE)
30085  #define R_IIC1             ((R_IIC0_Type *) R_IIC1_BASE)
30086  #define R_IIC2             ((R_IIC0_Type *) R_IIC2_BASE)
30087  #define R_IWDT             ((R_IWDT_Type *) R_IWDT_BASE)
30088  #define R_I3C0             ((R_I3C0_Type *) R_I3C0_BASE)
30089  #define R_I3C1             ((R_I3C0_Type *) R_I3C1_BASE)
30090  #define R_MPU_MMPU         ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
30091  #define R_MPU_SPMON        ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
30092  #define R_MSTP             ((R_MSTP_Type *) R_MSTP_BASE)
30093  #define R_PORT0            ((R_PORT0_Type *) R_PORT0_BASE)
30094  #define R_PORT1            ((R_PORT0_Type *) R_PORT1_BASE)
30095  #define R_PORT2            ((R_PORT0_Type *) R_PORT2_BASE)
30096  #define R_PORT3            ((R_PORT0_Type *) R_PORT3_BASE)
30097  #define R_PORT4            ((R_PORT0_Type *) R_PORT4_BASE)
30098  #define R_PORT5            ((R_PORT0_Type *) R_PORT5_BASE)
30099  #define R_PORT6            ((R_PORT0_Type *) R_PORT6_BASE)
30100  #define R_PORT7            ((R_PORT0_Type *) R_PORT7_BASE)
30101  #define R_PORT8            ((R_PORT0_Type *) R_PORT8_BASE)
30102  #define R_PORT9            ((R_PORT0_Type *) R_PORT9_BASE)
30103  #define R_PORT10           ((R_PORT0_Type *) R_PORT10_BASE)
30104  #define R_PORT11           ((R_PORT0_Type *) R_PORT11_BASE)
30105  #define R_PORT12           ((R_PORT0_Type *) R_PORT12_BASE)
30106  #define R_PORT13           ((R_PORT0_Type *) R_PORT13_BASE)
30107  #define R_PORT14           ((R_PORT0_Type *) R_PORT14_BASE)
30108  #define R_PFS              ((R_PFS_Type *) R_PFS_BASE)
30109  #define R_PMISC            ((R_PMISC_Type *) R_PMISC_BASE)
30110  #define R_RTC              ((R_RTC_Type *) R_RTC_BASE)
30111  #define R_SCI0             ((R_SCI0_Type *) R_SCI0_BASE)
30112  #define R_SCI1             ((R_SCI0_Type *) R_SCI1_BASE)
30113  #define R_SCI2             ((R_SCI0_Type *) R_SCI2_BASE)
30114  #define R_SCI3             ((R_SCI0_Type *) R_SCI3_BASE)
30115  #define R_SCI4             ((R_SCI0_Type *) R_SCI4_BASE)
30116  #define R_SCI5             ((R_SCI0_Type *) R_SCI5_BASE)
30117  #define R_SCI6             ((R_SCI0_Type *) R_SCI6_BASE)
30118  #define R_SCI7             ((R_SCI0_Type *) R_SCI7_BASE)
30119  #define R_SCI8             ((R_SCI0_Type *) R_SCI8_BASE)
30120  #define R_SCI9             ((R_SCI0_Type *) R_SCI9_BASE)
30121  #define R_SDHI0            ((R_SDHI0_Type *) R_SDHI0_BASE)
30122  #define R_SDHI1            ((R_SDHI0_Type *) R_SDHI1_BASE)
30123  #define R_SPI0             ((R_SPI0_Type *) R_SPI0_BASE)
30124  #define R_SPI1             ((R_SPI0_Type *) R_SPI1_BASE)
30125  #define R_SRAM             ((R_SRAM_Type *) R_SRAM_BASE)
30126  #define R_SSI0             ((R_SSI0_Type *) R_SSI0_BASE)
30127  #define R_SSI1             ((R_SSI0_Type *) R_SSI1_BASE)
30128  #define R_SYSTEM           ((R_SYSTEM_Type *) R_SYSTEM_BASE)
30129  #define R_TSN_CAL          ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
30130  #define R_TSN_CTRL         ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
30131  #define R_USB_FS0          ((R_USB_FS0_Type *) R_USB_FS0_BASE)
30132  #define R_WDT              ((R_WDT_Type *) R_WDT_BASE)
30133  #define R_TZF              ((R_TZF_Type *) R_TZF_BASE)
30134  #define R_CPSCU            ((R_CPSCU_Type *) R_CPSCU_BASE)
30135  #define R_DOC_B            ((R_DOC_B_Type *) R_DOC_B_BASE)
30136  #define R_SCI_B0           ((R_SCI_B0_Type *) R_SCI_B0_BASE)
30137  #define R_SCI_B1           ((R_SCI_B0_Type *) R_SCI_B1_BASE)
30138  #define R_SCI_B2           ((R_SCI_B0_Type *) R_SCI_B2_BASE)
30139  #define R_SCI_B3           ((R_SCI_B0_Type *) R_SCI_B3_BASE)
30140  #define R_SCI_B4           ((R_SCI_B0_Type *) R_SCI_B4_BASE)
30141  #define R_SCI_B9           ((R_SCI_B0_Type *) R_SCI_B9_BASE)
30142  #define R_SPI_B0           ((R_SPI_B0_Type *) R_SPI_B0_BASE)
30143  #define R_SPI_B1           ((R_SPI_B0_Type *) R_SPI_B1_BASE)
30144  #define R_USB_HS0          ((R_USB_HS0_Type *) R_USB_HS0_BASE)
30145  #define R_XSPI             ((R_XSPI_Type *) R_XSPI_BASE)
30146  #define R_CEU              ((R_CEU_Type *) R_CEU_BASE)
30147  #define R_ULPT0            ((R_ULPT0_Type *) R_ULPT0_BASE)
30148  #define R_ULPT1            ((R_ULPT0_Type *) R_ULPT1_BASE)
30149  #define R_DEBUG_OCD        ((R_DEBUG_OCD_Type *) R_DEBUG_OCD_BASE)
30150  #define R_DOTF             ((R_DOTF_Type *) R_DOTF_BASE)
30151  #define R_AGT0             ((R_AGTX0_Type *) R_AGTX0_BASE)
30152  #define R_AGT1             ((R_AGTX0_Type *) R_AGTX1_BASE)
30153  #define R_AGT2             ((R_AGTX0_Type *) R_AGTX2_BASE)
30154  #define R_AGT3             ((R_AGTX0_Type *) R_AGTX3_BASE)
30155  #define R_AGT4             ((R_AGTX0_Type *) R_AGTX4_BASE)
30156  #define R_AGT5             ((R_AGTX0_Type *) R_AGTX5_BASE)
30157  #define R_AGT6             ((R_AGTX0_Type *) R_AGTX6_BASE)
30158  #define R_AGT7             ((R_AGTX0_Type *) R_AGTX7_BASE)
30159  #define R_AGT8             ((R_AGTX0_Type *) R_AGTX8_BASE)
30160  #define R_AGT9             ((R_AGTX0_Type *) R_AGTX9_BASE)
30161  #define R_DPHYCNT          ((R_DPHYCNT_Type *) R_DPHYCNT_BASE)
30162  #define R_DSILINK          ((R_DSILINK_Type *) R_DSILINK_BASE)
30163  #define R_FLAD             ((R_FLAD_Type *) R_FLAD_BASE)
30164  #define R_OFS_DATAFLASH    ((R_OFS_DATAFLASH_Type *) R_OFS_DATAFLASH_BASE)
30165 
30166 /** @} */ /* End of group Device_Peripheral_declaration */
30167 
30168 /* =========================================  End of section using anonymous unions  ========================================= */
30169  #if defined(__CC_ARM)
30170   #pragma pop
30171  #elif defined(__ICCARM__)
30172 
30173 /* leave anonymous unions enabled */
30174  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
30175   #pragma clang diagnostic pop
30176  #elif defined(__GNUC__)
30177 
30178 /* anonymous unions are enabled by default */
30179  #elif defined(__TMS470__)
30180 
30181 /* anonymous unions are enabled by default */
30182  #elif defined(__TASKING__)
30183   #pragma warning restore
30184  #elif defined(__CSMC__)
30185 
30186 /* anonymous unions are enabled by default */
30187  #endif
30188 
30189 /* =========================================================================================================================== */
30190 /* ================                                 Pos/Mask Cluster Section                                  ================ */
30191 /* =========================================================================================================================== */
30192 
30193 /** @addtogroup PosMask_clusters
30194  * @{
30195  */
30196 
30197 /* =========================================================================================================================== */
30198 /* ================                                            CSa                                            ================ */
30199 /* =========================================================================================================================== */
30200 
30201 /* ==========================================================  MOD  ========================================================== */
30202  #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
30203  #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
30204  #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
30205  #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
30206  #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
30207  #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
30208  #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
30209  #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
30210  #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
30211  #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
30212 /* =========================================================  WCR1  ========================================================== */
30213  #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
30214  #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
30215  #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
30216  #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
30217  #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
30218  #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
30219  #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
30220  #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
30221 /* =========================================================  WCR2  ========================================================== */
30222  #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
30223  #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
30224  #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
30225  #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
30226  #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
30227  #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
30228  #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
30229  #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
30230  #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
30231  #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
30232  #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
30233  #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
30234  #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
30235  #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
30236  #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
30237  #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
30238 
30239 /* =========================================================================================================================== */
30240 /* ================                                            CSb                                            ================ */
30241 /* =========================================================================================================================== */
30242 
30243 /* ==========================================================  CR  =========================================================== */
30244  #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
30245  #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
30246  #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
30247  #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
30248  #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
30249  #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
30250  #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
30251  #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
30252 /* ==========================================================  REC  ========================================================== */
30253  #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
30254  #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
30255  #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
30256  #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
30257 
30258 /* =========================================================================================================================== */
30259 /* ================                                           SDRAM                                           ================ */
30260 /* =========================================================================================================================== */
30261 
30262 /* =========================================================  SDCCR  ========================================================= */
30263  #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
30264  #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
30265  #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
30266  #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
30267 /* ========================================================  SDCMOD  ========================================================= */
30268  #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
30269  #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
30270 /* ========================================================  SDAMOD  ========================================================= */
30271  #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
30272  #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
30273 /* ========================================================  SDSELF  ========================================================= */
30274  #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
30275  #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
30276 /* ========================================================  SDRFCR  ========================================================= */
30277  #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
30278  #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
30279  #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
30280  #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
30281 /* ========================================================  SDRFEN  ========================================================= */
30282  #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
30283  #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
30284 /* =========================================================  SDICR  ========================================================= */
30285  #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
30286  #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
30287 /* =========================================================  SDIR  ========================================================== */
30288  #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
30289  #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
30290  #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
30291  #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
30292  #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
30293  #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
30294 /* =========================================================  SDADR  ========================================================= */
30295  #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
30296  #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
30297 /* =========================================================  SDTR  ========================================================== */
30298  #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
30299  #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
30300  #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
30301  #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
30302  #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
30303  #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
30304  #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
30305  #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
30306  #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
30307  #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
30308 /* =========================================================  SDMOD  ========================================================= */
30309  #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
30310  #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
30311 /* =========================================================  SDSR  ========================================================== */
30312  #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
30313  #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
30314  #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
30315  #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
30316  #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
30317  #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
30318 
30319 /* =========================================================================================================================== */
30320 /* ================                                          BUSERRa                                          ================ */
30321 /* =========================================================================================================================== */
30322 
30323 /* ==========================================================  ADD  ========================================================== */
30324  #define R_BUS_BUSERRa_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
30325  #define R_BUS_BUSERRa_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
30326 /* =========================================================  STAT  ========================================================== */
30327  #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
30328  #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
30329  #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
30330  #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
30331 /* ==========================================================  RW  =========================================================== */
30332  #define R_BUS_BUSERRa_RW_RWSTAT_Pos       (0UL)          /*!< RWSTAT (Bit 0)                                        */
30333  #define R_BUS_BUSERRa_RW_RWSTAT_Msk       (0x1UL)        /*!< RWSTAT (Bitfield-Mask: 0x01)                          */
30334 
30335 /* =========================================================================================================================== */
30336 /* ================                                          BTZFERR                                          ================ */
30337 /* =========================================================================================================================== */
30338 
30339 /* ==========================================================  ADD  ========================================================== */
30340  #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos    (0UL)          /*!< BTZFERAD (Bit 0)                                      */
30341  #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk    (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff)                  */
30342 /* ==========================================================  RW  =========================================================== */
30343  #define R_BUS_BTZFERR_RW_TRWSTAT_Pos      (0UL)          /*!< TRWSTAT (Bit 0)                                       */
30344  #define R_BUS_BTZFERR_RW_TRWSTAT_Msk      (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */
30345 
30346 /* =========================================================================================================================== */
30347 /* ================                                          BUSERRb                                          ================ */
30348 /* =========================================================================================================================== */
30349 
30350 /* =========================================================  STAT  ========================================================== */
30351  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos    (5UL)    /*!< MSERRSTAT (Bit 5)                                     */
30352  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk    (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01)                       */
30353  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos    (4UL)    /*!< ILERRSTAT (Bit 4)                                     */
30354  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk    (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
30355  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos    (3UL)    /*!< MMERRSTAT (Bit 3)                                     */
30356  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk    (0x8UL)  /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
30357  #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos    (1UL)    /*!< STERRSTAT (Bit 1)                                     */
30358  #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk    (0x2UL)  /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
30359  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos    (0UL)    /*!< SLERRSTAT (Bit 0)                                     */
30360  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk    (0x1UL)  /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
30361 /* ==========================================================  CLR  ========================================================== */
30362  #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos      (5UL)    /*!< MSERRCLR (Bit 5)                                      */
30363  #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk      (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01)                        */
30364  #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos      (4UL)    /*!< ILERRCLR (Bit 4)                                      */
30365  #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk      (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
30366  #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos      (3UL)    /*!< MMERRCLR (Bit 3)                                      */
30367  #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk      (0x8UL)  /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
30368  #define R_BUS_BUSERRb_CLR_STERRCLR_Pos      (1UL)    /*!< STERRCLR (Bit 1)                                      */
30369  #define R_BUS_BUSERRb_CLR_STERRCLR_Msk      (0x2UL)  /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
30370  #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos      (0UL)    /*!< SLERRCLR (Bit 0)                                      */
30371  #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk      (0x1UL)  /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
30372 
30373 /* =========================================================================================================================== */
30374 /* ================                                        DMACDTCERR                                         ================ */
30375 /* =========================================================================================================================== */
30376 
30377 /* =========================================================  STAT  ========================================================== */
30378  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos    (0UL)   /*!< MTERRSTAT (Bit 0)                                     */
30379  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk    (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01)                       */
30380 /* ==========================================================  CLR  ========================================================== */
30381  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos      (0UL)   /*!< MTERRCLR (Bit 0)                                      */
30382  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk      (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01)                        */
30383 
30384 /* =========================================================================================================================== */
30385 /* ================                                         BUSSABT0                                          ================ */
30386 /* =========================================================================================================================== */
30387 
30388 /* =========================================================  FLBI  ========================================================== */
30389  #define R_BUS_BUSSABT0_FLBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30390  #define R_BUS_BUSSABT0_FLBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30391 /* ========================================================  MRE0BI  ========================================================= */
30392  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
30393  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30394 /* =========================================================  S0BI  ========================================================== */
30395  #define R_BUS_BUSSABT0_S0BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30396  #define R_BUS_BUSSABT0_S0BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30397 /* =========================================================  S1BI  ========================================================== */
30398  #define R_BUS_BUSSABT0_S1BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30399  #define R_BUS_BUSSABT0_S1BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30400 /* =========================================================  S2BI  ========================================================== */
30401  #define R_BUS_BUSSABT0_S2BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30402  #define R_BUS_BUSSABT0_S2BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30403 /* =========================================================  S3BI  ========================================================== */
30404  #define R_BUS_BUSSABT0_S3BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30405  #define R_BUS_BUSSABT0_S3BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30406 /* ========================================================  STBYSBI  ======================================================== */
30407  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
30408  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk      (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30409 /* =========================================================  ECBI  ========================================================== */
30410  #define R_BUS_BUSSABT0_ECBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30411  #define R_BUS_BUSSABT0_ECBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30412 /* =========================================================  EOBI  ========================================================== */
30413  #define R_BUS_BUSSABT0_EOBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30414  #define R_BUS_BUSSABT0_EOBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30415 /* ========================================================  SPI0BI  ========================================================= */
30416  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
30417  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30418 /* ========================================================  SPI1BI  ========================================================= */
30419  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
30420  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30421 /* =========================================================  PBBI  ========================================================== */
30422  #define R_BUS_BUSSABT0_PBBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30423  #define R_BUS_BUSSABT0_PBBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30424 /* =========================================================  PABI  ========================================================== */
30425  #define R_BUS_BUSSABT0_PABI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30426  #define R_BUS_BUSSABT0_PABI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30427 /* =========================================================  PIBI  ========================================================== */
30428  #define R_BUS_BUSSABT0_PIBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30429  #define R_BUS_BUSSABT0_PIBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30430 /* =========================================================  PSBI  ========================================================== */
30431  #define R_BUS_BUSSABT0_PSBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
30432  #define R_BUS_BUSSABT0_PSBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30433 /* =======================================================  CPU0SAHBI  ======================================================= */
30434  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
30435  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30436 /* =======================================================  CPU1TCMBI  ======================================================= */
30437  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
30438  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
30439 
30440 /* =========================================================================================================================== */
30441 /* ================                                         BUSSABT1                                          ================ */
30442 /* =========================================================================================================================== */
30443 
30444 /* =========================================================  FHBI  ========================================================== */
30445  #define R_BUS_BUSSABT1_FHBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
30446  #define R_BUS_BUSSABT1_FHBI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
30447 /* ========================================================  MRC0BI  ========================================================= */
30448  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
30449  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk    (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
30450 /* =========================================================  S0BI  ========================================================== */
30451  #define R_BUS_BUSSABT1_S0BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
30452  #define R_BUS_BUSSABT1_S0BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
30453 /* =========================================================  S1BI  ========================================================== */
30454  #define R_BUS_BUSSABT1_S1BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
30455  #define R_BUS_BUSSABT1_S1BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
30456 
30457 /* =========================================================================================================================== */
30458 /* ================                                          BMSAERR                                          ================ */
30459 /* =========================================================================================================================== */
30460 
30461 /* ==========================================================  ADD  ========================================================== */
30462  #define R_BUS_BMSAERR_ADD_MSERAD_Pos      (0UL)          /*!< MSERAD (Bit 0)                                        */
30463  #define R_BUS_BMSAERR_ADD_MSERAD_Msk      (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff)                    */
30464 /* ==========================================================  RW  =========================================================== */
30465  #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos    (0UL)          /*!< MSARWSTAT (Bit 0)                                     */
30466  #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk    (0x1UL)        /*!< MSARWSTAT (Bitfield-Mask: 0x01)                       */
30467 
30468 /* =========================================================================================================================== */
30469 /* ================                                            OAD                                            ================ */
30470 /* =========================================================================================================================== */
30471 
30472 /* ========================================================  BUSOAD  ========================================================= */
30473  #define R_BUS_OAD_BUSOAD_BWERROAD_Pos     (2UL)      /*!< BWERROAD (Bit 2)                                      */
30474  #define R_BUS_OAD_BUSOAD_BWERROAD_Msk     (0x4UL)    /*!< BWERROAD (Bitfield-Mask: 0x01)                        */
30475  #define R_BUS_OAD_BUSOAD_SLERROAD_Pos     (1UL)      /*!< SLERROAD (Bit 1)                                      */
30476  #define R_BUS_OAD_BUSOAD_SLERROAD_Msk     (0x2UL)    /*!< SLERROAD (Bitfield-Mask: 0x01)                        */
30477  #define R_BUS_OAD_BUSOAD_ILERROAD_Pos     (0UL)      /*!< ILERROAD (Bit 0)                                      */
30478  #define R_BUS_OAD_BUSOAD_ILERROAD_Msk     (0x1UL)    /*!< ILERROAD (Bitfield-Mask: 0x01)                        */
30479 /* =======================================================  BUSOADPT  ======================================================== */
30480  #define R_BUS_OAD_BUSOADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
30481  #define R_BUS_OAD_BUSOADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
30482  #define R_BUS_OAD_BUSOADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
30483  #define R_BUS_OAD_BUSOADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
30484 /* ========================================================  MSAOAD  ========================================================= */
30485  #define R_BUS_OAD_MSAOAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
30486  #define R_BUS_OAD_MSAOAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
30487  #define R_BUS_OAD_MSAOAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
30488  #define R_BUS_OAD_MSAOAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
30489 /* =========================================================  MSAPT  ========================================================= */
30490  #define R_BUS_OAD_MSAPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
30491  #define R_BUS_OAD_MSAPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
30492  #define R_BUS_OAD_MSAPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
30493  #define R_BUS_OAD_MSAPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
30494 
30495 /* =========================================================================================================================== */
30496 /* ================                                          MBWERR                                           ================ */
30497 /* =========================================================================================================================== */
30498 
30499 /* =========================================================  STAT  ========================================================== */
30500  #define R_BUS_MBWERR_STAT_BWERR_Pos    (0UL)   /*!< BWERR (Bit 0)                                         */
30501  #define R_BUS_MBWERR_STAT_BWERR_Msk    (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
30502 /* ==========================================================  CLR  ========================================================== */
30503  #define R_BUS_MBWERR_CLR_BWERR_Pos     (0UL)   /*!< BWERR (Bit 0)                                         */
30504  #define R_BUS_MBWERR_CLR_BWERR_Msk     (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
30505 
30506 /* =========================================================================================================================== */
30507 /* ================                                           BUSM                                            ================ */
30508 /* =========================================================================================================================== */
30509 
30510 /* ==========================================================  CNT  ========================================================== */
30511  #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
30512  #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
30513 
30514 /* =========================================================================================================================== */
30515 /* ================                                           BUSS                                            ================ */
30516 /* =========================================================================================================================== */
30517 
30518 /* ==========================================================  CNT  ========================================================== */
30519  #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
30520  #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
30521  #define R_BUS_BUSS_CNT_ARBS_Pos      (0UL)    /*!< ARBS (Bit 0)                                          */
30522  #define R_BUS_BUSS_CNT_ARBS_Msk      (0x3UL)  /*!< ARBS (Bitfield-Mask: 0x03)                            */
30523 
30524 /* =========================================================================================================================== */
30525 /* ================                                           CFDC                                            ================ */
30526 /* =========================================================================================================================== */
30527 
30528 /* =========================================================  NCFG  ========================================================== */
30529  #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
30530  #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
30531  #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
30532  #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
30533  #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
30534  #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
30535  #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
30536  #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
30537 /* ==========================================================  CTR  ========================================================== */
30538  #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
30539  #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
30540  #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
30541  #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
30542  #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
30543  #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
30544  #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
30545  #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
30546  #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
30547  #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
30548  #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
30549  #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
30550  #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
30551  #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
30552  #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
30553  #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
30554  #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
30555  #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
30556  #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
30557  #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
30558  #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
30559  #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
30560  #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
30561  #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
30562  #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
30563  #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
30564  #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
30565  #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
30566  #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
30567  #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
30568  #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
30569  #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
30570  #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
30571  #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
30572  #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
30573  #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
30574  #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
30575  #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
30576  #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
30577  #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
30578  #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
30579  #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
30580 /* ==========================================================  STS  ========================================================== */
30581  #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
30582  #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
30583  #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
30584  #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
30585  #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
30586  #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
30587  #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
30588  #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
30589  #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
30590  #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
30591  #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
30592  #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
30593  #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
30594  #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
30595  #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
30596  #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
30597  #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
30598  #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
30599  #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
30600  #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
30601  #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
30602  #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
30603 /* =========================================================  ERFL  ========================================================== */
30604  #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
30605  #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
30606  #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
30607  #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
30608  #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
30609  #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
30610  #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
30611  #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
30612  #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
30613  #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
30614  #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
30615  #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
30616  #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
30617  #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
30618  #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
30619  #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
30620  #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
30621  #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
30622  #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
30623  #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
30624  #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
30625  #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
30626  #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
30627  #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
30628  #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
30629  #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
30630  #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
30631  #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
30632  #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
30633  #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
30634  #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
30635  #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
30636 
30637 /* =========================================================================================================================== */
30638 /* ================                                           CFDC2                                           ================ */
30639 /* =========================================================================================================================== */
30640 
30641 /* =========================================================  DCFG  ========================================================== */
30642  #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
30643  #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
30644  #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
30645  #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
30646  #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
30647  #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
30648  #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
30649  #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
30650 /* =========================================================  FDCFG  ========================================================= */
30651  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
30652  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
30653  #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
30654  #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
30655  #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
30656  #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
30657  #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
30658  #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
30659  #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
30660  #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
30661  #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
30662  #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
30663  #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
30664  #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
30665  #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
30666  #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
30667 /* =========================================================  FDCTR  ========================================================= */
30668  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
30669  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
30670  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
30671  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
30672 /* =========================================================  FDSTS  ========================================================= */
30673  #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
30674  #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
30675  #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
30676  #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
30677  #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
30678  #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
30679  #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
30680  #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
30681  #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
30682  #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
30683  #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
30684  #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
30685 /* =========================================================  FDCRC  ========================================================= */
30686  #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
30687  #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
30688  #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
30689  #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */
30690 
30691 /* =========================================================================================================================== */
30692 /* ================                                          CFDGAFL                                          ================ */
30693 /* =========================================================================================================================== */
30694 
30695 /* ==========================================================  ID  =========================================================== */
30696  #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
30697  #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
30698  #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
30699  #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
30700  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
30701  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
30702  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
30703  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
30704 /* ===========================================================  M  =========================================================== */
30705  #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
30706  #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
30707  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
30708  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
30709  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
30710  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
30711  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
30712  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
30713 /* ==========================================================  P0  =========================================================== */
30714  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
30715  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
30716  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
30717  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
30718  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
30719  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
30720  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
30721  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
30722  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
30723  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
30724 /* ==========================================================  P1  =========================================================== */
30725  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
30726  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x1ffUL)      /*!< GAFLFDP (Bitfield-Mask: 0x1ff)                        */
30727 
30728 /* =========================================================================================================================== */
30729 /* ================                                          CFDTHL                                           ================ */
30730 /* =========================================================================================================================== */
30731 
30732 /* =========================================================  ACC0  ========================================================== */
30733  #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
30734  #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
30735  #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
30736  #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
30737  #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
30738  #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
30739 /* =========================================================  ACC1  ========================================================== */
30740  #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
30741  #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
30742  #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
30743  #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
30744 
30745 /* =========================================================================================================================== */
30746 /* ================                                           CFDRF                                           ================ */
30747 /* =========================================================================================================================== */
30748 
30749 /* ==========================================================  ID  =========================================================== */
30750  #define R_CANFD_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
30751  #define R_CANFD_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
30752  #define R_CANFD_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
30753  #define R_CANFD_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
30754  #define R_CANFD_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
30755  #define R_CANFD_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
30756 /* ==========================================================  PTR  ========================================================== */
30757  #define R_CANFD_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
30758  #define R_CANFD_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
30759  #define R_CANFD_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
30760  #define R_CANFD_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
30761 /* =========================================================  FDSTS  ========================================================= */
30762  #define R_CANFD_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
30763  #define R_CANFD_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
30764  #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
30765  #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
30766  #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
30767  #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
30768  #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
30769  #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
30770  #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
30771  #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
30772 /* ==========================================================  DF  =========================================================== */
30773  #define R_CANFD_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
30774  #define R_CANFD_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
30775 
30776 /* =========================================================================================================================== */
30777 /* ================                                           CFDCF                                           ================ */
30778 /* =========================================================================================================================== */
30779 
30780 /* ==========================================================  ID  =========================================================== */
30781  #define R_CANFD_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
30782  #define R_CANFD_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
30783  #define R_CANFD_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
30784  #define R_CANFD_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
30785  #define R_CANFD_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
30786  #define R_CANFD_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
30787 /* ==========================================================  PTR  ========================================================== */
30788  #define R_CANFD_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
30789  #define R_CANFD_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
30790  #define R_CANFD_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
30791  #define R_CANFD_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
30792 /* =========================================================  FDSTS  ========================================================= */
30793  #define R_CANFD_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
30794  #define R_CANFD_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
30795  #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
30796  #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
30797  #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
30798  #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
30799  #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
30800  #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
30801  #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
30802  #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
30803 /* ==========================================================  DF  =========================================================== */
30804  #define R_CANFD_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
30805  #define R_CANFD_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
30806 
30807 /* =========================================================================================================================== */
30808 /* ================                                           CFDTM                                           ================ */
30809 /* =========================================================================================================================== */
30810 
30811 /* ==========================================================  ID  =========================================================== */
30812  #define R_CANFD_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
30813  #define R_CANFD_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
30814  #define R_CANFD_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
30815  #define R_CANFD_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
30816  #define R_CANFD_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
30817  #define R_CANFD_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
30818 /* ==========================================================  PTR  ========================================================== */
30819  #define R_CANFD_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
30820  #define R_CANFD_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
30821  #define R_CANFD_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
30822  #define R_CANFD_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
30823 /* =========================================================  FDCTR  ========================================================= */
30824  #define R_CANFD_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
30825  #define R_CANFD_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
30826  #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
30827  #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
30828  #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
30829  #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
30830  #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
30831  #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
30832  #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
30833  #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
30834 /* ==========================================================  DF  =========================================================== */
30835  #define R_CANFD_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
30836  #define R_CANFD_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
30837 
30838 /* =========================================================================================================================== */
30839 /* ================                                            RM                                             ================ */
30840 /* =========================================================================================================================== */
30841 
30842 /* ==========================================================  ID  =========================================================== */
30843  #define R_CANFD_CFDRM_RM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
30844  #define R_CANFD_CFDRM_RM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
30845  #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
30846  #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
30847  #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
30848  #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
30849 /* ==========================================================  PTR  ========================================================== */
30850  #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
30851  #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
30852  #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
30853  #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
30854 /* =========================================================  FDSTS  ========================================================= */
30855  #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
30856  #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
30857  #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
30858  #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
30859  #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
30860  #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
30861  #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
30862  #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
30863  #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
30864  #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
30865 /* ==========================================================  DF  =========================================================== */
30866  #define R_CANFD_CFDRM_RM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
30867  #define R_CANFD_CFDRM_RM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
30868 
30869 /* =========================================================================================================================== */
30870 /* ================                                           CFDRM                                           ================ */
30871 /* =========================================================================================================================== */
30872 
30873 /* =========================================================================================================================== */
30874 /* ================                                          ELSEGR                                           ================ */
30875 /* =========================================================================================================================== */
30876 
30877 /* ==========================================================  BY  =========================================================== */
30878  #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
30879  #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
30880  #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
30881  #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
30882  #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
30883  #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
30884 
30885 /* =========================================================================================================================== */
30886 /* ================                                           ELSR                                            ================ */
30887 /* =========================================================================================================================== */
30888 
30889 /* ==========================================================  HA  =========================================================== */
30890  #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
30891  #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
30892 
30893 /* =========================================================================================================================== */
30894 /* ================                                            BG                                             ================ */
30895 /* =========================================================================================================================== */
30896 
30897 /* ==========================================================  EN  =========================================================== */
30898  #define R_GLCDC_BG_EN_SWRST_Pos     (16UL)        /*!< SWRST (Bit 16)                                        */
30899  #define R_GLCDC_BG_EN_SWRST_Msk     (0x10000UL)   /*!< SWRST (Bitfield-Mask: 0x01)                           */
30900  #define R_GLCDC_BG_EN_VEN_Pos       (8UL)         /*!< VEN (Bit 8)                                           */
30901  #define R_GLCDC_BG_EN_VEN_Msk       (0x100UL)     /*!< VEN (Bitfield-Mask: 0x01)                             */
30902  #define R_GLCDC_BG_EN_EN_Pos        (0UL)         /*!< EN (Bit 0)                                            */
30903  #define R_GLCDC_BG_EN_EN_Msk        (0x1UL)       /*!< EN (Bitfield-Mask: 0x01)                              */
30904 /* =========================================================  PERI  ========================================================== */
30905  #define R_GLCDC_BG_PERI_FV_Pos      (16UL)        /*!< FV (Bit 16)                                           */
30906  #define R_GLCDC_BG_PERI_FV_Msk      (0x7ff0000UL) /*!< FV (Bitfield-Mask: 0x7ff)                             */
30907  #define R_GLCDC_BG_PERI_FH_Pos      (0UL)         /*!< FH (Bit 0)                                            */
30908  #define R_GLCDC_BG_PERI_FH_Msk      (0x7ffUL)     /*!< FH (Bitfield-Mask: 0x7ff)                             */
30909 /* =========================================================  SYNC  ========================================================== */
30910  #define R_GLCDC_BG_SYNC_VP_Pos      (16UL)        /*!< VP (Bit 16)                                           */
30911  #define R_GLCDC_BG_SYNC_VP_Msk      (0xf0000UL)   /*!< VP (Bitfield-Mask: 0x0f)                              */
30912  #define R_GLCDC_BG_SYNC_HP_Pos      (0UL)         /*!< HP (Bit 0)                                            */
30913  #define R_GLCDC_BG_SYNC_HP_Msk      (0xfUL)       /*!< HP (Bitfield-Mask: 0x0f)                              */
30914 /* =========================================================  VSIZE  ========================================================= */
30915  #define R_GLCDC_BG_VSIZE_VP_Pos     (16UL)        /*!< VP (Bit 16)                                           */
30916  #define R_GLCDC_BG_VSIZE_VP_Msk     (0x7ff0000UL) /*!< VP (Bitfield-Mask: 0x7ff)                             */
30917  #define R_GLCDC_BG_VSIZE_VW_Pos     (0UL)         /*!< VW (Bit 0)                                            */
30918  #define R_GLCDC_BG_VSIZE_VW_Msk     (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
30919 /* =========================================================  HSIZE  ========================================================= */
30920  #define R_GLCDC_BG_HSIZE_HP_Pos     (16UL)        /*!< HP (Bit 16)                                           */
30921  #define R_GLCDC_BG_HSIZE_HP_Msk     (0x7ff0000UL) /*!< HP (Bitfield-Mask: 0x7ff)                             */
30922  #define R_GLCDC_BG_HSIZE_HW_Pos     (0UL)         /*!< HW (Bit 0)                                            */
30923  #define R_GLCDC_BG_HSIZE_HW_Msk     (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
30924 /* ==========================================================  BGC  ========================================================== */
30925  #define R_GLCDC_BG_BGC_R_Pos        (16UL)        /*!< R (Bit 16)                                            */
30926  #define R_GLCDC_BG_BGC_R_Msk        (0xff0000UL)  /*!< R (Bitfield-Mask: 0xff)                               */
30927  #define R_GLCDC_BG_BGC_G_Pos        (8UL)         /*!< G (Bit 8)                                             */
30928  #define R_GLCDC_BG_BGC_G_Msk        (0xff00UL)    /*!< G (Bitfield-Mask: 0xff)                               */
30929  #define R_GLCDC_BG_BGC_B_Pos        (0UL)         /*!< B (Bit 0)                                             */
30930  #define R_GLCDC_BG_BGC_B_Msk        (0xffUL)      /*!< B (Bitfield-Mask: 0xff)                               */
30931 /* ==========================================================  MON  ========================================================== */
30932  #define R_GLCDC_BG_MON_SWRST_Pos    (16UL)        /*!< SWRST (Bit 16)                                        */
30933  #define R_GLCDC_BG_MON_SWRST_Msk    (0x10000UL)   /*!< SWRST (Bitfield-Mask: 0x01)                           */
30934  #define R_GLCDC_BG_MON_VEN_Pos      (8UL)         /*!< VEN (Bit 8)                                           */
30935  #define R_GLCDC_BG_MON_VEN_Msk      (0x100UL)     /*!< VEN (Bitfield-Mask: 0x01)                             */
30936  #define R_GLCDC_BG_MON_EN_Pos       (0UL)         /*!< EN (Bit 0)                                            */
30937  #define R_GLCDC_BG_MON_EN_Msk       (0x1UL)       /*!< EN (Bitfield-Mask: 0x01)                              */
30938 
30939 /* =========================================================================================================================== */
30940 /* ================                                            GR                                             ================ */
30941 /* =========================================================================================================================== */
30942 
30943 /* ==========================================================  VEN  ========================================================== */
30944  #define R_GLCDC_GR_VEN_PVEN_Pos         (0UL)          /*!< PVEN (Bit 0)                                          */
30945  #define R_GLCDC_GR_VEN_PVEN_Msk         (0x1UL)        /*!< PVEN (Bitfield-Mask: 0x01)                            */
30946 /* =========================================================  FLMRD  ========================================================= */
30947  #define R_GLCDC_GR_FLMRD_RENB_Pos       (0UL)          /*!< RENB (Bit 0)                                          */
30948  #define R_GLCDC_GR_FLMRD_RENB_Msk       (0x1UL)        /*!< RENB (Bitfield-Mask: 0x01)                            */
30949 /* =========================================================  FLM1  ========================================================== */
30950  #define R_GLCDC_GR_FLM1_BSTMD_Pos       (0UL)          /*!< BSTMD (Bit 0)                                         */
30951  #define R_GLCDC_GR_FLM1_BSTMD_Msk       (0x3UL)        /*!< BSTMD (Bitfield-Mask: 0x03)                           */
30952 /* =========================================================  FLM2  ========================================================== */
30953  #define R_GLCDC_GR_FLM2_BASE_Pos        (0UL)          /*!< BASE (Bit 0)                                          */
30954  #define R_GLCDC_GR_FLM2_BASE_Msk        (0xffffffffUL) /*!< BASE (Bitfield-Mask: 0xffffffff)                      */
30955 /* =========================================================  FLM3  ========================================================== */
30956  #define R_GLCDC_GR_FLM3_LNOFF_Pos       (16UL)         /*!< LNOFF (Bit 16)                                        */
30957  #define R_GLCDC_GR_FLM3_LNOFF_Msk       (0xffff0000UL) /*!< LNOFF (Bitfield-Mask: 0xffff)                         */
30958 /* =========================================================  FLM5  ========================================================== */
30959  #define R_GLCDC_GR_FLM5_LNNUM_Pos       (16UL)         /*!< LNNUM (Bit 16)                                        */
30960  #define R_GLCDC_GR_FLM5_LNNUM_Msk       (0x7ff0000UL)  /*!< LNNUM (Bitfield-Mask: 0x7ff)                          */
30961  #define R_GLCDC_GR_FLM5_DATANUM_Pos     (0UL)          /*!< DATANUM (Bit 0)                                       */
30962  #define R_GLCDC_GR_FLM5_DATANUM_Msk     (0xffffUL)     /*!< DATANUM (Bitfield-Mask: 0xffff)                       */
30963 /* =========================================================  FLM6  ========================================================== */
30964  #define R_GLCDC_GR_FLM6_FORMAT_Pos      (28UL)         /*!< FORMAT (Bit 28)                                       */
30965  #define R_GLCDC_GR_FLM6_FORMAT_Msk      (0x70000000UL) /*!< FORMAT (Bitfield-Mask: 0x07)                          */
30966 /* ==========================================================  AB1  ========================================================== */
30967  #define R_GLCDC_GR_AB1_ARCON_Pos        (12UL)         /*!< ARCON (Bit 12)                                        */
30968  #define R_GLCDC_GR_AB1_ARCON_Msk        (0x1000UL)     /*!< ARCON (Bitfield-Mask: 0x01)                           */
30969  #define R_GLCDC_GR_AB1_ARCDISPON_Pos    (8UL)          /*!< ARCDISPON (Bit 8)                                     */
30970  #define R_GLCDC_GR_AB1_ARCDISPON_Msk    (0x100UL)      /*!< ARCDISPON (Bitfield-Mask: 0x01)                       */
30971  #define R_GLCDC_GR_AB1_GRCDISPON_Pos    (4UL)          /*!< GRCDISPON (Bit 4)                                     */
30972  #define R_GLCDC_GR_AB1_GRCDISPON_Msk    (0x10UL)       /*!< GRCDISPON (Bitfield-Mask: 0x01)                       */
30973  #define R_GLCDC_GR_AB1_DISPSEL_Pos      (0UL)          /*!< DISPSEL (Bit 0)                                       */
30974  #define R_GLCDC_GR_AB1_DISPSEL_Msk      (0x3UL)        /*!< DISPSEL (Bitfield-Mask: 0x03)                         */
30975 /* ==========================================================  AB2  ========================================================== */
30976  #define R_GLCDC_GR_AB2_GRCVS_Pos        (16UL)         /*!< GRCVS (Bit 16)                                        */
30977  #define R_GLCDC_GR_AB2_GRCVS_Msk        (0x7ff0000UL)  /*!< GRCVS (Bitfield-Mask: 0x7ff)                          */
30978  #define R_GLCDC_GR_AB2_GRCVW_Pos        (0UL)          /*!< GRCVW (Bit 0)                                         */
30979  #define R_GLCDC_GR_AB2_GRCVW_Msk        (0x7ffUL)      /*!< GRCVW (Bitfield-Mask: 0x7ff)                          */
30980 /* ==========================================================  AB3  ========================================================== */
30981  #define R_GLCDC_GR_AB3_GRCHS_Pos        (16UL)         /*!< GRCHS (Bit 16)                                        */
30982  #define R_GLCDC_GR_AB3_GRCHS_Msk        (0x7ff0000UL)  /*!< GRCHS (Bitfield-Mask: 0x7ff)                          */
30983  #define R_GLCDC_GR_AB3_GRCHW_Pos        (0UL)          /*!< GRCHW (Bit 0)                                         */
30984  #define R_GLCDC_GR_AB3_GRCHW_Msk        (0x7ffUL)      /*!< GRCHW (Bitfield-Mask: 0x7ff)                          */
30985 /* ==========================================================  AB4  ========================================================== */
30986  #define R_GLCDC_GR_AB4_ARCVS_Pos        (16UL)         /*!< ARCVS (Bit 16)                                        */
30987  #define R_GLCDC_GR_AB4_ARCVS_Msk        (0x7ff0000UL)  /*!< ARCVS (Bitfield-Mask: 0x7ff)                          */
30988  #define R_GLCDC_GR_AB4_ARCVW_Pos        (0UL)          /*!< ARCVW (Bit 0)                                         */
30989  #define R_GLCDC_GR_AB4_ARCVW_Msk        (0x7ffUL)      /*!< ARCVW (Bitfield-Mask: 0x7ff)                          */
30990 /* ==========================================================  AB5  ========================================================== */
30991  #define R_GLCDC_GR_AB5_ARCHS_Pos        (16UL)         /*!< ARCHS (Bit 16)                                        */
30992  #define R_GLCDC_GR_AB5_ARCHS_Msk        (0x7ff0000UL)  /*!< ARCHS (Bitfield-Mask: 0x7ff)                          */
30993  #define R_GLCDC_GR_AB5_ARCHW_Pos        (0UL)          /*!< ARCHW (Bit 0)                                         */
30994  #define R_GLCDC_GR_AB5_ARCHW_Msk        (0x7ffUL)      /*!< ARCHW (Bitfield-Mask: 0x7ff)                          */
30995 /* ==========================================================  AB6  ========================================================== */
30996  #define R_GLCDC_GR_AB6_ARCCOEF_Pos      (16UL)         /*!< ARCCOEF (Bit 16)                                      */
30997  #define R_GLCDC_GR_AB6_ARCCOEF_Msk      (0x1ff0000UL)  /*!< ARCCOEF (Bitfield-Mask: 0x1ff)                        */
30998  #define R_GLCDC_GR_AB6_ARCRATE_Pos      (0UL)          /*!< ARCRATE (Bit 0)                                       */
30999  #define R_GLCDC_GR_AB6_ARCRATE_Msk      (0xffUL)       /*!< ARCRATE (Bitfield-Mask: 0xff)                         */
31000 /* ==========================================================  AB7  ========================================================== */
31001  #define R_GLCDC_GR_AB7_ARCDEF_Pos       (16UL)         /*!< ARCDEF (Bit 16)                                       */
31002  #define R_GLCDC_GR_AB7_ARCDEF_Msk       (0xff0000UL)   /*!< ARCDEF (Bitfield-Mask: 0xff)                          */
31003  #define R_GLCDC_GR_AB7_CKON_Pos         (0UL)          /*!< CKON (Bit 0)                                          */
31004  #define R_GLCDC_GR_AB7_CKON_Msk         (0x1UL)        /*!< CKON (Bitfield-Mask: 0x01)                            */
31005 /* ==========================================================  AB8  ========================================================== */
31006  #define R_GLCDC_GR_AB8_CKKG_Pos         (16UL)         /*!< CKKG (Bit 16)                                         */
31007  #define R_GLCDC_GR_AB8_CKKG_Msk         (0xff0000UL)   /*!< CKKG (Bitfield-Mask: 0xff)                            */
31008  #define R_GLCDC_GR_AB8_CKKB_Pos         (8UL)          /*!< CKKB (Bit 8)                                          */
31009  #define R_GLCDC_GR_AB8_CKKB_Msk         (0xff00UL)     /*!< CKKB (Bitfield-Mask: 0xff)                            */
31010  #define R_GLCDC_GR_AB8_CKKR_Pos         (0UL)          /*!< CKKR (Bit 0)                                          */
31011  #define R_GLCDC_GR_AB8_CKKR_Msk         (0xffUL)       /*!< CKKR (Bitfield-Mask: 0xff)                            */
31012 /* ==========================================================  AB9  ========================================================== */
31013  #define R_GLCDC_GR_AB9_CKA_Pos          (24UL)         /*!< CKA (Bit 24)                                          */
31014  #define R_GLCDC_GR_AB9_CKA_Msk          (0xff000000UL) /*!< CKA (Bitfield-Mask: 0xff)                             */
31015  #define R_GLCDC_GR_AB9_CKG_Pos          (16UL)         /*!< CKG (Bit 16)                                          */
31016  #define R_GLCDC_GR_AB9_CKG_Msk          (0xff0000UL)   /*!< CKG (Bitfield-Mask: 0xff)                             */
31017  #define R_GLCDC_GR_AB9_CKB_Pos          (8UL)          /*!< CKB (Bit 8)                                           */
31018  #define R_GLCDC_GR_AB9_CKB_Msk          (0xff00UL)     /*!< CKB (Bitfield-Mask: 0xff)                             */
31019  #define R_GLCDC_GR_AB9_CKR_Pos          (0UL)          /*!< CKR (Bit 0)                                           */
31020  #define R_GLCDC_GR_AB9_CKR_Msk          (0xffUL)       /*!< CKR (Bitfield-Mask: 0xff)                             */
31021 /* =========================================================  BASE  ========================================================== */
31022  #define R_GLCDC_GR_BASE_G_Pos           (16UL)         /*!< G (Bit 16)                                            */
31023  #define R_GLCDC_GR_BASE_G_Msk           (0xff0000UL)   /*!< G (Bitfield-Mask: 0xff)                               */
31024  #define R_GLCDC_GR_BASE_B_Pos           (8UL)          /*!< B (Bit 8)                                             */
31025  #define R_GLCDC_GR_BASE_B_Msk           (0xff00UL)     /*!< B (Bitfield-Mask: 0xff)                               */
31026  #define R_GLCDC_GR_BASE_R_Pos           (0UL)          /*!< R (Bit 0)                                             */
31027  #define R_GLCDC_GR_BASE_R_Msk           (0xffUL)       /*!< R (Bitfield-Mask: 0xff)                               */
31028 /* ========================================================  CLUTINT  ======================================================== */
31029  #define R_GLCDC_GR_CLUTINT_SEL_Pos      (16UL)         /*!< SEL (Bit 16)                                          */
31030  #define R_GLCDC_GR_CLUTINT_SEL_Msk      (0x10000UL)    /*!< SEL (Bitfield-Mask: 0x01)                             */
31031  #define R_GLCDC_GR_CLUTINT_LINE_Pos     (0UL)          /*!< LINE (Bit 0)                                          */
31032  #define R_GLCDC_GR_CLUTINT_LINE_Msk     (0x7ffUL)      /*!< LINE (Bitfield-Mask: 0x7ff)                           */
31033 /* ==========================================================  MON  ========================================================== */
31034  #define R_GLCDC_GR_MON_UNDFLST_Pos      (16UL)         /*!< UNDFLST (Bit 16)                                      */
31035  #define R_GLCDC_GR_MON_UNDFLST_Msk      (0x10000UL)    /*!< UNDFLST (Bitfield-Mask: 0x01)                         */
31036  #define R_GLCDC_GR_MON_ARCST_Pos        (0UL)          /*!< ARCST (Bit 0)                                         */
31037  #define R_GLCDC_GR_MON_ARCST_Msk        (0x1UL)        /*!< ARCST (Bitfield-Mask: 0x01)                           */
31038 
31039 /* =========================================================================================================================== */
31040 /* ================                                            GAM                                            ================ */
31041 /* =========================================================================================================================== */
31042 
31043 /* =========================================================  LATCH  ========================================================= */
31044  #define R_GLCDC_GAM_LATCH_VEN_Pos       (0UL)     /*!< VEN (Bit 0)                                           */
31045  #define R_GLCDC_GAM_LATCH_VEN_Msk       (0x1UL)   /*!< VEN (Bitfield-Mask: 0x01)                             */
31046 /* ========================================================  GAM_SW  ========================================================= */
31047  #define R_GLCDC_GAM_GAM_SW_GAMON_Pos    (0UL)     /*!< GAMON (Bit 0)                                         */
31048  #define R_GLCDC_GAM_GAM_SW_GAMON_Msk    (0x1UL)   /*!< GAMON (Bitfield-Mask: 0x01)                           */
31049 /* ==========================================================  LUT  ========================================================== */
31050  #define R_GLCDC_GAM_LUT___Pos           (0UL)     /*!< _ (Bit 0)                                             */
31051  #define R_GLCDC_GAM_LUT___Msk           (0x7ffUL) /*!< _ (Bitfield-Mask: 0x7ff)                              */
31052 /* =========================================================  AREA  ========================================================== */
31053  #define R_GLCDC_GAM_AREA___Pos          (0UL)     /*!< _ (Bit 0)                                             */
31054  #define R_GLCDC_GAM_AREA___Msk          (0x3ffUL) /*!< _ (Bitfield-Mask: 0x3ff)                              */
31055 
31056 /* =========================================================================================================================== */
31057 /* ================                                            OUT                                            ================ */
31058 /* =========================================================================================================================== */
31059 
31060 /* ========================================================  VLATCH  ========================================================= */
31061  #define R_GLCDC_OUT_VLATCH_VEN_Pos            (0UL)          /*!< VEN (Bit 0)                                           */
31062  #define R_GLCDC_OUT_VLATCH_VEN_Msk            (0x1UL)        /*!< VEN (Bitfield-Mask: 0x01)                             */
31063 /* ==========================================================  SET  ========================================================== */
31064  #define R_GLCDC_OUT_SET_ENDIANON_Pos          (28UL)         /*!< ENDIANON (Bit 28)                                     */
31065  #define R_GLCDC_OUT_SET_ENDIANON_Msk          (0x10000000UL) /*!< ENDIANON (Bitfield-Mask: 0x01)                        */
31066  #define R_GLCDC_OUT_SET_SWAPON_Pos            (24UL)         /*!< SWAPON (Bit 24)                                       */
31067  #define R_GLCDC_OUT_SET_SWAPON_Msk            (0x1000000UL)  /*!< SWAPON (Bitfield-Mask: 0x01)                          */
31068  #define R_GLCDC_OUT_SET_FORMAT_Pos            (12UL)         /*!< FORMAT (Bit 12)                                       */
31069  #define R_GLCDC_OUT_SET_FORMAT_Msk            (0x3000UL)     /*!< FORMAT (Bitfield-Mask: 0x03)                          */
31070  #define R_GLCDC_OUT_SET_FRQSEL_Pos            (8UL)          /*!< FRQSEL (Bit 8)                                        */
31071  #define R_GLCDC_OUT_SET_FRQSEL_Msk            (0x300UL)      /*!< FRQSEL (Bitfield-Mask: 0x03)                          */
31072  #define R_GLCDC_OUT_SET_DIRSEL_Pos            (4UL)          /*!< DIRSEL (Bit 4)                                        */
31073  #define R_GLCDC_OUT_SET_DIRSEL_Msk            (0x10UL)       /*!< DIRSEL (Bitfield-Mask: 0x01)                          */
31074  #define R_GLCDC_OUT_SET_PHASE_Pos             (0UL)          /*!< PHASE (Bit 0)                                         */
31075  #define R_GLCDC_OUT_SET_PHASE_Msk             (0x3UL)        /*!< PHASE (Bitfield-Mask: 0x03)                           */
31076 /* ========================================================  BRIGHT1  ======================================================== */
31077  #define R_GLCDC_OUT_BRIGHT1_BRTG_Pos          (0UL)          /*!< BRTG (Bit 0)                                          */
31078  #define R_GLCDC_OUT_BRIGHT1_BRTG_Msk          (0x3ffUL)      /*!< BRTG (Bitfield-Mask: 0x3ff)                           */
31079 /* ========================================================  BRIGHT2  ======================================================== */
31080  #define R_GLCDC_OUT_BRIGHT2_BRTB_Pos          (16UL)         /*!< BRTB (Bit 16)                                         */
31081  #define R_GLCDC_OUT_BRIGHT2_BRTB_Msk          (0x3ff0000UL)  /*!< BRTB (Bitfield-Mask: 0x3ff)                           */
31082  #define R_GLCDC_OUT_BRIGHT2_BRTR_Pos          (0UL)          /*!< BRTR (Bit 0)                                          */
31083  #define R_GLCDC_OUT_BRIGHT2_BRTR_Msk          (0x3ffUL)      /*!< BRTR (Bitfield-Mask: 0x3ff)                           */
31084 /* =======================================================  CONTRAST  ======================================================== */
31085  #define R_GLCDC_OUT_CONTRAST_CONTG_Pos        (16UL)         /*!< CONTG (Bit 16)                                        */
31086  #define R_GLCDC_OUT_CONTRAST_CONTG_Msk        (0xff0000UL)   /*!< CONTG (Bitfield-Mask: 0xff)                           */
31087  #define R_GLCDC_OUT_CONTRAST_CONTB_Pos        (8UL)          /*!< CONTB (Bit 8)                                         */
31088  #define R_GLCDC_OUT_CONTRAST_CONTB_Msk        (0xff00UL)     /*!< CONTB (Bitfield-Mask: 0xff)                           */
31089  #define R_GLCDC_OUT_CONTRAST_CONTR_Pos        (0UL)          /*!< CONTR (Bit 0)                                         */
31090  #define R_GLCDC_OUT_CONTRAST_CONTR_Msk        (0xffUL)       /*!< CONTR (Bitfield-Mask: 0xff)                           */
31091 /* =========================================================  PDTHA  ========================================================= */
31092  #define R_GLCDC_OUT_PDTHA_SEL_Pos             (20UL)         /*!< SEL (Bit 20)                                          */
31093  #define R_GLCDC_OUT_PDTHA_SEL_Msk             (0x300000UL)   /*!< SEL (Bitfield-Mask: 0x03)                             */
31094  #define R_GLCDC_OUT_PDTHA_FORM_Pos            (16UL)         /*!< FORM (Bit 16)                                         */
31095  #define R_GLCDC_OUT_PDTHA_FORM_Msk            (0x30000UL)    /*!< FORM (Bitfield-Mask: 0x03)                            */
31096  #define R_GLCDC_OUT_PDTHA_PA_Pos              (12UL)         /*!< PA (Bit 12)                                           */
31097  #define R_GLCDC_OUT_PDTHA_PA_Msk              (0x3000UL)     /*!< PA (Bitfield-Mask: 0x03)                              */
31098  #define R_GLCDC_OUT_PDTHA_PB_Pos              (8UL)          /*!< PB (Bit 8)                                            */
31099  #define R_GLCDC_OUT_PDTHA_PB_Msk              (0x300UL)      /*!< PB (Bitfield-Mask: 0x03)                              */
31100  #define R_GLCDC_OUT_PDTHA_PC_Pos              (4UL)          /*!< PC (Bit 4)                                            */
31101  #define R_GLCDC_OUT_PDTHA_PC_Msk              (0x30UL)       /*!< PC (Bitfield-Mask: 0x03)                              */
31102  #define R_GLCDC_OUT_PDTHA_PD_Pos              (0UL)          /*!< PD (Bit 0)                                            */
31103  #define R_GLCDC_OUT_PDTHA_PD_Msk              (0x3UL)        /*!< PD (Bitfield-Mask: 0x03)                              */
31104 /* =======================================================  CLKPHASE  ======================================================== */
31105  #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Pos     (12UL)         /*!< FRONTGAM (Bit 12)                                     */
31106  #define R_GLCDC_OUT_CLKPHASE_FRONTGAM_Msk     (0x1000UL)     /*!< FRONTGAM (Bitfield-Mask: 0x01)                        */
31107  #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Pos      (8UL)          /*!< LCDEDGE (Bit 8)                                       */
31108  #define R_GLCDC_OUT_CLKPHASE_LCDEDGE_Msk      (0x100UL)      /*!< LCDEDGE (Bitfield-Mask: 0x01)                         */
31109  #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Pos    (6UL)          /*!< TCON0EDGE (Bit 6)                                     */
31110  #define R_GLCDC_OUT_CLKPHASE_TCON0EDGE_Msk    (0x40UL)       /*!< TCON0EDGE (Bitfield-Mask: 0x01)                       */
31111  #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Pos    (5UL)          /*!< TCON1EDGE (Bit 5)                                     */
31112  #define R_GLCDC_OUT_CLKPHASE_TCON1EDGE_Msk    (0x20UL)       /*!< TCON1EDGE (Bitfield-Mask: 0x01)                       */
31113  #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Pos    (4UL)          /*!< TCON2EDGE (Bit 4)                                     */
31114  #define R_GLCDC_OUT_CLKPHASE_TCON2EDGE_Msk    (0x10UL)       /*!< TCON2EDGE (Bitfield-Mask: 0x01)                       */
31115  #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Pos    (3UL)          /*!< TCON3EDGE (Bit 3)                                     */
31116  #define R_GLCDC_OUT_CLKPHASE_TCON3EDGE_Msk    (0x8UL)        /*!< TCON3EDGE (Bitfield-Mask: 0x01)                       */
31117 
31118 /* =========================================================================================================================== */
31119 /* ================                                           TCON                                            ================ */
31120 /* =========================================================================================================================== */
31121 
31122 /* ==========================================================  TIM  ========================================================== */
31123  #define R_GLCDC_TCON_TIM_HALF_Pos       (16UL)        /*!< HALF (Bit 16)                                         */
31124  #define R_GLCDC_TCON_TIM_HALF_Msk       (0x7ff0000UL) /*!< HALF (Bitfield-Mask: 0x7ff)                           */
31125  #define R_GLCDC_TCON_TIM_OFFSET_Pos     (0UL)         /*!< OFFSET (Bit 0)                                        */
31126  #define R_GLCDC_TCON_TIM_OFFSET_Msk     (0x7ffUL)     /*!< OFFSET (Bitfield-Mask: 0x7ff)                         */
31127 /* =========================================================  STVA1  ========================================================= */
31128  #define R_GLCDC_TCON_STVA1_VS_Pos       (16UL)        /*!< VS (Bit 16)                                           */
31129  #define R_GLCDC_TCON_STVA1_VS_Msk       (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff)                             */
31130  #define R_GLCDC_TCON_STVA1_VW_Pos       (0UL)         /*!< VW (Bit 0)                                            */
31131  #define R_GLCDC_TCON_STVA1_VW_Msk       (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
31132 /* =========================================================  STVB1  ========================================================= */
31133  #define R_GLCDC_TCON_STVB1_VS_Pos       (16UL)        /*!< VS (Bit 16)                                           */
31134  #define R_GLCDC_TCON_STVB1_VS_Msk       (0x7ff0000UL) /*!< VS (Bitfield-Mask: 0x7ff)                             */
31135  #define R_GLCDC_TCON_STVB1_VW_Pos       (0UL)         /*!< VW (Bit 0)                                            */
31136  #define R_GLCDC_TCON_STVB1_VW_Msk       (0x7ffUL)     /*!< VW (Bitfield-Mask: 0x7ff)                             */
31137 /* =========================================================  STVA2  ========================================================= */
31138  #define R_GLCDC_TCON_STVA2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
31139  #define R_GLCDC_TCON_STVA2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
31140  #define R_GLCDC_TCON_STVA2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
31141  #define R_GLCDC_TCON_STVA2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
31142 /* =========================================================  STVB2  ========================================================= */
31143  #define R_GLCDC_TCON_STVB2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
31144  #define R_GLCDC_TCON_STVB2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
31145  #define R_GLCDC_TCON_STVB2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
31146  #define R_GLCDC_TCON_STVB2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
31147 /* =========================================================  STHA1  ========================================================= */
31148  #define R_GLCDC_TCON_STHA1_HS_Pos       (16UL)        /*!< HS (Bit 16)                                           */
31149  #define R_GLCDC_TCON_STHA1_HS_Msk       (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff)                             */
31150  #define R_GLCDC_TCON_STHA1_HW_Pos       (0UL)         /*!< HW (Bit 0)                                            */
31151  #define R_GLCDC_TCON_STHA1_HW_Msk       (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
31152 /* =========================================================  STHB1  ========================================================= */
31153  #define R_GLCDC_TCON_STHB1_HS_Pos       (16UL)        /*!< HS (Bit 16)                                           */
31154  #define R_GLCDC_TCON_STHB1_HS_Msk       (0x7ff0000UL) /*!< HS (Bitfield-Mask: 0x7ff)                             */
31155  #define R_GLCDC_TCON_STHB1_HW_Pos       (0UL)         /*!< HW (Bit 0)                                            */
31156  #define R_GLCDC_TCON_STHB1_HW_Msk       (0x7ffUL)     /*!< HW (Bitfield-Mask: 0x7ff)                             */
31157 /* =========================================================  STHA2  ========================================================= */
31158  #define R_GLCDC_TCON_STHA2_HSSEL_Pos    (8UL)         /*!< HSSEL (Bit 8)                                         */
31159  #define R_GLCDC_TCON_STHA2_HSSEL_Msk    (0x100UL)     /*!< HSSEL (Bitfield-Mask: 0x01)                           */
31160  #define R_GLCDC_TCON_STHA2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
31161  #define R_GLCDC_TCON_STHA2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
31162  #define R_GLCDC_TCON_STHA2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
31163  #define R_GLCDC_TCON_STHA2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
31164 /* =========================================================  STHB2  ========================================================= */
31165  #define R_GLCDC_TCON_STHB2_HSSEL_Pos    (8UL)         /*!< HSSEL (Bit 8)                                         */
31166  #define R_GLCDC_TCON_STHB2_HSSEL_Msk    (0x100UL)     /*!< HSSEL (Bitfield-Mask: 0x01)                           */
31167  #define R_GLCDC_TCON_STHB2_INV_Pos      (4UL)         /*!< INV (Bit 4)                                           */
31168  #define R_GLCDC_TCON_STHB2_INV_Msk      (0x10UL)      /*!< INV (Bitfield-Mask: 0x01)                             */
31169  #define R_GLCDC_TCON_STHB2_SEL_Pos      (0UL)         /*!< SEL (Bit 0)                                           */
31170  #define R_GLCDC_TCON_STHB2_SEL_Msk      (0x7UL)       /*!< SEL (Bitfield-Mask: 0x07)                             */
31171 /* ==========================================================  DE  =========================================================== */
31172  #define R_GLCDC_TCON_DE_INV_Pos         (0UL)         /*!< INV (Bit 0)                                           */
31173  #define R_GLCDC_TCON_DE_INV_Msk         (0x1UL)       /*!< INV (Bitfield-Mask: 0x01)                             */
31174 
31175 /* =========================================================================================================================== */
31176 /* ================                                          SYSCNT                                           ================ */
31177 /* =========================================================================================================================== */
31178 
31179 /* ========================================================  DTCTEN  ========================================================= */
31180  #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Pos     (2UL)          /*!< L2UNDFDTC (Bit 2)                                     */
31181  #define R_GLCDC_SYSCNT_DTCTEN_L2UNDFDTC_Msk     (0x4UL)        /*!< L2UNDFDTC (Bitfield-Mask: 0x01)                       */
31182  #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Pos     (1UL)          /*!< L1UNDFDTC (Bit 1)                                     */
31183  #define R_GLCDC_SYSCNT_DTCTEN_L1UNDFDTC_Msk     (0x2UL)        /*!< L1UNDFDTC (Bitfield-Mask: 0x01)                       */
31184  #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Pos       (0UL)          /*!< VPOSDTC (Bit 0)                                       */
31185  #define R_GLCDC_SYSCNT_DTCTEN_VPOSDTC_Msk       (0x1UL)        /*!< VPOSDTC (Bitfield-Mask: 0x01)                         */
31186 /* =========================================================  INTEN  ========================================================= */
31187  #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Pos    (2UL)          /*!< L2UNDFINTEN (Bit 2)                                   */
31188  #define R_GLCDC_SYSCNT_INTEN_L2UNDFINTEN_Msk    (0x4UL)        /*!< L2UNDFINTEN (Bitfield-Mask: 0x01)                     */
31189  #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Pos    (1UL)          /*!< L1UNDFINTEN (Bit 1)                                   */
31190  #define R_GLCDC_SYSCNT_INTEN_L1UNDFINTEN_Msk    (0x2UL)        /*!< L1UNDFINTEN (Bitfield-Mask: 0x01)                     */
31191  #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Pos      (0UL)          /*!< VPOSINTEN (Bit 0)                                     */
31192  #define R_GLCDC_SYSCNT_INTEN_VPOSINTEN_Msk      (0x1UL)        /*!< VPOSINTEN (Bitfield-Mask: 0x01)                       */
31193 /* =========================================================  STCLR  ========================================================= */
31194  #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Pos      (2UL)          /*!< L2UNDFCLR (Bit 2)                                     */
31195  #define R_GLCDC_SYSCNT_STCLR_L2UNDFCLR_Msk      (0x4UL)        /*!< L2UNDFCLR (Bitfield-Mask: 0x01)                       */
31196  #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Pos      (1UL)          /*!< L1UNDFCLR (Bit 1)                                     */
31197  #define R_GLCDC_SYSCNT_STCLR_L1UNDFCLR_Msk      (0x2UL)        /*!< L1UNDFCLR (Bitfield-Mask: 0x01)                       */
31198  #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Pos        (0UL)          /*!< VPOSCLR (Bit 0)                                       */
31199  #define R_GLCDC_SYSCNT_STCLR_VPOSCLR_Msk        (0x1UL)        /*!< VPOSCLR (Bitfield-Mask: 0x01)                         */
31200 /* =========================================================  STMON  ========================================================= */
31201  #define R_GLCDC_SYSCNT_STMON_L2UNDF_Pos         (2UL)          /*!< L2UNDF (Bit 2)                                        */
31202  #define R_GLCDC_SYSCNT_STMON_L2UNDF_Msk         (0x4UL)        /*!< L2UNDF (Bitfield-Mask: 0x01)                          */
31203  #define R_GLCDC_SYSCNT_STMON_L1UNDF_Pos         (1UL)          /*!< L1UNDF (Bit 1)                                        */
31204  #define R_GLCDC_SYSCNT_STMON_L1UNDF_Msk         (0x2UL)        /*!< L1UNDF (Bitfield-Mask: 0x01)                          */
31205  #define R_GLCDC_SYSCNT_STMON_VPOS_Pos           (0UL)          /*!< VPOS (Bit 0)                                          */
31206  #define R_GLCDC_SYSCNT_STMON_VPOS_Msk           (0x1UL)        /*!< VPOS (Bitfield-Mask: 0x01)                            */
31207 /* =======================================================  PANEL_CLK  ======================================================= */
31208  #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Pos        (16UL)         /*!< VER (Bit 16)                                          */
31209  #define R_GLCDC_SYSCNT_PANEL_CLK_VER_Msk        (0xffff0000UL) /*!< VER (Bitfield-Mask: 0xffff)                           */
31210  #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Pos     (12UL)         /*!< PIXSEL (Bit 12)                                       */
31211  #define R_GLCDC_SYSCNT_PANEL_CLK_PIXSEL_Msk     (0x1000UL)     /*!< PIXSEL (Bitfield-Mask: 0x01)                          */
31212  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Pos     (8UL)          /*!< CLKSEL (Bit 8)                                        */
31213  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKSEL_Msk     (0x100UL)      /*!< CLKSEL (Bitfield-Mask: 0x01)                          */
31214  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Pos      (6UL)          /*!< CLKEN (Bit 6)                                         */
31215  #define R_GLCDC_SYSCNT_PANEL_CLK_CLKEN_Msk      (0x40UL)       /*!< CLKEN (Bitfield-Mask: 0x01)                           */
31216  #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Pos       (0UL)          /*!< DCDR (Bit 0)                                          */
31217  #define R_GLCDC_SYSCNT_PANEL_CLK_DCDR_Msk       (0x3fUL)       /*!< DCDR (Bitfield-Mask: 0x3f)                            */
31218 
31219 /* =========================================================================================================================== */
31220 /* ================                                            SAR                                            ================ */
31221 /* =========================================================================================================================== */
31222 
31223 /* ===========================================================  L  =========================================================== */
31224  #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
31225  #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
31226 /* ===========================================================  U  =========================================================== */
31227  #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
31228  #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
31229  #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
31230  #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
31231  #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
31232  #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
31233 
31234 /* =========================================================================================================================== */
31235 /* ================                                          REGION                                           ================ */
31236 /* =========================================================================================================================== */
31237 
31238 /* ==========================================================  AC  =========================================================== */
31239  #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos        (3UL)          /*!< PP (Bit 3)                                            */
31240  #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk        (0x8UL)        /*!< PP (Bitfield-Mask: 0x01)                              */
31241  #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos        (2UL)          /*!< WP (Bit 2)                                            */
31242  #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk        (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
31243  #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos        (1UL)          /*!< RP (Bit 1)                                            */
31244  #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk        (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
31245  #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos    (0UL)          /*!< ENABLE (Bit 0)                                        */
31246  #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk    (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
31247 /* ===========================================================  S  =========================================================== */
31248  #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos      (0UL)          /*!< MMPUS (Bit 0)                                         */
31249  #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk      (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff)                     */
31250 /* ===========================================================  E  =========================================================== */
31251  #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos      (0UL)          /*!< MMPUE (Bit 0)                                         */
31252  #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk      (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff)                     */
31253 
31254 /* =========================================================================================================================== */
31255 /* ================                                           GROUP                                           ================ */
31256 /* =========================================================================================================================== */
31257 
31258 /* ==========================================================  EN  =========================================================== */
31259  #define R_MPU_MMPU_GROUP_EN_KEY_Pos             (8UL)      /*!< KEY (Bit 8)                                           */
31260  #define R_MPU_MMPU_GROUP_EN_KEY_Msk             (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
31261  #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos          (0UL)      /*!< ENABLE (Bit 0)                                        */
31262  #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk          (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
31263 /* =========================================================  ENPT  ========================================================== */
31264  #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
31265  #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
31266  #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
31267  #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
31268 /* ==========================================================  RPT  ========================================================== */
31269  #define R_MPU_MMPU_GROUP_RPT_KEY_Pos            (8UL)      /*!< KEY (Bit 8)                                           */
31270  #define R_MPU_MMPU_GROUP_RPT_KEY_Msk            (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
31271  #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos        (0UL)      /*!< PROTECT (Bit 0)                                       */
31272  #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk        (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
31273 /* ========================================================  RPT_SEC  ======================================================== */
31274  #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
31275  #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
31276  #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
31277  #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
31278 
31279 /* =========================================================================================================================== */
31280 /* ================                                            SP                                             ================ */
31281 /* =========================================================================================================================== */
31282 
31283 /* ==========================================================  OAD  ========================================================== */
31284  #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
31285  #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
31286  #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
31287  #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
31288 /* ==========================================================  CTL  ========================================================== */
31289  #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
31290  #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
31291  #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
31292  #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
31293 /* ==========================================================  PT  =========================================================== */
31294  #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
31295  #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
31296  #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
31297  #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
31298 /* ==========================================================  SA  =========================================================== */
31299  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
31300  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
31301 /* ==========================================================  EA  =========================================================== */
31302  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
31303  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
31304 
31305 /* =========================================================================================================================== */
31306 /* ================                                            PIN                                            ================ */
31307 /* =========================================================================================================================== */
31308 
31309 /* =======================================================  PmnPFS_BY  ======================================================= */
31310  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
31311  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
31312  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
31313  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
31314  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
31315  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
31316  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
31317  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
31318  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
31319  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
31320 /* =======================================================  PmnPFS_HA  ======================================================= */
31321  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
31322  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
31323  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
31324  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
31325  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
31326  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
31327  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
31328  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
31329  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
31330  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
31331  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
31332  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
31333  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
31334  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
31335  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
31336  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
31337  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
31338  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
31339 /* ========================================================  PmnPFS  ========================================================= */
31340  #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
31341  #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
31342  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
31343  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
31344  #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
31345  #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
31346  #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
31347  #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
31348  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
31349  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
31350  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
31351  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
31352  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
31353  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
31354  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
31355  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
31356  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
31357  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
31358  #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
31359  #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
31360  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
31361  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
31362 
31363 /* =========================================================================================================================== */
31364 /* ================                                           PORT                                            ================ */
31365 /* =========================================================================================================================== */
31366 
31367 /* =========================================================================================================================== */
31368 /* ================                                           PMSAR                                           ================ */
31369 /* =========================================================================================================================== */
31370 
31371 /* =========================================================  PMSAR  ========================================================= */
31372 
31373 /* =========================================================================================================================== */
31374 /* ================                                           RTCCR                                           ================ */
31375 /* =========================================================================================================================== */
31376 
31377 /* =========================================================  RTCCR  ========================================================= */
31378  #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
31379  #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
31380  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
31381  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
31382  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
31383  #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
31384  #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
31385  #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
31386 
31387 /* =========================================================================================================================== */
31388 /* ================                                            CP                                             ================ */
31389 /* =========================================================================================================================== */
31390 
31391 /* =========================================================  RSEC  ========================================================== */
31392  #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
31393  #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
31394  #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
31395  #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
31396 /* =========================================================  BCNT0  ========================================================= */
31397  #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
31398  #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
31399 /* =========================================================  RMIN  ========================================================== */
31400  #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
31401  #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
31402  #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
31403  #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
31404 /* =========================================================  BCNT1  ========================================================= */
31405  #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
31406  #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
31407 /* ==========================================================  RHR  ========================================================== */
31408  #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
31409  #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
31410  #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
31411  #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
31412  #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
31413  #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
31414 /* =========================================================  BCNT2  ========================================================= */
31415  #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
31416  #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
31417 /* =========================================================  RDAY  ========================================================== */
31418  #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
31419  #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
31420  #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
31421  #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
31422 /* =========================================================  BCNT3  ========================================================= */
31423  #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
31424  #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
31425 /* =========================================================  RMON  ========================================================== */
31426  #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
31427  #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
31428  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
31429  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
31430 
31431 /* =========================================================================================================================== */
31432 /* ================                                          PIPE_TR                                          ================ */
31433 /* =========================================================================================================================== */
31434 
31435 /* ===========================================================  E  =========================================================== */
31436  #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
31437  #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
31438  #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
31439  #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
31440 /* ===========================================================  N  =========================================================== */
31441  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
31442  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
31443 
31444 /* =========================================================================================================================== */
31445 /* ================                                          PIPE_TR                                          ================ */
31446 /* =========================================================================================================================== */
31447 
31448 /* ===========================================================  E  =========================================================== */
31449  #define R_USB_HS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
31450  #define R_USB_HS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
31451  #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
31452  #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
31453 /* ===========================================================  N  =========================================================== */
31454  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
31455  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
31456 
31457 /* =========================================================================================================================== */
31458 /* ================                                          CMCFGCS                                          ================ */
31459 /* =========================================================================================================================== */
31460 
31461 /* ========================================================  CMCFG0  ========================================================= */
31462  #define R_XSPI_CMCFGCS_CMCFG0_FFMT_Pos       (0UL)          /*!< FFMT (Bit 0)                                          */
31463  #define R_XSPI_CMCFGCS_CMCFG0_FFMT_Msk       (0x3UL)        /*!< FFMT (Bitfield-Mask: 0x03)                            */
31464  #define R_XSPI_CMCFGCS_CMCFG0_ADDSIZE_Pos    (2UL)          /*!< ADDSIZE (Bit 2)                                       */
31465  #define R_XSPI_CMCFGCS_CMCFG0_ADDSIZE_Msk    (0xcUL)        /*!< ADDSIZE (Bitfield-Mask: 0x03)                         */
31466  #define R_XSPI_CMCFGCS_CMCFG0_WPBSTMD_Pos    (4UL)          /*!< WPBSTMD (Bit 4)                                       */
31467  #define R_XSPI_CMCFGCS_CMCFG0_WPBSTMD_Msk    (0x10UL)       /*!< WPBSTMD (Bitfield-Mask: 0x01)                         */
31468  #define R_XSPI_CMCFGCS_CMCFG0_ARYAMD_Pos     (5UL)          /*!< ARYAMD (Bit 5)                                        */
31469  #define R_XSPI_CMCFGCS_CMCFG0_ARYAMD_Msk     (0x20UL)       /*!< ARYAMD (Bitfield-Mask: 0x01)                          */
31470  #define R_XSPI_CMCFGCS_CMCFG0_ADDRPEN_Pos    (16UL)         /*!< ADDRPEN (Bit 16)                                      */
31471  #define R_XSPI_CMCFGCS_CMCFG0_ADDRPEN_Msk    (0xff0000UL)   /*!< ADDRPEN (Bitfield-Mask: 0xff)                         */
31472  #define R_XSPI_CMCFGCS_CMCFG0_ADDRPCD_Pos    (24UL)         /*!< ADDRPCD (Bit 24)                                      */
31473  #define R_XSPI_CMCFGCS_CMCFG0_ADDRPCD_Msk    (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff)                         */
31474 /* ========================================================  CMCFG1  ========================================================= */
31475  #define R_XSPI_CMCFGCS_CMCFG1_RDCMD_Pos      (0UL)          /*!< RDCMD (Bit 0)                                         */
31476  #define R_XSPI_CMCFGCS_CMCFG1_RDCMD_Msk      (0xffffUL)     /*!< RDCMD (Bitfield-Mask: 0xffff)                         */
31477  #define R_XSPI_CMCFGCS_CMCFG1_RDLATE_Pos     (16UL)         /*!< RDLATE (Bit 16)                                       */
31478  #define R_XSPI_CMCFGCS_CMCFG1_RDLATE_Msk     (0x1f0000UL)   /*!< RDLATE (Bitfield-Mask: 0x1f)                          */
31479 /* ========================================================  CMCFG2  ========================================================= */
31480  #define R_XSPI_CMCFGCS_CMCFG2_WRCMD_Pos      (0UL)          /*!< WRCMD (Bit 0)                                         */
31481  #define R_XSPI_CMCFGCS_CMCFG2_WRCMD_Msk      (0xffffUL)     /*!< WRCMD (Bitfield-Mask: 0xffff)                         */
31482  #define R_XSPI_CMCFGCS_CMCFG2_WRLATE_Pos     (16UL)         /*!< WRLATE (Bit 16)                                       */
31483  #define R_XSPI_CMCFGCS_CMCFG2_WRLATE_Msk     (0x1f0000UL)   /*!< WRLATE (Bitfield-Mask: 0x1f)                          */
31484 
31485 /* =========================================================================================================================== */
31486 /* ================                                           CDBUF                                           ================ */
31487 /* =========================================================================================================================== */
31488 
31489 /* ==========================================================  CDT  ========================================================== */
31490  #define R_XSPI_CDBUF_CDT_CMDSIZE_Pos     (0UL)          /*!< CMDSIZE (Bit 0)                                       */
31491  #define R_XSPI_CDBUF_CDT_CMDSIZE_Msk     (0x3UL)        /*!< CMDSIZE (Bitfield-Mask: 0x03)                         */
31492  #define R_XSPI_CDBUF_CDT_ADDSIZE_Pos     (2UL)          /*!< ADDSIZE (Bit 2)                                       */
31493  #define R_XSPI_CDBUF_CDT_ADDSIZE_Msk     (0x1cUL)       /*!< ADDSIZE (Bitfield-Mask: 0x07)                         */
31494  #define R_XSPI_CDBUF_CDT_DATASIZE_Pos    (5UL)          /*!< DATASIZE (Bit 5)                                      */
31495  #define R_XSPI_CDBUF_CDT_DATASIZE_Msk    (0x1e0UL)      /*!< DATASIZE (Bitfield-Mask: 0x0f)                        */
31496  #define R_XSPI_CDBUF_CDT_LATE_Pos        (9UL)          /*!< LATE (Bit 9)                                          */
31497  #define R_XSPI_CDBUF_CDT_LATE_Msk        (0x3e00UL)     /*!< LATE (Bitfield-Mask: 0x1f)                            */
31498  #define R_XSPI_CDBUF_CDT_TRTYPE_Pos      (15UL)         /*!< TRTYPE (Bit 15)                                       */
31499  #define R_XSPI_CDBUF_CDT_TRTYPE_Msk      (0x8000UL)     /*!< TRTYPE (Bitfield-Mask: 0x01)                          */
31500  #define R_XSPI_CDBUF_CDT_CMD_Pos         (16UL)         /*!< CMD (Bit 16)                                          */
31501  #define R_XSPI_CDBUF_CDT_CMD_Msk         (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff)                           */
31502 /* ==========================================================  CDA  ========================================================== */
31503  #define R_XSPI_CDBUF_CDA_ADD_Pos         (0UL)          /*!< ADD (Bit 0)                                           */
31504  #define R_XSPI_CDBUF_CDA_ADD_Msk         (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff)                       */
31505 /* =========================================================  CDD0  ========================================================== */
31506  #define R_XSPI_CDBUF_CDD0_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
31507  #define R_XSPI_CDBUF_CDD0_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
31508 /* =========================================================  CDD1  ========================================================== */
31509  #define R_XSPI_CDBUF_CDD1_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
31510  #define R_XSPI_CDBUF_CDD1_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
31511 
31512 /* =========================================================================================================================== */
31513 /* ================                                          CCCTLCS                                          ================ */
31514 /* =========================================================================================================================== */
31515 
31516 /* ========================================================  CCCTL0  ========================================================= */
31517  #define R_XSPI_CCCTLCS_CCCTL0_CAEN_Pos          (0UL)          /*!< CAEN (Bit 0)                                          */
31518  #define R_XSPI_CCCTLCS_CCCTL0_CAEN_Msk          (0x1UL)        /*!< CAEN (Bitfield-Mask: 0x01)                            */
31519  #define R_XSPI_CCCTLCS_CCCTL0_CANOWR_Pos        (1UL)          /*!< CANOWR (Bit 1)                                        */
31520  #define R_XSPI_CCCTLCS_CCCTL0_CANOWR_Msk        (0x2UL)        /*!< CANOWR (Bitfield-Mask: 0x01)                          */
31521  #define R_XSPI_CCCTLCS_CCCTL0_CAITV_Pos         (8UL)          /*!< CAITV (Bit 8)                                         */
31522  #define R_XSPI_CCCTLCS_CCCTL0_CAITV_Msk         (0x1f00UL)     /*!< CAITV (Bitfield-Mask: 0x1f)                           */
31523  #define R_XSPI_CCCTLCS_CCCTL0_CASFTSTA_Pos      (16UL)         /*!< CASFTSTA (Bit 16)                                     */
31524  #define R_XSPI_CCCTLCS_CCCTL0_CASFTSTA_Msk      (0x1f0000UL)   /*!< CASFTSTA (Bitfield-Mask: 0x1f)                        */
31525  #define R_XSPI_CCCTLCS_CCCTL0_CASFTEND_Pos      (24UL)         /*!< CASFTEND (Bit 24)                                     */
31526  #define R_XSPI_CCCTLCS_CCCTL0_CASFTEND_Msk      (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f)                        */
31527 /* ========================================================  CCCTL1  ========================================================= */
31528  #define R_XSPI_CCCTLCS_CCCTL1_CACMDSIZE_Pos     (0UL)          /*!< CACMDSIZE (Bit 0)                                     */
31529  #define R_XSPI_CCCTLCS_CCCTL1_CACMDSIZE_Msk     (0x3UL)        /*!< CACMDSIZE (Bitfield-Mask: 0x03)                       */
31530  #define R_XSPI_CCCTLCS_CCCTL1_CAADDSIZE_Pos     (2UL)          /*!< CAADDSIZE (Bit 2)                                     */
31531  #define R_XSPI_CCCTLCS_CCCTL1_CAADDSIZE_Msk     (0x1cUL)       /*!< CAADDSIZE (Bitfield-Mask: 0x07)                       */
31532  #define R_XSPI_CCCTLCS_CCCTL1_CADATASIZE_Pos    (5UL)          /*!< CADATASIZE (Bit 5)                                    */
31533  #define R_XSPI_CCCTLCS_CCCTL1_CADATASIZE_Msk    (0x1e0UL)      /*!< CADATASIZE (Bitfield-Mask: 0x0f)                      */
31534  #define R_XSPI_CCCTLCS_CCCTL1_CAWRLATE_Pos      (16UL)         /*!< CAWRLATE (Bit 16)                                     */
31535  #define R_XSPI_CCCTLCS_CCCTL1_CAWRLATE_Msk      (0x1f0000UL)   /*!< CAWRLATE (Bitfield-Mask: 0x1f)                        */
31536  #define R_XSPI_CCCTLCS_CCCTL1_CARDLATE_Pos      (24UL)         /*!< CARDLATE (Bit 24)                                     */
31537  #define R_XSPI_CCCTLCS_CCCTL1_CARDLATE_Msk      (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f)                        */
31538 /* ========================================================  CCCTL2  ========================================================= */
31539  #define R_XSPI_CCCTLCS_CCCTL2_CAWRCMD_Pos       (0UL)          /*!< CAWRCMD (Bit 0)                                       */
31540  #define R_XSPI_CCCTLCS_CCCTL2_CAWRCMD_Msk       (0xffffUL)     /*!< CAWRCMD (Bitfield-Mask: 0xffff)                       */
31541  #define R_XSPI_CCCTLCS_CCCTL2_CARDCMD_Pos       (16UL)         /*!< CARDCMD (Bit 16)                                      */
31542  #define R_XSPI_CCCTLCS_CCCTL2_CARDCMD_Msk       (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff)                       */
31543 /* ========================================================  CCCTL3  ========================================================= */
31544  #define R_XSPI_CCCTLCS_CCCTL3_CAADD_Pos         (0UL)          /*!< CAADD (Bit 0)                                         */
31545  #define R_XSPI_CCCTLCS_CCCTL3_CAADD_Msk         (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff)                     */
31546 /* ========================================================  CCCTL4  ========================================================= */
31547  #define R_XSPI_CCCTLCS_CCCTL4_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
31548  #define R_XSPI_CCCTLCS_CCCTL4_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
31549 /* ========================================================  CCCTL5  ========================================================= */
31550  #define R_XSPI_CCCTLCS_CCCTL5_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
31551  #define R_XSPI_CCCTLCS_CCCTL5_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
31552 /* ========================================================  CCCTL6  ========================================================= */
31553  #define R_XSPI_CCCTLCS_CCCTL6_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
31554  #define R_XSPI_CCCTLCS_CCCTL6_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
31555 /* ========================================================  CCCTL7  ========================================================= */
31556  #define R_XSPI_CCCTLCS_CCCTL7_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
31557  #define R_XSPI_CCCTLCS_CCCTL7_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
31558 
31559 /* =========================================================================================================================== */
31560 /* ================                                           CTRL                                            ================ */
31561 /* =========================================================================================================================== */
31562 
31563 /* =========================================================  AGTCR  ========================================================= */
31564  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
31565  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
31566  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
31567  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
31568  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
31569  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
31570  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
31571  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
31572  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
31573  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
31574  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
31575  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
31576  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
31577  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
31578 /* ========================================================  AGTMR1  ========================================================= */
31579  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
31580  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
31581  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
31582  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
31583  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
31584  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
31585 /* ========================================================  AGTMR2  ========================================================= */
31586  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
31587  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
31588  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
31589  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
31590 /* =====================================================  AGTIOSEL_ALT  ====================================================== */
31591  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
31592  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
31593  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
31594  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
31595 /* ========================================================  AGTIOC  ========================================================= */
31596  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
31597  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
31598  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
31599  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
31600  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
31601  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
31602  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
31603  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
31604 /* ========================================================  AGTISR  ========================================================= */
31605  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
31606  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
31607 /* ========================================================  AGTCMSR  ======================================================== */
31608  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
31609  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
31610  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
31611  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
31612  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
31613  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
31614  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
31615  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
31616  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
31617  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
31618  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
31619  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
31620 /* =======================================================  AGTIOSEL  ======================================================== */
31621  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
31622  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
31623  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
31624  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
31625 
31626 /* =========================================================================================================================== */
31627 /* ================                                           AGT16                                           ================ */
31628 /* =========================================================================================================================== */
31629 
31630 /* ==========================================================  AGT  ========================================================== */
31631  #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
31632  #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
31633 /* ========================================================  AGTCMA  ========================================================= */
31634  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
31635  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
31636 /* ========================================================  AGTCMB  ========================================================= */
31637  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
31638  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
31639 
31640 /* =========================================================================================================================== */
31641 /* ================                                           AGT32                                           ================ */
31642 /* =========================================================================================================================== */
31643 
31644 /* ==========================================================  AGT  ========================================================== */
31645  #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
31646  #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
31647 /* ========================================================  AGTCMA  ========================================================= */
31648  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
31649  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
31650 /* ========================================================  AGTCMB  ========================================================= */
31651  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
31652  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
31653 
31654 /* =========================================================================================================================== */
31655 /* ================                                           CFGD                                            ================ */
31656 /* =========================================================================================================================== */
31657 
31658 /* ========================================================  CFGD_L  ========================================================= */
31659  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Pos    (0UL)   /*!< CDLK (Bit 0)                                          */
31660  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_L_CDLK_Msk    (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01)                            */
31661 /* ========================================================  CFGD_H  ========================================================= */
31662  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Pos    (0UL)   /*!< CDLK (Bit 0)                                          */
31663  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD_CFGD_H_CDLK_Msk    (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01)                            */
31664 
31665 /* =========================================================================================================================== */
31666 /* ================                                         CFGDLOCK                                          ================ */
31667 /* =========================================================================================================================== */
31668 
31669 /* =========================================================  CFGD2  ========================================================= */
31670  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Pos    (0UL)   /*!< CDLK (Bit 0)                                          */
31671  #define R_OFS_DATAFLASH_CFGDLOCK_CFGD2_CDLK_Msk    (0x1UL) /*!< CDLK (Bitfield-Mask: 0x01)                            */
31672 
31673 /** @} */ /* End of group PosMask_clusters */
31674 
31675 /* =========================================================================================================================== */
31676 /* ================                                Pos/Mask Peripheral Section                                ================ */
31677 /* =========================================================================================================================== */
31678 
31679 /** @addtogroup PosMask_peripherals
31680  * @{
31681  */
31682 
31683 /* =========================================================================================================================== */
31684 /* ================                                         R_ACMPHS0                                         ================ */
31685 /* =========================================================================================================================== */
31686 
31687 /* ========================================================  CMPCTL  ========================================================= */
31688  #define R_ACMPHS0_CMPCTL_HCMPON_Pos     (7UL)    /*!< HCMPON (Bit 7)                                        */
31689  #define R_ACMPHS0_CMPCTL_HCMPON_Msk     (0x80UL) /*!< HCMPON (Bitfield-Mask: 0x01)                          */
31690  #define R_ACMPHS0_CMPCTL_CDFS_Pos       (5UL)    /*!< CDFS (Bit 5)                                          */
31691  #define R_ACMPHS0_CMPCTL_CDFS_Msk       (0x60UL) /*!< CDFS (Bitfield-Mask: 0x03)                            */
31692  #define R_ACMPHS0_CMPCTL_CEG_Pos        (3UL)    /*!< CEG (Bit 3)                                           */
31693  #define R_ACMPHS0_CMPCTL_CEG_Msk        (0x18UL) /*!< CEG (Bitfield-Mask: 0x03)                             */
31694  #define R_ACMPHS0_CMPCTL_CSTEN_Pos      (2UL)    /*!< CSTEN (Bit 2)                                         */
31695  #define R_ACMPHS0_CMPCTL_CSTEN_Msk      (0x4UL)  /*!< CSTEN (Bitfield-Mask: 0x01)                           */
31696  #define R_ACMPHS0_CMPCTL_COE_Pos        (1UL)    /*!< COE (Bit 1)                                           */
31697  #define R_ACMPHS0_CMPCTL_COE_Msk        (0x2UL)  /*!< COE (Bitfield-Mask: 0x01)                             */
31698  #define R_ACMPHS0_CMPCTL_CINV_Pos       (0UL)    /*!< CINV (Bit 0)                                          */
31699  #define R_ACMPHS0_CMPCTL_CINV_Msk       (0x1UL)  /*!< CINV (Bitfield-Mask: 0x01)                            */
31700 /* ========================================================  CMPSEL0  ======================================================== */
31701  #define R_ACMPHS0_CMPSEL0_CMPSEL_Pos    (0UL)    /*!< CMPSEL (Bit 0)                                        */
31702  #define R_ACMPHS0_CMPSEL0_CMPSEL_Msk    (0xfUL)  /*!< CMPSEL (Bitfield-Mask: 0x0f)                          */
31703 /* ========================================================  CMPSEL1  ======================================================== */
31704  #define R_ACMPHS0_CMPSEL1_CRVS_Pos      (0UL)    /*!< CRVS (Bit 0)                                          */
31705  #define R_ACMPHS0_CMPSEL1_CRVS_Msk      (0x3fUL) /*!< CRVS (Bitfield-Mask: 0x3f)                            */
31706 /* ========================================================  CMPMON  ========================================================= */
31707  #define R_ACMPHS0_CMPMON_CMPMON_Pos     (0UL)    /*!< CMPMON (Bit 0)                                        */
31708  #define R_ACMPHS0_CMPMON_CMPMON_Msk     (0x1UL)  /*!< CMPMON (Bitfield-Mask: 0x01)                          */
31709 /* =========================================================  CPIOC  ========================================================= */
31710  #define R_ACMPHS0_CPIOC_VREFEN_Pos      (7UL)    /*!< VREFEN (Bit 7)                                        */
31711  #define R_ACMPHS0_CPIOC_VREFEN_Msk      (0x80UL) /*!< VREFEN (Bitfield-Mask: 0x01)                          */
31712  #define R_ACMPHS0_CPIOC_CPOE_Pos        (0UL)    /*!< CPOE (Bit 0)                                          */
31713  #define R_ACMPHS0_CPIOC_CPOE_Msk        (0x1UL)  /*!< CPOE (Bitfield-Mask: 0x01)                            */
31714 
31715 /* =========================================================================================================================== */
31716 /* ================                                          R_ADC0                                           ================ */
31717 /* =========================================================================================================================== */
31718 
31719 /* =========================================================  ADCSR  ========================================================= */
31720  #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
31721  #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
31722  #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
31723  #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
31724  #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
31725  #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
31726  #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
31727  #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
31728  #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
31729  #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
31730  #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
31731  #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
31732  #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
31733  #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
31734  #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
31735  #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
31736  #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
31737  #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
31738 /* ========================================================  ADANSA  ========================================================= */
31739  #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
31740  #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
31741 /* =========================================================  ADADS  ========================================================= */
31742  #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
31743  #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
31744 /* =========================================================  ADADC  ========================================================= */
31745  #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
31746  #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
31747  #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
31748  #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
31749 /* =========================================================  ADCER  ========================================================= */
31750  #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
31751  #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
31752  #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
31753  #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
31754  #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
31755  #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
31756  #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
31757  #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
31758  #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
31759  #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
31760  #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
31761  #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
31762  #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
31763  #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
31764  #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
31765  #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
31766 /* ========================================================  ADSTRGR  ======================================================== */
31767  #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
31768  #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
31769  #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
31770  #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
31771 /* ========================================================  ADEXICR  ======================================================== */
31772  #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
31773  #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
31774  #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
31775  #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
31776  #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
31777  #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
31778  #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
31779  #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
31780  #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
31781  #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
31782  #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
31783  #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
31784  #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
31785  #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
31786  #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
31787  #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
31788 /* ========================================================  ADANSB  ========================================================= */
31789  #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
31790  #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
31791 /* ========================================================  ADDBLDR  ======================================================== */
31792  #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
31793  #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
31794 /* ========================================================  ADTSDR  ========================================================= */
31795  #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
31796  #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
31797 /* ========================================================  ADOCDR  ========================================================= */
31798  #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
31799  #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
31800 /* ======================================================  ADRD_RIGHT  ======================================================= */
31801  #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
31802  #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
31803  #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
31804  #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
31805 /* =======================================================  ADRD_LEFT  ======================================================= */
31806  #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
31807  #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
31808  #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
31809  #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
31810 /* =========================================================  ADDR  ========================================================== */
31811  #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
31812  #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
31813 /* ========================================================  ADSHCR  ========================================================= */
31814  #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
31815  #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
31816  #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
31817  #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
31818  #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
31819  #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
31820  #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
31821  #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
31822 /* ========================================================  ADDISCR  ======================================================== */
31823  #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
31824  #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
31825  #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
31826  #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
31827 /* ========================================================  ADSHMSR  ======================================================== */
31828  #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
31829  #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
31830 /* ========================================================  ADACSR  ========================================================= */
31831  #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
31832  #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
31833 /* ========================================================  ADGSPCR  ======================================================== */
31834  #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
31835  #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
31836  #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
31837  #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
31838  #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
31839  #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
31840  #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
31841  #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
31842 /* =========================================================  ADICR  ========================================================= */
31843  #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
31844  #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
31845 /* =======================================================  ADDBLDRA  ======================================================== */
31846  #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
31847  #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
31848 /* =======================================================  ADDBLDRB  ======================================================== */
31849  #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
31850  #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
31851 /* ======================================================  ADHVREFCNT  ======================================================= */
31852  #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
31853  #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
31854  #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
31855  #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
31856  #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
31857  #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
31858 /* =======================================================  ADWINMON  ======================================================== */
31859  #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
31860  #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
31861  #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
31862  #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
31863  #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
31864  #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
31865 /* ========================================================  ADCMPCR  ======================================================== */
31866  #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
31867  #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
31868  #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
31869  #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
31870  #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
31871  #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
31872  #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
31873  #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
31874  #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
31875  #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
31876  #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
31877  #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
31878 /* ======================================================  ADCMPANSER  ======================================================= */
31879  #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
31880  #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
31881  #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
31882  #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
31883 /* =======================================================  ADCMPLER  ======================================================== */
31884  #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
31885  #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
31886  #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
31887  #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
31888 /* =======================================================  ADCMPANSR  ======================================================= */
31889  #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
31890  #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
31891 /* ========================================================  ADCMPLR  ======================================================== */
31892  #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
31893  #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
31894 /* =======================================================  ADCMPDR0  ======================================================== */
31895  #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
31896  #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
31897 /* =======================================================  ADCMPDR1  ======================================================== */
31898  #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
31899  #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
31900 /* ========================================================  ADCMPSR  ======================================================== */
31901  #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
31902  #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
31903 /* =======================================================  ADCMPSER  ======================================================== */
31904  #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
31905  #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
31906  #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
31907  #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
31908 /* =======================================================  ADCMPBNSR  ======================================================= */
31909  #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
31910  #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
31911  #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
31912  #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
31913 /* =======================================================  ADWINLLB  ======================================================== */
31914  #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
31915  #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
31916 /* =======================================================  ADWINULB  ======================================================== */
31917  #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
31918  #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
31919 /* =======================================================  ADCMPBSR  ======================================================== */
31920  #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
31921  #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
31922 /* ========================================================  ADSSTRL  ======================================================== */
31923  #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
31924  #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
31925 /* ========================================================  ADSSTRT  ======================================================== */
31926  #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
31927  #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
31928 /* ========================================================  ADSSTRO  ======================================================== */
31929  #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
31930  #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
31931 /* ========================================================  ADSSTR  ========================================================= */
31932  #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
31933  #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
31934 /* ========================================================  ADPGACR  ======================================================== */
31935  #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
31936  #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
31937  #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
31938  #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
31939  #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
31940  #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
31941  #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
31942  #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
31943  #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
31944  #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
31945  #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
31946  #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
31947  #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
31948  #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
31949  #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
31950  #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
31951  #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
31952  #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
31953  #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
31954  #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
31955  #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
31956  #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
31957  #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
31958  #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
31959  #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
31960  #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
31961  #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
31962  #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
31963  #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
31964  #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
31965  #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
31966  #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
31967 /* =========================================================  ADRD  ========================================================== */
31968  #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
31969  #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
31970 /* =========================================================  ADRST  ========================================================= */
31971  #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
31972  #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
31973 /* ======================================================  VREFAMPCNT  ======================================================= */
31974  #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
31975  #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
31976  #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
31977  #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
31978  #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
31979  #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
31980  #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
31981  #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
31982  #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
31983  #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
31984 /* =======================================================  ADCALEXE  ======================================================== */
31985  #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
31986  #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
31987  #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
31988  #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
31989 /* ========================================================  ADANIM  ========================================================= */
31990  #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
31991  #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
31992 /* =======================================================  ADPGAGS0  ======================================================== */
31993  #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
31994  #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
31995  #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
31996  #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
31997  #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
31998  #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
31999  #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
32000  #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
32001 /* =======================================================  ADPGADCR0  ======================================================= */
32002  #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
32003  #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
32004  #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
32005  #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
32006  #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
32007  #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
32008  #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
32009  #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
32010  #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
32011  #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
32012  #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
32013  #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
32014  #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
32015  #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
32016  #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
32017  #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
32018 /* =========================================================  ADREF  ========================================================= */
32019  #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
32020  #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
32021  #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
32022  #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
32023 /* ========================================================  ADEXREF  ======================================================== */
32024  #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
32025  #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
32026 /* =======================================================  ADAMPOFF  ======================================================== */
32027  #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
32028  #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
32029 /* ========================================================  ADTSTPR  ======================================================== */
32030  #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
32031  #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
32032  #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
32033  #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
32034 /* =======================================================  ADDDACER  ======================================================== */
32035  #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
32036  #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
32037  #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
32038  #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
32039  #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
32040  #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
32041 /* =======================================================  ADEXTSTR  ======================================================== */
32042  #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
32043  #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
32044  #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
32045  #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
32046  #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
32047  #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
32048  #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
32049  #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
32050  #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
32051  #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
32052  #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
32053  #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
32054 /* ========================================================  ADTSTRA  ======================================================== */
32055  #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
32056  #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
32057  #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
32058  #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
32059  #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
32060  #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
32061  #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
32062  #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
32063  #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
32064  #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
32065  #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
32066  #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
32067 /* ========================================================  ADTSTRB  ======================================================== */
32068  #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
32069  #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
32070 /* ========================================================  ADTSTRC  ======================================================== */
32071  #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
32072  #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
32073  #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
32074  #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
32075 /* ========================================================  ADTSTRD  ======================================================== */
32076  #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
32077  #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
32078 /* =======================================================  ADSWTSTR0  ======================================================= */
32079  #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
32080  #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
32081  #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
32082  #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
32083  #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
32084  #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
32085  #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
32086  #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
32087  #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
32088  #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
32089  #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
32090  #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
32091 /* =======================================================  ADSWTSTR1  ======================================================= */
32092  #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
32093  #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
32094  #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
32095  #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
32096  #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
32097  #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
32098  #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
32099  #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
32100  #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
32101  #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
32102  #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
32103  #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
32104 /* =======================================================  ADSWTSTR2  ======================================================= */
32105  #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
32106  #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
32107  #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
32108  #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
32109  #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
32110  #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
32111  #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
32112  #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
32113  #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
32114  #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
32115  #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
32116  #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
32117  #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
32118  #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
32119  #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
32120  #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
32121  #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
32122  #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
32123  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
32124  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
32125 /* ========================================================  ADSWCR  ========================================================= */
32126  #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
32127  #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
32128  #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
32129  #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
32130 /* ========================================================  ADGSCS  ========================================================= */
32131  #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
32132  #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
32133  #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
32134  #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
32135 /* =========================================================  ADSER  ========================================================= */
32136  #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
32137  #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
32138 /* ========================================================  ADBUF0  ========================================================= */
32139  #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32140  #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32141 /* ========================================================  ADBUF1  ========================================================= */
32142  #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32143  #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32144 /* ========================================================  ADBUF2  ========================================================= */
32145  #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32146  #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32147 /* ========================================================  ADBUF3  ========================================================= */
32148  #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32149  #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32150 /* ========================================================  ADBUF4  ========================================================= */
32151  #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32152  #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32153 /* ========================================================  ADBUF5  ========================================================= */
32154  #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32155  #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32156 /* ========================================================  ADBUF6  ========================================================= */
32157  #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32158  #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32159 /* ========================================================  ADBUF7  ========================================================= */
32160  #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32161  #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32162 /* ========================================================  ADBUF8  ========================================================= */
32163  #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32164  #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32165 /* ========================================================  ADBUF9  ========================================================= */
32166  #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
32167  #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32168 /* ========================================================  ADBUF10  ======================================================== */
32169  #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
32170  #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32171 /* ========================================================  ADBUF11  ======================================================== */
32172  #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
32173  #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32174 /* ========================================================  ADBUF12  ======================================================== */
32175  #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
32176  #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32177 /* ========================================================  ADBUF13  ======================================================== */
32178  #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
32179  #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32180 /* ========================================================  ADBUF14  ======================================================== */
32181  #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
32182  #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32183 /* ========================================================  ADBUF15  ======================================================== */
32184  #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
32185  #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
32186 /* ========================================================  ADBUFEN  ======================================================== */
32187  #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
32188  #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
32189 /* =======================================================  ADBUFPTR  ======================================================== */
32190  #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
32191  #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
32192  #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
32193  #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
32194 /* =======================================================  ADPGADBS0  ======================================================= */
32195  #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
32196  #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
32197 /* =======================================================  ADPGADBS1  ======================================================= */
32198  #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
32199  #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
32200 /* =======================================================  ADREFMON  ======================================================== */
32201  #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
32202  #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
32203  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
32204  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
32205 
32206 /* =========================================================================================================================== */
32207 /* ================                                          R_PSCU                                           ================ */
32208 /* =========================================================================================================================== */
32209 
32210 /* =========================================================  PSARB  ========================================================= */
32211  #define R_PSCU_PSARB_PSARB4_Pos     (4UL)          /*!< PSARB4 (Bit 4)                                        */
32212  #define R_PSCU_PSARB_PSARB4_Msk     (0x10UL)       /*!< PSARB4 (Bitfield-Mask: 0x01)                          */
32213  #define R_PSCU_PSARB_PSARB8_Pos     (8UL)          /*!< PSARB8 (Bit 8)                                        */
32214  #define R_PSCU_PSARB_PSARB8_Msk     (0x100UL)      /*!< PSARB8 (Bitfield-Mask: 0x01)                          */
32215  #define R_PSCU_PSARB_PSARB9_Pos     (9UL)          /*!< PSARB9 (Bit 9)                                        */
32216  #define R_PSCU_PSARB_PSARB9_Msk     (0x200UL)      /*!< PSARB9 (Bitfield-Mask: 0x01)                          */
32217  #define R_PSCU_PSARB_PSARB11_Pos    (11UL)         /*!< PSARB11 (Bit 11)                                      */
32218  #define R_PSCU_PSARB_PSARB11_Msk    (0x800UL)      /*!< PSARB11 (Bitfield-Mask: 0x01)                         */
32219  #define R_PSCU_PSARB_PSARB12_Pos    (12UL)         /*!< PSARB12 (Bit 12)                                      */
32220  #define R_PSCU_PSARB_PSARB12_Msk    (0x1000UL)     /*!< PSARB12 (Bitfield-Mask: 0x01)                         */
32221  #define R_PSCU_PSARB_PSARB15_Pos    (15UL)         /*!< PSARB15 (Bit 15)                                      */
32222  #define R_PSCU_PSARB_PSARB15_Msk    (0x8000UL)     /*!< PSARB15 (Bitfield-Mask: 0x01)                         */
32223  #define R_PSCU_PSARB_PSARB16_Pos    (16UL)         /*!< PSARB16 (Bit 16)                                      */
32224  #define R_PSCU_PSARB_PSARB16_Msk    (0x10000UL)    /*!< PSARB16 (Bitfield-Mask: 0x01)                         */
32225  #define R_PSCU_PSARB_PSARB18_Pos    (18UL)         /*!< PSARB18 (Bit 18)                                      */
32226  #define R_PSCU_PSARB_PSARB18_Msk    (0x40000UL)    /*!< PSARB18 (Bitfield-Mask: 0x01)                         */
32227  #define R_PSCU_PSARB_PSARB19_Pos    (19UL)         /*!< PSARB19 (Bit 19)                                      */
32228  #define R_PSCU_PSARB_PSARB19_Msk    (0x80000UL)    /*!< PSARB19 (Bitfield-Mask: 0x01)                         */
32229  #define R_PSCU_PSARB_PSARB22_Pos    (22UL)         /*!< PSARB22 (Bit 22)                                      */
32230  #define R_PSCU_PSARB_PSARB22_Msk    (0x400000UL)   /*!< PSARB22 (Bitfield-Mask: 0x01)                         */
32231  #define R_PSCU_PSARB_PSARB27_Pos    (27UL)         /*!< PSARB27 (Bit 27)                                      */
32232  #define R_PSCU_PSARB_PSARB27_Msk    (0x8000000UL)  /*!< PSARB27 (Bitfield-Mask: 0x01)                         */
32233  #define R_PSCU_PSARB_PSARB28_Pos    (28UL)         /*!< PSARB28 (Bit 28)                                      */
32234  #define R_PSCU_PSARB_PSARB28_Msk    (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01)                         */
32235  #define R_PSCU_PSARB_PSARB29_Pos    (29UL)         /*!< PSARB29 (Bit 29)                                      */
32236  #define R_PSCU_PSARB_PSARB29_Msk    (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01)                         */
32237  #define R_PSCU_PSARB_PSARB30_Pos    (30UL)         /*!< PSARB30 (Bit 30)                                      */
32238  #define R_PSCU_PSARB_PSARB30_Msk    (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01)                         */
32239  #define R_PSCU_PSARB_PSARB31_Pos    (31UL)         /*!< PSARB31 (Bit 31)                                      */
32240  #define R_PSCU_PSARB_PSARB31_Msk    (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01)                         */
32241 /* =========================================================  PSARC  ========================================================= */
32242  #define R_PSCU_PSARC_PSARC0_Pos     (0UL)          /*!< PSARC0 (Bit 0)                                        */
32243  #define R_PSCU_PSARC_PSARC0_Msk     (0x1UL)        /*!< PSARC0 (Bitfield-Mask: 0x01)                          */
32244  #define R_PSCU_PSARC_PSARC1_Pos     (1UL)          /*!< PSARC1 (Bit 1)                                        */
32245  #define R_PSCU_PSARC_PSARC1_Msk     (0x2UL)        /*!< PSARC1 (Bitfield-Mask: 0x01)                          */
32246  #define R_PSCU_PSARC_PSARC7_Pos     (7UL)          /*!< PSARC7 (Bit 7)                                        */
32247  #define R_PSCU_PSARC_PSARC7_Msk     (0x80UL)       /*!< PSARC7 (Bitfield-Mask: 0x01)                          */
32248  #define R_PSCU_PSARC_PSARC8_Pos     (8UL)          /*!< PSARC8 (Bit 8)                                        */
32249  #define R_PSCU_PSARC_PSARC8_Msk     (0x100UL)      /*!< PSARC8 (Bitfield-Mask: 0x01)                          */
32250  #define R_PSCU_PSARC_PSARC11_Pos    (11UL)         /*!< PSARC11 (Bit 11)                                      */
32251  #define R_PSCU_PSARC_PSARC11_Msk    (0x800UL)      /*!< PSARC11 (Bitfield-Mask: 0x01)                         */
32252  #define R_PSCU_PSARC_PSARC12_Pos    (12UL)         /*!< PSARC12 (Bit 12)                                      */
32253  #define R_PSCU_PSARC_PSARC12_Msk    (0x1000UL)     /*!< PSARC12 (Bitfield-Mask: 0x01)                         */
32254  #define R_PSCU_PSARC_PSARC13_Pos    (13UL)         /*!< PSARC13 (Bit 13)                                      */
32255  #define R_PSCU_PSARC_PSARC13_Msk    (0x2000UL)     /*!< PSARC13 (Bitfield-Mask: 0x01)                         */
32256  #define R_PSCU_PSARC_PSARC15_Pos    (15UL)         /*!< PSARC15 (Bit 15)                                      */
32257  #define R_PSCU_PSARC_PSARC15_Msk    (0x8000UL)     /*!< PSARC15 (Bitfield-Mask: 0x01)                         */
32258  #define R_PSCU_PSARC_PSARC16_Pos    (16UL)         /*!< PSARC16 (Bit 16)                                      */
32259  #define R_PSCU_PSARC_PSARC16_Msk    (0x10000UL)    /*!< PSARC16 (Bitfield-Mask: 0x01)                         */
32260  #define R_PSCU_PSARC_PSARC26_Pos    (26UL)         /*!< PSARC26 (Bit 26)                                      */
32261  #define R_PSCU_PSARC_PSARC26_Msk    (0x4000000UL)  /*!< PSARC26 (Bitfield-Mask: 0x01)                         */
32262  #define R_PSCU_PSARC_PSARC27_Pos    (27UL)         /*!< PSARC27 (Bit 27)                                      */
32263  #define R_PSCU_PSARC_PSARC27_Msk    (0x8000000UL)  /*!< PSARC27 (Bitfield-Mask: 0x01)                         */
32264  #define R_PSCU_PSARC_PSARC31_Pos    (31UL)         /*!< PSARC31 (Bit 31)                                      */
32265  #define R_PSCU_PSARC_PSARC31_Msk    (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01)                         */
32266 /* =========================================================  PSARD  ========================================================= */
32267  #define R_PSCU_PSARD_PSARD4_Pos     (4UL)          /*!< PSARD4 (Bit 4)                                        */
32268  #define R_PSCU_PSARD_PSARD4_Msk     (0x10UL)       /*!< PSARD4 (Bitfield-Mask: 0x01)                          */
32269  #define R_PSCU_PSARD_PSARD5_Pos     (5UL)          /*!< PSARD5 (Bit 5)                                        */
32270  #define R_PSCU_PSARD_PSARD5_Msk     (0x20UL)       /*!< PSARD5 (Bitfield-Mask: 0x01)                          */
32271  #define R_PSCU_PSARD_PSARD11_Pos    (11UL)         /*!< PSARD11 (Bit 11)                                      */
32272  #define R_PSCU_PSARD_PSARD11_Msk    (0x800UL)      /*!< PSARD11 (Bitfield-Mask: 0x01)                         */
32273  #define R_PSCU_PSARD_PSARD12_Pos    (12UL)         /*!< PSARD12 (Bit 12)                                      */
32274  #define R_PSCU_PSARD_PSARD12_Msk    (0x1000UL)     /*!< PSARD12 (Bitfield-Mask: 0x01)                         */
32275  #define R_PSCU_PSARD_PSARD13_Pos    (13UL)         /*!< PSARD13 (Bit 13)                                      */
32276  #define R_PSCU_PSARD_PSARD13_Msk    (0x2000UL)     /*!< PSARD13 (Bitfield-Mask: 0x01)                         */
32277  #define R_PSCU_PSARD_PSARD14_Pos    (14UL)         /*!< PSARD14 (Bit 14)                                      */
32278  #define R_PSCU_PSARD_PSARD14_Msk    (0x4000UL)     /*!< PSARD14 (Bitfield-Mask: 0x01)                         */
32279  #define R_PSCU_PSARD_PSARD15_Pos    (15UL)         /*!< PSARD15 (Bit 15)                                      */
32280  #define R_PSCU_PSARD_PSARD15_Msk    (0x8000UL)     /*!< PSARD15 (Bitfield-Mask: 0x01)                         */
32281  #define R_PSCU_PSARD_PSARD16_Pos    (16UL)         /*!< PSARD16 (Bit 16)                                      */
32282  #define R_PSCU_PSARD_PSARD16_Msk    (0x10000UL)    /*!< PSARD16 (Bitfield-Mask: 0x01)                         */
32283  #define R_PSCU_PSARD_PSARD20_Pos    (20UL)         /*!< PSARD20 (Bit 20)                                      */
32284  #define R_PSCU_PSARD_PSARD20_Msk    (0x100000UL)   /*!< PSARD20 (Bitfield-Mask: 0x01)                         */
32285  #define R_PSCU_PSARD_PSARD22_Pos    (22UL)         /*!< PSARD22 (Bit 22)                                      */
32286  #define R_PSCU_PSARD_PSARD22_Msk    (0x400000UL)   /*!< PSARD22 (Bitfield-Mask: 0x01)                         */
32287  #define R_PSCU_PSARD_PSARD27_Pos    (27UL)         /*!< PSARD27 (Bit 27)                                      */
32288  #define R_PSCU_PSARD_PSARD27_Msk    (0x8000000UL)  /*!< PSARD27 (Bitfield-Mask: 0x01)                         */
32289  #define R_PSCU_PSARD_PSARD28_Pos    (28UL)         /*!< PSARD28 (Bit 28)                                      */
32290  #define R_PSCU_PSARD_PSARD28_Msk    (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01)                         */
32291 /* =========================================================  PSARE  ========================================================= */
32292  #define R_PSCU_PSARE_PSARE1_Pos     (1UL)          /*!< PSARE1 (Bit 1)                                        */
32293  #define R_PSCU_PSARE_PSARE1_Msk     (0x2UL)        /*!< PSARE1 (Bitfield-Mask: 0x01)                          */
32294  #define R_PSCU_PSARE_PSARE2_Pos     (2UL)          /*!< PSARE2 (Bit 2)                                        */
32295  #define R_PSCU_PSARE_PSARE2_Msk     (0x4UL)        /*!< PSARE2 (Bitfield-Mask: 0x01)                          */
32296  #define R_PSCU_PSARE_PSARE3_Pos     (3UL)          /*!< PSARE3 (Bit 3)                                        */
32297  #define R_PSCU_PSARE_PSARE3_Msk     (0x8UL)        /*!< PSARE3 (Bitfield-Mask: 0x01)                          */
32298  #define R_PSCU_PSARE_PSARE8_Pos     (8UL)          /*!< PSARE8 (Bit 8)                                        */
32299  #define R_PSCU_PSARE_PSARE8_Msk     (0x100UL)      /*!< PSARE8 (Bitfield-Mask: 0x01)                          */
32300  #define R_PSCU_PSARE_PSARE9_Pos     (9UL)          /*!< PSARE9 (Bit 9)                                        */
32301  #define R_PSCU_PSARE_PSARE9_Msk     (0x200UL)      /*!< PSARE9 (Bitfield-Mask: 0x01)                          */
32302  #define R_PSCU_PSARE_PSARE18_Pos    (18UL)         /*!< PSARE18 (Bit 18)                                      */
32303  #define R_PSCU_PSARE_PSARE18_Msk    (0x40000UL)    /*!< PSARE18 (Bitfield-Mask: 0x01)                         */
32304  #define R_PSCU_PSARE_PSARE19_Pos    (19UL)         /*!< PSARE19 (Bit 19)                                      */
32305  #define R_PSCU_PSARE_PSARE19_Msk    (0x80000UL)    /*!< PSARE19 (Bitfield-Mask: 0x01)                         */
32306  #define R_PSCU_PSARE_PSARE20_Pos    (20UL)         /*!< PSARE20 (Bit 20)                                      */
32307  #define R_PSCU_PSARE_PSARE20_Msk    (0x100000UL)   /*!< PSARE20 (Bitfield-Mask: 0x01)                         */
32308  #define R_PSCU_PSARE_PSARE21_Pos    (21UL)         /*!< PSARE21 (Bit 21)                                      */
32309  #define R_PSCU_PSARE_PSARE21_Msk    (0x200000UL)   /*!< PSARE21 (Bitfield-Mask: 0x01)                         */
32310  #define R_PSCU_PSARE_PSARE22_Pos    (22UL)         /*!< PSARE22 (Bit 22)                                      */
32311  #define R_PSCU_PSARE_PSARE22_Msk    (0x400000UL)   /*!< PSARE22 (Bitfield-Mask: 0x01)                         */
32312  #define R_PSCU_PSARE_PSARE23_Pos    (23UL)         /*!< PSARE23 (Bit 23)                                      */
32313  #define R_PSCU_PSARE_PSARE23_Msk    (0x800000UL)   /*!< PSARE23 (Bitfield-Mask: 0x01)                         */
32314  #define R_PSCU_PSARE_PSARE24_Pos    (24UL)         /*!< PSARE24 (Bit 24)                                      */
32315  #define R_PSCU_PSARE_PSARE24_Msk    (0x1000000UL)  /*!< PSARE24 (Bitfield-Mask: 0x01)                         */
32316  #define R_PSCU_PSARE_PSARE25_Pos    (25UL)         /*!< PSARE25 (Bit 25)                                      */
32317  #define R_PSCU_PSARE_PSARE25_Msk    (0x2000000UL)  /*!< PSARE25 (Bitfield-Mask: 0x01)                         */
32318  #define R_PSCU_PSARE_PSARE26_Pos    (26UL)         /*!< PSARE26 (Bit 26)                                      */
32319  #define R_PSCU_PSARE_PSARE26_Msk    (0x4000000UL)  /*!< PSARE26 (Bitfield-Mask: 0x01)                         */
32320  #define R_PSCU_PSARE_PSARE27_Pos    (27UL)         /*!< PSARE27 (Bit 27)                                      */
32321  #define R_PSCU_PSARE_PSARE27_Msk    (0x8000000UL)  /*!< PSARE27 (Bitfield-Mask: 0x01)                         */
32322  #define R_PSCU_PSARE_PSARE28_Pos    (28UL)         /*!< PSARE28 (Bit 28)                                      */
32323  #define R_PSCU_PSARE_PSARE28_Msk    (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01)                         */
32324  #define R_PSCU_PSARE_PSARE29_Pos    (29UL)         /*!< PSARE29 (Bit 29)                                      */
32325  #define R_PSCU_PSARE_PSARE29_Msk    (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01)                         */
32326  #define R_PSCU_PSARE_PSARE30_Pos    (30UL)         /*!< PSARE30 (Bit 30)                                      */
32327  #define R_PSCU_PSARE_PSARE30_Msk    (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01)                         */
32328  #define R_PSCU_PSARE_PSARE31_Pos    (31UL)         /*!< PSARE31 (Bit 31)                                      */
32329  #define R_PSCU_PSARE_PSARE31_Msk    (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01)                         */
32330 /* =========================================================  MSSAR  ========================================================= */
32331  #define R_PSCU_MSSAR_MSSAR0_Pos     (0UL)          /*!< MSSAR0 (Bit 0)                                        */
32332  #define R_PSCU_MSSAR_MSSAR0_Msk     (0x1UL)        /*!< MSSAR0 (Bitfield-Mask: 0x01)                          */
32333  #define R_PSCU_MSSAR_MSSAR1_Pos     (1UL)          /*!< MSSAR1 (Bit 1)                                        */
32334  #define R_PSCU_MSSAR_MSSAR1_Msk     (0x2UL)        /*!< MSSAR1 (Bitfield-Mask: 0x01)                          */
32335  #define R_PSCU_MSSAR_MSSAR11_Pos    (11UL)         /*!< MSSAR11 (Bit 11)                                      */
32336  #define R_PSCU_MSSAR_MSSAR11_Msk    (0x800UL)      /*!< MSSAR11 (Bitfield-Mask: 0x01)                         */
32337  #define R_PSCU_MSSAR_MSSAR13_Pos    (13UL)         /*!< MSSAR13 (Bit 13)                                      */
32338  #define R_PSCU_MSSAR_MSSAR13_Msk    (0x2000UL)     /*!< MSSAR13 (Bitfield-Mask: 0x01)                         */
32339  #define R_PSCU_MSSAR_MSSAR15_Pos    (15UL)         /*!< MSSAR15 (Bit 15)                                      */
32340  #define R_PSCU_MSSAR_MSSAR15_Msk    (0x8000UL)     /*!< MSSAR15 (Bitfield-Mask: 0x01)                         */
32341  #define R_PSCU_MSSAR_MSSAR22_Pos    (22UL)         /*!< MSSAR22 (Bit 22)                                      */
32342  #define R_PSCU_MSSAR_MSSAR22_Msk    (0x400000UL)   /*!< MSSAR22 (Bitfield-Mask: 0x01)                         */
32343  #define R_PSCU_MSSAR_MSSAR31_Pos    (31UL)         /*!< MSSAR31 (Bit 31)                                      */
32344  #define R_PSCU_MSSAR_MSSAR31_Msk    (0x80000000UL) /*!< MSSAR31 (Bitfield-Mask: 0x01)                         */
32345 /* =========================================================  PPARB  ========================================================= */
32346  #define R_PSCU_PPARB_PPARB4_Pos     (4UL)          /*!< PPARB4 (Bit 4)                                        */
32347  #define R_PSCU_PPARB_PPARB4_Msk     (0x10UL)       /*!< PPARB4 (Bitfield-Mask: 0x01)                          */
32348  #define R_PSCU_PPARB_PPARB8_Pos     (8UL)          /*!< PPARB8 (Bit 8)                                        */
32349  #define R_PSCU_PPARB_PPARB8_Msk     (0x100UL)      /*!< PPARB8 (Bitfield-Mask: 0x01)                          */
32350  #define R_PSCU_PPARB_PPARB9_Pos     (9UL)          /*!< PPARB9 (Bit 9)                                        */
32351  #define R_PSCU_PPARB_PPARB9_Msk     (0x200UL)      /*!< PPARB9 (Bitfield-Mask: 0x01)                          */
32352  #define R_PSCU_PPARB_PPARB11_Pos    (11UL)         /*!< PPARB11 (Bit 11)                                      */
32353  #define R_PSCU_PPARB_PPARB11_Msk    (0x800UL)      /*!< PPARB11 (Bitfield-Mask: 0x01)                         */
32354  #define R_PSCU_PPARB_PPARB12_Pos    (12UL)         /*!< PPARB12 (Bit 12)                                      */
32355  #define R_PSCU_PPARB_PPARB12_Msk    (0x1000UL)     /*!< PPARB12 (Bitfield-Mask: 0x01)                         */
32356  #define R_PSCU_PPARB_PPARB15_Pos    (15UL)         /*!< PPARB15 (Bit 15)                                      */
32357  #define R_PSCU_PPARB_PPARB15_Msk    (0x8000UL)     /*!< PPARB15 (Bitfield-Mask: 0x01)                         */
32358  #define R_PSCU_PPARB_PPARB16_Pos    (16UL)         /*!< PPARB16 (Bit 16)                                      */
32359  #define R_PSCU_PPARB_PPARB16_Msk    (0x10000UL)    /*!< PPARB16 (Bitfield-Mask: 0x01)                         */
32360  #define R_PSCU_PPARB_PPARB18_Pos    (18UL)         /*!< PPARB18 (Bit 18)                                      */
32361  #define R_PSCU_PPARB_PPARB18_Msk    (0x40000UL)    /*!< PPARB18 (Bitfield-Mask: 0x01)                         */
32362  #define R_PSCU_PPARB_PPARB19_Pos    (19UL)         /*!< PPARB19 (Bit 19)                                      */
32363  #define R_PSCU_PPARB_PPARB19_Msk    (0x80000UL)    /*!< PPARB19 (Bitfield-Mask: 0x01)                         */
32364  #define R_PSCU_PPARB_PPARB22_Pos    (22UL)         /*!< PPARB22 (Bit 22)                                      */
32365  #define R_PSCU_PPARB_PPARB22_Msk    (0x400000UL)   /*!< PPARB22 (Bitfield-Mask: 0x01)                         */
32366  #define R_PSCU_PPARB_PPARB27_Pos    (27UL)         /*!< PPARB27 (Bit 27)                                      */
32367  #define R_PSCU_PPARB_PPARB27_Msk    (0x8000000UL)  /*!< PPARB27 (Bitfield-Mask: 0x01)                         */
32368  #define R_PSCU_PPARB_PPARB28_Pos    (28UL)         /*!< PPARB28 (Bit 28)                                      */
32369  #define R_PSCU_PPARB_PPARB28_Msk    (0x10000000UL) /*!< PPARB28 (Bitfield-Mask: 0x01)                         */
32370  #define R_PSCU_PPARB_PPARB29_Pos    (29UL)         /*!< PPARB29 (Bit 29)                                      */
32371  #define R_PSCU_PPARB_PPARB29_Msk    (0x20000000UL) /*!< PPARB29 (Bitfield-Mask: 0x01)                         */
32372  #define R_PSCU_PPARB_PPARB30_Pos    (30UL)         /*!< PPARB30 (Bit 30)                                      */
32373  #define R_PSCU_PPARB_PPARB30_Msk    (0x40000000UL) /*!< PPARB30 (Bitfield-Mask: 0x01)                         */
32374  #define R_PSCU_PPARB_PPARB31_Pos    (31UL)         /*!< PPARB31 (Bit 31)                                      */
32375  #define R_PSCU_PPARB_PPARB31_Msk    (0x80000000UL) /*!< PPARB31 (Bitfield-Mask: 0x01)                         */
32376 /* =========================================================  PPARC  ========================================================= */
32377  #define R_PSCU_PPARC_PPARC0_Pos     (0UL)          /*!< PPARC0 (Bit 0)                                        */
32378  #define R_PSCU_PPARC_PPARC0_Msk     (0x1UL)        /*!< PPARC0 (Bitfield-Mask: 0x01)                          */
32379  #define R_PSCU_PPARC_PPARC1_Pos     (1UL)          /*!< PPARC1 (Bit 1)                                        */
32380  #define R_PSCU_PPARC_PPARC1_Msk     (0x2UL)        /*!< PPARC1 (Bitfield-Mask: 0x01)                          */
32381  #define R_PSCU_PPARC_PPARC7_Pos     (7UL)          /*!< PPARC7 (Bit 7)                                        */
32382  #define R_PSCU_PPARC_PPARC7_Msk     (0x80UL)       /*!< PPARC7 (Bitfield-Mask: 0x01)                          */
32383  #define R_PSCU_PPARC_PPARC8_Pos     (8UL)          /*!< PPARC8 (Bit 8)                                        */
32384  #define R_PSCU_PPARC_PPARC8_Msk     (0x100UL)      /*!< PPARC8 (Bitfield-Mask: 0x01)                          */
32385  #define R_PSCU_PPARC_PPARC11_Pos    (11UL)         /*!< PPARC11 (Bit 11)                                      */
32386  #define R_PSCU_PPARC_PPARC11_Msk    (0x800UL)      /*!< PPARC11 (Bitfield-Mask: 0x01)                         */
32387  #define R_PSCU_PPARC_PPARC12_Pos    (12UL)         /*!< PPARC12 (Bit 12)                                      */
32388  #define R_PSCU_PPARC_PPARC12_Msk    (0x1000UL)     /*!< PPARC12 (Bitfield-Mask: 0x01)                         */
32389  #define R_PSCU_PPARC_PPARC13_Pos    (13UL)         /*!< PPARC13 (Bit 13)                                      */
32390  #define R_PSCU_PPARC_PPARC13_Msk    (0x2000UL)     /*!< PPARC13 (Bitfield-Mask: 0x01)                         */
32391  #define R_PSCU_PPARC_PPARC15_Pos    (15UL)         /*!< PPARC15 (Bit 15)                                      */
32392  #define R_PSCU_PPARC_PPARC15_Msk    (0x8000UL)     /*!< PPARC15 (Bitfield-Mask: 0x01)                         */
32393  #define R_PSCU_PPARC_PPARC16_Pos    (16UL)         /*!< PPARC16 (Bit 16)                                      */
32394  #define R_PSCU_PPARC_PPARC16_Msk    (0x10000UL)    /*!< PPARC16 (Bitfield-Mask: 0x01)                         */
32395  #define R_PSCU_PPARC_PPARC26_Pos    (26UL)         /*!< PPARC26 (Bit 26)                                      */
32396  #define R_PSCU_PPARC_PPARC26_Msk    (0x4000000UL)  /*!< PPARC26 (Bitfield-Mask: 0x01)                         */
32397  #define R_PSCU_PPARC_PPARC27_Pos    (27UL)         /*!< PPARC27 (Bit 27)                                      */
32398  #define R_PSCU_PPARC_PPARC27_Msk    (0x8000000UL)  /*!< PPARC27 (Bitfield-Mask: 0x01)                         */
32399  #define R_PSCU_PPARC_PPARC31_Pos    (31UL)         /*!< PPARC31 (Bit 31)                                      */
32400  #define R_PSCU_PPARC_PPARC31_Msk    (0x80000000UL) /*!< PPARC31 (Bitfield-Mask: 0x01)                         */
32401 /* =========================================================  PPARD  ========================================================= */
32402  #define R_PSCU_PPARD_PPARD4_Pos     (4UL)          /*!< PPARD4 (Bit 4)                                        */
32403  #define R_PSCU_PPARD_PPARD4_Msk     (0x10UL)       /*!< PPARD4 (Bitfield-Mask: 0x01)                          */
32404  #define R_PSCU_PPARD_PPARD5_Pos     (5UL)          /*!< PPARD5 (Bit 5)                                        */
32405  #define R_PSCU_PPARD_PPARD5_Msk     (0x20UL)       /*!< PPARD5 (Bitfield-Mask: 0x01)                          */
32406  #define R_PSCU_PPARD_PPARD11_Pos    (11UL)         /*!< PPARD11 (Bit 11)                                      */
32407  #define R_PSCU_PPARD_PPARD11_Msk    (0x800UL)      /*!< PPARD11 (Bitfield-Mask: 0x01)                         */
32408  #define R_PSCU_PPARD_PPARD12_Pos    (12UL)         /*!< PPARD12 (Bit 12)                                      */
32409  #define R_PSCU_PPARD_PPARD12_Msk    (0x1000UL)     /*!< PPARD12 (Bitfield-Mask: 0x01)                         */
32410  #define R_PSCU_PPARD_PPARD13_Pos    (13UL)         /*!< PPARD13 (Bit 13)                                      */
32411  #define R_PSCU_PPARD_PPARD13_Msk    (0x2000UL)     /*!< PPARD13 (Bitfield-Mask: 0x01)                         */
32412  #define R_PSCU_PPARD_PPARD14_Pos    (14UL)         /*!< PPARD14 (Bit 14)                                      */
32413  #define R_PSCU_PPARD_PPARD14_Msk    (0x4000UL)     /*!< PPARD14 (Bitfield-Mask: 0x01)                         */
32414  #define R_PSCU_PPARD_PPARD15_Pos    (15UL)         /*!< PPARD15 (Bit 15)                                      */
32415  #define R_PSCU_PPARD_PPARD15_Msk    (0x8000UL)     /*!< PPARD15 (Bitfield-Mask: 0x01)                         */
32416  #define R_PSCU_PPARD_PPARD16_Pos    (16UL)         /*!< PPARD16 (Bit 16)                                      */
32417  #define R_PSCU_PPARD_PPARD16_Msk    (0x10000UL)    /*!< PPARD16 (Bitfield-Mask: 0x01)                         */
32418  #define R_PSCU_PPARD_PPARD20_Pos    (20UL)         /*!< PPARD20 (Bit 20)                                      */
32419  #define R_PSCU_PPARD_PPARD20_Msk    (0x100000UL)   /*!< PPARD20 (Bitfield-Mask: 0x01)                         */
32420  #define R_PSCU_PPARD_PPARD22_Pos    (22UL)         /*!< PPARD22 (Bit 22)                                      */
32421  #define R_PSCU_PPARD_PPARD22_Msk    (0x400000UL)   /*!< PPARD22 (Bitfield-Mask: 0x01)                         */
32422  #define R_PSCU_PPARD_PPARD27_Pos    (27UL)         /*!< PPARD27 (Bit 27)                                      */
32423  #define R_PSCU_PPARD_PPARD27_Msk    (0x8000000UL)  /*!< PPARD27 (Bitfield-Mask: 0x01)                         */
32424  #define R_PSCU_PPARD_PPARD28_Pos    (28UL)         /*!< PPARD28 (Bit 28)                                      */
32425  #define R_PSCU_PPARD_PPARD28_Msk    (0x10000000UL) /*!< PPARD28 (Bitfield-Mask: 0x01)                         */
32426 /* =========================================================  PPARE  ========================================================= */
32427  #define R_PSCU_PPARE_PPARE1_Pos     (1UL)          /*!< PPARE1 (Bit 1)                                        */
32428  #define R_PSCU_PPARE_PPARE1_Msk     (0x2UL)        /*!< PPARE1 (Bitfield-Mask: 0x01)                          */
32429  #define R_PSCU_PPARE_PPARE2_Pos     (2UL)          /*!< PPARE2 (Bit 2)                                        */
32430  #define R_PSCU_PPARE_PPARE2_Msk     (0x4UL)        /*!< PPARE2 (Bitfield-Mask: 0x01)                          */
32431  #define R_PSCU_PPARE_PPARE3_Pos     (3UL)          /*!< PPARE3 (Bit 3)                                        */
32432  #define R_PSCU_PPARE_PPARE3_Msk     (0x8UL)        /*!< PPARE3 (Bitfield-Mask: 0x01)                          */
32433  #define R_PSCU_PPARE_PPARE8_Pos     (8UL)          /*!< PPARE8 (Bit 8)                                        */
32434  #define R_PSCU_PPARE_PPARE8_Msk     (0x100UL)      /*!< PPARE8 (Bitfield-Mask: 0x01)                          */
32435  #define R_PSCU_PPARE_PPARE9_Pos     (9UL)          /*!< PPARE9 (Bit 9)                                        */
32436  #define R_PSCU_PPARE_PPARE9_Msk     (0x200UL)      /*!< PPARE9 (Bitfield-Mask: 0x01)                          */
32437  #define R_PSCU_PPARE_PPARE18_Pos    (18UL)         /*!< PPARE18 (Bit 18)                                      */
32438  #define R_PSCU_PPARE_PPARE18_Msk    (0x40000UL)    /*!< PPARE18 (Bitfield-Mask: 0x01)                         */
32439  #define R_PSCU_PPARE_PPARE19_Pos    (19UL)         /*!< PPARE19 (Bit 19)                                      */
32440  #define R_PSCU_PPARE_PPARE19_Msk    (0x80000UL)    /*!< PPARE19 (Bitfield-Mask: 0x01)                         */
32441  #define R_PSCU_PPARE_PPARE20_Pos    (20UL)         /*!< PPARE20 (Bit 20)                                      */
32442  #define R_PSCU_PPARE_PPARE20_Msk    (0x100000UL)   /*!< PPARE20 (Bitfield-Mask: 0x01)                         */
32443  #define R_PSCU_PPARE_PPARE21_Pos    (21UL)         /*!< PPARE21 (Bit 21)                                      */
32444  #define R_PSCU_PPARE_PPARE21_Msk    (0x200000UL)   /*!< PPARE21 (Bitfield-Mask: 0x01)                         */
32445  #define R_PSCU_PPARE_PPARE22_Pos    (22UL)         /*!< PPARE22 (Bit 22)                                      */
32446  #define R_PSCU_PPARE_PPARE22_Msk    (0x400000UL)   /*!< PPARE22 (Bitfield-Mask: 0x01)                         */
32447  #define R_PSCU_PPARE_PPARE23_Pos    (23UL)         /*!< PPARE23 (Bit 23)                                      */
32448  #define R_PSCU_PPARE_PPARE23_Msk    (0x800000UL)   /*!< PPARE23 (Bitfield-Mask: 0x01)                         */
32449  #define R_PSCU_PPARE_PPARE24_Pos    (24UL)         /*!< PPARE24 (Bit 24)                                      */
32450  #define R_PSCU_PPARE_PPARE24_Msk    (0x1000000UL)  /*!< PPARE24 (Bitfield-Mask: 0x01)                         */
32451  #define R_PSCU_PPARE_PPARE25_Pos    (25UL)         /*!< PPARE25 (Bit 25)                                      */
32452  #define R_PSCU_PPARE_PPARE25_Msk    (0x2000000UL)  /*!< PPARE25 (Bitfield-Mask: 0x01)                         */
32453  #define R_PSCU_PPARE_PPARE26_Pos    (26UL)         /*!< PPARE26 (Bit 26)                                      */
32454  #define R_PSCU_PPARE_PPARE26_Msk    (0x4000000UL)  /*!< PPARE26 (Bitfield-Mask: 0x01)                         */
32455  #define R_PSCU_PPARE_PPARE27_Pos    (27UL)         /*!< PPARE27 (Bit 27)                                      */
32456  #define R_PSCU_PPARE_PPARE27_Msk    (0x8000000UL)  /*!< PPARE27 (Bitfield-Mask: 0x01)                         */
32457  #define R_PSCU_PPARE_PPARE28_Pos    (28UL)         /*!< PPARE28 (Bit 28)                                      */
32458  #define R_PSCU_PPARE_PPARE28_Msk    (0x10000000UL) /*!< PPARE28 (Bitfield-Mask: 0x01)                         */
32459  #define R_PSCU_PPARE_PPARE29_Pos    (29UL)         /*!< PPARE29 (Bit 29)                                      */
32460  #define R_PSCU_PPARE_PPARE29_Msk    (0x20000000UL) /*!< PPARE29 (Bitfield-Mask: 0x01)                         */
32461  #define R_PSCU_PPARE_PPARE30_Pos    (30UL)         /*!< PPARE30 (Bit 30)                                      */
32462  #define R_PSCU_PPARE_PPARE30_Msk    (0x40000000UL) /*!< PPARE30 (Bitfield-Mask: 0x01)                         */
32463  #define R_PSCU_PPARE_PPARE31_Pos    (31UL)         /*!< PPARE31 (Bit 31)                                      */
32464  #define R_PSCU_PPARE_PPARE31_Msk    (0x80000000UL) /*!< PPARE31 (Bitfield-Mask: 0x01)                         */
32465 /* =========================================================  MSPAR  ========================================================= */
32466  #define R_PSCU_MSPAR_MSPAR31_Pos    (31UL)         /*!< MSPAR31 (Bit 31)                                      */
32467  #define R_PSCU_MSPAR_MSPAR31_Msk    (0x80000000UL) /*!< MSPAR31 (Bitfield-Mask: 0x01)                         */
32468 /* =======================================================  CFSAMONA  ======================================================== */
32469  #define R_PSCU_CFSAMONA_CFS2_Pos    (15UL)         /*!< CFS2 (Bit 15)                                         */
32470  #define R_PSCU_CFSAMONA_CFS2_Msk    (0xff8000UL)   /*!< CFS2 (Bitfield-Mask: 0x1ff)                           */
32471 /* ========================================================  DFSAMON  ======================================================== */
32472  #define R_PSCU_DFSAMON_DFS_Pos      (10UL)         /*!< DFS (Bit 10)                                          */
32473  #define R_PSCU_DFSAMON_DFS_Msk      (0xfc00UL)     /*!< DFS (Bitfield-Mask: 0x3f)                             */
32474 /* ========================================================  DLMMON  ========================================================= */
32475  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
32476  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
32477 
32478 /* =========================================================================================================================== */
32479 /* ================                                           R_BUS                                           ================ */
32480 /* =========================================================================================================================== */
32481 
32482 /* ========================================================  CSRECEN  ======================================================== */
32483  #define R_BUS_CSRECEN_RCVENM_Pos        (8UL)       /*!< RCVENM (Bit 8)                                        */
32484  #define R_BUS_CSRECEN_RCVENM_Msk        (0x100UL)   /*!< RCVENM (Bitfield-Mask: 0x01)                          */
32485  #define R_BUS_CSRECEN_RCVEN_Pos         (0UL)       /*!< RCVEN (Bit 0)                                         */
32486  #define R_BUS_CSRECEN_RCVEN_Msk         (0x1UL)     /*!< RCVEN (Bitfield-Mask: 0x01)                           */
32487 /* ========================================================  BUSMABT  ======================================================== */
32488  #define R_BUS_BUSMABT_ARBS_Pos          (0UL)       /*!< ARBS (Bit 0)                                          */
32489  #define R_BUS_BUSMABT_ARBS_Msk          (0x1UL)     /*!< ARBS (Bitfield-Mask: 0x01)                            */
32490 /* =======================================================  BUSDIVBYP  ======================================================= */
32491  #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos    (16UL)      /*!< CPU0SBPE (Bit 16)                                     */
32492  #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk    (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01)                        */
32493  #define R_BUS_BUSDIVBYP_GDSSBPE_Pos     (3UL)       /*!< GDSSBPE (Bit 3)                                       */
32494  #define R_BUS_BUSDIVBYP_GDSSBPE_Msk     (0x8UL)     /*!< GDSSBPE (Bitfield-Mask: 0x01)                         */
32495  #define R_BUS_BUSDIVBYP_EDMABPE_Pos     (0UL)       /*!< EDMABPE (Bit 0)                                       */
32496  #define R_BUS_BUSDIVBYP_EDMABPE_Msk     (0x1UL)     /*!< EDMABPE (Bitfield-Mask: 0x01)                         */
32497 
32498 /* =========================================================================================================================== */
32499 /* ================                                           R_CAC                                           ================ */
32500 /* =========================================================================================================================== */
32501 
32502 /* =========================================================  CACR0  ========================================================= */
32503  #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
32504  #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
32505 /* =========================================================  CACR1  ========================================================= */
32506  #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
32507  #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
32508  #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
32509  #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
32510  #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
32511  #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
32512  #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
32513  #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
32514 /* =========================================================  CACR2  ========================================================= */
32515  #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
32516  #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
32517  #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
32518  #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
32519  #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
32520  #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
32521  #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
32522  #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
32523 /* =========================================================  CAICR  ========================================================= */
32524  #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
32525  #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
32526  #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
32527  #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
32528  #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
32529  #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
32530  #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
32531  #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
32532  #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
32533  #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
32534  #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
32535  #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
32536 /* =========================================================  CASTR  ========================================================= */
32537  #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
32538  #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
32539  #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
32540  #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
32541  #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
32542  #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
32543 /* ========================================================  CAULVR  ========================================================= */
32544  #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
32545  #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
32546 /* ========================================================  CALLVR  ========================================================= */
32547  #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
32548  #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
32549 /* ========================================================  CACNTBR  ======================================================== */
32550  #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
32551  #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
32552 
32553 /* =========================================================================================================================== */
32554 /* ================                                         R_CANFD0                                          ================ */
32555 /* =========================================================================================================================== */
32556 
32557 /* ========================================================  CFDGCFG  ======================================================== */
32558  #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
32559  #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
32560  #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
32561  #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
32562  #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
32563  #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
32564  #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
32565  #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
32566  #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
32567  #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
32568  #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
32569  #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
32570  #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
32571  #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
32572  #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
32573  #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
32574  #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
32575  #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
32576 /* ========================================================  CFDGCTR  ======================================================== */
32577  #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
32578  #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
32579  #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
32580  #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
32581  #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
32582  #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
32583  #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
32584  #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
32585  #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
32586  #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
32587  #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
32588  #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
32589  #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
32590  #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
32591 /* ========================================================  CFDGSTS  ======================================================== */
32592  #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
32593  #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
32594  #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
32595  #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
32596  #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
32597  #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
32598  #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
32599  #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
32600 /* =======================================================  CFDGERFL  ======================================================== */
32601  #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
32602  #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
32603  #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
32604  #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
32605  #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
32606  #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
32607  #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
32608  #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
32609  #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
32610  #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
32611 /* ========================================================  CFDGTSC  ======================================================== */
32612  #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
32613  #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
32614 /* ======================================================  CFDGAFLECTR  ====================================================== */
32615  #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
32616  #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
32617  #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
32618  #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
32619 /* ======================================================  CFDGAFLCFG0  ====================================================== */
32620  #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
32621  #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
32622  #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
32623  #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
32624 /* ========================================================  CFDRMNB  ======================================================== */
32625  #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
32626  #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
32627  #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
32628  #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
32629 /* =======================================================  CFDRMND0  ======================================================== */
32630  #define R_CANFD_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
32631  #define R_CANFD_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
32632 /* =======================================================  CFDRMIEC  ======================================================== */
32633  #define R_CANFD_CFDRMIEC_RMIE_Pos               (0UL)          /*!< RMIE (Bit 0)                                          */
32634  #define R_CANFD_CFDRMIEC_RMIE_Msk               (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff)                      */
32635 /* ========================================================  CFDRFCC  ======================================================== */
32636  #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
32637  #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
32638  #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
32639  #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
32640  #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
32641  #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
32642  #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
32643  #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
32644  #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
32645  #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
32646  #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
32647  #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
32648 /* =======================================================  CFDRFSTS  ======================================================== */
32649  #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
32650  #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
32651  #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
32652  #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
32653  #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
32654  #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
32655  #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
32656  #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
32657  #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
32658  #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
32659 /* =======================================================  CFDRFPCTR  ======================================================= */
32660  #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
32661  #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
32662 /* ========================================================  CFDCFCC  ======================================================== */
32663  #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
32664  #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
32665  #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
32666  #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
32667  #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
32668  #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
32669  #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
32670  #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
32671  #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
32672  #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
32673  #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
32674  #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
32675  #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
32676  #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
32677  #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
32678  #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
32679  #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
32680  #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
32681  #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
32682  #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
32683  #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
32684  #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
32685  #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
32686  #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
32687 /* =======================================================  CFDCFSTS  ======================================================== */
32688  #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
32689  #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
32690  #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
32691  #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
32692  #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
32693  #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
32694  #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
32695  #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
32696  #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
32697  #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
32698  #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
32699  #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
32700 /* =======================================================  CFDCFPCTR  ======================================================= */
32701  #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
32702  #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
32703 /* =======================================================  CFDFESTS  ======================================================== */
32704  #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
32705  #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0x3UL)        /*!< RFXEMP (Bitfield-Mask: 0x03)                          */
32706  #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
32707  #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x100UL)      /*!< CFXEMP (Bitfield-Mask: 0x01)                          */
32708 /* =======================================================  CFDFFSTS  ======================================================== */
32709  #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
32710  #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0x3UL)        /*!< RFXFLL (Bitfield-Mask: 0x03)                          */
32711  #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
32712  #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x100UL)      /*!< CFXFLL (Bitfield-Mask: 0x01)                          */
32713 /* =======================================================  CFDFMSTS  ======================================================== */
32714  #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
32715  #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0x3UL)        /*!< RFXMLT (Bitfield-Mask: 0x03)                          */
32716  #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
32717  #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x100UL)      /*!< CFXMLT (Bitfield-Mask: 0x01)                          */
32718 /* =======================================================  CFDRFISTS  ======================================================= */
32719  #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
32720  #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0x1UL)        /*!< RFXIF (Bitfield-Mask: 0x01)                           */
32721 /* ========================================================  CFDTMC  ========================================================= */
32722  #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
32723  #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
32724  #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
32725  #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
32726  #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
32727  #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
32728 /* =======================================================  CFDTMSTS  ======================================================== */
32729  #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
32730  #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
32731  #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
32732  #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
32733  #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
32734  #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
32735  #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
32736  #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
32737 /* ======================================================  CFDTMTRSTS  ======================================================= */
32738  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
32739  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xfUL)        /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f)                     */
32740 /* ======================================================  CFDTMTARSTS  ====================================================== */
32741  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
32742  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xfUL)        /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f)                    */
32743 /* ======================================================  CFDTMTCSTS  ======================================================= */
32744  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
32745  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xfUL)        /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f)                     */
32746 /* ======================================================  CFDTMTASTS  ======================================================= */
32747  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
32748  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk      (0xfUL)        /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f)                     */
32749 /* =======================================================  CFDTMIEC  ======================================================== */
32750  #define R_CANFD_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
32751  #define R_CANFD_CFDTMIEC_TMIEg_Msk              (0xfUL)        /*!< TMIEg (Bitfield-Mask: 0x0f)                           */
32752 /* =======================================================  CFDTXQCC0  ======================================================= */
32753  #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
32754  #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
32755  #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
32756  #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
32757  #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
32758  #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
32759  #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
32760  #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x300UL)      /*!< TXQDC (Bitfield-Mask: 0x03)                           */
32761 /* ======================================================  CFDTXQSTS0  ======================================================= */
32762  #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
32763  #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
32764  #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
32765  #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
32766  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
32767  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
32768  #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
32769  #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
32770 /* ======================================================  CFDTXQPCTR0  ====================================================== */
32771  #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
32772  #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
32773 /* =======================================================  CFDTHLCC  ======================================================== */
32774  #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
32775  #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
32776  #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
32777  #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
32778  #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
32779  #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
32780  #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
32781  #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
32782 /* =======================================================  CFDTHLSTS  ======================================================= */
32783  #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
32784  #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
32785  #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
32786  #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
32787  #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
32788  #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
32789  #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
32790  #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
32791  #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
32792  #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
32793 /* ======================================================  CFDTHLPCTR  ======================================================= */
32794  #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
32795  #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
32796 /* =====================================================  CFDGTINTSTS0  ====================================================== */
32797  #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
32798  #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
32799  #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
32800  #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
32801  #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
32802  #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
32803  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
32804  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
32805  #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
32806  #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
32807 /* ======================================================  CFDGTSTCFG  ======================================================= */
32808  #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
32809  #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
32810 /* ======================================================  CFDGTSTCTR  ======================================================= */
32811  #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
32812  #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
32813 /* =======================================================  CFDGFDCFG  ======================================================= */
32814  #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
32815  #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
32816  #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
32817  #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
32818 /* =======================================================  CFDGLOCKK  ======================================================= */
32819  #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
32820  #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
32821 /* =====================================================  CFDGAFLIGNENT  ===================================================== */
32822  #define R_CANFD_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
32823  #define R_CANFD_CFDGAFLIGNENT_IRN_Msk           (0x1fUL)       /*!< IRN (Bitfield-Mask: 0x1f)                             */
32824 /* =====================================================  CFDGAFLIGNCTR  ===================================================== */
32825  #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
32826  #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
32827  #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
32828  #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
32829 /* =======================================================  CFDCDTCT  ======================================================== */
32830  #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
32831  #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
32832  #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
32833  #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
32834  #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
32835  #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
32836 /* =======================================================  CFDCDTSTS  ======================================================= */
32837  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
32838  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
32839  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
32840  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
32841  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
32842  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
32843 /* =======================================================  CFDGRSTC  ======================================================== */
32844  #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
32845  #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
32846  #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
32847  #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
32848 /* =======================================================  CFDRPGACC  ======================================================= */
32849  #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
32850  #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
32851 
32852 /* =========================================================================================================================== */
32853 /* ================                                           R_CRC                                           ================ */
32854 /* =========================================================================================================================== */
32855 
32856 /* ========================================================  CRCCR0  ========================================================= */
32857  #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
32858  #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
32859  #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
32860  #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
32861  #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
32862  #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
32863 /* ========================================================  CRCCR1  ========================================================= */
32864  #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
32865  #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
32866  #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
32867  #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
32868 /* ========================================================  CRCDIR  ========================================================= */
32869  #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
32870  #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
32871 /* =======================================================  CRCDIR_BY  ======================================================= */
32872  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
32873  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
32874 /* ========================================================  CRCDOR  ========================================================= */
32875  #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
32876  #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
32877 /* =======================================================  CRCDOR_HA  ======================================================= */
32878  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
32879  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
32880 /* =======================================================  CRCDOR_BY  ======================================================= */
32881  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
32882  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
32883 /* ========================================================  CRCSAR  ========================================================= */
32884  #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
32885  #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
32886 
32887 /* =========================================================================================================================== */
32888 /* ================                                           R_DAC                                           ================ */
32889 /* =========================================================================================================================== */
32890 
32891 /* =========================================================  DACR  ========================================================== */
32892  #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
32893  #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
32894  #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
32895  #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
32896 /* =========================================================  DADR  ========================================================== */
32897  #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
32898  #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
32899 /* =========================================================  DADPR  ========================================================= */
32900  #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
32901  #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
32902 /* ========================================================  DAADSCR  ======================================================== */
32903  #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
32904  #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
32905 /* =======================================================  DAVREFCR  ======================================================== */
32906  #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
32907  #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
32908 /* =========================================================  DAPC  ========================================================== */
32909  #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
32910  #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
32911 /* ========================================================  DAAMPCR  ======================================================== */
32912  #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
32913  #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
32914 /* ========================================================  DAASWCR  ======================================================== */
32915  #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
32916  #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
32917  #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
32918  #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
32919 /* ========================================================  DAADUSR  ======================================================== */
32920  #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
32921  #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
32922  #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
32923  #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
32924 
32925 /* =========================================================================================================================== */
32926 /* ================                                          R_DEBUG                                          ================ */
32927 /* =========================================================================================================================== */
32928 
32929 /* ========================================================  DBGSTR  ========================================================= */
32930  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
32931  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
32932  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
32933  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
32934 /* =======================================================  DBGSTOPCR  ======================================================= */
32935  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
32936  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
32937  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos      (14UL)         /*!< DBGSTOP_TIM (Bit 14)                                  */
32938  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk      (0x4000UL)     /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01)                     */
32939  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos      (15UL)         /*!< DBGSTOP_SIR (Bit 15)                                  */
32940  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk      (0x8000UL)     /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01)                     */
32941  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
32942  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
32943  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
32944  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
32945  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
32946  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
32947  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
32948  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
32949  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
32950  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
32951 /* =======================================================  FSBLSTAT  ======================================================== */
32952  #define R_DEBUG_FSBLSTAT_CS_Pos                (0UL)          /*!< CS (Bit 0)                                            */
32953  #define R_DEBUG_FSBLSTAT_CS_Msk                (0x1UL)        /*!< CS (Bitfield-Mask: 0x01)                              */
32954  #define R_DEBUG_FSBLSTAT_RS_Pos                (1UL)          /*!< RS (Bit 1)                                            */
32955  #define R_DEBUG_FSBLSTAT_RS_Msk                (0x2UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
32956  #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos           (8UL)          /*!< FSBLCLK (Bit 8)                                       */
32957  #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk           (0x700UL)      /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */
32958 
32959 /* =========================================================================================================================== */
32960 /* ================                                           R_DMA                                           ================ */
32961 /* =========================================================================================================================== */
32962 
32963 /* =========================================================  DMAST  ========================================================= */
32964  #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
32965  #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
32966 /* ========================================================  DMECHR  ========================================================= */
32967  #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
32968  #define R_DMA_DMECHR_DMECH_Msk       (0x7UL)     /*!< DMECH (Bitfield-Mask: 0x07)                           */
32969  #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
32970  #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
32971  #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
32972  #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
32973 /* =========================================================  DELSR  ========================================================= */
32974  #define R_DMA_DELSR_IR_Pos           (16UL)      /*!< IR (Bit 16)                                           */
32975  #define R_DMA_DELSR_IR_Msk           (0x10000UL) /*!< IR (Bitfield-Mask: 0x01)                              */
32976  #define R_DMA_DELSR_DELS_Pos         (0UL)       /*!< DELS (Bit 0)                                          */
32977  #define R_DMA_DELSR_DELS_Msk         (0x1ffUL)   /*!< DELS (Bitfield-Mask: 0x1ff)                           */
32978 
32979 /* =========================================================================================================================== */
32980 /* ================                                          R_DMAC0                                          ================ */
32981 /* =========================================================================================================================== */
32982 
32983 /* =========================================================  DMSAR  ========================================================= */
32984  #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
32985  #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
32986 /* =========================================================  DMDAR  ========================================================= */
32987  #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
32988  #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
32989 /* =========================================================  DMCRA  ========================================================= */
32990  #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
32991  #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
32992  #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
32993  #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
32994 /* =========================================================  DMCRB  ========================================================= */
32995  #define R_DMAC0_DMCRB_DMCRBL_Pos    (0UL)          /*!< DMCRBL (Bit 0)                                        */
32996  #define R_DMAC0_DMCRB_DMCRBL_Msk    (0xffffUL)     /*!< DMCRBL (Bitfield-Mask: 0xffff)                        */
32997  #define R_DMAC0_DMCRB_DMCRBH_Pos    (16UL)         /*!< DMCRBH (Bit 16)                                       */
32998  #define R_DMAC0_DMCRB_DMCRBH_Msk    (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff)                        */
32999 /* =========================================================  DMTMD  ========================================================= */
33000  #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
33001  #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
33002  #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
33003  #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
33004  #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
33005  #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
33006  #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
33007  #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
33008  #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
33009  #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
33010 /* =========================================================  DMINT  ========================================================= */
33011  #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
33012  #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
33013  #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
33014  #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
33015  #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
33016  #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
33017  #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
33018  #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
33019  #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
33020  #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
33021 /* =========================================================  DMAMD  ========================================================= */
33022  #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
33023  #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
33024  #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
33025  #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
33026  #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
33027  #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
33028  #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
33029  #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
33030  #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
33031  #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
33032  #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
33033  #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
33034 /* =========================================================  DMOFR  ========================================================= */
33035  #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
33036  #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
33037 /* =========================================================  DMCNT  ========================================================= */
33038  #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
33039  #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
33040 /* =========================================================  DMREQ  ========================================================= */
33041  #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
33042  #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
33043  #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
33044  #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
33045 /* =========================================================  DMSTS  ========================================================= */
33046  #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
33047  #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
33048  #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
33049  #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
33050  #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
33051  #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
33052 /* =========================================================  DMSRR  ========================================================= */
33053 /* =========================================================  DMDRR  ========================================================= */
33054 /* =========================================================  DMSBS  ========================================================= */
33055  #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
33056  #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
33057  #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
33058  #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
33059 /* =========================================================  DMDBS  ========================================================= */
33060  #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
33061  #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
33062  #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
33063  #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
33064 /* =========================================================  DMBWR  ========================================================= */
33065  #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
33066  #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */
33067 
33068 /* =========================================================================================================================== */
33069 /* ================                                           R_DOC                                           ================ */
33070 /* =========================================================================================================================== */
33071 
33072 /* =========================================================  DOCR  ========================================================== */
33073  #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
33074  #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
33075  #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
33076  #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
33077  #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
33078  #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
33079  #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
33080  #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
33081 /* =========================================================  DODIR  ========================================================= */
33082  #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
33083  #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
33084 /* =========================================================  DODSR  ========================================================= */
33085  #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
33086  #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
33087 
33088 /* =========================================================================================================================== */
33089 /* ================                                           R_DRW                                           ================ */
33090 /* =========================================================================================================================== */
33091 
33092 /* ========================================================  CONTROL  ======================================================== */
33093  #define R_DRW_CONTROL_SPANSTORE_Pos           (23UL)         /*!< SPANSTORE (Bit 23)                                    */
33094  #define R_DRW_CONTROL_SPANSTORE_Msk           (0x800000UL)   /*!< SPANSTORE (Bitfield-Mask: 0x01)                       */
33095  #define R_DRW_CONTROL_SPANABORT_Pos           (22UL)         /*!< SPANABORT (Bit 22)                                    */
33096  #define R_DRW_CONTROL_SPANABORT_Msk           (0x400000UL)   /*!< SPANABORT (Bitfield-Mask: 0x01)                       */
33097  #define R_DRW_CONTROL_UNIONCD_Pos             (21UL)         /*!< UNIONCD (Bit 21)                                      */
33098  #define R_DRW_CONTROL_UNIONCD_Msk             (0x200000UL)   /*!< UNIONCD (Bitfield-Mask: 0x01)                         */
33099  #define R_DRW_CONTROL_UNIONAB_Pos             (20UL)         /*!< UNIONAB (Bit 20)                                      */
33100  #define R_DRW_CONTROL_UNIONAB_Msk             (0x100000UL)   /*!< UNIONAB (Bitfield-Mask: 0x01)                         */
33101  #define R_DRW_CONTROL_UNION56_Pos             (19UL)         /*!< UNION56 (Bit 19)                                      */
33102  #define R_DRW_CONTROL_UNION56_Msk             (0x80000UL)    /*!< UNION56 (Bitfield-Mask: 0x01)                         */
33103  #define R_DRW_CONTROL_UNION34_Pos             (18UL)         /*!< UNION34 (Bit 18)                                      */
33104  #define R_DRW_CONTROL_UNION34_Msk             (0x40000UL)    /*!< UNION34 (Bitfield-Mask: 0x01)                         */
33105  #define R_DRW_CONTROL_UNION12_Pos             (17UL)         /*!< UNION12 (Bit 17)                                      */
33106  #define R_DRW_CONTROL_UNION12_Msk             (0x20000UL)    /*!< UNION12 (Bitfield-Mask: 0x01)                         */
33107  #define R_DRW_CONTROL_BAND2ENABLE_Pos         (16UL)         /*!< BAND2ENABLE (Bit 16)                                  */
33108  #define R_DRW_CONTROL_BAND2ENABLE_Msk         (0x10000UL)    /*!< BAND2ENABLE (Bitfield-Mask: 0x01)                     */
33109  #define R_DRW_CONTROL_BAND1ENABLE_Pos         (15UL)         /*!< BAND1ENABLE (Bit 15)                                  */
33110  #define R_DRW_CONTROL_BAND1ENABLE_Msk         (0x8000UL)     /*!< BAND1ENABLE (Bitfield-Mask: 0x01)                     */
33111  #define R_DRW_CONTROL_LIM6THRESHOLD_Pos       (14UL)         /*!< LIM6THRESHOLD (Bit 14)                                */
33112  #define R_DRW_CONTROL_LIM6THRESHOLD_Msk       (0x4000UL)     /*!< LIM6THRESHOLD (Bitfield-Mask: 0x01)                   */
33113  #define R_DRW_CONTROL_LIM5THRESHOLD_Pos       (13UL)         /*!< LIM5THRESHOLD (Bit 13)                                */
33114  #define R_DRW_CONTROL_LIM5THRESHOLD_Msk       (0x2000UL)     /*!< LIM5THRESHOLD (Bitfield-Mask: 0x01)                   */
33115  #define R_DRW_CONTROL_LIM4THRESHOLD_Pos       (12UL)         /*!< LIM4THRESHOLD (Bit 12)                                */
33116  #define R_DRW_CONTROL_LIM4THRESHOLD_Msk       (0x1000UL)     /*!< LIM4THRESHOLD (Bitfield-Mask: 0x01)                   */
33117  #define R_DRW_CONTROL_LIM3THRESHOLD_Pos       (11UL)         /*!< LIM3THRESHOLD (Bit 11)                                */
33118  #define R_DRW_CONTROL_LIM3THRESHOLD_Msk       (0x800UL)      /*!< LIM3THRESHOLD (Bitfield-Mask: 0x01)                   */
33119  #define R_DRW_CONTROL_LIM2THRESHOLD_Pos       (10UL)         /*!< LIM2THRESHOLD (Bit 10)                                */
33120  #define R_DRW_CONTROL_LIM2THRESHOLD_Msk       (0x400UL)      /*!< LIM2THRESHOLD (Bitfield-Mask: 0x01)                   */
33121  #define R_DRW_CONTROL_LIM1THRESHOLD_Pos       (9UL)          /*!< LIM1THRESHOLD (Bit 9)                                 */
33122  #define R_DRW_CONTROL_LIM1THRESHOLD_Msk       (0x200UL)      /*!< LIM1THRESHOLD (Bitfield-Mask: 0x01)                   */
33123  #define R_DRW_CONTROL_QUAD3ENABLE_Pos         (8UL)          /*!< QUAD3ENABLE (Bit 8)                                   */
33124  #define R_DRW_CONTROL_QUAD3ENABLE_Msk         (0x100UL)      /*!< QUAD3ENABLE (Bitfield-Mask: 0x01)                     */
33125  #define R_DRW_CONTROL_QUAD2ENABLE_Pos         (7UL)          /*!< QUAD2ENABLE (Bit 7)                                   */
33126  #define R_DRW_CONTROL_QUAD2ENABLE_Msk         (0x80UL)       /*!< QUAD2ENABLE (Bitfield-Mask: 0x01)                     */
33127  #define R_DRW_CONTROL_QUAD1ENABLE_Pos         (6UL)          /*!< QUAD1ENABLE (Bit 6)                                   */
33128  #define R_DRW_CONTROL_QUAD1ENABLE_Msk         (0x40UL)       /*!< QUAD1ENABLE (Bitfield-Mask: 0x01)                     */
33129  #define R_DRW_CONTROL_LIM6ENABLE_Pos          (5UL)          /*!< LIM6ENABLE (Bit 5)                                    */
33130  #define R_DRW_CONTROL_LIM6ENABLE_Msk          (0x20UL)       /*!< LIM6ENABLE (Bitfield-Mask: 0x01)                      */
33131  #define R_DRW_CONTROL_LIM5ENABLE_Pos          (4UL)          /*!< LIM5ENABLE (Bit 4)                                    */
33132  #define R_DRW_CONTROL_LIM5ENABLE_Msk          (0x10UL)       /*!< LIM5ENABLE (Bitfield-Mask: 0x01)                      */
33133  #define R_DRW_CONTROL_LIM4ENABLE_Pos          (3UL)          /*!< LIM4ENABLE (Bit 3)                                    */
33134  #define R_DRW_CONTROL_LIM4ENABLE_Msk          (0x8UL)        /*!< LIM4ENABLE (Bitfield-Mask: 0x01)                      */
33135  #define R_DRW_CONTROL_LIM3ENABLE_Pos          (2UL)          /*!< LIM3ENABLE (Bit 2)                                    */
33136  #define R_DRW_CONTROL_LIM3ENABLE_Msk          (0x4UL)        /*!< LIM3ENABLE (Bitfield-Mask: 0x01)                      */
33137  #define R_DRW_CONTROL_LIM2ENABLE_Pos          (1UL)          /*!< LIM2ENABLE (Bit 1)                                    */
33138  #define R_DRW_CONTROL_LIM2ENABLE_Msk          (0x2UL)        /*!< LIM2ENABLE (Bitfield-Mask: 0x01)                      */
33139  #define R_DRW_CONTROL_LIM1ENABLE_Pos          (0UL)          /*!< LIM1ENABLE (Bit 0)                                    */
33140  #define R_DRW_CONTROL_LIM1ENABLE_Msk          (0x1UL)        /*!< LIM1ENABLE (Bitfield-Mask: 0x01)                      */
33141 /* =======================================================  CONTROL2  ======================================================== */
33142  #define R_DRW_CONTROL2_RLEPIXELWIDTH_Pos      (30UL)         /*!< RLEPIXELWIDTH (Bit 30)                                */
33143  #define R_DRW_CONTROL2_RLEPIXELWIDTH_Msk      (0xc0000000UL) /*!< RLEPIXELWIDTH (Bitfield-Mask: 0x03)                   */
33144  #define R_DRW_CONTROL2_BDIA_Pos               (29UL)         /*!< BDIA (Bit 29)                                         */
33145  #define R_DRW_CONTROL2_BDIA_Msk               (0x20000000UL) /*!< BDIA (Bitfield-Mask: 0x01)                            */
33146  #define R_DRW_CONTROL2_BSIA_Pos               (28UL)         /*!< BSIA (Bit 28)                                         */
33147  #define R_DRW_CONTROL2_BSIA_Msk               (0x10000000UL) /*!< BSIA (Bitfield-Mask: 0x01)                            */
33148  #define R_DRW_CONTROL2_CLUTFORMAT_Pos         (27UL)         /*!< CLUTFORMAT (Bit 27)                                   */
33149  #define R_DRW_CONTROL2_CLUTFORMAT_Msk         (0x8000000UL)  /*!< CLUTFORMAT (Bitfield-Mask: 0x01)                      */
33150  #define R_DRW_CONTROL2_COLKEYENABLE_Pos       (26UL)         /*!< COLKEYENABLE (Bit 26)                                 */
33151  #define R_DRW_CONTROL2_COLKEYENABLE_Msk       (0x4000000UL)  /*!< COLKEYENABLE (Bitfield-Mask: 0x01)                    */
33152  #define R_DRW_CONTROL2_CLUTENABLE_Pos         (25UL)         /*!< CLUTENABLE (Bit 25)                                   */
33153  #define R_DRW_CONTROL2_CLUTENABLE_Msk         (0x2000000UL)  /*!< CLUTENABLE (Bitfield-Mask: 0x01)                      */
33154  #define R_DRW_CONTROL2_RLEENABLE_Pos          (24UL)         /*!< RLEENABLE (Bit 24)                                    */
33155  #define R_DRW_CONTROL2_RLEENABLE_Msk          (0x1000000UL)  /*!< RLEENABLE (Bitfield-Mask: 0x01)                       */
33156  #define R_DRW_CONTROL2_WRITEALPHA_Pos         (22UL)         /*!< WRITEALPHA (Bit 22)                                   */
33157  #define R_DRW_CONTROL2_WRITEALPHA_Msk         (0xc00000UL)   /*!< WRITEALPHA (Bitfield-Mask: 0x03)                      */
33158  #define R_DRW_CONTROL2_WRITEFORMAT10_Pos      (20UL)         /*!< WRITEFORMAT10 (Bit 20)                                */
33159  #define R_DRW_CONTROL2_WRITEFORMAT10_Msk      (0x300000UL)   /*!< WRITEFORMAT10 (Bitfield-Mask: 0x03)                   */
33160  #define R_DRW_CONTROL2_READFORMAT10_Pos       (18UL)         /*!< READFORMAT10 (Bit 18)                                 */
33161  #define R_DRW_CONTROL2_READFORMAT10_Msk       (0xc0000UL)    /*!< READFORMAT10 (Bitfield-Mask: 0x03)                    */
33162  #define R_DRW_CONTROL2_TEXTUREFILTERY_Pos     (17UL)         /*!< TEXTUREFILTERY (Bit 17)                               */
33163  #define R_DRW_CONTROL2_TEXTUREFILTERY_Msk     (0x20000UL)    /*!< TEXTUREFILTERY (Bitfield-Mask: 0x01)                  */
33164  #define R_DRW_CONTROL2_TEXTUREFILTERX_Pos     (16UL)         /*!< TEXTUREFILTERX (Bit 16)                               */
33165  #define R_DRW_CONTROL2_TEXTUREFILTERX_Msk     (0x10000UL)    /*!< TEXTUREFILTERX (Bitfield-Mask: 0x01)                  */
33166  #define R_DRW_CONTROL2_TEXTURECLAMPY_Pos      (15UL)         /*!< TEXTURECLAMPY (Bit 15)                                */
33167  #define R_DRW_CONTROL2_TEXTURECLAMPY_Msk      (0x8000UL)     /*!< TEXTURECLAMPY (Bitfield-Mask: 0x01)                   */
33168  #define R_DRW_CONTROL2_TEXTURECLAMPX_Pos      (14UL)         /*!< TEXTURECLAMPX (Bit 14)                                */
33169  #define R_DRW_CONTROL2_TEXTURECLAMPX_Msk      (0x4000UL)     /*!< TEXTURECLAMPX (Bitfield-Mask: 0x01)                   */
33170  #define R_DRW_CONTROL2_BC2_Pos                (13UL)         /*!< BC2 (Bit 13)                                          */
33171  #define R_DRW_CONTROL2_BC2_Msk                (0x2000UL)     /*!< BC2 (Bitfield-Mask: 0x01)                             */
33172  #define R_DRW_CONTROL2_BDI_Pos                (12UL)         /*!< BDI (Bit 12)                                          */
33173  #define R_DRW_CONTROL2_BDI_Msk                (0x1000UL)     /*!< BDI (Bitfield-Mask: 0x01)                             */
33174  #define R_DRW_CONTROL2_BSI_Pos                (11UL)         /*!< BSI (Bit 11)                                          */
33175  #define R_DRW_CONTROL2_BSI_Msk                (0x800UL)      /*!< BSI (Bitfield-Mask: 0x01)                             */
33176  #define R_DRW_CONTROL2_BDF_Pos                (10UL)         /*!< BDF (Bit 10)                                          */
33177  #define R_DRW_CONTROL2_BDF_Msk                (0x400UL)      /*!< BDF (Bitfield-Mask: 0x01)                             */
33178  #define R_DRW_CONTROL2_BSF_Pos                (9UL)          /*!< BSF (Bit 9)                                           */
33179  #define R_DRW_CONTROL2_BSF_Msk                (0x200UL)      /*!< BSF (Bitfield-Mask: 0x01)                             */
33180  #define R_DRW_CONTROL2_WRITEFORMAT2_Pos       (8UL)          /*!< WRITEFORMAT2 (Bit 8)                                  */
33181  #define R_DRW_CONTROL2_WRITEFORMAT2_Msk       (0x100UL)      /*!< WRITEFORMAT2 (Bitfield-Mask: 0x01)                    */
33182  #define R_DRW_CONTROL2_BDFA_Pos               (7UL)          /*!< BDFA (Bit 7)                                          */
33183  #define R_DRW_CONTROL2_BDFA_Msk               (0x80UL)       /*!< BDFA (Bitfield-Mask: 0x01)                            */
33184  #define R_DRW_CONTROL2_BSFA_Pos               (6UL)          /*!< BSFA (Bit 6)                                          */
33185  #define R_DRW_CONTROL2_BSFA_Msk               (0x40UL)       /*!< BSFA (Bitfield-Mask: 0x01)                            */
33186  #define R_DRW_CONTROL2_READFORMAT32_Pos       (4UL)          /*!< READFORMAT32 (Bit 4)                                  */
33187  #define R_DRW_CONTROL2_READFORMAT32_Msk       (0x30UL)       /*!< READFORMAT32 (Bitfield-Mask: 0x03)                    */
33188  #define R_DRW_CONTROL2_USEACB_Pos             (3UL)          /*!< USEACB (Bit 3)                                        */
33189  #define R_DRW_CONTROL2_USEACB_Msk             (0x8UL)        /*!< USEACB (Bitfield-Mask: 0x01)                          */
33190  #define R_DRW_CONTROL2_PATTERNSOURCEL5_Pos    (2UL)          /*!< PATTERNSOURCEL5 (Bit 2)                               */
33191  #define R_DRW_CONTROL2_PATTERNSOURCEL5_Msk    (0x4UL)        /*!< PATTERNSOURCEL5 (Bitfield-Mask: 0x01)                 */
33192  #define R_DRW_CONTROL2_TEXTUREENABLE_Pos      (1UL)          /*!< TEXTUREENABLE (Bit 1)                                 */
33193  #define R_DRW_CONTROL2_TEXTUREENABLE_Msk      (0x2UL)        /*!< TEXTUREENABLE (Bitfield-Mask: 0x01)                   */
33194  #define R_DRW_CONTROL2_PATTERNENABLE_Pos      (0UL)          /*!< PATTERNENABLE (Bit 0)                                 */
33195  #define R_DRW_CONTROL2_PATTERNENABLE_Msk      (0x1UL)        /*!< PATTERNENABLE (Bitfield-Mask: 0x01)                   */
33196 /* ========================================================  IRQCTL  ========================================================= */
33197  #define R_DRW_IRQCTL_BUSIRQCLR_Pos            (5UL)          /*!< BUSIRQCLR (Bit 5)                                     */
33198  #define R_DRW_IRQCTL_BUSIRQCLR_Msk            (0x20UL)       /*!< BUSIRQCLR (Bitfield-Mask: 0x01)                       */
33199  #define R_DRW_IRQCTL_BUSIRQEN_Pos             (4UL)          /*!< BUSIRQEN (Bit 4)                                      */
33200  #define R_DRW_IRQCTL_BUSIRQEN_Msk             (0x10UL)       /*!< BUSIRQEN (Bitfield-Mask: 0x01)                        */
33201  #define R_DRW_IRQCTL_DLISTIRQCLR_Pos          (3UL)          /*!< DLISTIRQCLR (Bit 3)                                   */
33202  #define R_DRW_IRQCTL_DLISTIRQCLR_Msk          (0x8UL)        /*!< DLISTIRQCLR (Bitfield-Mask: 0x01)                     */
33203  #define R_DRW_IRQCTL_ENUMIRQCLR_Pos           (2UL)          /*!< ENUMIRQCLR (Bit 2)                                    */
33204  #define R_DRW_IRQCTL_ENUMIRQCLR_Msk           (0x4UL)        /*!< ENUMIRQCLR (Bitfield-Mask: 0x01)                      */
33205  #define R_DRW_IRQCTL_DLISTIRQEN_Pos           (1UL)          /*!< DLISTIRQEN (Bit 1)                                    */
33206  #define R_DRW_IRQCTL_DLISTIRQEN_Msk           (0x2UL)        /*!< DLISTIRQEN (Bitfield-Mask: 0x01)                      */
33207  #define R_DRW_IRQCTL_ENUMIRQEN_Pos            (0UL)          /*!< ENUMIRQEN (Bit 0)                                     */
33208  #define R_DRW_IRQCTL_ENUMIRQEN_Msk            (0x1UL)        /*!< ENUMIRQEN (Bitfield-Mask: 0x01)                       */
33209 /* =======================================================  CACHECTL  ======================================================== */
33210  #define R_DRW_CACHECTL_CFLUSHTX_Pos           (3UL)          /*!< CFLUSHTX (Bit 3)                                      */
33211  #define R_DRW_CACHECTL_CFLUSHTX_Msk           (0x8UL)        /*!< CFLUSHTX (Bitfield-Mask: 0x01)                        */
33212  #define R_DRW_CACHECTL_CENABLETX_Pos          (2UL)          /*!< CENABLETX (Bit 2)                                     */
33213  #define R_DRW_CACHECTL_CENABLETX_Msk          (0x4UL)        /*!< CENABLETX (Bitfield-Mask: 0x01)                       */
33214  #define R_DRW_CACHECTL_CFLUSHFX_Pos           (1UL)          /*!< CFLUSHFX (Bit 1)                                      */
33215  #define R_DRW_CACHECTL_CFLUSHFX_Msk           (0x2UL)        /*!< CFLUSHFX (Bitfield-Mask: 0x01)                        */
33216  #define R_DRW_CACHECTL_CENABLEFX_Pos          (0UL)          /*!< CENABLEFX (Bit 0)                                     */
33217  #define R_DRW_CACHECTL_CENABLEFX_Msk          (0x1UL)        /*!< CENABLEFX (Bitfield-Mask: 0x01)                       */
33218 /* ========================================================  STATUS  ========================================================= */
33219  #define R_DRW_STATUS_BUSERRMDL_Pos            (10UL)         /*!< BUSERRMDL (Bit 10)                                    */
33220  #define R_DRW_STATUS_BUSERRMDL_Msk            (0x400UL)      /*!< BUSERRMDL (Bitfield-Mask: 0x01)                       */
33221  #define R_DRW_STATUS_BUSERRMTXMRL_Pos         (9UL)          /*!< BUSERRMTXMRL (Bit 9)                                  */
33222  #define R_DRW_STATUS_BUSERRMTXMRL_Msk         (0x200UL)      /*!< BUSERRMTXMRL (Bitfield-Mask: 0x01)                    */
33223  #define R_DRW_STATUS_BUSERRMFB_Pos            (8UL)          /*!< BUSERRMFB (Bit 8)                                     */
33224  #define R_DRW_STATUS_BUSERRMFB_Msk            (0x100UL)      /*!< BUSERRMFB (Bitfield-Mask: 0x01)                       */
33225  #define R_DRW_STATUS_BUSIRQ_Pos               (6UL)          /*!< BUSIRQ (Bit 6)                                        */
33226  #define R_DRW_STATUS_BUSIRQ_Msk               (0x40UL)       /*!< BUSIRQ (Bitfield-Mask: 0x01)                          */
33227  #define R_DRW_STATUS_DLISTIRQ_Pos             (5UL)          /*!< DLISTIRQ (Bit 5)                                      */
33228  #define R_DRW_STATUS_DLISTIRQ_Msk             (0x20UL)       /*!< DLISTIRQ (Bitfield-Mask: 0x01)                        */
33229  #define R_DRW_STATUS_ENUMIRQ_Pos              (4UL)          /*!< ENUMIRQ (Bit 4)                                       */
33230  #define R_DRW_STATUS_ENUMIRQ_Msk              (0x10UL)       /*!< ENUMIRQ (Bitfield-Mask: 0x01)                         */
33231  #define R_DRW_STATUS_DLISTACTIVE_Pos          (3UL)          /*!< DLISTACTIVE (Bit 3)                                   */
33232  #define R_DRW_STATUS_DLISTACTIVE_Msk          (0x8UL)        /*!< DLISTACTIVE (Bitfield-Mask: 0x01)                     */
33233  #define R_DRW_STATUS_CACHEDIRTY_Pos           (2UL)          /*!< CACHEDIRTY (Bit 2)                                    */
33234  #define R_DRW_STATUS_CACHEDIRTY_Msk           (0x4UL)        /*!< CACHEDIRTY (Bitfield-Mask: 0x01)                      */
33235  #define R_DRW_STATUS_BUSYWRITE_Pos            (1UL)          /*!< BUSYWRITE (Bit 1)                                     */
33236  #define R_DRW_STATUS_BUSYWRITE_Msk            (0x2UL)        /*!< BUSYWRITE (Bitfield-Mask: 0x01)                       */
33237  #define R_DRW_STATUS_BUSYENUM_Pos             (0UL)          /*!< BUSYENUM (Bit 0)                                      */
33238  #define R_DRW_STATUS_BUSYENUM_Msk             (0x1UL)        /*!< BUSYENUM (Bitfield-Mask: 0x01)                        */
33239 /* ======================================================  HWREVISION  ======================================================= */
33240  #define R_DRW_HWREVISION_ACBLEND_Pos          (27UL)         /*!< ACBLEND (Bit 27)                                      */
33241  #define R_DRW_HWREVISION_ACBLEND_Msk          (0x8000000UL)  /*!< ACBLEND (Bitfield-Mask: 0x01)                         */
33242  #define R_DRW_HWREVISION_COLORKEY_Pos         (25UL)         /*!< COLORKEY (Bit 25)                                     */
33243  #define R_DRW_HWREVISION_COLORKEY_Msk         (0x2000000UL)  /*!< COLORKEY (Bitfield-Mask: 0x01)                        */
33244  #define R_DRW_HWREVISION_TEXCLUT256_Pos       (24UL)         /*!< TEXCLUT256 (Bit 24)                                   */
33245  #define R_DRW_HWREVISION_TEXCLUT256_Msk       (0x1000000UL)  /*!< TEXCLUT256 (Bitfield-Mask: 0x01)                      */
33246  #define R_DRW_HWREVISION_RLEUNIT_Pos          (23UL)         /*!< RLEUNIT (Bit 23)                                      */
33247  #define R_DRW_HWREVISION_RLEUNIT_Msk          (0x800000UL)   /*!< RLEUNIT (Bitfield-Mask: 0x01)                         */
33248  #define R_DRW_HWREVISION_TEXCLU_Pos           (21UL)         /*!< TEXCLU (Bit 21)                                       */
33249  #define R_DRW_HWREVISION_TEXCLU_Msk           (0x200000UL)   /*!< TEXCLU (Bitfield-Mask: 0x01)                          */
33250  #define R_DRW_HWREVISION_PERFCOUNT_Pos        (20UL)         /*!< PERFCOUNT (Bit 20)                                    */
33251  #define R_DRW_HWREVISION_PERFCOUNT_Msk        (0x100000UL)   /*!< PERFCOUNT (Bitfield-Mask: 0x01)                       */
33252  #define R_DRW_HWREVISION_TXCACHE_Pos          (19UL)         /*!< TXCACHE (Bit 19)                                      */
33253  #define R_DRW_HWREVISION_TXCACHE_Msk          (0x80000UL)    /*!< TXCACHE (Bitfield-Mask: 0x01)                         */
33254  #define R_DRW_HWREVISION_FBCACHE_Pos          (18UL)         /*!< FBCACHE (Bit 18)                                      */
33255  #define R_DRW_HWREVISION_FBCACHE_Msk          (0x40000UL)    /*!< FBCACHE (Bitfield-Mask: 0x01)                         */
33256  #define R_DRW_HWREVISION_DLR_Pos              (17UL)         /*!< DLR (Bit 17)                                          */
33257  #define R_DRW_HWREVISION_DLR_Msk              (0x20000UL)    /*!< DLR (Bitfield-Mask: 0x01)                             */
33258  #define R_DRW_HWREVISION_REV_Pos              (0UL)          /*!< REV (Bit 0)                                           */
33259  #define R_DRW_HWREVISION_REV_Msk              (0xfffUL)      /*!< REV (Bitfield-Mask: 0xfff)                            */
33260 /* ========================================================  COLOR1  ========================================================= */
33261  #define R_DRW_COLOR1_COLOR1A_Pos              (24UL)         /*!< COLOR1A (Bit 24)                                      */
33262  #define R_DRW_COLOR1_COLOR1A_Msk              (0xff000000UL) /*!< COLOR1A (Bitfield-Mask: 0xff)                         */
33263  #define R_DRW_COLOR1_COLOR1R_Pos              (16UL)         /*!< COLOR1R (Bit 16)                                      */
33264  #define R_DRW_COLOR1_COLOR1R_Msk              (0xff0000UL)   /*!< COLOR1R (Bitfield-Mask: 0xff)                         */
33265  #define R_DRW_COLOR1_COLOR1G_Pos              (8UL)          /*!< COLOR1G (Bit 8)                                       */
33266  #define R_DRW_COLOR1_COLOR1G_Msk              (0xff00UL)     /*!< COLOR1G (Bitfield-Mask: 0xff)                         */
33267  #define R_DRW_COLOR1_COLOR1B_Pos              (0UL)          /*!< COLOR1B (Bit 0)                                       */
33268  #define R_DRW_COLOR1_COLOR1B_Msk              (0xffUL)       /*!< COLOR1B (Bitfield-Mask: 0xff)                         */
33269 /* ========================================================  COLOR2  ========================================================= */
33270  #define R_DRW_COLOR2_COLOR2A_Pos              (24UL)         /*!< COLOR2A (Bit 24)                                      */
33271  #define R_DRW_COLOR2_COLOR2A_Msk              (0xff000000UL) /*!< COLOR2A (Bitfield-Mask: 0xff)                         */
33272  #define R_DRW_COLOR2_COLOR2R_Pos              (16UL)         /*!< COLOR2R (Bit 16)                                      */
33273  #define R_DRW_COLOR2_COLOR2R_Msk              (0xff0000UL)   /*!< COLOR2R (Bitfield-Mask: 0xff)                         */
33274  #define R_DRW_COLOR2_COLOR2G_Pos              (8UL)          /*!< COLOR2G (Bit 8)                                       */
33275  #define R_DRW_COLOR2_COLOR2G_Msk              (0xff00UL)     /*!< COLOR2G (Bitfield-Mask: 0xff)                         */
33276  #define R_DRW_COLOR2_COLOR2B_Pos              (0UL)          /*!< COLOR2B (Bit 0)                                       */
33277  #define R_DRW_COLOR2_COLOR2B_Msk              (0xffUL)       /*!< COLOR2B (Bitfield-Mask: 0xff)                         */
33278 /* ========================================================  PATTERN  ======================================================== */
33279  #define R_DRW_PATTERN_PATTERN_Pos             (0UL)          /*!< PATTERN (Bit 0)                                       */
33280  #define R_DRW_PATTERN_PATTERN_Msk             (0xffUL)       /*!< PATTERN (Bitfield-Mask: 0xff)                         */
33281 /* ========================================================  L1START  ======================================================== */
33282  #define R_DRW_L1START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
33283  #define R_DRW_L1START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
33284 /* ========================================================  L2START  ======================================================== */
33285  #define R_DRW_L2START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
33286  #define R_DRW_L2START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
33287 /* ========================================================  L3START  ======================================================== */
33288  #define R_DRW_L3START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
33289  #define R_DRW_L3START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
33290 /* ========================================================  L4START  ======================================================== */
33291  #define R_DRW_L4START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
33292  #define R_DRW_L4START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
33293 /* ========================================================  L5START  ======================================================== */
33294  #define R_DRW_L5START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
33295  #define R_DRW_L5START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
33296 /* ========================================================  L6START  ======================================================== */
33297  #define R_DRW_L6START_LSTART_Pos              (0UL)          /*!< LSTART (Bit 0)                                        */
33298  #define R_DRW_L6START_LSTART_Msk              (0xffffffffUL) /*!< LSTART (Bitfield-Mask: 0xffffffff)                    */
33299 /* ========================================================  L1XADD  ========================================================= */
33300  #define R_DRW_L1XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
33301  #define R_DRW_L1XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
33302 /* ========================================================  L2XADD  ========================================================= */
33303  #define R_DRW_L2XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
33304  #define R_DRW_L2XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
33305 /* ========================================================  L3XADD  ========================================================= */
33306  #define R_DRW_L3XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
33307  #define R_DRW_L3XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
33308 /* ========================================================  L4XADD  ========================================================= */
33309  #define R_DRW_L4XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
33310  #define R_DRW_L4XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
33311 /* ========================================================  L5XADD  ========================================================= */
33312  #define R_DRW_L5XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
33313  #define R_DRW_L5XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
33314 /* ========================================================  L6XADD  ========================================================= */
33315  #define R_DRW_L6XADD_LXADD_Pos                (0UL)          /*!< LXADD (Bit 0)                                         */
33316  #define R_DRW_L6XADD_LXADD_Msk                (0xffffffffUL) /*!< LXADD (Bitfield-Mask: 0xffffffff)                     */
33317 /* ========================================================  L1YADD  ========================================================= */
33318  #define R_DRW_L1YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
33319  #define R_DRW_L1YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
33320 /* ========================================================  L2YADD  ========================================================= */
33321  #define R_DRW_L2YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
33322  #define R_DRW_L2YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
33323 /* ========================================================  L3YADD  ========================================================= */
33324  #define R_DRW_L3YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
33325  #define R_DRW_L3YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
33326 /* ========================================================  L4YADD  ========================================================= */
33327  #define R_DRW_L4YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
33328  #define R_DRW_L4YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
33329 /* ========================================================  L5YADD  ========================================================= */
33330  #define R_DRW_L5YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
33331  #define R_DRW_L5YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
33332 /* ========================================================  L6YADD  ========================================================= */
33333  #define R_DRW_L6YADD_LYADD_Pos                (0UL)          /*!< LYADD (Bit 0)                                         */
33334  #define R_DRW_L6YADD_LYADD_Msk                (0xffffffffUL) /*!< LYADD (Bitfield-Mask: 0xffffffff)                     */
33335 /* ========================================================  L1BAND  ========================================================= */
33336  #define R_DRW_L1BAND_LBAND_Pos                (0UL)          /*!< LBAND (Bit 0)                                         */
33337  #define R_DRW_L1BAND_LBAND_Msk                (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff)                     */
33338 /* ========================================================  L2BAND  ========================================================= */
33339  #define R_DRW_L2BAND_LBAND_Pos                (0UL)          /*!< LBAND (Bit 0)                                         */
33340  #define R_DRW_L2BAND_LBAND_Msk                (0xffffffffUL) /*!< LBAND (Bitfield-Mask: 0xffffffff)                     */
33341 /* =======================================================  TEXORIGIN  ======================================================= */
33342  #define R_DRW_TEXORIGIN_TEXORIGIN_Pos         (0UL)          /*!< TEXORIGIN (Bit 0)                                     */
33343  #define R_DRW_TEXORIGIN_TEXORIGIN_Msk         (0xffffffffUL) /*!< TEXORIGIN (Bitfield-Mask: 0xffffffff)                 */
33344 /* =======================================================  TEXPITCH  ======================================================== */
33345  #define R_DRW_TEXPITCH_TEXPITCH_Pos           (0UL)          /*!< TEXPITCH (Bit 0)                                      */
33346  #define R_DRW_TEXPITCH_TEXPITCH_Msk           (0xffffffffUL) /*!< TEXPITCH (Bitfield-Mask: 0xffffffff)                  */
33347 /* ========================================================  TEXMASK  ======================================================== */
33348  #define R_DRW_TEXMASK_TEXVMASK_Pos            (11UL)         /*!< TEXVMASK (Bit 11)                                     */
33349  #define R_DRW_TEXMASK_TEXVMASK_Msk            (0xfffff800UL) /*!< TEXVMASK (Bitfield-Mask: 0x1fffff)                    */
33350  #define R_DRW_TEXMASK_TEXUMASK_Pos            (0UL)          /*!< TEXUMASK (Bit 0)                                      */
33351  #define R_DRW_TEXMASK_TEXUMASK_Msk            (0x7ffUL)      /*!< TEXUMASK (Bitfield-Mask: 0x7ff)                       */
33352 /* ========================================================  LUSTART  ======================================================== */
33353  #define R_DRW_LUSTART_LUSTART_Pos             (0UL)          /*!< LUSTART (Bit 0)                                       */
33354  #define R_DRW_LUSTART_LUSTART_Msk             (0xffffffffUL) /*!< LUSTART (Bitfield-Mask: 0xffffffff)                   */
33355 /* ========================================================  LUXADD  ========================================================= */
33356  #define R_DRW_LUXADD_LUXADD_Pos               (0UL)          /*!< LUXADD (Bit 0)                                        */
33357  #define R_DRW_LUXADD_LUXADD_Msk               (0xffffffffUL) /*!< LUXADD (Bitfield-Mask: 0xffffffff)                    */
33358 /* ========================================================  LUYADD  ========================================================= */
33359  #define R_DRW_LUYADD_LUYADD_Pos               (0UL)          /*!< LUYADD (Bit 0)                                        */
33360  #define R_DRW_LUYADD_LUYADD_Msk               (0xffffffffUL) /*!< LUYADD (Bitfield-Mask: 0xffffffff)                    */
33361 /* =======================================================  LVSTARTI  ======================================================== */
33362  #define R_DRW_LVSTARTI_LVSTARTI_Pos           (0UL)          /*!< LVSTARTI (Bit 0)                                      */
33363  #define R_DRW_LVSTARTI_LVSTARTI_Msk           (0xffffffffUL) /*!< LVSTARTI (Bitfield-Mask: 0xffffffff)                  */
33364 /* =======================================================  LVSTARTF  ======================================================== */
33365  #define R_DRW_LVSTARTF_LVSTARTF_Pos           (0UL)          /*!< LVSTARTF (Bit 0)                                      */
33366  #define R_DRW_LVSTARTF_LVSTARTF_Msk           (0xffffUL)     /*!< LVSTARTF (Bitfield-Mask: 0xffff)                      */
33367 /* ========================================================  LVXADDI  ======================================================== */
33368  #define R_DRW_LVXADDI_LVXADDI_Pos             (0UL)          /*!< LVXADDI (Bit 0)                                       */
33369  #define R_DRW_LVXADDI_LVXADDI_Msk             (0xffffffffUL) /*!< LVXADDI (Bitfield-Mask: 0xffffffff)                   */
33370 /* ========================================================  LVYADDI  ======================================================== */
33371  #define R_DRW_LVYADDI_LVYADDI_Pos             (0UL)          /*!< LVYADDI (Bit 0)                                       */
33372  #define R_DRW_LVYADDI_LVYADDI_Msk             (0xffffffffUL) /*!< LVYADDI (Bitfield-Mask: 0xffffffff)                   */
33373 /* =======================================================  LVYXADDF  ======================================================== */
33374  #define R_DRW_LVYXADDF_LVYADDF_Pos            (16UL)         /*!< LVYADDF (Bit 16)                                      */
33375  #define R_DRW_LVYXADDF_LVYADDF_Msk            (0xffff0000UL) /*!< LVYADDF (Bitfield-Mask: 0xffff)                       */
33376  #define R_DRW_LVYXADDF_LVXADDF_Pos            (0UL)          /*!< LVXADDF (Bit 0)                                       */
33377  #define R_DRW_LVYXADDF_LVXADDF_Msk            (0xffffUL)     /*!< LVXADDF (Bitfield-Mask: 0xffff)                       */
33378 /* =======================================================  TEXCLADDR  ======================================================= */
33379  #define R_DRW_TEXCLADDR_CLADDR_Pos            (0UL)          /*!< CLADDR (Bit 0)                                        */
33380  #define R_DRW_TEXCLADDR_CLADDR_Msk            (0xffUL)       /*!< CLADDR (Bitfield-Mask: 0xff)                          */
33381 /* =======================================================  TEXCLDATA  ======================================================= */
33382  #define R_DRW_TEXCLDATA_CLDATA_Pos            (0UL)          /*!< CLDATA (Bit 0)                                        */
33383  #define R_DRW_TEXCLDATA_CLDATA_Msk            (0xffffffffUL) /*!< CLDATA (Bitfield-Mask: 0xffffffff)                    */
33384 /* ======================================================  TEXCLOFFSET  ====================================================== */
33385  #define R_DRW_TEXCLOFFSET_CLOFFSET_Pos        (0UL)          /*!< CLOFFSET (Bit 0)                                      */
33386  #define R_DRW_TEXCLOFFSET_CLOFFSET_Msk        (0xffUL)       /*!< CLOFFSET (Bitfield-Mask: 0xff)                        */
33387 /* ========================================================  COLKEY  ========================================================= */
33388  #define R_DRW_COLKEY_COLKEYR_Pos              (16UL)         /*!< COLKEYR (Bit 16)                                      */
33389  #define R_DRW_COLKEY_COLKEYR_Msk              (0xff0000UL)   /*!< COLKEYR (Bitfield-Mask: 0xff)                         */
33390  #define R_DRW_COLKEY_COLKEYG_Pos              (8UL)          /*!< COLKEYG (Bit 8)                                       */
33391  #define R_DRW_COLKEY_COLKEYG_Msk              (0xff00UL)     /*!< COLKEYG (Bitfield-Mask: 0xff)                         */
33392  #define R_DRW_COLKEY_COLKEYB_Pos              (0UL)          /*!< COLKEYB (Bit 0)                                       */
33393  #define R_DRW_COLKEY_COLKEYB_Msk              (0xffUL)       /*!< COLKEYB (Bitfield-Mask: 0xff)                         */
33394 /* =========================================================  SIZE  ========================================================== */
33395  #define R_DRW_SIZE_SIZEY_Pos                  (16UL)         /*!< SIZEY (Bit 16)                                        */
33396  #define R_DRW_SIZE_SIZEY_Msk                  (0xffff0000UL) /*!< SIZEY (Bitfield-Mask: 0xffff)                         */
33397  #define R_DRW_SIZE_SIZEX_Pos                  (0UL)          /*!< SIZEX (Bit 0)                                         */
33398  #define R_DRW_SIZE_SIZEX_Msk                  (0xffffUL)     /*!< SIZEX (Bitfield-Mask: 0xffff)                         */
33399 /* =========================================================  PITCH  ========================================================= */
33400  #define R_DRW_PITCH_SSD_Pos                   (16UL)         /*!< SSD (Bit 16)                                          */
33401  #define R_DRW_PITCH_SSD_Msk                   (0xffff0000UL) /*!< SSD (Bitfield-Mask: 0xffff)                           */
33402  #define R_DRW_PITCH_PITCH_Pos                 (0UL)          /*!< PITCH (Bit 0)                                         */
33403  #define R_DRW_PITCH_PITCH_Msk                 (0xffffUL)     /*!< PITCH (Bitfield-Mask: 0xffff)                         */
33404 /* ========================================================  ORIGIN  ========================================================= */
33405  #define R_DRW_ORIGIN_ORIGIN_Pos               (0UL)          /*!< ORIGIN (Bit 0)                                        */
33406  #define R_DRW_ORIGIN_ORIGIN_Msk               (0xffffffffUL) /*!< ORIGIN (Bitfield-Mask: 0xffffffff)                    */
33407 /* ======================================================  DLISTSTART  ======================================================= */
33408  #define R_DRW_DLISTSTART_DLISTSTART_Pos       (0UL)          /*!< DLISTSTART (Bit 0)                                    */
33409  #define R_DRW_DLISTSTART_DLISTSTART_Msk       (0xffffffffUL) /*!< DLISTSTART (Bitfield-Mask: 0xffffffff)                */
33410 /* ======================================================  PERFTRIGGER  ====================================================== */
33411  #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Pos    (16UL)         /*!< PERFTRIGGER2 (Bit 16)                                 */
33412  #define R_DRW_PERFTRIGGER_PERFTRIGGER2_Msk    (0xffff0000UL) /*!< PERFTRIGGER2 (Bitfield-Mask: 0xffff)                  */
33413  #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Pos    (0UL)          /*!< PERFTRIGGER1 (Bit 0)                                  */
33414  #define R_DRW_PERFTRIGGER_PERFTRIGGER1_Msk    (0xffffUL)     /*!< PERFTRIGGER1 (Bitfield-Mask: 0xffff)                  */
33415 /* ======================================================  PERFCOUNT1  ======================================================= */
33416  #define R_DRW_PERFCOUNT1_PERFCOUNT_Pos        (0UL)          /*!< PERFCOUNT (Bit 0)                                     */
33417  #define R_DRW_PERFCOUNT1_PERFCOUNT_Msk        (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff)                 */
33418 /* ======================================================  PERFCOUNT2  ======================================================= */
33419  #define R_DRW_PERFCOUNT2_PERFCOUNT_Pos        (0UL)          /*!< PERFCOUNT (Bit 0)                                     */
33420  #define R_DRW_PERFCOUNT2_PERFCOUNT_Msk        (0xffffffffUL) /*!< PERFCOUNT (Bitfield-Mask: 0xffffffff)                 */
33421 
33422 /* =========================================================================================================================== */
33423 /* ================                                           R_DTC                                           ================ */
33424 /* =========================================================================================================================== */
33425 
33426 /* =========================================================  DTCCR  ========================================================= */
33427  #define R_DTC_DTCCR_RRS_Pos         (4UL)          /*!< RRS (Bit 4)                                           */
33428  #define R_DTC_DTCCR_RRS_Msk         (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
33429 /* ========================================================  DTCVBR  ========================================================= */
33430  #define R_DTC_DTCVBR_DTCVBR_Pos     (0UL)          /*!< DTCVBR (Bit 0)                                        */
33431  #define R_DTC_DTCVBR_DTCVBR_Msk     (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
33432 /* =========================================================  DTCST  ========================================================= */
33433  #define R_DTC_DTCST_DTCST_Pos       (0UL)          /*!< DTCST (Bit 0)                                         */
33434  #define R_DTC_DTCST_DTCST_Msk       (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
33435 /* ========================================================  DTCSTS  ========================================================= */
33436  #define R_DTC_DTCSTS_ACT_Pos        (15UL)         /*!< ACT (Bit 15)                                          */
33437  #define R_DTC_DTCSTS_ACT_Msk        (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
33438  #define R_DTC_DTCSTS_VECN_Pos       (0UL)          /*!< VECN (Bit 0)                                          */
33439  #define R_DTC_DTCSTS_VECN_Msk       (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
33440 /* =======================================================  DTCCR_SEC  ======================================================= */
33441  #define R_DTC_DTCCR_SEC_RRSS_Pos    (4UL)          /*!< RRSS (Bit 4)                                          */
33442  #define R_DTC_DTCCR_SEC_RRSS_Msk    (0x10UL)       /*!< RRSS (Bitfield-Mask: 0x01)                            */
33443 /* ======================================================  DTCVBR_SEC  ======================================================= */
33444 /* =========================================================  DTEVR  ========================================================= */
33445  #define R_DTC_DTEVR_DTEV_Pos        (0UL)          /*!< DTEV (Bit 0)                                          */
33446  #define R_DTC_DTEVR_DTEV_Msk        (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
33447  #define R_DTC_DTEVR_DTEVSAM_Pos     (8UL)          /*!< DTEVSAM (Bit 8)                                       */
33448  #define R_DTC_DTEVR_DTEVSAM_Msk     (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
33449  #define R_DTC_DTEVR_DTESTA_Pos      (16UL)         /*!< DTESTA (Bit 16)                                       */
33450  #define R_DTC_DTEVR_DTESTA_Msk      (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
33451 
33452 /* =========================================================================================================================== */
33453 /* ================                                           R_ELC                                           ================ */
33454 /* =========================================================================================================================== */
33455 
33456 /* =========================================================  ELCR  ========================================================== */
33457  #define R_ELC_ELCR_ELCON_Pos         (7UL)          /*!< ELCON (Bit 7)                                         */
33458  #define R_ELC_ELCR_ELCON_Msk         (0x80UL)       /*!< ELCON (Bitfield-Mask: 0x01)                           */
33459 /* ========================================================  ELCSARA  ======================================================== */
33460  #define R_ELC_ELCSARA_ELCR_Pos       (0UL)          /*!< ELCR (Bit 0)                                          */
33461  #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)        /*!< ELCR (Bitfield-Mask: 0x01)                            */
33462  #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)          /*!< ELSEGR0 (Bit 1)                                       */
33463  #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)        /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
33464  #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)          /*!< ELSEGR1 (Bit 2)                                       */
33465  #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)        /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
33466 /* ========================================================  ELCSARB  ======================================================== */
33467  #define R_ELC_ELCSARB_ELSR_Pos       (0UL)          /*!< ELSR (Bit 0)                                          */
33468  #define R_ELC_ELCSARB_ELSR_Msk       (0x1UL)        /*!< ELSR (Bitfield-Mask: 0x01)                            */
33469  #define R_ELC_ELCSARB_ELSR30_Pos     (30UL)         /*!< ELSR30 (Bit 30)                                       */
33470  #define R_ELC_ELCSARB_ELSR30_Msk     (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01)                          */
33471 /* ========================================================  ELCPARA  ======================================================== */
33472  #define R_ELC_ELCPARA_ELCR_Pos       (0UL)          /*!< ELCR (Bit 0)                                          */
33473  #define R_ELC_ELCPARA_ELCR_Msk       (0x1UL)        /*!< ELCR (Bitfield-Mask: 0x01)                            */
33474  #define R_ELC_ELCPARA_ELSEGR0_Pos    (1UL)          /*!< ELSEGR0 (Bit 1)                                       */
33475  #define R_ELC_ELCPARA_ELSEGR0_Msk    (0x2UL)        /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
33476  #define R_ELC_ELCPARA_ELSEGR1_Pos    (2UL)          /*!< ELSEGR1 (Bit 2)                                       */
33477  #define R_ELC_ELCPARA_ELSEGR1_Msk    (0x4UL)        /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
33478 /* ========================================================  ELCPARB  ======================================================== */
33479  #define R_ELC_ELCPARB_ELSR_Pos       (0UL)          /*!< ELSR (Bit 0)                                          */
33480  #define R_ELC_ELCPARB_ELSR_Msk       (0x1UL)        /*!< ELSR (Bitfield-Mask: 0x01)                            */
33481  #define R_ELC_ELCPARB_ELSR30_Pos     (30UL)         /*!< ELSR30 (Bit 30)                                       */
33482  #define R_ELC_ELCPARB_ELSR30_Msk     (0x40000000UL) /*!< ELSR30 (Bitfield-Mask: 0x01)                          */
33483 
33484 /* =========================================================================================================================== */
33485 /* ================                                         R_ETHERC0                                         ================ */
33486 /* =========================================================================================================================== */
33487 
33488 /* =========================================================  ECMR  ========================================================== */
33489  #define R_ETHERC0_ECMR_TPC_Pos          (20UL)         /*!< TPC (Bit 20)                                          */
33490  #define R_ETHERC0_ECMR_TPC_Msk          (0x100000UL)   /*!< TPC (Bitfield-Mask: 0x01)                             */
33491  #define R_ETHERC0_ECMR_ZPF_Pos          (19UL)         /*!< ZPF (Bit 19)                                          */
33492  #define R_ETHERC0_ECMR_ZPF_Msk          (0x80000UL)    /*!< ZPF (Bitfield-Mask: 0x01)                             */
33493  #define R_ETHERC0_ECMR_PFR_Pos          (18UL)         /*!< PFR (Bit 18)                                          */
33494  #define R_ETHERC0_ECMR_PFR_Msk          (0x40000UL)    /*!< PFR (Bitfield-Mask: 0x01)                             */
33495  #define R_ETHERC0_ECMR_RXF_Pos          (17UL)         /*!< RXF (Bit 17)                                          */
33496  #define R_ETHERC0_ECMR_RXF_Msk          (0x20000UL)    /*!< RXF (Bitfield-Mask: 0x01)                             */
33497  #define R_ETHERC0_ECMR_TXF_Pos          (16UL)         /*!< TXF (Bit 16)                                          */
33498  #define R_ETHERC0_ECMR_TXF_Msk          (0x10000UL)    /*!< TXF (Bitfield-Mask: 0x01)                             */
33499  #define R_ETHERC0_ECMR_PRCEF_Pos        (12UL)         /*!< PRCEF (Bit 12)                                        */
33500  #define R_ETHERC0_ECMR_PRCEF_Msk        (0x1000UL)     /*!< PRCEF (Bitfield-Mask: 0x01)                           */
33501  #define R_ETHERC0_ECMR_MPDE_Pos         (9UL)          /*!< MPDE (Bit 9)                                          */
33502  #define R_ETHERC0_ECMR_MPDE_Msk         (0x200UL)      /*!< MPDE (Bitfield-Mask: 0x01)                            */
33503  #define R_ETHERC0_ECMR_RE_Pos           (6UL)          /*!< RE (Bit 6)                                            */
33504  #define R_ETHERC0_ECMR_RE_Msk           (0x40UL)       /*!< RE (Bitfield-Mask: 0x01)                              */
33505  #define R_ETHERC0_ECMR_TE_Pos           (5UL)          /*!< TE (Bit 5)                                            */
33506  #define R_ETHERC0_ECMR_TE_Msk           (0x20UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
33507  #define R_ETHERC0_ECMR_ILB_Pos          (3UL)          /*!< ILB (Bit 3)                                           */
33508  #define R_ETHERC0_ECMR_ILB_Msk          (0x8UL)        /*!< ILB (Bitfield-Mask: 0x01)                             */
33509  #define R_ETHERC0_ECMR_RTM_Pos          (2UL)          /*!< RTM (Bit 2)                                           */
33510  #define R_ETHERC0_ECMR_RTM_Msk          (0x4UL)        /*!< RTM (Bitfield-Mask: 0x01)                             */
33511  #define R_ETHERC0_ECMR_DM_Pos           (1UL)          /*!< DM (Bit 1)                                            */
33512  #define R_ETHERC0_ECMR_DM_Msk           (0x2UL)        /*!< DM (Bitfield-Mask: 0x01)                              */
33513  #define R_ETHERC0_ECMR_PRM_Pos          (0UL)          /*!< PRM (Bit 0)                                           */
33514  #define R_ETHERC0_ECMR_PRM_Msk          (0x1UL)        /*!< PRM (Bitfield-Mask: 0x01)                             */
33515 /* =========================================================  RFLR  ========================================================== */
33516  #define R_ETHERC0_RFLR_RFL_Pos          (0UL)          /*!< RFL (Bit 0)                                           */
33517  #define R_ETHERC0_RFLR_RFL_Msk          (0xfffUL)      /*!< RFL (Bitfield-Mask: 0xfff)                            */
33518 /* =========================================================  ECSR  ========================================================== */
33519  #define R_ETHERC0_ECSR_BFR_Pos          (5UL)          /*!< BFR (Bit 5)                                           */
33520  #define R_ETHERC0_ECSR_BFR_Msk          (0x20UL)       /*!< BFR (Bitfield-Mask: 0x01)                             */
33521  #define R_ETHERC0_ECSR_PSRTO_Pos        (4UL)          /*!< PSRTO (Bit 4)                                         */
33522  #define R_ETHERC0_ECSR_PSRTO_Msk        (0x10UL)       /*!< PSRTO (Bitfield-Mask: 0x01)                           */
33523  #define R_ETHERC0_ECSR_LCHNG_Pos        (2UL)          /*!< LCHNG (Bit 2)                                         */
33524  #define R_ETHERC0_ECSR_LCHNG_Msk        (0x4UL)        /*!< LCHNG (Bitfield-Mask: 0x01)                           */
33525  #define R_ETHERC0_ECSR_MPD_Pos          (1UL)          /*!< MPD (Bit 1)                                           */
33526  #define R_ETHERC0_ECSR_MPD_Msk          (0x2UL)        /*!< MPD (Bitfield-Mask: 0x01)                             */
33527  #define R_ETHERC0_ECSR_ICD_Pos          (0UL)          /*!< ICD (Bit 0)                                           */
33528  #define R_ETHERC0_ECSR_ICD_Msk          (0x1UL)        /*!< ICD (Bitfield-Mask: 0x01)                             */
33529 /* ========================================================  ECSIPR  ========================================================= */
33530  #define R_ETHERC0_ECSIPR_BFSIPR_Pos     (5UL)          /*!< BFSIPR (Bit 5)                                        */
33531  #define R_ETHERC0_ECSIPR_BFSIPR_Msk     (0x20UL)       /*!< BFSIPR (Bitfield-Mask: 0x01)                          */
33532  #define R_ETHERC0_ECSIPR_PSRTOIP_Pos    (4UL)          /*!< PSRTOIP (Bit 4)                                       */
33533  #define R_ETHERC0_ECSIPR_PSRTOIP_Msk    (0x10UL)       /*!< PSRTOIP (Bitfield-Mask: 0x01)                         */
33534  #define R_ETHERC0_ECSIPR_LCHNGIP_Pos    (2UL)          /*!< LCHNGIP (Bit 2)                                       */
33535  #define R_ETHERC0_ECSIPR_LCHNGIP_Msk    (0x4UL)        /*!< LCHNGIP (Bitfield-Mask: 0x01)                         */
33536  #define R_ETHERC0_ECSIPR_MPDIP_Pos      (1UL)          /*!< MPDIP (Bit 1)                                         */
33537  #define R_ETHERC0_ECSIPR_MPDIP_Msk      (0x2UL)        /*!< MPDIP (Bitfield-Mask: 0x01)                           */
33538  #define R_ETHERC0_ECSIPR_ICDIP_Pos      (0UL)          /*!< ICDIP (Bit 0)                                         */
33539  #define R_ETHERC0_ECSIPR_ICDIP_Msk      (0x1UL)        /*!< ICDIP (Bitfield-Mask: 0x01)                           */
33540 /* ==========================================================  PIR  ========================================================== */
33541  #define R_ETHERC0_PIR_MDI_Pos           (3UL)          /*!< MDI (Bit 3)                                           */
33542  #define R_ETHERC0_PIR_MDI_Msk           (0x8UL)        /*!< MDI (Bitfield-Mask: 0x01)                             */
33543  #define R_ETHERC0_PIR_MDO_Pos           (2UL)          /*!< MDO (Bit 2)                                           */
33544  #define R_ETHERC0_PIR_MDO_Msk           (0x4UL)        /*!< MDO (Bitfield-Mask: 0x01)                             */
33545  #define R_ETHERC0_PIR_MMD_Pos           (1UL)          /*!< MMD (Bit 1)                                           */
33546  #define R_ETHERC0_PIR_MMD_Msk           (0x2UL)        /*!< MMD (Bitfield-Mask: 0x01)                             */
33547  #define R_ETHERC0_PIR_MDC_Pos           (0UL)          /*!< MDC (Bit 0)                                           */
33548  #define R_ETHERC0_PIR_MDC_Msk           (0x1UL)        /*!< MDC (Bitfield-Mask: 0x01)                             */
33549 /* ==========================================================  PSR  ========================================================== */
33550  #define R_ETHERC0_PSR_LMON_Pos          (0UL)          /*!< LMON (Bit 0)                                          */
33551  #define R_ETHERC0_PSR_LMON_Msk          (0x1UL)        /*!< LMON (Bitfield-Mask: 0x01)                            */
33552 /* =========================================================  RDMLR  ========================================================= */
33553  #define R_ETHERC0_RDMLR_RMD_Pos         (0UL)          /*!< RMD (Bit 0)                                           */
33554  #define R_ETHERC0_RDMLR_RMD_Msk         (0xfffffUL)    /*!< RMD (Bitfield-Mask: 0xfffff)                          */
33555 /* =========================================================  IPGR  ========================================================== */
33556  #define R_ETHERC0_IPGR_IPG_Pos          (0UL)          /*!< IPG (Bit 0)                                           */
33557  #define R_ETHERC0_IPGR_IPG_Msk          (0x1fUL)       /*!< IPG (Bitfield-Mask: 0x1f)                             */
33558 /* ==========================================================  APR  ========================================================== */
33559  #define R_ETHERC0_APR_AP_Pos            (0UL)          /*!< AP (Bit 0)                                            */
33560  #define R_ETHERC0_APR_AP_Msk            (0xffffUL)     /*!< AP (Bitfield-Mask: 0xffff)                            */
33561 /* ==========================================================  MPR  ========================================================== */
33562  #define R_ETHERC0_MPR_MP_Pos            (0UL)          /*!< MP (Bit 0)                                            */
33563  #define R_ETHERC0_MPR_MP_Msk            (0xffffUL)     /*!< MP (Bitfield-Mask: 0xffff)                            */
33564 /* =========================================================  RFCF  ========================================================== */
33565  #define R_ETHERC0_RFCF_RPAUSE_Pos       (0UL)          /*!< RPAUSE (Bit 0)                                        */
33566  #define R_ETHERC0_RFCF_RPAUSE_Msk       (0xffUL)       /*!< RPAUSE (Bitfield-Mask: 0xff)                          */
33567 /* ========================================================  TPAUSER  ======================================================== */
33568  #define R_ETHERC0_TPAUSER_TPAUSE_Pos    (0UL)          /*!< TPAUSE (Bit 0)                                        */
33569  #define R_ETHERC0_TPAUSER_TPAUSE_Msk    (0xffffUL)     /*!< TPAUSE (Bitfield-Mask: 0xffff)                        */
33570 /* =======================================================  TPAUSECR  ======================================================== */
33571 /* =========================================================  BCFRR  ========================================================= */
33572  #define R_ETHERC0_BCFRR_BCF_Pos         (0UL)          /*!< BCF (Bit 0)                                           */
33573  #define R_ETHERC0_BCFRR_BCF_Msk         (0xffffUL)     /*!< BCF (Bitfield-Mask: 0xffff)                           */
33574 /* =========================================================  MAHR  ========================================================== */
33575  #define R_ETHERC0_MAHR_MAHR_Pos         (0UL)          /*!< MAHR (Bit 0)                                          */
33576  #define R_ETHERC0_MAHR_MAHR_Msk         (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff)                      */
33577 /* =========================================================  MALR  ========================================================== */
33578  #define R_ETHERC0_MALR_MALR_Pos         (0UL)          /*!< MALR (Bit 0)                                          */
33579  #define R_ETHERC0_MALR_MALR_Msk         (0xffffUL)     /*!< MALR (Bitfield-Mask: 0xffff)                          */
33580 /* =========================================================  TROCR  ========================================================= */
33581  #define R_ETHERC0_TROCR_TROCR_Pos       (0UL)          /*!< TROCR (Bit 0)                                         */
33582  #define R_ETHERC0_TROCR_TROCR_Msk       (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff)                     */
33583 /* =========================================================  CDCR  ========================================================== */
33584 /* =========================================================  LCCR  ========================================================== */
33585  #define R_ETHERC0_LCCR_LCCR_Pos         (0UL)          /*!< LCCR (Bit 0)                                          */
33586  #define R_ETHERC0_LCCR_LCCR_Msk         (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff)                      */
33587 /* =========================================================  CNDCR  ========================================================= */
33588  #define R_ETHERC0_CNDCR_CNDCR_Pos       (0UL)          /*!< CNDCR (Bit 0)                                         */
33589  #define R_ETHERC0_CNDCR_CNDCR_Msk       (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff)                     */
33590 /* =========================================================  CEFCR  ========================================================= */
33591  #define R_ETHERC0_CEFCR_CEFCR_Pos       (0UL)          /*!< CEFCR (Bit 0)                                         */
33592  #define R_ETHERC0_CEFCR_CEFCR_Msk       (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff)                     */
33593 /* =========================================================  FRECR  ========================================================= */
33594  #define R_ETHERC0_FRECR_FRECR_Pos       (0UL)          /*!< FRECR (Bit 0)                                         */
33595  #define R_ETHERC0_FRECR_FRECR_Msk       (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff)                     */
33596 /* ========================================================  TSFRCR  ========================================================= */
33597  #define R_ETHERC0_TSFRCR_TSFRCR_Pos     (0UL)          /*!< TSFRCR (Bit 0)                                        */
33598  #define R_ETHERC0_TSFRCR_TSFRCR_Msk     (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff)                    */
33599 /* ========================================================  TLFRCR  ========================================================= */
33600  #define R_ETHERC0_TLFRCR_TLFRCR_Pos     (0UL)          /*!< TLFRCR (Bit 0)                                        */
33601  #define R_ETHERC0_TLFRCR_TLFRCR_Msk     (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff)                    */
33602 /* =========================================================  RFCR  ========================================================== */
33603  #define R_ETHERC0_RFCR_RFCR_Pos         (0UL)          /*!< RFCR (Bit 0)                                          */
33604  #define R_ETHERC0_RFCR_RFCR_Msk         (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff)                      */
33605 /* =========================================================  MAFCR  ========================================================= */
33606  #define R_ETHERC0_MAFCR_MAFCR_Pos       (0UL)          /*!< MAFCR (Bit 0)                                         */
33607  #define R_ETHERC0_MAFCR_MAFCR_Msk       (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff)                     */
33608 
33609 /* =========================================================================================================================== */
33610 /* ================                                      R_ETHERC_EDMAC                                       ================ */
33611 /* =========================================================================================================================== */
33612 
33613 /* =========================================================  EDMR  ========================================================== */
33614  #define R_ETHERC_EDMAC_EDMR_DE_Pos           (6UL)          /*!< DE (Bit 6)                                            */
33615  #define R_ETHERC_EDMAC_EDMR_DE_Msk           (0x40UL)       /*!< DE (Bitfield-Mask: 0x01)                              */
33616  #define R_ETHERC_EDMAC_EDMR_DL_Pos           (4UL)          /*!< DL (Bit 4)                                            */
33617  #define R_ETHERC_EDMAC_EDMR_DL_Msk           (0x30UL)       /*!< DL (Bitfield-Mask: 0x03)                              */
33618  #define R_ETHERC_EDMAC_EDMR_SWR_Pos          (0UL)          /*!< SWR (Bit 0)                                           */
33619  #define R_ETHERC_EDMAC_EDMR_SWR_Msk          (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
33620 /* =========================================================  EDTRR  ========================================================= */
33621  #define R_ETHERC_EDMAC_EDTRR_TR_Pos          (0UL)          /*!< TR (Bit 0)                                            */
33622  #define R_ETHERC_EDMAC_EDTRR_TR_Msk          (0x1UL)        /*!< TR (Bitfield-Mask: 0x01)                              */
33623 /* =========================================================  EDRRR  ========================================================= */
33624  #define R_ETHERC_EDMAC_EDRRR_RR_Pos          (0UL)          /*!< RR (Bit 0)                                            */
33625  #define R_ETHERC_EDMAC_EDRRR_RR_Msk          (0x1UL)        /*!< RR (Bitfield-Mask: 0x01)                              */
33626 /* =========================================================  TDLAR  ========================================================= */
33627  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos       (0UL)          /*!< TDLAR (Bit 0)                                         */
33628  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk       (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff)                     */
33629 /* =========================================================  RDLAR  ========================================================= */
33630  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos       (0UL)          /*!< RDLAR (Bit 0)                                         */
33631  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk       (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff)                     */
33632 /* =========================================================  EESR  ========================================================== */
33633  #define R_ETHERC_EDMAC_EESR_TWB_Pos          (30UL)         /*!< TWB (Bit 30)                                          */
33634  #define R_ETHERC_EDMAC_EESR_TWB_Msk          (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01)                             */
33635  #define R_ETHERC_EDMAC_EESR_TABT_Pos         (26UL)         /*!< TABT (Bit 26)                                         */
33636  #define R_ETHERC_EDMAC_EESR_TABT_Msk         (0x4000000UL)  /*!< TABT (Bitfield-Mask: 0x01)                            */
33637  #define R_ETHERC_EDMAC_EESR_RABT_Pos         (25UL)         /*!< RABT (Bit 25)                                         */
33638  #define R_ETHERC_EDMAC_EESR_RABT_Msk         (0x2000000UL)  /*!< RABT (Bitfield-Mask: 0x01)                            */
33639  #define R_ETHERC_EDMAC_EESR_RFCOF_Pos        (24UL)         /*!< RFCOF (Bit 24)                                        */
33640  #define R_ETHERC_EDMAC_EESR_RFCOF_Msk        (0x1000000UL)  /*!< RFCOF (Bitfield-Mask: 0x01)                           */
33641  #define R_ETHERC_EDMAC_EESR_ADE_Pos          (23UL)         /*!< ADE (Bit 23)                                          */
33642  #define R_ETHERC_EDMAC_EESR_ADE_Msk          (0x800000UL)   /*!< ADE (Bitfield-Mask: 0x01)                             */
33643  #define R_ETHERC_EDMAC_EESR_ECI_Pos          (22UL)         /*!< ECI (Bit 22)                                          */
33644  #define R_ETHERC_EDMAC_EESR_ECI_Msk          (0x400000UL)   /*!< ECI (Bitfield-Mask: 0x01)                             */
33645  #define R_ETHERC_EDMAC_EESR_TC_Pos           (21UL)         /*!< TC (Bit 21)                                           */
33646  #define R_ETHERC_EDMAC_EESR_TC_Msk           (0x200000UL)   /*!< TC (Bitfield-Mask: 0x01)                              */
33647  #define R_ETHERC_EDMAC_EESR_TDE_Pos          (20UL)         /*!< TDE (Bit 20)                                          */
33648  #define R_ETHERC_EDMAC_EESR_TDE_Msk          (0x100000UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
33649  #define R_ETHERC_EDMAC_EESR_TFUF_Pos         (19UL)         /*!< TFUF (Bit 19)                                         */
33650  #define R_ETHERC_EDMAC_EESR_TFUF_Msk         (0x80000UL)    /*!< TFUF (Bitfield-Mask: 0x01)                            */
33651  #define R_ETHERC_EDMAC_EESR_FR_Pos           (18UL)         /*!< FR (Bit 18)                                           */
33652  #define R_ETHERC_EDMAC_EESR_FR_Msk           (0x40000UL)    /*!< FR (Bitfield-Mask: 0x01)                              */
33653  #define R_ETHERC_EDMAC_EESR_RDE_Pos          (17UL)         /*!< RDE (Bit 17)                                          */
33654  #define R_ETHERC_EDMAC_EESR_RDE_Msk          (0x20000UL)    /*!< RDE (Bitfield-Mask: 0x01)                             */
33655  #define R_ETHERC_EDMAC_EESR_RFOF_Pos         (16UL)         /*!< RFOF (Bit 16)                                         */
33656  #define R_ETHERC_EDMAC_EESR_RFOF_Msk         (0x10000UL)    /*!< RFOF (Bitfield-Mask: 0x01)                            */
33657  #define R_ETHERC_EDMAC_EESR_CND_Pos          (11UL)         /*!< CND (Bit 11)                                          */
33658  #define R_ETHERC_EDMAC_EESR_CND_Msk          (0x800UL)      /*!< CND (Bitfield-Mask: 0x01)                             */
33659  #define R_ETHERC_EDMAC_EESR_DLC_Pos          (10UL)         /*!< DLC (Bit 10)                                          */
33660  #define R_ETHERC_EDMAC_EESR_DLC_Msk          (0x400UL)      /*!< DLC (Bitfield-Mask: 0x01)                             */
33661  #define R_ETHERC_EDMAC_EESR_CD_Pos           (9UL)          /*!< CD (Bit 9)                                            */
33662  #define R_ETHERC_EDMAC_EESR_CD_Msk           (0x200UL)      /*!< CD (Bitfield-Mask: 0x01)                              */
33663  #define R_ETHERC_EDMAC_EESR_TRO_Pos          (8UL)          /*!< TRO (Bit 8)                                           */
33664  #define R_ETHERC_EDMAC_EESR_TRO_Msk          (0x100UL)      /*!< TRO (Bitfield-Mask: 0x01)                             */
33665  #define R_ETHERC_EDMAC_EESR_RMAF_Pos         (7UL)          /*!< RMAF (Bit 7)                                          */
33666  #define R_ETHERC_EDMAC_EESR_RMAF_Msk         (0x80UL)       /*!< RMAF (Bitfield-Mask: 0x01)                            */
33667  #define R_ETHERC_EDMAC_EESR_RRF_Pos          (4UL)          /*!< RRF (Bit 4)                                           */
33668  #define R_ETHERC_EDMAC_EESR_RRF_Msk          (0x10UL)       /*!< RRF (Bitfield-Mask: 0x01)                             */
33669  #define R_ETHERC_EDMAC_EESR_RTLF_Pos         (3UL)          /*!< RTLF (Bit 3)                                          */
33670  #define R_ETHERC_EDMAC_EESR_RTLF_Msk         (0x8UL)        /*!< RTLF (Bitfield-Mask: 0x01)                            */
33671  #define R_ETHERC_EDMAC_EESR_RTSF_Pos         (2UL)          /*!< RTSF (Bit 2)                                          */
33672  #define R_ETHERC_EDMAC_EESR_RTSF_Msk         (0x4UL)        /*!< RTSF (Bitfield-Mask: 0x01)                            */
33673  #define R_ETHERC_EDMAC_EESR_PRE_Pos          (1UL)          /*!< PRE (Bit 1)                                           */
33674  #define R_ETHERC_EDMAC_EESR_PRE_Msk          (0x2UL)        /*!< PRE (Bitfield-Mask: 0x01)                             */
33675  #define R_ETHERC_EDMAC_EESR_CERF_Pos         (0UL)          /*!< CERF (Bit 0)                                          */
33676  #define R_ETHERC_EDMAC_EESR_CERF_Msk         (0x1UL)        /*!< CERF (Bitfield-Mask: 0x01)                            */
33677 /* ========================================================  EESIPR  ========================================================= */
33678  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos      (30UL)         /*!< TWBIP (Bit 30)                                        */
33679  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk      (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01)                           */
33680  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos     (26UL)         /*!< TABTIP (Bit 26)                                       */
33681  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk     (0x4000000UL)  /*!< TABTIP (Bitfield-Mask: 0x01)                          */
33682  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos     (25UL)         /*!< RABTIP (Bit 25)                                       */
33683  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk     (0x2000000UL)  /*!< RABTIP (Bitfield-Mask: 0x01)                          */
33684  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos    (24UL)         /*!< RFCOFIP (Bit 24)                                      */
33685  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk    (0x1000000UL)  /*!< RFCOFIP (Bitfield-Mask: 0x01)                         */
33686  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos      (23UL)         /*!< ADEIP (Bit 23)                                        */
33687  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk      (0x800000UL)   /*!< ADEIP (Bitfield-Mask: 0x01)                           */
33688  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos      (22UL)         /*!< ECIIP (Bit 22)                                        */
33689  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk      (0x400000UL)   /*!< ECIIP (Bitfield-Mask: 0x01)                           */
33690  #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos       (21UL)         /*!< TCIP (Bit 21)                                         */
33691  #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk       (0x200000UL)   /*!< TCIP (Bitfield-Mask: 0x01)                            */
33692  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos      (20UL)         /*!< TDEIP (Bit 20)                                        */
33693  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk      (0x100000UL)   /*!< TDEIP (Bitfield-Mask: 0x01)                           */
33694  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos     (19UL)         /*!< TFUFIP (Bit 19)                                       */
33695  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk     (0x80000UL)    /*!< TFUFIP (Bitfield-Mask: 0x01)                          */
33696  #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos       (18UL)         /*!< FRIP (Bit 18)                                         */
33697  #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk       (0x40000UL)    /*!< FRIP (Bitfield-Mask: 0x01)                            */
33698  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos      (17UL)         /*!< RDEIP (Bit 17)                                        */
33699  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk      (0x20000UL)    /*!< RDEIP (Bitfield-Mask: 0x01)                           */
33700  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos     (16UL)         /*!< RFOFIP (Bit 16)                                       */
33701  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk     (0x10000UL)    /*!< RFOFIP (Bitfield-Mask: 0x01)                          */
33702  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos      (11UL)         /*!< CNDIP (Bit 11)                                        */
33703  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk      (0x800UL)      /*!< CNDIP (Bitfield-Mask: 0x01)                           */
33704  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos      (10UL)         /*!< DLCIP (Bit 10)                                        */
33705  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk      (0x400UL)      /*!< DLCIP (Bitfield-Mask: 0x01)                           */
33706  #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos       (9UL)          /*!< CDIP (Bit 9)                                          */
33707  #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk       (0x200UL)      /*!< CDIP (Bitfield-Mask: 0x01)                            */
33708  #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos      (8UL)          /*!< TROIP (Bit 8)                                         */
33709  #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk      (0x100UL)      /*!< TROIP (Bitfield-Mask: 0x01)                           */
33710  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos     (7UL)          /*!< RMAFIP (Bit 7)                                        */
33711  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk     (0x80UL)       /*!< RMAFIP (Bitfield-Mask: 0x01)                          */
33712  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos      (4UL)          /*!< RRFIP (Bit 4)                                         */
33713  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk      (0x10UL)       /*!< RRFIP (Bitfield-Mask: 0x01)                           */
33714  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos     (3UL)          /*!< RTLFIP (Bit 3)                                        */
33715  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk     (0x8UL)        /*!< RTLFIP (Bitfield-Mask: 0x01)                          */
33716  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos     (2UL)          /*!< RTSFIP (Bit 2)                                        */
33717  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk     (0x4UL)        /*!< RTSFIP (Bitfield-Mask: 0x01)                          */
33718  #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos      (1UL)          /*!< PREIP (Bit 1)                                         */
33719  #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk      (0x2UL)        /*!< PREIP (Bitfield-Mask: 0x01)                           */
33720  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos     (0UL)          /*!< CERFIP (Bit 0)                                        */
33721  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk     (0x1UL)        /*!< CERFIP (Bitfield-Mask: 0x01)                          */
33722 /* ========================================================  TRSCER  ========================================================= */
33723  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos     (7UL)          /*!< RMAFCE (Bit 7)                                        */
33724  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk     (0x80UL)       /*!< RMAFCE (Bitfield-Mask: 0x01)                          */
33725  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos      (4UL)          /*!< RRFCE (Bit 4)                                         */
33726  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk      (0x10UL)       /*!< RRFCE (Bitfield-Mask: 0x01)                           */
33727 /* =========================================================  RMFCR  ========================================================= */
33728  #define R_ETHERC_EDMAC_RMFCR_MFC_Pos         (0UL)          /*!< MFC (Bit 0)                                           */
33729  #define R_ETHERC_EDMAC_RMFCR_MFC_Msk         (0xffffUL)     /*!< MFC (Bitfield-Mask: 0xffff)                           */
33730 /* =========================================================  TFTR  ========================================================== */
33731  #define R_ETHERC_EDMAC_TFTR_TFT_Pos          (0UL)          /*!< TFT (Bit 0)                                           */
33732  #define R_ETHERC_EDMAC_TFTR_TFT_Msk          (0x7ffUL)      /*!< TFT (Bitfield-Mask: 0x7ff)                            */
33733 /* ==========================================================  FDR  ========================================================== */
33734  #define R_ETHERC_EDMAC_FDR_TFD_Pos           (8UL)          /*!< TFD (Bit 8)                                           */
33735  #define R_ETHERC_EDMAC_FDR_TFD_Msk           (0x1f00UL)     /*!< TFD (Bitfield-Mask: 0x1f)                             */
33736  #define R_ETHERC_EDMAC_FDR_RFD_Pos           (0UL)          /*!< RFD (Bit 0)                                           */
33737  #define R_ETHERC_EDMAC_FDR_RFD_Msk           (0x1fUL)       /*!< RFD (Bitfield-Mask: 0x1f)                             */
33738 /* =========================================================  RMCR  ========================================================== */
33739  #define R_ETHERC_EDMAC_RMCR_RNR_Pos          (0UL)          /*!< RNR (Bit 0)                                           */
33740  #define R_ETHERC_EDMAC_RMCR_RNR_Msk          (0x1UL)        /*!< RNR (Bitfield-Mask: 0x01)                             */
33741 /* =========================================================  TFUCR  ========================================================= */
33742  #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos       (0UL)          /*!< UNDER (Bit 0)                                         */
33743  #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk       (0xffffUL)     /*!< UNDER (Bitfield-Mask: 0xffff)                         */
33744 /* =========================================================  RFOCR  ========================================================= */
33745  #define R_ETHERC_EDMAC_RFOCR_OVER_Pos        (0UL)          /*!< OVER (Bit 0)                                          */
33746  #define R_ETHERC_EDMAC_RFOCR_OVER_Msk        (0xffffUL)     /*!< OVER (Bitfield-Mask: 0xffff)                          */
33747 /* =========================================================  IOSR  ========================================================== */
33748  #define R_ETHERC_EDMAC_IOSR_ELB_Pos          (0UL)          /*!< ELB (Bit 0)                                           */
33749  #define R_ETHERC_EDMAC_IOSR_ELB_Msk          (0x1UL)        /*!< ELB (Bitfield-Mask: 0x01)                             */
33750 /* =========================================================  FCFTR  ========================================================= */
33751  #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos        (16UL)         /*!< RFFO (Bit 16)                                         */
33752  #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk        (0x70000UL)    /*!< RFFO (Bitfield-Mask: 0x07)                            */
33753  #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos        (0UL)          /*!< RFDO (Bit 0)                                          */
33754  #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk        (0x7UL)        /*!< RFDO (Bitfield-Mask: 0x07)                            */
33755 /* ========================================================  RPADIR  ========================================================= */
33756  #define R_ETHERC_EDMAC_RPADIR_PADS_Pos       (16UL)         /*!< PADS (Bit 16)                                         */
33757  #define R_ETHERC_EDMAC_RPADIR_PADS_Msk       (0x30000UL)    /*!< PADS (Bitfield-Mask: 0x03)                            */
33758  #define R_ETHERC_EDMAC_RPADIR_PADR_Pos       (0UL)          /*!< PADR (Bit 0)                                          */
33759  #define R_ETHERC_EDMAC_RPADIR_PADR_Msk       (0x3fUL)       /*!< PADR (Bitfield-Mask: 0x3f)                            */
33760 /* =========================================================  TRIMD  ========================================================= */
33761  #define R_ETHERC_EDMAC_TRIMD_TIM_Pos         (4UL)          /*!< TIM (Bit 4)                                           */
33762  #define R_ETHERC_EDMAC_TRIMD_TIM_Msk         (0x10UL)       /*!< TIM (Bitfield-Mask: 0x01)                             */
33763  #define R_ETHERC_EDMAC_TRIMD_TIS_Pos         (0UL)          /*!< TIS (Bit 0)                                           */
33764  #define R_ETHERC_EDMAC_TRIMD_TIS_Msk         (0x1UL)        /*!< TIS (Bitfield-Mask: 0x01)                             */
33765 /* =========================================================  RBWAR  ========================================================= */
33766  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos       (0UL)          /*!< RBWAR (Bit 0)                                         */
33767  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk       (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff)                     */
33768 /* =========================================================  RDFAR  ========================================================= */
33769  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos       (0UL)          /*!< RDFAR (Bit 0)                                         */
33770  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk       (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff)                     */
33771 /* =========================================================  TBRAR  ========================================================= */
33772  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos       (0UL)          /*!< TBRAR (Bit 0)                                         */
33773  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk       (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff)                     */
33774 /* =========================================================  TDFAR  ========================================================= */
33775  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos       (0UL)          /*!< TDFAR (Bit 0)                                         */
33776  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk       (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff)                     */
33777 
33778 /* =========================================================================================================================== */
33779 /* ================                                       R_FACI_HP_CMD                                       ================ */
33780 /* =========================================================================================================================== */
33781 
33782 /* ======================================================  FACI_CMD16  ======================================================= */
33783 /* =======================================================  FACI_CMD8  ======================================================= */
33784 
33785 /* =========================================================================================================================== */
33786 /* ================                                         R_FACI_HP                                         ================ */
33787 /* =========================================================================================================================== */
33788 
33789 /* ========================================================  FASTAT  ========================================================= */
33790  #define R_FACI_HP_FASTAT_CFAE_Pos         (7UL)          /*!< CFAE (Bit 7)                                          */
33791  #define R_FACI_HP_FASTAT_CFAE_Msk         (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
33792  #define R_FACI_HP_FASTAT_CMDLK_Pos        (4UL)          /*!< CMDLK (Bit 4)                                         */
33793  #define R_FACI_HP_FASTAT_CMDLK_Msk        (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
33794  #define R_FACI_HP_FASTAT_DFAE_Pos         (3UL)          /*!< DFAE (Bit 3)                                          */
33795  #define R_FACI_HP_FASTAT_DFAE_Msk         (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
33796 /* ========================================================  FAEINT  ========================================================= */
33797  #define R_FACI_HP_FAEINT_CFAEIE_Pos       (7UL)          /*!< CFAEIE (Bit 7)                                        */
33798  #define R_FACI_HP_FAEINT_CFAEIE_Msk       (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
33799  #define R_FACI_HP_FAEINT_CMDLKIE_Pos      (4UL)          /*!< CMDLKIE (Bit 4)                                       */
33800  #define R_FACI_HP_FAEINT_CMDLKIE_Msk      (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
33801  #define R_FACI_HP_FAEINT_DFAEIE_Pos       (3UL)          /*!< DFAEIE (Bit 3)                                        */
33802  #define R_FACI_HP_FAEINT_DFAEIE_Msk       (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
33803 /* ========================================================  FRDYIE  ========================================================= */
33804  #define R_FACI_HP_FRDYIE_FRDYIE_Pos       (0UL)          /*!< FRDYIE (Bit 0)                                        */
33805  #define R_FACI_HP_FRDYIE_FRDYIE_Msk       (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
33806 /* ========================================================  FSADDR  ========================================================= */
33807  #define R_FACI_HP_FSADDR_FSA_Pos          (0UL)          /*!< FSA (Bit 0)                                           */
33808  #define R_FACI_HP_FSADDR_FSA_Msk          (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
33809 /* ========================================================  FEADDR  ========================================================= */
33810  #define R_FACI_HP_FEADDR_FEA_Pos          (0UL)          /*!< FEA (Bit 0)                                           */
33811  #define R_FACI_HP_FEADDR_FEA_Msk          (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
33812 /* ========================================================  FMEPROT  ======================================================== */
33813  #define R_FACI_HP_FMEPROT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
33814  #define R_FACI_HP_FMEPROT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33815  #define R_FACI_HP_FMEPROT_CEPROT_Pos      (0UL)          /*!< CEPROT (Bit 0)                                        */
33816  #define R_FACI_HP_FMEPROT_CEPROT_Msk      (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
33817 /* ========================================================  FBPROT0  ======================================================== */
33818  #define R_FACI_HP_FBPROT0_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
33819  #define R_FACI_HP_FBPROT0_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33820  #define R_FACI_HP_FBPROT0_BPCN0_Pos       (0UL)          /*!< BPCN0 (Bit 0)                                         */
33821  #define R_FACI_HP_FBPROT0_BPCN0_Msk       (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
33822 /* ========================================================  FBPROT1  ======================================================== */
33823  #define R_FACI_HP_FBPROT1_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
33824  #define R_FACI_HP_FBPROT1_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33825  #define R_FACI_HP_FBPROT1_BPCN1_Pos       (0UL)          /*!< BPCN1 (Bit 0)                                         */
33826  #define R_FACI_HP_FBPROT1_BPCN1_Msk       (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
33827 /* ========================================================  FSTATR  ========================================================= */
33828  #define R_FACI_HP_FSTATR_ILGCOMERR_Pos    (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
33829  #define R_FACI_HP_FSTATR_ILGCOMERR_Msk    (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
33830  #define R_FACI_HP_FSTATR_FESETERR_Pos     (22UL)         /*!< FESETERR (Bit 22)                                     */
33831  #define R_FACI_HP_FSTATR_FESETERR_Msk     (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
33832  #define R_FACI_HP_FSTATR_SECERR_Pos       (21UL)         /*!< SECERR (Bit 21)                                       */
33833  #define R_FACI_HP_FSTATR_SECERR_Msk       (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
33834  #define R_FACI_HP_FSTATR_OTERR_Pos        (20UL)         /*!< OTERR (Bit 20)                                        */
33835  #define R_FACI_HP_FSTATR_OTERR_Msk        (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
33836  #define R_FACI_HP_FSTATR_FRDY_Pos         (15UL)         /*!< FRDY (Bit 15)                                         */
33837  #define R_FACI_HP_FSTATR_FRDY_Msk         (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
33838  #define R_FACI_HP_FSTATR_ILGLERR_Pos      (14UL)         /*!< ILGLERR (Bit 14)                                      */
33839  #define R_FACI_HP_FSTATR_ILGLERR_Msk      (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
33840  #define R_FACI_HP_FSTATR_ERSERR_Pos       (13UL)         /*!< ERSERR (Bit 13)                                       */
33841  #define R_FACI_HP_FSTATR_ERSERR_Msk       (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
33842  #define R_FACI_HP_FSTATR_PRGERR_Pos       (12UL)         /*!< PRGERR (Bit 12)                                       */
33843  #define R_FACI_HP_FSTATR_PRGERR_Msk       (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
33844  #define R_FACI_HP_FSTATR_SUSRDY_Pos       (11UL)         /*!< SUSRDY (Bit 11)                                       */
33845  #define R_FACI_HP_FSTATR_SUSRDY_Msk       (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
33846  #define R_FACI_HP_FSTATR_DBFULL_Pos       (10UL)         /*!< DBFULL (Bit 10)                                       */
33847  #define R_FACI_HP_FSTATR_DBFULL_Msk       (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
33848  #define R_FACI_HP_FSTATR_ERSSPD_Pos       (9UL)          /*!< ERSSPD (Bit 9)                                        */
33849  #define R_FACI_HP_FSTATR_ERSSPD_Msk       (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
33850  #define R_FACI_HP_FSTATR_PRGSPD_Pos       (8UL)          /*!< PRGSPD (Bit 8)                                        */
33851  #define R_FACI_HP_FSTATR_PRGSPD_Msk       (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
33852  #define R_FACI_HP_FSTATR_FLWEERR_Pos      (6UL)          /*!< FLWEERR (Bit 6)                                       */
33853  #define R_FACI_HP_FSTATR_FLWEERR_Msk      (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
33854 /* ========================================================  FENTRYR  ======================================================== */
33855  #define R_FACI_HP_FENTRYR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
33856  #define R_FACI_HP_FENTRYR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33857  #define R_FACI_HP_FENTRYR_FENTRYD_Pos     (7UL)          /*!< FENTRYD (Bit 7)                                       */
33858  #define R_FACI_HP_FENTRYR_FENTRYD_Msk     (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
33859  #define R_FACI_HP_FENTRYR_FENTRYC_Pos     (0UL)          /*!< FENTRYC (Bit 0)                                       */
33860  #define R_FACI_HP_FENTRYR_FENTRYC_Msk     (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
33861 /* =======================================================  FSUINITR  ======================================================== */
33862  #define R_FACI_HP_FSUINITR_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
33863  #define R_FACI_HP_FSUINITR_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33864  #define R_FACI_HP_FSUINITR_SUINIT_Pos     (0UL)          /*!< SUINIT (Bit 0)                                        */
33865  #define R_FACI_HP_FSUINITR_SUINIT_Msk     (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
33866 /* =========================================================  FCMDR  ========================================================= */
33867  #define R_FACI_HP_FCMDR_CMDR_Pos          (8UL)          /*!< CMDR (Bit 8)                                          */
33868  #define R_FACI_HP_FCMDR_CMDR_Msk          (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
33869  #define R_FACI_HP_FCMDR_PCMDR_Pos         (0UL)          /*!< PCMDR (Bit 0)                                         */
33870  #define R_FACI_HP_FCMDR_PCMDR_Msk         (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
33871 /* ========================================================  FBCCNT  ========================================================= */
33872  #define R_FACI_HP_FBCCNT_BCDIR_Pos        (0UL)          /*!< BCDIR (Bit 0)                                         */
33873  #define R_FACI_HP_FBCCNT_BCDIR_Msk        (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
33874 /* ========================================================  FBCSTAT  ======================================================== */
33875  #define R_FACI_HP_FBCSTAT_BCST_Pos        (0UL)          /*!< BCST (Bit 0)                                          */
33876  #define R_FACI_HP_FBCSTAT_BCST_Msk        (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
33877 /* ========================================================  FPSADDR  ======================================================== */
33878  #define R_FACI_HP_FPSADDR_PSADR_Pos       (0UL)          /*!< PSADR (Bit 0)                                         */
33879  #define R_FACI_HP_FPSADDR_PSADR_Msk       (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
33880 /* ========================================================  FAWMON  ========================================================= */
33881  #define R_FACI_HP_FAWMON_BTFLG_Pos        (31UL)         /*!< BTFLG (Bit 31)                                        */
33882  #define R_FACI_HP_FAWMON_BTFLG_Msk        (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
33883  #define R_FACI_HP_FAWMON_FAWE_Pos         (16UL)         /*!< FAWE (Bit 16)                                         */
33884  #define R_FACI_HP_FAWMON_FAWE_Msk         (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
33885  #define R_FACI_HP_FAWMON_FSPR_Pos         (15UL)         /*!< FSPR (Bit 15)                                         */
33886  #define R_FACI_HP_FAWMON_FSPR_Msk         (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
33887  #define R_FACI_HP_FAWMON_FAWS_Pos         (0UL)          /*!< FAWS (Bit 0)                                          */
33888  #define R_FACI_HP_FAWMON_FAWS_Msk         (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
33889 /* =========================================================  FCPSR  ========================================================= */
33890  #define R_FACI_HP_FCPSR_ESUSPMD_Pos       (0UL)          /*!< ESUSPMD (Bit 0)                                       */
33891  #define R_FACI_HP_FCPSR_ESUSPMD_Msk       (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
33892 /* ========================================================  FPCKAR  ========================================================= */
33893  #define R_FACI_HP_FPCKAR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
33894  #define R_FACI_HP_FPCKAR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33895  #define R_FACI_HP_FPCKAR_PCKA_Pos         (0UL)          /*!< PCKA (Bit 0)                                          */
33896  #define R_FACI_HP_FPCKAR_PCKA_Msk         (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
33897 /* ========================================================  FSUACR  ========================================================= */
33898  #define R_FACI_HP_FSUACR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
33899  #define R_FACI_HP_FSUACR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33900  #define R_FACI_HP_FSUACR_SAS_Pos          (0UL)          /*!< SAS (Bit 0)                                           */
33901  #define R_FACI_HP_FSUACR_SAS_Msk          (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
33902 
33903 /* =========================================================================================================================== */
33904 /* ================                                         R_FCACHE                                          ================ */
33905 /* =========================================================================================================================== */
33906 
33907 /* ========================================================  FCACHEE  ======================================================== */
33908  #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)     /*!< FCACHEEN (Bit 0)                                      */
33909  #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)   /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
33910 /* =======================================================  FCACHEIV  ======================================================== */
33911  #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)     /*!< FCACHEIV (Bit 0)                                      */
33912  #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)   /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
33913 /* =========================================================  FLWT  ========================================================== */
33914  #define R_FCACHE_FLWT_FLWT_Pos            (0UL)     /*!< FLWT (Bit 0)                                          */
33915  #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)   /*!< FLWT (Bitfield-Mask: 0x07)                            */
33916 /* =========================================================  FSAR  ========================================================== */
33917  #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)     /*!< FLWTSA (Bit 0)                                        */
33918  #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)   /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
33919  #define R_FCACHE_FSAR_FCACHEENSA_Pos      (1UL)     /*!< FCACHEENSA (Bit 1)                                    */
33920  #define R_FCACHE_FSAR_FCACHEENSA_Msk      (0x2UL)   /*!< FCACHEENSA (Bitfield-Mask: 0x01)                      */
33921  #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)     /*!< FCKMHZSA (Bit 8)                                      */
33922  #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
33923  #define R_FCACHE_FSAR_FACICOMISA_Pos      (9UL)     /*!< FACICOMISA (Bit 9)                                    */
33924  #define R_FCACHE_FSAR_FACICOMISA_Msk      (0x200UL) /*!< FACICOMISA (Bitfield-Mask: 0x01)                      */
33925  #define R_FCACHE_FSAR_FACICOMRSA_Pos      (10UL)    /*!< FACICOMRSA (Bit 10)                                   */
33926  #define R_FCACHE_FSAR_FACICOMRSA_Msk      (0x400UL) /*!< FACICOMRSA (Bitfield-Mask: 0x01)                      */
33927  #define R_FCACHE_FSAR_FACITRSA_Pos        (11UL)    /*!< FACITRSA (Bit 11)                                     */
33928  #define R_FCACHE_FSAR_FACITRSA_Msk        (0x800UL) /*!< FACITRSA (Bitfield-Mask: 0x01)                        */
33929 
33930 /* =========================================================================================================================== */
33931 /* ================                                          R_GLCDC                                          ================ */
33932 /* =========================================================================================================================== */
33933 
33934 /* =======================================================  GR1_CLUT0  ======================================================= */
33935  #define R_GLCDC_GR1_CLUT0_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
33936  #define R_GLCDC_GR1_CLUT0_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
33937  #define R_GLCDC_GR1_CLUT0_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
33938  #define R_GLCDC_GR1_CLUT0_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
33939  #define R_GLCDC_GR1_CLUT0_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
33940  #define R_GLCDC_GR1_CLUT0_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
33941  #define R_GLCDC_GR1_CLUT0_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
33942  #define R_GLCDC_GR1_CLUT0_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
33943 /* =======================================================  GR1_CLUT1  ======================================================= */
33944  #define R_GLCDC_GR1_CLUT1_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
33945  #define R_GLCDC_GR1_CLUT1_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
33946  #define R_GLCDC_GR1_CLUT1_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
33947  #define R_GLCDC_GR1_CLUT1_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
33948  #define R_GLCDC_GR1_CLUT1_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
33949  #define R_GLCDC_GR1_CLUT1_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
33950  #define R_GLCDC_GR1_CLUT1_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
33951  #define R_GLCDC_GR1_CLUT1_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
33952 /* =======================================================  GR2_CLUT0  ======================================================= */
33953  #define R_GLCDC_GR2_CLUT0_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
33954  #define R_GLCDC_GR2_CLUT0_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
33955  #define R_GLCDC_GR2_CLUT0_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
33956  #define R_GLCDC_GR2_CLUT0_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
33957  #define R_GLCDC_GR2_CLUT0_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
33958  #define R_GLCDC_GR2_CLUT0_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
33959  #define R_GLCDC_GR2_CLUT0_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
33960  #define R_GLCDC_GR2_CLUT0_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
33961 /* =======================================================  GR2_CLUT1  ======================================================= */
33962  #define R_GLCDC_GR2_CLUT1_A_Pos    (24UL)         /*!< A (Bit 24)                                            */
33963  #define R_GLCDC_GR2_CLUT1_A_Msk    (0xff000000UL) /*!< A (Bitfield-Mask: 0xff)                               */
33964  #define R_GLCDC_GR2_CLUT1_R_Pos    (16UL)         /*!< R (Bit 16)                                            */
33965  #define R_GLCDC_GR2_CLUT1_R_Msk    (0xff0000UL)   /*!< R (Bitfield-Mask: 0xff)                               */
33966  #define R_GLCDC_GR2_CLUT1_G_Pos    (8UL)          /*!< G (Bit 8)                                             */
33967  #define R_GLCDC_GR2_CLUT1_G_Msk    (0xff00UL)     /*!< G (Bitfield-Mask: 0xff)                               */
33968  #define R_GLCDC_GR2_CLUT1_B_Pos    (0UL)          /*!< B (Bit 0)                                             */
33969  #define R_GLCDC_GR2_CLUT1_B_Msk    (0xffUL)       /*!< B (Bitfield-Mask: 0xff)                               */
33970 
33971 /* =========================================================================================================================== */
33972 /* ================                                          R_GPT0                                           ================ */
33973 /* =========================================================================================================================== */
33974 
33975 /* =========================================================  GTWP  ========================================================== */
33976  #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
33977  #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
33978  #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
33979  #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
33980  #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
33981  #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
33982  #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
33983  #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
33984  #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
33985  #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
33986  #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
33987  #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
33988 /* =========================================================  GTSTR  ========================================================= */
33989  #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
33990  #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
33991 /* =========================================================  GTSTP  ========================================================= */
33992  #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
33993  #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
33994 /* =========================================================  GTCLR  ========================================================= */
33995  #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
33996  #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
33997 /* =========================================================  GTSSR  ========================================================= */
33998  #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
33999  #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
34000  #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
34001  #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
34002  #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
34003  #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
34004  #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
34005  #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
34006  #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
34007  #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
34008  #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
34009  #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
34010  #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
34011  #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
34012  #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
34013  #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
34014  #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
34015  #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
34016  #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
34017  #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
34018  #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
34019  #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
34020  #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
34021  #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
34022 /* =========================================================  GTPSR  ========================================================= */
34023  #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
34024  #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
34025  #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
34026  #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
34027  #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
34028  #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
34029  #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
34030  #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
34031  #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
34032  #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
34033  #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
34034  #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
34035  #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
34036  #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
34037  #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
34038  #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
34039  #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
34040  #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
34041  #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
34042  #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
34043  #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
34044  #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
34045  #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
34046  #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
34047 /* =========================================================  GTCSR  ========================================================= */
34048  #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
34049  #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
34050  #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
34051  #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
34052  #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
34053  #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
34054  #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
34055  #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
34056  #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
34057  #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
34058  #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
34059  #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
34060  #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
34061  #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
34062  #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
34063  #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
34064  #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
34065  #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
34066  #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
34067  #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
34068  #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
34069  #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
34070  #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
34071  #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
34072  #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
34073  #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
34074  #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
34075  #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
34076 /* ========================================================  GTUPSR  ========================================================= */
34077  #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
34078  #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
34079  #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
34080  #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
34081  #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
34082  #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
34083  #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
34084  #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
34085  #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
34086  #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
34087  #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
34088  #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
34089  #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
34090  #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
34091  #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
34092  #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
34093  #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
34094  #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
34095  #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
34096  #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
34097  #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
34098  #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
34099  #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
34100  #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
34101 /* ========================================================  GTDNSR  ========================================================= */
34102  #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
34103  #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
34104  #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
34105  #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
34106  #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
34107  #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
34108  #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
34109  #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
34110  #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
34111  #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
34112  #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
34113  #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
34114  #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
34115  #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
34116  #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
34117  #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
34118  #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
34119  #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
34120  #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
34121  #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
34122  #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
34123  #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
34124  #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
34125  #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
34126 /* ========================================================  GTICASR  ======================================================== */
34127  #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
34128  #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
34129  #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
34130  #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
34131  #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
34132  #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
34133  #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
34134  #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
34135  #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
34136  #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
34137  #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
34138  #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
34139  #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
34140  #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
34141  #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
34142  #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
34143  #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
34144  #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
34145  #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
34146  #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
34147  #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
34148  #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
34149 /* ========================================================  GTICBSR  ======================================================== */
34150  #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
34151  #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
34152  #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
34153  #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
34154  #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
34155  #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
34156  #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
34157  #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
34158  #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
34159  #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
34160  #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
34161  #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
34162  #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
34163  #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
34164  #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
34165  #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
34166  #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
34167  #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
34168  #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
34169  #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
34170  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
34171  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
34172 /* =========================================================  GTCR  ========================================================== */
34173  #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
34174  #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
34175  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
34176  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
34177  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
34178  #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
34179  #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
34180  #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
34181  #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
34182  #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
34183  #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
34184  #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
34185  #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
34186  #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
34187  #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
34188  #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
34189  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
34190  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
34191 /* =======================================================  GTUDDTYC  ======================================================== */
34192  #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
34193  #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
34194  #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
34195  #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
34196  #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
34197  #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
34198  #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
34199  #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
34200  #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
34201  #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
34202  #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
34203  #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
34204  #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
34205  #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
34206  #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
34207  #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
34208 /* =========================================================  GTIOR  ========================================================= */
34209  #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
34210  #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
34211  #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
34212  #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
34213  #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
34214  #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
34215  #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
34216  #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
34217  #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
34218  #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
34219  #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
34220  #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
34221  #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
34222  #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
34223  #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
34224  #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
34225  #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
34226  #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
34227  #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
34228  #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
34229  #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
34230  #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
34231  #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
34232  #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
34233  #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
34234  #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
34235  #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
34236  #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
34237  #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
34238  #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
34239  #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
34240  #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
34241  #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
34242  #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
34243  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
34244  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
34245 /* ========================================================  GTINTAD  ======================================================== */
34246  #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
34247  #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
34248  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
34249  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
34250  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
34251  #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
34252  #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
34253  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
34254  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
34255  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
34256  #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
34257  #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
34258  #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
34259  #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
34260  #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
34261  #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
34262  #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
34263  #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
34264  #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
34265  #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
34266 /* =========================================================  GTST  ========================================================== */
34267  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
34268  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
34269  #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
34270  #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
34271  #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
34272  #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
34273  #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
34274  #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
34275  #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
34276  #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
34277  #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
34278  #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
34279  #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
34280  #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
34281  #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
34282  #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
34283  #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
34284  #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
34285  #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
34286  #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
34287  #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
34288  #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
34289  #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
34290  #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
34291  #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
34292  #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
34293  #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
34294  #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
34295  #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
34296  #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
34297  #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
34298  #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
34299  #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
34300  #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
34301  #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
34302  #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
34303  #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
34304  #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
34305 /* =========================================================  GTBER  ========================================================= */
34306  #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
34307  #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
34308  #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
34309  #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
34310  #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
34311  #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
34312  #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
34313  #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
34314  #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
34315  #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
34316  #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
34317  #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
34318  #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
34319  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
34320  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
34321  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
34322  #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
34323  #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
34324  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
34325  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
34326  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
34327  #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
34328  #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
34329  #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
34330  #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
34331  #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
34332 /* =========================================================  GTITC  ========================================================= */
34333  #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
34334  #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
34335  #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
34336  #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
34337  #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
34338  #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
34339  #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
34340  #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
34341  #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
34342  #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
34343  #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
34344  #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
34345  #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
34346  #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
34347  #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
34348  #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
34349  #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
34350  #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
34351  #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
34352  #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
34353 /* =========================================================  GTCNT  ========================================================= */
34354  #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
34355  #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
34356 /* =========================================================  GTCCR  ========================================================= */
34357  #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
34358  #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
34359 /* =========================================================  GTPR  ========================================================== */
34360  #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
34361  #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
34362 /* =========================================================  GTPBR  ========================================================= */
34363  #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
34364  #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
34365 /* ========================================================  GTPDBR  ========================================================= */
34366  #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
34367  #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
34368 /* ========================================================  GTADTRA  ======================================================== */
34369  #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
34370  #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
34371 /* ========================================================  GTADTRB  ======================================================== */
34372  #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
34373  #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
34374 /* =======================================================  GTADTBRA  ======================================================== */
34375  #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
34376  #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
34377 /* =======================================================  GTADTBRB  ======================================================== */
34378  #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
34379  #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
34380 /* =======================================================  GTADTDBRA  ======================================================= */
34381  #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
34382  #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
34383 /* =======================================================  GTADTDBRB  ======================================================= */
34384  #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
34385  #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
34386 /* ========================================================  GTDTCR  ========================================================= */
34387  #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
34388  #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
34389  #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
34390  #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
34391  #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
34392  #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
34393  #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
34394  #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
34395 /* =========================================================  GTDVU  ========================================================= */
34396  #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
34397  #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
34398 /* =========================================================  GTDVD  ========================================================= */
34399  #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
34400  #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
34401 /* =========================================================  GTDBU  ========================================================= */
34402  #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
34403  #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
34404 /* =========================================================  GTDBD  ========================================================= */
34405  #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
34406  #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
34407 /* =========================================================  GTSOS  ========================================================= */
34408  #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
34409  #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
34410 /* ========================================================  GTSOTR  ========================================================= */
34411  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
34412  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
34413 /* ========================================================  GTADSMR  ======================================================== */
34414  #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
34415  #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
34416  #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
34417  #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
34418  #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
34419  #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
34420  #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
34421  #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
34422 /* ========================================================  GTEITC  ========================================================= */
34423  #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
34424  #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
34425  #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
34426  #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
34427  #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
34428  #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
34429  #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
34430  #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
34431  #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
34432  #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
34433  #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
34434  #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
34435  #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
34436  #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
34437 /* =======================================================  GTEITLI1  ======================================================== */
34438  #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
34439  #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
34440  #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
34441  #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
34442  #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
34443  #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
34444  #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
34445  #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
34446  #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
34447  #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
34448  #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
34449  #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
34450  #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
34451  #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
34452  #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
34453  #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
34454 /* =======================================================  GTEITLI2  ======================================================== */
34455  #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
34456  #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
34457  #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
34458  #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
34459 /* ========================================================  GTEITLB  ======================================================== */
34460  #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
34461  #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
34462  #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
34463  #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
34464  #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
34465  #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
34466  #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
34467  #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
34468  #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
34469  #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
34470  #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
34471  #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
34472  #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
34473  #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
34474 /* ========================================================  GTICLF  ========================================================= */
34475  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
34476  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
34477  #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
34478  #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
34479  #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
34480  #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
34481  #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
34482  #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
34483 /* =========================================================  GTPC  ========================================================== */
34484  #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
34485  #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
34486  #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
34487  #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
34488  #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
34489  #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
34490 /* ========================================================  GTSECSR  ======================================================== */
34491  #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
34492  #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
34493  #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
34494  #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
34495  #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
34496  #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
34497  #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
34498  #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
34499  #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
34500  #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
34501  #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
34502  #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
34503  #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
34504  #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
34505  #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
34506  #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
34507  #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
34508  #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
34509  #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
34510  #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
34511 /* ========================================================  GTSECR  ========================================================= */
34512  #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
34513  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
34514  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
34515  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
34516  #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
34517  #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
34518  #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
34519  #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
34520  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
34521  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
34522  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
34523  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
34524  #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
34525  #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
34526  #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
34527  #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
34528  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
34529  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
34530  #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
34531  #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
34532  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
34533  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
34534  #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
34535  #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
34536 /* ========================================================  GTBER2  ========================================================= */
34537  #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
34538  #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
34539  #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
34540  #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
34541  #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
34542  #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
34543  #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
34544  #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
34545  #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
34546  #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
34547  #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
34548  #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
34549  #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
34550  #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
34551  #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
34552  #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
34553  #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
34554  #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
34555  #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
34556  #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
34557  #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
34558  #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
34559  #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
34560  #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
34561  #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
34562  #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
34563  #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
34564  #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
34565  #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
34566  #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
34567  #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
34568  #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
34569  #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
34570  #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
34571  #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
34572  #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
34573  #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
34574  #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
34575  #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
34576  #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
34577 /* ========================================================  GTOLBR  ========================================================= */
34578  #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
34579  #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
34580  #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
34581  #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
34582 /* ========================================================  GTICCR  ========================================================= */
34583  #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
34584  #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
34585  #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
34586  #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
34587  #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
34588  #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
34589  #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
34590  #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
34591  #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
34592  #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
34593  #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
34594  #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
34595  #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
34596  #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
34597  #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
34598  #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
34599  #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
34600  #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
34601  #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
34602  #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
34603  #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
34604  #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
34605  #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
34606  #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
34607  #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
34608  #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
34609  #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
34610  #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
34611  #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
34612  #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
34613  #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
34614  #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
34615  #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
34616  #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
34617  #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
34618  #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
34619  #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
34620  #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
34621  #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
34622  #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
34623 
34624 /* =========================================================================================================================== */
34625 /* ================                                         R_GPT_OPS                                         ================ */
34626 /* =========================================================================================================================== */
34627 
34628 /* =========================================================  OPSCR  ========================================================= */
34629  #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
34630  #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
34631  #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
34632  #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
34633  #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
34634  #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
34635  #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
34636  #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
34637  #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
34638  #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
34639  #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
34640  #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
34641  #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
34642  #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
34643  #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
34644  #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
34645  #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
34646  #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
34647  #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
34648  #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
34649  #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
34650  #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
34651  #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
34652  #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
34653  #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
34654  #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
34655  #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
34656  #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
34657  #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
34658  #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
34659  #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
34660  #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
34661  #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
34662  #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
34663 
34664 /* =========================================================================================================================== */
34665 /* ================                                        R_GPT_POEG0                                        ================ */
34666 /* =========================================================================================================================== */
34667 
34668 /* =========================================================  POEGG  ========================================================= */
34669  #define R_GPT_POEG0_POEGG_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
34670  #define R_GPT_POEG0_POEGG_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
34671  #define R_GPT_POEG0_POEGG_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
34672  #define R_GPT_POEG0_POEGG_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
34673  #define R_GPT_POEG0_POEGG_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
34674  #define R_GPT_POEG0_POEGG_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
34675  #define R_GPT_POEG0_POEGG_DERRE_Pos      (26UL)         /*!< DERRE (Bit 26)                                        */
34676  #define R_GPT_POEG0_POEGG_DERRE_Msk      (0x4000000UL)  /*!< DERRE (Bitfield-Mask: 0x01)                           */
34677  #define R_GPT_POEG0_POEGG_DERRST_Pos     (24UL)         /*!< DERRST (Bit 24)                                       */
34678  #define R_GPT_POEG0_POEGG_DERRST_Msk     (0x1000000UL)  /*!< DERRST (Bitfield-Mask: 0x01)                          */
34679  #define R_GPT_POEG0_POEGG_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
34680  #define R_GPT_POEG0_POEGG_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
34681  #define R_GPT_POEG0_POEGG_CDRE_Pos       (8UL)          /*!< CDRE (Bit 8)                                          */
34682  #define R_GPT_POEG0_POEGG_CDRE_Msk       (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
34683  #define R_GPT_POEG0_POEGG_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
34684  #define R_GPT_POEG0_POEGG_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
34685  #define R_GPT_POEG0_POEGG_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
34686  #define R_GPT_POEG0_POEGG_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
34687  #define R_GPT_POEG0_POEGG_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
34688  #define R_GPT_POEG0_POEGG_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
34689  #define R_GPT_POEG0_POEGG_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
34690  #define R_GPT_POEG0_POEGG_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
34691  #define R_GPT_POEG0_POEGG_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
34692  #define R_GPT_POEG0_POEGG_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
34693  #define R_GPT_POEG0_POEGG_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
34694  #define R_GPT_POEG0_POEGG_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
34695  #define R_GPT_POEG0_POEGG_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
34696  #define R_GPT_POEG0_POEGG_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
34697 /* ========================================================  GTONCWP  ======================================================== */
34698  #define R_GPT_POEG0_GTONCWP_WP_Pos       (0UL)          /*!< WP (Bit 0)                                            */
34699  #define R_GPT_POEG0_GTONCWP_WP_Msk       (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
34700  #define R_GPT_POEG0_GTONCWP_PRKEY_Pos    (8UL)          /*!< PRKEY (Bit 8)                                         */
34701  #define R_GPT_POEG0_GTONCWP_PRKEY_Msk    (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
34702 /* ========================================================  GTONCCR  ======================================================== */
34703  #define R_GPT_POEG0_GTONCCR_NE_Pos       (0UL)          /*!< NE (Bit 0)                                            */
34704  #define R_GPT_POEG0_GTONCCR_NE_Msk       (0x1UL)        /*!< NE (Bitfield-Mask: 0x01)                              */
34705  #define R_GPT_POEG0_GTONCCR_NFS_Pos      (4UL)          /*!< NFS (Bit 4)                                           */
34706  #define R_GPT_POEG0_GTONCCR_NFS_Msk      (0xf0UL)       /*!< NFS (Bitfield-Mask: 0x0f)                             */
34707  #define R_GPT_POEG0_GTONCCR_NFV_Pos      (8UL)          /*!< NFV (Bit 8)                                           */
34708  #define R_GPT_POEG0_GTONCCR_NFV_Msk      (0x100UL)      /*!< NFV (Bitfield-Mask: 0x01)                             */
34709 
34710 /* =========================================================================================================================== */
34711 /* ================                                           R_ICU                                           ================ */
34712 /* =========================================================================================================================== */
34713 
34714 /* =========================================================  IRQCR  ========================================================= */
34715  #define R_ICU_IRQCR_FLTEN_Pos            (7UL)          /*!< FLTEN (Bit 7)                                         */
34716  #define R_ICU_IRQCR_FLTEN_Msk            (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
34717  #define R_ICU_IRQCR_FCLKSEL_Pos          (4UL)          /*!< FCLKSEL (Bit 4)                                       */
34718  #define R_ICU_IRQCR_FCLKSEL_Msk          (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
34719  #define R_ICU_IRQCR_IRQMD_Pos            (0UL)          /*!< IRQMD (Bit 0)                                         */
34720  #define R_ICU_IRQCR_IRQMD_Msk            (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
34721 /* =========================================================  NMICR  ========================================================= */
34722  #define R_ICU_NMICR_NMIMD_Pos            (0UL)          /*!< NMIMD (Bit 0)                                         */
34723  #define R_ICU_NMICR_NMIMD_Msk            (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
34724  #define R_ICU_NMICR_NFCLKSEL_Pos         (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
34725  #define R_ICU_NMICR_NFCLKSEL_Msk         (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
34726  #define R_ICU_NMICR_NFLTEN_Pos           (7UL)          /*!< NFLTEN (Bit 7)                                        */
34727  #define R_ICU_NMICR_NFLTEN_Msk           (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
34728 /* ========================================================  SWIRQ_S  ======================================================== */
34729  #define R_ICU_SWIRQ_S_SWIRQS_Pos         (0UL)          /*!< SWIRQS (Bit 0)                                        */
34730  #define R_ICU_SWIRQ_S_SWIRQS_Msk         (0x1UL)        /*!< SWIRQS (Bitfield-Mask: 0x01)                          */
34731 /* =======================================================  SWIRQ_NS  ======================================================== */
34732  #define R_ICU_SWIRQ_NS_SWIRQNS_Pos       (0UL)          /*!< SWIRQNS (Bit 0)                                       */
34733  #define R_ICU_SWIRQ_NS_SWIRQNS_Msk       (0x1UL)        /*!< SWIRQNS (Bitfield-Mask: 0x01)                         */
34734 /* ========================================================  IENMIER  ======================================================== */
34735  #define R_ICU_IENMIER_CMEN_Pos           (0UL)          /*!< CMEN (Bit 0)                                          */
34736  #define R_ICU_IENMIER_CMEN_Msk           (0x1UL)        /*!< CMEN (Bitfield-Mask: 0x01)                            */
34737  #define R_ICU_IENMIER_LMEN_Pos           (1UL)          /*!< LMEN (Bit 1)                                          */
34738  #define R_ICU_IENMIER_LMEN_Msk           (0x2UL)        /*!< LMEN (Bitfield-Mask: 0x01)                            */
34739  #define R_ICU_IENMIER_BUSEN_Pos          (2UL)          /*!< BUSEN (Bit 2)                                         */
34740  #define R_ICU_IENMIER_BUSEN_Msk          (0x4UL)        /*!< BUSEN (Bitfield-Mask: 0x01)                           */
34741 /* =========================================================  NMIER  ========================================================= */
34742  #define R_ICU_NMIER_IWDTEN_Pos           (0UL)          /*!< IWDTEN (Bit 0)                                        */
34743  #define R_ICU_NMIER_IWDTEN_Msk           (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
34744  #define R_ICU_NMIER_WDTEN_Pos            (1UL)          /*!< WDTEN (Bit 1)                                         */
34745  #define R_ICU_NMIER_WDTEN_Msk            (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
34746  #define R_ICU_NMIER_LVD1EN_Pos           (2UL)          /*!< LVD1EN (Bit 2)                                        */
34747  #define R_ICU_NMIER_LVD1EN_Msk           (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
34748  #define R_ICU_NMIER_LVD2EN_Pos           (3UL)          /*!< LVD2EN (Bit 3)                                        */
34749  #define R_ICU_NMIER_LVD2EN_Msk           (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
34750  #define R_ICU_NMIER_OSTEN_Pos            (6UL)          /*!< OSTEN (Bit 6)                                         */
34751  #define R_ICU_NMIER_OSTEN_Msk            (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
34752  #define R_ICU_NMIER_NMIEN_Pos            (7UL)          /*!< NMIEN (Bit 7)                                         */
34753  #define R_ICU_NMIER_NMIEN_Msk            (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
34754  #define R_ICU_NMIER_BUSEN_Pos            (12UL)         /*!< BUSEN (Bit 12)                                        */
34755  #define R_ICU_NMIER_BUSEN_Msk            (0x1000UL)     /*!< BUSEN (Bitfield-Mask: 0x01)                           */
34756  #define R_ICU_NMIER_CMEN_Pos             (13UL)         /*!< CMEN (Bit 13)                                         */
34757  #define R_ICU_NMIER_CMEN_Msk             (0x2000UL)     /*!< CMEN (Bitfield-Mask: 0x01)                            */
34758  #define R_ICU_NMIER_LUEN_Pos             (15UL)         /*!< LUEN (Bit 15)                                         */
34759  #define R_ICU_NMIER_LUEN_Msk             (0x8000UL)     /*!< LUEN (Bitfield-Mask: 0x01)                            */
34760 /* ========================================================  NMICLR  ========================================================= */
34761  #define R_ICU_NMICLR_IWDTCLR_Pos         (0UL)          /*!< IWDTCLR (Bit 0)                                       */
34762  #define R_ICU_NMICLR_IWDTCLR_Msk         (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
34763  #define R_ICU_NMICLR_WDTCLR_Pos          (1UL)          /*!< WDTCLR (Bit 1)                                        */
34764  #define R_ICU_NMICLR_WDTCLR_Msk          (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
34765  #define R_ICU_NMICLR_LVD1CLR_Pos         (2UL)          /*!< LVD1CLR (Bit 2)                                       */
34766  #define R_ICU_NMICLR_LVD1CLR_Msk         (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
34767  #define R_ICU_NMICLR_LVD2CLR_Pos         (3UL)          /*!< LVD2CLR (Bit 3)                                       */
34768  #define R_ICU_NMICLR_LVD2CLR_Msk         (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
34769  #define R_ICU_NMICLR_OSTCLR_Pos          (6UL)          /*!< OSTCLR (Bit 6)                                        */
34770  #define R_ICU_NMICLR_OSTCLR_Msk          (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
34771  #define R_ICU_NMICLR_NMICLR_Pos          (7UL)          /*!< NMICLR (Bit 7)                                        */
34772  #define R_ICU_NMICLR_NMICLR_Msk          (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
34773  #define R_ICU_NMICLR_BUSCLR_Pos          (12UL)         /*!< BUSCLR (Bit 12)                                       */
34774  #define R_ICU_NMICLR_BUSCLR_Msk          (0x1000UL)     /*!< BUSCLR (Bitfield-Mask: 0x01)                          */
34775  #define R_ICU_NMICLR_CMCLR_Pos           (13UL)         /*!< CMCLR (Bit 13)                                        */
34776  #define R_ICU_NMICLR_CMCLR_Msk           (0x2000UL)     /*!< CMCLR (Bitfield-Mask: 0x01)                           */
34777  #define R_ICU_NMICLR_LUCLR_Pos           (15UL)         /*!< LUCLR (Bit 15)                                        */
34778  #define R_ICU_NMICLR_LUCLR_Msk           (0x8000UL)     /*!< LUCLR (Bitfield-Mask: 0x01)                           */
34779 /* =========================================================  NMISR  ========================================================= */
34780  #define R_ICU_NMISR_IWDTST_Pos           (0UL)          /*!< IWDTST (Bit 0)                                        */
34781  #define R_ICU_NMISR_IWDTST_Msk           (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
34782  #define R_ICU_NMISR_WDTST_Pos            (1UL)          /*!< WDTST (Bit 1)                                         */
34783  #define R_ICU_NMISR_WDTST_Msk            (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
34784  #define R_ICU_NMISR_LVD1ST_Pos           (2UL)          /*!< LVD1ST (Bit 2)                                        */
34785  #define R_ICU_NMISR_LVD1ST_Msk           (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
34786  #define R_ICU_NMISR_LVD2ST_Pos           (3UL)          /*!< LVD2ST (Bit 3)                                        */
34787  #define R_ICU_NMISR_LVD2ST_Msk           (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
34788  #define R_ICU_NMISR_OSTST_Pos            (6UL)          /*!< OSTST (Bit 6)                                         */
34789  #define R_ICU_NMISR_OSTST_Msk            (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
34790  #define R_ICU_NMISR_NMIST_Pos            (7UL)          /*!< NMIST (Bit 7)                                         */
34791  #define R_ICU_NMISR_NMIST_Msk            (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
34792  #define R_ICU_NMISR_BUSST_Pos            (12UL)         /*!< BUSST (Bit 12)                                        */
34793  #define R_ICU_NMISR_BUSST_Msk            (0x1000UL)     /*!< BUSST (Bitfield-Mask: 0x01)                           */
34794  #define R_ICU_NMISR_CMST_Pos             (13UL)         /*!< CMST (Bit 13)                                         */
34795  #define R_ICU_NMISR_CMST_Msk             (0x2000UL)     /*!< CMST (Bitfield-Mask: 0x01)                            */
34796  #define R_ICU_NMISR_LUST_Pos             (15UL)         /*!< LUST (Bit 15)                                         */
34797  #define R_ICU_NMISR_LUST_Msk             (0x8000UL)     /*!< LUST (Bitfield-Mask: 0x01)                            */
34798 /* =========================================================  WUPEN  ========================================================= */
34799  #define R_ICU_WUPEN_IRQWUPEN0_Pos        (0UL)          /*!< IRQWUPEN0 (Bit 0)                                     */
34800  #define R_ICU_WUPEN_IRQWUPEN0_Msk        (0x1UL)        /*!< IRQWUPEN0 (Bitfield-Mask: 0x01)                       */
34801  #define R_ICU_WUPEN_IRQWUPEN1_Pos        (1UL)          /*!< IRQWUPEN1 (Bit 1)                                     */
34802  #define R_ICU_WUPEN_IRQWUPEN1_Msk        (0x2UL)        /*!< IRQWUPEN1 (Bitfield-Mask: 0x01)                       */
34803  #define R_ICU_WUPEN_IRQWUPEN2_Pos        (2UL)          /*!< IRQWUPEN2 (Bit 2)                                     */
34804  #define R_ICU_WUPEN_IRQWUPEN2_Msk        (0x4UL)        /*!< IRQWUPEN2 (Bitfield-Mask: 0x01)                       */
34805  #define R_ICU_WUPEN_IRQWUPEN3_Pos        (3UL)          /*!< IRQWUPEN3 (Bit 3)                                     */
34806  #define R_ICU_WUPEN_IRQWUPEN3_Msk        (0x8UL)        /*!< IRQWUPEN3 (Bitfield-Mask: 0x01)                       */
34807  #define R_ICU_WUPEN_IRQWUPEN4_Pos        (4UL)          /*!< IRQWUPEN4 (Bit 4)                                     */
34808  #define R_ICU_WUPEN_IRQWUPEN4_Msk        (0x10UL)       /*!< IRQWUPEN4 (Bitfield-Mask: 0x01)                       */
34809  #define R_ICU_WUPEN_IRQWUPEN5_Pos        (5UL)          /*!< IRQWUPEN5 (Bit 5)                                     */
34810  #define R_ICU_WUPEN_IRQWUPEN5_Msk        (0x20UL)       /*!< IRQWUPEN5 (Bitfield-Mask: 0x01)                       */
34811  #define R_ICU_WUPEN_IRQWUPEN6_Pos        (6UL)          /*!< IRQWUPEN6 (Bit 6)                                     */
34812  #define R_ICU_WUPEN_IRQWUPEN6_Msk        (0x40UL)       /*!< IRQWUPEN6 (Bitfield-Mask: 0x01)                       */
34813  #define R_ICU_WUPEN_IRQWUPEN7_Pos        (7UL)          /*!< IRQWUPEN7 (Bit 7)                                     */
34814  #define R_ICU_WUPEN_IRQWUPEN7_Msk        (0x80UL)       /*!< IRQWUPEN7 (Bitfield-Mask: 0x01)                       */
34815  #define R_ICU_WUPEN_IRQWUPEN8_Pos        (8UL)          /*!< IRQWUPEN8 (Bit 8)                                     */
34816  #define R_ICU_WUPEN_IRQWUPEN8_Msk        (0x100UL)      /*!< IRQWUPEN8 (Bitfield-Mask: 0x01)                       */
34817  #define R_ICU_WUPEN_IRQWUPEN9_Pos        (9UL)          /*!< IRQWUPEN9 (Bit 9)                                     */
34818  #define R_ICU_WUPEN_IRQWUPEN9_Msk        (0x200UL)      /*!< IRQWUPEN9 (Bitfield-Mask: 0x01)                       */
34819  #define R_ICU_WUPEN_IRQWUPEN10_Pos       (10UL)         /*!< IRQWUPEN10 (Bit 10)                                   */
34820  #define R_ICU_WUPEN_IRQWUPEN10_Msk       (0x400UL)      /*!< IRQWUPEN10 (Bitfield-Mask: 0x01)                      */
34821  #define R_ICU_WUPEN_IRQWUPEN11_Pos       (11UL)         /*!< IRQWUPEN11 (Bit 11)                                   */
34822  #define R_ICU_WUPEN_IRQWUPEN11_Msk       (0x800UL)      /*!< IRQWUPEN11 (Bitfield-Mask: 0x01)                      */
34823  #define R_ICU_WUPEN_IRQWUPEN12_Pos       (12UL)         /*!< IRQWUPEN12 (Bit 12)                                   */
34824  #define R_ICU_WUPEN_IRQWUPEN12_Msk       (0x1000UL)     /*!< IRQWUPEN12 (Bitfield-Mask: 0x01)                      */
34825  #define R_ICU_WUPEN_IRQWUPEN13_Pos       (13UL)         /*!< IRQWUPEN13 (Bit 13)                                   */
34826  #define R_ICU_WUPEN_IRQWUPEN13_Msk       (0x2000UL)     /*!< IRQWUPEN13 (Bitfield-Mask: 0x01)                      */
34827  #define R_ICU_WUPEN_IRQWUPEN14_Pos       (14UL)         /*!< IRQWUPEN14 (Bit 14)                                   */
34828  #define R_ICU_WUPEN_IRQWUPEN14_Msk       (0x4000UL)     /*!< IRQWUPEN14 (Bitfield-Mask: 0x01)                      */
34829  #define R_ICU_WUPEN_IRQWUPEN15_Pos       (15UL)         /*!< IRQWUPEN15 (Bit 15)                                   */
34830  #define R_ICU_WUPEN_IRQWUPEN15_Msk       (0x8000UL)     /*!< IRQWUPEN15 (Bitfield-Mask: 0x01)                      */
34831  #define R_ICU_WUPEN_IWDTWUPEN_Pos        (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
34832  #define R_ICU_WUPEN_IWDTWUPEN_Msk        (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
34833  #define R_ICU_WUPEN_LVD1WUPEN_Pos        (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
34834  #define R_ICU_WUPEN_LVD1WUPEN_Msk        (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
34835  #define R_ICU_WUPEN_LVD2WUPEN_Pos        (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
34836  #define R_ICU_WUPEN_LVD2WUPEN_Msk        (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
34837  #define R_ICU_WUPEN_VBATTWUPEN_Pos       (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
34838  #define R_ICU_WUPEN_VBATTWUPEN_Msk       (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
34839  #define R_ICU_WUPEN_RTCALMWUPEN_Pos      (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
34840  #define R_ICU_WUPEN_RTCALMWUPEN_Msk      (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
34841  #define R_ICU_WUPEN_RTCPRDWUPEN_Pos      (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
34842  #define R_ICU_WUPEN_RTCPRDWUPEN_Msk      (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
34843  #define R_ICU_WUPEN_USBHSWUPEN_Pos       (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
34844  #define R_ICU_WUPEN_USBHSWUPEN_Msk       (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
34845  #define R_ICU_WUPEN_USBFSWUPEN_Pos       (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
34846  #define R_ICU_WUPEN_USBFSWUPEN_Msk       (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
34847  #define R_ICU_WUPEN_AGT1UDWUPEN_Pos      (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
34848  #define R_ICU_WUPEN_AGT1UDWUPEN_Msk      (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
34849  #define R_ICU_WUPEN_AGT1CAWUPEN_Pos      (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
34850  #define R_ICU_WUPEN_AGT1CAWUPEN_Msk      (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
34851  #define R_ICU_WUPEN_AGT1CBWUPEN_Pos      (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
34852  #define R_ICU_WUPEN_AGT1CBWUPEN_Msk      (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
34853  #define R_ICU_WUPEN_RIIC0WUPEN_Pos       (31UL)         /*!< RIIC0WUPEN (Bit 31)                                   */
34854  #define R_ICU_WUPEN_RIIC0WUPEN_Msk       (0x80000000UL) /*!< RIIC0WUPEN (Bitfield-Mask: 0x01)                      */
34855 /* ========================================================  WUPEN1  ========================================================= */
34856  #define R_ICU_WUPEN1_COMPHS0WUPEN_Pos    (3UL)          /*!< COMPHS0WUPEN (Bit 3)                                  */
34857  #define R_ICU_WUPEN1_COMPHS0WUPEN_Msk    (0x8UL)        /*!< COMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
34858  #define R_ICU_WUPEN1_ULP0UWUPEN_Pos      (8UL)          /*!< ULP0UWUPEN (Bit 8)                                    */
34859  #define R_ICU_WUPEN1_ULP0UWUPEN_Msk      (0x100UL)      /*!< ULP0UWUPEN (Bitfield-Mask: 0x01)                      */
34860  #define R_ICU_WUPEN1_ULP0AWUPEN_Pos      (9UL)          /*!< ULP0AWUPEN (Bit 9)                                    */
34861  #define R_ICU_WUPEN1_ULP0AWUPEN_Msk      (0x200UL)      /*!< ULP0AWUPEN (Bitfield-Mask: 0x01)                      */
34862  #define R_ICU_WUPEN1_ULP0BWUPEN_Pos      (10UL)         /*!< ULP0BWUPEN (Bit 10)                                   */
34863  #define R_ICU_WUPEN1_ULP0BWUPEN_Msk      (0x400UL)      /*!< ULP0BWUPEN (Bitfield-Mask: 0x01)                      */
34864  #define R_ICU_WUPEN1_I3CWUPEN_Pos        (11UL)         /*!< I3CWUPEN (Bit 11)                                     */
34865  #define R_ICU_WUPEN1_I3CWUPEN_Msk        (0x800UL)      /*!< I3CWUPEN (Bitfield-Mask: 0x01)                        */
34866  #define R_ICU_WUPEN1_ULP1UWUPEN_Pos      (12UL)         /*!< ULP1UWUPEN (Bit 12)                                   */
34867  #define R_ICU_WUPEN1_ULP1UWUPEN_Msk      (0x1000UL)     /*!< ULP1UWUPEN (Bitfield-Mask: 0x01)                      */
34868  #define R_ICU_WUPEN1_ULP1AWUPEN_Pos      (13UL)         /*!< ULP1AWUPEN (Bit 13)                                   */
34869  #define R_ICU_WUPEN1_ULP1AWUPEN_Msk      (0x2000UL)     /*!< ULP1AWUPEN (Bitfield-Mask: 0x01)                      */
34870  #define R_ICU_WUPEN1_ULP1BWUPEN_Pos      (14UL)         /*!< ULP1BWUPEN (Bit 14)                                   */
34871  #define R_ICU_WUPEN1_ULP1BWUPEN_Msk      (0x4000UL)     /*!< ULP1BWUPEN (Bitfield-Mask: 0x01)                      */
34872 /* =========================================================  IELSR  ========================================================= */
34873  #define R_ICU_IELSR_DTCE_Pos             (24UL)         /*!< DTCE (Bit 24)                                         */
34874  #define R_ICU_IELSR_DTCE_Msk             (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
34875  #define R_ICU_IELSR_IR_Pos               (16UL)         /*!< IR (Bit 16)                                           */
34876  #define R_ICU_IELSR_IR_Msk               (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
34877  #define R_ICU_IELSR_IELS_Pos             (0UL)          /*!< IELS (Bit 0)                                          */
34878  #define R_ICU_IELSR_IELS_Msk             (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
34879 
34880 /* =========================================================================================================================== */
34881 /* ================                                          R_IIC0                                           ================ */
34882 /* =========================================================================================================================== */
34883 
34884 /* =========================================================  ICCR1  ========================================================= */
34885  #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
34886  #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
34887  #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
34888  #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
34889  #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
34890  #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
34891  #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
34892  #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
34893  #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
34894  #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
34895  #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
34896  #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
34897  #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
34898  #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
34899  #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
34900  #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
34901 /* =========================================================  ICCR2  ========================================================= */
34902  #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
34903  #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
34904  #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
34905  #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
34906  #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
34907  #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
34908  #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
34909  #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
34910  #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
34911  #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
34912  #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
34913  #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
34914 /* =========================================================  ICMR1  ========================================================= */
34915  #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
34916  #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
34917  #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
34918  #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
34919  #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
34920  #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
34921  #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
34922  #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
34923 /* =========================================================  ICMR2  ========================================================= */
34924  #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
34925  #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
34926  #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
34927  #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
34928  #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
34929  #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
34930  #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
34931  #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
34932  #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
34933  #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
34934 /* =========================================================  ICMR3  ========================================================= */
34935  #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
34936  #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
34937  #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
34938  #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
34939  #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
34940  #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
34941  #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
34942  #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
34943  #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
34944  #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
34945  #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
34946  #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
34947  #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
34948  #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
34949 /* =========================================================  ICFER  ========================================================= */
34950  #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
34951  #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
34952  #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
34953  #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
34954  #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
34955  #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
34956  #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
34957  #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
34958  #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
34959  #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
34960  #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
34961  #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
34962  #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
34963  #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
34964  #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
34965  #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
34966 /* =========================================================  ICSER  ========================================================= */
34967  #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
34968  #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
34969  #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
34970  #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
34971  #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
34972  #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
34973  #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
34974  #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
34975  #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
34976  #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
34977  #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
34978  #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
34979 /* =========================================================  ICIER  ========================================================= */
34980  #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
34981  #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
34982  #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
34983  #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
34984  #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
34985  #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
34986  #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
34987  #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
34988  #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
34989  #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
34990  #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
34991  #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
34992  #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
34993  #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
34994  #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
34995  #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
34996 /* =========================================================  ICSR1  ========================================================= */
34997  #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
34998  #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
34999  #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
35000  #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
35001  #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
35002  #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
35003  #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
35004  #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
35005  #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
35006  #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
35007  #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
35008  #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
35009 /* =========================================================  ICSR2  ========================================================= */
35010  #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
35011  #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
35012  #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
35013  #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
35014  #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
35015  #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
35016  #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
35017  #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
35018  #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
35019  #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
35020  #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
35021  #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
35022  #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
35023  #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
35024  #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
35025  #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
35026 /* =========================================================  ICBRL  ========================================================= */
35027  #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
35028  #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
35029 /* =========================================================  ICBRH  ========================================================= */
35030  #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
35031  #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
35032 /* =========================================================  ICDRT  ========================================================= */
35033  #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
35034  #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
35035 /* =========================================================  ICDRR  ========================================================= */
35036  #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
35037  #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
35038 /* =========================================================  ICWUR  ========================================================= */
35039  #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
35040  #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
35041  #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
35042  #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
35043  #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
35044  #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
35045  #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
35046  #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
35047  #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
35048  #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
35049 /* ========================================================  ICWUR2  ========================================================= */
35050  #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
35051  #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
35052  #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
35053  #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
35054  #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
35055  #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
35056 
35057 /* =========================================================================================================================== */
35058 /* ================                                          R_IWDT                                           ================ */
35059 /* =========================================================================================================================== */
35060 
35061 /* ========================================================  IWDTRR  ========================================================= */
35062  #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
35063  #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
35064 /* ========================================================  IWDTCR  ========================================================= */
35065  #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
35066  #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
35067  #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
35068  #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
35069  #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
35070  #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
35071  #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
35072  #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
35073 /* ========================================================  IWDTSR  ========================================================= */
35074  #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
35075  #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
35076  #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
35077  #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
35078  #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
35079  #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
35080 /* ========================================================  IWDTRCR  ======================================================== */
35081  #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
35082  #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
35083 /* =======================================================  IWDTCSTPR  ======================================================= */
35084  #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
35085  #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
35086 
35087 /* =========================================================================================================================== */
35088 /* ================                                          R_I3C0                                           ================ */
35089 /* =========================================================================================================================== */
35090 
35091 /* =========================================================  PRTS  ========================================================== */
35092  #define R_I3C0_PRTS_PRTMD_Pos          (0UL)          /*!< PRTMD (Bit 0)                                         */
35093  #define R_I3C0_PRTS_PRTMD_Msk          (0x1UL)        /*!< PRTMD (Bitfield-Mask: 0x01)                           */
35094 /* =========================================================  CECTL  ========================================================= */
35095  #define R_I3C0_CECTL_CLKE_Pos          (0UL)          /*!< CLKE (Bit 0)                                          */
35096  #define R_I3C0_CECTL_CLKE_Msk          (0x1UL)        /*!< CLKE (Bitfield-Mask: 0x01)                            */
35097 /* =========================================================  BCTL  ========================================================== */
35098  #define R_I3C0_BCTL_INCBA_Pos          (0UL)          /*!< INCBA (Bit 0)                                         */
35099  #define R_I3C0_BCTL_INCBA_Msk          (0x1UL)        /*!< INCBA (Bitfield-Mask: 0x01)                           */
35100  #define R_I3C0_BCTL_BMDS_Pos           (7UL)          /*!< BMDS (Bit 7)                                          */
35101  #define R_I3C0_BCTL_BMDS_Msk           (0x80UL)       /*!< BMDS (Bitfield-Mask: 0x01)                            */
35102  #define R_I3C0_BCTL_HJACKCTL_Pos       (8UL)          /*!< HJACKCTL (Bit 8)                                      */
35103  #define R_I3C0_BCTL_HJACKCTL_Msk       (0x100UL)      /*!< HJACKCTL (Bitfield-Mask: 0x01)                        */
35104  #define R_I3C0_BCTL_ABT_Pos            (29UL)         /*!< ABT (Bit 29)                                          */
35105  #define R_I3C0_BCTL_ABT_Msk            (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01)                             */
35106  #define R_I3C0_BCTL_RSM_Pos            (30UL)         /*!< RSM (Bit 30)                                          */
35107  #define R_I3C0_BCTL_RSM_Msk            (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01)                             */
35108  #define R_I3C0_BCTL_BUSE_Pos           (31UL)         /*!< BUSE (Bit 31)                                         */
35109  #define R_I3C0_BCTL_BUSE_Msk           (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01)                            */
35110 /* ========================================================  MSDVAD  ========================================================= */
35111  #define R_I3C0_MSDVAD_MDYAD_Pos        (16UL)         /*!< MDYAD (Bit 16)                                        */
35112  #define R_I3C0_MSDVAD_MDYAD_Msk        (0x7f0000UL)   /*!< MDYAD (Bitfield-Mask: 0x7f)                           */
35113  #define R_I3C0_MSDVAD_MDYADV_Pos       (31UL)         /*!< MDYADV (Bit 31)                                       */
35114  #define R_I3C0_MSDVAD_MDYADV_Msk       (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01)                          */
35115 /* ========================================================  RSTCTL  ========================================================= */
35116  #define R_I3C0_RSTCTL_RI3CRST_Pos      (0UL)          /*!< RI3CRST (Bit 0)                                       */
35117  #define R_I3C0_RSTCTL_RI3CRST_Msk      (0x1UL)        /*!< RI3CRST (Bitfield-Mask: 0x01)                         */
35118  #define R_I3C0_RSTCTL_CMDQRST_Pos      (1UL)          /*!< CMDQRST (Bit 1)                                       */
35119  #define R_I3C0_RSTCTL_CMDQRST_Msk      (0x2UL)        /*!< CMDQRST (Bitfield-Mask: 0x01)                         */
35120  #define R_I3C0_RSTCTL_RSPQRST_Pos      (2UL)          /*!< RSPQRST (Bit 2)                                       */
35121  #define R_I3C0_RSTCTL_RSPQRST_Msk      (0x4UL)        /*!< RSPQRST (Bitfield-Mask: 0x01)                         */
35122  #define R_I3C0_RSTCTL_TDBRST_Pos       (3UL)          /*!< TDBRST (Bit 3)                                        */
35123  #define R_I3C0_RSTCTL_TDBRST_Msk       (0x8UL)        /*!< TDBRST (Bitfield-Mask: 0x01)                          */
35124  #define R_I3C0_RSTCTL_RDBRST_Pos       (4UL)          /*!< RDBRST (Bit 4)                                        */
35125  #define R_I3C0_RSTCTL_RDBRST_Msk       (0x10UL)       /*!< RDBRST (Bitfield-Mask: 0x01)                          */
35126  #define R_I3C0_RSTCTL_IBIQRST_Pos      (5UL)          /*!< IBIQRST (Bit 5)                                       */
35127  #define R_I3C0_RSTCTL_IBIQRST_Msk      (0x20UL)       /*!< IBIQRST (Bitfield-Mask: 0x01)                         */
35128  #define R_I3C0_RSTCTL_RSQRST_Pos       (6UL)          /*!< RSQRST (Bit 6)                                        */
35129  #define R_I3C0_RSTCTL_RSQRST_Msk       (0x40UL)       /*!< RSQRST (Bitfield-Mask: 0x01)                          */
35130  #define R_I3C0_RSTCTL_INTLRST_Pos      (16UL)         /*!< INTLRST (Bit 16)                                      */
35131  #define R_I3C0_RSTCTL_INTLRST_Msk      (0x10000UL)    /*!< INTLRST (Bitfield-Mask: 0x01)                         */
35132 /* =========================================================  PRSST  ========================================================= */
35133  #define R_I3C0_PRSST_CRMS_Pos          (2UL)          /*!< CRMS (Bit 2)                                          */
35134  #define R_I3C0_PRSST_CRMS_Msk          (0x4UL)        /*!< CRMS (Bitfield-Mask: 0x01)                            */
35135  #define R_I3C0_PRSST_TRMD_Pos          (4UL)          /*!< TRMD (Bit 4)                                          */
35136  #define R_I3C0_PRSST_TRMD_Msk          (0x10UL)       /*!< TRMD (Bitfield-Mask: 0x01)                            */
35137  #define R_I3C0_PRSST_PRSSTWP_Pos       (7UL)          /*!< PRSSTWP (Bit 7)                                       */
35138  #define R_I3C0_PRSST_PRSSTWP_Msk       (0x80UL)       /*!< PRSSTWP (Bitfield-Mask: 0x01)                         */
35139 /* =========================================================  INST  ========================================================== */
35140  #define R_I3C0_INST_INEF_Pos           (10UL)         /*!< INEF (Bit 10)                                         */
35141  #define R_I3C0_INST_INEF_Msk           (0x400UL)      /*!< INEF (Bitfield-Mask: 0x01)                            */
35142 /* =========================================================  INSTE  ========================================================= */
35143  #define R_I3C0_INSTE_INEE_Pos          (10UL)         /*!< INEE (Bit 10)                                         */
35144  #define R_I3C0_INSTE_INEE_Msk          (0x400UL)      /*!< INEE (Bitfield-Mask: 0x01)                            */
35145 /* =========================================================  INIE  ========================================================== */
35146  #define R_I3C0_INIE_INEIE_Pos          (10UL)         /*!< INEIE (Bit 10)                                        */
35147  #define R_I3C0_INIE_INEIE_Msk          (0x400UL)      /*!< INEIE (Bitfield-Mask: 0x01)                           */
35148 /* ========================================================  INSTFC  ========================================================= */
35149  #define R_I3C0_INSTFC_INEFC_Pos        (10UL)         /*!< INEFC (Bit 10)                                        */
35150  #define R_I3C0_INSTFC_INEFC_Msk        (0x400UL)      /*!< INEFC (Bitfield-Mask: 0x01)                           */
35151 /* =========================================================  DVCT  ========================================================== */
35152  #define R_I3C0_DVCT_IDX_Pos            (19UL)         /*!< IDX (Bit 19)                                          */
35153  #define R_I3C0_DVCT_IDX_Msk            (0xf80000UL)   /*!< IDX (Bitfield-Mask: 0x1f)                             */
35154 /* ========================================================  IBINCTL  ======================================================== */
35155  #define R_I3C0_IBINCTL_NRHJCTL_Pos     (0UL)          /*!< NRHJCTL (Bit 0)                                       */
35156  #define R_I3C0_IBINCTL_NRHJCTL_Msk     (0x1UL)        /*!< NRHJCTL (Bitfield-Mask: 0x01)                         */
35157  #define R_I3C0_IBINCTL_NRMRCTL_Pos     (1UL)          /*!< NRMRCTL (Bit 1)                                       */
35158  #define R_I3C0_IBINCTL_NRMRCTL_Msk     (0x2UL)        /*!< NRMRCTL (Bitfield-Mask: 0x01)                         */
35159  #define R_I3C0_IBINCTL_NRSIRCTL_Pos    (3UL)          /*!< NRSIRCTL (Bit 3)                                      */
35160  #define R_I3C0_IBINCTL_NRSIRCTL_Msk    (0x8UL)        /*!< NRSIRCTL (Bitfield-Mask: 0x01)                        */
35161 /* =========================================================  BFCTL  ========================================================= */
35162  #define R_I3C0_BFCTL_MALE_Pos          (0UL)          /*!< MALE (Bit 0)                                          */
35163  #define R_I3C0_BFCTL_MALE_Msk          (0x1UL)        /*!< MALE (Bitfield-Mask: 0x01)                            */
35164  #define R_I3C0_BFCTL_NALE_Pos          (1UL)          /*!< NALE (Bit 1)                                          */
35165  #define R_I3C0_BFCTL_NALE_Msk          (0x2UL)        /*!< NALE (Bitfield-Mask: 0x01)                            */
35166  #define R_I3C0_BFCTL_SALE_Pos          (2UL)          /*!< SALE (Bit 2)                                          */
35167  #define R_I3C0_BFCTL_SALE_Msk          (0x4UL)        /*!< SALE (Bitfield-Mask: 0x01)                            */
35168  #define R_I3C0_BFCTL_SCSYNE_Pos        (8UL)          /*!< SCSYNE (Bit 8)                                        */
35169  #define R_I3C0_BFCTL_SCSYNE_Msk        (0x100UL)      /*!< SCSYNE (Bitfield-Mask: 0x01)                          */
35170  #define R_I3C0_BFCTL_SMBS_Pos          (12UL)         /*!< SMBS (Bit 12)                                         */
35171  #define R_I3C0_BFCTL_SMBS_Msk          (0x1000UL)     /*!< SMBS (Bitfield-Mask: 0x01)                            */
35172  #define R_I3C0_BFCTL_FMPE_Pos          (14UL)         /*!< FMPE (Bit 14)                                         */
35173  #define R_I3C0_BFCTL_FMPE_Msk          (0x4000UL)     /*!< FMPE (Bitfield-Mask: 0x01)                            */
35174  #define R_I3C0_BFCTL_HSME_Pos          (15UL)         /*!< HSME (Bit 15)                                         */
35175  #define R_I3C0_BFCTL_HSME_Msk          (0x8000UL)     /*!< HSME (Bitfield-Mask: 0x01)                            */
35176 /* =========================================================  SVCTL  ========================================================= */
35177  #define R_I3C0_SVCTL_GCAE_Pos          (0UL)          /*!< GCAE (Bit 0)                                          */
35178  #define R_I3C0_SVCTL_GCAE_Msk          (0x1UL)        /*!< GCAE (Bitfield-Mask: 0x01)                            */
35179  #define R_I3C0_SVCTL_HSMCE_Pos         (5UL)          /*!< HSMCE (Bit 5)                                         */
35180  #define R_I3C0_SVCTL_HSMCE_Msk         (0x20UL)       /*!< HSMCE (Bitfield-Mask: 0x01)                           */
35181  #define R_I3C0_SVCTL_DVIDE_Pos         (6UL)          /*!< DVIDE (Bit 6)                                         */
35182  #define R_I3C0_SVCTL_DVIDE_Msk         (0x40UL)       /*!< DVIDE (Bitfield-Mask: 0x01)                           */
35183  #define R_I3C0_SVCTL_HOAE_Pos          (15UL)         /*!< HOAE (Bit 15)                                         */
35184  #define R_I3C0_SVCTL_HOAE_Msk          (0x8000UL)     /*!< HOAE (Bitfield-Mask: 0x01)                            */
35185  #define R_I3C0_SVCTL_SVAEn_Pos         (16UL)         /*!< SVAEn (Bit 16)                                        */
35186  #define R_I3C0_SVCTL_SVAEn_Msk         (0x10000UL)    /*!< SVAEn (Bitfield-Mask: 0x01)                           */
35187 /* =======================================================  REFCKCTL  ======================================================== */
35188  #define R_I3C0_REFCKCTL_IREFCKS_Pos    (0UL)          /*!< IREFCKS (Bit 0)                                       */
35189  #define R_I3C0_REFCKCTL_IREFCKS_Msk    (0x7UL)        /*!< IREFCKS (Bitfield-Mask: 0x07)                         */
35190 /* =========================================================  STDBR  ========================================================= */
35191  #define R_I3C0_STDBR_SBRLO_Pos         (0UL)          /*!< SBRLO (Bit 0)                                         */
35192  #define R_I3C0_STDBR_SBRLO_Msk         (0xffUL)       /*!< SBRLO (Bitfield-Mask: 0xff)                           */
35193  #define R_I3C0_STDBR_SBRHO_Pos         (8UL)          /*!< SBRHO (Bit 8)                                         */
35194  #define R_I3C0_STDBR_SBRHO_Msk         (0xff00UL)     /*!< SBRHO (Bitfield-Mask: 0xff)                           */
35195  #define R_I3C0_STDBR_SBRLP_Pos         (16UL)         /*!< SBRLP (Bit 16)                                        */
35196  #define R_I3C0_STDBR_SBRLP_Msk         (0x3f0000UL)   /*!< SBRLP (Bitfield-Mask: 0x3f)                           */
35197  #define R_I3C0_STDBR_SBRHP_Pos         (24UL)         /*!< SBRHP (Bit 24)                                        */
35198  #define R_I3C0_STDBR_SBRHP_Msk         (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f)                           */
35199  #define R_I3C0_STDBR_DSBRPO_Pos        (31UL)         /*!< DSBRPO (Bit 31)                                       */
35200  #define R_I3C0_STDBR_DSBRPO_Msk        (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01)                          */
35201 /* =========================================================  EXTBR  ========================================================= */
35202  #define R_I3C0_EXTBR_EBRLO_Pos         (0UL)          /*!< EBRLO (Bit 0)                                         */
35203  #define R_I3C0_EXTBR_EBRLO_Msk         (0xffUL)       /*!< EBRLO (Bitfield-Mask: 0xff)                           */
35204  #define R_I3C0_EXTBR_EBRHO_Pos         (8UL)          /*!< EBRHO (Bit 8)                                         */
35205  #define R_I3C0_EXTBR_EBRHO_Msk         (0xff00UL)     /*!< EBRHO (Bitfield-Mask: 0xff)                           */
35206  #define R_I3C0_EXTBR_EBRLP_Pos         (16UL)         /*!< EBRLP (Bit 16)                                        */
35207  #define R_I3C0_EXTBR_EBRLP_Msk         (0x3f0000UL)   /*!< EBRLP (Bitfield-Mask: 0x3f)                           */
35208  #define R_I3C0_EXTBR_EBRHP_Pos         (24UL)         /*!< EBRHP (Bit 24)                                        */
35209  #define R_I3C0_EXTBR_EBRHP_Msk         (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f)                           */
35210 /* ========================================================  BFRECDT  ======================================================== */
35211  #define R_I3C0_BFRECDT_FRECYC_Pos      (0UL)          /*!< FRECYC (Bit 0)                                        */
35212  #define R_I3C0_BFRECDT_FRECYC_Msk      (0x1ffUL)      /*!< FRECYC (Bitfield-Mask: 0x1ff)                         */
35213 /* ========================================================  BAVLCDT  ======================================================== */
35214  #define R_I3C0_BAVLCDT_AVLCYC_Pos      (0UL)          /*!< AVLCYC (Bit 0)                                        */
35215  #define R_I3C0_BAVLCDT_AVLCYC_Msk      (0x1ffUL)      /*!< AVLCYC (Bitfield-Mask: 0x1ff)                         */
35216 /* ========================================================  BIDLCDT  ======================================================== */
35217  #define R_I3C0_BIDLCDT_IDLCYC_Pos      (0UL)          /*!< IDLCYC (Bit 0)                                        */
35218  #define R_I3C0_BIDLCDT_IDLCYC_Msk      (0x3ffffUL)    /*!< IDLCYC (Bitfield-Mask: 0x3ffff)                       */
35219 /* ========================================================  OUTCTL  ========================================================= */
35220  #define R_I3C0_OUTCTL_SDOC_Pos         (0UL)          /*!< SDOC (Bit 0)                                          */
35221  #define R_I3C0_OUTCTL_SDOC_Msk         (0x1UL)        /*!< SDOC (Bitfield-Mask: 0x01)                            */
35222  #define R_I3C0_OUTCTL_SCOC_Pos         (1UL)          /*!< SCOC (Bit 1)                                          */
35223  #define R_I3C0_OUTCTL_SCOC_Msk         (0x2UL)        /*!< SCOC (Bitfield-Mask: 0x01)                            */
35224  #define R_I3C0_OUTCTL_SOCWP_Pos        (2UL)          /*!< SOCWP (Bit 2)                                         */
35225  #define R_I3C0_OUTCTL_SOCWP_Msk        (0x4UL)        /*!< SOCWP (Bitfield-Mask: 0x01)                           */
35226  #define R_I3C0_OUTCTL_EXCYC_Pos        (4UL)          /*!< EXCYC (Bit 4)                                         */
35227  #define R_I3C0_OUTCTL_EXCYC_Msk        (0x10UL)       /*!< EXCYC (Bitfield-Mask: 0x01)                           */
35228  #define R_I3C0_OUTCTL_SDOD_Pos         (8UL)          /*!< SDOD (Bit 8)                                          */
35229  #define R_I3C0_OUTCTL_SDOD_Msk         (0x700UL)      /*!< SDOD (Bitfield-Mask: 0x07)                            */
35230  #define R_I3C0_OUTCTL_SDODCS_Pos       (15UL)         /*!< SDODCS (Bit 15)                                       */
35231  #define R_I3C0_OUTCTL_SDODCS_Msk       (0x8000UL)     /*!< SDODCS (Bitfield-Mask: 0x01)                          */
35232 /* =========================================================  INCTL  ========================================================= */
35233  #define R_I3C0_INCTL_DNFS_Pos          (0UL)          /*!< DNFS (Bit 0)                                          */
35234  #define R_I3C0_INCTL_DNFS_Msk          (0xfUL)        /*!< DNFS (Bitfield-Mask: 0x0f)                            */
35235  #define R_I3C0_INCTL_DNFE_Pos          (4UL)          /*!< DNFE (Bit 4)                                          */
35236  #define R_I3C0_INCTL_DNFE_Msk          (0x10UL)       /*!< DNFE (Bitfield-Mask: 0x01)                            */
35237 /* ========================================================  TMOCTL  ========================================================= */
35238  #define R_I3C0_TMOCTL_TODTS_Pos        (0UL)          /*!< TODTS (Bit 0)                                         */
35239  #define R_I3C0_TMOCTL_TODTS_Msk        (0x3UL)        /*!< TODTS (Bitfield-Mask: 0x03)                           */
35240  #define R_I3C0_TMOCTL_TOLCTL_Pos       (4UL)          /*!< TOLCTL (Bit 4)                                        */
35241  #define R_I3C0_TMOCTL_TOLCTL_Msk       (0x10UL)       /*!< TOLCTL (Bitfield-Mask: 0x01)                          */
35242  #define R_I3C0_TMOCTL_TOHCTL_Pos       (5UL)          /*!< TOHCTL (Bit 5)                                        */
35243  #define R_I3C0_TMOCTL_TOHCTL_Msk       (0x20UL)       /*!< TOHCTL (Bitfield-Mask: 0x01)                          */
35244  #define R_I3C0_TMOCTL_TOMDS_Pos        (6UL)          /*!< TOMDS (Bit 6)                                         */
35245  #define R_I3C0_TMOCTL_TOMDS_Msk        (0xc0UL)       /*!< TOMDS (Bitfield-Mask: 0x03)                           */
35246 /* =========================================================  WUCTL  ========================================================= */
35247  #define R_I3C0_WUCTL_WUACKS_Pos        (0UL)          /*!< WUACKS (Bit 0)                                        */
35248  #define R_I3C0_WUCTL_WUACKS_Msk        (0x1UL)        /*!< WUACKS (Bitfield-Mask: 0x01)                          */
35249  #define R_I3C0_WUCTL_WUANFS_Pos        (4UL)          /*!< WUANFS (Bit 4)                                        */
35250  #define R_I3C0_WUCTL_WUANFS_Msk        (0x10UL)       /*!< WUANFS (Bitfield-Mask: 0x01)                          */
35251  #define R_I3C0_WUCTL_WUFSYNE_Pos       (6UL)          /*!< WUFSYNE (Bit 6)                                       */
35252  #define R_I3C0_WUCTL_WUFSYNE_Msk       (0x40UL)       /*!< WUFSYNE (Bitfield-Mask: 0x01)                         */
35253  #define R_I3C0_WUCTL_WUFE_Pos          (7UL)          /*!< WUFE (Bit 7)                                          */
35254  #define R_I3C0_WUCTL_WUFE_Msk          (0x80UL)       /*!< WUFE (Bitfield-Mask: 0x01)                            */
35255 /* ========================================================  ACKCTL  ========================================================= */
35256  #define R_I3C0_ACKCTL_ACKR_Pos         (0UL)          /*!< ACKR (Bit 0)                                          */
35257  #define R_I3C0_ACKCTL_ACKR_Msk         (0x1UL)        /*!< ACKR (Bitfield-Mask: 0x01)                            */
35258  #define R_I3C0_ACKCTL_ACKT_Pos         (1UL)          /*!< ACKT (Bit 1)                                          */
35259  #define R_I3C0_ACKCTL_ACKT_Msk         (0x2UL)        /*!< ACKT (Bitfield-Mask: 0x01)                            */
35260  #define R_I3C0_ACKCTL_ACKTWP_Pos       (2UL)          /*!< ACKTWP (Bit 2)                                        */
35261  #define R_I3C0_ACKCTL_ACKTWP_Msk       (0x4UL)        /*!< ACKTWP (Bitfield-Mask: 0x01)                          */
35262 /* =======================================================  SCSTRCTL  ======================================================== */
35263  #define R_I3C0_SCSTRCTL_ACKTWE_Pos     (0UL)          /*!< ACKTWE (Bit 0)                                        */
35264  #define R_I3C0_SCSTRCTL_ACKTWE_Msk     (0x1UL)        /*!< ACKTWE (Bitfield-Mask: 0x01)                          */
35265  #define R_I3C0_SCSTRCTL_RWE_Pos        (1UL)          /*!< RWE (Bit 1)                                           */
35266  #define R_I3C0_SCSTRCTL_RWE_Msk        (0x2UL)        /*!< RWE (Bitfield-Mask: 0x01)                             */
35267 /* =======================================================  SCSTLCTL  ======================================================== */
35268  #define R_I3C0_SCSTLCTL_STLCYC_Pos     (0UL)          /*!< STLCYC (Bit 0)                                        */
35269  #define R_I3C0_SCSTLCTL_STLCYC_Msk     (0xffffUL)     /*!< STLCYC (Bitfield-Mask: 0xffff)                        */
35270  #define R_I3C0_SCSTLCTL_AAPE_Pos       (28UL)         /*!< AAPE (Bit 28)                                         */
35271  #define R_I3C0_SCSTLCTL_AAPE_Msk       (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01)                            */
35272  #define R_I3C0_SCSTLCTL_TRAPE_Pos      (29UL)         /*!< TRAPE (Bit 29)                                        */
35273  #define R_I3C0_SCSTLCTL_TRAPE_Msk      (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01)                           */
35274  #define R_I3C0_SCSTLCTL_PARPE_Pos      (30UL)         /*!< PARPE (Bit 30)                                        */
35275  #define R_I3C0_SCSTLCTL_PARPE_Msk      (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01)                           */
35276  #define R_I3C0_SCSTLCTL_ACKPE_Pos      (31UL)         /*!< ACKPE (Bit 31)                                        */
35277  #define R_I3C0_SCSTLCTL_ACKPE_Msk      (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01)                           */
35278 /* ========================================================  SVTDLG0  ======================================================== */
35279  #define R_I3C0_SVTDLG0_STDLG_Pos       (16UL)         /*!< STDLG (Bit 16)                                        */
35280  #define R_I3C0_SVTDLG0_STDLG_Msk       (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff)                         */
35281 /* ========================================================  CNDCTL  ========================================================= */
35282  #define R_I3C0_CNDCTL_STCND_Pos        (0UL)          /*!< STCND (Bit 0)                                         */
35283  #define R_I3C0_CNDCTL_STCND_Msk        (0x1UL)        /*!< STCND (Bitfield-Mask: 0x01)                           */
35284  #define R_I3C0_CNDCTL_SRCND_Pos        (1UL)          /*!< SRCND (Bit 1)                                         */
35285  #define R_I3C0_CNDCTL_SRCND_Msk        (0x2UL)        /*!< SRCND (Bitfield-Mask: 0x01)                           */
35286  #define R_I3C0_CNDCTL_SPCND_Pos        (2UL)          /*!< SPCND (Bit 2)                                         */
35287  #define R_I3C0_CNDCTL_SPCND_Msk        (0x4UL)        /*!< SPCND (Bitfield-Mask: 0x01)                           */
35288 /* ========================================================  NCMDQP  ========================================================= */
35289 /* ========================================================  NRSPQP  ========================================================= */
35290 /* ========================================================  NTDTBP0  ======================================================== */
35291 /* ========================================================  NIBIQP  ========================================================= */
35292 /* =========================================================  NRSQP  ========================================================= */
35293 /* ========================================================  NQTHCTL  ======================================================== */
35294  #define R_I3C0_NQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
35295  #define R_I3C0_NQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
35296  #define R_I3C0_NQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
35297  #define R_I3C0_NQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
35298  #define R_I3C0_NQTHCTL_IBIDSSZ_Pos     (16UL)         /*!< IBIDSSZ (Bit 16)                                      */
35299  #define R_I3C0_NQTHCTL_IBIDSSZ_Msk     (0xff0000UL)   /*!< IBIDSSZ (Bitfield-Mask: 0xff)                         */
35300  #define R_I3C0_NQTHCTL_IBIQTH_Pos      (24UL)         /*!< IBIQTH (Bit 24)                                       */
35301  #define R_I3C0_NQTHCTL_IBIQTH_Msk      (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff)                          */
35302 /* =======================================================  NTBTHCTL0  ======================================================= */
35303  #define R_I3C0_NTBTHCTL0_TXDBTH_Pos    (0UL)          /*!< TXDBTH (Bit 0)                                        */
35304  #define R_I3C0_NTBTHCTL0_TXDBTH_Msk    (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
35305  #define R_I3C0_NTBTHCTL0_RXDBTH_Pos    (8UL)          /*!< RXDBTH (Bit 8)                                        */
35306  #define R_I3C0_NTBTHCTL0_RXDBTH_Msk    (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
35307  #define R_I3C0_NTBTHCTL0_TXSTTH_Pos    (16UL)         /*!< TXSTTH (Bit 16)                                       */
35308  #define R_I3C0_NTBTHCTL0_TXSTTH_Msk    (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
35309  #define R_I3C0_NTBTHCTL0_RXSTTH_Pos    (24UL)         /*!< RXSTTH (Bit 24)                                       */
35310  #define R_I3C0_NTBTHCTL0_RXSTTH_Msk    (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
35311 /* =======================================================  NRQTHCTL  ======================================================== */
35312  #define R_I3C0_NRQTHCTL_RSQTH_Pos      (0UL)          /*!< RSQTH (Bit 0)                                         */
35313  #define R_I3C0_NRQTHCTL_RSQTH_Msk      (0xffUL)       /*!< RSQTH (Bitfield-Mask: 0xff)                           */
35314 /* ==========================================================  BST  ========================================================== */
35315  #define R_I3C0_BST_STCNDDF_Pos         (0UL)          /*!< STCNDDF (Bit 0)                                       */
35316  #define R_I3C0_BST_STCNDDF_Msk         (0x1UL)        /*!< STCNDDF (Bitfield-Mask: 0x01)                         */
35317  #define R_I3C0_BST_SPCNDDF_Pos         (1UL)          /*!< SPCNDDF (Bit 1)                                       */
35318  #define R_I3C0_BST_SPCNDDF_Msk         (0x2UL)        /*!< SPCNDDF (Bitfield-Mask: 0x01)                         */
35319  #define R_I3C0_BST_HDREXDF_Pos         (2UL)          /*!< HDREXDF (Bit 2)                                       */
35320  #define R_I3C0_BST_HDREXDF_Msk         (0x4UL)        /*!< HDREXDF (Bitfield-Mask: 0x01)                         */
35321  #define R_I3C0_BST_NACKDF_Pos          (4UL)          /*!< NACKDF (Bit 4)                                        */
35322  #define R_I3C0_BST_NACKDF_Msk          (0x10UL)       /*!< NACKDF (Bitfield-Mask: 0x01)                          */
35323  #define R_I3C0_BST_TENDF_Pos           (8UL)          /*!< TENDF (Bit 8)                                         */
35324  #define R_I3C0_BST_TENDF_Msk           (0x100UL)      /*!< TENDF (Bitfield-Mask: 0x01)                           */
35325  #define R_I3C0_BST_ALF_Pos             (16UL)         /*!< ALF (Bit 16)                                          */
35326  #define R_I3C0_BST_ALF_Msk             (0x10000UL)    /*!< ALF (Bitfield-Mask: 0x01)                             */
35327  #define R_I3C0_BST_TODF_Pos            (20UL)         /*!< TODF (Bit 20)                                         */
35328  #define R_I3C0_BST_TODF_Msk            (0x100000UL)   /*!< TODF (Bitfield-Mask: 0x01)                            */
35329 /* =========================================================  BSTE  ========================================================== */
35330  #define R_I3C0_BSTE_STCNDDE_Pos        (0UL)          /*!< STCNDDE (Bit 0)                                       */
35331  #define R_I3C0_BSTE_STCNDDE_Msk        (0x1UL)        /*!< STCNDDE (Bitfield-Mask: 0x01)                         */
35332  #define R_I3C0_BSTE_SPCNDDE_Pos        (1UL)          /*!< SPCNDDE (Bit 1)                                       */
35333  #define R_I3C0_BSTE_SPCNDDE_Msk        (0x2UL)        /*!< SPCNDDE (Bitfield-Mask: 0x01)                         */
35334  #define R_I3C0_BSTE_HDREXDE_Pos        (2UL)          /*!< HDREXDE (Bit 2)                                       */
35335  #define R_I3C0_BSTE_HDREXDE_Msk        (0x4UL)        /*!< HDREXDE (Bitfield-Mask: 0x01)                         */
35336  #define R_I3C0_BSTE_NACKDE_Pos         (4UL)          /*!< NACKDE (Bit 4)                                        */
35337  #define R_I3C0_BSTE_NACKDE_Msk         (0x10UL)       /*!< NACKDE (Bitfield-Mask: 0x01)                          */
35338  #define R_I3C0_BSTE_TENDE_Pos          (8UL)          /*!< TENDE (Bit 8)                                         */
35339  #define R_I3C0_BSTE_TENDE_Msk          (0x100UL)      /*!< TENDE (Bitfield-Mask: 0x01)                           */
35340  #define R_I3C0_BSTE_ALE_Pos            (16UL)         /*!< ALE (Bit 16)                                          */
35341  #define R_I3C0_BSTE_ALE_Msk            (0x10000UL)    /*!< ALE (Bitfield-Mask: 0x01)                             */
35342  #define R_I3C0_BSTE_TODE_Pos           (20UL)         /*!< TODE (Bit 20)                                         */
35343  #define R_I3C0_BSTE_TODE_Msk           (0x100000UL)   /*!< TODE (Bitfield-Mask: 0x01)                            */
35344 /* ==========================================================  BIE  ========================================================== */
35345  #define R_I3C0_BIE_STCNDDIE_Pos        (0UL)          /*!< STCNDDIE (Bit 0)                                      */
35346  #define R_I3C0_BIE_STCNDDIE_Msk        (0x1UL)        /*!< STCNDDIE (Bitfield-Mask: 0x01)                        */
35347  #define R_I3C0_BIE_SPCNDDIE_Pos        (1UL)          /*!< SPCNDDIE (Bit 1)                                      */
35348  #define R_I3C0_BIE_SPCNDDIE_Msk        (0x2UL)        /*!< SPCNDDIE (Bitfield-Mask: 0x01)                        */
35349  #define R_I3C0_BIE_HDREXDIE_Pos        (2UL)          /*!< HDREXDIE (Bit 2)                                      */
35350  #define R_I3C0_BIE_HDREXDIE_Msk        (0x4UL)        /*!< HDREXDIE (Bitfield-Mask: 0x01)                        */
35351  #define R_I3C0_BIE_NACKDIE_Pos         (4UL)          /*!< NACKDIE (Bit 4)                                       */
35352  #define R_I3C0_BIE_NACKDIE_Msk         (0x10UL)       /*!< NACKDIE (Bitfield-Mask: 0x01)                         */
35353  #define R_I3C0_BIE_TENDIE_Pos          (8UL)          /*!< TENDIE (Bit 8)                                        */
35354  #define R_I3C0_BIE_TENDIE_Msk          (0x100UL)      /*!< TENDIE (Bitfield-Mask: 0x01)                          */
35355  #define R_I3C0_BIE_ALIE_Pos            (16UL)         /*!< ALIE (Bit 16)                                         */
35356  #define R_I3C0_BIE_ALIE_Msk            (0x10000UL)    /*!< ALIE (Bitfield-Mask: 0x01)                            */
35357  #define R_I3C0_BIE_TODIE_Pos           (20UL)         /*!< TODIE (Bit 20)                                        */
35358  #define R_I3C0_BIE_TODIE_Msk           (0x100000UL)   /*!< TODIE (Bitfield-Mask: 0x01)                           */
35359 /* =========================================================  BSTFC  ========================================================= */
35360  #define R_I3C0_BSTFC_STCNDDFC_Pos      (0UL)          /*!< STCNDDFC (Bit 0)                                      */
35361  #define R_I3C0_BSTFC_STCNDDFC_Msk      (0x1UL)        /*!< STCNDDFC (Bitfield-Mask: 0x01)                        */
35362  #define R_I3C0_BSTFC_SPCNDDFC_Pos      (1UL)          /*!< SPCNDDFC (Bit 1)                                      */
35363  #define R_I3C0_BSTFC_SPCNDDFC_Msk      (0x2UL)        /*!< SPCNDDFC (Bitfield-Mask: 0x01)                        */
35364  #define R_I3C0_BSTFC_HDREXDFC_Pos      (2UL)          /*!< HDREXDFC (Bit 2)                                      */
35365  #define R_I3C0_BSTFC_HDREXDFC_Msk      (0x4UL)        /*!< HDREXDFC (Bitfield-Mask: 0x01)                        */
35366  #define R_I3C0_BSTFC_NACKDFC_Pos       (4UL)          /*!< NACKDFC (Bit 4)                                       */
35367  #define R_I3C0_BSTFC_NACKDFC_Msk       (0x10UL)       /*!< NACKDFC (Bitfield-Mask: 0x01)                         */
35368  #define R_I3C0_BSTFC_TENDFC_Pos        (8UL)          /*!< TENDFC (Bit 8)                                        */
35369  #define R_I3C0_BSTFC_TENDFC_Msk        (0x100UL)      /*!< TENDFC (Bitfield-Mask: 0x01)                          */
35370  #define R_I3C0_BSTFC_ALFC_Pos          (16UL)         /*!< ALFC (Bit 16)                                         */
35371  #define R_I3C0_BSTFC_ALFC_Msk          (0x10000UL)    /*!< ALFC (Bitfield-Mask: 0x01)                            */
35372  #define R_I3C0_BSTFC_TODFC_Pos         (20UL)         /*!< TODFC (Bit 20)                                        */
35373  #define R_I3C0_BSTFC_TODFC_Msk         (0x100000UL)   /*!< TODFC (Bitfield-Mask: 0x01)                           */
35374 /* =========================================================  NTST  ========================================================== */
35375  #define R_I3C0_NTST_TDBEF0_Pos         (0UL)          /*!< TDBEF0 (Bit 0)                                        */
35376  #define R_I3C0_NTST_TDBEF0_Msk         (0x1UL)        /*!< TDBEF0 (Bitfield-Mask: 0x01)                          */
35377  #define R_I3C0_NTST_RDBFF0_Pos         (1UL)          /*!< RDBFF0 (Bit 1)                                        */
35378  #define R_I3C0_NTST_RDBFF0_Msk         (0x2UL)        /*!< RDBFF0 (Bitfield-Mask: 0x01)                          */
35379  #define R_I3C0_NTST_IBIQEFF_Pos        (2UL)          /*!< IBIQEFF (Bit 2)                                       */
35380  #define R_I3C0_NTST_IBIQEFF_Msk        (0x4UL)        /*!< IBIQEFF (Bitfield-Mask: 0x01)                         */
35381  #define R_I3C0_NTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
35382  #define R_I3C0_NTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
35383  #define R_I3C0_NTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
35384  #define R_I3C0_NTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
35385  #define R_I3C0_NTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
35386  #define R_I3C0_NTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
35387  #define R_I3C0_NTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
35388  #define R_I3C0_NTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
35389  #define R_I3C0_NTST_RSQFF_Pos          (20UL)         /*!< RSQFF (Bit 20)                                        */
35390  #define R_I3C0_NTST_RSQFF_Msk          (0x100000UL)   /*!< RSQFF (Bitfield-Mask: 0x01)                           */
35391 /* =========================================================  NTSTE  ========================================================= */
35392  #define R_I3C0_NTSTE_TDBEE0_Pos        (0UL)          /*!< TDBEE0 (Bit 0)                                        */
35393  #define R_I3C0_NTSTE_TDBEE0_Msk        (0x1UL)        /*!< TDBEE0 (Bitfield-Mask: 0x01)                          */
35394  #define R_I3C0_NTSTE_RDBFE0_Pos        (1UL)          /*!< RDBFE0 (Bit 1)                                        */
35395  #define R_I3C0_NTSTE_RDBFE0_Msk        (0x2UL)        /*!< RDBFE0 (Bitfield-Mask: 0x01)                          */
35396  #define R_I3C0_NTSTE_IBIQEFE_Pos       (2UL)          /*!< IBIQEFE (Bit 2)                                       */
35397  #define R_I3C0_NTSTE_IBIQEFE_Msk       (0x4UL)        /*!< IBIQEFE (Bitfield-Mask: 0x01)                         */
35398  #define R_I3C0_NTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
35399  #define R_I3C0_NTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
35400  #define R_I3C0_NTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
35401  #define R_I3C0_NTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
35402  #define R_I3C0_NTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
35403  #define R_I3C0_NTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
35404  #define R_I3C0_NTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
35405  #define R_I3C0_NTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
35406  #define R_I3C0_NTSTE_RSQFE_Pos         (20UL)         /*!< RSQFE (Bit 20)                                        */
35407  #define R_I3C0_NTSTE_RSQFE_Msk         (0x100000UL)   /*!< RSQFE (Bitfield-Mask: 0x01)                           */
35408 /* =========================================================  NTIE  ========================================================== */
35409  #define R_I3C0_NTIE_TDBEIE0_Pos        (0UL)          /*!< TDBEIE0 (Bit 0)                                       */
35410  #define R_I3C0_NTIE_TDBEIE0_Msk        (0x1UL)        /*!< TDBEIE0 (Bitfield-Mask: 0x01)                         */
35411  #define R_I3C0_NTIE_RDBFIE0_Pos        (1UL)          /*!< RDBFIE0 (Bit 1)                                       */
35412  #define R_I3C0_NTIE_RDBFIE0_Msk        (0x2UL)        /*!< RDBFIE0 (Bitfield-Mask: 0x01)                         */
35413  #define R_I3C0_NTIE_IBIQEFIE_Pos       (2UL)          /*!< IBIQEFIE (Bit 2)                                      */
35414  #define R_I3C0_NTIE_IBIQEFIE_Msk       (0x4UL)        /*!< IBIQEFIE (Bitfield-Mask: 0x01)                        */
35415  #define R_I3C0_NTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
35416  #define R_I3C0_NTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
35417  #define R_I3C0_NTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
35418  #define R_I3C0_NTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
35419  #define R_I3C0_NTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
35420  #define R_I3C0_NTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
35421  #define R_I3C0_NTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
35422  #define R_I3C0_NTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
35423  #define R_I3C0_NTIE_RSQFIE_Pos         (20UL)         /*!< RSQFIE (Bit 20)                                       */
35424  #define R_I3C0_NTIE_RSQFIE_Msk         (0x100000UL)   /*!< RSQFIE (Bitfield-Mask: 0x01)                          */
35425 /* ========================================================  NTSTFC  ========================================================= */
35426  #define R_I3C0_NTSTFC_TDBEFC0_Pos      (0UL)          /*!< TDBEFC0 (Bit 0)                                       */
35427  #define R_I3C0_NTSTFC_TDBEFC0_Msk      (0x1UL)        /*!< TDBEFC0 (Bitfield-Mask: 0x01)                         */
35428  #define R_I3C0_NTSTFC_RDBFFC0_Pos      (1UL)          /*!< RDBFFC0 (Bit 1)                                       */
35429  #define R_I3C0_NTSTFC_RDBFFC0_Msk      (0x2UL)        /*!< RDBFFC0 (Bitfield-Mask: 0x01)                         */
35430  #define R_I3C0_NTSTFC_IBIQEFFC_Pos     (2UL)          /*!< IBIQEFFC (Bit 2)                                      */
35431  #define R_I3C0_NTSTFC_IBIQEFFC_Msk     (0x4UL)        /*!< IBIQEFFC (Bitfield-Mask: 0x01)                        */
35432  #define R_I3C0_NTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
35433  #define R_I3C0_NTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
35434  #define R_I3C0_NTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
35435  #define R_I3C0_NTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
35436  #define R_I3C0_NTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
35437  #define R_I3C0_NTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
35438  #define R_I3C0_NTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
35439  #define R_I3C0_NTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
35440  #define R_I3C0_NTSTFC_RSQFFC_Pos       (20UL)         /*!< RSQFFC (Bit 20)                                       */
35441  #define R_I3C0_NTSTFC_RSQFFC_Msk       (0x100000UL)   /*!< RSQFFC (Bitfield-Mask: 0x01)                          */
35442 /* =========================================================  BCST  ========================================================== */
35443  #define R_I3C0_BCST_BFREF_Pos          (0UL)          /*!< BFREF (Bit 0)                                         */
35444  #define R_I3C0_BCST_BFREF_Msk          (0x1UL)        /*!< BFREF (Bitfield-Mask: 0x01)                           */
35445  #define R_I3C0_BCST_BAVLF_Pos          (1UL)          /*!< BAVLF (Bit 1)                                         */
35446  #define R_I3C0_BCST_BAVLF_Msk          (0x2UL)        /*!< BAVLF (Bitfield-Mask: 0x01)                           */
35447  #define R_I3C0_BCST_BIDLF_Pos          (2UL)          /*!< BIDLF (Bit 2)                                         */
35448  #define R_I3C0_BCST_BIDLF_Msk          (0x4UL)        /*!< BIDLF (Bitfield-Mask: 0x01)                           */
35449 /* =========================================================  SVST  ========================================================== */
35450  #define R_I3C0_SVST_GCAF_Pos           (0UL)          /*!< GCAF (Bit 0)                                          */
35451  #define R_I3C0_SVST_GCAF_Msk           (0x1UL)        /*!< GCAF (Bitfield-Mask: 0x01)                            */
35452  #define R_I3C0_SVST_HSMCF_Pos          (5UL)          /*!< HSMCF (Bit 5)                                         */
35453  #define R_I3C0_SVST_HSMCF_Msk          (0x20UL)       /*!< HSMCF (Bitfield-Mask: 0x01)                           */
35454  #define R_I3C0_SVST_DVIDF_Pos          (6UL)          /*!< DVIDF (Bit 6)                                         */
35455  #define R_I3C0_SVST_DVIDF_Msk          (0x40UL)       /*!< DVIDF (Bitfield-Mask: 0x01)                           */
35456  #define R_I3C0_SVST_HOAF_Pos           (15UL)         /*!< HOAF (Bit 15)                                         */
35457  #define R_I3C0_SVST_HOAF_Msk           (0x8000UL)     /*!< HOAF (Bitfield-Mask: 0x01)                            */
35458  #define R_I3C0_SVST_SVAFn_Pos          (16UL)         /*!< SVAFn (Bit 16)                                        */
35459  #define R_I3C0_SVST_SVAFn_Msk          (0x10000UL)    /*!< SVAFn (Bitfield-Mask: 0x01)                           */
35460 /* =========================================================  WUST  ========================================================== */
35461  #define R_I3C0_WUST_WUASYNF_Pos        (0UL)          /*!< WUASYNF (Bit 0)                                       */
35462  #define R_I3C0_WUST_WUASYNF_Msk        (0x1UL)        /*!< WUASYNF (Bitfield-Mask: 0x01)                         */
35463 /* ========================================================  DATBAS0  ======================================================== */
35464  #define R_I3C0_DATBAS0_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
35465  #define R_I3C0_DATBAS0_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
35466  #define R_I3C0_DATBAS0_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
35467  #define R_I3C0_DATBAS0_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
35468  #define R_I3C0_DATBAS0_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
35469  #define R_I3C0_DATBAS0_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
35470  #define R_I3C0_DATBAS0_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
35471  #define R_I3C0_DATBAS0_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
35472  #define R_I3C0_DATBAS0_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
35473  #define R_I3C0_DATBAS0_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
35474  #define R_I3C0_DATBAS0_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
35475  #define R_I3C0_DATBAS0_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
35476  #define R_I3C0_DATBAS0_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
35477  #define R_I3C0_DATBAS0_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
35478  #define R_I3C0_DATBAS0_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
35479  #define R_I3C0_DATBAS0_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
35480 /* ========================================================  DATBAS1  ======================================================== */
35481  #define R_I3C0_DATBAS1_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
35482  #define R_I3C0_DATBAS1_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
35483  #define R_I3C0_DATBAS1_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
35484  #define R_I3C0_DATBAS1_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
35485  #define R_I3C0_DATBAS1_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
35486  #define R_I3C0_DATBAS1_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
35487  #define R_I3C0_DATBAS1_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
35488  #define R_I3C0_DATBAS1_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
35489  #define R_I3C0_DATBAS1_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
35490  #define R_I3C0_DATBAS1_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
35491  #define R_I3C0_DATBAS1_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
35492  #define R_I3C0_DATBAS1_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
35493  #define R_I3C0_DATBAS1_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
35494  #define R_I3C0_DATBAS1_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
35495  #define R_I3C0_DATBAS1_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
35496  #define R_I3C0_DATBAS1_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
35497 /* ========================================================  DATBAS2  ======================================================== */
35498  #define R_I3C0_DATBAS2_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
35499  #define R_I3C0_DATBAS2_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
35500  #define R_I3C0_DATBAS2_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
35501  #define R_I3C0_DATBAS2_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
35502  #define R_I3C0_DATBAS2_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
35503  #define R_I3C0_DATBAS2_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
35504  #define R_I3C0_DATBAS2_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
35505  #define R_I3C0_DATBAS2_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
35506  #define R_I3C0_DATBAS2_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
35507  #define R_I3C0_DATBAS2_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
35508  #define R_I3C0_DATBAS2_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
35509  #define R_I3C0_DATBAS2_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
35510  #define R_I3C0_DATBAS2_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
35511  #define R_I3C0_DATBAS2_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
35512  #define R_I3C0_DATBAS2_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
35513  #define R_I3C0_DATBAS2_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
35514 /* ========================================================  DATBAS3  ======================================================== */
35515  #define R_I3C0_DATBAS3_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
35516  #define R_I3C0_DATBAS3_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
35517  #define R_I3C0_DATBAS3_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
35518  #define R_I3C0_DATBAS3_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
35519  #define R_I3C0_DATBAS3_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
35520  #define R_I3C0_DATBAS3_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
35521  #define R_I3C0_DATBAS3_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
35522  #define R_I3C0_DATBAS3_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
35523  #define R_I3C0_DATBAS3_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
35524  #define R_I3C0_DATBAS3_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
35525  #define R_I3C0_DATBAS3_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
35526  #define R_I3C0_DATBAS3_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
35527  #define R_I3C0_DATBAS3_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
35528  #define R_I3C0_DATBAS3_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
35529  #define R_I3C0_DATBAS3_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
35530  #define R_I3C0_DATBAS3_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
35531 /* =======================================================  EXDATBAS  ======================================================== */
35532  #define R_I3C0_EXDATBAS_EDSTAD_Pos     (0UL)          /*!< EDSTAD (Bit 0)                                        */
35533  #define R_I3C0_EXDATBAS_EDSTAD_Msk     (0x7fUL)       /*!< EDSTAD (Bitfield-Mask: 0x7f)                          */
35534  #define R_I3C0_EXDATBAS_EDDYAD_Pos     (16UL)         /*!< EDDYAD (Bit 16)                                       */
35535  #define R_I3C0_EXDATBAS_EDDYAD_Msk     (0xff0000UL)   /*!< EDDYAD (Bitfield-Mask: 0xff)                          */
35536  #define R_I3C0_EXDATBAS_EDNACK_Pos     (29UL)         /*!< EDNACK (Bit 29)                                       */
35537  #define R_I3C0_EXDATBAS_EDNACK_Msk     (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03)                          */
35538  #define R_I3C0_EXDATBAS_EDTYP_Pos      (31UL)         /*!< EDTYP (Bit 31)                                        */
35539  #define R_I3C0_EXDATBAS_EDTYP_Msk      (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01)                           */
35540 /* =======================================================  SDATBAS0  ======================================================== */
35541  #define R_I3C0_SDATBAS0_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
35542  #define R_I3C0_SDATBAS0_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
35543  #define R_I3C0_SDATBAS0_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
35544  #define R_I3C0_SDATBAS0_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
35545  #define R_I3C0_SDATBAS0_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
35546  #define R_I3C0_SDATBAS0_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
35547  #define R_I3C0_SDATBAS0_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
35548  #define R_I3C0_SDATBAS0_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
35549 /* =======================================================  SDATBAS1  ======================================================== */
35550  #define R_I3C0_SDATBAS1_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
35551  #define R_I3C0_SDATBAS1_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
35552  #define R_I3C0_SDATBAS1_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
35553  #define R_I3C0_SDATBAS1_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
35554  #define R_I3C0_SDATBAS1_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
35555  #define R_I3C0_SDATBAS1_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
35556  #define R_I3C0_SDATBAS1_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
35557  #define R_I3C0_SDATBAS1_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
35558 /* =======================================================  SDATBAS2  ======================================================== */
35559  #define R_I3C0_SDATBAS2_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
35560  #define R_I3C0_SDATBAS2_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
35561  #define R_I3C0_SDATBAS2_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
35562  #define R_I3C0_SDATBAS2_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
35563  #define R_I3C0_SDATBAS2_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
35564  #define R_I3C0_SDATBAS2_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
35565  #define R_I3C0_SDATBAS2_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
35566  #define R_I3C0_SDATBAS2_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
35567 /* ========================================================  MSDCT0  ========================================================= */
35568  #define R_I3C0_MSDCT0_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
35569  #define R_I3C0_MSDCT0_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
35570  #define R_I3C0_MSDCT0_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
35571  #define R_I3C0_MSDCT0_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
35572  #define R_I3C0_MSDCT0_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
35573  #define R_I3C0_MSDCT0_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
35574  #define R_I3C0_MSDCT0_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
35575  #define R_I3C0_MSDCT0_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
35576  #define R_I3C0_MSDCT0_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
35577  #define R_I3C0_MSDCT0_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
35578 /* ========================================================  MSDCT1  ========================================================= */
35579  #define R_I3C0_MSDCT1_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
35580  #define R_I3C0_MSDCT1_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
35581  #define R_I3C0_MSDCT1_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
35582  #define R_I3C0_MSDCT1_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
35583  #define R_I3C0_MSDCT1_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
35584  #define R_I3C0_MSDCT1_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
35585  #define R_I3C0_MSDCT1_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
35586  #define R_I3C0_MSDCT1_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
35587  #define R_I3C0_MSDCT1_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
35588  #define R_I3C0_MSDCT1_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
35589 /* ========================================================  MSDCT2  ========================================================= */
35590  #define R_I3C0_MSDCT2_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
35591  #define R_I3C0_MSDCT2_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
35592  #define R_I3C0_MSDCT2_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
35593  #define R_I3C0_MSDCT2_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
35594  #define R_I3C0_MSDCT2_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
35595  #define R_I3C0_MSDCT2_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
35596  #define R_I3C0_MSDCT2_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
35597  #define R_I3C0_MSDCT2_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
35598  #define R_I3C0_MSDCT2_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
35599  #define R_I3C0_MSDCT2_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
35600 /* ========================================================  MSDCT3  ========================================================= */
35601  #define R_I3C0_MSDCT3_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
35602  #define R_I3C0_MSDCT3_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
35603  #define R_I3C0_MSDCT3_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
35604  #define R_I3C0_MSDCT3_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
35605  #define R_I3C0_MSDCT3_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
35606  #define R_I3C0_MSDCT3_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
35607  #define R_I3C0_MSDCT3_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
35608  #define R_I3C0_MSDCT3_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
35609  #define R_I3C0_MSDCT3_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
35610  #define R_I3C0_MSDCT3_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
35611 /* =========================================================  SVDCT  ========================================================= */
35612  #define R_I3C0_SVDCT_TDCR_Pos          (0UL)          /*!< TDCR (Bit 0)                                          */
35613  #define R_I3C0_SVDCT_TDCR_Msk          (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
35614  #define R_I3C0_SVDCT_TBCR0_Pos         (8UL)          /*!< TBCR0 (Bit 8)                                         */
35615  #define R_I3C0_SVDCT_TBCR0_Msk         (0x100UL)      /*!< TBCR0 (Bitfield-Mask: 0x01)                           */
35616  #define R_I3C0_SVDCT_TBCR1_Pos         (9UL)          /*!< TBCR1 (Bit 9)                                         */
35617  #define R_I3C0_SVDCT_TBCR1_Msk         (0x200UL)      /*!< TBCR1 (Bitfield-Mask: 0x01)                           */
35618  #define R_I3C0_SVDCT_TBCR2_Pos         (10UL)         /*!< TBCR2 (Bit 10)                                        */
35619  #define R_I3C0_SVDCT_TBCR2_Msk         (0x400UL)      /*!< TBCR2 (Bitfield-Mask: 0x01)                           */
35620  #define R_I3C0_SVDCT_TBCR3_Pos         (11UL)         /*!< TBCR3 (Bit 11)                                        */
35621  #define R_I3C0_SVDCT_TBCR3_Msk         (0x800UL)      /*!< TBCR3 (Bitfield-Mask: 0x01)                           */
35622  #define R_I3C0_SVDCT_TBCR76_Pos        (14UL)         /*!< TBCR76 (Bit 14)                                       */
35623  #define R_I3C0_SVDCT_TBCR76_Msk        (0xc000UL)     /*!< TBCR76 (Bitfield-Mask: 0x03)                          */
35624 /* =======================================================  SDCTPIDL  ======================================================== */
35625 /* =======================================================  SDCTPIDH  ======================================================== */
35626 /* ========================================================  SVDVAD0  ======================================================== */
35627  #define R_I3C0_SVDVAD0_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
35628  #define R_I3C0_SVDVAD0_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
35629  #define R_I3C0_SVDVAD0_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
35630  #define R_I3C0_SVDVAD0_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
35631  #define R_I3C0_SVDVAD0_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
35632  #define R_I3C0_SVDVAD0_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
35633  #define R_I3C0_SVDVAD0_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
35634  #define R_I3C0_SVDVAD0_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
35635 /* ========================================================  CSECMD  ========================================================= */
35636  #define R_I3C0_CSECMD_SVIRQE_Pos       (0UL)          /*!< SVIRQE (Bit 0)                                        */
35637  #define R_I3C0_CSECMD_SVIRQE_Msk       (0x1UL)        /*!< SVIRQE (Bitfield-Mask: 0x01)                          */
35638  #define R_I3C0_CSECMD_MSRQE_Pos        (1UL)          /*!< MSRQE (Bit 1)                                         */
35639  #define R_I3C0_CSECMD_MSRQE_Msk        (0x2UL)        /*!< MSRQE (Bitfield-Mask: 0x01)                           */
35640  #define R_I3C0_CSECMD_HJEVE_Pos        (3UL)          /*!< HJEVE (Bit 3)                                         */
35641  #define R_I3C0_CSECMD_HJEVE_Msk        (0x8UL)        /*!< HJEVE (Bitfield-Mask: 0x01)                           */
35642 /* ========================================================  CEACTST  ======================================================== */
35643  #define R_I3C0_CEACTST_ACTST_Pos       (0UL)          /*!< ACTST (Bit 0)                                         */
35644  #define R_I3C0_CEACTST_ACTST_Msk       (0xfUL)        /*!< ACTST (Bitfield-Mask: 0x0f)                           */
35645 /* =========================================================  CMWLG  ========================================================= */
35646  #define R_I3C0_CMWLG_MWLG_Pos          (0UL)          /*!< MWLG (Bit 0)                                          */
35647  #define R_I3C0_CMWLG_MWLG_Msk          (0xffffUL)     /*!< MWLG (Bitfield-Mask: 0xffff)                          */
35648 /* =========================================================  CMRLG  ========================================================= */
35649  #define R_I3C0_CMRLG_MRLG_Pos          (0UL)          /*!< MRLG (Bit 0)                                          */
35650  #define R_I3C0_CMRLG_MRLG_Msk          (0xffffUL)     /*!< MRLG (Bitfield-Mask: 0xffff)                          */
35651  #define R_I3C0_CMRLG_IBIPSZ_Pos        (16UL)         /*!< IBIPSZ (Bit 16)                                       */
35652  #define R_I3C0_CMRLG_IBIPSZ_Msk        (0xff0000UL)   /*!< IBIPSZ (Bitfield-Mask: 0xff)                          */
35653 /* ========================================================  CETSTMD  ======================================================== */
35654  #define R_I3C0_CETSTMD_TSTMD_Pos       (0UL)          /*!< TSTMD (Bit 0)                                         */
35655  #define R_I3C0_CETSTMD_TSTMD_Msk       (0xffUL)       /*!< TSTMD (Bitfield-Mask: 0xff)                           */
35656 /* ========================================================  CGDVST  ========================================================= */
35657  #define R_I3C0_CGDVST_PNDINT_Pos       (0UL)          /*!< PNDINT (Bit 0)                                        */
35658  #define R_I3C0_CGDVST_PNDINT_Msk       (0xfUL)        /*!< PNDINT (Bitfield-Mask: 0x0f)                          */
35659  #define R_I3C0_CGDVST_PRTE_Pos         (5UL)          /*!< PRTE (Bit 5)                                          */
35660  #define R_I3C0_CGDVST_PRTE_Msk         (0x20UL)       /*!< PRTE (Bitfield-Mask: 0x01)                            */
35661  #define R_I3C0_CGDVST_ACTMD_Pos        (6UL)          /*!< ACTMD (Bit 6)                                         */
35662  #define R_I3C0_CGDVST_ACTMD_Msk        (0xc0UL)       /*!< ACTMD (Bitfield-Mask: 0x03)                           */
35663  #define R_I3C0_CGDVST_VDRSV_Pos        (8UL)          /*!< VDRSV (Bit 8)                                         */
35664  #define R_I3C0_CGDVST_VDRSV_Msk        (0xff00UL)     /*!< VDRSV (Bitfield-Mask: 0xff)                           */
35665 /* ========================================================  CMDSPW  ========================================================= */
35666  #define R_I3C0_CMDSPW_MSWDR_Pos        (0UL)          /*!< MSWDR (Bit 0)                                         */
35667  #define R_I3C0_CMDSPW_MSWDR_Msk        (0x7UL)        /*!< MSWDR (Bitfield-Mask: 0x07)                           */
35668 /* ========================================================  CMDSPR  ========================================================= */
35669  #define R_I3C0_CMDSPR_MSRDR_Pos        (0UL)          /*!< MSRDR (Bit 0)                                         */
35670  #define R_I3C0_CMDSPR_MSRDR_Msk        (0x7UL)        /*!< MSRDR (Bitfield-Mask: 0x07)                           */
35671  #define R_I3C0_CMDSPR_CDTTIM_Pos       (3UL)          /*!< CDTTIM (Bit 3)                                        */
35672  #define R_I3C0_CMDSPR_CDTTIM_Msk       (0x38UL)       /*!< CDTTIM (Bitfield-Mask: 0x07)                          */
35673 /* ========================================================  CMDSPT  ========================================================= */
35674  #define R_I3C0_CMDSPT_MRTTIM_Pos       (0UL)          /*!< MRTTIM (Bit 0)                                        */
35675  #define R_I3C0_CMDSPT_MRTTIM_Msk       (0xffffffUL)   /*!< MRTTIM (Bitfield-Mask: 0xffffff)                      */
35676  #define R_I3C0_CMDSPT_MRTE_Pos         (31UL)         /*!< MRTE (Bit 31)                                         */
35677  #define R_I3C0_CMDSPT_MRTE_Msk         (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01)                            */
35678 /* =========================================================  CETSM  ========================================================= */
35679  #define R_I3C0_CETSM_FREQ_Pos          (8UL)          /*!< FREQ (Bit 8)                                          */
35680  #define R_I3C0_CETSM_FREQ_Msk          (0xff00UL)     /*!< FREQ (Bitfield-Mask: 0xff)                            */
35681  #define R_I3C0_CETSM_INAC_Pos          (16UL)         /*!< INAC (Bit 16)                                         */
35682  #define R_I3C0_CETSM_INAC_Msk          (0xff0000UL)   /*!< INAC (Bitfield-Mask: 0xff)                            */
35683 /* ========================================================  BITCNT  ========================================================= */
35684  #define R_I3C0_BITCNT_BCNT_Pos         (0UL)          /*!< BCNT (Bit 0)                                          */
35685  #define R_I3C0_BITCNT_BCNT_Msk         (0x1fUL)       /*!< BCNT (Bitfield-Mask: 0x1f)                            */
35686  #define R_I3C0_BITCNT_BCNTWP_Pos       (7UL)          /*!< BCNTWP (Bit 7)                                        */
35687  #define R_I3C0_BITCNT_BCNTWP_Msk       (0x80UL)       /*!< BCNTWP (Bitfield-Mask: 0x01)                          */
35688 /* ========================================================  NQSTLV  ========================================================= */
35689  #define R_I3C0_NQSTLV_CMDQFLV_Pos      (0UL)          /*!< CMDQFLV (Bit 0)                                       */
35690  #define R_I3C0_NQSTLV_CMDQFLV_Msk      (0xffUL)       /*!< CMDQFLV (Bitfield-Mask: 0xff)                         */
35691  #define R_I3C0_NQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
35692  #define R_I3C0_NQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
35693  #define R_I3C0_NQSTLV_IBIQLV_Pos       (16UL)         /*!< IBIQLV (Bit 16)                                       */
35694  #define R_I3C0_NQSTLV_IBIQLV_Msk       (0xff0000UL)   /*!< IBIQLV (Bitfield-Mask: 0xff)                          */
35695  #define R_I3C0_NQSTLV_IBISCNT_Pos      (24UL)         /*!< IBISCNT (Bit 24)                                      */
35696  #define R_I3C0_NQSTLV_IBISCNT_Msk      (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f)                         */
35697 /* =======================================================  NDBSTLV0  ======================================================== */
35698  #define R_I3C0_NDBSTLV0_TDBFLV_Pos     (0UL)          /*!< TDBFLV (Bit 0)                                        */
35699  #define R_I3C0_NDBSTLV0_TDBFLV_Msk     (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
35700  #define R_I3C0_NDBSTLV0_RDBLV_Pos      (8UL)          /*!< RDBLV (Bit 8)                                         */
35701  #define R_I3C0_NDBSTLV0_RDBLV_Msk      (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
35702 /* =======================================================  NRSQSTLV  ======================================================== */
35703  #define R_I3C0_NRSQSTLV_RSQLV_Pos      (0UL)          /*!< RSQLV (Bit 0)                                         */
35704  #define R_I3C0_NRSQSTLV_RSQLV_Msk      (0xffUL)       /*!< RSQLV (Bitfield-Mask: 0xff)                           */
35705 /* ========================================================  PRSTDBG  ======================================================== */
35706  #define R_I3C0_PRSTDBG_SCILV_Pos       (0UL)          /*!< SCILV (Bit 0)                                         */
35707  #define R_I3C0_PRSTDBG_SCILV_Msk       (0x1UL)        /*!< SCILV (Bitfield-Mask: 0x01)                           */
35708  #define R_I3C0_PRSTDBG_SDILV_Pos       (1UL)          /*!< SDILV (Bit 1)                                         */
35709  #define R_I3C0_PRSTDBG_SDILV_Msk       (0x2UL)        /*!< SDILV (Bitfield-Mask: 0x01)                           */
35710  #define R_I3C0_PRSTDBG_SCOLV_Pos       (2UL)          /*!< SCOLV (Bit 2)                                         */
35711  #define R_I3C0_PRSTDBG_SCOLV_Msk       (0x4UL)        /*!< SCOLV (Bitfield-Mask: 0x01)                           */
35712  #define R_I3C0_PRSTDBG_SDOLV_Pos       (3UL)          /*!< SDOLV (Bit 3)                                         */
35713  #define R_I3C0_PRSTDBG_SDOLV_Msk       (0x8UL)        /*!< SDOLV (Bitfield-Mask: 0x01)                           */
35714 /* =======================================================  MSERRCNT  ======================================================== */
35715  #define R_I3C0_MSERRCNT_M2ECNT_Pos     (0UL)          /*!< M2ECNT (Bit 0)                                        */
35716  #define R_I3C0_MSERRCNT_M2ECNT_Msk     (0xffUL)       /*!< M2ECNT (Bitfield-Mask: 0xff)                          */
35717 
35718 /* =========================================================================================================================== */
35719 /* ================                                        R_MPU_MMPU                                         ================ */
35720 /* =========================================================================================================================== */
35721 
35722 /* ==========================================================  OAD  ========================================================== */
35723  #define R_MPU_MMPU_OAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
35724  #define R_MPU_MMPU_OAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
35725  #define R_MPU_MMPU_OAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
35726  #define R_MPU_MMPU_OAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
35727 /* =========================================================  OADPT  ========================================================= */
35728  #define R_MPU_MMPU_OADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
35729  #define R_MPU_MMPU_OADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
35730  #define R_MPU_MMPU_OADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
35731  #define R_MPU_MMPU_OADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
35732 
35733 /* =========================================================================================================================== */
35734 /* ================                                        R_MPU_SPMON                                        ================ */
35735 /* =========================================================================================================================== */
35736 
35737 /* =========================================================================================================================== */
35738 /* ================                                          R_MSTP                                           ================ */
35739 /* =========================================================================================================================== */
35740 
35741 /* ========================================================  MSTPCRA  ======================================================== */
35742  #define R_MSTP_MSTPCRA_MSTPA_Pos        (0UL)      /*!< MSTPA (Bit 0)                                         */
35743  #define R_MSTP_MSTPCRA_MSTPA_Msk        (0x1UL)    /*!< MSTPA (Bitfield-Mask: 0x01)                           */
35744 /* ========================================================  MSTPCRB  ======================================================== */
35745  #define R_MSTP_MSTPCRB_MSTPB_Pos        (0UL)      /*!< MSTPB (Bit 0)                                         */
35746  #define R_MSTP_MSTPCRB_MSTPB_Msk        (0x1UL)    /*!< MSTPB (Bitfield-Mask: 0x01)                           */
35747 /* ========================================================  MSTPCRC  ======================================================== */
35748  #define R_MSTP_MSTPCRC_MSTPC_Pos        (0UL)      /*!< MSTPC (Bit 0)                                         */
35749  #define R_MSTP_MSTPCRC_MSTPC_Msk        (0x1UL)    /*!< MSTPC (Bitfield-Mask: 0x01)                           */
35750 /* ========================================================  MSTPCRD  ======================================================== */
35751  #define R_MSTP_MSTPCRD_MSTPD_Pos        (0UL)      /*!< MSTPD (Bit 0)                                         */
35752  #define R_MSTP_MSTPCRD_MSTPD_Msk        (0x1UL)    /*!< MSTPD (Bitfield-Mask: 0x01)                           */
35753 /* ========================================================  MSTPCRE  ======================================================== */
35754  #define R_MSTP_MSTPCRE_MSTPE_Pos        (0UL)      /*!< MSTPE (Bit 0)                                         */
35755  #define R_MSTP_MSTPCRE_MSTPE_Msk        (0x1UL)    /*!< MSTPE (Bitfield-Mask: 0x01)                           */
35756 /* =======================================================  LSMRWDIS  ======================================================== */
35757  #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos    (0UL)      /*!< RTCRWDIS (Bit 0)                                      */
35758  #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk    (0x1UL)    /*!< RTCRWDIS (Bitfield-Mask: 0x01)                        */
35759  #define R_MSTP_LSMRWDIS_WDTDIS_Pos      (1UL)      /*!< WDTDIS (Bit 1)                                        */
35760  #define R_MSTP_LSMRWDIS_WDTDIS_Msk      (0x2UL)    /*!< WDTDIS (Bitfield-Mask: 0x01)                          */
35761  #define R_MSTP_LSMRWDIS_IWDTIDS_Pos     (2UL)      /*!< IWDTIDS (Bit 2)                                       */
35762  #define R_MSTP_LSMRWDIS_IWDTIDS_Msk     (0x4UL)    /*!< IWDTIDS (Bitfield-Mask: 0x01)                         */
35763  #define R_MSTP_LSMRWDIS_WREN_Pos        (7UL)      /*!< WREN (Bit 7)                                          */
35764  #define R_MSTP_LSMRWDIS_WREN_Msk        (0x80UL)   /*!< WREN (Bitfield-Mask: 0x01)                            */
35765  #define R_MSTP_LSMRWDIS_PRKEY_Pos       (8UL)      /*!< PRKEY (Bit 8)                                         */
35766  #define R_MSTP_LSMRWDIS_PRKEY_Msk       (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
35767 
35768 /* =========================================================================================================================== */
35769 /* ================                                          R_PORT0                                          ================ */
35770 /* =========================================================================================================================== */
35771 
35772 /* ========================================================  PCNTR1  ========================================================= */
35773  #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
35774  #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
35775  #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
35776  #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
35777 /* ==========================================================  PDR  ========================================================== */
35778  #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
35779  #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
35780 /* =========================================================  PODR  ========================================================== */
35781  #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
35782  #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
35783 /* ========================================================  PCNTR2  ========================================================= */
35784  #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
35785  #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
35786  #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
35787  #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
35788 /* =========================================================  PIDR  ========================================================== */
35789  #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
35790  #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
35791 /* =========================================================  EIDR  ========================================================== */
35792  #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
35793  #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
35794 /* ========================================================  PCNTR3  ========================================================= */
35795  #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
35796  #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
35797  #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
35798  #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
35799 /* =========================================================  POSR  ========================================================== */
35800  #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
35801  #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
35802 /* =========================================================  PORR  ========================================================== */
35803  #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
35804  #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
35805 /* ========================================================  PCNTR4  ========================================================= */
35806  #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
35807  #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
35808  #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
35809  #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
35810 /* =========================================================  EOSR  ========================================================== */
35811  #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
35812  #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
35813 /* =========================================================  EORR  ========================================================== */
35814  #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
35815  #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
35816 
35817 /* =========================================================================================================================== */
35818 /* ================                                           R_PFS                                           ================ */
35819 /* =========================================================================================================================== */
35820 
35821 /* =========================================================================================================================== */
35822 /* ================                                          R_PMISC                                          ================ */
35823 /* =========================================================================================================================== */
35824 
35825 /* ========================================================  PFENET  ========================================================= */
35826  #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
35827  #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
35828 /* =========================================================  PWPR  ========================================================== */
35829  #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
35830  #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
35831  #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
35832  #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
35833 /* =========================================================  PWPRS  ========================================================= */
35834  #define R_PMISC_PWPRS_PFSWE_Pos        (6UL)    /*!< PFSWE (Bit 6)                                         */
35835  #define R_PMISC_PWPRS_PFSWE_Msk        (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
35836  #define R_PMISC_PWPRS_B0WI_Pos         (7UL)    /*!< B0WI (Bit 7)                                          */
35837  #define R_PMISC_PWPRS_B0WI_Msk         (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
35838 
35839 /* =========================================================================================================================== */
35840 /* ================                                           R_RTC                                           ================ */
35841 /* =========================================================================================================================== */
35842 
35843 /* ========================================================  R64CNT  ========================================================= */
35844  #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
35845  #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
35846  #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
35847  #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
35848  #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
35849  #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
35850  #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
35851  #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
35852  #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
35853  #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
35854  #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
35855  #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
35856  #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
35857  #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
35858 /* =========================================================  BCNT0  ========================================================= */
35859  #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
35860  #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
35861 /* ========================================================  RSECCNT  ======================================================== */
35862  #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
35863  #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
35864  #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
35865  #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
35866 /* =========================================================  BCNT1  ========================================================= */
35867  #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
35868  #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
35869 /* ========================================================  RMINCNT  ======================================================== */
35870  #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
35871  #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
35872  #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
35873  #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
35874 /* =========================================================  BCNT2  ========================================================= */
35875  #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
35876  #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
35877 /* ========================================================  RHRCNT  ========================================================= */
35878  #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
35879  #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
35880  #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
35881  #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
35882  #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
35883  #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
35884 /* =========================================================  BCNT3  ========================================================= */
35885  #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
35886  #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
35887 /* ========================================================  RWKCNT  ========================================================= */
35888  #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
35889  #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
35890 /* ========================================================  RDAYCNT  ======================================================== */
35891  #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
35892  #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
35893  #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
35894  #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
35895 /* ========================================================  RMONCNT  ======================================================== */
35896  #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
35897  #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
35898  #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
35899  #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
35900 /* ========================================================  RYRCNT  ========================================================= */
35901  #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
35902  #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
35903  #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
35904  #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
35905 /* ========================================================  BCNT0AR  ======================================================== */
35906  #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
35907  #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
35908 /* ========================================================  RSECAR  ========================================================= */
35909  #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
35910  #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
35911  #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
35912  #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
35913  #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
35914  #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
35915 /* ========================================================  BCNT1AR  ======================================================== */
35916  #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
35917  #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
35918 /* ========================================================  RMINAR  ========================================================= */
35919  #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
35920  #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
35921  #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
35922  #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
35923  #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
35924  #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
35925 /* ========================================================  BCNT2AR  ======================================================== */
35926  #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
35927  #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
35928 /* =========================================================  RHRAR  ========================================================= */
35929  #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
35930  #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
35931  #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
35932  #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
35933  #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
35934  #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
35935  #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
35936  #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
35937 /* ========================================================  BCNT3AR  ======================================================== */
35938  #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
35939  #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
35940 /* =========================================================  RWKAR  ========================================================= */
35941  #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
35942  #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
35943  #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
35944  #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
35945 /* =======================================================  BCNT0AER  ======================================================== */
35946  #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
35947  #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
35948 /* ========================================================  RDAYAR  ========================================================= */
35949  #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
35950  #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
35951  #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
35952  #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
35953  #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
35954  #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
35955 /* =======================================================  BCNT1AER  ======================================================== */
35956  #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
35957  #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
35958 /* ========================================================  RMONAR  ========================================================= */
35959  #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
35960  #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
35961  #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
35962  #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
35963  #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
35964  #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
35965 /* =======================================================  BCNT2AER  ======================================================== */
35966  #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
35967  #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
35968 /* =========================================================  RYRAR  ========================================================= */
35969  #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
35970  #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
35971  #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
35972  #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
35973 /* =======================================================  BCNT3AER  ======================================================== */
35974  #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
35975  #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
35976 /* ========================================================  RYRAREN  ======================================================== */
35977  #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
35978  #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
35979 /* =========================================================  RCR1  ========================================================== */
35980  #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
35981  #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
35982  #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
35983  #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
35984  #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
35985  #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
35986  #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
35987  #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
35988  #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
35989  #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
35990 /* =========================================================  RCR2  ========================================================== */
35991  #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
35992  #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
35993  #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
35994  #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
35995  #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
35996  #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
35997  #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
35998  #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
35999  #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
36000  #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
36001  #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
36002  #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
36003  #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
36004  #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
36005  #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
36006  #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
36007 /* =========================================================  RCR4  ========================================================== */
36008  #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
36009  #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
36010  #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
36011  #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
36012 /* =========================================================  RFRH  ========================================================== */
36013  #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
36014  #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
36015 /* =========================================================  RFRL  ========================================================== */
36016  #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
36017  #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
36018 /* =========================================================  RADJ  ========================================================== */
36019  #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
36020  #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
36021  #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
36022  #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
36023 
36024 /* =========================================================================================================================== */
36025 /* ================                                          R_SCI0                                           ================ */
36026 /* =========================================================================================================================== */
36027 
36028 /* ==========================================================  SMR  ========================================================== */
36029  #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
36030  #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
36031  #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
36032  #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
36033  #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
36034  #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
36035  #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
36036  #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
36037  #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
36038  #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
36039  #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
36040  #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
36041  #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
36042  #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
36043 /* =======================================================  SMR_SMCI  ======================================================== */
36044  #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
36045  #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
36046  #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
36047  #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
36048  #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
36049  #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
36050  #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
36051  #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
36052  #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
36053  #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
36054  #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
36055  #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
36056 /* ==========================================================  BRR  ========================================================== */
36057  #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
36058  #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
36059 /* ==========================================================  SCR  ========================================================== */
36060  #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
36061  #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
36062  #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
36063  #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
36064  #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
36065  #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
36066  #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
36067  #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
36068  #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
36069  #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
36070  #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
36071  #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
36072  #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
36073  #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
36074 /* =======================================================  SCR_SMCI  ======================================================== */
36075  #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
36076  #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
36077  #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
36078  #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
36079  #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
36080  #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
36081  #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
36082  #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
36083  #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
36084  #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
36085  #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
36086  #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
36087  #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
36088  #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
36089 /* ==========================================================  TDR  ========================================================== */
36090  #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
36091  #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
36092 /* ==========================================================  SSR  ========================================================== */
36093  #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
36094  #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
36095  #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
36096  #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
36097  #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
36098  #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
36099  #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
36100  #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
36101  #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
36102  #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
36103  #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
36104  #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
36105  #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
36106  #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
36107  #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
36108  #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
36109 /* =======================================================  SSR_FIFO  ======================================================== */
36110  #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
36111  #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
36112  #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
36113  #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
36114  #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
36115  #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
36116  #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
36117  #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
36118  #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
36119  #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
36120  #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
36121  #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
36122  #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
36123  #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
36124 /* =======================================================  SSR_SMCI  ======================================================== */
36125  #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
36126  #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
36127  #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
36128  #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
36129  #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
36130  #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
36131  #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
36132  #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
36133  #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
36134  #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
36135  #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
36136  #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
36137  #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
36138  #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
36139  #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
36140  #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
36141 /* ==========================================================  RDR  ========================================================== */
36142  #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
36143  #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
36144 /* =========================================================  SCMR  ========================================================== */
36145  #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
36146  #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
36147  #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
36148  #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
36149  #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
36150  #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
36151  #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
36152  #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
36153  #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
36154  #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
36155 /* =========================================================  SEMR  ========================================================== */
36156  #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
36157  #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
36158  #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
36159  #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
36160  #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
36161  #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
36162  #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
36163  #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
36164  #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
36165  #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
36166  #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
36167  #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
36168  #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
36169  #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
36170  #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
36171  #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
36172 /* =========================================================  SNFR  ========================================================== */
36173  #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
36174  #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
36175 /* =========================================================  SIMR1  ========================================================= */
36176  #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
36177  #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
36178  #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
36179  #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
36180 /* =========================================================  SIMR2  ========================================================= */
36181  #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
36182  #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
36183  #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
36184  #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
36185  #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
36186  #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
36187 /* =========================================================  SIMR3  ========================================================= */
36188  #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
36189  #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
36190  #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
36191  #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
36192  #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
36193  #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
36194  #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
36195  #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
36196  #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
36197  #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
36198  #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
36199  #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
36200 /* =========================================================  SISR  ========================================================== */
36201  #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
36202  #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
36203 /* =========================================================  SPMR  ========================================================== */
36204  #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
36205  #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
36206  #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
36207  #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
36208  #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
36209  #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
36210  #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
36211  #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
36212  #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
36213  #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
36214  #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
36215  #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
36216  #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
36217  #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
36218 /* =========================================================  TDRHL  ========================================================= */
36219  #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
36220  #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
36221 /* ========================================================  FTDRHL  ========================================================= */
36222  #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
36223  #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
36224  #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
36225  #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
36226 /* =========================================================  FTDRH  ========================================================= */
36227  #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
36228  #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
36229  #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
36230  #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
36231 /* =========================================================  FTDRL  ========================================================= */
36232  #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
36233  #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
36234 /* =========================================================  RDRHL  ========================================================= */
36235  #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
36236  #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
36237 /* ========================================================  FRDRHL  ========================================================= */
36238  #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
36239  #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
36240  #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
36241  #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
36242  #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
36243  #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
36244  #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
36245  #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
36246  #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
36247  #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
36248  #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
36249  #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
36250  #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
36251  #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
36252 /* =========================================================  FRDRH  ========================================================= */
36253  #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
36254  #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
36255  #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
36256  #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
36257  #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
36258  #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
36259  #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
36260  #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
36261  #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
36262  #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
36263  #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
36264  #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
36265  #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
36266  #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
36267 /* =========================================================  FRDRL  ========================================================= */
36268  #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
36269  #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
36270 /* =========================================================  MDDR  ========================================================== */
36271  #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
36272  #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
36273 /* =========================================================  DCCR  ========================================================== */
36274  #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
36275  #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
36276  #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
36277  #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
36278  #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
36279  #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
36280  #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
36281  #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
36282  #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
36283  #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
36284 /* ==========================================================  FCR  ========================================================== */
36285  #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
36286  #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
36287  #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
36288  #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
36289  #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
36290  #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
36291  #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
36292  #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
36293  #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
36294  #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
36295  #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
36296  #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
36297  #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
36298  #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
36299 /* ==========================================================  FDR  ========================================================== */
36300  #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
36301  #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
36302  #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
36303  #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
36304 /* ==========================================================  LSR  ========================================================== */
36305  #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
36306  #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
36307  #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
36308  #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
36309  #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
36310  #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
36311 /* ==========================================================  CDR  ========================================================== */
36312  #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
36313  #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
36314 /* =========================================================  SPTR  ========================================================== */
36315  #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
36316  #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
36317  #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
36318  #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
36319  #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
36320  #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
36321  #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
36322  #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
36323  #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
36324  #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
36325  #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
36326  #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
36327  #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
36328  #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
36329 /* =========================================================  ACTR  ========================================================== */
36330  #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
36331  #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
36332  #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
36333  #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
36334  #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
36335  #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
36336  #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
36337  #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
36338 /* =========================================================  ESMER  ========================================================= */
36339  #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
36340  #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
36341 /* ==========================================================  CR0  ========================================================== */
36342  #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
36343  #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
36344  #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
36345  #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
36346  #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
36347  #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
36348 /* ==========================================================  CR1  ========================================================== */
36349  #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
36350  #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
36351  #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
36352  #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
36353  #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
36354  #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
36355  #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
36356  #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
36357  #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
36358  #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
36359 /* ==========================================================  CR2  ========================================================== */
36360  #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
36361  #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
36362  #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
36363  #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
36364  #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
36365  #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
36366 /* ==========================================================  CR3  ========================================================== */
36367  #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
36368  #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
36369 /* ==========================================================  PCR  ========================================================== */
36370  #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
36371  #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
36372  #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
36373  #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
36374  #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
36375  #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
36376 /* ==========================================================  ICR  ========================================================== */
36377  #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
36378  #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
36379  #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
36380  #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
36381  #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
36382  #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
36383  #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
36384  #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
36385  #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
36386  #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
36387  #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
36388  #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
36389 /* ==========================================================  STR  ========================================================== */
36390  #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
36391  #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
36392  #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
36393  #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
36394  #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
36395  #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
36396  #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
36397  #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
36398  #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
36399  #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
36400  #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
36401  #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
36402 /* =========================================================  STCR  ========================================================== */
36403  #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
36404  #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
36405  #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
36406  #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
36407  #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
36408  #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
36409  #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
36410  #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
36411  #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
36412  #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
36413  #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
36414  #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
36415 /* =========================================================  CF0DR  ========================================================= */
36416 /* =========================================================  CF0CR  ========================================================= */
36417  #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
36418  #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
36419  #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
36420  #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
36421  #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
36422  #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
36423  #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
36424  #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
36425  #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
36426  #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
36427  #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
36428  #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
36429  #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
36430  #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
36431  #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
36432  #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
36433 /* =========================================================  CF0RR  ========================================================= */
36434 /* ========================================================  PCF1DR  ========================================================= */
36435 /* ========================================================  SCF1DR  ========================================================= */
36436 /* =========================================================  CF1CR  ========================================================= */
36437  #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
36438  #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
36439  #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
36440  #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
36441  #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
36442  #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
36443  #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
36444  #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
36445  #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
36446  #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
36447  #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
36448  #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
36449  #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
36450  #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
36451  #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
36452  #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
36453 /* =========================================================  CF1RR  ========================================================= */
36454 /* ==========================================================  TCR  ========================================================== */
36455  #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
36456  #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
36457 /* ==========================================================  TMR  ========================================================== */
36458  #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
36459  #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
36460  #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
36461  #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
36462  #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
36463  #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
36464 /* =========================================================  TPRE  ========================================================== */
36465 /* =========================================================  TCNT  ========================================================== */
36466 
36467 /* =========================================================================================================================== */
36468 /* ================                                          R_SDHI0                                          ================ */
36469 /* =========================================================================================================================== */
36470 
36471 /* ========================================================  SD_CMD  ========================================================= */
36472  #define R_SDHI0_SD_CMD_CMD12AT_Pos              (14UL)         /*!< CMD12AT (Bit 14)                                      */
36473  #define R_SDHI0_SD_CMD_CMD12AT_Msk              (0xc000UL)     /*!< CMD12AT (Bitfield-Mask: 0x03)                         */
36474  #define R_SDHI0_SD_CMD_TRSTP_Pos                (13UL)         /*!< TRSTP (Bit 13)                                        */
36475  #define R_SDHI0_SD_CMD_TRSTP_Msk                (0x2000UL)     /*!< TRSTP (Bitfield-Mask: 0x01)                           */
36476  #define R_SDHI0_SD_CMD_CMDRW_Pos                (12UL)         /*!< CMDRW (Bit 12)                                        */
36477  #define R_SDHI0_SD_CMD_CMDRW_Msk                (0x1000UL)     /*!< CMDRW (Bitfield-Mask: 0x01)                           */
36478  #define R_SDHI0_SD_CMD_CMDTP_Pos                (11UL)         /*!< CMDTP (Bit 11)                                        */
36479  #define R_SDHI0_SD_CMD_CMDTP_Msk                (0x800UL)      /*!< CMDTP (Bitfield-Mask: 0x01)                           */
36480  #define R_SDHI0_SD_CMD_RSPTP_Pos                (8UL)          /*!< RSPTP (Bit 8)                                         */
36481  #define R_SDHI0_SD_CMD_RSPTP_Msk                (0x700UL)      /*!< RSPTP (Bitfield-Mask: 0x07)                           */
36482  #define R_SDHI0_SD_CMD_ACMD_Pos                 (6UL)          /*!< ACMD (Bit 6)                                          */
36483  #define R_SDHI0_SD_CMD_ACMD_Msk                 (0xc0UL)       /*!< ACMD (Bitfield-Mask: 0x03)                            */
36484  #define R_SDHI0_SD_CMD_CMDIDX_Pos               (0UL)          /*!< CMDIDX (Bit 0)                                        */
36485  #define R_SDHI0_SD_CMD_CMDIDX_Msk               (0x3fUL)       /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
36486 /* ========================================================  SD_ARG  ========================================================= */
36487  #define R_SDHI0_SD_ARG_SD_ARG_Pos               (0UL)          /*!< SD_ARG (Bit 0)                                        */
36488  #define R_SDHI0_SD_ARG_SD_ARG_Msk               (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff)                    */
36489 /* ========================================================  SD_ARG1  ======================================================== */
36490  #define R_SDHI0_SD_ARG1_SD_ARG1_Pos             (0UL)          /*!< SD_ARG1 (Bit 0)                                       */
36491  #define R_SDHI0_SD_ARG1_SD_ARG1_Msk             (0xffffUL)     /*!< SD_ARG1 (Bitfield-Mask: 0xffff)                       */
36492 /* ========================================================  SD_STOP  ======================================================== */
36493  #define R_SDHI0_SD_STOP_SEC_Pos                 (8UL)          /*!< SEC (Bit 8)                                           */
36494  #define R_SDHI0_SD_STOP_SEC_Msk                 (0x100UL)      /*!< SEC (Bitfield-Mask: 0x01)                             */
36495  #define R_SDHI0_SD_STOP_STP_Pos                 (0UL)          /*!< STP (Bit 0)                                           */
36496  #define R_SDHI0_SD_STOP_STP_Msk                 (0x1UL)        /*!< STP (Bitfield-Mask: 0x01)                             */
36497 /* =======================================================  SD_SECCNT  ======================================================= */
36498  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos         (0UL)          /*!< SD_SECCNT (Bit 0)                                     */
36499  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk         (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff)                 */
36500 /* =======================================================  SD_RSP10  ======================================================== */
36501  #define R_SDHI0_SD_RSP10_SD_RSP10_Pos           (0UL)          /*!< SD_RSP10 (Bit 0)                                      */
36502  #define R_SDHI0_SD_RSP10_SD_RSP10_Msk           (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff)                  */
36503 /* ========================================================  SD_RSP1  ======================================================== */
36504  #define R_SDHI0_SD_RSP1_SD_RSP1_Pos             (0UL)          /*!< SD_RSP1 (Bit 0)                                       */
36505  #define R_SDHI0_SD_RSP1_SD_RSP1_Msk             (0xffffUL)     /*!< SD_RSP1 (Bitfield-Mask: 0xffff)                       */
36506 /* =======================================================  SD_RSP32  ======================================================== */
36507  #define R_SDHI0_SD_RSP32_SD_RSP32_Pos           (0UL)          /*!< SD_RSP32 (Bit 0)                                      */
36508  #define R_SDHI0_SD_RSP32_SD_RSP32_Msk           (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff)                  */
36509 /* ========================================================  SD_RSP3  ======================================================== */
36510  #define R_SDHI0_SD_RSP3_SD_RSP3_Pos             (0UL)          /*!< SD_RSP3 (Bit 0)                                       */
36511  #define R_SDHI0_SD_RSP3_SD_RSP3_Msk             (0xffffUL)     /*!< SD_RSP3 (Bitfield-Mask: 0xffff)                       */
36512 /* =======================================================  SD_RSP54  ======================================================== */
36513  #define R_SDHI0_SD_RSP54_SD_RSP54_Pos           (0UL)          /*!< SD_RSP54 (Bit 0)                                      */
36514  #define R_SDHI0_SD_RSP54_SD_RSP54_Msk           (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff)                  */
36515 /* ========================================================  SD_RSP5  ======================================================== */
36516  #define R_SDHI0_SD_RSP5_SD_RSP5_Pos             (0UL)          /*!< SD_RSP5 (Bit 0)                                       */
36517  #define R_SDHI0_SD_RSP5_SD_RSP5_Msk             (0xffffUL)     /*!< SD_RSP5 (Bitfield-Mask: 0xffff)                       */
36518 /* =======================================================  SD_RSP76  ======================================================== */
36519  #define R_SDHI0_SD_RSP76_SD_RSP76_Pos           (0UL)          /*!< SD_RSP76 (Bit 0)                                      */
36520  #define R_SDHI0_SD_RSP76_SD_RSP76_Msk           (0xffffffUL)   /*!< SD_RSP76 (Bitfield-Mask: 0xffffff)                    */
36521 /* ========================================================  SD_RSP7  ======================================================== */
36522  #define R_SDHI0_SD_RSP7_SD_RSP7_Pos             (0UL)          /*!< SD_RSP7 (Bit 0)                                       */
36523  #define R_SDHI0_SD_RSP7_SD_RSP7_Msk             (0xffUL)       /*!< SD_RSP7 (Bitfield-Mask: 0xff)                         */
36524 /* =======================================================  SD_INFO1  ======================================================== */
36525  #define R_SDHI0_SD_INFO1_SDD3MON_Pos            (10UL)         /*!< SDD3MON (Bit 10)                                      */
36526  #define R_SDHI0_SD_INFO1_SDD3MON_Msk            (0x400UL)      /*!< SDD3MON (Bitfield-Mask: 0x01)                         */
36527  #define R_SDHI0_SD_INFO1_SDD3IN_Pos             (9UL)          /*!< SDD3IN (Bit 9)                                        */
36528  #define R_SDHI0_SD_INFO1_SDD3IN_Msk             (0x200UL)      /*!< SDD3IN (Bitfield-Mask: 0x01)                          */
36529  #define R_SDHI0_SD_INFO1_SDD3RM_Pos             (8UL)          /*!< SDD3RM (Bit 8)                                        */
36530  #define R_SDHI0_SD_INFO1_SDD3RM_Msk             (0x100UL)      /*!< SDD3RM (Bitfield-Mask: 0x01)                          */
36531  #define R_SDHI0_SD_INFO1_SDWPMON_Pos            (7UL)          /*!< SDWPMON (Bit 7)                                       */
36532  #define R_SDHI0_SD_INFO1_SDWPMON_Msk            (0x80UL)       /*!< SDWPMON (Bitfield-Mask: 0x01)                         */
36533  #define R_SDHI0_SD_INFO1_SDCDMON_Pos            (5UL)          /*!< SDCDMON (Bit 5)                                       */
36534  #define R_SDHI0_SD_INFO1_SDCDMON_Msk            (0x20UL)       /*!< SDCDMON (Bitfield-Mask: 0x01)                         */
36535  #define R_SDHI0_SD_INFO1_SDCDIN_Pos             (4UL)          /*!< SDCDIN (Bit 4)                                        */
36536  #define R_SDHI0_SD_INFO1_SDCDIN_Msk             (0x10UL)       /*!< SDCDIN (Bitfield-Mask: 0x01)                          */
36537  #define R_SDHI0_SD_INFO1_SDCDRM_Pos             (3UL)          /*!< SDCDRM (Bit 3)                                        */
36538  #define R_SDHI0_SD_INFO1_SDCDRM_Msk             (0x8UL)        /*!< SDCDRM (Bitfield-Mask: 0x01)                          */
36539  #define R_SDHI0_SD_INFO1_ACEND_Pos              (2UL)          /*!< ACEND (Bit 2)                                         */
36540  #define R_SDHI0_SD_INFO1_ACEND_Msk              (0x4UL)        /*!< ACEND (Bitfield-Mask: 0x01)                           */
36541  #define R_SDHI0_SD_INFO1_RSPEND_Pos             (0UL)          /*!< RSPEND (Bit 0)                                        */
36542  #define R_SDHI0_SD_INFO1_RSPEND_Msk             (0x1UL)        /*!< RSPEND (Bitfield-Mask: 0x01)                          */
36543 /* =======================================================  SD_INFO2  ======================================================== */
36544  #define R_SDHI0_SD_INFO2_ILA_Pos                (15UL)         /*!< ILA (Bit 15)                                          */
36545  #define R_SDHI0_SD_INFO2_ILA_Msk                (0x8000UL)     /*!< ILA (Bitfield-Mask: 0x01)                             */
36546  #define R_SDHI0_SD_INFO2_CBSY_Pos               (14UL)         /*!< CBSY (Bit 14)                                         */
36547  #define R_SDHI0_SD_INFO2_CBSY_Msk               (0x4000UL)     /*!< CBSY (Bitfield-Mask: 0x01)                            */
36548  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos      (13UL)         /*!< SD_CLK_CTRLEN (Bit 13)                                */
36549  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk      (0x2000UL)     /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01)                   */
36550  #define R_SDHI0_SD_INFO2_BWE_Pos                (9UL)          /*!< BWE (Bit 9)                                           */
36551  #define R_SDHI0_SD_INFO2_BWE_Msk                (0x200UL)      /*!< BWE (Bitfield-Mask: 0x01)                             */
36552  #define R_SDHI0_SD_INFO2_BRE_Pos                (8UL)          /*!< BRE (Bit 8)                                           */
36553  #define R_SDHI0_SD_INFO2_BRE_Msk                (0x100UL)      /*!< BRE (Bitfield-Mask: 0x01)                             */
36554  #define R_SDHI0_SD_INFO2_SDD0MON_Pos            (7UL)          /*!< SDD0MON (Bit 7)                                       */
36555  #define R_SDHI0_SD_INFO2_SDD0MON_Msk            (0x80UL)       /*!< SDD0MON (Bitfield-Mask: 0x01)                         */
36556  #define R_SDHI0_SD_INFO2_RSPTO_Pos              (6UL)          /*!< RSPTO (Bit 6)                                         */
36557  #define R_SDHI0_SD_INFO2_RSPTO_Msk              (0x40UL)       /*!< RSPTO (Bitfield-Mask: 0x01)                           */
36558  #define R_SDHI0_SD_INFO2_ILR_Pos                (5UL)          /*!< ILR (Bit 5)                                           */
36559  #define R_SDHI0_SD_INFO2_ILR_Msk                (0x20UL)       /*!< ILR (Bitfield-Mask: 0x01)                             */
36560  #define R_SDHI0_SD_INFO2_ILW_Pos                (4UL)          /*!< ILW (Bit 4)                                           */
36561  #define R_SDHI0_SD_INFO2_ILW_Msk                (0x10UL)       /*!< ILW (Bitfield-Mask: 0x01)                             */
36562  #define R_SDHI0_SD_INFO2_DTO_Pos                (3UL)          /*!< DTO (Bit 3)                                           */
36563  #define R_SDHI0_SD_INFO2_DTO_Msk                (0x8UL)        /*!< DTO (Bitfield-Mask: 0x01)                             */
36564  #define R_SDHI0_SD_INFO2_ENDE_Pos               (2UL)          /*!< ENDE (Bit 2)                                          */
36565  #define R_SDHI0_SD_INFO2_ENDE_Msk               (0x4UL)        /*!< ENDE (Bitfield-Mask: 0x01)                            */
36566  #define R_SDHI0_SD_INFO2_CRCE_Pos               (1UL)          /*!< CRCE (Bit 1)                                          */
36567  #define R_SDHI0_SD_INFO2_CRCE_Msk               (0x2UL)        /*!< CRCE (Bitfield-Mask: 0x01)                            */
36568  #define R_SDHI0_SD_INFO2_CMDE_Pos               (0UL)          /*!< CMDE (Bit 0)                                          */
36569  #define R_SDHI0_SD_INFO2_CMDE_Msk               (0x1UL)        /*!< CMDE (Bitfield-Mask: 0x01)                            */
36570 /* =====================================================  SD_INFO1_MASK  ===================================================== */
36571  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos       (9UL)          /*!< SDD3INM (Bit 9)                                       */
36572  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk       (0x200UL)      /*!< SDD3INM (Bitfield-Mask: 0x01)                         */
36573  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos       (8UL)          /*!< SDD3RMM (Bit 8)                                       */
36574  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk       (0x100UL)      /*!< SDD3RMM (Bitfield-Mask: 0x01)                         */
36575  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos       (4UL)          /*!< SDCDINM (Bit 4)                                       */
36576  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk       (0x10UL)       /*!< SDCDINM (Bitfield-Mask: 0x01)                         */
36577  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos       (3UL)          /*!< SDCDRMM (Bit 3)                                       */
36578  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk       (0x8UL)        /*!< SDCDRMM (Bitfield-Mask: 0x01)                         */
36579  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos        (2UL)          /*!< ACENDM (Bit 2)                                        */
36580  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk        (0x4UL)        /*!< ACENDM (Bitfield-Mask: 0x01)                          */
36581  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos       (0UL)          /*!< RSPENDM (Bit 0)                                       */
36582  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk       (0x1UL)        /*!< RSPENDM (Bitfield-Mask: 0x01)                         */
36583 /* =====================================================  SD_INFO2_MASK  ===================================================== */
36584  #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos          (15UL)         /*!< ILAM (Bit 15)                                         */
36585  #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk          (0x8000UL)     /*!< ILAM (Bitfield-Mask: 0x01)                            */
36586  #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos          (9UL)          /*!< BWEM (Bit 9)                                          */
36587  #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk          (0x200UL)      /*!< BWEM (Bitfield-Mask: 0x01)                            */
36588  #define R_SDHI0_SD_INFO2_MASK_BREM_Pos          (8UL)          /*!< BREM (Bit 8)                                          */
36589  #define R_SDHI0_SD_INFO2_MASK_BREM_Msk          (0x100UL)      /*!< BREM (Bitfield-Mask: 0x01)                            */
36590  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos        (6UL)          /*!< RSPTOM (Bit 6)                                        */
36591  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk        (0x40UL)       /*!< RSPTOM (Bitfield-Mask: 0x01)                          */
36592  #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos          (5UL)          /*!< ILRM (Bit 5)                                          */
36593  #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk          (0x20UL)       /*!< ILRM (Bitfield-Mask: 0x01)                            */
36594  #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos          (4UL)          /*!< ILWM (Bit 4)                                          */
36595  #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk          (0x10UL)       /*!< ILWM (Bitfield-Mask: 0x01)                            */
36596  #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos          (3UL)          /*!< DTOM (Bit 3)                                          */
36597  #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk          (0x8UL)        /*!< DTOM (Bitfield-Mask: 0x01)                            */
36598  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos         (2UL)          /*!< ENDEM (Bit 2)                                         */
36599  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk         (0x4UL)        /*!< ENDEM (Bitfield-Mask: 0x01)                           */
36600  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos         (1UL)          /*!< CRCEM (Bit 1)                                         */
36601  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk         (0x2UL)        /*!< CRCEM (Bitfield-Mask: 0x01)                           */
36602  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos         (0UL)          /*!< CMDEM (Bit 0)                                         */
36603  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk         (0x1UL)        /*!< CMDEM (Bitfield-Mask: 0x01)                           */
36604 /* ======================================================  SD_CLK_CTRL  ====================================================== */
36605  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos       (9UL)          /*!< CLKCTRLEN (Bit 9)                                     */
36606  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk       (0x200UL)      /*!< CLKCTRLEN (Bitfield-Mask: 0x01)                       */
36607  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos           (8UL)          /*!< CLKEN (Bit 8)                                         */
36608  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk           (0x100UL)      /*!< CLKEN (Bitfield-Mask: 0x01)                           */
36609  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos          (0UL)          /*!< CLKSEL (Bit 0)                                        */
36610  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk          (0xffUL)       /*!< CLKSEL (Bitfield-Mask: 0xff)                          */
36611 /* ========================================================  SD_SIZE  ======================================================== */
36612  #define R_SDHI0_SD_SIZE_LEN_Pos                 (0UL)          /*!< LEN (Bit 0)                                           */
36613  #define R_SDHI0_SD_SIZE_LEN_Msk                 (0x3ffUL)      /*!< LEN (Bitfield-Mask: 0x3ff)                            */
36614 /* =======================================================  SD_OPTION  ======================================================= */
36615  #define R_SDHI0_SD_OPTION_WIDTH_Pos             (15UL)         /*!< WIDTH (Bit 15)                                        */
36616  #define R_SDHI0_SD_OPTION_WIDTH_Msk             (0x8000UL)     /*!< WIDTH (Bitfield-Mask: 0x01)                           */
36617  #define R_SDHI0_SD_OPTION_WIDTH8_Pos            (13UL)         /*!< WIDTH8 (Bit 13)                                       */
36618  #define R_SDHI0_SD_OPTION_WIDTH8_Msk            (0x2000UL)     /*!< WIDTH8 (Bitfield-Mask: 0x01)                          */
36619  #define R_SDHI0_SD_OPTION_TOUTMASK_Pos          (8UL)          /*!< TOUTMASK (Bit 8)                                      */
36620  #define R_SDHI0_SD_OPTION_TOUTMASK_Msk          (0x100UL)      /*!< TOUTMASK (Bitfield-Mask: 0x01)                        */
36621  #define R_SDHI0_SD_OPTION_TOP_Pos               (4UL)          /*!< TOP (Bit 4)                                           */
36622  #define R_SDHI0_SD_OPTION_TOP_Msk               (0xf0UL)       /*!< TOP (Bitfield-Mask: 0x0f)                             */
36623  #define R_SDHI0_SD_OPTION_CTOP_Pos              (0UL)          /*!< CTOP (Bit 0)                                          */
36624  #define R_SDHI0_SD_OPTION_CTOP_Msk              (0xfUL)        /*!< CTOP (Bitfield-Mask: 0x0f)                            */
36625 /* ======================================================  SD_ERR_STS1  ====================================================== */
36626  #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos           (12UL)         /*!< CRCTK (Bit 12)                                        */
36627  #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk           (0x7000UL)     /*!< CRCTK (Bitfield-Mask: 0x07)                           */
36628  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos          (11UL)         /*!< CRCTKE (Bit 11)                                       */
36629  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk          (0x800UL)      /*!< CRCTKE (Bitfield-Mask: 0x01)                          */
36630  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos          (10UL)         /*!< RDCRCE (Bit 10)                                       */
36631  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk          (0x400UL)      /*!< RDCRCE (Bitfield-Mask: 0x01)                          */
36632  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos        (9UL)          /*!< RSPCRCE1 (Bit 9)                                      */
36633  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk        (0x200UL)      /*!< RSPCRCE1 (Bitfield-Mask: 0x01)                        */
36634  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos        (8UL)          /*!< RSPCRCE0 (Bit 8)                                      */
36635  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk        (0x100UL)      /*!< RSPCRCE0 (Bitfield-Mask: 0x01)                        */
36636  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos         (5UL)          /*!< CRCLENE (Bit 5)                                       */
36637  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk         (0x20UL)       /*!< CRCLENE (Bitfield-Mask: 0x01)                         */
36638  #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos          (4UL)          /*!< RDLENE (Bit 4)                                        */
36639  #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk          (0x10UL)       /*!< RDLENE (Bitfield-Mask: 0x01)                          */
36640  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos        (3UL)          /*!< RSPLENE1 (Bit 3)                                      */
36641  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk        (0x8UL)        /*!< RSPLENE1 (Bitfield-Mask: 0x01)                        */
36642  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos        (2UL)          /*!< RSPLENE0 (Bit 2)                                      */
36643  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk        (0x4UL)        /*!< RSPLENE0 (Bitfield-Mask: 0x01)                        */
36644  #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos           (1UL)          /*!< CMDE1 (Bit 1)                                         */
36645  #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk           (0x2UL)        /*!< CMDE1 (Bitfield-Mask: 0x01)                           */
36646  #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos           (0UL)          /*!< CMDE0 (Bit 0)                                         */
36647  #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk           (0x1UL)        /*!< CMDE0 (Bitfield-Mask: 0x01)                           */
36648 /* ======================================================  SD_ERR_STS2  ====================================================== */
36649  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos        (6UL)          /*!< CRCBSYTO (Bit 6)                                      */
36650  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk        (0x40UL)       /*!< CRCBSYTO (Bitfield-Mask: 0x01)                        */
36651  #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos           (5UL)          /*!< CRCTO (Bit 5)                                         */
36652  #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk           (0x20UL)       /*!< CRCTO (Bitfield-Mask: 0x01)                           */
36653  #define R_SDHI0_SD_ERR_STS2_RDTO_Pos            (4UL)          /*!< RDTO (Bit 4)                                          */
36654  #define R_SDHI0_SD_ERR_STS2_RDTO_Msk            (0x10UL)       /*!< RDTO (Bitfield-Mask: 0x01)                            */
36655  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos          (3UL)          /*!< BSYTO1 (Bit 3)                                        */
36656  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk          (0x8UL)        /*!< BSYTO1 (Bitfield-Mask: 0x01)                          */
36657  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos          (2UL)          /*!< BSYTO0 (Bit 2)                                        */
36658  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk          (0x4UL)        /*!< BSYTO0 (Bitfield-Mask: 0x01)                          */
36659  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos          (1UL)          /*!< RSPTO1 (Bit 1)                                        */
36660  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk          (0x2UL)        /*!< RSPTO1 (Bitfield-Mask: 0x01)                          */
36661  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos          (0UL)          /*!< RSPTO0 (Bit 0)                                        */
36662  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk          (0x1UL)        /*!< RSPTO0 (Bitfield-Mask: 0x01)                          */
36663 /* ========================================================  SD_BUF0  ======================================================== */
36664  #define R_SDHI0_SD_BUF0_SD_BUF_Pos              (0UL)          /*!< SD_BUF (Bit 0)                                        */
36665  #define R_SDHI0_SD_BUF0_SD_BUF_Msk              (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff)                    */
36666 /* =======================================================  SDIO_MODE  ======================================================= */
36667  #define R_SDHI0_SDIO_MODE_C52PUB_Pos            (9UL)          /*!< C52PUB (Bit 9)                                        */
36668  #define R_SDHI0_SDIO_MODE_C52PUB_Msk            (0x200UL)      /*!< C52PUB (Bitfield-Mask: 0x01)                          */
36669  #define R_SDHI0_SDIO_MODE_IOABT_Pos             (8UL)          /*!< IOABT (Bit 8)                                         */
36670  #define R_SDHI0_SDIO_MODE_IOABT_Msk             (0x100UL)      /*!< IOABT (Bitfield-Mask: 0x01)                           */
36671  #define R_SDHI0_SDIO_MODE_RWREQ_Pos             (2UL)          /*!< RWREQ (Bit 2)                                         */
36672  #define R_SDHI0_SDIO_MODE_RWREQ_Msk             (0x4UL)        /*!< RWREQ (Bitfield-Mask: 0x01)                           */
36673  #define R_SDHI0_SDIO_MODE_INTEN_Pos             (0UL)          /*!< INTEN (Bit 0)                                         */
36674  #define R_SDHI0_SDIO_MODE_INTEN_Msk             (0x1UL)        /*!< INTEN (Bitfield-Mask: 0x01)                           */
36675 /* ======================================================  SDIO_INFO1  ======================================================= */
36676  #define R_SDHI0_SDIO_INFO1_EXWT_Pos             (15UL)         /*!< EXWT (Bit 15)                                         */
36677  #define R_SDHI0_SDIO_INFO1_EXWT_Msk             (0x8000UL)     /*!< EXWT (Bitfield-Mask: 0x01)                            */
36678  #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos          (14UL)         /*!< EXPUB52 (Bit 14)                                      */
36679  #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk          (0x4000UL)     /*!< EXPUB52 (Bitfield-Mask: 0x01)                         */
36680  #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos            (0UL)          /*!< IOIRQ (Bit 0)                                         */
36681  #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk            (0x1UL)        /*!< IOIRQ (Bitfield-Mask: 0x01)                           */
36682 /* ====================================================  SDIO_INFO1_MASK  ==================================================== */
36683  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos       (15UL)         /*!< EXWTM (Bit 15)                                        */
36684  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk       (0x8000UL)     /*!< EXWTM (Bitfield-Mask: 0x01)                           */
36685  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos    (14UL)         /*!< EXPUB52M (Bit 14)                                     */
36686  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk    (0x4000UL)     /*!< EXPUB52M (Bitfield-Mask: 0x01)                        */
36687  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos      (0UL)          /*!< IOIRQM (Bit 0)                                        */
36688  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk      (0x1UL)        /*!< IOIRQM (Bitfield-Mask: 0x01)                          */
36689 /* =======================================================  SD_DMAEN  ======================================================== */
36690  #define R_SDHI0_SD_DMAEN_DMAEN_Pos              (1UL)          /*!< DMAEN (Bit 1)                                         */
36691  #define R_SDHI0_SD_DMAEN_DMAEN_Msk              (0x2UL)        /*!< DMAEN (Bitfield-Mask: 0x01)                           */
36692 /* =======================================================  SOFT_RST  ======================================================== */
36693  #define R_SDHI0_SOFT_RST_SDRST_Pos              (0UL)          /*!< SDRST (Bit 0)                                         */
36694  #define R_SDHI0_SOFT_RST_SDRST_Msk              (0x1UL)        /*!< SDRST (Bitfield-Mask: 0x01)                           */
36695 /* =======================================================  SDIF_MODE  ======================================================= */
36696  #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos           (8UL)          /*!< NOCHKCR (Bit 8)                                       */
36697  #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk           (0x100UL)      /*!< NOCHKCR (Bitfield-Mask: 0x01)                         */
36698 /* =======================================================  EXT_SWAP  ======================================================== */
36699  #define R_SDHI0_EXT_SWAP_BRSWP_Pos              (7UL)          /*!< BRSWP (Bit 7)                                         */
36700  #define R_SDHI0_EXT_SWAP_BRSWP_Msk              (0x80UL)       /*!< BRSWP (Bitfield-Mask: 0x01)                           */
36701  #define R_SDHI0_EXT_SWAP_BWSWP_Pos              (6UL)          /*!< BWSWP (Bit 6)                                         */
36702  #define R_SDHI0_EXT_SWAP_BWSWP_Msk              (0x40UL)       /*!< BWSWP (Bitfield-Mask: 0x01)                           */
36703 
36704 /* =========================================================================================================================== */
36705 /* ================                                          R_SPI0                                           ================ */
36706 /* =========================================================================================================================== */
36707 
36708 /* =========================================================  SPCR  ========================================================== */
36709  #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
36710  #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
36711  #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
36712  #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
36713  #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
36714  #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
36715  #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
36716  #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
36717  #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
36718  #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
36719  #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
36720  #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
36721  #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
36722  #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
36723  #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
36724  #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
36725 /* =========================================================  SSLP  ========================================================== */
36726  #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
36727  #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
36728  #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
36729  #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
36730  #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
36731  #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
36732  #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
36733  #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
36734  #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
36735  #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
36736  #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
36737  #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
36738  #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
36739  #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
36740  #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
36741  #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
36742 /* =========================================================  SPPCR  ========================================================= */
36743  #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
36744  #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
36745  #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
36746  #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
36747  #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
36748  #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
36749  #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
36750  #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
36751 /* =========================================================  SPSR  ========================================================== */
36752  #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
36753  #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
36754  #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
36755  #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
36756  #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
36757  #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
36758  #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
36759  #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
36760  #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
36761  #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
36762  #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
36763  #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
36764  #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
36765  #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
36766  #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
36767  #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
36768 /* =========================================================  SPDR  ========================================================== */
36769 /* ========================================================  SPDR_HA  ======================================================== */
36770 /* ========================================================  SPDR_BY  ======================================================== */
36771 /* =========================================================  SPSCR  ========================================================= */
36772  #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
36773  #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
36774 /* =========================================================  SPBR  ========================================================== */
36775  #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
36776  #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
36777 /* =========================================================  SPDCR  ========================================================= */
36778  #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
36779  #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
36780  #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
36781  #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
36782  #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
36783  #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
36784  #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
36785  #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
36786  #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
36787  #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
36788 /* =========================================================  SPCKD  ========================================================= */
36789  #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
36790  #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
36791 /* =========================================================  SSLND  ========================================================= */
36792  #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
36793  #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
36794 /* =========================================================  SPND  ========================================================== */
36795  #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
36796  #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
36797 /* =========================================================  SPCR2  ========================================================= */
36798  #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
36799  #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
36800  #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
36801  #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
36802  #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
36803  #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
36804  #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
36805  #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
36806  #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
36807  #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
36808  #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
36809  #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
36810 /* =========================================================  SPCMD  ========================================================= */
36811  #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
36812  #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
36813  #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
36814  #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
36815  #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
36816  #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
36817  #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
36818  #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
36819  #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
36820  #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
36821  #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
36822  #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
36823  #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
36824  #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
36825  #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
36826  #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
36827  #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
36828  #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
36829  #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
36830  #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
36831 /* ========================================================  SPDCR2  ========================================================= */
36832  #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
36833  #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
36834  #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
36835  #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
36836 /* =========================================================  SPSSR  ========================================================= */
36837  #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
36838  #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
36839  #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
36840  #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
36841 /* =========================================================  SPCR3  ========================================================= */
36842  #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
36843  #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
36844  #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
36845  #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
36846  #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
36847  #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
36848 /* =========================================================  SPPR  ========================================================== */
36849  #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
36850  #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
36851  #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
36852  #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
36853  #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
36854  #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
36855 
36856 /* =========================================================================================================================== */
36857 /* ================                                          R_SRAM                                           ================ */
36858 /* =========================================================================================================================== */
36859 
36860 /* =======================================================  SRAMPRCR  ======================================================== */
36861  #define R_SRAM_SRAMPRCR_PR_Pos           (0UL)       /*!< PR (Bit 0)                                            */
36862  #define R_SRAM_SRAMPRCR_PR_Msk           (0x1UL)     /*!< PR (Bitfield-Mask: 0x01)                              */
36863  #define R_SRAM_SRAMPRCR_KW_Pos           (8UL)       /*!< KW (Bit 8)                                            */
36864  #define R_SRAM_SRAMPRCR_KW_Msk           (0xff00UL)  /*!< KW (Bitfield-Mask: 0xff)                              */
36865 /* ======================================================  SRAMPRCR_NS  ====================================================== */
36866  #define R_SRAM_SRAMPRCR_NS_PR_Pos        (0UL)       /*!< PR (Bit 0)                                            */
36867  #define R_SRAM_SRAMPRCR_NS_PR_Msk        (0x1UL)     /*!< PR (Bitfield-Mask: 0x01)                              */
36868  #define R_SRAM_SRAMPRCR_NS_KW_Pos        (8UL)       /*!< KW (Bit 8)                                            */
36869  #define R_SRAM_SRAMPRCR_NS_KW_Msk        (0xff00UL)  /*!< KW (Bitfield-Mask: 0xff)                              */
36870 /* =======================================================  SRAMWTSC  ======================================================== */
36871  #define R_SRAM_SRAMWTSC_WTEN_Pos         (0UL)       /*!< WTEN (Bit 0)                                          */
36872  #define R_SRAM_SRAMWTSC_WTEN_Msk         (0x1UL)     /*!< WTEN (Bitfield-Mask: 0x01)                            */
36873 /* ========================================================  SRAMCR0  ======================================================== */
36874  #define R_SRAM_SRAMCR0_OAD_Pos           (0UL)       /*!< OAD (Bit 0)                                           */
36875  #define R_SRAM_SRAMCR0_OAD_Msk           (0x1UL)     /*!< OAD (Bitfield-Mask: 0x01)                             */
36876  #define R_SRAM_SRAMCR0_ECCMOD_Pos        (2UL)       /*!< ECCMOD (Bit 2)                                        */
36877  #define R_SRAM_SRAMCR0_ECCMOD_Msk        (0xcUL)     /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
36878  #define R_SRAM_SRAMCR0_E1STSEN_Pos       (4UL)       /*!< E1STSEN (Bit 4)                                       */
36879  #define R_SRAM_SRAMCR0_E1STSEN_Msk       (0x10UL)    /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
36880  #define R_SRAM_SRAMCR0_TSTBYP_Pos        (7UL)       /*!< TSTBYP (Bit 7)                                        */
36881  #define R_SRAM_SRAMCR0_TSTBYP_Msk        (0x80UL)    /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
36882 /* ========================================================  SRAMCR1  ======================================================== */
36883  #define R_SRAM_SRAMCR1_OAD_Pos           (0UL)       /*!< OAD (Bit 0)                                           */
36884  #define R_SRAM_SRAMCR1_OAD_Msk           (0x1UL)     /*!< OAD (Bitfield-Mask: 0x01)                             */
36885 /* ======================================================  SRAMECCRGN0  ====================================================== */
36886  #define R_SRAM_SRAMECCRGN0_ECCRGN_Pos    (0UL)       /*!< ECCRGN (Bit 0)                                        */
36887  #define R_SRAM_SRAMECCRGN0_ECCRGN_Msk    (0x3UL)     /*!< ECCRGN (Bitfield-Mask: 0x03)                          */
36888 /* ========================================================  SRAMESR  ======================================================== */
36889  #define R_SRAM_SRAMESR_ERR00_Pos         (0UL)       /*!< ERR00 (Bit 0)                                         */
36890  #define R_SRAM_SRAMESR_ERR00_Msk         (0x1UL)     /*!< ERR00 (Bitfield-Mask: 0x01)                           */
36891  #define R_SRAM_SRAMESR_ERR01_Pos         (1UL)       /*!< ERR01 (Bit 1)                                         */
36892  #define R_SRAM_SRAMESR_ERR01_Msk         (0x2UL)     /*!< ERR01 (Bitfield-Mask: 0x01)                           */
36893  #define R_SRAM_SRAMESR_ERR1_Pos          (2UL)       /*!< ERR1 (Bit 2)                                          */
36894  #define R_SRAM_SRAMESR_ERR1_Msk          (0x4UL)     /*!< ERR1 (Bitfield-Mask: 0x01)                            */
36895  #define R_SRAM_SRAMESR_ERRS_Pos          (14UL)      /*!< ERRS (Bit 14)                                         */
36896  #define R_SRAM_SRAMESR_ERRS_Msk          (0x4000UL)  /*!< ERRS (Bitfield-Mask: 0x01)                            */
36897 /* =======================================================  SRAMESCLR  ======================================================= */
36898  #define R_SRAM_SRAMESCLR_CLR00_Pos       (0UL)       /*!< CLR00 (Bit 0)                                         */
36899  #define R_SRAM_SRAMESCLR_CLR00_Msk       (0x1UL)     /*!< CLR00 (Bitfield-Mask: 0x01)                           */
36900  #define R_SRAM_SRAMESCLR_CLR01_Pos       (1UL)       /*!< CLR01 (Bit 1)                                         */
36901  #define R_SRAM_SRAMESCLR_CLR01_Msk       (0x2UL)     /*!< CLR01 (Bitfield-Mask: 0x01)                           */
36902  #define R_SRAM_SRAMESCLR_CLR1_Pos        (2UL)       /*!< CLR1 (Bit 2)                                          */
36903  #define R_SRAM_SRAMESCLR_CLR1_Msk        (0x4UL)     /*!< CLR1 (Bitfield-Mask: 0x01)                            */
36904  #define R_SRAM_SRAMESCLR_CLRS_Pos        (14UL)      /*!< CLRS (Bit 14)                                         */
36905  #define R_SRAM_SRAMESCLR_CLRS_Msk        (0x4000UL)  /*!< CLRS (Bitfield-Mask: 0x01)                            */
36906 /* =======================================================  SRAMEAR0  ======================================================== */
36907  #define R_SRAM_SRAMEAR0_EA_Pos           (3UL)       /*!< EA (Bit 3)                                            */
36908  #define R_SRAM_SRAMEAR0_EA_Msk           (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff)                           */
36909 /* =======================================================  SRAMEAR1  ======================================================== */
36910  #define R_SRAM_SRAMEAR1_EA_Pos           (3UL)       /*!< EA (Bit 3)                                            */
36911  #define R_SRAM_SRAMEAR1_EA_Msk           (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff)                           */
36912 /* =======================================================  SRAMEAR2  ======================================================== */
36913  #define R_SRAM_SRAMEAR2_EA_Pos           (3UL)       /*!< EA (Bit 3)                                            */
36914  #define R_SRAM_SRAMEAR2_EA_Msk           (0xffff8UL) /*!< EA (Bitfield-Mask: 0x1ffff)                           */
36915 /* =======================================================  STBRAMCR  ======================================================== */
36916  #define R_SRAM_STBRAMCR_OAD_Pos          (0UL)       /*!< OAD (Bit 0)                                           */
36917  #define R_SRAM_STBRAMCR_OAD_Msk          (0x1UL)     /*!< OAD (Bitfield-Mask: 0x01)                             */
36918 /* =======================================================  STBRAMEAR  ======================================================= */
36919  #define R_SRAM_STBRAMEAR_EA_Pos          (2UL)       /*!< EA (Bit 2)                                            */
36920  #define R_SRAM_STBRAMEAR_EA_Msk          (0x3fcUL)   /*!< EA (Bitfield-Mask: 0xff)                              */
36921 
36922 /* =========================================================================================================================== */
36923 /* ================                                          R_SSI0                                           ================ */
36924 /* =========================================================================================================================== */
36925 
36926 /* =========================================================  SSICR  ========================================================= */
36927  #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
36928  #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
36929  #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
36930  #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
36931  #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
36932  #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
36933  #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
36934  #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
36935  #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
36936  #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
36937  #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
36938  #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
36939  #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
36940  #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
36941  #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
36942  #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
36943  #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
36944  #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
36945  #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
36946  #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
36947  #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
36948  #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
36949  #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
36950  #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
36951  #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
36952  #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
36953  #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
36954  #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
36955  #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
36956  #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
36957  #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
36958  #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
36959  #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
36960  #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
36961  #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
36962  #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
36963  #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
36964  #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
36965  #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
36966  #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
36967 /* =========================================================  SSISR  ========================================================= */
36968  #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
36969  #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
36970  #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
36971  #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
36972  #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
36973  #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
36974  #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
36975  #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
36976  #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
36977  #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
36978  #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
36979  #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
36980  #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
36981  #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
36982  #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
36983  #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
36984  #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
36985  #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
36986  #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
36987  #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
36988 /* ========================================================  SSIFCR  ========================================================= */
36989  #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
36990  #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
36991  #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
36992  #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
36993  #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
36994  #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
36995  #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
36996  #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
36997  #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
36998  #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
36999  #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
37000  #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
37001  #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
37002  #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
37003  #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
37004  #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
37005  #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
37006  #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
37007 /* ========================================================  SSIFSR  ========================================================= */
37008  #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
37009  #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
37010  #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
37011  #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
37012  #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
37013  #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
37014  #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
37015  #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
37016 /* ========================================================  SSIFTDR  ======================================================== */
37017  #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
37018  #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
37019 /* =======================================================  SSIFTDR16  ======================================================= */
37020 /* =======================================================  SSIFTDR8  ======================================================== */
37021 /* ========================================================  SSIFRDR  ======================================================== */
37022  #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
37023  #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
37024 /* =======================================================  SSIFRDR16  ======================================================= */
37025 /* =======================================================  SSIFRDR8  ======================================================== */
37026 /* ========================================================  SSIOFR  ========================================================= */
37027  #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
37028  #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
37029  #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
37030  #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
37031  #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
37032  #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
37033 /* ========================================================  SSISCR  ========================================================= */
37034  #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
37035  #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
37036  #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
37037  #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
37038 
37039 /* =========================================================================================================================== */
37040 /* ================                                         R_SYSTEM                                          ================ */
37041 /* =========================================================================================================================== */
37042 
37043 /* =========================================================  SBYCR  ========================================================= */
37044  #define R_SYSTEM_SBYCR_OPE_Pos                  (6UL)          /*!< OPE (Bit 6)                                           */
37045  #define R_SYSTEM_SBYCR_OPE_Msk                  (0x40UL)       /*!< OPE (Bitfield-Mask: 0x01)                             */
37046 /* =========================================================  SSCR2  ========================================================= */
37047  #define R_SYSTEM_SSCR2_SS1RSF_Pos               (0UL)          /*!< SS1RSF (Bit 0)                                        */
37048  #define R_SYSTEM_SSCR2_SS1RSF_Msk               (0x1UL)        /*!< SS1RSF (Bitfield-Mask: 0x01)                          */
37049 /* =========================================================  FLSCR  ========================================================= */
37050  #define R_SYSTEM_FLSCR_FLSWCF_Pos               (0UL)          /*!< FLSWCF (Bit 0)                                        */
37051  #define R_SYSTEM_FLSCR_FLSWCF_Msk               (0x1UL)        /*!< FLSWCF (Bitfield-Mask: 0x01)                          */
37052 /* ========================================================  MSTPCRA  ======================================================== */
37053  #define R_SYSTEM_MSTPCRA_MSTPA_Pos              (0UL)          /*!< MSTPA (Bit 0)                                         */
37054  #define R_SYSTEM_MSTPCRA_MSTPA_Msk              (0x1UL)        /*!< MSTPA (Bitfield-Mask: 0x01)                           */
37055 /* =======================================================  SCKDIVCR  ======================================================== */
37056  #define R_SYSTEM_SCKDIVCR_FCK_Pos               (28UL)         /*!< FCK (Bit 28)                                          */
37057  #define R_SYSTEM_SCKDIVCR_FCK_Msk               (0xf0000000UL) /*!< FCK (Bitfield-Mask: 0x0f)                             */
37058  #define R_SYSTEM_SCKDIVCR_ICK_Pos               (24UL)         /*!< ICK (Bit 24)                                          */
37059  #define R_SYSTEM_SCKDIVCR_ICK_Msk               (0xf000000UL)  /*!< ICK (Bitfield-Mask: 0x0f)                             */
37060  #define R_SYSTEM_SCKDIVCR_PCKE_Pos              (20UL)         /*!< PCKE (Bit 20)                                         */
37061  #define R_SYSTEM_SCKDIVCR_PCKE_Msk              (0xf00000UL)   /*!< PCKE (Bitfield-Mask: 0x0f)                            */
37062  #define R_SYSTEM_SCKDIVCR_BCK_Pos               (16UL)         /*!< BCK (Bit 16)                                          */
37063  #define R_SYSTEM_SCKDIVCR_BCK_Msk               (0xf0000UL)    /*!< BCK (Bitfield-Mask: 0x0f)                             */
37064  #define R_SYSTEM_SCKDIVCR_PCKA_Pos              (12UL)         /*!< PCKA (Bit 12)                                         */
37065  #define R_SYSTEM_SCKDIVCR_PCKA_Msk              (0xf000UL)     /*!< PCKA (Bitfield-Mask: 0x0f)                            */
37066  #define R_SYSTEM_SCKDIVCR_PCKB_Pos              (8UL)          /*!< PCKB (Bit 8)                                          */
37067  #define R_SYSTEM_SCKDIVCR_PCKB_Msk              (0xf00UL)      /*!< PCKB (Bitfield-Mask: 0x0f)                            */
37068  #define R_SYSTEM_SCKDIVCR_PCKC_Pos              (4UL)          /*!< PCKC (Bit 4)                                          */
37069  #define R_SYSTEM_SCKDIVCR_PCKC_Msk              (0xf0UL)       /*!< PCKC (Bitfield-Mask: 0x0f)                            */
37070  #define R_SYSTEM_SCKDIVCR_PCKD_Pos              (0UL)          /*!< PCKD (Bit 0)                                          */
37071  #define R_SYSTEM_SCKDIVCR_PCKD_Msk              (0xfUL)        /*!< PCKD (Bitfield-Mask: 0x0f)                            */
37072 /* =======================================================  SCKDIVCR2  ======================================================= */
37073  #define R_SYSTEM_SCKDIVCR2_CPUCK_Pos            (0UL)          /*!< CPUCK (Bit 0)                                         */
37074  #define R_SYSTEM_SCKDIVCR2_CPUCK_Msk            (0xfUL)        /*!< CPUCK (Bitfield-Mask: 0x0f)                           */
37075 /* ========================================================  SCKSCR  ========================================================= */
37076  #define R_SYSTEM_SCKSCR_CKSEL_Pos               (0UL)          /*!< CKSEL (Bit 0)                                         */
37077  #define R_SYSTEM_SCKSCR_CKSEL_Msk               (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
37078 /* ========================================================  PLLCCR  ========================================================= */
37079  #define R_SYSTEM_PLLCCR_PLIDIV_Pos              (0UL)          /*!< PLIDIV (Bit 0)                                        */
37080  #define R_SYSTEM_PLLCCR_PLIDIV_Msk              (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
37081  #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos            (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
37082  #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk            (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
37083  #define R_SYSTEM_PLLCCR_PLLMULNF_Pos            (6UL)          /*!< PLLMULNF (Bit 6)                                      */
37084  #define R_SYSTEM_PLLCCR_PLLMULNF_Msk            (0xc0UL)       /*!< PLLMULNF (Bitfield-Mask: 0x03)                        */
37085  #define R_SYSTEM_PLLCCR_PLLMUL_Pos              (8UL)          /*!< PLLMUL (Bit 8)                                        */
37086  #define R_SYSTEM_PLLCCR_PLLMUL_Msk              (0xff00UL)     /*!< PLLMUL (Bitfield-Mask: 0xff)                          */
37087 /* =========================================================  PLLCR  ========================================================= */
37088  #define R_SYSTEM_PLLCR_PLLSTP_Pos               (0UL)          /*!< PLLSTP (Bit 0)                                        */
37089  #define R_SYSTEM_PLLCR_PLLSTP_Msk               (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
37090 /* =========================================================  BCKCR  ========================================================= */
37091  #define R_SYSTEM_BCKCR_BCLKDIV_Pos              (0UL)          /*!< BCLKDIV (Bit 0)                                       */
37092  #define R_SYSTEM_BCKCR_BCLKDIV_Msk              (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
37093 /* ========================================================  MOSCCR  ========================================================= */
37094  #define R_SYSTEM_MOSCCR_MOSTP_Pos               (0UL)          /*!< MOSTP (Bit 0)                                         */
37095  #define R_SYSTEM_MOSCCR_MOSTP_Msk               (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
37096 /* ========================================================  HOCOCR  ========================================================= */
37097  #define R_SYSTEM_HOCOCR_HCSTP_Pos               (0UL)          /*!< HCSTP (Bit 0)                                         */
37098  #define R_SYSTEM_HOCOCR_HCSTP_Msk               (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
37099 /* ========================================================  MOCOCR  ========================================================= */
37100  #define R_SYSTEM_MOCOCR_MCSTP_Pos               (0UL)          /*!< MCSTP (Bit 0)                                         */
37101  #define R_SYSTEM_MOCOCR_MCSTP_Msk               (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
37102 /* ========================================================  FLLCR1  ========================================================= */
37103  #define R_SYSTEM_FLLCR1_FLLEN_Pos               (0UL)          /*!< FLLEN (Bit 0)                                         */
37104  #define R_SYSTEM_FLLCR1_FLLEN_Msk               (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
37105 /* ========================================================  FLLCR2  ========================================================= */
37106  #define R_SYSTEM_FLLCR2_FLLCNTL_Pos             (0UL)          /*!< FLLCNTL (Bit 0)                                       */
37107  #define R_SYSTEM_FLLCR2_FLLCNTL_Msk             (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
37108 /* =========================================================  OSCSF  ========================================================= */
37109  #define R_SYSTEM_OSCSF_HOCOSF_Pos               (0UL)          /*!< HOCOSF (Bit 0)                                        */
37110  #define R_SYSTEM_OSCSF_HOCOSF_Msk               (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
37111  #define R_SYSTEM_OSCSF_MOSCSF_Pos               (3UL)          /*!< MOSCSF (Bit 3)                                        */
37112  #define R_SYSTEM_OSCSF_MOSCSF_Msk               (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
37113  #define R_SYSTEM_OSCSF_PLLSF_Pos                (5UL)          /*!< PLLSF (Bit 5)                                         */
37114  #define R_SYSTEM_OSCSF_PLLSF_Msk                (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
37115  #define R_SYSTEM_OSCSF_PLL2SF_Pos               (6UL)          /*!< PLL2SF (Bit 6)                                        */
37116  #define R_SYSTEM_OSCSF_PLL2SF_Msk               (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
37117 /* =========================================================  CKOCR  ========================================================= */
37118  #define R_SYSTEM_CKOCR_CKODIV_Pos               (4UL)          /*!< CKODIV (Bit 4)                                        */
37119  #define R_SYSTEM_CKOCR_CKODIV_Msk               (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
37120  #define R_SYSTEM_CKOCR_CKOEN_Pos                (7UL)          /*!< CKOEN (Bit 7)                                         */
37121  #define R_SYSTEM_CKOCR_CKOEN_Msk                (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
37122 /* ========================================================  TRCKCR  ========================================================= */
37123  #define R_SYSTEM_TRCKCR_TRCK_Pos                (0UL)          /*!< TRCK (Bit 0)                                          */
37124  #define R_SYSTEM_TRCKCR_TRCK_Msk                (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
37125  #define R_SYSTEM_TRCKCR_TRCKSEL_Pos             (4UL)          /*!< TRCKSEL (Bit 4)                                       */
37126  #define R_SYSTEM_TRCKCR_TRCKSEL_Msk             (0x10UL)       /*!< TRCKSEL (Bitfield-Mask: 0x01)                         */
37127  #define R_SYSTEM_TRCKCR_TRCKEN_Pos              (7UL)          /*!< TRCKEN (Bit 7)                                        */
37128  #define R_SYSTEM_TRCKCR_TRCKEN_Msk              (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
37129 /* ========================================================  OSTDCR  ========================================================= */
37130  #define R_SYSTEM_OSTDCR_OSTDIE_Pos              (0UL)          /*!< OSTDIE (Bit 0)                                        */
37131  #define R_SYSTEM_OSTDCR_OSTDIE_Msk              (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
37132  #define R_SYSTEM_OSTDCR_OSTDE_Pos               (7UL)          /*!< OSTDE (Bit 7)                                         */
37133  #define R_SYSTEM_OSTDCR_OSTDE_Msk               (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
37134 /* ========================================================  OSTDSR  ========================================================= */
37135  #define R_SYSTEM_OSTDSR_OSTDF_Pos               (0UL)          /*!< OSTDF (Bit 0)                                         */
37136  #define R_SYSTEM_OSTDSR_OSTDF_Msk               (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
37137 /* ========================================================  OSCMONR  ======================================================== */
37138  #define R_SYSTEM_OSCMONR_MOCOMON_Pos            (1UL)          /*!< MOCOMON (Bit 1)                                       */
37139  #define R_SYSTEM_OSCMONR_MOCOMON_Msk            (0x2UL)        /*!< MOCOMON (Bitfield-Mask: 0x01)                         */
37140  #define R_SYSTEM_OSCMONR_LOCOMON_Pos            (2UL)          /*!< LOCOMON (Bit 2)                                       */
37141  #define R_SYSTEM_OSCMONR_LOCOMON_Msk            (0x4UL)        /*!< LOCOMON (Bitfield-Mask: 0x01)                         */
37142 /* ========================================================  PLL2CCR  ======================================================== */
37143  #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos            (0UL)          /*!< PL2IDIV (Bit 0)                                       */
37144  #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk            (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
37145  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos          (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
37146  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk          (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
37147  #define R_SYSTEM_PLL2CCR_PLL2MULNF_Pos          (6UL)          /*!< PLL2MULNF (Bit 6)                                     */
37148  #define R_SYSTEM_PLL2CCR_PLL2MULNF_Msk          (0xc0UL)       /*!< PLL2MULNF (Bitfield-Mask: 0x03)                       */
37149  #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos            (8UL)          /*!< PLL2MUL (Bit 8)                                       */
37150  #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk            (0xff00UL)     /*!< PLL2MUL (Bitfield-Mask: 0xff)                         */
37151 /* ========================================================  PLL2CR  ========================================================= */
37152  #define R_SYSTEM_PLL2CR_PLL2STP_Pos             (0UL)          /*!< PLL2STP (Bit 0)                                       */
37153  #define R_SYSTEM_PLL2CR_PLL2STP_Msk             (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
37154 /* ========================================================  PLLCCR2  ======================================================== */
37155  #define R_SYSTEM_PLLCCR2_PLODIVP_Pos            (0UL)          /*!< PLODIVP (Bit 0)                                       */
37156  #define R_SYSTEM_PLLCCR2_PLODIVP_Msk            (0xfUL)        /*!< PLODIVP (Bitfield-Mask: 0x0f)                         */
37157  #define R_SYSTEM_PLLCCR2_PLODIVQ_Pos            (4UL)          /*!< PLODIVQ (Bit 4)                                       */
37158  #define R_SYSTEM_PLLCCR2_PLODIVQ_Msk            (0xf0UL)       /*!< PLODIVQ (Bitfield-Mask: 0x0f)                         */
37159  #define R_SYSTEM_PLLCCR2_PLODIVR_Pos            (8UL)          /*!< PLODIVR (Bit 8)                                       */
37160  #define R_SYSTEM_PLLCCR2_PLODIVR_Msk            (0xf00UL)      /*!< PLODIVR (Bitfield-Mask: 0x0f)                         */
37161 /* =======================================================  PLL2CCR2  ======================================================== */
37162  #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Pos          (0UL)          /*!< PL2ODIVP (Bit 0)                                      */
37163  #define R_SYSTEM_PLL2CCR2_PL2ODIVP_Msk          (0xfUL)        /*!< PL2ODIVP (Bitfield-Mask: 0x0f)                        */
37164  #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Pos          (4UL)          /*!< PL2ODIVQ (Bit 4)                                      */
37165  #define R_SYSTEM_PLL2CCR2_PL2ODIVQ_Msk          (0xf0UL)       /*!< PL2ODIVQ (Bitfield-Mask: 0x0f)                        */
37166  #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Pos          (8UL)          /*!< PL2ODIVR (Bit 8)                                      */
37167  #define R_SYSTEM_PLL2CCR2_PL2ODIVR_Msk          (0xf00UL)      /*!< PL2ODIVR (Bitfield-Mask: 0x0f)                        */
37168 /* ========================================================  EBCKOCR  ======================================================== */
37169  #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos            (0UL)          /*!< EBCKOEN (Bit 0)                                       */
37170  #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk            (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
37171 /* ========================================================  SDCKOCR  ======================================================== */
37172  #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos            (0UL)          /*!< SDCKOEN (Bit 0)                                       */
37173  #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk            (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
37174 /* ======================================================  SCICKDIVCR  ======================================================= */
37175  #define R_SYSTEM_SCICKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
37176  #define R_SYSTEM_SCICKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
37177 /* ========================================================  SCICKCR  ======================================================== */
37178  #define R_SYSTEM_SCICKCR_SCICKSEL_Pos           (0UL)          /*!< SCICKSEL (Bit 0)                                      */
37179  #define R_SYSTEM_SCICKCR_SCICKSEL_Msk           (0xfUL)        /*!< SCICKSEL (Bitfield-Mask: 0x0f)                        */
37180  #define R_SYSTEM_SCICKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
37181  #define R_SYSTEM_SCICKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
37182  #define R_SYSTEM_SCICKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
37183  #define R_SYSTEM_SCICKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
37184 /* ======================================================  SPICKDIVCR  ======================================================= */
37185  #define R_SYSTEM_SPICKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
37186  #define R_SYSTEM_SPICKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
37187 /* ========================================================  SPICKCR  ======================================================== */
37188  #define R_SYSTEM_SPICKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
37189  #define R_SYSTEM_SPICKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */
37190  #define R_SYSTEM_SPICKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
37191  #define R_SYSTEM_SPICKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
37192  #define R_SYSTEM_SPICKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
37193  #define R_SYSTEM_SPICKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
37194 /* ======================================================  ADCCKDIVCR  ======================================================= */
37195  #define R_SYSTEM_ADCCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
37196  #define R_SYSTEM_ADCCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
37197 /* ========================================================  ADCCKCR  ======================================================== */
37198  #define R_SYSTEM_ADCCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
37199  #define R_SYSTEM_ADCCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */
37200  #define R_SYSTEM_ADCCKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
37201  #define R_SYSTEM_ADCCKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
37202  #define R_SYSTEM_ADCCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
37203  #define R_SYSTEM_ADCCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
37204 /* ======================================================  GPTCKDIVCR  ======================================================= */
37205  #define R_SYSTEM_GPTCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
37206  #define R_SYSTEM_GPTCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
37207 /* ========================================================  GPTCKCR  ======================================================== */
37208  #define R_SYSTEM_GPTCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
37209  #define R_SYSTEM_GPTCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */
37210  #define R_SYSTEM_GPTCKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
37211  #define R_SYSTEM_GPTCKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
37212  #define R_SYSTEM_GPTCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
37213  #define R_SYSTEM_GPTCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
37214 /* ======================================================  LCDCKDIVCR  ======================================================= */
37215  #define R_SYSTEM_LCDCKDIVCR_CKDIV_Pos           (0UL)          /*!< CKDIV (Bit 0)                                         */
37216  #define R_SYSTEM_LCDCKDIVCR_CKDIV_Msk           (0x7UL)        /*!< CKDIV (Bitfield-Mask: 0x07)                           */
37217 /* ========================================================  LCDCKCR  ======================================================== */
37218  #define R_SYSTEM_LCDCKCR_CKSEL_Pos              (0UL)          /*!< CKSEL (Bit 0)                                         */
37219  #define R_SYSTEM_LCDCKCR_CKSEL_Msk              (0xfUL)        /*!< CKSEL (Bitfield-Mask: 0x0f)                           */
37220  #define R_SYSTEM_LCDCKCR_CKSREQ_Pos             (6UL)          /*!< CKSREQ (Bit 6)                                        */
37221  #define R_SYSTEM_LCDCKCR_CKSREQ_Msk             (0x40UL)       /*!< CKSREQ (Bitfield-Mask: 0x01)                          */
37222  #define R_SYSTEM_LCDCKCR_CKSRDY_Pos             (7UL)          /*!< CKSRDY (Bit 7)                                        */
37223  #define R_SYSTEM_LCDCKCR_CKSRDY_Msk             (0x80UL)       /*!< CKSRDY (Bitfield-Mask: 0x01)                          */
37224 /* =======================================================  MOCOUTCR  ======================================================== */
37225  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos          (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
37226  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk          (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
37227 /* =======================================================  HOCOUTCR  ======================================================== */
37228  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos          (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
37229  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk          (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
37230 /* ======================================================  USBCKDIVCR  ======================================================= */
37231  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos        (0UL)          /*!< USBCKDIV (Bit 0)                                      */
37232  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk        (0x7UL)        /*!< USBCKDIV (Bitfield-Mask: 0x07)                        */
37233 /* ======================================================  OCTACKDIVCR  ====================================================== */
37234  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos      (0UL)          /*!< OCTACKDIV (Bit 0)                                     */
37235  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk      (0x7UL)        /*!< OCTACKDIV (Bitfield-Mask: 0x07)                       */
37236 /* =====================================================  CANFDCKDIVCR  ====================================================== */
37237  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos    (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
37238  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk    (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
37239 /* =====================================================  USB60CKDIVCR  ====================================================== */
37240  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos    (0UL)          /*!< USB60CKDIV (Bit 0)                                    */
37241  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk    (0x7UL)        /*!< USB60CKDIV (Bitfield-Mask: 0x07)                      */
37242 /* ======================================================  I3CCKDIVCR  ======================================================= */
37243  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos        (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
37244  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk        (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
37245 /* ========================================================  USBCKCR  ======================================================== */
37246  #define R_SYSTEM_USBCKCR_USBCKSEL_Pos           (0UL)          /*!< USBCKSEL (Bit 0)                                      */
37247  #define R_SYSTEM_USBCKCR_USBCKSEL_Msk           (0xfUL)        /*!< USBCKSEL (Bitfield-Mask: 0x0f)                        */
37248  #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos          (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
37249  #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk          (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
37250  #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos          (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
37251  #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk          (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
37252 /* =======================================================  OCTACKCR  ======================================================== */
37253  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos         (0UL)          /*!< OCTACKSEL (Bit 0)                                     */
37254  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk         (0xfUL)        /*!< OCTACKSEL (Bitfield-Mask: 0x0f)                       */
37255  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos        (6UL)          /*!< OCTACKSREQ (Bit 6)                                    */
37256  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk        (0x40UL)       /*!< OCTACKSREQ (Bitfield-Mask: 0x01)                      */
37257  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos        (7UL)          /*!< OCTACKSRDY (Bit 7)                                    */
37258  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk        (0x80UL)       /*!< OCTACKSRDY (Bitfield-Mask: 0x01)                      */
37259 /* =======================================================  CANFDCKCR  ======================================================= */
37260  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos       (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
37261  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk       (0xfUL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x0f)                      */
37262  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos      (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
37263  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk      (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
37264  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos      (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
37265  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk      (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
37266 /* =======================================================  USB60CKCR  ======================================================= */
37267  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos       (0UL)          /*!< USB60CKSEL (Bit 0)                                    */
37268  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk       (0xfUL)        /*!< USB60CKSEL (Bitfield-Mask: 0x0f)                      */
37269  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos      (6UL)          /*!< USB60CKSREQ (Bit 6)                                   */
37270  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk      (0x40UL)       /*!< USB60CKSREQ (Bitfield-Mask: 0x01)                     */
37271  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos      (7UL)          /*!< USB60CKSRDY (Bit 7)                                   */
37272  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk      (0x80UL)       /*!< USB60CKSRDY (Bitfield-Mask: 0x01)                     */
37273 /* ========================================================  I3CCKCR  ======================================================== */
37274  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos           (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
37275  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk           (0xfUL)        /*!< I3CCKSEL (Bitfield-Mask: 0x0f)                        */
37276  #define R_SYSTEM_I3CCKCR_I3CCKREQ_Pos           (6UL)          /*!< I3CCKREQ (Bit 6)                                      */
37277  #define R_SYSTEM_I3CCKCR_I3CCKREQ_Msk           (0x40UL)       /*!< I3CCKREQ (Bitfield-Mask: 0x01)                        */
37278  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos          (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
37279  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk          (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
37280 /* ========================================================  MOSCSCR  ======================================================== */
37281  #define R_SYSTEM_MOSCSCR_MOSCSOKP_Pos           (0UL)          /*!< MOSCSOKP (Bit 0)                                      */
37282  #define R_SYSTEM_MOSCSCR_MOSCSOKP_Msk           (0x1UL)        /*!< MOSCSOKP (Bitfield-Mask: 0x01)                        */
37283 /* ========================================================  HOCOSCR  ======================================================== */
37284  #define R_SYSTEM_HOCOSCR_HOCOSOKP_Pos           (0UL)          /*!< HOCOSOKP (Bit 0)                                      */
37285  #define R_SYSTEM_HOCOSCR_HOCOSOKP_Msk           (0x1UL)        /*!< HOCOSOKP (Bitfield-Mask: 0x01)                        */
37286 /* =========================================================  OPCCR  ========================================================= */
37287  #define R_SYSTEM_OPCCR_OPCMTSF_Pos              (4UL)          /*!< OPCMTSF (Bit 4)                                       */
37288  #define R_SYSTEM_OPCCR_OPCMTSF_Msk              (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
37289  #define R_SYSTEM_OPCCR_OPCM_Pos                 (0UL)          /*!< OPCM (Bit 0)                                          */
37290  #define R_SYSTEM_OPCCR_OPCM_Msk                 (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
37291 /* =======================================================  MOSCWTCR  ======================================================== */
37292  #define R_SYSTEM_MOSCWTCR_MSTS_Pos              (0UL)          /*!< MSTS (Bit 0)                                          */
37293  #define R_SYSTEM_MOSCWTCR_MSTS_Msk              (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
37294 /* =======================================================  HOCOWTCR  ======================================================== */
37295  #define R_SYSTEM_HOCOWTCR_HSTS_Pos              (0UL)          /*!< HSTS (Bit 0)                                          */
37296  #define R_SYSTEM_HOCOWTCR_HSTS_Msk              (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
37297 /* ========================================================  SOPCCR  ========================================================= */
37298  #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos            (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
37299  #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk            (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
37300  #define R_SYSTEM_SOPCCR_SOPCM_Pos               (0UL)          /*!< SOPCM (Bit 0)                                         */
37301  #define R_SYSTEM_SOPCCR_SOPCM_Msk               (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
37302 /* ========================================================  RSTSR1  ========================================================= */
37303  #define R_SYSTEM_RSTSR1_IWDTRF_Pos              (0UL)          /*!< IWDTRF (Bit 0)                                        */
37304  #define R_SYSTEM_RSTSR1_IWDTRF_Msk              (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
37305  #define R_SYSTEM_RSTSR1_WDTRF_Pos               (1UL)          /*!< WDTRF (Bit 1)                                         */
37306  #define R_SYSTEM_RSTSR1_WDTRF_Msk               (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
37307  #define R_SYSTEM_RSTSR1_SWRF_Pos                (2UL)          /*!< SWRF (Bit 2)                                          */
37308  #define R_SYSTEM_RSTSR1_SWRF_Msk                (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
37309  #define R_SYSTEM_RSTSR1_CLU0RF_Pos              (4UL)          /*!< CLU0RF (Bit 4)                                        */
37310  #define R_SYSTEM_RSTSR1_CLU0RF_Msk              (0x10UL)       /*!< CLU0RF (Bitfield-Mask: 0x01)                          */
37311  #define R_SYSTEM_RSTSR1_LM0RF_Pos               (5UL)          /*!< LM0RF (Bit 5)                                         */
37312  #define R_SYSTEM_RSTSR1_LM0RF_Msk               (0x20UL)       /*!< LM0RF (Bitfield-Mask: 0x01)                           */
37313  #define R_SYSTEM_RSTSR1_BUSRF_Pos               (10UL)         /*!< BUSRF (Bit 10)                                        */
37314  #define R_SYSTEM_RSTSR1_BUSRF_Msk               (0x400UL)      /*!< BUSRF (Bitfield-Mask: 0x01)                           */
37315  #define R_SYSTEM_RSTSR1_CMRF_Pos                (14UL)         /*!< CMRF (Bit 14)                                         */
37316  #define R_SYSTEM_RSTSR1_CMRF_Msk                (0x4000UL)     /*!< CMRF (Bitfield-Mask: 0x01)                            */
37317  #define R_SYSTEM_RSTSR1_WDT1RF_Pos              (17UL)         /*!< WDT1RF (Bit 17)                                       */
37318  #define R_SYSTEM_RSTSR1_WDT1RF_Msk              (0x20000UL)    /*!< WDT1RF (Bitfield-Mask: 0x01)                          */
37319  #define R_SYSTEM_RSTSR1_CLU1RF_Pos              (20UL)         /*!< CLU1RF (Bit 20)                                       */
37320  #define R_SYSTEM_RSTSR1_CLU1RF_Msk              (0x100000UL)   /*!< CLU1RF (Bitfield-Mask: 0x01)                          */
37321  #define R_SYSTEM_RSTSR1_LM1RF_Pos               (21UL)         /*!< LM1RF (Bit 21)                                        */
37322  #define R_SYSTEM_RSTSR1_LM1RF_Msk               (0x200000UL)   /*!< LM1RF (Bitfield-Mask: 0x01)                           */
37323  #define R_SYSTEM_RSTSR1_NWRF_Pos                (22UL)         /*!< NWRF (Bit 22)                                         */
37324  #define R_SYSTEM_RSTSR1_NWRF_Msk                (0x400000UL)   /*!< NWRF (Bitfield-Mask: 0x01)                            */
37325 /* ========================================================  SYRACCR  ======================================================== */
37326  #define R_SYSTEM_SYRACCR_BUSY_Pos               (0UL)          /*!< BUSY (Bit 0)                                          */
37327  #define R_SYSTEM_SYRACCR_BUSY_Msk               (0x1UL)        /*!< BUSY (Bitfield-Mask: 0x01)                            */
37328 /* ========================================================  LVD1CR1  ======================================================== */
37329  #define R_SYSTEM_LVD1CR1_IDTSEL_Pos             (0UL)          /*!< IDTSEL (Bit 0)                                        */
37330  #define R_SYSTEM_LVD1CR1_IDTSEL_Msk             (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
37331  #define R_SYSTEM_LVD1CR1_IRQSEL_Pos             (2UL)          /*!< IRQSEL (Bit 2)                                        */
37332  #define R_SYSTEM_LVD1CR1_IRQSEL_Msk             (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
37333 /* ========================================================  LVD2CR1  ======================================================== */
37334  #define R_SYSTEM_LVD2CR1_IDTSEL_Pos             (0UL)          /*!< IDTSEL (Bit 0)                                        */
37335  #define R_SYSTEM_LVD2CR1_IDTSEL_Msk             (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
37336  #define R_SYSTEM_LVD2CR1_IRQSEL_Pos             (2UL)          /*!< IRQSEL (Bit 2)                                        */
37337  #define R_SYSTEM_LVD2CR1_IRQSEL_Msk             (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
37338 /* ========================================================  LVD1SR  ========================================================= */
37339  #define R_SYSTEM_LVD1SR_DET_Pos                 (0UL)          /*!< DET (Bit 0)                                           */
37340  #define R_SYSTEM_LVD1SR_DET_Msk                 (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
37341  #define R_SYSTEM_LVD1SR_MON_Pos                 (1UL)          /*!< MON (Bit 1)                                           */
37342  #define R_SYSTEM_LVD1SR_MON_Msk                 (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
37343 /* ========================================================  LVD2SR  ========================================================= */
37344  #define R_SYSTEM_LVD2SR_DET_Pos                 (0UL)          /*!< DET (Bit 0)                                           */
37345  #define R_SYSTEM_LVD2SR_DET_Msk                 (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
37346  #define R_SYSTEM_LVD2SR_MON_Pos                 (1UL)          /*!< MON (Bit 1)                                           */
37347  #define R_SYSTEM_LVD2SR_MON_Msk                 (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
37348 /* =======================================================  CRVSYSCR  ======================================================== */
37349  #define R_SYSTEM_CRVSYSCR_CRVEN_Pos             (0UL)          /*!< CRVEN (Bit 0)                                         */
37350  #define R_SYSTEM_CRVSYSCR_CRVEN_Msk             (0x1UL)        /*!< CRVEN (Bitfield-Mask: 0x01)                           */
37351 /* ========================================================  PDCTRGD  ======================================================== */
37352  #define R_SYSTEM_PDCTRGD_PDDE_Pos               (0UL)          /*!< PDDE (Bit 0)                                          */
37353  #define R_SYSTEM_PDCTRGD_PDDE_Msk               (0x1UL)        /*!< PDDE (Bitfield-Mask: 0x01)                            */
37354  #define R_SYSTEM_PDCTRGD_PDCSF_Pos              (6UL)          /*!< PDCSF (Bit 6)                                         */
37355  #define R_SYSTEM_PDCTRGD_PDCSF_Msk              (0x40UL)       /*!< PDCSF (Bitfield-Mask: 0x01)                           */
37356  #define R_SYSTEM_PDCTRGD_PDPGSF_Pos             (7UL)          /*!< PDPGSF (Bit 7)                                        */
37357  #define R_SYSTEM_PDCTRGD_PDPGSF_Msk             (0x80UL)       /*!< PDPGSF (Bitfield-Mask: 0x01)                          */
37358 /* =======================================================  PDRAMSCR0  ======================================================= */
37359 /* =======================================================  PDRAMSCR1  ======================================================= */
37360 /* =======================================================  VBRSABAR  ======================================================== */
37361  #define R_SYSTEM_VBRSABAR_SABA_Pos              (0UL)          /*!< SABA (Bit 0)                                          */
37362  #define R_SYSTEM_VBRSABAR_SABA_Msk              (0xffffUL)     /*!< SABA (Bitfield-Mask: 0xffff)                          */
37363 /* =======================================================  VBRPABARS  ======================================================= */
37364  #define R_SYSTEM_VBRPABARS_PABAS_Pos            (0UL)          /*!< PABAS (Bit 0)                                         */
37365  #define R_SYSTEM_VBRPABARS_PABAS_Msk            (0xffffUL)     /*!< PABAS (Bitfield-Mask: 0xffff)                         */
37366 /* ======================================================  VBRPABARNS  ======================================================= */
37367  #define R_SYSTEM_VBRPABARNS_PABANS_Pos          (0UL)          /*!< PABANS (Bit 0)                                        */
37368  #define R_SYSTEM_VBRPABARNS_PABANS_Msk          (0xffffUL)     /*!< PABANS (Bitfield-Mask: 0xffff)                        */
37369 /* ========================================================  CGFSAR  ========================================================= */
37370  #define R_SYSTEM_CGFSAR_NONSEC00_Pos            (0UL)          /*!< NONSEC00 (Bit 0)                                      */
37371  #define R_SYSTEM_CGFSAR_NONSEC00_Msk            (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
37372  #define R_SYSTEM_CGFSAR_NONSEC02_Pos            (2UL)          /*!< NONSEC02 (Bit 2)                                      */
37373  #define R_SYSTEM_CGFSAR_NONSEC02_Msk            (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
37374  #define R_SYSTEM_CGFSAR_NONSEC03_Pos            (3UL)          /*!< NONSEC03 (Bit 3)                                      */
37375  #define R_SYSTEM_CGFSAR_NONSEC03_Msk            (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
37376  #define R_SYSTEM_CGFSAR_NONSEC04_Pos            (4UL)          /*!< NONSEC04 (Bit 4)                                      */
37377  #define R_SYSTEM_CGFSAR_NONSEC04_Msk            (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
37378  #define R_SYSTEM_CGFSAR_NONSEC05_Pos            (5UL)          /*!< NONSEC05 (Bit 5)                                      */
37379  #define R_SYSTEM_CGFSAR_NONSEC05_Msk            (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
37380  #define R_SYSTEM_CGFSAR_NONSEC06_Pos            (6UL)          /*!< NONSEC06 (Bit 6)                                      */
37381  #define R_SYSTEM_CGFSAR_NONSEC06_Msk            (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
37382  #define R_SYSTEM_CGFSAR_NONSEC07_Pos            (7UL)          /*!< NONSEC07 (Bit 7)                                      */
37383  #define R_SYSTEM_CGFSAR_NONSEC07_Msk            (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
37384  #define R_SYSTEM_CGFSAR_NONSEC08_Pos            (8UL)          /*!< NONSEC08 (Bit 8)                                      */
37385  #define R_SYSTEM_CGFSAR_NONSEC08_Msk            (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
37386  #define R_SYSTEM_CGFSAR_NONSEC09_Pos            (9UL)          /*!< NONSEC09 (Bit 9)                                      */
37387  #define R_SYSTEM_CGFSAR_NONSEC09_Msk            (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
37388  #define R_SYSTEM_CGFSAR_NONSEC11_Pos            (11UL)         /*!< NONSEC11 (Bit 11)                                     */
37389  #define R_SYSTEM_CGFSAR_NONSEC11_Msk            (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
37390  #define R_SYSTEM_CGFSAR_NONSEC12_Pos            (12UL)         /*!< NONSEC12 (Bit 12)                                     */
37391  #define R_SYSTEM_CGFSAR_NONSEC12_Msk            (0x1000UL)     /*!< NONSEC12 (Bitfield-Mask: 0x01)                        */
37392  #define R_SYSTEM_CGFSAR_NONSEC13_Pos            (13UL)         /*!< NONSEC13 (Bit 13)                                     */
37393  #define R_SYSTEM_CGFSAR_NONSEC13_Msk            (0x2000UL)     /*!< NONSEC13 (Bitfield-Mask: 0x01)                        */
37394  #define R_SYSTEM_CGFSAR_NONSEC16_Pos            (16UL)         /*!< NONSEC16 (Bit 16)                                     */
37395  #define R_SYSTEM_CGFSAR_NONSEC16_Msk            (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
37396  #define R_SYSTEM_CGFSAR_NONSEC17_Pos            (17UL)         /*!< NONSEC17 (Bit 17)                                     */
37397  #define R_SYSTEM_CGFSAR_NONSEC17_Msk            (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
37398  #define R_SYSTEM_CGFSAR_NONSEC18_Pos            (18UL)         /*!< NONSEC18 (Bit 18)                                     */
37399  #define R_SYSTEM_CGFSAR_NONSEC18_Msk            (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
37400  #define R_SYSTEM_CGFSAR_NONSEC19_Pos            (19UL)         /*!< NONSEC19 (Bit 19)                                     */
37401  #define R_SYSTEM_CGFSAR_NONSEC19_Msk            (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
37402  #define R_SYSTEM_CGFSAR_NONSEC20_Pos            (20UL)         /*!< NONSEC20 (Bit 20)                                     */
37403  #define R_SYSTEM_CGFSAR_NONSEC20_Msk            (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
37404  #define R_SYSTEM_CGFSAR_NONSEC21_Pos            (21UL)         /*!< NONSEC21 (Bit 21)                                     */
37405  #define R_SYSTEM_CGFSAR_NONSEC21_Msk            (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
37406  #define R_SYSTEM_CGFSAR_NONSEC22_Pos            (22UL)         /*!< NONSEC22 (Bit 22)                                     */
37407  #define R_SYSTEM_CGFSAR_NONSEC22_Msk            (0x400000UL)   /*!< NONSEC22 (Bitfield-Mask: 0x01)                        */
37408  #define R_SYSTEM_CGFSAR_NONSEC24_Pos            (24UL)         /*!< NONSEC24 (Bit 24)                                     */
37409  #define R_SYSTEM_CGFSAR_NONSEC24_Msk            (0x1000000UL)  /*!< NONSEC24 (Bitfield-Mask: 0x01)                        */
37410  #define R_SYSTEM_CGFSAR_NONSEC25_Pos            (25UL)         /*!< NONSEC25 (Bit 25)                                     */
37411  #define R_SYSTEM_CGFSAR_NONSEC25_Msk            (0x2000000UL)  /*!< NONSEC25 (Bitfield-Mask: 0x01)                        */
37412  #define R_SYSTEM_CGFSAR_NONSEC26_Pos            (26UL)         /*!< NONSEC26 (Bit 26)                                     */
37413  #define R_SYSTEM_CGFSAR_NONSEC26_Msk            (0x4000000UL)  /*!< NONSEC26 (Bitfield-Mask: 0x01)                        */
37414 /* ========================================================  RSTSAR  ========================================================= */
37415  #define R_SYSTEM_RSTSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
37416  #define R_SYSTEM_RSTSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
37417  #define R_SYSTEM_RSTSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
37418  #define R_SYSTEM_RSTSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
37419  #define R_SYSTEM_RSTSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
37420  #define R_SYSTEM_RSTSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
37421  #define R_SYSTEM_RSTSAR_NONSEC3_Pos             (3UL)          /*!< NONSEC3 (Bit 3)                                       */
37422  #define R_SYSTEM_RSTSAR_NONSEC3_Msk             (0x8UL)        /*!< NONSEC3 (Bitfield-Mask: 0x01)                         */
37423 /* ========================================================  LPMSAR  ========================================================= */
37424  #define R_SYSTEM_LPMSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
37425  #define R_SYSTEM_LPMSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
37426  #define R_SYSTEM_LPMSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
37427  #define R_SYSTEM_LPMSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
37428  #define R_SYSTEM_LPMSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
37429  #define R_SYSTEM_LPMSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
37430  #define R_SYSTEM_LPMSAR_NONSEC3_Pos             (3UL)          /*!< NONSEC3 (Bit 3)                                       */
37431  #define R_SYSTEM_LPMSAR_NONSEC3_Msk             (0x8UL)        /*!< NONSEC3 (Bitfield-Mask: 0x01)                         */
37432  #define R_SYSTEM_LPMSAR_NONSEC8_Pos             (8UL)          /*!< NONSEC8 (Bit 8)                                       */
37433  #define R_SYSTEM_LPMSAR_NONSEC8_Msk             (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
37434  #define R_SYSTEM_LPMSAR_NONSEC16_Pos            (16UL)         /*!< NONSEC16 (Bit 16)                                     */
37435  #define R_SYSTEM_LPMSAR_NONSEC16_Msk            (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
37436  #define R_SYSTEM_LPMSAR_NONSEC17_Pos            (17UL)         /*!< NONSEC17 (Bit 17)                                     */
37437  #define R_SYSTEM_LPMSAR_NONSEC17_Msk            (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
37438  #define R_SYSTEM_LPMSAR_NONSEC18_Pos            (18UL)         /*!< NONSEC18 (Bit 18)                                     */
37439  #define R_SYSTEM_LPMSAR_NONSEC18_Msk            (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
37440  #define R_SYSTEM_LPMSAR_NONSEC19_Pos            (19UL)         /*!< NONSEC19 (Bit 19)                                     */
37441  #define R_SYSTEM_LPMSAR_NONSEC19_Msk            (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
37442  #define R_SYSTEM_LPMSAR_NONSEC21_Pos            (21UL)         /*!< NONSEC21 (Bit 21)                                     */
37443  #define R_SYSTEM_LPMSAR_NONSEC21_Msk            (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
37444 /* ========================================================  LVDSAR  ========================================================= */
37445  #define R_SYSTEM_LVDSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
37446  #define R_SYSTEM_LVDSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
37447  #define R_SYSTEM_LVDSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
37448  #define R_SYSTEM_LVDSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
37449 /* ========================================================  BBFSAR  ========================================================= */
37450  #define R_SYSTEM_BBFSAR_NONSEC0_Pos             (0UL)          /*!< NONSEC0 (Bit 0)                                       */
37451  #define R_SYSTEM_BBFSAR_NONSEC0_Msk             (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
37452  #define R_SYSTEM_BBFSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
37453  #define R_SYSTEM_BBFSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
37454  #define R_SYSTEM_BBFSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
37455  #define R_SYSTEM_BBFSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
37456  #define R_SYSTEM_BBFSAR_NONSEC3_Pos             (3UL)          /*!< NONSEC3 (Bit 3)                                       */
37457  #define R_SYSTEM_BBFSAR_NONSEC3_Msk             (0x8UL)        /*!< NONSEC3 (Bitfield-Mask: 0x01)                         */
37458  #define R_SYSTEM_BBFSAR_NONSEC4_Pos             (4UL)          /*!< NONSEC4 (Bit 4)                                       */
37459  #define R_SYSTEM_BBFSAR_NONSEC4_Msk             (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
37460 /* ========================================================  PGCSAR  ========================================================= */
37461  #define R_SYSTEM_PGCSAR_NONSEC1_Pos             (1UL)          /*!< NONSEC1 (Bit 1)                                       */
37462  #define R_SYSTEM_PGCSAR_NONSEC1_Msk             (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
37463  #define R_SYSTEM_PGCSAR_NONSEC2_Pos             (2UL)          /*!< NONSEC2 (Bit 2)                                       */
37464  #define R_SYSTEM_PGCSAR_NONSEC2_Msk             (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
37465 /* ========================================================  DPFSAR  ========================================================= */
37466  #define R_SYSTEM_DPFSAR_DPFSA16_Pos             (16UL)         /*!< DPFSA16 (Bit 16)                                      */
37467  #define R_SYSTEM_DPFSAR_DPFSA16_Msk             (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
37468  #define R_SYSTEM_DPFSAR_DPFSA17_Pos             (17UL)         /*!< DPFSA17 (Bit 17)                                      */
37469  #define R_SYSTEM_DPFSAR_DPFSA17_Msk             (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
37470  #define R_SYSTEM_DPFSAR_DPFSA18_Pos             (18UL)         /*!< DPFSA18 (Bit 18)                                      */
37471  #define R_SYSTEM_DPFSAR_DPFSA18_Msk             (0x40000UL)    /*!< DPFSA18 (Bitfield-Mask: 0x01)                         */
37472  #define R_SYSTEM_DPFSAR_DPFSA19_Pos             (19UL)         /*!< DPFSA19 (Bit 19)                                      */
37473  #define R_SYSTEM_DPFSAR_DPFSA19_Msk             (0x80000UL)    /*!< DPFSA19 (Bitfield-Mask: 0x01)                         */
37474  #define R_SYSTEM_DPFSAR_DPFSA20_Pos             (20UL)         /*!< DPFSA20 (Bit 20)                                      */
37475  #define R_SYSTEM_DPFSAR_DPFSA20_Msk             (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
37476  #define R_SYSTEM_DPFSAR_DPFSA24_Pos             (24UL)         /*!< DPFSA24 (Bit 24)                                      */
37477  #define R_SYSTEM_DPFSAR_DPFSA24_Msk             (0x1000000UL)  /*!< DPFSA24 (Bitfield-Mask: 0x01)                         */
37478  #define R_SYSTEM_DPFSAR_DPFSA25_Pos             (25UL)         /*!< DPFSA25 (Bit 25)                                      */
37479  #define R_SYSTEM_DPFSAR_DPFSA25_Msk             (0x2000000UL)  /*!< DPFSA25 (Bitfield-Mask: 0x01)                         */
37480  #define R_SYSTEM_DPFSAR_DPFSA26_Pos             (26UL)         /*!< DPFSA26 (Bit 26)                                      */
37481  #define R_SYSTEM_DPFSAR_DPFSA26_Msk             (0x4000000UL)  /*!< DPFSA26 (Bitfield-Mask: 0x01)                         */
37482  #define R_SYSTEM_DPFSAR_DPFSA27_Pos             (27UL)         /*!< DPFSA27 (Bit 27)                                      */
37483  #define R_SYSTEM_DPFSAR_DPFSA27_Msk             (0x8000000UL)  /*!< DPFSA27 (Bitfield-Mask: 0x01)                         */
37484  #define R_SYSTEM_DPFSAR_DPFSA29_Pos             (29UL)         /*!< DPFSA29 (Bit 29)                                      */
37485  #define R_SYSTEM_DPFSAR_DPFSA29_Msk             (0x20000000UL) /*!< DPFSA29 (Bitfield-Mask: 0x01)                         */
37486  #define R_SYSTEM_DPFSAR_DPFSA31_Pos             (31UL)         /*!< DPFSA31 (Bit 31)                                      */
37487  #define R_SYSTEM_DPFSAR_DPFSA31_Msk             (0x80000000UL) /*!< DPFSA31 (Bitfield-Mask: 0x01)                         */
37488 /* ========================================================  RSCSAR  ========================================================= */
37489  #define R_SYSTEM_RSCSAR_RSCSA0_Pos              (0UL)          /*!< RSCSA0 (Bit 0)                                        */
37490  #define R_SYSTEM_RSCSAR_RSCSA0_Msk              (0x1UL)        /*!< RSCSA0 (Bitfield-Mask: 0x01)                          */
37491  #define R_SYSTEM_RSCSAR_RSCSA1_Pos              (1UL)          /*!< RSCSA1 (Bit 1)                                        */
37492  #define R_SYSTEM_RSCSAR_RSCSA1_Msk              (0x2UL)        /*!< RSCSA1 (Bitfield-Mask: 0x01)                          */
37493  #define R_SYSTEM_RSCSAR_RSCSA2_Pos              (2UL)          /*!< RSCSA2 (Bit 2)                                        */
37494  #define R_SYSTEM_RSCSAR_RSCSA2_Msk              (0x4UL)        /*!< RSCSA2 (Bitfield-Mask: 0x01)                          */
37495  #define R_SYSTEM_RSCSAR_RSCSA3_Pos              (3UL)          /*!< RSCSA3 (Bit 3)                                        */
37496  #define R_SYSTEM_RSCSAR_RSCSA3_Msk              (0x8UL)        /*!< RSCSA3 (Bitfield-Mask: 0x01)                          */
37497  #define R_SYSTEM_RSCSAR_RSCSA4_Pos              (4UL)          /*!< RSCSA4 (Bit 4)                                        */
37498  #define R_SYSTEM_RSCSAR_RSCSA4_Msk              (0x10UL)       /*!< RSCSA4 (Bitfield-Mask: 0x01)                          */
37499  #define R_SYSTEM_RSCSAR_RSCSA5_Pos              (5UL)          /*!< RSCSA5 (Bit 5)                                        */
37500  #define R_SYSTEM_RSCSAR_RSCSA5_Msk              (0x20UL)       /*!< RSCSA5 (Bitfield-Mask: 0x01)                          */
37501  #define R_SYSTEM_RSCSAR_RSCSA6_Pos              (6UL)          /*!< RSCSA6 (Bit 6)                                        */
37502  #define R_SYSTEM_RSCSAR_RSCSA6_Msk              (0x40UL)       /*!< RSCSA6 (Bitfield-Mask: 0x01)                          */
37503  #define R_SYSTEM_RSCSAR_RSCSA7_Pos              (7UL)          /*!< RSCSA7 (Bit 7)                                        */
37504  #define R_SYSTEM_RSCSAR_RSCSA7_Msk              (0x80UL)       /*!< RSCSA7 (Bitfield-Mask: 0x01)                          */
37505  #define R_SYSTEM_RSCSAR_RSCSA8_Pos              (8UL)          /*!< RSCSA8 (Bit 8)                                        */
37506  #define R_SYSTEM_RSCSAR_RSCSA8_Msk              (0x100UL)      /*!< RSCSA8 (Bitfield-Mask: 0x01)                          */
37507  #define R_SYSTEM_RSCSAR_RSCSA9_Pos              (9UL)          /*!< RSCSA9 (Bit 9)                                        */
37508  #define R_SYSTEM_RSCSAR_RSCSA9_Msk              (0x200UL)      /*!< RSCSA9 (Bitfield-Mask: 0x01)                          */
37509  #define R_SYSTEM_RSCSAR_RSCSA10_Pos             (10UL)         /*!< RSCSA10 (Bit 10)                                      */
37510  #define R_SYSTEM_RSCSAR_RSCSA10_Msk             (0x400UL)      /*!< RSCSA10 (Bitfield-Mask: 0x01)                         */
37511  #define R_SYSTEM_RSCSAR_RSCSA11_Pos             (11UL)         /*!< RSCSA11 (Bit 11)                                      */
37512  #define R_SYSTEM_RSCSAR_RSCSA11_Msk             (0x800UL)      /*!< RSCSA11 (Bitfield-Mask: 0x01)                         */
37513  #define R_SYSTEM_RSCSAR_RSCSA12_Pos             (12UL)         /*!< RSCSA12 (Bit 12)                                      */
37514  #define R_SYSTEM_RSCSAR_RSCSA12_Msk             (0x1000UL)     /*!< RSCSA12 (Bitfield-Mask: 0x01)                         */
37515  #define R_SYSTEM_RSCSAR_RSCSA13_Pos             (13UL)         /*!< RSCSA13 (Bit 13)                                      */
37516  #define R_SYSTEM_RSCSAR_RSCSA13_Msk             (0x2000UL)     /*!< RSCSA13 (Bitfield-Mask: 0x01)                         */
37517  #define R_SYSTEM_RSCSAR_RSCSA14_Pos             (14UL)         /*!< RSCSA14 (Bit 14)                                      */
37518  #define R_SYSTEM_RSCSAR_RSCSA14_Msk             (0x4000UL)     /*!< RSCSA14 (Bitfield-Mask: 0x01)                         */
37519  #define R_SYSTEM_RSCSAR_RSCSA16_Pos             (16UL)         /*!< RSCSA16 (Bit 16)                                      */
37520  #define R_SYSTEM_RSCSAR_RSCSA16_Msk             (0x10000UL)    /*!< RSCSA16 (Bitfield-Mask: 0x01)                         */
37521  #define R_SYSTEM_RSCSAR_RSCSA17_Pos             (17UL)         /*!< RSCSA17 (Bit 17)                                      */
37522  #define R_SYSTEM_RSCSAR_RSCSA17_Msk             (0x20000UL)    /*!< RSCSA17 (Bitfield-Mask: 0x01)                         */
37523 /* =========================================================  PRCR  ========================================================== */
37524  #define R_SYSTEM_PRCR_PRC0_Pos                  (0UL)          /*!< PRC0 (Bit 0)                                          */
37525  #define R_SYSTEM_PRCR_PRC0_Msk                  (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
37526  #define R_SYSTEM_PRCR_PRC1_Pos                  (1UL)          /*!< PRC1 (Bit 1)                                          */
37527  #define R_SYSTEM_PRCR_PRC1_Msk                  (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
37528  #define R_SYSTEM_PRCR_PRC3_Pos                  (3UL)          /*!< PRC3 (Bit 3)                                          */
37529  #define R_SYSTEM_PRCR_PRC3_Msk                  (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
37530  #define R_SYSTEM_PRCR_PRC4_Pos                  (4UL)          /*!< PRC4 (Bit 4)                                          */
37531  #define R_SYSTEM_PRCR_PRC4_Msk                  (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
37532  #define R_SYSTEM_PRCR_PRC5_Pos                  (5UL)          /*!< PRC5 (Bit 5)                                          */
37533  #define R_SYSTEM_PRCR_PRC5_Msk                  (0x20UL)       /*!< PRC5 (Bitfield-Mask: 0x01)                            */
37534  #define R_SYSTEM_PRCR_PRKEY_Pos                 (8UL)          /*!< PRKEY (Bit 8)                                         */
37535  #define R_SYSTEM_PRCR_PRKEY_Msk                 (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
37536 /* ========================================================  PRCR_NS  ======================================================== */
37537  #define R_SYSTEM_PRCR_NS_PRC0_Pos               (0UL)          /*!< PRC0 (Bit 0)                                          */
37538  #define R_SYSTEM_PRCR_NS_PRC0_Msk               (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
37539  #define R_SYSTEM_PRCR_NS_PRC1_Pos               (1UL)          /*!< PRC1 (Bit 1)                                          */
37540  #define R_SYSTEM_PRCR_NS_PRC1_Msk               (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
37541  #define R_SYSTEM_PRCR_NS_PRC3_Pos               (3UL)          /*!< PRC3 (Bit 3)                                          */
37542  #define R_SYSTEM_PRCR_NS_PRC3_Msk               (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
37543  #define R_SYSTEM_PRCR_NS_PRC4_Pos               (4UL)          /*!< PRC4 (Bit 4)                                          */
37544  #define R_SYSTEM_PRCR_NS_PRC4_Msk               (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
37545  #define R_SYSTEM_PRCR_NS_PRKEY_Pos              (8UL)          /*!< PRKEY (Bit 8)                                         */
37546  #define R_SYSTEM_PRCR_NS_PRKEY_Msk              (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
37547 /* ========================================================  LOCOCR  ========================================================= */
37548  #define R_SYSTEM_LOCOCR_LCSTP_Pos               (0UL)          /*!< LCSTP (Bit 0)                                         */
37549  #define R_SYSTEM_LOCOCR_LCSTP_Msk               (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
37550 /* =======================================================  LOCOUTCR  ======================================================== */
37551  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos          (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
37552  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk          (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
37553 /* ========================================================  STCONR  ========================================================= */
37554  #define R_SYSTEM_STCONR_STCON_Pos               (0UL)          /*!< STCON (Bit 0)                                         */
37555  #define R_SYSTEM_STCONR_STCON_Msk               (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
37556 /* ========================================================  DPSBYCR  ======================================================== */
37557  #define R_SYSTEM_DPSBYCR_DCSSMODE_Pos           (2UL)          /*!< DCSSMODE (Bit 2)                                      */
37558  #define R_SYSTEM_DPSBYCR_DCSSMODE_Msk           (0x4UL)        /*!< DCSSMODE (Bitfield-Mask: 0x01)                        */
37559  #define R_SYSTEM_DPSBYCR_SRKEEP_Pos             (4UL)          /*!< SRKEEP (Bit 4)                                        */
37560  #define R_SYSTEM_DPSBYCR_SRKEEP_Msk             (0x10UL)       /*!< SRKEEP (Bitfield-Mask: 0x01)                          */
37561  #define R_SYSTEM_DPSBYCR_IOKEEP_Pos             (6UL)          /*!< IOKEEP (Bit 6)                                        */
37562  #define R_SYSTEM_DPSBYCR_IOKEEP_Msk             (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
37563  #define R_SYSTEM_DPSBYCR_DPSBY_Pos              (7UL)          /*!< DPSBY (Bit 7)                                         */
37564  #define R_SYSTEM_DPSBYCR_DPSBY_Msk              (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
37565 /* ========================================================  DPSWCR  ========================================================= */
37566  #define R_SYSTEM_DPSWCR_WTSTS_Pos               (0UL)          /*!< WTSTS (Bit 0)                                         */
37567  #define R_SYSTEM_DPSWCR_WTSTS_Msk               (0xffUL)       /*!< WTSTS (Bitfield-Mask: 0xff)                           */
37568 /* ========================================================  DPSIER0  ======================================================== */
37569  #define R_SYSTEM_DPSIER0_DIRQ0E_Pos             (0UL)          /*!< DIRQ0E (Bit 0)                                        */
37570  #define R_SYSTEM_DPSIER0_DIRQ0E_Msk             (0x1UL)        /*!< DIRQ0E (Bitfield-Mask: 0x01)                          */
37571  #define R_SYSTEM_DPSIER0_DIRQ1E_Pos             (1UL)          /*!< DIRQ1E (Bit 1)                                        */
37572  #define R_SYSTEM_DPSIER0_DIRQ1E_Msk             (0x2UL)        /*!< DIRQ1E (Bitfield-Mask: 0x01)                          */
37573  #define R_SYSTEM_DPSIER0_DIRQ2E_Pos             (2UL)          /*!< DIRQ2E (Bit 2)                                        */
37574  #define R_SYSTEM_DPSIER0_DIRQ2E_Msk             (0x4UL)        /*!< DIRQ2E (Bitfield-Mask: 0x01)                          */
37575  #define R_SYSTEM_DPSIER0_DIRQ3E_Pos             (3UL)          /*!< DIRQ3E (Bit 3)                                        */
37576  #define R_SYSTEM_DPSIER0_DIRQ3E_Msk             (0x8UL)        /*!< DIRQ3E (Bitfield-Mask: 0x01)                          */
37577  #define R_SYSTEM_DPSIER0_DIRQ4E_Pos             (4UL)          /*!< DIRQ4E (Bit 4)                                        */
37578  #define R_SYSTEM_DPSIER0_DIRQ4E_Msk             (0x10UL)       /*!< DIRQ4E (Bitfield-Mask: 0x01)                          */
37579  #define R_SYSTEM_DPSIER0_DIRQ5E_Pos             (5UL)          /*!< DIRQ5E (Bit 5)                                        */
37580  #define R_SYSTEM_DPSIER0_DIRQ5E_Msk             (0x20UL)       /*!< DIRQ5E (Bitfield-Mask: 0x01)                          */
37581  #define R_SYSTEM_DPSIER0_DIRQ6E_Pos             (6UL)          /*!< DIRQ6E (Bit 6)                                        */
37582  #define R_SYSTEM_DPSIER0_DIRQ6E_Msk             (0x40UL)       /*!< DIRQ6E (Bitfield-Mask: 0x01)                          */
37583  #define R_SYSTEM_DPSIER0_DIRQ7E_Pos             (7UL)          /*!< DIRQ7E (Bit 7)                                        */
37584  #define R_SYSTEM_DPSIER0_DIRQ7E_Msk             (0x80UL)       /*!< DIRQ7E (Bitfield-Mask: 0x01)                          */
37585 /* ========================================================  DPSIER1  ======================================================== */
37586  #define R_SYSTEM_DPSIER1_DIRQ8E_Pos             (0UL)          /*!< DIRQ8E (Bit 0)                                        */
37587  #define R_SYSTEM_DPSIER1_DIRQ8E_Msk             (0x1UL)        /*!< DIRQ8E (Bitfield-Mask: 0x01)                          */
37588  #define R_SYSTEM_DPSIER1_DIRQ9E_Pos             (1UL)          /*!< DIRQ9E (Bit 1)                                        */
37589  #define R_SYSTEM_DPSIER1_DIRQ9E_Msk             (0x2UL)        /*!< DIRQ9E (Bitfield-Mask: 0x01)                          */
37590  #define R_SYSTEM_DPSIER1_DIRQ10E_Pos            (2UL)          /*!< DIRQ10E (Bit 2)                                       */
37591  #define R_SYSTEM_DPSIER1_DIRQ10E_Msk            (0x4UL)        /*!< DIRQ10E (Bitfield-Mask: 0x01)                         */
37592  #define R_SYSTEM_DPSIER1_DIRQ11E_Pos            (3UL)          /*!< DIRQ11E (Bit 3)                                       */
37593  #define R_SYSTEM_DPSIER1_DIRQ11E_Msk            (0x8UL)        /*!< DIRQ11E (Bitfield-Mask: 0x01)                         */
37594  #define R_SYSTEM_DPSIER1_DIRQ12E_Pos            (4UL)          /*!< DIRQ12E (Bit 4)                                       */
37595  #define R_SYSTEM_DPSIER1_DIRQ12E_Msk            (0x10UL)       /*!< DIRQ12E (Bitfield-Mask: 0x01)                         */
37596  #define R_SYSTEM_DPSIER1_DIRQ13E_Pos            (5UL)          /*!< DIRQ13E (Bit 5)                                       */
37597  #define R_SYSTEM_DPSIER1_DIRQ13E_Msk            (0x20UL)       /*!< DIRQ13E (Bitfield-Mask: 0x01)                         */
37598  #define R_SYSTEM_DPSIER1_DIRQ14E_Pos            (6UL)          /*!< DIRQ14E (Bit 6)                                       */
37599  #define R_SYSTEM_DPSIER1_DIRQ14E_Msk            (0x40UL)       /*!< DIRQ14E (Bitfield-Mask: 0x01)                         */
37600  #define R_SYSTEM_DPSIER1_DIRQ15E_Pos            (7UL)          /*!< DIRQ15E (Bit 7)                                       */
37601  #define R_SYSTEM_DPSIER1_DIRQ15E_Msk            (0x80UL)       /*!< DIRQ15E (Bitfield-Mask: 0x01)                         */
37602 /* ========================================================  DPSIER2  ======================================================== */
37603  #define R_SYSTEM_DPSIER2_DPVD1IE_Pos            (0UL)          /*!< DPVD1IE (Bit 0)                                       */
37604  #define R_SYSTEM_DPSIER2_DPVD1IE_Msk            (0x1UL)        /*!< DPVD1IE (Bitfield-Mask: 0x01)                         */
37605  #define R_SYSTEM_DPSIER2_DPVD2IE_Pos            (1UL)          /*!< DPVD2IE (Bit 1)                                       */
37606  #define R_SYSTEM_DPSIER2_DPVD2IE_Msk            (0x2UL)        /*!< DPVD2IE (Bitfield-Mask: 0x01)                         */
37607  #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos           (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
37608  #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk           (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
37609  #define R_SYSTEM_DPSIER2_DRTCAIE_Pos            (3UL)          /*!< DRTCAIE (Bit 3)                                       */
37610  #define R_SYSTEM_DPSIER2_DRTCAIE_Msk            (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
37611  #define R_SYSTEM_DPSIER2_DNMIE_Pos              (4UL)          /*!< DNMIE (Bit 4)                                         */
37612  #define R_SYSTEM_DPSIER2_DNMIE_Msk              (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
37613 /* ========================================================  DPSIER3  ======================================================== */
37614  #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos           (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
37615  #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk           (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
37616  #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos           (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
37617  #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk           (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
37618  #define R_SYSTEM_DPSIER3_DULPT0IE_Pos           (2UL)          /*!< DULPT0IE (Bit 2)                                      */
37619  #define R_SYSTEM_DPSIER3_DULPT0IE_Msk           (0x4UL)        /*!< DULPT0IE (Bitfield-Mask: 0x01)                        */
37620  #define R_SYSTEM_DPSIER3_DULPT1IE_Pos           (3UL)          /*!< DULPT1IE (Bit 3)                                      */
37621  #define R_SYSTEM_DPSIER3_DULPT1IE_Msk           (0x8UL)        /*!< DULPT1IE (Bitfield-Mask: 0x01)                        */
37622  #define R_SYSTEM_DPSIER3_DIWDTIE_Pos            (5UL)          /*!< DIWDTIE (Bit 5)                                       */
37623  #define R_SYSTEM_DPSIER3_DIWDTIE_Msk            (0x20UL)       /*!< DIWDTIE (Bitfield-Mask: 0x01)                         */
37624  #define R_SYSTEM_DPSIER3_DVBATTADIE_Pos         (7UL)          /*!< DVBATTADIE (Bit 7)                                    */
37625  #define R_SYSTEM_DPSIER3_DVBATTADIE_Msk         (0x80UL)       /*!< DVBATTADIE (Bitfield-Mask: 0x01)                      */
37626 /* ========================================================  DPSIFR0  ======================================================== */
37627  #define R_SYSTEM_DPSIFR0_DIRQ0F_Pos             (0UL)          /*!< DIRQ0F (Bit 0)                                        */
37628  #define R_SYSTEM_DPSIFR0_DIRQ0F_Msk             (0x1UL)        /*!< DIRQ0F (Bitfield-Mask: 0x01)                          */
37629  #define R_SYSTEM_DPSIFR0_DIRQ1F_Pos             (1UL)          /*!< DIRQ1F (Bit 1)                                        */
37630  #define R_SYSTEM_DPSIFR0_DIRQ1F_Msk             (0x2UL)        /*!< DIRQ1F (Bitfield-Mask: 0x01)                          */
37631  #define R_SYSTEM_DPSIFR0_DIRQ2F_Pos             (2UL)          /*!< DIRQ2F (Bit 2)                                        */
37632  #define R_SYSTEM_DPSIFR0_DIRQ2F_Msk             (0x4UL)        /*!< DIRQ2F (Bitfield-Mask: 0x01)                          */
37633  #define R_SYSTEM_DPSIFR0_DIRQ3F_Pos             (3UL)          /*!< DIRQ3F (Bit 3)                                        */
37634  #define R_SYSTEM_DPSIFR0_DIRQ3F_Msk             (0x8UL)        /*!< DIRQ3F (Bitfield-Mask: 0x01)                          */
37635  #define R_SYSTEM_DPSIFR0_DIRQ4F_Pos             (4UL)          /*!< DIRQ4F (Bit 4)                                        */
37636  #define R_SYSTEM_DPSIFR0_DIRQ4F_Msk             (0x10UL)       /*!< DIRQ4F (Bitfield-Mask: 0x01)                          */
37637  #define R_SYSTEM_DPSIFR0_DIRQ5F_Pos             (5UL)          /*!< DIRQ5F (Bit 5)                                        */
37638  #define R_SYSTEM_DPSIFR0_DIRQ5F_Msk             (0x20UL)       /*!< DIRQ5F (Bitfield-Mask: 0x01)                          */
37639  #define R_SYSTEM_DPSIFR0_DIRQ6F_Pos             (6UL)          /*!< DIRQ6F (Bit 6)                                        */
37640  #define R_SYSTEM_DPSIFR0_DIRQ6F_Msk             (0x40UL)       /*!< DIRQ6F (Bitfield-Mask: 0x01)                          */
37641  #define R_SYSTEM_DPSIFR0_DIRQ7F_Pos             (7UL)          /*!< DIRQ7F (Bit 7)                                        */
37642  #define R_SYSTEM_DPSIFR0_DIRQ7F_Msk             (0x80UL)       /*!< DIRQ7F (Bitfield-Mask: 0x01)                          */
37643 /* ========================================================  DPSIFR1  ======================================================== */
37644  #define R_SYSTEM_DPSIFR1_DIRQ8F_Pos             (0UL)          /*!< DIRQ8F (Bit 0)                                        */
37645  #define R_SYSTEM_DPSIFR1_DIRQ8F_Msk             (0x1UL)        /*!< DIRQ8F (Bitfield-Mask: 0x01)                          */
37646  #define R_SYSTEM_DPSIFR1_DIRQ9F_Pos             (1UL)          /*!< DIRQ9F (Bit 1)                                        */
37647  #define R_SYSTEM_DPSIFR1_DIRQ9F_Msk             (0x2UL)        /*!< DIRQ9F (Bitfield-Mask: 0x01)                          */
37648  #define R_SYSTEM_DPSIFR1_DIRQ10F_Pos            (2UL)          /*!< DIRQ10F (Bit 2)                                       */
37649  #define R_SYSTEM_DPSIFR1_DIRQ10F_Msk            (0x4UL)        /*!< DIRQ10F (Bitfield-Mask: 0x01)                         */
37650  #define R_SYSTEM_DPSIFR1_DIRQ11F_Pos            (3UL)          /*!< DIRQ11F (Bit 3)                                       */
37651  #define R_SYSTEM_DPSIFR1_DIRQ11F_Msk            (0x8UL)        /*!< DIRQ11F (Bitfield-Mask: 0x01)                         */
37652  #define R_SYSTEM_DPSIFR1_DIRQ12F_Pos            (4UL)          /*!< DIRQ12F (Bit 4)                                       */
37653  #define R_SYSTEM_DPSIFR1_DIRQ12F_Msk            (0x10UL)       /*!< DIRQ12F (Bitfield-Mask: 0x01)                         */
37654  #define R_SYSTEM_DPSIFR1_DIRQ13F_Pos            (5UL)          /*!< DIRQ13F (Bit 5)                                       */
37655  #define R_SYSTEM_DPSIFR1_DIRQ13F_Msk            (0x20UL)       /*!< DIRQ13F (Bitfield-Mask: 0x01)                         */
37656  #define R_SYSTEM_DPSIFR1_DIRQ14F_Pos            (6UL)          /*!< DIRQ14F (Bit 6)                                       */
37657  #define R_SYSTEM_DPSIFR1_DIRQ14F_Msk            (0x40UL)       /*!< DIRQ14F (Bitfield-Mask: 0x01)                         */
37658  #define R_SYSTEM_DPSIFR1_DIRQ15F_Pos            (7UL)          /*!< DIRQ15F (Bit 7)                                       */
37659  #define R_SYSTEM_DPSIFR1_DIRQ15F_Msk            (0x80UL)       /*!< DIRQ15F (Bitfield-Mask: 0x01)                         */
37660 /* ========================================================  DPSIFR2  ======================================================== */
37661  #define R_SYSTEM_DPSIFR2_DPVD1IF_Pos            (0UL)          /*!< DPVD1IF (Bit 0)                                       */
37662  #define R_SYSTEM_DPSIFR2_DPVD1IF_Msk            (0x1UL)        /*!< DPVD1IF (Bitfield-Mask: 0x01)                         */
37663  #define R_SYSTEM_DPSIFR2_DPVD2IF_Pos            (1UL)          /*!< DPVD2IF (Bit 1)                                       */
37664  #define R_SYSTEM_DPSIFR2_DPVD2IF_Msk            (0x2UL)        /*!< DPVD2IF (Bitfield-Mask: 0x01)                         */
37665  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos           (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
37666  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk           (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
37667  #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos            (3UL)          /*!< DRTCAIF (Bit 3)                                       */
37668  #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk            (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
37669  #define R_SYSTEM_DPSIFR2_DNMIF_Pos              (4UL)          /*!< DNMIF (Bit 4)                                         */
37670  #define R_SYSTEM_DPSIFR2_DNMIF_Msk              (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
37671 /* ========================================================  DPSIFR3  ======================================================== */
37672  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos           (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
37673  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk           (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
37674  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos           (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
37675  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk           (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
37676  #define R_SYSTEM_DPSIFR3_DULPT0IF_Pos           (2UL)          /*!< DULPT0IF (Bit 2)                                      */
37677  #define R_SYSTEM_DPSIFR3_DULPT0IF_Msk           (0x4UL)        /*!< DULPT0IF (Bitfield-Mask: 0x01)                        */
37678  #define R_SYSTEM_DPSIFR3_DULPT1IF_Pos           (3UL)          /*!< DULPT1IF (Bit 3)                                      */
37679  #define R_SYSTEM_DPSIFR3_DULPT1IF_Msk           (0x8UL)        /*!< DULPT1IF (Bitfield-Mask: 0x01)                        */
37680  #define R_SYSTEM_DPSIFR3_DIWDTIF_Pos            (5UL)          /*!< DIWDTIF (Bit 5)                                       */
37681  #define R_SYSTEM_DPSIFR3_DIWDTIF_Msk            (0x20UL)       /*!< DIWDTIF (Bitfield-Mask: 0x01)                         */
37682  #define R_SYSTEM_DPSIFR3_DVBATTADIF_Pos         (7UL)          /*!< DVBATTADIF (Bit 7)                                    */
37683  #define R_SYSTEM_DPSIFR3_DVBATTADIF_Msk         (0x80UL)       /*!< DVBATTADIF (Bitfield-Mask: 0x01)                      */
37684 /* =======================================================  DPSIEGR0  ======================================================== */
37685  #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Pos           (0UL)          /*!< DIRQ0EG (Bit 0)                                       */
37686  #define R_SYSTEM_DPSIEGR0_DIRQ0EG_Msk           (0x1UL)        /*!< DIRQ0EG (Bitfield-Mask: 0x01)                         */
37687  #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Pos           (1UL)          /*!< DIRQ1EG (Bit 1)                                       */
37688  #define R_SYSTEM_DPSIEGR0_DIRQ1EG_Msk           (0x2UL)        /*!< DIRQ1EG (Bitfield-Mask: 0x01)                         */
37689  #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Pos           (2UL)          /*!< DIRQ2EG (Bit 2)                                       */
37690  #define R_SYSTEM_DPSIEGR0_DIRQ2EG_Msk           (0x4UL)        /*!< DIRQ2EG (Bitfield-Mask: 0x01)                         */
37691  #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Pos           (3UL)          /*!< DIRQ3EG (Bit 3)                                       */
37692  #define R_SYSTEM_DPSIEGR0_DIRQ3EG_Msk           (0x8UL)        /*!< DIRQ3EG (Bitfield-Mask: 0x01)                         */
37693  #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Pos           (4UL)          /*!< DIRQ4EG (Bit 4)                                       */
37694  #define R_SYSTEM_DPSIEGR0_DIRQ4EG_Msk           (0x10UL)       /*!< DIRQ4EG (Bitfield-Mask: 0x01)                         */
37695  #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Pos           (5UL)          /*!< DIRQ5EG (Bit 5)                                       */
37696  #define R_SYSTEM_DPSIEGR0_DIRQ5EG_Msk           (0x20UL)       /*!< DIRQ5EG (Bitfield-Mask: 0x01)                         */
37697  #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Pos           (6UL)          /*!< DIRQ6EG (Bit 6)                                       */
37698  #define R_SYSTEM_DPSIEGR0_DIRQ6EG_Msk           (0x40UL)       /*!< DIRQ6EG (Bitfield-Mask: 0x01)                         */
37699  #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Pos           (7UL)          /*!< DIRQ7EG (Bit 7)                                       */
37700  #define R_SYSTEM_DPSIEGR0_DIRQ7EG_Msk           (0x80UL)       /*!< DIRQ7EG (Bitfield-Mask: 0x01)                         */
37701 /* =======================================================  DPSIEGR1  ======================================================== */
37702  #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Pos           (0UL)          /*!< DIRQ8EG (Bit 0)                                       */
37703  #define R_SYSTEM_DPSIEGR1_DIRQ8EG_Msk           (0x1UL)        /*!< DIRQ8EG (Bitfield-Mask: 0x01)                         */
37704  #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Pos           (1UL)          /*!< DIRQ9EG (Bit 1)                                       */
37705  #define R_SYSTEM_DPSIEGR1_DIRQ9EG_Msk           (0x2UL)        /*!< DIRQ9EG (Bitfield-Mask: 0x01)                         */
37706  #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Pos          (2UL)          /*!< DIRQ10EG (Bit 2)                                      */
37707  #define R_SYSTEM_DPSIEGR1_DIRQ10EG_Msk          (0x4UL)        /*!< DIRQ10EG (Bitfield-Mask: 0x01)                        */
37708  #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Pos          (3UL)          /*!< DIRQ11EG (Bit 3)                                      */
37709  #define R_SYSTEM_DPSIEGR1_DIRQ11EG_Msk          (0x8UL)        /*!< DIRQ11EG (Bitfield-Mask: 0x01)                        */
37710  #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Pos          (4UL)          /*!< DIRQ12EG (Bit 4)                                      */
37711  #define R_SYSTEM_DPSIEGR1_DIRQ12EG_Msk          (0x10UL)       /*!< DIRQ12EG (Bitfield-Mask: 0x01)                        */
37712  #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Pos          (5UL)          /*!< DIRQ13EG (Bit 5)                                      */
37713  #define R_SYSTEM_DPSIEGR1_DIRQ13EG_Msk          (0x20UL)       /*!< DIRQ13EG (Bitfield-Mask: 0x01)                        */
37714  #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Pos          (6UL)          /*!< DIRQ14EG (Bit 6)                                      */
37715  #define R_SYSTEM_DPSIEGR1_DIRQ14EG_Msk          (0x40UL)       /*!< DIRQ14EG (Bitfield-Mask: 0x01)                        */
37716  #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Pos          (7UL)          /*!< DIRQ15EG (Bit 7)                                      */
37717  #define R_SYSTEM_DPSIEGR1_DIRQ15EG_Msk          (0x80UL)       /*!< DIRQ15EG (Bitfield-Mask: 0x01)                        */
37718 /* =======================================================  DPSIEGR2  ======================================================== */
37719  #define R_SYSTEM_DPSIEGR2_DPVD1EG_Pos           (0UL)          /*!< DPVD1EG (Bit 0)                                       */
37720  #define R_SYSTEM_DPSIEGR2_DPVD1EG_Msk           (0x1UL)        /*!< DPVD1EG (Bitfield-Mask: 0x01)                         */
37721  #define R_SYSTEM_DPSIEGR2_DPVD2EG_Pos           (1UL)          /*!< DPVD2EG (Bit 1)                                       */
37722  #define R_SYSTEM_DPSIEGR2_DPVD2EG_Msk           (0x2UL)        /*!< DPVD2EG (Bitfield-Mask: 0x01)                         */
37723  #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos            (4UL)          /*!< DNMIEG (Bit 4)                                        */
37724  #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk            (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
37725 /* ========================================================  SYOCDCR  ======================================================== */
37726  #define R_SYSTEM_SYOCDCR_DOCDF_Pos              (0UL)          /*!< DOCDF (Bit 0)                                         */
37727  #define R_SYSTEM_SYOCDCR_DOCDF_Msk              (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
37728  #define R_SYSTEM_SYOCDCR_DBGEN_Pos              (7UL)          /*!< DBGEN (Bit 7)                                         */
37729  #define R_SYSTEM_SYOCDCR_DBGEN_Msk              (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
37730 /* ========================================================  RSTSR0  ========================================================= */
37731  #define R_SYSTEM_RSTSR0_PORF_Pos                (0UL)          /*!< PORF (Bit 0)                                          */
37732  #define R_SYSTEM_RSTSR0_PORF_Msk                (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
37733  #define R_SYSTEM_RSTSR0_LVD0RF_Pos              (1UL)          /*!< LVD0RF (Bit 1)                                        */
37734  #define R_SYSTEM_RSTSR0_LVD0RF_Msk              (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
37735  #define R_SYSTEM_RSTSR0_LVD1RF_Pos              (2UL)          /*!< LVD1RF (Bit 2)                                        */
37736  #define R_SYSTEM_RSTSR0_LVD1RF_Msk              (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
37737  #define R_SYSTEM_RSTSR0_LVD2RF_Pos              (3UL)          /*!< LVD2RF (Bit 3)                                        */
37738  #define R_SYSTEM_RSTSR0_LVD2RF_Msk              (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
37739  #define R_SYSTEM_RSTSR0_LVD3RF_Pos              (4UL)          /*!< LVD3RF (Bit 4)                                        */
37740  #define R_SYSTEM_RSTSR0_LVD3RF_Msk              (0x10UL)       /*!< LVD3RF (Bitfield-Mask: 0x01)                          */
37741  #define R_SYSTEM_RSTSR0_LVD4RF_Pos              (5UL)          /*!< LVD4RF (Bit 5)                                        */
37742  #define R_SYSTEM_RSTSR0_LVD4RF_Msk              (0x20UL)       /*!< LVD4RF (Bitfield-Mask: 0x01)                          */
37743  #define R_SYSTEM_RSTSR0_LVD5RF_Pos              (6UL)          /*!< LVD5RF (Bit 6)                                        */
37744  #define R_SYSTEM_RSTSR0_LVD5RF_Msk              (0x40UL)       /*!< LVD5RF (Bitfield-Mask: 0x01)                          */
37745  #define R_SYSTEM_RSTSR0_DPSRSTF_Pos             (7UL)          /*!< DPSRSTF (Bit 7)                                       */
37746  #define R_SYSTEM_RSTSR0_DPSRSTF_Msk             (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
37747 /* ========================================================  RSTSR2  ========================================================= */
37748  #define R_SYSTEM_RSTSR2_CWSF_Pos                (0UL)          /*!< CWSF (Bit 0)                                          */
37749  #define R_SYSTEM_RSTSR2_CWSF_Msk                (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
37750 /* ========================================================  RSTSR3  ========================================================= */
37751  #define R_SYSTEM_RSTSR3_OCPRF_Pos               (4UL)          /*!< OCPRF (Bit 4)                                         */
37752  #define R_SYSTEM_RSTSR3_OCPRF_Msk               (0x10UL)       /*!< OCPRF (Bitfield-Mask: 0x01)                           */
37753 /* =========================================================  MOMCR  ========================================================= */
37754  #define R_SYSTEM_MOMCR_MODRV0_Pos               (1UL)          /*!< MODRV0 (Bit 1)                                        */
37755  #define R_SYSTEM_MOMCR_MODRV0_Msk               (0xeUL)        /*!< MODRV0 (Bitfield-Mask: 0x07)                          */
37756  #define R_SYSTEM_MOMCR_MOSEL_Pos                (6UL)          /*!< MOSEL (Bit 6)                                         */
37757  #define R_SYSTEM_MOMCR_MOSEL_Msk                (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
37758 /* ========================================================  FWEPROR  ======================================================== */
37759  #define R_SYSTEM_FWEPROR_FLWE_Pos               (0UL)          /*!< FLWE (Bit 0)                                          */
37760  #define R_SYSTEM_FWEPROR_FLWE_Msk               (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
37761 /* ========================================================  LVCMPCR  ======================================================== */
37762  #define R_SYSTEM_LVCMPCR_LVD2E_Pos              (6UL)          /*!< LVD2E (Bit 6)                                         */
37763  #define R_SYSTEM_LVCMPCR_LVD2E_Msk              (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
37764  #define R_SYSTEM_LVCMPCR_LVD1E_Pos              (5UL)          /*!< LVD1E (Bit 5)                                         */
37765  #define R_SYSTEM_LVCMPCR_LVD1E_Msk              (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
37766 /* =======================================================  LVD1CMPCR  ======================================================= */
37767  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos          (0UL)          /*!< LVD1LVL (Bit 0)                                       */
37768  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk          (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
37769  #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos            (7UL)          /*!< LVD1E (Bit 7)                                         */
37770  #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk            (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
37771 /* =======================================================  LVD2CMPCR  ======================================================= */
37772  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos          (0UL)          /*!< LVD2LVL (Bit 0)                                       */
37773  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk          (0x1fUL)       /*!< LVD2LVL (Bitfield-Mask: 0x1f)                         */
37774  #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos            (7UL)          /*!< LVD2E (Bit 7)                                         */
37775  #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk            (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
37776 /* ========================================================  LVD1CR0  ======================================================== */
37777  #define R_SYSTEM_LVD1CR0_RIE_Pos                (0UL)          /*!< RIE (Bit 0)                                           */
37778  #define R_SYSTEM_LVD1CR0_RIE_Msk                (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
37779  #define R_SYSTEM_LVD1CR0_DFDIS_Pos              (1UL)          /*!< DFDIS (Bit 1)                                         */
37780  #define R_SYSTEM_LVD1CR0_DFDIS_Msk              (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
37781  #define R_SYSTEM_LVD1CR0_CMPE_Pos               (2UL)          /*!< CMPE (Bit 2)                                          */
37782  #define R_SYSTEM_LVD1CR0_CMPE_Msk               (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
37783  #define R_SYSTEM_LVD1CR0_FSAMP_Pos              (4UL)          /*!< FSAMP (Bit 4)                                         */
37784  #define R_SYSTEM_LVD1CR0_FSAMP_Msk              (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
37785  #define R_SYSTEM_LVD1CR0_RI_Pos                 (6UL)          /*!< RI (Bit 6)                                            */
37786  #define R_SYSTEM_LVD1CR0_RI_Msk                 (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
37787  #define R_SYSTEM_LVD1CR0_RN_Pos                 (7UL)          /*!< RN (Bit 7)                                            */
37788  #define R_SYSTEM_LVD1CR0_RN_Msk                 (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
37789 /* ========================================================  LVD2CR0  ======================================================== */
37790  #define R_SYSTEM_LVD2CR0_RIE_Pos                (0UL)          /*!< RIE (Bit 0)                                           */
37791  #define R_SYSTEM_LVD2CR0_RIE_Msk                (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
37792  #define R_SYSTEM_LVD2CR0_DFDIS_Pos              (1UL)          /*!< DFDIS (Bit 1)                                         */
37793  #define R_SYSTEM_LVD2CR0_DFDIS_Msk              (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
37794  #define R_SYSTEM_LVD2CR0_CMPE_Pos               (2UL)          /*!< CMPE (Bit 2)                                          */
37795  #define R_SYSTEM_LVD2CR0_CMPE_Msk               (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
37796  #define R_SYSTEM_LVD2CR0_FSAMP_Pos              (4UL)          /*!< FSAMP (Bit 4)                                         */
37797  #define R_SYSTEM_LVD2CR0_FSAMP_Msk              (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
37798  #define R_SYSTEM_LVD2CR0_RI_Pos                 (6UL)          /*!< RI (Bit 6)                                            */
37799  #define R_SYSTEM_LVD2CR0_RI_Msk                 (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
37800  #define R_SYSTEM_LVD2CR0_RN_Pos                 (7UL)          /*!< RN (Bit 7)                                            */
37801  #define R_SYSTEM_LVD2CR0_RN_Msk                 (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
37802 /* ======================================================  VBATTMNSELR  ====================================================== */
37803  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos     (0UL)          /*!< VBATTMNSEL (Bit 0)                                    */
37804  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk     (0x1UL)        /*!< VBATTMNSEL (Bitfield-Mask: 0x01)                      */
37805 /* =======================================================  VBTBPCR1  ======================================================== */
37806  #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Pos          (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
37807  #define R_SYSTEM_VBTBPCR1_BPWSWSTP_Msk          (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
37808 /* =========================================================  LPSCR  ========================================================= */
37809  #define R_SYSTEM_LPSCR_LPMD_Pos                 (0UL)          /*!< LPMD (Bit 0)                                          */
37810  #define R_SYSTEM_LPSCR_LPMD_Msk                 (0xfUL)        /*!< LPMD (Bitfield-Mask: 0x0f)                            */
37811 /* =========================================================  SSCR1  ========================================================= */
37812  #define R_SYSTEM_SSCR1_SS1FR_Pos                (0UL)          /*!< SS1FR (Bit 0)                                         */
37813  #define R_SYSTEM_SSCR1_SS1FR_Msk                (0x1UL)        /*!< SS1FR (Bitfield-Mask: 0x01)                           */
37814 /* =========================================================  LVOCR  ========================================================= */
37815  #define R_SYSTEM_LVOCR_LVO0E_Pos                (0UL)          /*!< LVO0E (Bit 0)                                         */
37816  #define R_SYSTEM_LVOCR_LVO0E_Msk                (0x1UL)        /*!< LVO0E (Bitfield-Mask: 0x01)                           */
37817  #define R_SYSTEM_LVOCR_LVO1E_Pos                (1UL)          /*!< LVO1E (Bit 1)                                         */
37818  #define R_SYSTEM_LVOCR_LVO1E_Msk                (0x2UL)        /*!< LVO1E (Bitfield-Mask: 0x01)                           */
37819 /* =======================================================  SYRSTMSK0  ======================================================= */
37820  #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Pos         (0UL)          /*!< IWDTMASK (Bit 0)                                      */
37821  #define R_SYSTEM_SYRSTMSK0_IWDTMASK_Msk         (0x1UL)        /*!< IWDTMASK (Bitfield-Mask: 0x01)                        */
37822  #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Pos         (1UL)          /*!< WDT0MASK (Bit 1)                                      */
37823  #define R_SYSTEM_SYRSTMSK0_WDT0MASK_Msk         (0x2UL)        /*!< WDT0MASK (Bitfield-Mask: 0x01)                        */
37824  #define R_SYSTEM_SYRSTMSK0_SWMASK_Pos           (2UL)          /*!< SWMASK (Bit 2)                                        */
37825  #define R_SYSTEM_SYRSTMSK0_SWMASK_Msk           (0x4UL)        /*!< SWMASK (Bitfield-Mask: 0x01)                          */
37826  #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Pos        (4UL)          /*!< CLUP0MASK (Bit 4)                                     */
37827  #define R_SYSTEM_SYRSTMSK0_CLUP0MASK_Msk        (0x10UL)       /*!< CLUP0MASK (Bitfield-Mask: 0x01)                       */
37828  #define R_SYSTEM_SYRSTMSK0_LM0MASK_Pos          (5UL)          /*!< LM0MASK (Bit 5)                                       */
37829  #define R_SYSTEM_SYRSTMSK0_LM0MASK_Msk          (0x20UL)       /*!< LM0MASK (Bitfield-Mask: 0x01)                         */
37830  #define R_SYSTEM_SYRSTMSK0_CMMASK_Pos           (6UL)          /*!< CMMASK (Bit 6)                                        */
37831  #define R_SYSTEM_SYRSTMSK0_CMMASK_Msk           (0x40UL)       /*!< CMMASK (Bitfield-Mask: 0x01)                          */
37832  #define R_SYSTEM_SYRSTMSK0_BUSMASK_Pos          (7UL)          /*!< BUSMASK (Bit 7)                                       */
37833  #define R_SYSTEM_SYRSTMSK0_BUSMASK_Msk          (0x80UL)       /*!< BUSMASK (Bitfield-Mask: 0x01)                         */
37834 /* =======================================================  SYRSTMSK1  ======================================================= */
37835  #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Pos         (1UL)          /*!< WDT1MASK (Bit 1)                                      */
37836  #define R_SYSTEM_SYRSTMSK1_WDT1MASK_Msk         (0x2UL)        /*!< WDT1MASK (Bitfield-Mask: 0x01)                        */
37837  #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Pos        (4UL)          /*!< CLUP1MASK (Bit 4)                                     */
37838  #define R_SYSTEM_SYRSTMSK1_CLUP1MASK_Msk        (0x10UL)       /*!< CLUP1MASK (Bitfield-Mask: 0x01)                       */
37839  #define R_SYSTEM_SYRSTMSK1_LM1MASK_Pos          (5UL)          /*!< LM1MASK (Bit 5)                                       */
37840  #define R_SYSTEM_SYRSTMSK1_LM1MASK_Msk          (0x20UL)       /*!< LM1MASK (Bitfield-Mask: 0x01)                         */
37841  #define R_SYSTEM_SYRSTMSK1_NWMASK_Pos           (7UL)          /*!< NWMASK (Bit 7)                                        */
37842  #define R_SYSTEM_SYRSTMSK1_NWMASK_Msk           (0x80UL)       /*!< NWMASK (Bitfield-Mask: 0x01)                          */
37843 /* =======================================================  SYRSTMSK2  ======================================================= */
37844  #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Pos         (0UL)          /*!< LVD1MASK (Bit 0)                                      */
37845  #define R_SYSTEM_SYRSTMSK2_LVD1MASK_Msk         (0x1UL)        /*!< LVD1MASK (Bitfield-Mask: 0x01)                        */
37846  #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Pos         (1UL)          /*!< LVD2MASK (Bit 1)                                      */
37847  #define R_SYSTEM_SYRSTMSK2_LVD2MASK_Msk         (0x2UL)        /*!< LVD2MASK (Bitfield-Mask: 0x01)                        */
37848  #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Pos         (2UL)          /*!< LVD3MASK (Bit 2)                                      */
37849  #define R_SYSTEM_SYRSTMSK2_LVD3MASK_Msk         (0x4UL)        /*!< LVD3MASK (Bitfield-Mask: 0x01)                        */
37850  #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Pos         (3UL)          /*!< LVD4MASK (Bit 3)                                      */
37851  #define R_SYSTEM_SYRSTMSK2_LVD4MASK_Msk         (0x8UL)        /*!< LVD4MASK (Bitfield-Mask: 0x01)                        */
37852  #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Pos         (4UL)          /*!< LVD5MASK (Bit 4)                                      */
37853  #define R_SYSTEM_SYRSTMSK2_LVD5MASK_Msk         (0x10UL)       /*!< LVD5MASK (Bitfield-Mask: 0x01)                        */
37854 /* =======================================================  PLL1LDOCR  ======================================================= */
37855  #define R_SYSTEM_PLL1LDOCR_LDOSTP_Pos           (0UL)          /*!< LDOSTP (Bit 0)                                        */
37856  #define R_SYSTEM_PLL1LDOCR_LDOSTP_Msk           (0x1UL)        /*!< LDOSTP (Bitfield-Mask: 0x01)                          */
37857  #define R_SYSTEM_PLL1LDOCR_SKEEP_Pos            (1UL)          /*!< SKEEP (Bit 1)                                         */
37858  #define R_SYSTEM_PLL1LDOCR_SKEEP_Msk            (0x2UL)        /*!< SKEEP (Bitfield-Mask: 0x01)                           */
37859 /* =======================================================  PLL2LDOCR  ======================================================= */
37860  #define R_SYSTEM_PLL2LDOCR_LDOSTP_Pos           (0UL)          /*!< LDOSTP (Bit 0)                                        */
37861  #define R_SYSTEM_PLL2LDOCR_LDOSTP_Msk           (0x1UL)        /*!< LDOSTP (Bitfield-Mask: 0x01)                          */
37862  #define R_SYSTEM_PLL2LDOCR_SKEEP_Pos            (1UL)          /*!< SKEEP (Bit 1)                                         */
37863  #define R_SYSTEM_PLL2LDOCR_SKEEP_Msk            (0x2UL)        /*!< SKEEP (Bitfield-Mask: 0x01)                           */
37864 /* =======================================================  HOCOLDOCR  ======================================================= */
37865  #define R_SYSTEM_HOCOLDOCR_LDOSTP_Pos           (0UL)          /*!< LDOSTP (Bit 0)                                        */
37866  #define R_SYSTEM_HOCOLDOCR_LDOSTP_Msk           (0x1UL)        /*!< LDOSTP (Bitfield-Mask: 0x01)                          */
37867  #define R_SYSTEM_HOCOLDOCR_SKEEP_Pos            (1UL)          /*!< SKEEP (Bit 1)                                         */
37868  #define R_SYSTEM_HOCOLDOCR_SKEEP_Msk            (0x2UL)        /*!< SKEEP (Bitfield-Mask: 0x01)                           */
37869 /* ========================================================  LVD1FCR  ======================================================== */
37870  #define R_SYSTEM_LVD1FCR_RHSEL_Pos              (0UL)          /*!< RHSEL (Bit 0)                                         */
37871  #define R_SYSTEM_LVD1FCR_RHSEL_Msk              (0x1UL)        /*!< RHSEL (Bitfield-Mask: 0x01)                           */
37872 /* ========================================================  LVD2FCR  ======================================================== */
37873  #define R_SYSTEM_LVD2FCR_RHSEL_Pos              (0UL)          /*!< RHSEL (Bit 0)                                         */
37874  #define R_SYSTEM_LVD2FCR_RHSEL_Msk              (0x1UL)        /*!< RHSEL (Bitfield-Mask: 0x01)                           */
37875 /* ========================================================  SOSCCR  ========================================================= */
37876  #define R_SYSTEM_SOSCCR_SOSTP_Pos               (0UL)          /*!< SOSTP (Bit 0)                                         */
37877  #define R_SYSTEM_SOSCCR_SOSTP_Msk               (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
37878 /* =========================================================  SOMCR  ========================================================= */
37879  #define R_SYSTEM_SOMCR_SODRV_Pos                (0UL)          /*!< SODRV (Bit 0)                                         */
37880  #define R_SYSTEM_SOMCR_SODRV_Msk                (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
37881  #define R_SYSTEM_SOMCR_SOSEL_Pos                (6UL)          /*!< SOSEL (Bit 6)                                         */
37882  #define R_SYSTEM_SOMCR_SOSEL_Msk                (0x40UL)       /*!< SOSEL (Bitfield-Mask: 0x01)                           */
37883 /* ========================================================  VBTBER  ========================================================= */
37884  #define R_SYSTEM_VBTBER_VBAE_Pos                (3UL)          /*!< VBAE (Bit 3)                                          */
37885  #define R_SYSTEM_VBTBER_VBAE_Msk                (0x8UL)        /*!< VBAE (Bitfield-Mask: 0x01)                            */
37886 /* =======================================================  VBTBPCR2  ======================================================== */
37887  #define R_SYSTEM_VBTBPCR2_VDETLVL_Pos           (0UL)          /*!< VDETLVL (Bit 0)                                       */
37888  #define R_SYSTEM_VBTBPCR2_VDETLVL_Msk           (0x7UL)        /*!< VDETLVL (Bitfield-Mask: 0x07)                         */
37889  #define R_SYSTEM_VBTBPCR2_VDETE_Pos             (4UL)          /*!< VDETE (Bit 4)                                         */
37890  #define R_SYSTEM_VBTBPCR2_VDETE_Msk             (0x10UL)       /*!< VDETE (Bitfield-Mask: 0x01)                           */
37891 /* ========================================================  VBTBPSR  ======================================================== */
37892  #define R_SYSTEM_VBTBPSR_VBPORF_Pos             (0UL)          /*!< VBPORF (Bit 0)                                        */
37893  #define R_SYSTEM_VBTBPSR_VBPORF_Msk             (0x1UL)        /*!< VBPORF (Bitfield-Mask: 0x01)                          */
37894  #define R_SYSTEM_VBTBPSR_VBPORM_Pos             (4UL)          /*!< VBPORM (Bit 4)                                        */
37895  #define R_SYSTEM_VBTBPSR_VBPORM_Msk             (0x10UL)       /*!< VBPORM (Bitfield-Mask: 0x01)                          */
37896  #define R_SYSTEM_VBTBPSR_BPWSWM_Pos             (5UL)          /*!< BPWSWM (Bit 5)                                        */
37897  #define R_SYSTEM_VBTBPSR_BPWSWM_Msk             (0x20UL)       /*!< BPWSWM (Bitfield-Mask: 0x01)                          */
37898 /* ========================================================  VBTADSR  ======================================================== */
37899  #define R_SYSTEM_VBTADSR_VBTADF0_Pos            (0UL)          /*!< VBTADF0 (Bit 0)                                       */
37900  #define R_SYSTEM_VBTADSR_VBTADF0_Msk            (0x1UL)        /*!< VBTADF0 (Bitfield-Mask: 0x01)                         */
37901  #define R_SYSTEM_VBTADSR_VBTADF1_Pos            (1UL)          /*!< VBTADF1 (Bit 1)                                       */
37902  #define R_SYSTEM_VBTADSR_VBTADF1_Msk            (0x2UL)        /*!< VBTADF1 (Bitfield-Mask: 0x01)                         */
37903  #define R_SYSTEM_VBTADSR_VBTADF2_Pos            (2UL)          /*!< VBTADF2 (Bit 2)                                       */
37904  #define R_SYSTEM_VBTADSR_VBTADF2_Msk            (0x4UL)        /*!< VBTADF2 (Bitfield-Mask: 0x01)                         */
37905 /* =======================================================  VBTADCR1  ======================================================== */
37906  #define R_SYSTEM_VBTADCR1_VBTADIE0_Pos          (0UL)          /*!< VBTADIE0 (Bit 0)                                      */
37907  #define R_SYSTEM_VBTADCR1_VBTADIE0_Msk          (0x1UL)        /*!< VBTADIE0 (Bitfield-Mask: 0x01)                        */
37908  #define R_SYSTEM_VBTADCR1_VBTADIE1_Pos          (1UL)          /*!< VBTADIE1 (Bit 1)                                      */
37909  #define R_SYSTEM_VBTADCR1_VBTADIE1_Msk          (0x2UL)        /*!< VBTADIE1 (Bitfield-Mask: 0x01)                        */
37910  #define R_SYSTEM_VBTADCR1_VBTADIE2_Pos          (2UL)          /*!< VBTADIE2 (Bit 2)                                      */
37911  #define R_SYSTEM_VBTADCR1_VBTADIE2_Msk          (0x4UL)        /*!< VBTADIE2 (Bitfield-Mask: 0x01)                        */
37912  #define R_SYSTEM_VBTADCR1_VBTADCLE0_Pos         (4UL)          /*!< VBTADCLE0 (Bit 4)                                     */
37913  #define R_SYSTEM_VBTADCR1_VBTADCLE0_Msk         (0x10UL)       /*!< VBTADCLE0 (Bitfield-Mask: 0x01)                       */
37914  #define R_SYSTEM_VBTADCR1_VBTADCLE1_Pos         (5UL)          /*!< VBTADCLE1 (Bit 5)                                     */
37915  #define R_SYSTEM_VBTADCR1_VBTADCLE1_Msk         (0x20UL)       /*!< VBTADCLE1 (Bitfield-Mask: 0x01)                       */
37916  #define R_SYSTEM_VBTADCR1_VBTADCLE2_Pos         (6UL)          /*!< VBTADCLE2 (Bit 6)                                     */
37917  #define R_SYSTEM_VBTADCR1_VBTADCLE2_Msk         (0x40UL)       /*!< VBTADCLE2 (Bitfield-Mask: 0x01)                       */
37918 /* =======================================================  VBTADCR2  ======================================================== */
37919  #define R_SYSTEM_VBTADCR2_VBRTCES0_Pos          (0UL)          /*!< VBRTCES0 (Bit 0)                                      */
37920  #define R_SYSTEM_VBTADCR2_VBRTCES0_Msk          (0x1UL)        /*!< VBRTCES0 (Bitfield-Mask: 0x01)                        */
37921  #define R_SYSTEM_VBTADCR2_VBRTCES1_Pos          (1UL)          /*!< VBRTCES1 (Bit 1)                                      */
37922  #define R_SYSTEM_VBTADCR2_VBRTCES1_Msk          (0x2UL)        /*!< VBRTCES1 (Bitfield-Mask: 0x01)                        */
37923  #define R_SYSTEM_VBTADCR2_VBRTCES2_Pos          (2UL)          /*!< VBRTCES2 (Bit 2)                                      */
37924  #define R_SYSTEM_VBTADCR2_VBRTCES2_Msk          (0x4UL)        /*!< VBRTCES2 (Bitfield-Mask: 0x01)                        */
37925 /* =======================================================  VBTICTLR  ======================================================== */
37926  #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos          (0UL)          /*!< VCH0INEN (Bit 0)                                      */
37927  #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk          (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
37928  #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos          (1UL)          /*!< VCH1INEN (Bit 1)                                      */
37929  #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk          (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
37930  #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos          (2UL)          /*!< VCH2INEN (Bit 2)                                      */
37931  #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk          (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
37932 /* =======================================================  VBTICTLR2  ======================================================= */
37933  #define R_SYSTEM_VBTICTLR2_VCH0NCE_Pos          (0UL)          /*!< VCH0NCE (Bit 0)                                       */
37934  #define R_SYSTEM_VBTICTLR2_VCH0NCE_Msk          (0x1UL)        /*!< VCH0NCE (Bitfield-Mask: 0x01)                         */
37935  #define R_SYSTEM_VBTICTLR2_VCH1NCE_Pos          (1UL)          /*!< VCH1NCE (Bit 1)                                       */
37936  #define R_SYSTEM_VBTICTLR2_VCH1NCE_Msk          (0x2UL)        /*!< VCH1NCE (Bitfield-Mask: 0x01)                         */
37937  #define R_SYSTEM_VBTICTLR2_VCH2NCE_Pos          (2UL)          /*!< VCH2NCE (Bit 2)                                       */
37938  #define R_SYSTEM_VBTICTLR2_VCH2NCE_Msk          (0x4UL)        /*!< VCH2NCE (Bitfield-Mask: 0x01)                         */
37939  #define R_SYSTEM_VBTICTLR2_VCH0EG_Pos           (4UL)          /*!< VCH0EG (Bit 4)                                        */
37940  #define R_SYSTEM_VBTICTLR2_VCH0EG_Msk           (0x10UL)       /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
37941  #define R_SYSTEM_VBTICTLR2_VCH1EG_Pos           (5UL)          /*!< VCH1EG (Bit 5)                                        */
37942  #define R_SYSTEM_VBTICTLR2_VCH1EG_Msk           (0x20UL)       /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
37943  #define R_SYSTEM_VBTICTLR2_VCH2EG_Pos           (6UL)          /*!< VCH2EG (Bit 6)                                        */
37944  #define R_SYSTEM_VBTICTLR2_VCH2EG_Msk           (0x40UL)       /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
37945 /* =======================================================  VBTIMONR  ======================================================== */
37946  #define R_SYSTEM_VBTIMONR_VCH0MON_Pos           (0UL)          /*!< VCH0MON (Bit 0)                                       */
37947  #define R_SYSTEM_VBTIMONR_VCH0MON_Msk           (0x1UL)        /*!< VCH0MON (Bitfield-Mask: 0x01)                         */
37948  #define R_SYSTEM_VBTIMONR_VCH1MON_Pos           (1UL)          /*!< VCH1MON (Bit 1)                                       */
37949  #define R_SYSTEM_VBTIMONR_VCH1MON_Msk           (0x2UL)        /*!< VCH1MON (Bitfield-Mask: 0x01)                         */
37950  #define R_SYSTEM_VBTIMONR_VCH2MON_Pos           (2UL)          /*!< VCH2MON (Bit 2)                                       */
37951  #define R_SYSTEM_VBTIMONR_VCH2MON_Msk           (0x4UL)        /*!< VCH2MON (Bitfield-Mask: 0x01)                         */
37952 /* ========================================================  VBTBKR0  ======================================================== */
37953  #define R_SYSTEM_VBTBKR0_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37954  #define R_SYSTEM_VBTBKR0_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37955 /* ========================================================  VBTBKR1  ======================================================== */
37956  #define R_SYSTEM_VBTBKR1_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37957  #define R_SYSTEM_VBTBKR1_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37958 /* ========================================================  VBTBKR2  ======================================================== */
37959  #define R_SYSTEM_VBTBKR2_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37960  #define R_SYSTEM_VBTBKR2_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37961 /* ========================================================  VBTBKR3  ======================================================== */
37962  #define R_SYSTEM_VBTBKR3_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37963  #define R_SYSTEM_VBTBKR3_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37964 /* ========================================================  VBTBKR4  ======================================================== */
37965  #define R_SYSTEM_VBTBKR4_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37966  #define R_SYSTEM_VBTBKR4_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37967 /* ========================================================  VBTBKR5  ======================================================== */
37968  #define R_SYSTEM_VBTBKR5_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37969  #define R_SYSTEM_VBTBKR5_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37970 /* ========================================================  VBTBKR6  ======================================================== */
37971  #define R_SYSTEM_VBTBKR6_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37972  #define R_SYSTEM_VBTBKR6_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37973 /* ========================================================  VBTBKR7  ======================================================== */
37974  #define R_SYSTEM_VBTBKR7_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37975  #define R_SYSTEM_VBTBKR7_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37976 /* ========================================================  VBTBKR8  ======================================================== */
37977  #define R_SYSTEM_VBTBKR8_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37978  #define R_SYSTEM_VBTBKR8_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37979 /* ========================================================  VBTBKR9  ======================================================== */
37980  #define R_SYSTEM_VBTBKR9_VBTBKR_Pos             (0UL)          /*!< VBTBKR (Bit 0)                                        */
37981  #define R_SYSTEM_VBTBKR9_VBTBKR_Msk             (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37982 /* =======================================================  VBTBKR10  ======================================================== */
37983  #define R_SYSTEM_VBTBKR10_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
37984  #define R_SYSTEM_VBTBKR10_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37985 /* =======================================================  VBTBKR11  ======================================================== */
37986  #define R_SYSTEM_VBTBKR11_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
37987  #define R_SYSTEM_VBTBKR11_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37988 /* =======================================================  VBTBKR12  ======================================================== */
37989  #define R_SYSTEM_VBTBKR12_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
37990  #define R_SYSTEM_VBTBKR12_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37991 /* =======================================================  VBTBKR13  ======================================================== */
37992  #define R_SYSTEM_VBTBKR13_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
37993  #define R_SYSTEM_VBTBKR13_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37994 /* =======================================================  VBTBKR14  ======================================================== */
37995  #define R_SYSTEM_VBTBKR14_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
37996  #define R_SYSTEM_VBTBKR14_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
37997 /* =======================================================  VBTBKR15  ======================================================== */
37998  #define R_SYSTEM_VBTBKR15_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
37999  #define R_SYSTEM_VBTBKR15_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38000 /* =======================================================  VBTBKR16  ======================================================== */
38001  #define R_SYSTEM_VBTBKR16_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38002  #define R_SYSTEM_VBTBKR16_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38003 /* =======================================================  VBTBKR17  ======================================================== */
38004  #define R_SYSTEM_VBTBKR17_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38005  #define R_SYSTEM_VBTBKR17_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38006 /* =======================================================  VBTBKR18  ======================================================== */
38007  #define R_SYSTEM_VBTBKR18_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38008  #define R_SYSTEM_VBTBKR18_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38009 /* =======================================================  VBTBKR19  ======================================================== */
38010  #define R_SYSTEM_VBTBKR19_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38011  #define R_SYSTEM_VBTBKR19_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38012 /* =======================================================  VBTBKR20  ======================================================== */
38013  #define R_SYSTEM_VBTBKR20_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38014  #define R_SYSTEM_VBTBKR20_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38015 /* =======================================================  VBTBKR21  ======================================================== */
38016  #define R_SYSTEM_VBTBKR21_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38017  #define R_SYSTEM_VBTBKR21_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38018 /* =======================================================  VBTBKR22  ======================================================== */
38019  #define R_SYSTEM_VBTBKR22_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38020  #define R_SYSTEM_VBTBKR22_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38021 /* =======================================================  VBTBKR23  ======================================================== */
38022  #define R_SYSTEM_VBTBKR23_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38023  #define R_SYSTEM_VBTBKR23_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38024 /* =======================================================  VBTBKR24  ======================================================== */
38025  #define R_SYSTEM_VBTBKR24_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38026  #define R_SYSTEM_VBTBKR24_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38027 /* =======================================================  VBTBKR25  ======================================================== */
38028  #define R_SYSTEM_VBTBKR25_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38029  #define R_SYSTEM_VBTBKR25_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38030 /* =======================================================  VBTBKR26  ======================================================== */
38031  #define R_SYSTEM_VBTBKR26_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38032  #define R_SYSTEM_VBTBKR26_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38033 /* =======================================================  VBTBKR27  ======================================================== */
38034  #define R_SYSTEM_VBTBKR27_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38035  #define R_SYSTEM_VBTBKR27_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38036 /* =======================================================  VBTBKR28  ======================================================== */
38037  #define R_SYSTEM_VBTBKR28_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38038  #define R_SYSTEM_VBTBKR28_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38039 /* =======================================================  VBTBKR29  ======================================================== */
38040  #define R_SYSTEM_VBTBKR29_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38041  #define R_SYSTEM_VBTBKR29_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38042 /* =======================================================  VBTBKR30  ======================================================== */
38043  #define R_SYSTEM_VBTBKR30_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38044  #define R_SYSTEM_VBTBKR30_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38045 /* =======================================================  VBTBKR31  ======================================================== */
38046  #define R_SYSTEM_VBTBKR31_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38047  #define R_SYSTEM_VBTBKR31_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38048 /* =======================================================  VBTBKR32  ======================================================== */
38049  #define R_SYSTEM_VBTBKR32_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38050  #define R_SYSTEM_VBTBKR32_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38051 /* =======================================================  VBTBKR33  ======================================================== */
38052  #define R_SYSTEM_VBTBKR33_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38053  #define R_SYSTEM_VBTBKR33_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38054 /* =======================================================  VBTBKR34  ======================================================== */
38055  #define R_SYSTEM_VBTBKR34_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38056  #define R_SYSTEM_VBTBKR34_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38057 /* =======================================================  VBTBKR35  ======================================================== */
38058  #define R_SYSTEM_VBTBKR35_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38059  #define R_SYSTEM_VBTBKR35_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38060 /* =======================================================  VBTBKR36  ======================================================== */
38061  #define R_SYSTEM_VBTBKR36_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38062  #define R_SYSTEM_VBTBKR36_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38063 /* =======================================================  VBTBKR37  ======================================================== */
38064  #define R_SYSTEM_VBTBKR37_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38065  #define R_SYSTEM_VBTBKR37_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38066 /* =======================================================  VBTBKR38  ======================================================== */
38067  #define R_SYSTEM_VBTBKR38_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38068  #define R_SYSTEM_VBTBKR38_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38069 /* =======================================================  VBTBKR39  ======================================================== */
38070  #define R_SYSTEM_VBTBKR39_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38071  #define R_SYSTEM_VBTBKR39_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38072 /* =======================================================  VBTBKR40  ======================================================== */
38073  #define R_SYSTEM_VBTBKR40_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38074  #define R_SYSTEM_VBTBKR40_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38075 /* =======================================================  VBTBKR41  ======================================================== */
38076  #define R_SYSTEM_VBTBKR41_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38077  #define R_SYSTEM_VBTBKR41_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38078 /* =======================================================  VBTBKR42  ======================================================== */
38079  #define R_SYSTEM_VBTBKR42_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38080  #define R_SYSTEM_VBTBKR42_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38081 /* =======================================================  VBTBKR43  ======================================================== */
38082  #define R_SYSTEM_VBTBKR43_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38083  #define R_SYSTEM_VBTBKR43_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38084 /* =======================================================  VBTBKR44  ======================================================== */
38085  #define R_SYSTEM_VBTBKR44_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38086  #define R_SYSTEM_VBTBKR44_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38087 /* =======================================================  VBTBKR45  ======================================================== */
38088  #define R_SYSTEM_VBTBKR45_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38089  #define R_SYSTEM_VBTBKR45_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38090 /* =======================================================  VBTBKR46  ======================================================== */
38091  #define R_SYSTEM_VBTBKR46_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38092  #define R_SYSTEM_VBTBKR46_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38093 /* =======================================================  VBTBKR47  ======================================================== */
38094  #define R_SYSTEM_VBTBKR47_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38095  #define R_SYSTEM_VBTBKR47_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38096 /* =======================================================  VBTBKR48  ======================================================== */
38097  #define R_SYSTEM_VBTBKR48_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38098  #define R_SYSTEM_VBTBKR48_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38099 /* =======================================================  VBTBKR49  ======================================================== */
38100  #define R_SYSTEM_VBTBKR49_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38101  #define R_SYSTEM_VBTBKR49_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38102 /* =======================================================  VBTBKR50  ======================================================== */
38103  #define R_SYSTEM_VBTBKR50_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38104  #define R_SYSTEM_VBTBKR50_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38105 /* =======================================================  VBTBKR51  ======================================================== */
38106  #define R_SYSTEM_VBTBKR51_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38107  #define R_SYSTEM_VBTBKR51_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38108 /* =======================================================  VBTBKR52  ======================================================== */
38109  #define R_SYSTEM_VBTBKR52_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38110  #define R_SYSTEM_VBTBKR52_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38111 /* =======================================================  VBTBKR53  ======================================================== */
38112  #define R_SYSTEM_VBTBKR53_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38113  #define R_SYSTEM_VBTBKR53_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38114 /* =======================================================  VBTBKR54  ======================================================== */
38115  #define R_SYSTEM_VBTBKR54_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38116  #define R_SYSTEM_VBTBKR54_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38117 /* =======================================================  VBTBKR55  ======================================================== */
38118  #define R_SYSTEM_VBTBKR55_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38119  #define R_SYSTEM_VBTBKR55_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38120 /* =======================================================  VBTBKR56  ======================================================== */
38121  #define R_SYSTEM_VBTBKR56_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38122  #define R_SYSTEM_VBTBKR56_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38123 /* =======================================================  VBTBKR57  ======================================================== */
38124  #define R_SYSTEM_VBTBKR57_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38125  #define R_SYSTEM_VBTBKR57_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38126 /* =======================================================  VBTBKR58  ======================================================== */
38127  #define R_SYSTEM_VBTBKR58_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38128  #define R_SYSTEM_VBTBKR58_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38129 /* =======================================================  VBTBKR59  ======================================================== */
38130  #define R_SYSTEM_VBTBKR59_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38131  #define R_SYSTEM_VBTBKR59_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38132 /* =======================================================  VBTBKR60  ======================================================== */
38133  #define R_SYSTEM_VBTBKR60_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38134  #define R_SYSTEM_VBTBKR60_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38135 /* =======================================================  VBTBKR61  ======================================================== */
38136  #define R_SYSTEM_VBTBKR61_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38137  #define R_SYSTEM_VBTBKR61_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38138 /* =======================================================  VBTBKR62  ======================================================== */
38139  #define R_SYSTEM_VBTBKR62_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38140  #define R_SYSTEM_VBTBKR62_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38141 /* =======================================================  VBTBKR63  ======================================================== */
38142  #define R_SYSTEM_VBTBKR63_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38143  #define R_SYSTEM_VBTBKR63_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38144 /* =======================================================  VBTBKR64  ======================================================== */
38145  #define R_SYSTEM_VBTBKR64_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38146  #define R_SYSTEM_VBTBKR64_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38147 /* =======================================================  VBTBKR65  ======================================================== */
38148  #define R_SYSTEM_VBTBKR65_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38149  #define R_SYSTEM_VBTBKR65_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38150 /* =======================================================  VBTBKR66  ======================================================== */
38151  #define R_SYSTEM_VBTBKR66_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38152  #define R_SYSTEM_VBTBKR66_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38153 /* =======================================================  VBTBKR67  ======================================================== */
38154  #define R_SYSTEM_VBTBKR67_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38155  #define R_SYSTEM_VBTBKR67_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38156 /* =======================================================  VBTBKR68  ======================================================== */
38157  #define R_SYSTEM_VBTBKR68_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38158  #define R_SYSTEM_VBTBKR68_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38159 /* =======================================================  VBTBKR69  ======================================================== */
38160  #define R_SYSTEM_VBTBKR69_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38161  #define R_SYSTEM_VBTBKR69_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38162 /* =======================================================  VBTBKR70  ======================================================== */
38163  #define R_SYSTEM_VBTBKR70_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38164  #define R_SYSTEM_VBTBKR70_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38165 /* =======================================================  VBTBKR71  ======================================================== */
38166  #define R_SYSTEM_VBTBKR71_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38167  #define R_SYSTEM_VBTBKR71_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38168 /* =======================================================  VBTBKR72  ======================================================== */
38169  #define R_SYSTEM_VBTBKR72_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38170  #define R_SYSTEM_VBTBKR72_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38171 /* =======================================================  VBTBKR73  ======================================================== */
38172  #define R_SYSTEM_VBTBKR73_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38173  #define R_SYSTEM_VBTBKR73_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38174 /* =======================================================  VBTBKR74  ======================================================== */
38175  #define R_SYSTEM_VBTBKR74_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38176  #define R_SYSTEM_VBTBKR74_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38177 /* =======================================================  VBTBKR75  ======================================================== */
38178  #define R_SYSTEM_VBTBKR75_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38179  #define R_SYSTEM_VBTBKR75_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38180 /* =======================================================  VBTBKR76  ======================================================== */
38181  #define R_SYSTEM_VBTBKR76_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38182  #define R_SYSTEM_VBTBKR76_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38183 /* =======================================================  VBTBKR77  ======================================================== */
38184  #define R_SYSTEM_VBTBKR77_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38185  #define R_SYSTEM_VBTBKR77_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38186 /* =======================================================  VBTBKR78  ======================================================== */
38187  #define R_SYSTEM_VBTBKR78_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38188  #define R_SYSTEM_VBTBKR78_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38189 /* =======================================================  VBTBKR79  ======================================================== */
38190  #define R_SYSTEM_VBTBKR79_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38191  #define R_SYSTEM_VBTBKR79_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38192 /* =======================================================  VBTBKR80  ======================================================== */
38193  #define R_SYSTEM_VBTBKR80_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38194  #define R_SYSTEM_VBTBKR80_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38195 /* =======================================================  VBTBKR81  ======================================================== */
38196  #define R_SYSTEM_VBTBKR81_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38197  #define R_SYSTEM_VBTBKR81_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38198 /* =======================================================  VBTBKR82  ======================================================== */
38199  #define R_SYSTEM_VBTBKR82_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38200  #define R_SYSTEM_VBTBKR82_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38201 /* =======================================================  VBTBKR83  ======================================================== */
38202  #define R_SYSTEM_VBTBKR83_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38203  #define R_SYSTEM_VBTBKR83_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38204 /* =======================================================  VBTBKR84  ======================================================== */
38205  #define R_SYSTEM_VBTBKR84_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38206  #define R_SYSTEM_VBTBKR84_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38207 /* =======================================================  VBTBKR85  ======================================================== */
38208  #define R_SYSTEM_VBTBKR85_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38209  #define R_SYSTEM_VBTBKR85_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38210 /* =======================================================  VBTBKR86  ======================================================== */
38211  #define R_SYSTEM_VBTBKR86_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38212  #define R_SYSTEM_VBTBKR86_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38213 /* =======================================================  VBTBKR87  ======================================================== */
38214  #define R_SYSTEM_VBTBKR87_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38215  #define R_SYSTEM_VBTBKR87_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38216 /* =======================================================  VBTBKR88  ======================================================== */
38217  #define R_SYSTEM_VBTBKR88_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38218  #define R_SYSTEM_VBTBKR88_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38219 /* =======================================================  VBTBKR89  ======================================================== */
38220  #define R_SYSTEM_VBTBKR89_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38221  #define R_SYSTEM_VBTBKR89_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38222 /* =======================================================  VBTBKR90  ======================================================== */
38223  #define R_SYSTEM_VBTBKR90_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38224  #define R_SYSTEM_VBTBKR90_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38225 /* =======================================================  VBTBKR91  ======================================================== */
38226  #define R_SYSTEM_VBTBKR91_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38227  #define R_SYSTEM_VBTBKR91_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38228 /* =======================================================  VBTBKR92  ======================================================== */
38229  #define R_SYSTEM_VBTBKR92_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38230  #define R_SYSTEM_VBTBKR92_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38231 /* =======================================================  VBTBKR93  ======================================================== */
38232  #define R_SYSTEM_VBTBKR93_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38233  #define R_SYSTEM_VBTBKR93_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38234 /* =======================================================  VBTBKR94  ======================================================== */
38235  #define R_SYSTEM_VBTBKR94_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38236  #define R_SYSTEM_VBTBKR94_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38237 /* =======================================================  VBTBKR95  ======================================================== */
38238  #define R_SYSTEM_VBTBKR95_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38239  #define R_SYSTEM_VBTBKR95_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38240 /* =======================================================  VBTBKR96  ======================================================== */
38241  #define R_SYSTEM_VBTBKR96_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38242  #define R_SYSTEM_VBTBKR96_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38243 /* =======================================================  VBTBKR97  ======================================================== */
38244  #define R_SYSTEM_VBTBKR97_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38245  #define R_SYSTEM_VBTBKR97_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38246 /* =======================================================  VBTBKR98  ======================================================== */
38247  #define R_SYSTEM_VBTBKR98_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38248  #define R_SYSTEM_VBTBKR98_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38249 /* =======================================================  VBTBKR99  ======================================================== */
38250  #define R_SYSTEM_VBTBKR99_VBTBKR_Pos            (0UL)          /*!< VBTBKR (Bit 0)                                        */
38251  #define R_SYSTEM_VBTBKR99_VBTBKR_Msk            (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38252 /* =======================================================  VBTBKR100  ======================================================= */
38253  #define R_SYSTEM_VBTBKR100_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38254  #define R_SYSTEM_VBTBKR100_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38255 /* =======================================================  VBTBKR101  ======================================================= */
38256  #define R_SYSTEM_VBTBKR101_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38257  #define R_SYSTEM_VBTBKR101_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38258 /* =======================================================  VBTBKR102  ======================================================= */
38259  #define R_SYSTEM_VBTBKR102_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38260  #define R_SYSTEM_VBTBKR102_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38261 /* =======================================================  VBTBKR103  ======================================================= */
38262  #define R_SYSTEM_VBTBKR103_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38263  #define R_SYSTEM_VBTBKR103_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38264 /* =======================================================  VBTBKR104  ======================================================= */
38265  #define R_SYSTEM_VBTBKR104_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38266  #define R_SYSTEM_VBTBKR104_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38267 /* =======================================================  VBTBKR105  ======================================================= */
38268  #define R_SYSTEM_VBTBKR105_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38269  #define R_SYSTEM_VBTBKR105_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38270 /* =======================================================  VBTBKR106  ======================================================= */
38271  #define R_SYSTEM_VBTBKR106_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38272  #define R_SYSTEM_VBTBKR106_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38273 /* =======================================================  VBTBKR107  ======================================================= */
38274  #define R_SYSTEM_VBTBKR107_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38275  #define R_SYSTEM_VBTBKR107_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38276 /* =======================================================  VBTBKR108  ======================================================= */
38277  #define R_SYSTEM_VBTBKR108_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38278  #define R_SYSTEM_VBTBKR108_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38279 /* =======================================================  VBTBKR109  ======================================================= */
38280  #define R_SYSTEM_VBTBKR109_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38281  #define R_SYSTEM_VBTBKR109_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38282 /* =======================================================  VBTBKR110  ======================================================= */
38283  #define R_SYSTEM_VBTBKR110_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38284  #define R_SYSTEM_VBTBKR110_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38285 /* =======================================================  VBTBKR111  ======================================================= */
38286  #define R_SYSTEM_VBTBKR111_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38287  #define R_SYSTEM_VBTBKR111_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38288 /* =======================================================  VBTBKR112  ======================================================= */
38289  #define R_SYSTEM_VBTBKR112_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38290  #define R_SYSTEM_VBTBKR112_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38291 /* =======================================================  VBTBKR113  ======================================================= */
38292  #define R_SYSTEM_VBTBKR113_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38293  #define R_SYSTEM_VBTBKR113_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38294 /* =======================================================  VBTBKR114  ======================================================= */
38295  #define R_SYSTEM_VBTBKR114_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38296  #define R_SYSTEM_VBTBKR114_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38297 /* =======================================================  VBTBKR115  ======================================================= */
38298  #define R_SYSTEM_VBTBKR115_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38299  #define R_SYSTEM_VBTBKR115_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38300 /* =======================================================  VBTBKR116  ======================================================= */
38301  #define R_SYSTEM_VBTBKR116_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38302  #define R_SYSTEM_VBTBKR116_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38303 /* =======================================================  VBTBKR117  ======================================================= */
38304  #define R_SYSTEM_VBTBKR117_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38305  #define R_SYSTEM_VBTBKR117_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38306 /* =======================================================  VBTBKR118  ======================================================= */
38307  #define R_SYSTEM_VBTBKR118_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38308  #define R_SYSTEM_VBTBKR118_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38309 /* =======================================================  VBTBKR119  ======================================================= */
38310  #define R_SYSTEM_VBTBKR119_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38311  #define R_SYSTEM_VBTBKR119_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38312 /* =======================================================  VBTBKR120  ======================================================= */
38313  #define R_SYSTEM_VBTBKR120_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38314  #define R_SYSTEM_VBTBKR120_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38315 /* =======================================================  VBTBKR121  ======================================================= */
38316  #define R_SYSTEM_VBTBKR121_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38317  #define R_SYSTEM_VBTBKR121_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38318 /* =======================================================  VBTBKR122  ======================================================= */
38319  #define R_SYSTEM_VBTBKR122_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38320  #define R_SYSTEM_VBTBKR122_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38321 /* =======================================================  VBTBKR123  ======================================================= */
38322  #define R_SYSTEM_VBTBKR123_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38323  #define R_SYSTEM_VBTBKR123_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38324 /* =======================================================  VBTBKR124  ======================================================= */
38325  #define R_SYSTEM_VBTBKR124_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38326  #define R_SYSTEM_VBTBKR124_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38327 /* =======================================================  VBTBKR125  ======================================================= */
38328  #define R_SYSTEM_VBTBKR125_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38329  #define R_SYSTEM_VBTBKR125_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38330 /* =======================================================  VBTBKR126  ======================================================= */
38331  #define R_SYSTEM_VBTBKR126_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38332  #define R_SYSTEM_VBTBKR126_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38333 /* =======================================================  VBTBKR127  ======================================================= */
38334  #define R_SYSTEM_VBTBKR127_VBTBKR_Pos           (0UL)          /*!< VBTBKR (Bit 0)                                        */
38335  #define R_SYSTEM_VBTBKR127_VBTBKR_Msk           (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
38336 
38337 /* =========================================================================================================================== */
38338 /* ================                                         R_TSN_CAL                                         ================ */
38339 /* =========================================================================================================================== */
38340 
38341 /* =========================================================  TSCDR  ========================================================= */
38342  #define R_TSN_CAL_TSCDR_TSCDR_Pos    (0UL)          /*!< TSCDR (Bit 0)                                         */
38343  #define R_TSN_CAL_TSCDR_TSCDR_Msk    (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff)                     */
38344 
38345 /* =========================================================================================================================== */
38346 /* ================                                        R_TSN_CTRL                                         ================ */
38347 /* =========================================================================================================================== */
38348 
38349 /* =========================================================  TSCR  ========================================================== */
38350  #define R_TSN_CTRL_TSCR_TSEN_Pos    (7UL)    /*!< TSEN (Bit 7)                                          */
38351  #define R_TSN_CTRL_TSCR_TSEN_Msk    (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01)                            */
38352  #define R_TSN_CTRL_TSCR_TSOE_Pos    (4UL)    /*!< TSOE (Bit 4)                                          */
38353  #define R_TSN_CTRL_TSCR_TSOE_Msk    (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01)                            */
38354 
38355 /* =========================================================================================================================== */
38356 /* ================                                         R_USB_FS0                                         ================ */
38357 /* =========================================================================================================================== */
38358 
38359 /* ========================================================  SYSCFG  ========================================================= */
38360  #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
38361  #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
38362  #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
38363  #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
38364  #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
38365  #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
38366  #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
38367  #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
38368  #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
38369  #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
38370  #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
38371  #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
38372  #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
38373  #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
38374 /* ========================================================  BUSWAIT  ======================================================== */
38375  #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
38376  #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
38377 /* ========================================================  SYSSTS0  ======================================================== */
38378  #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
38379  #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
38380  #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
38381  #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
38382  #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
38383  #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
38384  #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
38385  #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
38386  #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
38387  #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
38388 /* ========================================================  PLLSTA  ========================================================= */
38389  #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
38390  #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
38391 /* =======================================================  DVSTCTR0  ======================================================== */
38392  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
38393  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
38394  #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
38395  #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
38396  #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
38397  #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
38398  #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
38399  #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
38400  #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
38401  #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
38402  #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
38403  #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
38404  #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
38405  #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
38406  #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
38407  #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
38408  #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
38409  #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
38410 /* =======================================================  TESTMODE  ======================================================== */
38411  #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
38412  #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
38413 /* ========================================================  CFIFOL  ========================================================= */
38414 /* ========================================================  CFIFOLL  ======================================================== */
38415 /* =========================================================  CFIFO  ========================================================= */
38416 /* ========================================================  CFIFOH  ========================================================= */
38417 /* ========================================================  CFIFOHH  ======================================================== */
38418 /* ========================================================  D0FIFOL  ======================================================== */
38419 /* =======================================================  D0FIFOLL  ======================================================== */
38420 /* ========================================================  D0FIFO  ========================================================= */
38421 /* ========================================================  D0FIFOH  ======================================================== */
38422 /* =======================================================  D0FIFOHH  ======================================================== */
38423 /* ========================================================  D1FIFOL  ======================================================== */
38424 /* =======================================================  D1FIFOLL  ======================================================== */
38425 /* ========================================================  D1FIFO  ========================================================= */
38426 /* ========================================================  D1FIFOH  ======================================================== */
38427 /* =======================================================  D1FIFOHH  ======================================================== */
38428 /* =======================================================  CFIFOSEL  ======================================================== */
38429  #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
38430  #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
38431  #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
38432  #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
38433  #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
38434  #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
38435  #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
38436  #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
38437  #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
38438  #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
38439  #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
38440  #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
38441 /* =======================================================  CFIFOCTR  ======================================================== */
38442  #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
38443  #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
38444  #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
38445  #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
38446  #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
38447  #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
38448  #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
38449  #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
38450 /* =======================================================  D0FIFOSEL  ======================================================= */
38451  #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
38452  #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
38453  #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
38454  #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
38455  #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
38456  #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
38457  #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
38458  #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
38459  #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
38460  #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
38461  #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
38462  #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
38463  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
38464  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
38465 /* =======================================================  D0FIFOCTR  ======================================================= */
38466  #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
38467  #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
38468  #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
38469  #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
38470  #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
38471  #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
38472  #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
38473  #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
38474 /* =======================================================  D1FIFOSEL  ======================================================= */
38475  #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
38476  #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
38477  #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
38478  #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
38479  #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
38480  #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
38481  #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
38482  #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
38483  #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
38484  #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
38485  #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
38486  #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
38487  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
38488  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
38489 /* =======================================================  D1FIFOCTR  ======================================================= */
38490  #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
38491  #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
38492  #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
38493  #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
38494  #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
38495  #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
38496  #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
38497  #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
38498 /* ========================================================  INTENB0  ======================================================== */
38499  #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
38500  #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
38501  #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
38502  #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
38503  #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
38504  #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
38505  #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
38506  #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
38507  #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
38508  #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
38509  #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
38510  #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
38511  #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
38512  #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
38513  #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
38514  #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
38515 /* ========================================================  INTENB1  ======================================================== */
38516  #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
38517  #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
38518  #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
38519  #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
38520  #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
38521  #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
38522  #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
38523  #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
38524  #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
38525  #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
38526  #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
38527  #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
38528  #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
38529  #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
38530  #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
38531  #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
38532 /* ========================================================  BRDYENB  ======================================================== */
38533  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
38534  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
38535 /* ========================================================  NRDYENB  ======================================================== */
38536  #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
38537  #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
38538 /* ========================================================  BEMPENB  ======================================================== */
38539  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
38540  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
38541 /* ========================================================  SOFCFG  ========================================================= */
38542  #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
38543  #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
38544  #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
38545  #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
38546  #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
38547  #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
38548  #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
38549  #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
38550 /* ========================================================  PHYSET  ========================================================= */
38551  #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
38552  #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
38553  #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
38554  #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
38555  #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
38556  #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
38557  #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
38558  #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
38559  #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
38560  #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
38561  #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
38562  #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
38563  #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
38564  #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
38565 /* ========================================================  INTSTS0  ======================================================== */
38566  #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
38567  #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
38568  #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
38569  #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
38570  #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
38571  #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
38572  #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
38573  #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
38574  #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
38575  #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
38576  #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
38577  #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
38578  #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
38579  #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
38580  #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
38581  #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
38582  #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
38583  #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
38584  #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
38585  #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
38586  #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
38587  #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
38588  #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
38589  #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
38590 /* ========================================================  INTSTS1  ======================================================== */
38591  #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
38592  #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
38593  #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
38594  #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
38595  #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
38596  #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
38597  #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
38598  #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
38599  #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
38600  #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
38601  #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
38602  #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
38603  #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
38604  #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
38605  #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
38606  #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
38607  #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
38608  #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
38609  #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
38610  #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
38611 /* ========================================================  BRDYSTS  ======================================================== */
38612  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
38613  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
38614 /* ========================================================  NRDYSTS  ======================================================== */
38615  #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
38616  #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
38617 /* ========================================================  BEMPSTS  ======================================================== */
38618  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
38619  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
38620 /* ========================================================  FRMNUM  ========================================================= */
38621  #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
38622  #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
38623  #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
38624  #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
38625  #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
38626  #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
38627 /* ========================================================  UFRMNUM  ======================================================== */
38628  #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
38629  #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
38630  #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
38631  #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
38632 /* ========================================================  USBADDR  ======================================================== */
38633  #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
38634  #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
38635  #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
38636  #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
38637 /* ========================================================  USBREQ  ========================================================= */
38638  #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
38639  #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
38640  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
38641  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
38642 /* ========================================================  USBVAL  ========================================================= */
38643  #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
38644  #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
38645 /* ========================================================  USBINDX  ======================================================== */
38646  #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
38647  #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
38648 /* ========================================================  USBLENG  ======================================================== */
38649  #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
38650  #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
38651 /* ========================================================  DCPCFG  ========================================================= */
38652  #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
38653  #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
38654  #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
38655  #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
38656  #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
38657  #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
38658 /* ========================================================  DCPMAXP  ======================================================== */
38659  #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
38660  #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
38661  #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
38662  #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
38663 /* ========================================================  DCPCTR  ========================================================= */
38664  #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
38665  #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
38666  #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
38667  #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
38668  #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
38669  #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
38670  #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
38671  #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
38672  #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
38673  #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
38674  #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
38675  #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
38676  #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
38677  #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
38678  #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
38679  #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
38680  #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
38681  #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
38682 /* ========================================================  PIPESEL  ======================================================== */
38683  #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
38684  #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
38685 /* ========================================================  PIPECFG  ======================================================== */
38686  #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
38687  #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
38688  #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
38689  #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
38690  #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
38691  #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
38692  #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
38693  #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
38694  #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
38695  #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
38696  #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
38697  #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
38698 /* =======================================================  PIPEMAXP  ======================================================== */
38699  #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
38700  #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
38701  #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
38702  #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
38703 /* =======================================================  PIPEPERI  ======================================================== */
38704  #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
38705  #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
38706  #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
38707  #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
38708 /* =======================================================  PIPE_CTR  ======================================================== */
38709  #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
38710  #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
38711  #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
38712  #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
38713  #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
38714  #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
38715  #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
38716  #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
38717  #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
38718  #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
38719  #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
38720  #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
38721  #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
38722  #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
38723  #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
38724  #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
38725  #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
38726  #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
38727  #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
38728  #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
38729  #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
38730  #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
38731 /* ========================================================  DEVADD  ========================================================= */
38732  #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
38733  #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
38734  #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
38735  #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
38736  #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
38737  #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
38738 /* ======================================================  USBBCCTRL0  ======================================================= */
38739  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
38740  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
38741  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
38742  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
38743  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
38744  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
38745  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
38746  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
38747  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
38748  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
38749  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
38750  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
38751  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
38752  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
38753  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
38754  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
38755  #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
38756  #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
38757 /* ========================================================  UCKSEL  ========================================================= */
38758  #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
38759  #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
38760 /* =========================================================  USBMC  ========================================================= */
38761  #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
38762  #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
38763  #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
38764  #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
38765 /* ========================================================  PHYSLEW  ======================================================== */
38766  #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
38767  #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
38768  #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
38769  #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
38770  #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
38771  #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
38772  #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
38773  #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
38774 /* ========================================================  LPCTRL  ========================================================= */
38775  #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
38776  #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
38777 /* =========================================================  LPSTS  ========================================================= */
38778  #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
38779  #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
38780 /* ========================================================  BCCTRL  ========================================================= */
38781  #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
38782  #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
38783  #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
38784  #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
38785  #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
38786  #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
38787  #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
38788  #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
38789  #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
38790  #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
38791  #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
38792  #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
38793  #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
38794  #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
38795  #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
38796  #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
38797 /* =======================================================  PL1CTRL1  ======================================================== */
38798  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
38799  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
38800  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
38801  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
38802  #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
38803  #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
38804  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
38805  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
38806  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
38807  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
38808  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
38809  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
38810 /* =======================================================  PL1CTRL2  ======================================================== */
38811  #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
38812  #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
38813  #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
38814  #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
38815 /* =======================================================  HL1CTRL1  ======================================================== */
38816  #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
38817  #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
38818  #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
38819  #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
38820 /* =======================================================  HL1CTRL2  ======================================================== */
38821  #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
38822  #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
38823  #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
38824  #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
38825  #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
38826  #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
38827  #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
38828  #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
38829 /* ========================================================  DPUSR0R  ======================================================== */
38830  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
38831  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
38832  #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
38833  #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
38834  #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
38835  #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
38836 /* ========================================================  DPUSR1R  ======================================================== */
38837  #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
38838  #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
38839  #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
38840  #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
38841  #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
38842  #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
38843  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
38844  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
38845  #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
38846  #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
38847  #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
38848  #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
38849 /* ========================================================  DPUSR2R  ======================================================== */
38850  #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
38851  #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
38852  #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
38853  #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
38854  #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
38855  #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
38856  #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
38857  #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
38858  #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
38859  #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
38860  #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
38861  #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
38862 /* ========================================================  DPUSRCR  ======================================================== */
38863  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
38864  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
38865  #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
38866  #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
38867 /* ======================================================  DPUSR0R_FS  ======================================================= */
38868  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
38869  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
38870  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
38871  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
38872  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
38873  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
38874  #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
38875  #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
38876  #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
38877  #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
38878  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
38879  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
38880  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
38881  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
38882  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
38883  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
38884  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
38885  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
38886 /* ======================================================  DPUSR1R_FS  ======================================================= */
38887  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
38888  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
38889  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
38890  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
38891  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
38892  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
38893  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
38894  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
38895  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
38896  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
38897  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
38898  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
38899  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
38900  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
38901  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
38902  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
38903  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
38904  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
38905  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
38906  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
38907 
38908 /* =========================================================================================================================== */
38909 /* ================                                           R_WDT                                           ================ */
38910 /* =========================================================================================================================== */
38911 
38912 /* =========================================================  WDTRR  ========================================================= */
38913  #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
38914  #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
38915 /* =========================================================  WDTCR  ========================================================= */
38916  #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
38917  #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
38918  #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
38919  #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
38920  #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
38921  #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
38922  #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
38923  #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
38924 /* =========================================================  WDTSR  ========================================================= */
38925  #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
38926  #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
38927  #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
38928  #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
38929  #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
38930  #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
38931 /* ========================================================  WDTRCR  ========================================================= */
38932  #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
38933  #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
38934 /* =======================================================  WDTCSTPR  ======================================================== */
38935  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
38936  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
38937 
38938 /* =========================================================================================================================== */
38939 /* ================                                           R_TZF                                           ================ */
38940 /* =========================================================================================================================== */
38941 
38942 /* ========================================================  TZFOAD  ========================================================= */
38943  #define R_TZF_TZFOAD_OAD_Pos       (0UL)      /*!< OAD (Bit 0)                                           */
38944  #define R_TZF_TZFOAD_OAD_Msk       (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
38945  #define R_TZF_TZFOAD_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
38946  #define R_TZF_TZFOAD_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
38947 /* =========================================================  TZFPT  ========================================================= */
38948  #define R_TZF_TZFPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
38949  #define R_TZF_TZFPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
38950  #define R_TZF_TZFPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
38951  #define R_TZF_TZFPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
38952 
38953 /* =========================================================================================================================== */
38954 /* ================                                          R_CPSCU                                          ================ */
38955 /* =========================================================================================================================== */
38956 
38957 /* =========================================================  CSAR  ========================================================== */
38958  #define R_CPSCU_CSAR_CACHESA_Pos            (0UL)          /*!< CACHESA (Bit 0)                                       */
38959  #define R_CPSCU_CSAR_CACHESA_Msk            (0x1UL)        /*!< CACHESA (Bitfield-Mask: 0x01)                         */
38960  #define R_CPSCU_CSAR_CACHELSA_Pos           (1UL)          /*!< CACHELSA (Bit 1)                                      */
38961  #define R_CPSCU_CSAR_CACHELSA_Msk           (0x2UL)        /*!< CACHELSA (Bitfield-Mask: 0x01)                        */
38962  #define R_CPSCU_CSAR_CACHEESA_Pos           (2UL)          /*!< CACHEESA (Bit 2)                                      */
38963  #define R_CPSCU_CSAR_CACHEESA_Msk           (0x4UL)        /*!< CACHEESA (Bitfield-Mask: 0x01)                        */
38964 /* ========================================================  SRAMSAR  ======================================================== */
38965  #define R_CPSCU_SRAMSAR_SRAMSA0_Pos         (0UL)          /*!< SRAMSA0 (Bit 0)                                       */
38966  #define R_CPSCU_SRAMSAR_SRAMSA0_Msk         (0x1UL)        /*!< SRAMSA0 (Bitfield-Mask: 0x01)                         */
38967  #define R_CPSCU_SRAMSAR_SRAMSA1_Pos         (1UL)          /*!< SRAMSA1 (Bit 1)                                       */
38968  #define R_CPSCU_SRAMSAR_SRAMSA1_Msk         (0x2UL)        /*!< SRAMSA1 (Bitfield-Mask: 0x01)                         */
38969  #define R_CPSCU_SRAMSAR_SRAMSA2_Pos         (2UL)          /*!< SRAMSA2 (Bit 2)                                       */
38970  #define R_CPSCU_SRAMSAR_SRAMSA2_Msk         (0x4UL)        /*!< SRAMSA2 (Bitfield-Mask: 0x01)                         */
38971 /* =======================================================  STBRAMSAR  ======================================================= */
38972  #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos       (0UL)          /*!< NSBSTBR (Bit 0)                                       */
38973  #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk       (0xfUL)        /*!< NSBSTBR (Bitfield-Mask: 0x0f)                         */
38974 /* ========================================================  DTCSAR  ========================================================= */
38975  #define R_CPSCU_DTCSAR_DTCSTSA_Pos          (0UL)          /*!< DTCSTSA (Bit 0)                                       */
38976  #define R_CPSCU_DTCSAR_DTCSTSA_Msk          (0x1UL)        /*!< DTCSTSA (Bitfield-Mask: 0x01)                         */
38977 /* ========================================================  DMACSAR  ======================================================== */
38978  #define R_CPSCU_DMACSAR_DMASTSA_Pos         (0UL)          /*!< DMASTSA (Bit 0)                                       */
38979  #define R_CPSCU_DMACSAR_DMASTSA_Msk         (0x1UL)        /*!< DMASTSA (Bitfield-Mask: 0x01)                         */
38980 /* ========================================================  ICUSARA  ======================================================== */
38981  #define R_CPSCU_ICUSARA_SAIRQCRn_Pos        (0UL)          /*!< SAIRQCRn (Bit 0)                                      */
38982  #define R_CPSCU_ICUSARA_SAIRQCRn_Msk        (0xffffUL)     /*!< SAIRQCRn (Bitfield-Mask: 0xffff)                      */
38983 /* ========================================================  ICUSARB  ======================================================== */
38984  #define R_CPSCU_ICUSARB_SANMI_Pos           (0UL)          /*!< SANMI (Bit 0)                                         */
38985  #define R_CPSCU_ICUSARB_SANMI_Msk           (0x1UL)        /*!< SANMI (Bitfield-Mask: 0x01)                           */
38986 /* ========================================================  ICUSARC  ======================================================== */
38987  #define R_CPSCU_ICUSARC_SADMACn_Pos         (0UL)          /*!< SADMACn (Bit 0)                                       */
38988  #define R_CPSCU_ICUSARC_SADMACn_Msk         (0xffUL)       /*!< SADMACn (Bitfield-Mask: 0xff)                         */
38989 /* ========================================================  ICUSARD  ======================================================== */
38990  #define R_CPSCU_ICUSARD_SASELSR0_Pos        (0UL)          /*!< SASELSR0 (Bit 0)                                      */
38991  #define R_CPSCU_ICUSARD_SASELSR0_Msk        (0x1UL)        /*!< SASELSR0 (Bitfield-Mask: 0x01)                        */
38992 /* ========================================================  ICUSARE  ======================================================== */
38993  #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos       (16UL)         /*!< SAIWDTWUP (Bit 16)                                    */
38994  #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk       (0x10000UL)    /*!< SAIWDTWUP (Bitfield-Mask: 0x01)                       */
38995  #define R_CPSCU_ICUSARE_SALVD1WUP_Pos       (18UL)         /*!< SALVD1WUP (Bit 18)                                    */
38996  #define R_CPSCU_ICUSARE_SALVD1WUP_Msk       (0x40000UL)    /*!< SALVD1WUP (Bitfield-Mask: 0x01)                       */
38997  #define R_CPSCU_ICUSARE_SALVD2WUP_Pos       (19UL)         /*!< SALVD2WUP (Bit 19)                                    */
38998  #define R_CPSCU_ICUSARE_SALVD2WUP_Msk       (0x80000UL)    /*!< SALVD2WUP (Bitfield-Mask: 0x01)                       */
38999  #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos      (20UL)         /*!< SAVBATTWUP (Bit 20)                                   */
39000  #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk      (0x100000UL)   /*!< SAVBATTWUP (Bitfield-Mask: 0x01)                      */
39001  #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos     (24UL)         /*!< SARTCALMWUP (Bit 24)                                  */
39002  #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk     (0x1000000UL)  /*!< SARTCALMWUP (Bitfield-Mask: 0x01)                     */
39003  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos     (25UL)         /*!< SARTCPRDWUP (Bit 25)                                  */
39004  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk     (0x2000000UL)  /*!< SARTCPRDWUP (Bitfield-Mask: 0x01)                     */
39005  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos     (27UL)         /*!< SAUSBFS0WUP (Bit 27)                                  */
39006  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk     (0x8000000UL)  /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01)                     */
39007  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos     (28UL)         /*!< SAAGT1UDWUP (Bit 28)                                  */
39008  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk     (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01)                     */
39009  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos     (29UL)         /*!< SAAGT1CAWUP (Bit 29)                                  */
39010  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk     (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01)                     */
39011  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos     (30UL)         /*!< SAAGT1CBWUP (Bit 30)                                  */
39012  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk     (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01)                     */
39013  #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos       (31UL)         /*!< SAIIC0WUP (Bit 31)                                    */
39014  #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk       (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01)                       */
39015 /* ========================================================  ICUSARF  ======================================================== */
39016  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos     (0UL)          /*!< SAAGT3UDWUP (Bit 0)                                   */
39017  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk     (0x1UL)        /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01)                     */
39018  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos     (1UL)          /*!< SAAGT3CAWUP (Bit 1)                                   */
39019  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk     (0x2UL)        /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01)                     */
39020  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos     (2UL)          /*!< SAAGT3CBWUP (Bit 2)                                   */
39021  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk     (0x4UL)        /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01)                     */
39022  #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos    (3UL)          /*!< SACOMPHS0WUP (Bit 3)                                  */
39023  #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk    (0x8UL)        /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01)                    */
39024  #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos      (8UL)          /*!< SAULP0UWUP (Bit 8)                                    */
39025  #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk      (0x100UL)      /*!< SAULP0UWUP (Bitfield-Mask: 0x01)                      */
39026  #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos      (9UL)          /*!< SAULP0AWUP (Bit 9)                                    */
39027  #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk      (0x200UL)      /*!< SAULP0AWUP (Bitfield-Mask: 0x01)                      */
39028  #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos      (10UL)         /*!< SAULP0BWUP (Bit 10)                                   */
39029  #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk      (0x400UL)      /*!< SAULP0BWUP (Bitfield-Mask: 0x01)                      */
39030  #define R_CPSCU_ICUSARF_SAI3CWUP_Pos        (11UL)         /*!< SAI3CWUP (Bit 11)                                     */
39031  #define R_CPSCU_ICUSARF_SAI3CWUP_Msk        (0x800UL)      /*!< SAI3CWUP (Bitfield-Mask: 0x01)                        */
39032  #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos      (12UL)         /*!< SAULP1UWUP (Bit 12)                                   */
39033  #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk      (0x1000UL)     /*!< SAULP1UWUP (Bitfield-Mask: 0x01)                      */
39034  #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos      (13UL)         /*!< SAULP1AWUP (Bit 13)                                   */
39035  #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk      (0x2000UL)     /*!< SAULP1AWUP (Bitfield-Mask: 0x01)                      */
39036  #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos      (14UL)         /*!< SAULP1BWUP (Bit 14)                                   */
39037  #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk      (0x4000UL)     /*!< SAULP1BWUP (Bitfield-Mask: 0x01)                      */
39038 /* ========================================================  ICUSARG  ======================================================== */
39039  #define R_CPSCU_ICUSARG_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
39040  #define R_CPSCU_ICUSARG_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
39041 /* ========================================================  ICUSARH  ======================================================== */
39042  #define R_CPSCU_ICUSARH_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
39043  #define R_CPSCU_ICUSARH_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
39044 /* ========================================================  ICUSARI  ======================================================== */
39045  #define R_CPSCU_ICUSARI_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
39046  #define R_CPSCU_ICUSARI_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
39047 /* ========================================================  BUSSARA  ======================================================== */
39048  #define R_CPSCU_BUSSARA_BUSSA0_Pos          (0UL)          /*!< BUSSA0 (Bit 0)                                        */
39049  #define R_CPSCU_BUSSARA_BUSSA0_Msk          (0x1UL)        /*!< BUSSA0 (Bitfield-Mask: 0x01)                          */
39050 /* ========================================================  BUSSARB  ======================================================== */
39051  #define R_CPSCU_BUSSARB_BUSSB0_Pos          (0UL)          /*!< BUSSB0 (Bit 0)                                        */
39052  #define R_CPSCU_BUSSARB_BUSSB0_Msk          (0x1UL)        /*!< BUSSB0 (Bitfield-Mask: 0x01)                          */
39053 /* =======================================================  MMPUSARA  ======================================================== */
39054  #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos       (0UL)          /*!< MMPUAnSA (Bit 0)                                      */
39055  #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk       (0xffUL)       /*!< MMPUAnSA (Bitfield-Mask: 0xff)                        */
39056 /* =======================================================  MMPUSARB  ======================================================== */
39057  #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos       (0UL)          /*!< MMPUB0SA (Bit 0)                                      */
39058  #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk       (0x1UL)        /*!< MMPUB0SA (Bitfield-Mask: 0x01)                        */
39059 /* =======================================================  DMACCHSAR  ======================================================= */
39060  #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos    (0UL)          /*!< DMACCHSARn (Bit 0)                                    */
39061  #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk    (0xffUL)       /*!< DMACCHSARn (Bitfield-Mask: 0xff)                      */
39062 /* ========================================================  CPUDSAR  ======================================================== */
39063  #define R_CPSCU_CPUDSAR_CPUDSA0_Pos         (0UL)          /*!< CPUDSA0 (Bit 0)                                       */
39064  #define R_CPSCU_CPUDSAR_CPUDSA0_Msk         (0x1UL)        /*!< CPUDSA0 (Bitfield-Mask: 0x01)                         */
39065 /* ======================================================  SRAMSABAR0  ======================================================= */
39066  #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos    (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
39067  #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk    (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
39068 /* ======================================================  SRAMSABAR1  ======================================================= */
39069  #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos    (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
39070  #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk    (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
39071 /* ========================================================  TEVTRCR  ======================================================== */
39072  #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
39073  #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
39074 
39075 /* =========================================================================================================================== */
39076 /* ================                                          R_DOC_B                                          ================ */
39077 /* =========================================================================================================================== */
39078 
39079 /* =========================================================  DOCR  ========================================================== */
39080  #define R_DOC_B_DOCR_OMS_Pos         (0UL)    /*!< OMS (Bit 0)                                           */
39081  #define R_DOC_B_DOCR_OMS_Msk         (0x3UL)  /*!< OMS (Bitfield-Mask: 0x03)                             */
39082  #define R_DOC_B_DOCR_DOBW_Pos        (3UL)    /*!< DOBW (Bit 3)                                          */
39083  #define R_DOC_B_DOCR_DOBW_Msk        (0x8UL)  /*!< DOBW (Bitfield-Mask: 0x01)                            */
39084  #define R_DOC_B_DOCR_DCSEL_Pos       (4UL)    /*!< DCSEL (Bit 4)                                         */
39085  #define R_DOC_B_DOCR_DCSEL_Msk       (0x70UL) /*!< DCSEL (Bitfield-Mask: 0x07)                           */
39086 /* =========================================================  DOSR  ========================================================== */
39087  #define R_DOC_B_DOSR_DOPCF_Pos       (0UL)    /*!< DOPCF (Bit 0)                                         */
39088  #define R_DOC_B_DOSR_DOPCF_Msk       (0x1UL)  /*!< DOPCF (Bitfield-Mask: 0x01)                           */
39089 /* =========================================================  DOSCR  ========================================================= */
39090  #define R_DOC_B_DOSCR_DOPCFCL_Pos    (0UL)    /*!< DOPCFCL (Bit 0)                                       */
39091  #define R_DOC_B_DOSCR_DOPCFCL_Msk    (0x1UL)  /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
39092 /* =========================================================  DODIR  ========================================================= */
39093 /* ========================================================  DODSR0  ========================================================= */
39094 /* ========================================================  DODSR1  ========================================================= */
39095 
39096 /* =========================================================================================================================== */
39097 /* ================                                         R_SCI_B0                                          ================ */
39098 /* =========================================================================================================================== */
39099 
39100 /* ==========================================================  RDR  ========================================================== */
39101  #define R_SCI_B0_RDR_RDAT_Pos           (0UL)          /*!< RDAT (Bit 0)                                          */
39102  #define R_SCI_B0_RDR_RDAT_Msk           (0x1ffUL)      /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
39103  #define R_SCI_B0_RDR_MPB_Pos            (9UL)          /*!< MPB (Bit 9)                                           */
39104  #define R_SCI_B0_RDR_MPB_Msk            (0x200UL)      /*!< MPB (Bitfield-Mask: 0x01)                             */
39105  #define R_SCI_B0_RDR_DR_Pos             (10UL)         /*!< DR (Bit 10)                                           */
39106  #define R_SCI_B0_RDR_DR_Msk             (0x400UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
39107  #define R_SCI_B0_RDR_FPER_Pos           (11UL)         /*!< FPER (Bit 11)                                         */
39108  #define R_SCI_B0_RDR_FPER_Msk           (0x800UL)      /*!< FPER (Bitfield-Mask: 0x01)                            */
39109  #define R_SCI_B0_RDR_FFER_Pos           (12UL)         /*!< FFER (Bit 12)                                         */
39110  #define R_SCI_B0_RDR_FFER_Msk           (0x1000UL)     /*!< FFER (Bitfield-Mask: 0x01)                            */
39111  #define R_SCI_B0_RDR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
39112  #define R_SCI_B0_RDR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
39113  #define R_SCI_B0_RDR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
39114  #define R_SCI_B0_RDR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
39115  #define R_SCI_B0_RDR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
39116  #define R_SCI_B0_RDR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
39117 /* ========================================================  RDR_BY  ========================================================= */
39118  #define R_SCI_B0_RDR_BY_RDAT_Pos        (0UL)          /*!< RDAT (Bit 0)                                          */
39119  #define R_SCI_B0_RDR_BY_RDAT_Msk        (0xffUL)       /*!< RDAT (Bitfield-Mask: 0xff)                            */
39120 /* ==========================================================  TDR  ========================================================== */
39121  #define R_SCI_B0_TDR_TDAT_Pos           (0UL)          /*!< TDAT (Bit 0)                                          */
39122  #define R_SCI_B0_TDR_TDAT_Msk           (0x1ffUL)      /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
39123  #define R_SCI_B0_TDR_MPBT_Pos           (9UL)          /*!< MPBT (Bit 9)                                          */
39124  #define R_SCI_B0_TDR_MPBT_Msk           (0x200UL)      /*!< MPBT (Bitfield-Mask: 0x01)                            */
39125  #define R_SCI_B0_TDR_TSYNC_Pos          (12UL)         /*!< TSYNC (Bit 12)                                        */
39126  #define R_SCI_B0_TDR_TSYNC_Msk          (0x1000UL)     /*!< TSYNC (Bitfield-Mask: 0x01)                           */
39127 /* ========================================================  TDR_BY  ========================================================= */
39128  #define R_SCI_B0_TDR_BY_TDAT_Pos        (0UL)          /*!< TDAT (Bit 0)                                          */
39129  #define R_SCI_B0_TDR_BY_TDAT_Msk        (0xffUL)       /*!< TDAT (Bitfield-Mask: 0xff)                            */
39130 /* =========================================================  CCR0  ========================================================== */
39131  #define R_SCI_B0_CCR0_RE_Pos            (0UL)          /*!< RE (Bit 0)                                            */
39132  #define R_SCI_B0_CCR0_RE_Msk            (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
39133  #define R_SCI_B0_CCR0_TE_Pos            (4UL)          /*!< TE (Bit 4)                                            */
39134  #define R_SCI_B0_CCR0_TE_Msk            (0x10UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
39135  #define R_SCI_B0_CCR0_MPIE_Pos          (8UL)          /*!< MPIE (Bit 8)                                          */
39136  #define R_SCI_B0_CCR0_MPIE_Msk          (0x100UL)      /*!< MPIE (Bitfield-Mask: 0x01)                            */
39137  #define R_SCI_B0_CCR0_DCME_Pos          (9UL)          /*!< DCME (Bit 9)                                          */
39138  #define R_SCI_B0_CCR0_DCME_Msk          (0x200UL)      /*!< DCME (Bitfield-Mask: 0x01)                            */
39139  #define R_SCI_B0_CCR0_IDSEL_Pos         (10UL)         /*!< IDSEL (Bit 10)                                        */
39140  #define R_SCI_B0_CCR0_IDSEL_Msk         (0x400UL)      /*!< IDSEL (Bitfield-Mask: 0x01)                           */
39141  #define R_SCI_B0_CCR0_RIE_Pos           (16UL)         /*!< RIE (Bit 16)                                          */
39142  #define R_SCI_B0_CCR0_RIE_Msk           (0x10000UL)    /*!< RIE (Bitfield-Mask: 0x01)                             */
39143  #define R_SCI_B0_CCR0_TIE_Pos           (20UL)         /*!< TIE (Bit 20)                                          */
39144  #define R_SCI_B0_CCR0_TIE_Msk           (0x100000UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
39145  #define R_SCI_B0_CCR0_TEIE_Pos          (21UL)         /*!< TEIE (Bit 21)                                         */
39146  #define R_SCI_B0_CCR0_TEIE_Msk          (0x200000UL)   /*!< TEIE (Bitfield-Mask: 0x01)                            */
39147  #define R_SCI_B0_CCR0_SSE_Pos           (24UL)         /*!< SSE (Bit 24)                                          */
39148  #define R_SCI_B0_CCR0_SSE_Msk           (0x1000000UL)  /*!< SSE (Bitfield-Mask: 0x01)                             */
39149 /* =========================================================  CCR1  ========================================================== */
39150  #define R_SCI_B0_CCR1_CTSE_Pos          (0UL)          /*!< CTSE (Bit 0)                                          */
39151  #define R_SCI_B0_CCR1_CTSE_Msk          (0x1UL)        /*!< CTSE (Bitfield-Mask: 0x01)                            */
39152  #define R_SCI_B0_CCR1_CTSPEN_Pos        (1UL)          /*!< CTSPEN (Bit 1)                                        */
39153  #define R_SCI_B0_CCR1_CTSPEN_Msk        (0x2UL)        /*!< CTSPEN (Bitfield-Mask: 0x01)                          */
39154  #define R_SCI_B0_CCR1_SPB2DT_Pos        (4UL)          /*!< SPB2DT (Bit 4)                                        */
39155  #define R_SCI_B0_CCR1_SPB2DT_Msk        (0x10UL)       /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
39156  #define R_SCI_B0_CCR1_SPB2IO_Pos        (5UL)          /*!< SPB2IO (Bit 5)                                        */
39157  #define R_SCI_B0_CCR1_SPB2IO_Msk        (0x20UL)       /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
39158  #define R_SCI_B0_CCR1_PE_Pos            (8UL)          /*!< PE (Bit 8)                                            */
39159  #define R_SCI_B0_CCR1_PE_Msk            (0x100UL)      /*!< PE (Bitfield-Mask: 0x01)                              */
39160  #define R_SCI_B0_CCR1_PM_Pos            (9UL)          /*!< PM (Bit 9)                                            */
39161  #define R_SCI_B0_CCR1_PM_Msk            (0x200UL)      /*!< PM (Bitfield-Mask: 0x01)                              */
39162  #define R_SCI_B0_CCR1_TINV_Pos          (12UL)         /*!< TINV (Bit 12)                                         */
39163  #define R_SCI_B0_CCR1_TINV_Msk          (0x1000UL)     /*!< TINV (Bitfield-Mask: 0x01)                            */
39164  #define R_SCI_B0_CCR1_RINV_Pos          (13UL)         /*!< RINV (Bit 13)                                         */
39165  #define R_SCI_B0_CCR1_RINV_Msk          (0x2000UL)     /*!< RINV (Bitfield-Mask: 0x01)                            */
39166  #define R_SCI_B0_CCR1_SPLP_Pos          (16UL)         /*!< SPLP (Bit 16)                                         */
39167  #define R_SCI_B0_CCR1_SPLP_Msk          (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
39168  #define R_SCI_B0_CCR1_SHARPS_Pos        (20UL)         /*!< SHARPS (Bit 20)                                       */
39169  #define R_SCI_B0_CCR1_SHARPS_Msk        (0x100000UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
39170  #define R_SCI_B0_CCR1_NFCS_Pos          (24UL)         /*!< NFCS (Bit 24)                                         */
39171  #define R_SCI_B0_CCR1_NFCS_Msk          (0x7000000UL)  /*!< NFCS (Bitfield-Mask: 0x07)                            */
39172  #define R_SCI_B0_CCR1_NFEN_Pos          (28UL)         /*!< NFEN (Bit 28)                                         */
39173  #define R_SCI_B0_CCR1_NFEN_Msk          (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
39174 /* =========================================================  CCR2  ========================================================== */
39175  #define R_SCI_B0_CCR2_BCP_Pos           (0UL)          /*!< BCP (Bit 0)                                           */
39176  #define R_SCI_B0_CCR2_BCP_Msk           (0x7UL)        /*!< BCP (Bitfield-Mask: 0x07)                             */
39177  #define R_SCI_B0_CCR2_BGDM_Pos          (4UL)          /*!< BGDM (Bit 4)                                          */
39178  #define R_SCI_B0_CCR2_BGDM_Msk          (0x10UL)       /*!< BGDM (Bitfield-Mask: 0x01)                            */
39179  #define R_SCI_B0_CCR2_ABCS_Pos          (5UL)          /*!< ABCS (Bit 5)                                          */
39180  #define R_SCI_B0_CCR2_ABCS_Msk          (0x20UL)       /*!< ABCS (Bitfield-Mask: 0x01)                            */
39181  #define R_SCI_B0_CCR2_ABCSE_Pos         (6UL)          /*!< ABCSE (Bit 6)                                         */
39182  #define R_SCI_B0_CCR2_ABCSE_Msk         (0x40UL)       /*!< ABCSE (Bitfield-Mask: 0x01)                           */
39183  #define R_SCI_B0_CCR2_BRR_Pos           (8UL)          /*!< BRR (Bit 8)                                           */
39184  #define R_SCI_B0_CCR2_BRR_Msk           (0xff00UL)     /*!< BRR (Bitfield-Mask: 0xff)                             */
39185  #define R_SCI_B0_CCR2_BRME_Pos          (16UL)         /*!< BRME (Bit 16)                                         */
39186  #define R_SCI_B0_CCR2_BRME_Msk          (0x10000UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
39187  #define R_SCI_B0_CCR2_CKS_Pos           (20UL)         /*!< CKS (Bit 20)                                          */
39188  #define R_SCI_B0_CCR2_CKS_Msk           (0x300000UL)   /*!< CKS (Bitfield-Mask: 0x03)                             */
39189  #define R_SCI_B0_CCR2_MDDR_Pos          (24UL)         /*!< MDDR (Bit 24)                                         */
39190  #define R_SCI_B0_CCR2_MDDR_Msk          (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff)                            */
39191 /* =========================================================  CCR3  ========================================================== */
39192  #define R_SCI_B0_CCR3_CPHA_Pos          (0UL)          /*!< CPHA (Bit 0)                                          */
39193  #define R_SCI_B0_CCR3_CPHA_Msk          (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39194  #define R_SCI_B0_CCR3_CPOL_Pos          (1UL)          /*!< CPOL (Bit 1)                                          */
39195  #define R_SCI_B0_CCR3_CPOL_Msk          (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39196  #define R_SCI_B0_CCR3_BPEN_Pos          (7UL)          /*!< BPEN (Bit 7)                                          */
39197  #define R_SCI_B0_CCR3_BPEN_Msk          (0x80UL)       /*!< BPEN (Bitfield-Mask: 0x01)                            */
39198  #define R_SCI_B0_CCR3_CHR_Pos           (8UL)          /*!< CHR (Bit 8)                                           */
39199  #define R_SCI_B0_CCR3_CHR_Msk           (0x300UL)      /*!< CHR (Bitfield-Mask: 0x03)                             */
39200  #define R_SCI_B0_CCR3_LSBF_Pos          (12UL)         /*!< LSBF (Bit 12)                                         */
39201  #define R_SCI_B0_CCR3_LSBF_Msk          (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39202  #define R_SCI_B0_CCR3_SINV_Pos          (13UL)         /*!< SINV (Bit 13)                                         */
39203  #define R_SCI_B0_CCR3_SINV_Msk          (0x2000UL)     /*!< SINV (Bitfield-Mask: 0x01)                            */
39204  #define R_SCI_B0_CCR3_STP_Pos           (14UL)         /*!< STP (Bit 14)                                          */
39205  #define R_SCI_B0_CCR3_STP_Msk           (0x4000UL)     /*!< STP (Bitfield-Mask: 0x01)                             */
39206  #define R_SCI_B0_CCR3_RXDESEL_Pos       (15UL)         /*!< RXDESEL (Bit 15)                                      */
39207  #define R_SCI_B0_CCR3_RXDESEL_Msk       (0x8000UL)     /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
39208  #define R_SCI_B0_CCR3_MOD_Pos           (16UL)         /*!< MOD (Bit 16)                                          */
39209  #define R_SCI_B0_CCR3_MOD_Msk           (0x70000UL)    /*!< MOD (Bitfield-Mask: 0x07)                             */
39210  #define R_SCI_B0_CCR3_MP_Pos            (19UL)         /*!< MP (Bit 19)                                           */
39211  #define R_SCI_B0_CCR3_MP_Msk            (0x80000UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
39212  #define R_SCI_B0_CCR3_FM_Pos            (20UL)         /*!< FM (Bit 20)                                           */
39213  #define R_SCI_B0_CCR3_FM_Msk            (0x100000UL)   /*!< FM (Bitfield-Mask: 0x01)                              */
39214  #define R_SCI_B0_CCR3_DEN_Pos           (21UL)         /*!< DEN (Bit 21)                                          */
39215  #define R_SCI_B0_CCR3_DEN_Msk           (0x200000UL)   /*!< DEN (Bitfield-Mask: 0x01)                             */
39216  #define R_SCI_B0_CCR3_CKE_Pos           (24UL)         /*!< CKE (Bit 24)                                          */
39217  #define R_SCI_B0_CCR3_CKE_Msk           (0x3000000UL)  /*!< CKE (Bitfield-Mask: 0x03)                             */
39218  #define R_SCI_B0_CCR3_GM_Pos            (28UL)         /*!< GM (Bit 28)                                           */
39219  #define R_SCI_B0_CCR3_GM_Msk            (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01)                              */
39220  #define R_SCI_B0_CCR3_BLK_Pos           (29UL)         /*!< BLK (Bit 29)                                          */
39221  #define R_SCI_B0_CCR3_BLK_Msk           (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01)                             */
39222 /* =========================================================  CCR4  ========================================================== */
39223  #define R_SCI_B0_CCR4_CMPD_Pos          (0UL)          /*!< CMPD (Bit 0)                                          */
39224  #define R_SCI_B0_CCR4_CMPD_Msk          (0x1ffUL)      /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
39225  #define R_SCI_B0_CCR4_ASEN_Pos          (16UL)         /*!< ASEN (Bit 16)                                         */
39226  #define R_SCI_B0_CCR4_ASEN_Msk          (0x10000UL)    /*!< ASEN (Bitfield-Mask: 0x01)                            */
39227  #define R_SCI_B0_CCR4_ATEN_Pos          (17UL)         /*!< ATEN (Bit 17)                                         */
39228  #define R_SCI_B0_CCR4_ATEN_Msk          (0x20000UL)    /*!< ATEN (Bitfield-Mask: 0x01)                            */
39229  #define R_SCI_B0_CCR4_SCKSEL_Pos        (19UL)         /*!< SCKSEL (Bit 19)                                       */
39230  #define R_SCI_B0_CCR4_SCKSEL_Msk        (0x80000UL)    /*!< SCKSEL (Bitfield-Mask: 0x01)                          */
39231  #define R_SCI_B0_CCR4_AST_Pos           (24UL)         /*!< AST (Bit 24)                                          */
39232  #define R_SCI_B0_CCR4_AST_Msk           (0x7000000UL)  /*!< AST (Bitfield-Mask: 0x07)                             */
39233  #define R_SCI_B0_CCR4_AJD_Pos           (27UL)         /*!< AJD (Bit 27)                                          */
39234  #define R_SCI_B0_CCR4_AJD_Msk           (0x8000000UL)  /*!< AJD (Bitfield-Mask: 0x01)                             */
39235  #define R_SCI_B0_CCR4_ATT_Pos           (28UL)         /*!< ATT (Bit 28)                                          */
39236  #define R_SCI_B0_CCR4_ATT_Msk           (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07)                             */
39237  #define R_SCI_B0_CCR4_AET_Pos           (31UL)         /*!< AET (Bit 31)                                          */
39238  #define R_SCI_B0_CCR4_AET_Msk           (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01)                             */
39239 /* =========================================================  CESR  ========================================================== */
39240  #define R_SCI_B0_CESR_RIST_Pos          (0UL)          /*!< RIST (Bit 0)                                          */
39241  #define R_SCI_B0_CESR_RIST_Msk          (0x1UL)        /*!< RIST (Bitfield-Mask: 0x01)                            */
39242  #define R_SCI_B0_CESR_TIST_Pos          (4UL)          /*!< TIST (Bit 4)                                          */
39243  #define R_SCI_B0_CESR_TIST_Msk          (0x10UL)       /*!< TIST (Bitfield-Mask: 0x01)                            */
39244 /* ==========================================================  ICR  ========================================================== */
39245  #define R_SCI_B0_ICR_IICDL_Pos          (0UL)          /*!< IICDL (Bit 0)                                         */
39246  #define R_SCI_B0_ICR_IICDL_Msk          (0x1fUL)       /*!< IICDL (Bitfield-Mask: 0x1f)                           */
39247  #define R_SCI_B0_ICR_IICINTM_Pos        (8UL)          /*!< IICINTM (Bit 8)                                       */
39248  #define R_SCI_B0_ICR_IICINTM_Msk        (0x100UL)      /*!< IICINTM (Bitfield-Mask: 0x01)                         */
39249  #define R_SCI_B0_ICR_IICCSC_Pos         (9UL)          /*!< IICCSC (Bit 9)                                        */
39250  #define R_SCI_B0_ICR_IICCSC_Msk         (0x200UL)      /*!< IICCSC (Bitfield-Mask: 0x01)                          */
39251  #define R_SCI_B0_ICR_IICACKT_Pos        (13UL)         /*!< IICACKT (Bit 13)                                      */
39252  #define R_SCI_B0_ICR_IICACKT_Msk        (0x2000UL)     /*!< IICACKT (Bitfield-Mask: 0x01)                         */
39253  #define R_SCI_B0_ICR_IICSTAREQ_Pos      (16UL)         /*!< IICSTAREQ (Bit 16)                                    */
39254  #define R_SCI_B0_ICR_IICSTAREQ_Msk      (0x10000UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
39255  #define R_SCI_B0_ICR_IICRSTAREQ_Pos     (17UL)         /*!< IICRSTAREQ (Bit 17)                                   */
39256  #define R_SCI_B0_ICR_IICRSTAREQ_Msk     (0x20000UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
39257  #define R_SCI_B0_ICR_IICSTPREQ_Pos      (18UL)         /*!< IICSTPREQ (Bit 18)                                    */
39258  #define R_SCI_B0_ICR_IICSTPREQ_Msk      (0x40000UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
39259  #define R_SCI_B0_ICR_IICSDAS_Pos        (20UL)         /*!< IICSDAS (Bit 20)                                      */
39260  #define R_SCI_B0_ICR_IICSDAS_Msk        (0x300000UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
39261  #define R_SCI_B0_ICR_IICSCLS_Pos        (22UL)         /*!< IICSCLS (Bit 22)                                      */
39262  #define R_SCI_B0_ICR_IICSCLS_Msk        (0xc00000UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
39263 /* ==========================================================  FCR  ========================================================== */
39264  #define R_SCI_B0_FCR_DRES_Pos           (0UL)          /*!< DRES (Bit 0)                                          */
39265  #define R_SCI_B0_FCR_DRES_Msk           (0x1UL)        /*!< DRES (Bitfield-Mask: 0x01)                            */
39266  #define R_SCI_B0_FCR_TTRG_Pos           (8UL)          /*!< TTRG (Bit 8)                                          */
39267  #define R_SCI_B0_FCR_TTRG_Msk           (0x1f00UL)     /*!< TTRG (Bitfield-Mask: 0x1f)                            */
39268  #define R_SCI_B0_FCR_TFRST_Pos          (15UL)         /*!< TFRST (Bit 15)                                        */
39269  #define R_SCI_B0_FCR_TFRST_Msk          (0x8000UL)     /*!< TFRST (Bitfield-Mask: 0x01)                           */
39270  #define R_SCI_B0_FCR_RTRG_Pos           (16UL)         /*!< RTRG (Bit 16)                                         */
39271  #define R_SCI_B0_FCR_RTRG_Msk           (0x1f0000UL)   /*!< RTRG (Bitfield-Mask: 0x1f)                            */
39272  #define R_SCI_B0_FCR_RFRST_Pos          (23UL)         /*!< RFRST (Bit 23)                                        */
39273  #define R_SCI_B0_FCR_RFRST_Msk          (0x800000UL)   /*!< RFRST (Bitfield-Mask: 0x01)                           */
39274  #define R_SCI_B0_FCR_RSTRG_Pos          (24UL)         /*!< RSTRG (Bit 24)                                        */
39275  #define R_SCI_B0_FCR_RSTRG_Msk          (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f)                           */
39276 /* ==========================================================  MCR  ========================================================== */
39277  #define R_SCI_B0_MCR_RMPOL_Pos          (0UL)          /*!< RMPOL (Bit 0)                                         */
39278  #define R_SCI_B0_MCR_RMPOL_Msk          (0x1UL)        /*!< RMPOL (Bitfield-Mask: 0x01)                           */
39279  #define R_SCI_B0_MCR_TMPOL_Pos          (1UL)          /*!< TMPOL (Bit 1)                                         */
39280  #define R_SCI_B0_MCR_TMPOL_Msk          (0x2UL)        /*!< TMPOL (Bitfield-Mask: 0x01)                           */
39281  #define R_SCI_B0_MCR_ERTEN_Pos          (2UL)          /*!< ERTEN (Bit 2)                                         */
39282  #define R_SCI_B0_MCR_ERTEN_Msk          (0x4UL)        /*!< ERTEN (Bitfield-Mask: 0x01)                           */
39283  #define R_SCI_B0_MCR_SYNVAL_Pos         (4UL)          /*!< SYNVAL (Bit 4)                                        */
39284  #define R_SCI_B0_MCR_SYNVAL_Msk         (0x10UL)       /*!< SYNVAL (Bitfield-Mask: 0x01)                          */
39285  #define R_SCI_B0_MCR_SYNSEL_Pos         (5UL)          /*!< SYNSEL (Bit 5)                                        */
39286  #define R_SCI_B0_MCR_SYNSEL_Msk         (0x20UL)       /*!< SYNSEL (Bitfield-Mask: 0x01)                          */
39287  #define R_SCI_B0_MCR_SBSEL_Pos          (6UL)          /*!< SBSEL (Bit 6)                                         */
39288  #define R_SCI_B0_MCR_SBSEL_Msk          (0x40UL)       /*!< SBSEL (Bitfield-Mask: 0x01)                           */
39289  #define R_SCI_B0_MCR_TPLEN_Pos          (8UL)          /*!< TPLEN (Bit 8)                                         */
39290  #define R_SCI_B0_MCR_TPLEN_Msk          (0xf00UL)      /*!< TPLEN (Bitfield-Mask: 0x0f)                           */
39291  #define R_SCI_B0_MCR_TPPAT_Pos          (12UL)         /*!< TPPAT (Bit 12)                                        */
39292  #define R_SCI_B0_MCR_TPPAT_Msk          (0x3000UL)     /*!< TPPAT (Bitfield-Mask: 0x03)                           */
39293  #define R_SCI_B0_MCR_RPLEN_Pos          (16UL)         /*!< RPLEN (Bit 16)                                        */
39294  #define R_SCI_B0_MCR_RPLEN_Msk          (0xf0000UL)    /*!< RPLEN (Bitfield-Mask: 0x0f)                           */
39295  #define R_SCI_B0_MCR_RPPAT_Pos          (20UL)         /*!< RPPAT (Bit 20)                                        */
39296  #define R_SCI_B0_MCR_RPPAT_Msk          (0x300000UL)   /*!< RPPAT (Bitfield-Mask: 0x03)                           */
39297  #define R_SCI_B0_MCR_PFEREN_Pos         (24UL)         /*!< PFEREN (Bit 24)                                       */
39298  #define R_SCI_B0_MCR_PFEREN_Msk         (0x1000000UL)  /*!< PFEREN (Bitfield-Mask: 0x01)                          */
39299  #define R_SCI_B0_MCR_SYEREN_Pos         (25UL)         /*!< SYEREN (Bit 25)                                       */
39300  #define R_SCI_B0_MCR_SYEREN_Msk         (0x2000000UL)  /*!< SYEREN (Bitfield-Mask: 0x01)                          */
39301  #define R_SCI_B0_MCR_SBEREN_Pos         (26UL)         /*!< SBEREN (Bit 26)                                       */
39302  #define R_SCI_B0_MCR_SBEREN_Msk         (0x4000000UL)  /*!< SBEREN (Bitfield-Mask: 0x01)                          */
39303 /* ==========================================================  DCR  ========================================================== */
39304  #define R_SCI_B0_DCR_DEPOL_Pos          (0UL)          /*!< DEPOL (Bit 0)                                         */
39305  #define R_SCI_B0_DCR_DEPOL_Msk          (0x1UL)        /*!< DEPOL (Bitfield-Mask: 0x01)                           */
39306  #define R_SCI_B0_DCR_DEAST_Pos          (8UL)          /*!< DEAST (Bit 8)                                         */
39307  #define R_SCI_B0_DCR_DEAST_Msk          (0x1f00UL)     /*!< DEAST (Bitfield-Mask: 0x1f)                           */
39308  #define R_SCI_B0_DCR_DENGT_Pos          (16UL)         /*!< DENGT (Bit 16)                                        */
39309  #define R_SCI_B0_DCR_DENGT_Msk          (0x1f0000UL)   /*!< DENGT (Bitfield-Mask: 0x1f)                           */
39310 /* =========================================================  XCR0  ========================================================== */
39311  #define R_SCI_B0_XCR0_TCSS_Pos          (0UL)          /*!< TCSS (Bit 0)                                          */
39312  #define R_SCI_B0_XCR0_TCSS_Msk          (0x3UL)        /*!< TCSS (Bitfield-Mask: 0x03)                            */
39313  #define R_SCI_B0_XCR0_BFE_Pos           (8UL)          /*!< BFE (Bit 8)                                           */
39314  #define R_SCI_B0_XCR0_BFE_Msk           (0x100UL)      /*!< BFE (Bitfield-Mask: 0x01)                             */
39315  #define R_SCI_B0_XCR0_CF0RE_Pos         (9UL)          /*!< CF0RE (Bit 9)                                         */
39316  #define R_SCI_B0_XCR0_CF0RE_Msk         (0x200UL)      /*!< CF0RE (Bitfield-Mask: 0x01)                           */
39317  #define R_SCI_B0_XCR0_CF1DS_Pos         (10UL)         /*!< CF1DS (Bit 10)                                        */
39318  #define R_SCI_B0_XCR0_CF1DS_Msk         (0xc00UL)      /*!< CF1DS (Bitfield-Mask: 0x03)                           */
39319  #define R_SCI_B0_XCR0_PIBE_Pos          (12UL)         /*!< PIBE (Bit 12)                                         */
39320  #define R_SCI_B0_XCR0_PIBE_Msk          (0x1000UL)     /*!< PIBE (Bitfield-Mask: 0x01)                            */
39321  #define R_SCI_B0_XCR0_PIBS_Pos          (13UL)         /*!< PIBS (Bit 13)                                         */
39322  #define R_SCI_B0_XCR0_PIBS_Msk          (0xe000UL)     /*!< PIBS (Bitfield-Mask: 0x07)                            */
39323  #define R_SCI_B0_XCR0_BFOIE_Pos         (16UL)         /*!< BFOIE (Bit 16)                                        */
39324  #define R_SCI_B0_XCR0_BFOIE_Msk         (0x10000UL)    /*!< BFOIE (Bitfield-Mask: 0x01)                           */
39325  #define R_SCI_B0_XCR0_BCDIE_Pos         (17UL)         /*!< BCDIE (Bit 17)                                        */
39326  #define R_SCI_B0_XCR0_BCDIE_Msk         (0x20000UL)    /*!< BCDIE (Bitfield-Mask: 0x01)                           */
39327  #define R_SCI_B0_XCR0_BFDIE_Pos         (20UL)         /*!< BFDIE (Bit 20)                                        */
39328  #define R_SCI_B0_XCR0_BFDIE_Msk         (0x100000UL)   /*!< BFDIE (Bitfield-Mask: 0x01)                           */
39329  #define R_SCI_B0_XCR0_COFIE_Pos         (21UL)         /*!< COFIE (Bit 21)                                        */
39330  #define R_SCI_B0_XCR0_COFIE_Msk         (0x200000UL)   /*!< COFIE (Bitfield-Mask: 0x01)                           */
39331  #define R_SCI_B0_XCR0_AEDIE_Pos         (22UL)         /*!< AEDIE (Bit 22)                                        */
39332  #define R_SCI_B0_XCR0_AEDIE_Msk         (0x400000UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
39333  #define R_SCI_B0_XCR0_BCCS_Pos          (24UL)         /*!< BCCS (Bit 24)                                         */
39334  #define R_SCI_B0_XCR0_BCCS_Msk          (0x3000000UL)  /*!< BCCS (Bitfield-Mask: 0x03)                            */
39335 /* =========================================================  XCR1  ========================================================== */
39336  #define R_SCI_B0_XCR1_TCST_Pos          (0UL)          /*!< TCST (Bit 0)                                          */
39337  #define R_SCI_B0_XCR1_TCST_Msk          (0x1UL)        /*!< TCST (Bitfield-Mask: 0x01)                            */
39338  #define R_SCI_B0_XCR1_SDST_Pos          (4UL)          /*!< SDST (Bit 4)                                          */
39339  #define R_SCI_B0_XCR1_SDST_Msk          (0x10UL)       /*!< SDST (Bitfield-Mask: 0x01)                            */
39340  #define R_SCI_B0_XCR1_BMEN_Pos          (5UL)          /*!< BMEN (Bit 5)                                          */
39341  #define R_SCI_B0_XCR1_BMEN_Msk          (0x20UL)       /*!< BMEN (Bitfield-Mask: 0x01)                            */
39342  #define R_SCI_B0_XCR1_PCF1D_Pos         (8UL)          /*!< PCF1D (Bit 8)                                         */
39343  #define R_SCI_B0_XCR1_PCF1D_Msk         (0xff00UL)     /*!< PCF1D (Bitfield-Mask: 0xff)                           */
39344  #define R_SCI_B0_XCR1_SCF1D_Pos         (16UL)         /*!< SCF1D (Bit 16)                                        */
39345  #define R_SCI_B0_XCR1_SCF1D_Msk         (0xff0000UL)   /*!< SCF1D (Bitfield-Mask: 0xff)                           */
39346  #define R_SCI_B0_XCR1_CF1CE_Pos         (24UL)         /*!< CF1CE (Bit 24)                                        */
39347  #define R_SCI_B0_XCR1_CF1CE_Msk         (0xff000000UL) /*!< CF1CE (Bitfield-Mask: 0xff)                           */
39348 /* =========================================================  XCR2  ========================================================== */
39349  #define R_SCI_B0_XCR2_CF0D_Pos          (0UL)          /*!< CF0D (Bit 0)                                          */
39350  #define R_SCI_B0_XCR2_CF0D_Msk          (0xffUL)       /*!< CF0D (Bitfield-Mask: 0xff)                            */
39351  #define R_SCI_B0_XCR2_CF0CE_Pos         (8UL)          /*!< CF0CE (Bit 8)                                         */
39352  #define R_SCI_B0_XCR2_CF0CE_Msk         (0xff00UL)     /*!< CF0CE (Bitfield-Mask: 0xff)                           */
39353  #define R_SCI_B0_XCR2_BFLW_Pos          (16UL)         /*!< BFLW (Bit 16)                                         */
39354  #define R_SCI_B0_XCR2_BFLW_Msk          (0xffff0000UL) /*!< BFLW (Bitfield-Mask: 0xffff)                          */
39355 /* ==========================================================  CSR  ========================================================== */
39356  #define R_SCI_B0_CSR_ERS_Pos            (4UL)          /*!< ERS (Bit 4)                                           */
39357  #define R_SCI_B0_CSR_ERS_Msk            (0x10UL)       /*!< ERS (Bitfield-Mask: 0x01)                             */
39358  #define R_SCI_B0_CSR_RXDMON_Pos         (15UL)         /*!< RXDMON (Bit 15)                                       */
39359  #define R_SCI_B0_CSR_RXDMON_Msk         (0x8000UL)     /*!< RXDMON (Bitfield-Mask: 0x01)                          */
39360  #define R_SCI_B0_CSR_DCMF_Pos           (16UL)         /*!< DCMF (Bit 16)                                         */
39361  #define R_SCI_B0_CSR_DCMF_Msk           (0x10000UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
39362  #define R_SCI_B0_CSR_DPER_Pos           (17UL)         /*!< DPER (Bit 17)                                         */
39363  #define R_SCI_B0_CSR_DPER_Msk           (0x20000UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
39364  #define R_SCI_B0_CSR_DFER_Pos           (18UL)         /*!< DFER (Bit 18)                                         */
39365  #define R_SCI_B0_CSR_DFER_Msk           (0x40000UL)    /*!< DFER (Bitfield-Mask: 0x01)                            */
39366  #define R_SCI_B0_CSR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
39367  #define R_SCI_B0_CSR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
39368  #define R_SCI_B0_CSR_MFF_Pos            (26UL)         /*!< MFF (Bit 26)                                          */
39369  #define R_SCI_B0_CSR_MFF_Msk            (0x4000000UL)  /*!< MFF (Bitfield-Mask: 0x01)                             */
39370  #define R_SCI_B0_CSR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
39371  #define R_SCI_B0_CSR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
39372  #define R_SCI_B0_CSR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
39373  #define R_SCI_B0_CSR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
39374  #define R_SCI_B0_CSR_TDRE_Pos           (29UL)         /*!< TDRE (Bit 29)                                         */
39375  #define R_SCI_B0_CSR_TDRE_Msk           (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
39376  #define R_SCI_B0_CSR_TEND_Pos           (30UL)         /*!< TEND (Bit 30)                                         */
39377  #define R_SCI_B0_CSR_TEND_Msk           (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
39378  #define R_SCI_B0_CSR_RDRF_Pos           (31UL)         /*!< RDRF (Bit 31)                                         */
39379  #define R_SCI_B0_CSR_RDRF_Msk           (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
39380 /* ==========================================================  ISR  ========================================================== */
39381  #define R_SCI_B0_ISR_IICACKR_Pos        (0UL)          /*!< IICACKR (Bit 0)                                       */
39382  #define R_SCI_B0_ISR_IICACKR_Msk        (0x1UL)        /*!< IICACKR (Bitfield-Mask: 0x01)                         */
39383  #define R_SCI_B0_ISR_IICSTIF_Pos        (3UL)          /*!< IICSTIF (Bit 3)                                       */
39384  #define R_SCI_B0_ISR_IICSTIF_Msk        (0x8UL)        /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
39385 /* =========================================================  FRSR  ========================================================== */
39386  #define R_SCI_B0_FRSR_DR_Pos            (0UL)          /*!< DR (Bit 0)                                            */
39387  #define R_SCI_B0_FRSR_DR_Msk            (0x1UL)        /*!< DR (Bitfield-Mask: 0x01)                              */
39388  #define R_SCI_B0_FRSR_R_Pos             (8UL)          /*!< R (Bit 8)                                             */
39389  #define R_SCI_B0_FRSR_R_Msk             (0x3f00UL)     /*!< R (Bitfield-Mask: 0x3f)                               */
39390  #define R_SCI_B0_FRSR_PNUM_Pos          (16UL)         /*!< PNUM (Bit 16)                                         */
39391  #define R_SCI_B0_FRSR_PNUM_Msk          (0x3f0000UL)   /*!< PNUM (Bitfield-Mask: 0x3f)                            */
39392  #define R_SCI_B0_FRSR_FNUM_Pos          (24UL)         /*!< FNUM (Bit 24)                                         */
39393  #define R_SCI_B0_FRSR_FNUM_Msk          (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f)                            */
39394 /* =========================================================  FTSR  ========================================================== */
39395  #define R_SCI_B0_FTSR_T_Pos             (0UL)          /*!< T (Bit 0)                                             */
39396  #define R_SCI_B0_FTSR_T_Msk             (0x3fUL)       /*!< T (Bitfield-Mask: 0x3f)                               */
39397 /* ==========================================================  MSR  ========================================================== */
39398  #define R_SCI_B0_MSR_PFER_Pos           (0UL)          /*!< PFER (Bit 0)                                          */
39399  #define R_SCI_B0_MSR_PFER_Msk           (0x1UL)        /*!< PFER (Bitfield-Mask: 0x01)                            */
39400  #define R_SCI_B0_MSR_SYER_Pos           (1UL)          /*!< SYER (Bit 1)                                          */
39401  #define R_SCI_B0_MSR_SYER_Msk           (0x2UL)        /*!< SYER (Bitfield-Mask: 0x01)                            */
39402  #define R_SCI_B0_MSR_SBER_Pos           (2UL)          /*!< SBER (Bit 2)                                          */
39403  #define R_SCI_B0_MSR_SBER_Msk           (0x4UL)        /*!< SBER (Bitfield-Mask: 0x01)                            */
39404  #define R_SCI_B0_MSR_MER_Pos            (4UL)          /*!< MER (Bit 4)                                           */
39405  #define R_SCI_B0_MSR_MER_Msk            (0x10UL)       /*!< MER (Bitfield-Mask: 0x01)                             */
39406  #define R_SCI_B0_MSR_RSYNC_Pos          (6UL)          /*!< RSYNC (Bit 6)                                         */
39407  #define R_SCI_B0_MSR_RSYNC_Msk          (0x40UL)       /*!< RSYNC (Bitfield-Mask: 0x01)                           */
39408 /* =========================================================  XSR0  ========================================================== */
39409  #define R_SCI_B0_XSR0_SFSF_Pos          (0UL)          /*!< SFSF (Bit 0)                                          */
39410  #define R_SCI_B0_XSR0_SFSF_Msk          (0x1UL)        /*!< SFSF (Bitfield-Mask: 0x01)                            */
39411  #define R_SCI_B0_XSR0_RXDSF_Pos         (1UL)          /*!< RXDSF (Bit 1)                                         */
39412  #define R_SCI_B0_XSR0_RXDSF_Msk         (0x2UL)        /*!< RXDSF (Bitfield-Mask: 0x01)                           */
39413  #define R_SCI_B0_XSR0_BFOF_Pos          (8UL)          /*!< BFOF (Bit 8)                                          */
39414  #define R_SCI_B0_XSR0_BFOF_Msk          (0x100UL)      /*!< BFOF (Bitfield-Mask: 0x01)                            */
39415  #define R_SCI_B0_XSR0_BCDF_Pos          (9UL)          /*!< BCDF (Bit 9)                                          */
39416  #define R_SCI_B0_XSR0_BCDF_Msk          (0x200UL)      /*!< BCDF (Bitfield-Mask: 0x01)                            */
39417  #define R_SCI_B0_XSR0_BFDF_Pos          (10UL)         /*!< BFDF (Bit 10)                                         */
39418  #define R_SCI_B0_XSR0_BFDF_Msk          (0x400UL)      /*!< BFDF (Bitfield-Mask: 0x01)                            */
39419  #define R_SCI_B0_XSR0_CF0MF_Pos         (11UL)         /*!< CF0MF (Bit 11)                                        */
39420  #define R_SCI_B0_XSR0_CF0MF_Msk         (0x800UL)      /*!< CF0MF (Bitfield-Mask: 0x01)                           */
39421  #define R_SCI_B0_XSR0_CF1MF_Pos         (12UL)         /*!< CF1MF (Bit 12)                                        */
39422  #define R_SCI_B0_XSR0_CF1MF_Msk         (0x1000UL)     /*!< CF1MF (Bitfield-Mask: 0x01)                           */
39423  #define R_SCI_B0_XSR0_PIBDF_Pos         (13UL)         /*!< PIBDF (Bit 13)                                        */
39424  #define R_SCI_B0_XSR0_PIBDF_Msk         (0x2000UL)     /*!< PIBDF (Bitfield-Mask: 0x01)                           */
39425  #define R_SCI_B0_XSR0_COF_Pos           (14UL)         /*!< COF (Bit 14)                                          */
39426  #define R_SCI_B0_XSR0_COF_Msk           (0x4000UL)     /*!< COF (Bitfield-Mask: 0x01)                             */
39427  #define R_SCI_B0_XSR0_AEDF_Pos          (15UL)         /*!< AEDF (Bit 15)                                         */
39428  #define R_SCI_B0_XSR0_AEDF_Msk          (0x8000UL)     /*!< AEDF (Bitfield-Mask: 0x01)                            */
39429  #define R_SCI_B0_XSR0_CF0RD_Pos         (16UL)         /*!< CF0RD (Bit 16)                                        */
39430  #define R_SCI_B0_XSR0_CF0RD_Msk         (0xff0000UL)   /*!< CF0RD (Bitfield-Mask: 0xff)                           */
39431  #define R_SCI_B0_XSR0_CF1RD_Pos         (24UL)         /*!< CF1RD (Bit 24)                                        */
39432  #define R_SCI_B0_XSR0_CF1RD_Msk         (0xff000000UL) /*!< CF1RD (Bitfield-Mask: 0xff)                           */
39433 /* =========================================================  XSR1  ========================================================== */
39434  #define R_SCI_B0_XSR1_TCNT_Pos          (0UL)          /*!< TCNT (Bit 0)                                          */
39435  #define R_SCI_B0_XSR1_TCNT_Msk          (0xffffUL)     /*!< TCNT (Bitfield-Mask: 0xffff)                          */
39436 /* =========================================================  CFCLR  ========================================================= */
39437  #define R_SCI_B0_CFCLR_ERSC_Pos         (4UL)          /*!< ERSC (Bit 4)                                          */
39438  #define R_SCI_B0_CFCLR_ERSC_Msk         (0x10UL)       /*!< ERSC (Bitfield-Mask: 0x01)                            */
39439  #define R_SCI_B0_CFCLR_DCMFC_Pos        (16UL)         /*!< DCMFC (Bit 16)                                        */
39440  #define R_SCI_B0_CFCLR_DCMFC_Msk        (0x10000UL)    /*!< DCMFC (Bitfield-Mask: 0x01)                           */
39441  #define R_SCI_B0_CFCLR_DPERC_Pos        (17UL)         /*!< DPERC (Bit 17)                                        */
39442  #define R_SCI_B0_CFCLR_DPERC_Msk        (0x20000UL)    /*!< DPERC (Bitfield-Mask: 0x01)                           */
39443  #define R_SCI_B0_CFCLR_DFERC_Pos        (18UL)         /*!< DFERC (Bit 18)                                        */
39444  #define R_SCI_B0_CFCLR_DFERC_Msk        (0x40000UL)    /*!< DFERC (Bitfield-Mask: 0x01)                           */
39445  #define R_SCI_B0_CFCLR_ORERC_Pos        (24UL)         /*!< ORERC (Bit 24)                                        */
39446  #define R_SCI_B0_CFCLR_ORERC_Msk        (0x1000000UL)  /*!< ORERC (Bitfield-Mask: 0x01)                           */
39447  #define R_SCI_B0_CFCLR_MFFC_Pos         (26UL)         /*!< MFFC (Bit 26)                                         */
39448  #define R_SCI_B0_CFCLR_MFFC_Msk         (0x4000000UL)  /*!< MFFC (Bitfield-Mask: 0x01)                            */
39449  #define R_SCI_B0_CFCLR_PERC_Pos         (27UL)         /*!< PERC (Bit 27)                                         */
39450  #define R_SCI_B0_CFCLR_PERC_Msk         (0x8000000UL)  /*!< PERC (Bitfield-Mask: 0x01)                            */
39451  #define R_SCI_B0_CFCLR_FERC_Pos         (28UL)         /*!< FERC (Bit 28)                                         */
39452  #define R_SCI_B0_CFCLR_FERC_Msk         (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01)                            */
39453  #define R_SCI_B0_CFCLR_TDREC_Pos        (29UL)         /*!< TDREC (Bit 29)                                        */
39454  #define R_SCI_B0_CFCLR_TDREC_Msk        (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01)                           */
39455  #define R_SCI_B0_CFCLR_RDRFC_Pos        (31UL)         /*!< RDRFC (Bit 31)                                        */
39456  #define R_SCI_B0_CFCLR_RDRFC_Msk        (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01)                           */
39457 /* ========================================================  ICFCLR  ========================================================= */
39458  #define R_SCI_B0_ICFCLR_IICSTIFC_Pos    (3UL)          /*!< IICSTIFC (Bit 3)                                      */
39459  #define R_SCI_B0_ICFCLR_IICSTIFC_Msk    (0x8UL)        /*!< IICSTIFC (Bitfield-Mask: 0x01)                        */
39460 /* =========================================================  FFCLR  ========================================================= */
39461  #define R_SCI_B0_FFCLR_DRC_Pos          (0UL)          /*!< DRC (Bit 0)                                           */
39462  #define R_SCI_B0_FFCLR_DRC_Msk          (0x1UL)        /*!< DRC (Bitfield-Mask: 0x01)                             */
39463 /* =========================================================  MFCLR  ========================================================= */
39464  #define R_SCI_B0_MFCLR_PFERC_Pos        (0UL)          /*!< PFERC (Bit 0)                                         */
39465  #define R_SCI_B0_MFCLR_PFERC_Msk        (0x1UL)        /*!< PFERC (Bitfield-Mask: 0x01)                           */
39466  #define R_SCI_B0_MFCLR_SYERC_Pos        (1UL)          /*!< SYERC (Bit 1)                                         */
39467  #define R_SCI_B0_MFCLR_SYERC_Msk        (0x2UL)        /*!< SYERC (Bitfield-Mask: 0x01)                           */
39468  #define R_SCI_B0_MFCLR_SBERC_Pos        (2UL)          /*!< SBERC (Bit 2)                                         */
39469  #define R_SCI_B0_MFCLR_SBERC_Msk        (0x4UL)        /*!< SBERC (Bitfield-Mask: 0x01)                           */
39470  #define R_SCI_B0_MFCLR_MERC_Pos         (4UL)          /*!< MERC (Bit 4)                                          */
39471  #define R_SCI_B0_MFCLR_MERC_Msk         (0x10UL)       /*!< MERC (Bitfield-Mask: 0x01)                            */
39472 /* =========================================================  XFCLR  ========================================================= */
39473  #define R_SCI_B0_XFCLR_BFOC_Pos         (8UL)          /*!< BFOC (Bit 8)                                          */
39474  #define R_SCI_B0_XFCLR_BFOC_Msk         (0x100UL)      /*!< BFOC (Bitfield-Mask: 0x01)                            */
39475  #define R_SCI_B0_XFCLR_BCDC_Pos         (9UL)          /*!< BCDC (Bit 9)                                          */
39476  #define R_SCI_B0_XFCLR_BCDC_Msk         (0x200UL)      /*!< BCDC (Bitfield-Mask: 0x01)                            */
39477  #define R_SCI_B0_XFCLR_BFDC_Pos         (10UL)         /*!< BFDC (Bit 10)                                         */
39478  #define R_SCI_B0_XFCLR_BFDC_Msk         (0x400UL)      /*!< BFDC (Bitfield-Mask: 0x01)                            */
39479  #define R_SCI_B0_XFCLR_CF0MC_Pos        (11UL)         /*!< CF0MC (Bit 11)                                        */
39480  #define R_SCI_B0_XFCLR_CF0MC_Msk        (0x800UL)      /*!< CF0MC (Bitfield-Mask: 0x01)                           */
39481  #define R_SCI_B0_XFCLR_CF1MC_Pos        (12UL)         /*!< CF1MC (Bit 12)                                        */
39482  #define R_SCI_B0_XFCLR_CF1MC_Msk        (0x1000UL)     /*!< CF1MC (Bitfield-Mask: 0x01)                           */
39483  #define R_SCI_B0_XFCLR_PIBDC_Pos        (13UL)         /*!< PIBDC (Bit 13)                                        */
39484  #define R_SCI_B0_XFCLR_PIBDC_Msk        (0x2000UL)     /*!< PIBDC (Bitfield-Mask: 0x01)                           */
39485  #define R_SCI_B0_XFCLR_COFC_Pos         (14UL)         /*!< COFC (Bit 14)                                         */
39486  #define R_SCI_B0_XFCLR_COFC_Msk         (0x4000UL)     /*!< COFC (Bitfield-Mask: 0x01)                            */
39487  #define R_SCI_B0_XFCLR_AEDC_Pos         (15UL)         /*!< AEDC (Bit 15)                                         */
39488  #define R_SCI_B0_XFCLR_AEDC_Msk         (0x8000UL)     /*!< AEDC (Bitfield-Mask: 0x01)                            */
39489 
39490 /* =========================================================================================================================== */
39491 /* ================                                         R_SPI_B0                                          ================ */
39492 /* =========================================================================================================================== */
39493 
39494 /* =========================================================  SPDR  ========================================================== */
39495 /* ========================================================  SPDECR  ========================================================= */
39496  #define R_SPI_B0_SPDECR_SCKDL_Pos     (0UL)          /*!< SCKDL (Bit 0)                                         */
39497  #define R_SPI_B0_SPDECR_SCKDL_Msk     (0x7UL)        /*!< SCKDL (Bitfield-Mask: 0x07)                           */
39498  #define R_SPI_B0_SPDECR_SLNDL_Pos     (8UL)          /*!< SLNDL (Bit 8)                                         */
39499  #define R_SPI_B0_SPDECR_SLNDL_Msk     (0x700UL)      /*!< SLNDL (Bitfield-Mask: 0x07)                           */
39500  #define R_SPI_B0_SPDECR_SPNDL_Pos     (16UL)         /*!< SPNDL (Bit 16)                                        */
39501  #define R_SPI_B0_SPDECR_SPNDL_Msk     (0x70000UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
39502  #define R_SPI_B0_SPDECR_ARST_Pos      (24UL)         /*!< ARST (Bit 24)                                         */
39503  #define R_SPI_B0_SPDECR_ARST_Msk      (0x7000000UL)  /*!< ARST (Bitfield-Mask: 0x07)                            */
39504 /* =========================================================  SPCR  ========================================================== */
39505  #define R_SPI_B0_SPCR_SPE_Pos         (0UL)          /*!< SPE (Bit 0)                                           */
39506  #define R_SPI_B0_SPCR_SPE_Msk         (0x1UL)        /*!< SPE (Bitfield-Mask: 0x01)                             */
39507  #define R_SPI_B0_SPCR_SPSCKSEL_Pos    (7UL)          /*!< SPSCKSEL (Bit 7)                                      */
39508  #define R_SPI_B0_SPCR_SPSCKSEL_Msk    (0x80UL)       /*!< SPSCKSEL (Bitfield-Mask: 0x01)                        */
39509  #define R_SPI_B0_SPCR_SPPE_Pos        (8UL)          /*!< SPPE (Bit 8)                                          */
39510  #define R_SPI_B0_SPCR_SPPE_Msk        (0x100UL)      /*!< SPPE (Bitfield-Mask: 0x01)                            */
39511  #define R_SPI_B0_SPCR_SPOE_Pos        (9UL)          /*!< SPOE (Bit 9)                                          */
39512  #define R_SPI_B0_SPCR_SPOE_Msk        (0x200UL)      /*!< SPOE (Bitfield-Mask: 0x01)                            */
39513  #define R_SPI_B0_SPCR_PTE_Pos         (11UL)         /*!< PTE (Bit 11)                                          */
39514  #define R_SPI_B0_SPCR_PTE_Msk         (0x800UL)      /*!< PTE (Bitfield-Mask: 0x01)                             */
39515  #define R_SPI_B0_SPCR_SCKASE_Pos      (12UL)         /*!< SCKASE (Bit 12)                                       */
39516  #define R_SPI_B0_SPCR_SCKASE_Msk      (0x1000UL)     /*!< SCKASE (Bitfield-Mask: 0x01)                          */
39517  #define R_SPI_B0_SPCR_BFDS_Pos        (13UL)         /*!< BFDS (Bit 13)                                         */
39518  #define R_SPI_B0_SPCR_BFDS_Msk        (0x2000UL)     /*!< BFDS (Bitfield-Mask: 0x01)                            */
39519  #define R_SPI_B0_SPCR_MODFEN_Pos      (14UL)         /*!< MODFEN (Bit 14)                                       */
39520  #define R_SPI_B0_SPCR_MODFEN_Msk      (0x4000UL)     /*!< MODFEN (Bitfield-Mask: 0x01)                          */
39521  #define R_SPI_B0_SPCR_SPEIE_Pos       (16UL)         /*!< SPEIE (Bit 16)                                        */
39522  #define R_SPI_B0_SPCR_SPEIE_Msk       (0x10000UL)    /*!< SPEIE (Bitfield-Mask: 0x01)                           */
39523  #define R_SPI_B0_SPCR_SPRIE_Pos       (17UL)         /*!< SPRIE (Bit 17)                                        */
39524  #define R_SPI_B0_SPCR_SPRIE_Msk       (0x20000UL)    /*!< SPRIE (Bitfield-Mask: 0x01)                           */
39525  #define R_SPI_B0_SPCR_SPIIE_Pos       (18UL)         /*!< SPIIE (Bit 18)                                        */
39526  #define R_SPI_B0_SPCR_SPIIE_Msk       (0x40000UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
39527  #define R_SPI_B0_SPCR_SPDRES_Pos      (19UL)         /*!< SPDRES (Bit 19)                                       */
39528  #define R_SPI_B0_SPCR_SPDRES_Msk      (0x80000UL)    /*!< SPDRES (Bitfield-Mask: 0x01)                          */
39529  #define R_SPI_B0_SPCR_SPTIE_Pos       (20UL)         /*!< SPTIE (Bit 20)                                        */
39530  #define R_SPI_B0_SPCR_SPTIE_Msk       (0x100000UL)   /*!< SPTIE (Bitfield-Mask: 0x01)                           */
39531  #define R_SPI_B0_SPCR_CENDIE_Pos      (21UL)         /*!< CENDIE (Bit 21)                                       */
39532  #define R_SPI_B0_SPCR_CENDIE_Msk      (0x200000UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
39533  #define R_SPI_B0_SPCR_SPMS_Pos        (24UL)         /*!< SPMS (Bit 24)                                         */
39534  #define R_SPI_B0_SPCR_SPMS_Msk        (0x1000000UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
39535  #define R_SPI_B0_SPCR_SPFRF_Pos       (25UL)         /*!< SPFRF (Bit 25)                                        */
39536  #define R_SPI_B0_SPCR_SPFRF_Msk       (0x2000000UL)  /*!< SPFRF (Bitfield-Mask: 0x01)                           */
39537  #define R_SPI_B0_SPCR_TXMD_Pos        (28UL)         /*!< TXMD (Bit 28)                                         */
39538  #define R_SPI_B0_SPCR_TXMD_Msk        (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03)                            */
39539  #define R_SPI_B0_SPCR_MSTR_Pos        (30UL)         /*!< MSTR (Bit 30)                                         */
39540  #define R_SPI_B0_SPCR_MSTR_Msk        (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01)                            */
39541  #define R_SPI_B0_SPCR_BPEN_Pos        (31UL)         /*!< BPEN (Bit 31)                                         */
39542  #define R_SPI_B0_SPCR_BPEN_Msk        (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01)                            */
39543 /* =========================================================  SPCR2  ========================================================= */
39544  #define R_SPI_B0_SPCR2_RMFM_Pos       (0UL)          /*!< RMFM (Bit 0)                                          */
39545  #define R_SPI_B0_SPCR2_RMFM_Msk       (0x1fUL)       /*!< RMFM (Bitfield-Mask: 0x1f)                            */
39546  #define R_SPI_B0_SPCR2_RMEDTG_Pos     (6UL)          /*!< RMEDTG (Bit 6)                                        */
39547  #define R_SPI_B0_SPCR2_RMEDTG_Msk     (0x40UL)       /*!< RMEDTG (Bitfield-Mask: 0x01)                          */
39548  #define R_SPI_B0_SPCR2_RMSTTG_Pos     (7UL)          /*!< RMSTTG (Bit 7)                                        */
39549  #define R_SPI_B0_SPCR2_RMSTTG_Msk     (0x80UL)       /*!< RMSTTG (Bitfield-Mask: 0x01)                          */
39550  #define R_SPI_B0_SPCR2_SPDRC_Pos      (8UL)          /*!< SPDRC (Bit 8)                                         */
39551  #define R_SPI_B0_SPCR2_SPDRC_Msk      (0xff00UL)     /*!< SPDRC (Bitfield-Mask: 0xff)                           */
39552  #define R_SPI_B0_SPCR2_SPLP_Pos       (16UL)         /*!< SPLP (Bit 16)                                         */
39553  #define R_SPI_B0_SPCR2_SPLP_Msk       (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
39554  #define R_SPI_B0_SPCR2_SPLP2_Pos      (17UL)         /*!< SPLP2 (Bit 17)                                        */
39555  #define R_SPI_B0_SPCR2_SPLP2_Msk      (0x20000UL)    /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
39556  #define R_SPI_B0_SPCR2_MOIFV_Pos      (20UL)         /*!< MOIFV (Bit 20)                                        */
39557  #define R_SPI_B0_SPCR2_MOIFV_Msk      (0x100000UL)   /*!< MOIFV (Bitfield-Mask: 0x01)                           */
39558  #define R_SPI_B0_SPCR2_MOIFE_Pos      (21UL)         /*!< MOIFE (Bit 21)                                        */
39559  #define R_SPI_B0_SPCR2_MOIFE_Msk      (0x200000UL)   /*!< MOIFE (Bitfield-Mask: 0x01)                           */
39560 /* =========================================================  SPCR3  ========================================================= */
39561  #define R_SPI_B0_SPCR3_SSL0P_Pos      (0UL)          /*!< SSL0P (Bit 0)                                         */
39562  #define R_SPI_B0_SPCR3_SSL0P_Msk      (0x1UL)        /*!< SSL0P (Bitfield-Mask: 0x01)                           */
39563  #define R_SPI_B0_SPCR3_SSL1P_Pos      (1UL)          /*!< SSL1P (Bit 1)                                         */
39564  #define R_SPI_B0_SPCR3_SSL1P_Msk      (0x2UL)        /*!< SSL1P (Bitfield-Mask: 0x01)                           */
39565  #define R_SPI_B0_SPCR3_SSL2P_Pos      (2UL)          /*!< SSL2P (Bit 2)                                         */
39566  #define R_SPI_B0_SPCR3_SSL2P_Msk      (0x4UL)        /*!< SSL2P (Bitfield-Mask: 0x01)                           */
39567  #define R_SPI_B0_SPCR3_SSL3P_Pos      (3UL)          /*!< SSL3P (Bit 3)                                         */
39568  #define R_SPI_B0_SPCR3_SSL3P_Msk      (0x8UL)        /*!< SSL3P (Bitfield-Mask: 0x01)                           */
39569  #define R_SPI_B0_SPCR3_SPBR_Pos       (8UL)          /*!< SPBR (Bit 8)                                          */
39570  #define R_SPI_B0_SPCR3_SPBR_Msk       (0xff00UL)     /*!< SPBR (Bitfield-Mask: 0xff)                            */
39571  #define R_SPI_B0_SPCR3_SPSLN_Pos      (24UL)         /*!< SPSLN (Bit 24)                                        */
39572  #define R_SPI_B0_SPCR3_SPSLN_Msk      (0x7000000UL)  /*!< SPSLN (Bitfield-Mask: 0x07)                           */
39573 /* ========================================================  SPCMD0  ========================================================= */
39574  #define R_SPI_B0_SPCMD0_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
39575  #define R_SPI_B0_SPCMD0_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39576  #define R_SPI_B0_SPCMD0_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
39577  #define R_SPI_B0_SPCMD0_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39578  #define R_SPI_B0_SPCMD0_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
39579  #define R_SPI_B0_SPCMD0_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
39580  #define R_SPI_B0_SPCMD0_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
39581  #define R_SPI_B0_SPCMD0_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
39582  #define R_SPI_B0_SPCMD0_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
39583  #define R_SPI_B0_SPCMD0_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39584  #define R_SPI_B0_SPCMD0_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
39585  #define R_SPI_B0_SPCMD0_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
39586  #define R_SPI_B0_SPCMD0_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
39587  #define R_SPI_B0_SPCMD0_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
39588  #define R_SPI_B0_SPCMD0_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
39589  #define R_SPI_B0_SPCMD0_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
39590  #define R_SPI_B0_SPCMD0_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
39591  #define R_SPI_B0_SPCMD0_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
39592  #define R_SPI_B0_SPCMD0_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
39593  #define R_SPI_B0_SPCMD0_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
39594 /* ========================================================  SPCMD1  ========================================================= */
39595  #define R_SPI_B0_SPCMD1_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
39596  #define R_SPI_B0_SPCMD1_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39597  #define R_SPI_B0_SPCMD1_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
39598  #define R_SPI_B0_SPCMD1_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39599  #define R_SPI_B0_SPCMD1_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
39600  #define R_SPI_B0_SPCMD1_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
39601  #define R_SPI_B0_SPCMD1_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
39602  #define R_SPI_B0_SPCMD1_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
39603  #define R_SPI_B0_SPCMD1_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
39604  #define R_SPI_B0_SPCMD1_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39605  #define R_SPI_B0_SPCMD1_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
39606  #define R_SPI_B0_SPCMD1_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
39607  #define R_SPI_B0_SPCMD1_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
39608  #define R_SPI_B0_SPCMD1_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
39609  #define R_SPI_B0_SPCMD1_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
39610  #define R_SPI_B0_SPCMD1_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
39611  #define R_SPI_B0_SPCMD1_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
39612  #define R_SPI_B0_SPCMD1_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
39613  #define R_SPI_B0_SPCMD1_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
39614  #define R_SPI_B0_SPCMD1_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
39615 /* ========================================================  SPCMD2  ========================================================= */
39616  #define R_SPI_B0_SPCMD2_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
39617  #define R_SPI_B0_SPCMD2_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39618  #define R_SPI_B0_SPCMD2_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
39619  #define R_SPI_B0_SPCMD2_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39620  #define R_SPI_B0_SPCMD2_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
39621  #define R_SPI_B0_SPCMD2_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
39622  #define R_SPI_B0_SPCMD2_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
39623  #define R_SPI_B0_SPCMD2_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
39624  #define R_SPI_B0_SPCMD2_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
39625  #define R_SPI_B0_SPCMD2_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39626  #define R_SPI_B0_SPCMD2_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
39627  #define R_SPI_B0_SPCMD2_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
39628  #define R_SPI_B0_SPCMD2_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
39629  #define R_SPI_B0_SPCMD2_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
39630  #define R_SPI_B0_SPCMD2_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
39631  #define R_SPI_B0_SPCMD2_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
39632  #define R_SPI_B0_SPCMD2_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
39633  #define R_SPI_B0_SPCMD2_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
39634  #define R_SPI_B0_SPCMD2_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
39635  #define R_SPI_B0_SPCMD2_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
39636 /* ========================================================  SPCMD3  ========================================================= */
39637  #define R_SPI_B0_SPCMD3_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
39638  #define R_SPI_B0_SPCMD3_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39639  #define R_SPI_B0_SPCMD3_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
39640  #define R_SPI_B0_SPCMD3_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39641  #define R_SPI_B0_SPCMD3_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
39642  #define R_SPI_B0_SPCMD3_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
39643  #define R_SPI_B0_SPCMD3_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
39644  #define R_SPI_B0_SPCMD3_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
39645  #define R_SPI_B0_SPCMD3_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
39646  #define R_SPI_B0_SPCMD3_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39647  #define R_SPI_B0_SPCMD3_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
39648  #define R_SPI_B0_SPCMD3_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
39649  #define R_SPI_B0_SPCMD3_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
39650  #define R_SPI_B0_SPCMD3_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
39651  #define R_SPI_B0_SPCMD3_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
39652  #define R_SPI_B0_SPCMD3_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
39653  #define R_SPI_B0_SPCMD3_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
39654  #define R_SPI_B0_SPCMD3_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
39655  #define R_SPI_B0_SPCMD3_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
39656  #define R_SPI_B0_SPCMD3_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
39657 /* ========================================================  SPCMD4  ========================================================= */
39658  #define R_SPI_B0_SPCMD4_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
39659  #define R_SPI_B0_SPCMD4_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39660  #define R_SPI_B0_SPCMD4_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
39661  #define R_SPI_B0_SPCMD4_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39662  #define R_SPI_B0_SPCMD4_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
39663  #define R_SPI_B0_SPCMD4_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
39664  #define R_SPI_B0_SPCMD4_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
39665  #define R_SPI_B0_SPCMD4_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
39666  #define R_SPI_B0_SPCMD4_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
39667  #define R_SPI_B0_SPCMD4_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39668  #define R_SPI_B0_SPCMD4_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
39669  #define R_SPI_B0_SPCMD4_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
39670  #define R_SPI_B0_SPCMD4_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
39671  #define R_SPI_B0_SPCMD4_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
39672  #define R_SPI_B0_SPCMD4_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
39673  #define R_SPI_B0_SPCMD4_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
39674  #define R_SPI_B0_SPCMD4_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
39675  #define R_SPI_B0_SPCMD4_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
39676  #define R_SPI_B0_SPCMD4_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
39677  #define R_SPI_B0_SPCMD4_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
39678 /* ========================================================  SPCMD5  ========================================================= */
39679  #define R_SPI_B0_SPCMD5_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
39680  #define R_SPI_B0_SPCMD5_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39681  #define R_SPI_B0_SPCMD5_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
39682  #define R_SPI_B0_SPCMD5_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39683  #define R_SPI_B0_SPCMD5_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
39684  #define R_SPI_B0_SPCMD5_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
39685  #define R_SPI_B0_SPCMD5_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
39686  #define R_SPI_B0_SPCMD5_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
39687  #define R_SPI_B0_SPCMD5_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
39688  #define R_SPI_B0_SPCMD5_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39689  #define R_SPI_B0_SPCMD5_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
39690  #define R_SPI_B0_SPCMD5_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
39691  #define R_SPI_B0_SPCMD5_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
39692  #define R_SPI_B0_SPCMD5_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
39693  #define R_SPI_B0_SPCMD5_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
39694  #define R_SPI_B0_SPCMD5_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
39695  #define R_SPI_B0_SPCMD5_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
39696  #define R_SPI_B0_SPCMD5_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
39697  #define R_SPI_B0_SPCMD5_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
39698  #define R_SPI_B0_SPCMD5_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
39699 /* ========================================================  SPCMD6  ========================================================= */
39700  #define R_SPI_B0_SPCMD6_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
39701  #define R_SPI_B0_SPCMD6_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39702  #define R_SPI_B0_SPCMD6_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
39703  #define R_SPI_B0_SPCMD6_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39704  #define R_SPI_B0_SPCMD6_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
39705  #define R_SPI_B0_SPCMD6_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
39706  #define R_SPI_B0_SPCMD6_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
39707  #define R_SPI_B0_SPCMD6_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
39708  #define R_SPI_B0_SPCMD6_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
39709  #define R_SPI_B0_SPCMD6_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39710  #define R_SPI_B0_SPCMD6_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
39711  #define R_SPI_B0_SPCMD6_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
39712  #define R_SPI_B0_SPCMD6_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
39713  #define R_SPI_B0_SPCMD6_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
39714  #define R_SPI_B0_SPCMD6_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
39715  #define R_SPI_B0_SPCMD6_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
39716  #define R_SPI_B0_SPCMD6_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
39717  #define R_SPI_B0_SPCMD6_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
39718  #define R_SPI_B0_SPCMD6_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
39719  #define R_SPI_B0_SPCMD6_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
39720 /* ========================================================  SPCMD7  ========================================================= */
39721  #define R_SPI_B0_SPCMD7_CPHA_Pos      (0UL)          /*!< CPHA (Bit 0)                                          */
39722  #define R_SPI_B0_SPCMD7_CPHA_Msk      (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
39723  #define R_SPI_B0_SPCMD7_CPOL_Pos      (1UL)          /*!< CPOL (Bit 1)                                          */
39724  #define R_SPI_B0_SPCMD7_CPOL_Msk      (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
39725  #define R_SPI_B0_SPCMD7_BRDV_Pos      (2UL)          /*!< BRDV (Bit 2)                                          */
39726  #define R_SPI_B0_SPCMD7_BRDV_Msk      (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
39727  #define R_SPI_B0_SPCMD7_SSLKP_Pos     (7UL)          /*!< SSLKP (Bit 7)                                         */
39728  #define R_SPI_B0_SPCMD7_SSLKP_Msk     (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
39729  #define R_SPI_B0_SPCMD7_LSBF_Pos      (12UL)         /*!< LSBF (Bit 12)                                         */
39730  #define R_SPI_B0_SPCMD7_LSBF_Msk      (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
39731  #define R_SPI_B0_SPCMD7_SPNDEN_Pos    (13UL)         /*!< SPNDEN (Bit 13)                                       */
39732  #define R_SPI_B0_SPCMD7_SPNDEN_Msk    (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
39733  #define R_SPI_B0_SPCMD7_SLNDEN_Pos    (14UL)         /*!< SLNDEN (Bit 14)                                       */
39734  #define R_SPI_B0_SPCMD7_SLNDEN_Msk    (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
39735  #define R_SPI_B0_SPCMD7_SCKDEN_Pos    (15UL)         /*!< SCKDEN (Bit 15)                                       */
39736  #define R_SPI_B0_SPCMD7_SCKDEN_Msk    (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
39737  #define R_SPI_B0_SPCMD7_SPB_Pos       (16UL)         /*!< SPB (Bit 16)                                          */
39738  #define R_SPI_B0_SPCMD7_SPB_Msk       (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
39739  #define R_SPI_B0_SPCMD7_SSLA_Pos      (24UL)         /*!< SSLA (Bit 24)                                         */
39740  #define R_SPI_B0_SPCMD7_SSLA_Msk      (0x7000000UL)  /*!< SSLA (Bitfield-Mask: 0x07)                            */
39741 /* =========================================================  SPDCR  ========================================================= */
39742  #define R_SPI_B0_SPDCR_BYSW_Pos       (0UL)          /*!< BYSW (Bit 0)                                          */
39743  #define R_SPI_B0_SPDCR_BYSW_Msk       (0x1UL)        /*!< BYSW (Bitfield-Mask: 0x01)                            */
39744  #define R_SPI_B0_SPDCR_SPRDTD_Pos     (3UL)          /*!< SPRDTD (Bit 3)                                        */
39745  #define R_SPI_B0_SPDCR_SPRDTD_Msk     (0x8UL)        /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
39746  #define R_SPI_B0_SPDCR_SINV_Pos       (4UL)          /*!< SINV (Bit 4)                                          */
39747  #define R_SPI_B0_SPDCR_SINV_Msk       (0x10UL)       /*!< SINV (Bitfield-Mask: 0x01)                            */
39748  #define R_SPI_B0_SPDCR_SPFC_Pos       (8UL)          /*!< SPFC (Bit 8)                                          */
39749  #define R_SPI_B0_SPDCR_SPFC_Msk       (0x300UL)      /*!< SPFC (Bitfield-Mask: 0x03)                            */
39750 /* ========================================================  SPDCR2  ========================================================= */
39751  #define R_SPI_B0_SPDCR2_RTRG_Pos      (0UL)          /*!< RTRG (Bit 0)                                          */
39752  #define R_SPI_B0_SPDCR2_RTRG_Msk      (0x3UL)        /*!< RTRG (Bitfield-Mask: 0x03)                            */
39753  #define R_SPI_B0_SPDCR2_TTRG_Pos      (8UL)          /*!< TTRG (Bit 8)                                          */
39754  #define R_SPI_B0_SPDCR2_TTRG_Msk      (0x300UL)      /*!< TTRG (Bitfield-Mask: 0x03)                            */
39755 /* =========================================================  SPSR  ========================================================== */
39756  #define R_SPI_B0_SPSR_SPCP_Pos        (8UL)          /*!< SPCP (Bit 8)                                          */
39757  #define R_SPI_B0_SPSR_SPCP_Msk        (0x700UL)      /*!< SPCP (Bitfield-Mask: 0x07)                            */
39758  #define R_SPI_B0_SPSR_SPECM_Pos       (12UL)         /*!< SPECM (Bit 12)                                        */
39759  #define R_SPI_B0_SPSR_SPECM_Msk       (0x7000UL)     /*!< SPECM (Bitfield-Mask: 0x07)                           */
39760  #define R_SPI_B0_SPSR_SPDRF_Pos       (23UL)         /*!< SPDRF (Bit 23)                                        */
39761  #define R_SPI_B0_SPSR_SPDRF_Msk       (0x800000UL)   /*!< SPDRF (Bitfield-Mask: 0x01)                           */
39762  #define R_SPI_B0_SPSR_OVRF_Pos        (24UL)         /*!< OVRF (Bit 24)                                         */
39763  #define R_SPI_B0_SPSR_OVRF_Msk        (0x1000000UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
39764  #define R_SPI_B0_SPSR_IDLNF_Pos       (25UL)         /*!< IDLNF (Bit 25)                                        */
39765  #define R_SPI_B0_SPSR_IDLNF_Msk       (0x2000000UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
39766  #define R_SPI_B0_SPSR_MODF_Pos        (26UL)         /*!< MODF (Bit 26)                                         */
39767  #define R_SPI_B0_SPSR_MODF_Msk        (0x4000000UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
39768  #define R_SPI_B0_SPSR_PERF_Pos        (27UL)         /*!< PERF (Bit 27)                                         */
39769  #define R_SPI_B0_SPSR_PERF_Msk        (0x8000000UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
39770  #define R_SPI_B0_SPSR_UDRF_Pos        (28UL)         /*!< UDRF (Bit 28)                                         */
39771  #define R_SPI_B0_SPSR_UDRF_Msk        (0x10000000UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
39772  #define R_SPI_B0_SPSR_SPTEF_Pos       (29UL)         /*!< SPTEF (Bit 29)                                        */
39773  #define R_SPI_B0_SPSR_SPTEF_Msk       (0x20000000UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
39774  #define R_SPI_B0_SPSR_CENDF_Pos       (30UL)         /*!< CENDF (Bit 30)                                        */
39775  #define R_SPI_B0_SPSR_CENDF_Msk       (0x40000000UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
39776  #define R_SPI_B0_SPSR_SPRF_Pos        (31UL)         /*!< SPRF (Bit 31)                                         */
39777  #define R_SPI_B0_SPSR_SPRF_Msk        (0x80000000UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
39778 /* ========================================================  SPTFSR  ========================================================= */
39779  #define R_SPI_B0_SPTFSR_TFDN_Pos      (0UL)          /*!< TFDN (Bit 0)                                          */
39780  #define R_SPI_B0_SPTFSR_TFDN_Msk      (0x7UL)        /*!< TFDN (Bitfield-Mask: 0x07)                            */
39781 /* ========================================================  SPRFSR  ========================================================= */
39782  #define R_SPI_B0_SPRFSR_RFDN_Pos      (0UL)          /*!< RFDN (Bit 0)                                          */
39783  #define R_SPI_B0_SPRFSR_RFDN_Msk      (0x7UL)        /*!< RFDN (Bitfield-Mask: 0x07)                            */
39784 /* =========================================================  SPPSR  ========================================================= */
39785  #define R_SPI_B0_SPPSR_SPEPS_Pos      (0UL)          /*!< SPEPS (Bit 0)                                         */
39786  #define R_SPI_B0_SPPSR_SPEPS_Msk      (0x1UL)        /*!< SPEPS (Bitfield-Mask: 0x01)                           */
39787 /* =========================================================  SPSRC  ========================================================= */
39788  #define R_SPI_B0_SPSRC_SPDRFC_Pos     (23UL)         /*!< SPDRFC (Bit 23)                                       */
39789  #define R_SPI_B0_SPSRC_SPDRFC_Msk     (0x800000UL)   /*!< SPDRFC (Bitfield-Mask: 0x01)                          */
39790  #define R_SPI_B0_SPSRC_OVRFC_Pos      (24UL)         /*!< OVRFC (Bit 24)                                        */
39791  #define R_SPI_B0_SPSRC_OVRFC_Msk      (0x1000000UL)  /*!< OVRFC (Bitfield-Mask: 0x01)                           */
39792  #define R_SPI_B0_SPSRC_MODFC_Pos      (26UL)         /*!< MODFC (Bit 26)                                        */
39793  #define R_SPI_B0_SPSRC_MODFC_Msk      (0x4000000UL)  /*!< MODFC (Bitfield-Mask: 0x01)                           */
39794  #define R_SPI_B0_SPSRC_PERFC_Pos      (27UL)         /*!< PERFC (Bit 27)                                        */
39795  #define R_SPI_B0_SPSRC_PERFC_Msk      (0x8000000UL)  /*!< PERFC (Bitfield-Mask: 0x01)                           */
39796  #define R_SPI_B0_SPSRC_UDRFC_Pos      (28UL)         /*!< UDRFC (Bit 28)                                        */
39797  #define R_SPI_B0_SPSRC_UDRFC_Msk      (0x10000000UL) /*!< UDRFC (Bitfield-Mask: 0x01)                           */
39798  #define R_SPI_B0_SPSRC_SPTEFC_Pos     (29UL)         /*!< SPTEFC (Bit 29)                                       */
39799  #define R_SPI_B0_SPSRC_SPTEFC_Msk     (0x20000000UL) /*!< SPTEFC (Bitfield-Mask: 0x01)                          */
39800  #define R_SPI_B0_SPSRC_CENDFC_Pos     (30UL)         /*!< CENDFC (Bit 30)                                       */
39801  #define R_SPI_B0_SPSRC_CENDFC_Msk     (0x40000000UL) /*!< CENDFC (Bitfield-Mask: 0x01)                          */
39802  #define R_SPI_B0_SPSRC_SPRFC_Pos      (31UL)         /*!< SPRFC (Bit 31)                                        */
39803  #define R_SPI_B0_SPSRC_SPRFC_Msk      (0x80000000UL) /*!< SPRFC (Bitfield-Mask: 0x01)                           */
39804 /* =========================================================  SPFCR  ========================================================= */
39805  #define R_SPI_B0_SPFCR_SPFRST_Pos     (0UL)          /*!< SPFRST (Bit 0)                                        */
39806  #define R_SPI_B0_SPFCR_SPFRST_Msk     (0x1UL)        /*!< SPFRST (Bitfield-Mask: 0x01)                          */
39807 
39808 /* =========================================================================================================================== */
39809 /* ================                                         R_USB_HS0                                         ================ */
39810 /* =========================================================================================================================== */
39811 
39812 /* ========================================================  SYSCFG  ========================================================= */
39813  #define R_USB_HS0_SYSCFG_CNEN_Pos         (8UL)          /*!< CNEN (Bit 8)                                          */
39814  #define R_USB_HS0_SYSCFG_CNEN_Msk         (0x100UL)      /*!< CNEN (Bitfield-Mask: 0x01)                            */
39815  #define R_USB_HS0_SYSCFG_HSE_Pos          (7UL)          /*!< HSE (Bit 7)                                           */
39816  #define R_USB_HS0_SYSCFG_HSE_Msk          (0x80UL)       /*!< HSE (Bitfield-Mask: 0x01)                             */
39817  #define R_USB_HS0_SYSCFG_DCFM_Pos         (6UL)          /*!< DCFM (Bit 6)                                          */
39818  #define R_USB_HS0_SYSCFG_DCFM_Msk         (0x40UL)       /*!< DCFM (Bitfield-Mask: 0x01)                            */
39819  #define R_USB_HS0_SYSCFG_DRPD_Pos         (5UL)          /*!< DRPD (Bit 5)                                          */
39820  #define R_USB_HS0_SYSCFG_DRPD_Msk         (0x20UL)       /*!< DRPD (Bitfield-Mask: 0x01)                            */
39821  #define R_USB_HS0_SYSCFG_DPRPU_Pos        (4UL)          /*!< DPRPU (Bit 4)                                         */
39822  #define R_USB_HS0_SYSCFG_DPRPU_Msk        (0x10UL)       /*!< DPRPU (Bitfield-Mask: 0x01)                           */
39823  #define R_USB_HS0_SYSCFG_USBE_Pos         (0UL)          /*!< USBE (Bit 0)                                          */
39824  #define R_USB_HS0_SYSCFG_USBE_Msk         (0x1UL)        /*!< USBE (Bitfield-Mask: 0x01)                            */
39825 /* ========================================================  BUSWAIT  ======================================================== */
39826  #define R_USB_HS0_BUSWAIT_BWAIT_Pos       (0UL)          /*!< BWAIT (Bit 0)                                         */
39827  #define R_USB_HS0_BUSWAIT_BWAIT_Msk       (0xfUL)        /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
39828 /* ========================================================  SYSSTS0  ======================================================== */
39829  #define R_USB_HS0_SYSSTS0_HTACT_Pos       (6UL)          /*!< HTACT (Bit 6)                                         */
39830  #define R_USB_HS0_SYSSTS0_HTACT_Msk       (0x40UL)       /*!< HTACT (Bitfield-Mask: 0x01)                           */
39831  #define R_USB_HS0_SYSSTS0_SOFEA_Pos       (5UL)          /*!< SOFEA (Bit 5)                                         */
39832  #define R_USB_HS0_SYSSTS0_SOFEA_Msk       (0x20UL)       /*!< SOFEA (Bitfield-Mask: 0x01)                           */
39833  #define R_USB_HS0_SYSSTS0_IDMON_Pos       (2UL)          /*!< IDMON (Bit 2)                                         */
39834  #define R_USB_HS0_SYSSTS0_IDMON_Msk       (0x4UL)        /*!< IDMON (Bitfield-Mask: 0x01)                           */
39835  #define R_USB_HS0_SYSSTS0_LNST_Pos        (0UL)          /*!< LNST (Bit 0)                                          */
39836  #define R_USB_HS0_SYSSTS0_LNST_Msk        (0x3UL)        /*!< LNST (Bitfield-Mask: 0x03)                            */
39837  #define R_USB_HS0_SYSSTS0_OVCMON_Pos      (14UL)         /*!< OVCMON (Bit 14)                                       */
39838  #define R_USB_HS0_SYSSTS0_OVCMON_Msk      (0xc000UL)     /*!< OVCMON (Bitfield-Mask: 0x03)                          */
39839 /* ========================================================  PLLSTA  ========================================================= */
39840  #define R_USB_HS0_PLLSTA_PLLLOCK_Pos      (0UL)          /*!< PLLLOCK (Bit 0)                                       */
39841  #define R_USB_HS0_PLLSTA_PLLLOCK_Msk      (0x1UL)        /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
39842 /* =======================================================  DVSTCTR0  ======================================================== */
39843  #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos    (11UL)         /*!< HNPBTOA (Bit 11)                                      */
39844  #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)      /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
39845  #define R_USB_HS0_DVSTCTR0_EXICEN_Pos     (10UL)         /*!< EXICEN (Bit 10)                                       */
39846  #define R_USB_HS0_DVSTCTR0_EXICEN_Msk     (0x400UL)      /*!< EXICEN (Bitfield-Mask: 0x01)                          */
39847  #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos     (9UL)          /*!< VBUSEN (Bit 9)                                        */
39848  #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)      /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
39849  #define R_USB_HS0_DVSTCTR0_WKUP_Pos       (8UL)          /*!< WKUP (Bit 8)                                          */
39850  #define R_USB_HS0_DVSTCTR0_WKUP_Msk       (0x100UL)      /*!< WKUP (Bitfield-Mask: 0x01)                            */
39851  #define R_USB_HS0_DVSTCTR0_RWUPE_Pos      (7UL)          /*!< RWUPE (Bit 7)                                         */
39852  #define R_USB_HS0_DVSTCTR0_RWUPE_Msk      (0x80UL)       /*!< RWUPE (Bitfield-Mask: 0x01)                           */
39853  #define R_USB_HS0_DVSTCTR0_USBRST_Pos     (6UL)          /*!< USBRST (Bit 6)                                        */
39854  #define R_USB_HS0_DVSTCTR0_USBRST_Msk     (0x40UL)       /*!< USBRST (Bitfield-Mask: 0x01)                          */
39855  #define R_USB_HS0_DVSTCTR0_RESUME_Pos     (5UL)          /*!< RESUME (Bit 5)                                        */
39856  #define R_USB_HS0_DVSTCTR0_RESUME_Msk     (0x20UL)       /*!< RESUME (Bitfield-Mask: 0x01)                          */
39857  #define R_USB_HS0_DVSTCTR0_UACT_Pos       (4UL)          /*!< UACT (Bit 4)                                          */
39858  #define R_USB_HS0_DVSTCTR0_UACT_Msk       (0x10UL)       /*!< UACT (Bitfield-Mask: 0x01)                            */
39859  #define R_USB_HS0_DVSTCTR0_RHST_Pos       (0UL)          /*!< RHST (Bit 0)                                          */
39860  #define R_USB_HS0_DVSTCTR0_RHST_Msk       (0x7UL)        /*!< RHST (Bitfield-Mask: 0x07)                            */
39861 /* =======================================================  TESTMODE  ======================================================== */
39862  #define R_USB_HS0_TESTMODE_UTST_Pos       (0UL)          /*!< UTST (Bit 0)                                          */
39863  #define R_USB_HS0_TESTMODE_UTST_Msk       (0xfUL)        /*!< UTST (Bitfield-Mask: 0x0f)                            */
39864 /* =========================================================  CFIFO  ========================================================= */
39865  #define R_USB_HS0_CFIFO_FIFOPORT_Pos      (0UL)          /*!< FIFOPORT (Bit 0)                                      */
39866  #define R_USB_HS0_CFIFO_FIFOPORT_Msk      (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
39867 /* ========================================================  CFIFOL  ========================================================= */
39868 /* ========================================================  CFIFOH  ========================================================= */
39869 /* ========================================================  CFIFOLL  ======================================================== */
39870 /* ========================================================  CFIFOHH  ======================================================== */
39871 /* ========================================================  D0FIFO  ========================================================= */
39872  #define R_USB_HS0_D0FIFO_FIFOPORT_Pos    (0UL)          /*!< FIFOPORT (Bit 0)                                      */
39873  #define R_USB_HS0_D0FIFO_FIFOPORT_Msk    (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
39874 /* ========================================================  D0FIFOL  ======================================================== */
39875 /* ========================================================  D0FIFOH  ======================================================== */
39876 /* =======================================================  D0FIFOLL  ======================================================== */
39877 /* =======================================================  D0FIFOHH  ======================================================== */
39878 /* ========================================================  D1FIFO  ========================================================= */
39879  #define R_USB_HS0_D1FIFO_FIFOPORT_Pos    (0UL)          /*!< FIFOPORT (Bit 0)                                      */
39880  #define R_USB_HS0_D1FIFO_FIFOPORT_Msk    (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
39881 /* ========================================================  D1FIFOL  ======================================================== */
39882 /* ========================================================  D1FIFOH  ======================================================== */
39883 /* =======================================================  D1FIFOLL  ======================================================== */
39884 /* =======================================================  D1FIFOHH  ======================================================== */
39885 /* =======================================================  CFIFOSEL  ======================================================== */
39886  #define R_USB_HS0_CFIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
39887  #define R_USB_HS0_CFIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
39888  #define R_USB_HS0_CFIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
39889  #define R_USB_HS0_CFIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
39890  #define R_USB_HS0_CFIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
39891  #define R_USB_HS0_CFIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
39892  #define R_USB_HS0_CFIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
39893  #define R_USB_HS0_CFIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
39894  #define R_USB_HS0_CFIFOSEL_ISEL_Pos           (5UL)        /*!< ISEL (Bit 5)                                          */
39895  #define R_USB_HS0_CFIFOSEL_ISEL_Msk           (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
39896  #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
39897  #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
39898 /* =======================================================  CFIFOCTR  ======================================================== */
39899  #define R_USB_HS0_CFIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
39900  #define R_USB_HS0_CFIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
39901  #define R_USB_HS0_CFIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
39902  #define R_USB_HS0_CFIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
39903  #define R_USB_HS0_CFIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
39904  #define R_USB_HS0_CFIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
39905  #define R_USB_HS0_CFIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
39906  #define R_USB_HS0_CFIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
39907 /* =======================================================  D0FIFOSEL  ======================================================= */
39908  #define R_USB_HS0_D0FIFOSEL_RCNT_Pos          (15UL)       /*!< RCNT (Bit 15)                                         */
39909  #define R_USB_HS0_D0FIFOSEL_RCNT_Msk          (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
39910  #define R_USB_HS0_D0FIFOSEL_REW_Pos           (14UL)       /*!< REW (Bit 14)                                          */
39911  #define R_USB_HS0_D0FIFOSEL_REW_Msk           (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
39912  #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos         (13UL)       /*!< DCLRM (Bit 13)                                        */
39913  #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk         (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
39914  #define R_USB_HS0_D0FIFOSEL_DREQE_Pos         (12UL)       /*!< DREQE (Bit 12)                                        */
39915  #define R_USB_HS0_D0FIFOSEL_DREQE_Msk         (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
39916  #define R_USB_HS0_D0FIFOSEL_MBW_Pos           (10UL)       /*!< MBW (Bit 10)                                          */
39917  #define R_USB_HS0_D0FIFOSEL_MBW_Msk           (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
39918  #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos        (8UL)        /*!< BIGEND (Bit 8)                                        */
39919  #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk        (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
39920  #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos       (0UL)        /*!< CURPIPE (Bit 0)                                       */
39921  #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk       (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
39922 /* =======================================================  D0FIFOCTR  ======================================================= */
39923  #define R_USB_HS0_D0FIFOCTR_BVAL_Pos          (15UL)       /*!< BVAL (Bit 15)                                         */
39924  #define R_USB_HS0_D0FIFOCTR_BVAL_Msk          (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
39925  #define R_USB_HS0_D0FIFOCTR_BCLR_Pos          (14UL)       /*!< BCLR (Bit 14)                                         */
39926  #define R_USB_HS0_D0FIFOCTR_BCLR_Msk          (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
39927  #define R_USB_HS0_D0FIFOCTR_FRDY_Pos          (13UL)       /*!< FRDY (Bit 13)                                         */
39928  #define R_USB_HS0_D0FIFOCTR_FRDY_Msk          (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
39929  #define R_USB_HS0_D0FIFOCTR_DTLN_Pos          (0UL)        /*!< DTLN (Bit 0)                                          */
39930  #define R_USB_HS0_D0FIFOCTR_DTLN_Msk          (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
39931 /* =======================================================  D1FIFOSEL  ======================================================= */
39932  #define R_USB_HS0_D1FIFOSEL_RCNT_Pos          (15UL)       /*!< RCNT (Bit 15)                                         */
39933  #define R_USB_HS0_D1FIFOSEL_RCNT_Msk          (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
39934  #define R_USB_HS0_D1FIFOSEL_REW_Pos           (14UL)       /*!< REW (Bit 14)                                          */
39935  #define R_USB_HS0_D1FIFOSEL_REW_Msk           (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
39936  #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos         (13UL)       /*!< DCLRM (Bit 13)                                        */
39937  #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk         (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
39938  #define R_USB_HS0_D1FIFOSEL_DREQE_Pos         (12UL)       /*!< DREQE (Bit 12)                                        */
39939  #define R_USB_HS0_D1FIFOSEL_DREQE_Msk         (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
39940  #define R_USB_HS0_D1FIFOSEL_MBW_Pos           (10UL)       /*!< MBW (Bit 10)                                          */
39941  #define R_USB_HS0_D1FIFOSEL_MBW_Msk           (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
39942  #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos        (8UL)        /*!< BIGEND (Bit 8)                                        */
39943  #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk        (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
39944  #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos       (0UL)        /*!< CURPIPE (Bit 0)                                       */
39945  #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk       (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
39946 /* =======================================================  D1FIFOCTR  ======================================================= */
39947  #define R_USB_HS0_D1FIFOCTR_BVAL_Pos          (15UL)       /*!< BVAL (Bit 15)                                         */
39948  #define R_USB_HS0_D1FIFOCTR_BVAL_Msk          (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
39949  #define R_USB_HS0_D1FIFOCTR_BCLR_Pos          (14UL)       /*!< BCLR (Bit 14)                                         */
39950  #define R_USB_HS0_D1FIFOCTR_BCLR_Msk          (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
39951  #define R_USB_HS0_D1FIFOCTR_FRDY_Pos          (13UL)       /*!< FRDY (Bit 13)                                         */
39952  #define R_USB_HS0_D1FIFOCTR_FRDY_Msk          (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
39953  #define R_USB_HS0_D1FIFOCTR_DTLN_Pos          (0UL)        /*!< DTLN (Bit 0)                                          */
39954  #define R_USB_HS0_D1FIFOCTR_DTLN_Msk          (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
39955 /* ========================================================  INTENB0  ======================================================== */
39956  #define R_USB_HS0_INTENB0_VBSE_Pos            (15UL)       /*!< VBSE (Bit 15)                                         */
39957  #define R_USB_HS0_INTENB0_VBSE_Msk            (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
39958  #define R_USB_HS0_INTENB0_RSME_Pos            (14UL)       /*!< RSME (Bit 14)                                         */
39959  #define R_USB_HS0_INTENB0_RSME_Msk            (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
39960  #define R_USB_HS0_INTENB0_SOFE_Pos            (13UL)       /*!< SOFE (Bit 13)                                         */
39961  #define R_USB_HS0_INTENB0_SOFE_Msk            (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
39962  #define R_USB_HS0_INTENB0_DVSE_Pos            (12UL)       /*!< DVSE (Bit 12)                                         */
39963  #define R_USB_HS0_INTENB0_DVSE_Msk            (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
39964  #define R_USB_HS0_INTENB0_CTRE_Pos            (11UL)       /*!< CTRE (Bit 11)                                         */
39965  #define R_USB_HS0_INTENB0_CTRE_Msk            (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
39966  #define R_USB_HS0_INTENB0_BEMPE_Pos           (10UL)       /*!< BEMPE (Bit 10)                                        */
39967  #define R_USB_HS0_INTENB0_BEMPE_Msk           (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
39968  #define R_USB_HS0_INTENB0_NRDYE_Pos           (9UL)        /*!< NRDYE (Bit 9)                                         */
39969  #define R_USB_HS0_INTENB0_NRDYE_Msk           (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
39970  #define R_USB_HS0_INTENB0_BRDYE_Pos           (8UL)        /*!< BRDYE (Bit 8)                                         */
39971  #define R_USB_HS0_INTENB0_BRDYE_Msk           (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
39972 /* ========================================================  INTENB1  ======================================================== */
39973  #define R_USB_HS0_INTENB1_OVRCRE_Pos          (15UL)       /*!< OVRCRE (Bit 15)                                       */
39974  #define R_USB_HS0_INTENB1_OVRCRE_Msk          (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
39975  #define R_USB_HS0_INTENB1_BCHGE_Pos           (14UL)       /*!< BCHGE (Bit 14)                                        */
39976  #define R_USB_HS0_INTENB1_BCHGE_Msk           (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
39977  #define R_USB_HS0_INTENB1_DTCHE_Pos           (12UL)       /*!< DTCHE (Bit 12)                                        */
39978  #define R_USB_HS0_INTENB1_DTCHE_Msk           (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
39979  #define R_USB_HS0_INTENB1_ATTCHE_Pos          (11UL)       /*!< ATTCHE (Bit 11)                                       */
39980  #define R_USB_HS0_INTENB1_ATTCHE_Msk          (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
39981  #define R_USB_HS0_INTENB1_L1RSMENDE_Pos       (9UL)        /*!< L1RSMENDE (Bit 9)                                     */
39982  #define R_USB_HS0_INTENB1_L1RSMENDE_Msk       (0x200UL)    /*!< L1RSMENDE (Bitfield-Mask: 0x01)                       */
39983  #define R_USB_HS0_INTENB1_LPMENDE_Pos         (8UL)        /*!< LPMENDE (Bit 8)                                       */
39984  #define R_USB_HS0_INTENB1_LPMENDE_Msk         (0x100UL)    /*!< LPMENDE (Bitfield-Mask: 0x01)                         */
39985  #define R_USB_HS0_INTENB1_EOFERRE_Pos         (6UL)        /*!< EOFERRE (Bit 6)                                       */
39986  #define R_USB_HS0_INTENB1_EOFERRE_Msk         (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
39987  #define R_USB_HS0_INTENB1_SIGNE_Pos           (5UL)        /*!< SIGNE (Bit 5)                                         */
39988  #define R_USB_HS0_INTENB1_SIGNE_Msk           (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
39989  #define R_USB_HS0_INTENB1_SACKE_Pos           (4UL)        /*!< SACKE (Bit 4)                                         */
39990  #define R_USB_HS0_INTENB1_SACKE_Msk           (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
39991  #define R_USB_HS0_INTENB1_PDDETINTE0_Pos      (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
39992  #define R_USB_HS0_INTENB1_PDDETINTE0_Msk      (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
39993 /* ========================================================  BRDYENB  ======================================================== */
39994  #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos       (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
39995  #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk       (0x3ffUL)    /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff)                      */
39996 /* ========================================================  NRDYENB  ======================================================== */
39997  #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos       (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
39998  #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk       (0x3ffUL)    /*!< PIPENRDYE (Bitfield-Mask: 0x3ff)                      */
39999 /* ========================================================  BEMPENB  ======================================================== */
40000  #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos       (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
40001  #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk       (0x3ffUL)    /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff)                      */
40002 /* ========================================================  SOFCFG  ========================================================= */
40003  #define R_USB_HS0_SOFCFG_TRNENSEL_Pos         (8UL)        /*!< TRNENSEL (Bit 8)                                      */
40004  #define R_USB_HS0_SOFCFG_TRNENSEL_Msk         (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
40005  #define R_USB_HS0_SOFCFG_BRDYM_Pos            (6UL)        /*!< BRDYM (Bit 6)                                         */
40006  #define R_USB_HS0_SOFCFG_BRDYM_Msk            (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
40007  #define R_USB_HS0_SOFCFG_INTL_Pos             (5UL)        /*!< INTL (Bit 5)                                          */
40008  #define R_USB_HS0_SOFCFG_INTL_Msk             (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
40009  #define R_USB_HS0_SOFCFG_EDGESTS_Pos          (4UL)        /*!< EDGESTS (Bit 4)                                       */
40010  #define R_USB_HS0_SOFCFG_EDGESTS_Msk          (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
40011 /* ========================================================  PHYSET  ========================================================= */
40012  #define R_USB_HS0_PHYSET_HSEB_Pos             (15UL)       /*!< HSEB (Bit 15)                                         */
40013  #define R_USB_HS0_PHYSET_HSEB_Msk             (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
40014  #define R_USB_HS0_PHYSET_REPSTART_Pos         (11UL)       /*!< REPSTART (Bit 11)                                     */
40015  #define R_USB_HS0_PHYSET_REPSTART_Msk         (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
40016  #define R_USB_HS0_PHYSET_REPSEL_Pos           (8UL)        /*!< REPSEL (Bit 8)                                        */
40017  #define R_USB_HS0_PHYSET_REPSEL_Msk           (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
40018  #define R_USB_HS0_PHYSET_CLKSEL_Pos           (4UL)        /*!< CLKSEL (Bit 4)                                        */
40019  #define R_USB_HS0_PHYSET_CLKSEL_Msk           (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
40020  #define R_USB_HS0_PHYSET_CDPEN_Pos            (3UL)        /*!< CDPEN (Bit 3)                                         */
40021  #define R_USB_HS0_PHYSET_CDPEN_Msk            (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
40022  #define R_USB_HS0_PHYSET_PLLRESET_Pos         (1UL)        /*!< PLLRESET (Bit 1)                                      */
40023  #define R_USB_HS0_PHYSET_PLLRESET_Msk         (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
40024  #define R_USB_HS0_PHYSET_DIRPD_Pos            (0UL)        /*!< DIRPD (Bit 0)                                         */
40025  #define R_USB_HS0_PHYSET_DIRPD_Msk            (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
40026 /* ========================================================  INTSTS0  ======================================================== */
40027  #define R_USB_HS0_INTSTS0_VBINT_Pos           (15UL)       /*!< VBINT (Bit 15)                                        */
40028  #define R_USB_HS0_INTSTS0_VBINT_Msk           (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
40029  #define R_USB_HS0_INTSTS0_RESM_Pos            (14UL)       /*!< RESM (Bit 14)                                         */
40030  #define R_USB_HS0_INTSTS0_RESM_Msk            (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
40031  #define R_USB_HS0_INTSTS0_SOFR_Pos            (13UL)       /*!< SOFR (Bit 13)                                         */
40032  #define R_USB_HS0_INTSTS0_SOFR_Msk            (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
40033  #define R_USB_HS0_INTSTS0_DVST_Pos            (12UL)       /*!< DVST (Bit 12)                                         */
40034  #define R_USB_HS0_INTSTS0_DVST_Msk            (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
40035  #define R_USB_HS0_INTSTS0_CTRT_Pos            (11UL)       /*!< CTRT (Bit 11)                                         */
40036  #define R_USB_HS0_INTSTS0_CTRT_Msk            (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
40037  #define R_USB_HS0_INTSTS0_BEMP_Pos            (10UL)       /*!< BEMP (Bit 10)                                         */
40038  #define R_USB_HS0_INTSTS0_BEMP_Msk            (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
40039  #define R_USB_HS0_INTSTS0_NRDY_Pos            (9UL)        /*!< NRDY (Bit 9)                                          */
40040  #define R_USB_HS0_INTSTS0_NRDY_Msk            (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
40041  #define R_USB_HS0_INTSTS0_BRDY_Pos            (8UL)        /*!< BRDY (Bit 8)                                          */
40042  #define R_USB_HS0_INTSTS0_BRDY_Msk            (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
40043  #define R_USB_HS0_INTSTS0_VBSTS_Pos           (7UL)        /*!< VBSTS (Bit 7)                                         */
40044  #define R_USB_HS0_INTSTS0_VBSTS_Msk           (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
40045  #define R_USB_HS0_INTSTS0_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
40046  #define R_USB_HS0_INTSTS0_DVSQ_Msk            (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
40047  #define R_USB_HS0_INTSTS0_VALID_Pos           (3UL)        /*!< VALID (Bit 3)                                         */
40048  #define R_USB_HS0_INTSTS0_VALID_Msk           (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
40049  #define R_USB_HS0_INTSTS0_CTSQ_Pos            (0UL)        /*!< CTSQ (Bit 0)                                          */
40050  #define R_USB_HS0_INTSTS0_CTSQ_Msk            (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
40051 /* ========================================================  INTSTS1  ======================================================== */
40052  #define R_USB_HS0_INTSTS1_OVRCR_Pos           (15UL)       /*!< OVRCR (Bit 15)                                        */
40053  #define R_USB_HS0_INTSTS1_OVRCR_Msk           (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
40054  #define R_USB_HS0_INTSTS1_BCHG_Pos            (14UL)       /*!< BCHG (Bit 14)                                         */
40055  #define R_USB_HS0_INTSTS1_BCHG_Msk            (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
40056  #define R_USB_HS0_INTSTS1_DTCH_Pos            (12UL)       /*!< DTCH (Bit 12)                                         */
40057  #define R_USB_HS0_INTSTS1_DTCH_Msk            (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
40058  #define R_USB_HS0_INTSTS1_ATTCH_Pos           (11UL)       /*!< ATTCH (Bit 11)                                        */
40059  #define R_USB_HS0_INTSTS1_ATTCH_Msk           (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
40060  #define R_USB_HS0_INTSTS1_L1RSMEND_Pos        (9UL)        /*!< L1RSMEND (Bit 9)                                      */
40061  #define R_USB_HS0_INTSTS1_L1RSMEND_Msk        (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
40062  #define R_USB_HS0_INTSTS1_LPMEND_Pos          (8UL)        /*!< LPMEND (Bit 8)                                        */
40063  #define R_USB_HS0_INTSTS1_LPMEND_Msk          (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
40064  #define R_USB_HS0_INTSTS1_EOFERR_Pos          (6UL)        /*!< EOFERR (Bit 6)                                        */
40065  #define R_USB_HS0_INTSTS1_EOFERR_Msk          (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
40066  #define R_USB_HS0_INTSTS1_SIGN_Pos            (5UL)        /*!< SIGN (Bit 5)                                          */
40067  #define R_USB_HS0_INTSTS1_SIGN_Msk            (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
40068  #define R_USB_HS0_INTSTS1_SACK_Pos            (4UL)        /*!< SACK (Bit 4)                                          */
40069  #define R_USB_HS0_INTSTS1_SACK_Msk            (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
40070  #define R_USB_HS0_INTSTS1_PDDETINT0_Pos       (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
40071  #define R_USB_HS0_INTSTS1_PDDETINT0_Msk       (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
40072 /* ========================================================  BRDYSTS  ======================================================== */
40073  #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos        (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
40074  #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk        (0x3ffUL)    /*!< PIPEBRDY (Bitfield-Mask: 0x3ff)                       */
40075 /* ========================================================  NRDYSTS  ======================================================== */
40076  #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos        (0UL)        /*!< PIPENRDY (Bit 0)                                      */
40077  #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk        (0x3ffUL)    /*!< PIPENRDY (Bitfield-Mask: 0x3ff)                       */
40078 /* ========================================================  BEMPSTS  ======================================================== */
40079  #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos        (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
40080  #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk        (0x3ffUL)    /*!< PIPEBEMP (Bitfield-Mask: 0x3ff)                       */
40081 /* ========================================================  FRMNUM  ========================================================= */
40082  #define R_USB_HS0_FRMNUM_OVRN_Pos             (15UL)       /*!< OVRN (Bit 15)                                         */
40083  #define R_USB_HS0_FRMNUM_OVRN_Msk             (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
40084  #define R_USB_HS0_FRMNUM_CRCE_Pos             (14UL)       /*!< CRCE (Bit 14)                                         */
40085  #define R_USB_HS0_FRMNUM_CRCE_Msk             (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
40086  #define R_USB_HS0_FRMNUM_FRNM_Pos             (0UL)        /*!< FRNM (Bit 0)                                          */
40087  #define R_USB_HS0_FRMNUM_FRNM_Msk             (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
40088 /* ========================================================  UFRMNUM  ======================================================== */
40089  #define R_USB_HS0_UFRMNUM_DVCHG_Pos           (15UL)       /*!< DVCHG (Bit 15)                                        */
40090  #define R_USB_HS0_UFRMNUM_DVCHG_Msk           (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
40091  #define R_USB_HS0_UFRMNUM_UFRNM_Pos           (0UL)        /*!< UFRNM (Bit 0)                                         */
40092  #define R_USB_HS0_UFRMNUM_UFRNM_Msk           (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
40093 /* ========================================================  USBADDR  ======================================================== */
40094  #define R_USB_HS0_USBADDR_STSRECOV0_Pos       (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
40095  #define R_USB_HS0_USBADDR_STSRECOV0_Msk       (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
40096 /* ========================================================  USBREQ  ========================================================= */
40097  #define R_USB_HS0_USBREQ_BREQUEST_Pos         (8UL)        /*!< BREQUEST (Bit 8)                                      */
40098  #define R_USB_HS0_USBREQ_BREQUEST_Msk         (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
40099  #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos    (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
40100  #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk    (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
40101 /* ========================================================  USBVAL  ========================================================= */
40102  #define R_USB_HS0_USBVAL_WVALUE_Pos           (0UL)        /*!< WVALUE (Bit 0)                                        */
40103  #define R_USB_HS0_USBVAL_WVALUE_Msk           (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
40104 /* ========================================================  USBINDX  ======================================================== */
40105  #define R_USB_HS0_USBINDX_WINDEX_Pos          (0UL)        /*!< WINDEX (Bit 0)                                        */
40106  #define R_USB_HS0_USBINDX_WINDEX_Msk          (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
40107 /* ========================================================  USBLENG  ======================================================== */
40108  #define R_USB_HS0_USBLENG_WLENGTH_Pos         (0UL)        /*!< WLENGTH (Bit 0)                                       */
40109  #define R_USB_HS0_USBLENG_WLENGTH_Msk         (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
40110 /* ========================================================  DCPCFG  ========================================================= */
40111  #define R_USB_HS0_DCPCFG_CNTMD_Pos            (8UL)        /*!< CNTMD (Bit 8)                                         */
40112  #define R_USB_HS0_DCPCFG_CNTMD_Msk            (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
40113  #define R_USB_HS0_DCPCFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
40114  #define R_USB_HS0_DCPCFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
40115  #define R_USB_HS0_DCPCFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
40116  #define R_USB_HS0_DCPCFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
40117 /* ========================================================  DCPMAXP  ======================================================== */
40118  #define R_USB_HS0_DCPMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
40119  #define R_USB_HS0_DCPMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
40120  #define R_USB_HS0_DCPMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
40121  #define R_USB_HS0_DCPMAXP_MXPS_Msk            (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
40122 /* ========================================================  DCPCTR  ========================================================= */
40123  #define R_USB_HS0_DCPCTR_BSTS_Pos             (15UL)       /*!< BSTS (Bit 15)                                         */
40124  #define R_USB_HS0_DCPCTR_BSTS_Msk             (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
40125  #define R_USB_HS0_DCPCTR_SUREQ_Pos            (14UL)       /*!< SUREQ (Bit 14)                                        */
40126  #define R_USB_HS0_DCPCTR_SUREQ_Msk            (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
40127  #define R_USB_HS0_DCPCTR_CSCLR_Pos            (13UL)       /*!< CSCLR (Bit 13)                                        */
40128  #define R_USB_HS0_DCPCTR_CSCLR_Msk            (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
40129  #define R_USB_HS0_DCPCTR_CSSTS_Pos            (12UL)       /*!< CSSTS (Bit 12)                                        */
40130  #define R_USB_HS0_DCPCTR_CSSTS_Msk            (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
40131  #define R_USB_HS0_DCPCTR_SUREQCLR_Pos         (11UL)       /*!< SUREQCLR (Bit 11)                                     */
40132  #define R_USB_HS0_DCPCTR_SUREQCLR_Msk         (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
40133  #define R_USB_HS0_DCPCTR_SQCLR_Pos            (8UL)        /*!< SQCLR (Bit 8)                                         */
40134  #define R_USB_HS0_DCPCTR_SQCLR_Msk            (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
40135  #define R_USB_HS0_DCPCTR_SQSET_Pos            (7UL)        /*!< SQSET (Bit 7)                                         */
40136  #define R_USB_HS0_DCPCTR_SQSET_Msk            (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
40137  #define R_USB_HS0_DCPCTR_SQMON_Pos            (6UL)        /*!< SQMON (Bit 6)                                         */
40138  #define R_USB_HS0_DCPCTR_SQMON_Msk            (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
40139  #define R_USB_HS0_DCPCTR_PBUSY_Pos            (5UL)        /*!< PBUSY (Bit 5)                                         */
40140  #define R_USB_HS0_DCPCTR_PBUSY_Msk            (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
40141  #define R_USB_HS0_DCPCTR_PINGE_Pos            (4UL)        /*!< PINGE (Bit 4)                                         */
40142  #define R_USB_HS0_DCPCTR_PINGE_Msk            (0x10UL)     /*!< PINGE (Bitfield-Mask: 0x01)                           */
40143  #define R_USB_HS0_DCPCTR_CCPL_Pos             (2UL)        /*!< CCPL (Bit 2)                                          */
40144  #define R_USB_HS0_DCPCTR_CCPL_Msk             (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
40145  #define R_USB_HS0_DCPCTR_PID_Pos              (0UL)        /*!< PID (Bit 0)                                           */
40146  #define R_USB_HS0_DCPCTR_PID_Msk              (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
40147 /* ========================================================  PIPESEL  ======================================================== */
40148 /* ========================================================  PIPECFG  ======================================================== */
40149  #define R_USB_HS0_PIPECFG_TYPE_Pos            (14UL)       /*!< TYPE (Bit 14)                                         */
40150  #define R_USB_HS0_PIPECFG_TYPE_Msk            (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
40151  #define R_USB_HS0_PIPECFG_BFRE_Pos            (10UL)       /*!< BFRE (Bit 10)                                         */
40152  #define R_USB_HS0_PIPECFG_BFRE_Msk            (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
40153  #define R_USB_HS0_PIPECFG_DBLB_Pos            (9UL)        /*!< DBLB (Bit 9)                                          */
40154  #define R_USB_HS0_PIPECFG_DBLB_Msk            (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
40155  #define R_USB_HS0_PIPECFG_CNTMD_Pos           (8UL)        /*!< CNTMD (Bit 8)                                         */
40156  #define R_USB_HS0_PIPECFG_CNTMD_Msk           (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
40157  #define R_USB_HS0_PIPECFG_SHTNAK_Pos          (7UL)        /*!< SHTNAK (Bit 7)                                        */
40158  #define R_USB_HS0_PIPECFG_SHTNAK_Msk          (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
40159  #define R_USB_HS0_PIPECFG_DIR_Pos             (4UL)        /*!< DIR (Bit 4)                                           */
40160  #define R_USB_HS0_PIPECFG_DIR_Msk             (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
40161  #define R_USB_HS0_PIPECFG_EPNUM_Pos           (0UL)        /*!< EPNUM (Bit 0)                                         */
40162  #define R_USB_HS0_PIPECFG_EPNUM_Msk           (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
40163 /* ========================================================  PIPEBUF  ======================================================== */
40164  #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos         (10UL)       /*!< BUFSIZE (Bit 10)                                      */
40165  #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk         (0x7c00UL)   /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
40166  #define R_USB_HS0_PIPEBUF_BUFNMB_Pos          (0UL)        /*!< BUFNMB (Bit 0)                                        */
40167  #define R_USB_HS0_PIPEBUF_BUFNMB_Msk          (0xffUL)     /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
40168 /* =======================================================  PIPEMAXP  ======================================================== */
40169  #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos         (12UL)       /*!< DEVSEL (Bit 12)                                       */
40170  #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk         (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
40171  #define R_USB_HS0_PIPEMAXP_MXPS_Pos           (0UL)        /*!< MXPS (Bit 0)                                          */
40172  #define R_USB_HS0_PIPEMAXP_MXPS_Msk           (0x7ffUL)    /*!< MXPS (Bitfield-Mask: 0x7ff)                           */
40173 /* =======================================================  PIPEPERI  ======================================================== */
40174  #define R_USB_HS0_PIPEPERI_IFIS_Pos           (12UL)       /*!< IFIS (Bit 12)                                         */
40175  #define R_USB_HS0_PIPEPERI_IFIS_Msk           (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
40176  #define R_USB_HS0_PIPEPERI_IITV_Pos           (0UL)        /*!< IITV (Bit 0)                                          */
40177  #define R_USB_HS0_PIPEPERI_IITV_Msk           (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
40178 /* =======================================================  PIPE_CTR  ======================================================== */
40179  #define R_USB_HS0_PIPE_CTR_BSTS_Pos           (15UL)       /*!< BSTS (Bit 15)                                         */
40180  #define R_USB_HS0_PIPE_CTR_BSTS_Msk           (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
40181  #define R_USB_HS0_PIPE_CTR_INBUFM_Pos         (14UL)       /*!< INBUFM (Bit 14)                                       */
40182  #define R_USB_HS0_PIPE_CTR_INBUFM_Msk         (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
40183  #define R_USB_HS0_PIPE_CTR_CSCLR_Pos          (13UL)       /*!< CSCLR (Bit 13)                                        */
40184  #define R_USB_HS0_PIPE_CTR_CSCLR_Msk          (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
40185  #define R_USB_HS0_PIPE_CTR_CSSTS_Pos          (12UL)       /*!< CSSTS (Bit 12)                                        */
40186  #define R_USB_HS0_PIPE_CTR_CSSTS_Msk          (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
40187  #define R_USB_HS0_PIPE_CTR_ATREPM_Pos         (10UL)       /*!< ATREPM (Bit 10)                                       */
40188  #define R_USB_HS0_PIPE_CTR_ATREPM_Msk         (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
40189  #define R_USB_HS0_PIPE_CTR_ACLRM_Pos          (9UL)        /*!< ACLRM (Bit 9)                                         */
40190  #define R_USB_HS0_PIPE_CTR_ACLRM_Msk          (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
40191  #define R_USB_HS0_PIPE_CTR_SQCLR_Pos          (8UL)        /*!< SQCLR (Bit 8)                                         */
40192  #define R_USB_HS0_PIPE_CTR_SQCLR_Msk          (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
40193  #define R_USB_HS0_PIPE_CTR_SQSET_Pos          (7UL)        /*!< SQSET (Bit 7)                                         */
40194  #define R_USB_HS0_PIPE_CTR_SQSET_Msk          (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
40195  #define R_USB_HS0_PIPE_CTR_SQMON_Pos          (6UL)        /*!< SQMON (Bit 6)                                         */
40196  #define R_USB_HS0_PIPE_CTR_SQMON_Msk          (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
40197  #define R_USB_HS0_PIPE_CTR_PBUSY_Pos          (5UL)        /*!< PBUSY (Bit 5)                                         */
40198  #define R_USB_HS0_PIPE_CTR_PBUSY_Msk          (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
40199  #define R_USB_HS0_PIPE_CTR_PID_Pos            (0UL)        /*!< PID (Bit 0)                                           */
40200  #define R_USB_HS0_PIPE_CTR_PID_Msk            (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
40201 /* ========================================================  DEVADD  ========================================================= */
40202  #define R_USB_HS0_DEVADD_UPPHUB_Pos           (11UL)       /*!< UPPHUB (Bit 11)                                       */
40203  #define R_USB_HS0_DEVADD_UPPHUB_Msk           (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
40204  #define R_USB_HS0_DEVADD_HUBPORT_Pos          (8UL)        /*!< HUBPORT (Bit 8)                                       */
40205  #define R_USB_HS0_DEVADD_HUBPORT_Msk          (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
40206  #define R_USB_HS0_DEVADD_USBSPD_Pos           (6UL)        /*!< USBSPD (Bit 6)                                        */
40207  #define R_USB_HS0_DEVADD_USBSPD_Msk           (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
40208 /* ========================================================  LPCTRL  ========================================================= */
40209  #define R_USB_HS0_LPCTRL_HWUPM_Pos            (7UL)        /*!< HWUPM (Bit 7)                                         */
40210  #define R_USB_HS0_LPCTRL_HWUPM_Msk            (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
40211 /* =========================================================  LPSTS  ========================================================= */
40212  #define R_USB_HS0_LPSTS_SUSPENDM_Pos          (14UL)       /*!< SUSPENDM (Bit 14)                                     */
40213  #define R_USB_HS0_LPSTS_SUSPENDM_Msk          (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
40214 /* ========================================================  BCCTRL  ========================================================= */
40215  #define R_USB_HS0_BCCTRL_PDDETSTS_Pos         (9UL)        /*!< PDDETSTS (Bit 9)                                      */
40216  #define R_USB_HS0_BCCTRL_PDDETSTS_Msk         (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
40217  #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos        (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
40218  #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk        (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
40219  #define R_USB_HS0_BCCTRL_DCPMODE_Pos          (5UL)        /*!< DCPMODE (Bit 5)                                       */
40220  #define R_USB_HS0_BCCTRL_DCPMODE_Msk          (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
40221  #define R_USB_HS0_BCCTRL_VDMSRCE_Pos          (4UL)        /*!< VDMSRCE (Bit 4)                                       */
40222  #define R_USB_HS0_BCCTRL_VDMSRCE_Msk          (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
40223  #define R_USB_HS0_BCCTRL_IDPSINKE_Pos         (3UL)        /*!< IDPSINKE (Bit 3)                                      */
40224  #define R_USB_HS0_BCCTRL_IDPSINKE_Msk         (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
40225  #define R_USB_HS0_BCCTRL_VDPSRCE_Pos          (2UL)        /*!< VDPSRCE (Bit 2)                                       */
40226  #define R_USB_HS0_BCCTRL_VDPSRCE_Msk          (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
40227  #define R_USB_HS0_BCCTRL_IDMSINKE_Pos         (1UL)        /*!< IDMSINKE (Bit 1)                                      */
40228  #define R_USB_HS0_BCCTRL_IDMSINKE_Msk         (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
40229  #define R_USB_HS0_BCCTRL_IDPSRCE_Pos          (0UL)        /*!< IDPSRCE (Bit 0)                                       */
40230  #define R_USB_HS0_BCCTRL_IDPSRCE_Msk          (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
40231 /* =======================================================  PL1CTRL1  ======================================================== */
40232  #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos        (14UL)       /*!< L1EXTMD (Bit 14)                                      */
40233  #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk        (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
40234  #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos        (8UL)        /*!< HIRDTHR (Bit 8)                                       */
40235  #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk        (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
40236  #define R_USB_HS0_PL1CTRL1_DVSQ_Pos           (4UL)        /*!< DVSQ (Bit 4)                                          */
40237  #define R_USB_HS0_PL1CTRL1_DVSQ_Msk           (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
40238  #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos       (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
40239  #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk       (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
40240  #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos       (1UL)        /*!< L1RESPMD (Bit 1)                                      */
40241  #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk       (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
40242  #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos       (0UL)        /*!< L1RESPEN (Bit 0)                                      */
40243  #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk       (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
40244 /* =======================================================  PL1CTRL2  ======================================================== */
40245  #define R_USB_HS0_PL1CTRL2_RWEMON_Pos         (12UL)       /*!< RWEMON (Bit 12)                                       */
40246  #define R_USB_HS0_PL1CTRL2_RWEMON_Msk         (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
40247  #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos        (8UL)        /*!< HIRDMON (Bit 8)                                       */
40248  #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk        (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
40249 /* =======================================================  HL1CTRL1  ======================================================== */
40250  #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos       (1UL)        /*!< L1STATUS (Bit 1)                                      */
40251  #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk       (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
40252  #define R_USB_HS0_HL1CTRL1_L1REQ_Pos          (0UL)        /*!< L1REQ (Bit 0)                                         */
40253  #define R_USB_HS0_HL1CTRL1_L1REQ_Msk          (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
40254 /* =======================================================  HL1CTRL2  ======================================================== */
40255  #define R_USB_HS0_HL1CTRL2_BESL_Pos           (15UL)       /*!< BESL (Bit 15)                                         */
40256  #define R_USB_HS0_HL1CTRL2_BESL_Msk           (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
40257  #define R_USB_HS0_HL1CTRL2_L1RWE_Pos          (12UL)       /*!< L1RWE (Bit 12)                                        */
40258  #define R_USB_HS0_HL1CTRL2_L1RWE_Msk          (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
40259  #define R_USB_HS0_HL1CTRL2_HIRD_Pos           (8UL)        /*!< HIRD (Bit 8)                                          */
40260  #define R_USB_HS0_HL1CTRL2_HIRD_Msk           (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
40261  #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos         (0UL)        /*!< L1ADDR (Bit 0)                                        */
40262  #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk         (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
40263 /* =======================================================  PHYTRIM1  ======================================================== */
40264  #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos      (12UL)       /*!< IMPOFFSET (Bit 12)                                    */
40265  #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk      (0x7000UL)   /*!< IMPOFFSET (Bitfield-Mask: 0x07)                       */
40266  #define R_USB_HS0_PHYTRIM1_HSIUP_Pos          (8UL)        /*!< HSIUP (Bit 8)                                         */
40267  #define R_USB_HS0_PHYTRIM1_HSIUP_Msk          (0xf00UL)    /*!< HSIUP (Bitfield-Mask: 0x0f)                           */
40268  #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos       (7UL)        /*!< PCOMPENB (Bit 7)                                      */
40269  #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk       (0x80UL)     /*!< PCOMPENB (Bitfield-Mask: 0x01)                        */
40270  #define R_USB_HS0_PHYTRIM1_DFALL_Pos          (2UL)        /*!< DFALL (Bit 2)                                         */
40271  #define R_USB_HS0_PHYTRIM1_DFALL_Msk          (0xcUL)      /*!< DFALL (Bitfield-Mask: 0x03)                           */
40272  #define R_USB_HS0_PHYTRIM1_DRISE_Pos          (0UL)        /*!< DRISE (Bit 0)                                         */
40273  #define R_USB_HS0_PHYTRIM1_DRISE_Msk          (0x3UL)      /*!< DRISE (Bitfield-Mask: 0x03)                           */
40274 /* =======================================================  PHYTRIM2  ======================================================== */
40275  #define R_USB_HS0_PHYTRIM2_DIS_Pos            (12UL)       /*!< DIS (Bit 12)                                          */
40276  #define R_USB_HS0_PHYTRIM2_DIS_Msk            (0x7000UL)   /*!< DIS (Bitfield-Mask: 0x07)                             */
40277  #define R_USB_HS0_PHYTRIM2_PDR_Pos            (8UL)        /*!< PDR (Bit 8)                                           */
40278  #define R_USB_HS0_PHYTRIM2_PDR_Msk            (0x300UL)    /*!< PDR (Bitfield-Mask: 0x03)                             */
40279  #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos       (7UL)        /*!< HSRXENMO (Bit 7)                                      */
40280  #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk       (0x80UL)     /*!< HSRXENMO (Bitfield-Mask: 0x01)                        */
40281  #define R_USB_HS0_PHYTRIM2_SQU_Pos            (0UL)        /*!< SQU (Bit 0)                                           */
40282  #define R_USB_HS0_PHYTRIM2_SQU_Msk            (0xfUL)      /*!< SQU (Bitfield-Mask: 0x0f)                             */
40283 /* ========================================================  DPUSR0R  ======================================================== */
40284  #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos        (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
40285  #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk        (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
40286  #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos         (21UL)       /*!< DOVCBHM (Bit 21)                                      */
40287  #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk         (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
40288  #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos         (20UL)       /*!< DOVCAHM (Bit 20)                                      */
40289  #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk         (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
40290 /* ========================================================  DPUSR1R  ======================================================== */
40291  #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos         (23UL)       /*!< DVBSTSH (Bit 23)                                      */
40292  #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk         (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
40293  #define R_USB_HS0_DPUSR1R_DOVCBH_Pos          (21UL)       /*!< DOVCBH (Bit 21)                                       */
40294  #define R_USB_HS0_DPUSR1R_DOVCBH_Msk          (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
40295  #define R_USB_HS0_DPUSR1R_DOVCAH_Pos          (20UL)       /*!< DOVCAH (Bit 20)                                       */
40296  #define R_USB_HS0_DPUSR1R_DOVCAH_Msk          (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
40297  #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos        (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
40298  #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk        (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
40299  #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos         (5UL)        /*!< DOVCBHE (Bit 5)                                       */
40300  #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk         (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
40301  #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos         (4UL)        /*!< DOVCAHE (Bit 4)                                       */
40302  #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk         (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
40303 /* ========================================================  DPUSR2R  ======================================================== */
40304  #define R_USB_HS0_DPUSR2R_DMINTE_Pos          (9UL)        /*!< DMINTE (Bit 9)                                        */
40305  #define R_USB_HS0_DPUSR2R_DMINTE_Msk          (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
40306  #define R_USB_HS0_DPUSR2R_DPINTE_Pos          (8UL)        /*!< DPINTE (Bit 8)                                        */
40307  #define R_USB_HS0_DPUSR2R_DPINTE_Msk          (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
40308  #define R_USB_HS0_DPUSR2R_DMVAL_Pos           (5UL)        /*!< DMVAL (Bit 5)                                         */
40309  #define R_USB_HS0_DPUSR2R_DMVAL_Msk           (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
40310  #define R_USB_HS0_DPUSR2R_DPVAL_Pos           (4UL)        /*!< DPVAL (Bit 4)                                         */
40311  #define R_USB_HS0_DPUSR2R_DPVAL_Msk           (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
40312  #define R_USB_HS0_DPUSR2R_DMINT_Pos           (1UL)        /*!< DMINT (Bit 1)                                         */
40313  #define R_USB_HS0_DPUSR2R_DMINT_Msk           (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
40314  #define R_USB_HS0_DPUSR2R_DPINT_Pos           (0UL)        /*!< DPINT (Bit 0)                                         */
40315  #define R_USB_HS0_DPUSR2R_DPINT_Msk           (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
40316 /* ========================================================  DPUSRCR  ======================================================== */
40317  #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos        (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
40318  #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk        (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
40319  #define R_USB_HS0_DPUSRCR_FIXPHY_Pos          (0UL)        /*!< FIXPHY (Bit 0)                                        */
40320  #define R_USB_HS0_DPUSRCR_FIXPHY_Msk          (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
40321 
40322 /* =========================================================================================================================== */
40323 /* ================                                          R_XSPI                                           ================ */
40324 /* =========================================================================================================================== */
40325 
40326 /* ========================================================  WRAPCFG  ======================================================== */
40327  #define R_XSPI_WRAPCFG_CKSFTCS0_Pos      (0UL)          /*!< CKSFTCS0 (Bit 0)                                      */
40328  #define R_XSPI_WRAPCFG_CKSFTCS0_Msk      (0x1fUL)       /*!< CKSFTCS0 (Bitfield-Mask: 0x1f)                        */
40329  #define R_XSPI_WRAPCFG_DSSFTCS0_Pos      (8UL)          /*!< DSSFTCS0 (Bit 8)                                      */
40330  #define R_XSPI_WRAPCFG_DSSFTCS0_Msk      (0x1f00UL)     /*!< DSSFTCS0 (Bitfield-Mask: 0x1f)                        */
40331  #define R_XSPI_WRAPCFG_CKSFTCS1_Pos      (16UL)         /*!< CKSFTCS1 (Bit 16)                                     */
40332  #define R_XSPI_WRAPCFG_CKSFTCS1_Msk      (0x1f0000UL)   /*!< CKSFTCS1 (Bitfield-Mask: 0x1f)                        */
40333  #define R_XSPI_WRAPCFG_DSSFTCS1_Pos      (24UL)         /*!< DSSFTCS1 (Bit 24)                                     */
40334  #define R_XSPI_WRAPCFG_DSSFTCS1_Msk      (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f)                        */
40335 /* ========================================================  COMCFG  ========================================================= */
40336  #define R_XSPI_COMCFG_ARBMD_Pos          (0UL)          /*!< ARBMD (Bit 0)                                         */
40337  #define R_XSPI_COMCFG_ARBMD_Msk          (0x3UL)        /*!< ARBMD (Bitfield-Mask: 0x03)                           */
40338  #define R_XSPI_COMCFG_ECSINTOUTEN_Pos    (4UL)          /*!< ECSINTOUTEN (Bit 4)                                   */
40339  #define R_XSPI_COMCFG_ECSINTOUTEN_Msk    (0x30UL)       /*!< ECSINTOUTEN (Bitfield-Mask: 0x03)                     */
40340  #define R_XSPI_COMCFG_OEASTEX_Pos        (16UL)         /*!< OEASTEX (Bit 16)                                      */
40341  #define R_XSPI_COMCFG_OEASTEX_Msk        (0x10000UL)    /*!< OEASTEX (Bitfield-Mask: 0x01)                         */
40342  #define R_XSPI_COMCFG_OENEGEX_Pos        (17UL)         /*!< OENEGEX (Bit 17)                                      */
40343  #define R_XSPI_COMCFG_OENEGEX_Msk        (0x20000UL)    /*!< OENEGEX (Bitfield-Mask: 0x01)                         */
40344 /* ========================================================  BMCFGCH  ======================================================== */
40345  #define R_XSPI_BMCFGCH_WRMD_Pos          (0UL)          /*!< WRMD (Bit 0)                                          */
40346  #define R_XSPI_BMCFGCH_WRMD_Msk          (0x1UL)        /*!< WRMD (Bitfield-Mask: 0x01)                            */
40347  #define R_XSPI_BMCFGCH_MWRCOMB_Pos       (7UL)          /*!< MWRCOMB (Bit 7)                                       */
40348  #define R_XSPI_BMCFGCH_MWRCOMB_Msk       (0x80UL)       /*!< MWRCOMB (Bitfield-Mask: 0x01)                         */
40349  #define R_XSPI_BMCFGCH_MWRSIZE_Pos       (8UL)          /*!< MWRSIZE (Bit 8)                                       */
40350  #define R_XSPI_BMCFGCH_MWRSIZE_Msk       (0xff00UL)     /*!< MWRSIZE (Bitfield-Mask: 0xff)                         */
40351  #define R_XSPI_BMCFGCH_PREEN_Pos         (16UL)         /*!< PREEN (Bit 16)                                        */
40352  #define R_XSPI_BMCFGCH_PREEN_Msk         (0x10000UL)    /*!< PREEN (Bitfield-Mask: 0x01)                           */
40353  #define R_XSPI_BMCFGCH_CMBTIM_Pos        (24UL)         /*!< CMBTIM (Bit 24)                                       */
40354  #define R_XSPI_BMCFGCH_CMBTIM_Msk        (0xff000000UL) /*!< CMBTIM (Bitfield-Mask: 0xff)                          */
40355 /* =======================================================  LIOCFGCS  ======================================================== */
40356  #define R_XSPI_LIOCFGCS_PRTMD_Pos        (0UL)          /*!< PRTMD (Bit 0)                                         */
40357  #define R_XSPI_LIOCFGCS_PRTMD_Msk        (0x3ffUL)      /*!< PRTMD (Bitfield-Mask: 0x3ff)                          */
40358  #define R_XSPI_LIOCFGCS_LATEMD_Pos       (10UL)         /*!< LATEMD (Bit 10)                                       */
40359  #define R_XSPI_LIOCFGCS_LATEMD_Msk       (0x400UL)      /*!< LATEMD (Bitfield-Mask: 0x01)                          */
40360  #define R_XSPI_LIOCFGCS_WRMSKMD_Pos      (11UL)         /*!< WRMSKMD (Bit 11)                                      */
40361  #define R_XSPI_LIOCFGCS_WRMSKMD_Msk      (0x800UL)      /*!< WRMSKMD (Bitfield-Mask: 0x01)                         */
40362  #define R_XSPI_LIOCFGCS_CSMIN_Pos        (16UL)         /*!< CSMIN (Bit 16)                                        */
40363  #define R_XSPI_LIOCFGCS_CSMIN_Msk        (0xf0000UL)    /*!< CSMIN (Bitfield-Mask: 0x0f)                           */
40364  #define R_XSPI_LIOCFGCS_CSASTEX_Pos      (20UL)         /*!< CSASTEX (Bit 20)                                      */
40365  #define R_XSPI_LIOCFGCS_CSASTEX_Msk      (0x100000UL)   /*!< CSASTEX (Bitfield-Mask: 0x01)                         */
40366  #define R_XSPI_LIOCFGCS_CSNEGEX_Pos      (21UL)         /*!< CSNEGEX (Bit 21)                                      */
40367  #define R_XSPI_LIOCFGCS_CSNEGEX_Msk      (0x200000UL)   /*!< CSNEGEX (Bitfield-Mask: 0x01)                         */
40368  #define R_XSPI_LIOCFGCS_SDRDRV_Pos       (22UL)         /*!< SDRDRV (Bit 22)                                       */
40369  #define R_XSPI_LIOCFGCS_SDRDRV_Msk       (0x400000UL)   /*!< SDRDRV (Bitfield-Mask: 0x01)                          */
40370  #define R_XSPI_LIOCFGCS_SDRSMPMD_Pos     (23UL)         /*!< SDRSMPMD (Bit 23)                                     */
40371  #define R_XSPI_LIOCFGCS_SDRSMPMD_Msk     (0x800000UL)   /*!< SDRSMPMD (Bitfield-Mask: 0x01)                        */
40372  #define R_XSPI_LIOCFGCS_SDRSMPSFT_Pos    (24UL)         /*!< SDRSMPSFT (Bit 24)                                    */
40373  #define R_XSPI_LIOCFGCS_SDRSMPSFT_Msk    (0xf000000UL)  /*!< SDRSMPSFT (Bitfield-Mask: 0x0f)                       */
40374  #define R_XSPI_LIOCFGCS_DDRSMPEX_Pos     (28UL)         /*!< DDRSMPEX (Bit 28)                                     */
40375  #define R_XSPI_LIOCFGCS_DDRSMPEX_Msk     (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f)                        */
40376 /* ========================================================  ABMCFG  ========================================================= */
40377  #define R_XSPI_ABMCFG_ODRMD_Pos          (0UL)          /*!< ODRMD (Bit 0)                                         */
40378  #define R_XSPI_ABMCFG_ODRMD_Msk          (0x3UL)        /*!< ODRMD (Bitfield-Mask: 0x03)                           */
40379  #define R_XSPI_ABMCFG_CHSEL_Pos          (16UL)         /*!< CHSEL (Bit 16)                                        */
40380  #define R_XSPI_ABMCFG_CHSEL_Msk          (0xffff0000UL) /*!< CHSEL (Bitfield-Mask: 0xffff)                         */
40381 /* ========================================================  BMCTL0  ========================================================= */
40382  #define R_XSPI_BMCTL0_CH0CS0ACC_Pos      (0UL)          /*!< CH0CS0ACC (Bit 0)                                     */
40383  #define R_XSPI_BMCTL0_CH0CS0ACC_Msk      (0x3UL)        /*!< CH0CS0ACC (Bitfield-Mask: 0x03)                       */
40384  #define R_XSPI_BMCTL0_CH0CS1ACC_Pos      (2UL)          /*!< CH0CS1ACC (Bit 2)                                     */
40385  #define R_XSPI_BMCTL0_CH0CS1ACC_Msk      (0xcUL)        /*!< CH0CS1ACC (Bitfield-Mask: 0x03)                       */
40386  #define R_XSPI_BMCTL0_CH1CS0ACC_Pos      (4UL)          /*!< CH1CS0ACC (Bit 4)                                     */
40387  #define R_XSPI_BMCTL0_CH1CS0ACC_Msk      (0x30UL)       /*!< CH1CS0ACC (Bitfield-Mask: 0x03)                       */
40388  #define R_XSPI_BMCTL0_CH1CS1ACC_Pos      (6UL)          /*!< CH1CS1ACC (Bit 6)                                     */
40389  #define R_XSPI_BMCTL0_CH1CS1ACC_Msk      (0xc0UL)       /*!< CH1CS1ACC (Bitfield-Mask: 0x03)                       */
40390 /* ========================================================  BMCTL1  ========================================================= */
40391  #define R_XSPI_BMCTL1_MWRPUSHCH_Pos      (8UL)          /*!< MWRPUSHCH (Bit 8)                                     */
40392  #define R_XSPI_BMCTL1_MWRPUSHCH_Msk      (0x100UL)      /*!< MWRPUSHCH (Bitfield-Mask: 0x01)                       */
40393  #define R_XSPI_BMCTL1_PBUFCLRCH_Pos      (10UL)         /*!< PBUFCLRCH (Bit 10)                                    */
40394  #define R_XSPI_BMCTL1_PBUFCLRCH_Msk      (0x400UL)      /*!< PBUFCLRCH (Bitfield-Mask: 0x01)                       */
40395 /* ========================================================  CMCTLCH  ======================================================== */
40396  #define R_XSPI_CMCTLCH_XIPENCODE_Pos     (0UL)          /*!< XIPENCODE (Bit 0)                                     */
40397  #define R_XSPI_CMCTLCH_XIPENCODE_Msk     (0xffUL)       /*!< XIPENCODE (Bitfield-Mask: 0xff)                       */
40398  #define R_XSPI_CMCTLCH_XIPEXCODE_Pos     (8UL)          /*!< XIPEXCODE (Bit 8)                                     */
40399  #define R_XSPI_CMCTLCH_XIPEXCODE_Msk     (0xff00UL)     /*!< XIPEXCODE (Bitfield-Mask: 0xff)                       */
40400  #define R_XSPI_CMCTLCH_XIPEN_Pos         (16UL)         /*!< XIPEN (Bit 16)                                        */
40401  #define R_XSPI_CMCTLCH_XIPEN_Msk         (0x10000UL)    /*!< XIPEN (Bitfield-Mask: 0x01)                           */
40402 /* ========================================================  CDCTL0  ========================================================= */
40403  #define R_XSPI_CDCTL0_TRREQ_Pos          (0UL)          /*!< TRREQ (Bit 0)                                         */
40404  #define R_XSPI_CDCTL0_TRREQ_Msk          (0x1UL)        /*!< TRREQ (Bitfield-Mask: 0x01)                           */
40405  #define R_XSPI_CDCTL0_PERMD_Pos          (1UL)          /*!< PERMD (Bit 1)                                         */
40406  #define R_XSPI_CDCTL0_PERMD_Msk          (0x2UL)        /*!< PERMD (Bitfield-Mask: 0x01)                           */
40407  #define R_XSPI_CDCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
40408  #define R_XSPI_CDCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
40409  #define R_XSPI_CDCTL0_TRNUM_Pos          (4UL)          /*!< TRNUM (Bit 4)                                         */
40410  #define R_XSPI_CDCTL0_TRNUM_Msk          (0x30UL)       /*!< TRNUM (Bitfield-Mask: 0x03)                           */
40411  #define R_XSPI_CDCTL0_PERITV_Pos         (16UL)         /*!< PERITV (Bit 16)                                       */
40412  #define R_XSPI_CDCTL0_PERITV_Msk         (0x1f0000UL)   /*!< PERITV (Bitfield-Mask: 0x1f)                          */
40413  #define R_XSPI_CDCTL0_PERREP_Pos         (24UL)         /*!< PERREP (Bit 24)                                       */
40414  #define R_XSPI_CDCTL0_PERREP_Msk         (0xf000000UL)  /*!< PERREP (Bitfield-Mask: 0x0f)                          */
40415 /* ========================================================  CDCTL1  ========================================================= */
40416  #define R_XSPI_CDCTL1_PEREXP_Pos         (0UL)          /*!< PEREXP (Bit 0)                                        */
40417  #define R_XSPI_CDCTL1_PEREXP_Msk         (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff)                    */
40418 /* ========================================================  CDCTL2  ========================================================= */
40419  #define R_XSPI_CDCTL2_PERMSK_Pos         (0UL)          /*!< PERMSK (Bit 0)                                        */
40420  #define R_XSPI_CDCTL2_PERMSK_Msk         (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff)                    */
40421 /* ========================================================  LPCTL0  ========================================================= */
40422  #define R_XSPI_LPCTL0_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
40423  #define R_XSPI_LPCTL0_PATREQ_Msk         (0x1UL)        /*!< PATREQ (Bitfield-Mask: 0x01)                          */
40424  #define R_XSPI_LPCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
40425  #define R_XSPI_LPCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
40426  #define R_XSPI_LPCTL0_XDPIN_Pos          (4UL)          /*!< XDPIN (Bit 4)                                         */
40427  #define R_XSPI_LPCTL0_XDPIN_Msk          (0x30UL)       /*!< XDPIN (Bitfield-Mask: 0x03)                           */
40428  #define R_XSPI_LPCTL0_XD1LEN_Pos         (16UL)         /*!< XD1LEN (Bit 16)                                       */
40429  #define R_XSPI_LPCTL0_XD1LEN_Msk         (0x1f0000UL)   /*!< XD1LEN (Bitfield-Mask: 0x1f)                          */
40430  #define R_XSPI_LPCTL0_XD1VAL_Pos         (23UL)         /*!< XD1VAL (Bit 23)                                       */
40431  #define R_XSPI_LPCTL0_XD1VAL_Msk         (0x800000UL)   /*!< XD1VAL (Bitfield-Mask: 0x01)                          */
40432  #define R_XSPI_LPCTL0_XD2LEN_Pos         (24UL)         /*!< XD2LEN (Bit 24)                                       */
40433  #define R_XSPI_LPCTL0_XD2LEN_Msk         (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f)                          */
40434  #define R_XSPI_LPCTL0_XD2VAL_Pos         (31UL)         /*!< XD2VAL (Bit 31)                                       */
40435  #define R_XSPI_LPCTL0_XD2VAL_Msk         (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01)                          */
40436 /* ========================================================  LPCTL1  ========================================================= */
40437  #define R_XSPI_LPCTL1_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
40438  #define R_XSPI_LPCTL1_PATREQ_Msk         (0x3UL)        /*!< PATREQ (Bitfield-Mask: 0x03)                          */
40439  #define R_XSPI_LPCTL1_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
40440  #define R_XSPI_LPCTL1_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
40441  #define R_XSPI_LPCTL1_RSTREP_Pos         (4UL)          /*!< RSTREP (Bit 4)                                        */
40442  #define R_XSPI_LPCTL1_RSTREP_Msk         (0x30UL)       /*!< RSTREP (Bitfield-Mask: 0x03)                          */
40443  #define R_XSPI_LPCTL1_RSTWID_Pos         (8UL)          /*!< RSTWID (Bit 8)                                        */
40444  #define R_XSPI_LPCTL1_RSTWID_Msk         (0x700UL)      /*!< RSTWID (Bitfield-Mask: 0x07)                          */
40445  #define R_XSPI_LPCTL1_RSTSU_Pos          (12UL)         /*!< RSTSU (Bit 12)                                        */
40446  #define R_XSPI_LPCTL1_RSTSU_Msk          (0x7000UL)     /*!< RSTSU (Bitfield-Mask: 0x07)                           */
40447 /* ========================================================  LIOCTL  ========================================================= */
40448  #define R_XSPI_LIOCTL_WPCS_Pos           (0UL)          /*!< WPCS (Bit 0)                                          */
40449  #define R_XSPI_LIOCTL_WPCS_Msk           (0x1UL)        /*!< WPCS (Bitfield-Mask: 0x01)                            */
40450  #define R_XSPI_LIOCTL_RSTCS_Pos          (16UL)         /*!< RSTCS (Bit 16)                                        */
40451  #define R_XSPI_LIOCTL_RSTCS_Msk          (0x10000UL)    /*!< RSTCS (Bitfield-Mask: 0x01)                           */
40452 /* ========================================================  VERSTT  ========================================================= */
40453  #define R_XSPI_VERSTT_VER_Pos            (0UL)          /*!< VER (Bit 0)                                           */
40454  #define R_XSPI_VERSTT_VER_Msk            (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff)                       */
40455 /* ========================================================  COMSTT  ========================================================= */
40456  #define R_XSPI_COMSTT_MEMACCCH_Pos       (0UL)          /*!< MEMACCCH (Bit 0)                                      */
40457  #define R_XSPI_COMSTT_MEMACCCH_Msk       (0x1UL)        /*!< MEMACCCH (Bitfield-Mask: 0x01)                        */
40458  #define R_XSPI_COMSTT_PBUFNECH_Pos       (4UL)          /*!< PBUFNECH (Bit 4)                                      */
40459  #define R_XSPI_COMSTT_PBUFNECH_Msk       (0x10UL)       /*!< PBUFNECH (Bitfield-Mask: 0x01)                        */
40460  #define R_XSPI_COMSTT_WRBUFNECH_Pos      (6UL)          /*!< WRBUFNECH (Bit 6)                                     */
40461  #define R_XSPI_COMSTT_WRBUFNECH_Msk      (0x40UL)       /*!< WRBUFNECH (Bitfield-Mask: 0x01)                       */
40462  #define R_XSPI_COMSTT_ECSCS_Pos          (16UL)         /*!< ECSCS (Bit 16)                                        */
40463  #define R_XSPI_COMSTT_ECSCS_Msk          (0x10000UL)    /*!< ECSCS (Bitfield-Mask: 0x01)                           */
40464  #define R_XSPI_COMSTT_INTCS_Pos          (17UL)         /*!< INTCS (Bit 17)                                        */
40465  #define R_XSPI_COMSTT_INTCS_Msk          (0x20000UL)    /*!< INTCS (Bitfield-Mask: 0x01)                           */
40466  #define R_XSPI_COMSTT_RSTOCS_Pos         (18UL)         /*!< RSTOCS (Bit 18)                                       */
40467  #define R_XSPI_COMSTT_RSTOCS_Msk         (0x40000UL)    /*!< RSTOCS (Bitfield-Mask: 0x01)                          */
40468 /* ========================================================  CASTTCS  ======================================================== */
40469  #define R_XSPI_CASTTCS_CASUC_Pos         (0UL)          /*!< CASUC (Bit 0)                                         */
40470  #define R_XSPI_CASTTCS_CASUC_Msk         (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff)                     */
40471 /* =========================================================  INTS  ========================================================== */
40472  #define R_XSPI_INTS_CMDCMP_Pos           (0UL)          /*!< CMDCMP (Bit 0)                                        */
40473  #define R_XSPI_INTS_CMDCMP_Msk           (0x1UL)        /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
40474  #define R_XSPI_INTS_PATCMP_Pos           (1UL)          /*!< PATCMP (Bit 1)                                        */
40475  #define R_XSPI_INTS_PATCMP_Msk           (0x2UL)        /*!< PATCMP (Bitfield-Mask: 0x01)                          */
40476  #define R_XSPI_INTS_INICMP_Pos           (2UL)          /*!< INICMP (Bit 2)                                        */
40477  #define R_XSPI_INTS_INICMP_Msk           (0x4UL)        /*!< INICMP (Bitfield-Mask: 0x01)                          */
40478  #define R_XSPI_INTS_PERTO_Pos            (3UL)          /*!< PERTO (Bit 3)                                         */
40479  #define R_XSPI_INTS_PERTO_Msk            (0x8UL)        /*!< PERTO (Bitfield-Mask: 0x01)                           */
40480  #define R_XSPI_INTS_DSTOCS_Pos           (4UL)          /*!< DSTOCS (Bit 4)                                        */
40481  #define R_XSPI_INTS_DSTOCS_Msk           (0x10UL)       /*!< DSTOCS (Bitfield-Mask: 0x01)                          */
40482  #define R_XSPI_INTS_ECSCS_Pos            (8UL)          /*!< ECSCS (Bit 8)                                         */
40483  #define R_XSPI_INTS_ECSCS_Msk            (0x100UL)      /*!< ECSCS (Bitfield-Mask: 0x01)                           */
40484  #define R_XSPI_INTS_INTCS_Pos            (12UL)         /*!< INTCS (Bit 12)                                        */
40485  #define R_XSPI_INTS_INTCS_Msk            (0x1000UL)     /*!< INTCS (Bitfield-Mask: 0x01)                           */
40486  #define R_XSPI_INTS_BRGOFCH_Pos          (16UL)         /*!< BRGOFCH (Bit 16)                                      */
40487  #define R_XSPI_INTS_BRGOFCH_Msk          (0x10000UL)    /*!< BRGOFCH (Bitfield-Mask: 0x01)                         */
40488  #define R_XSPI_INTS_BRGUFCH_Pos          (18UL)         /*!< BRGUFCH (Bit 18)                                      */
40489  #define R_XSPI_INTS_BRGUFCH_Msk          (0x40000UL)    /*!< BRGUFCH (Bitfield-Mask: 0x01)                         */
40490  #define R_XSPI_INTS_BUSERRCH_Pos         (20UL)         /*!< BUSERRCH (Bit 20)                                     */
40491  #define R_XSPI_INTS_BUSERRCH_Msk         (0x100000UL)   /*!< BUSERRCH (Bitfield-Mask: 0x01)                        */
40492  #define R_XSPI_INTS_CAFAILCS_Pos         (28UL)         /*!< CAFAILCS (Bit 28)                                     */
40493  #define R_XSPI_INTS_CAFAILCS_Msk         (0x10000000UL) /*!< CAFAILCS (Bitfield-Mask: 0x01)                        */
40494  #define R_XSPI_INTS_CASUCCS_Pos          (30UL)         /*!< CASUCCS (Bit 30)                                      */
40495  #define R_XSPI_INTS_CASUCCS_Msk          (0x40000000UL) /*!< CASUCCS (Bitfield-Mask: 0x01)                         */
40496 /* =========================================================  INTC  ========================================================== */
40497  #define R_XSPI_INTC_CMDCMPC_Pos          (0UL)          /*!< CMDCMPC (Bit 0)                                       */
40498  #define R_XSPI_INTC_CMDCMPC_Msk          (0x1UL)        /*!< CMDCMPC (Bitfield-Mask: 0x01)                         */
40499  #define R_XSPI_INTC_PATCMPC_Pos          (1UL)          /*!< PATCMPC (Bit 1)                                       */
40500  #define R_XSPI_INTC_PATCMPC_Msk          (0x2UL)        /*!< PATCMPC (Bitfield-Mask: 0x01)                         */
40501  #define R_XSPI_INTC_INICMPC_Pos          (2UL)          /*!< INICMPC (Bit 2)                                       */
40502  #define R_XSPI_INTC_INICMPC_Msk          (0x4UL)        /*!< INICMPC (Bitfield-Mask: 0x01)                         */
40503  #define R_XSPI_INTC_PERTOC_Pos           (3UL)          /*!< PERTOC (Bit 3)                                        */
40504  #define R_XSPI_INTC_PERTOC_Msk           (0x8UL)        /*!< PERTOC (Bitfield-Mask: 0x01)                          */
40505  #define R_XSPI_INTC_DSTOCSC_Pos          (4UL)          /*!< DSTOCSC (Bit 4)                                       */
40506  #define R_XSPI_INTC_DSTOCSC_Msk          (0x10UL)       /*!< DSTOCSC (Bitfield-Mask: 0x01)                         */
40507  #define R_XSPI_INTC_ECSCSC_Pos           (8UL)          /*!< ECSCSC (Bit 8)                                        */
40508  #define R_XSPI_INTC_ECSCSC_Msk           (0x100UL)      /*!< ECSCSC (Bitfield-Mask: 0x01)                          */
40509  #define R_XSPI_INTC_INTCSC_Pos           (12UL)         /*!< INTCSC (Bit 12)                                       */
40510  #define R_XSPI_INTC_INTCSC_Msk           (0x1000UL)     /*!< INTCSC (Bitfield-Mask: 0x01)                          */
40511  #define R_XSPI_INTC_BRGOFCHC_Pos         (16UL)         /*!< BRGOFCHC (Bit 16)                                     */
40512  #define R_XSPI_INTC_BRGOFCHC_Msk         (0x10000UL)    /*!< BRGOFCHC (Bitfield-Mask: 0x01)                        */
40513  #define R_XSPI_INTC_BRGUFCHC_Pos         (18UL)         /*!< BRGUFCHC (Bit 18)                                     */
40514  #define R_XSPI_INTC_BRGUFCHC_Msk         (0x40000UL)    /*!< BRGUFCHC (Bitfield-Mask: 0x01)                        */
40515  #define R_XSPI_INTC_BUSERRCHC_Pos        (20UL)         /*!< BUSERRCHC (Bit 20)                                    */
40516  #define R_XSPI_INTC_BUSERRCHC_Msk        (0x100000UL)   /*!< BUSERRCHC (Bitfield-Mask: 0x01)                       */
40517  #define R_XSPI_INTC_CAFAILCSC_Pos        (28UL)         /*!< CAFAILCSC (Bit 28)                                    */
40518  #define R_XSPI_INTC_CAFAILCSC_Msk        (0x10000000UL) /*!< CAFAILCSC (Bitfield-Mask: 0x01)                       */
40519  #define R_XSPI_INTC_CASUCCSC_Pos         (30UL)         /*!< CASUCCSC (Bit 30)                                     */
40520  #define R_XSPI_INTC_CASUCCSC_Msk         (0x40000000UL) /*!< CASUCCSC (Bitfield-Mask: 0x01)                        */
40521 /* =========================================================  INTE  ========================================================== */
40522  #define R_XSPI_INTE_CMDCMPE_Pos          (0UL)          /*!< CMDCMPE (Bit 0)                                       */
40523  #define R_XSPI_INTE_CMDCMPE_Msk          (0x1UL)        /*!< CMDCMPE (Bitfield-Mask: 0x01)                         */
40524  #define R_XSPI_INTE_PATCMPE_Pos          (1UL)          /*!< PATCMPE (Bit 1)                                       */
40525  #define R_XSPI_INTE_PATCMPE_Msk          (0x2UL)        /*!< PATCMPE (Bitfield-Mask: 0x01)                         */
40526  #define R_XSPI_INTE_INICMPE_Pos          (2UL)          /*!< INICMPE (Bit 2)                                       */
40527  #define R_XSPI_INTE_INICMPE_Msk          (0x4UL)        /*!< INICMPE (Bitfield-Mask: 0x01)                         */
40528  #define R_XSPI_INTE_PERTOE_Pos           (3UL)          /*!< PERTOE (Bit 3)                                        */
40529  #define R_XSPI_INTE_PERTOE_Msk           (0x8UL)        /*!< PERTOE (Bitfield-Mask: 0x01)                          */
40530  #define R_XSPI_INTE_DSTOCSE_Pos          (4UL)          /*!< DSTOCSE (Bit 4)                                       */
40531  #define R_XSPI_INTE_DSTOCSE_Msk          (0x10UL)       /*!< DSTOCSE (Bitfield-Mask: 0x01)                         */
40532  #define R_XSPI_INTE_ECSCSE_Pos           (8UL)          /*!< ECSCSE (Bit 8)                                        */
40533  #define R_XSPI_INTE_ECSCSE_Msk           (0x100UL)      /*!< ECSCSE (Bitfield-Mask: 0x01)                          */
40534  #define R_XSPI_INTE_INTCSE_Pos           (12UL)         /*!< INTCSE (Bit 12)                                       */
40535  #define R_XSPI_INTE_INTCSE_Msk           (0x1000UL)     /*!< INTCSE (Bitfield-Mask: 0x01)                          */
40536  #define R_XSPI_INTE_BRGOFCHE_Pos         (16UL)         /*!< BRGOFCHE (Bit 16)                                     */
40537  #define R_XSPI_INTE_BRGOFCHE_Msk         (0x10000UL)    /*!< BRGOFCHE (Bitfield-Mask: 0x01)                        */
40538  #define R_XSPI_INTE_BRGUFCHE_Pos         (18UL)         /*!< BRGUFCHE (Bit 18)                                     */
40539  #define R_XSPI_INTE_BRGUFCHE_Msk         (0x40000UL)    /*!< BRGUFCHE (Bitfield-Mask: 0x01)                        */
40540  #define R_XSPI_INTE_BUSERRCHE_Pos        (20UL)         /*!< BUSERRCHE (Bit 20)                                    */
40541  #define R_XSPI_INTE_BUSERRCHE_Msk        (0x100000UL)   /*!< BUSERRCHE (Bitfield-Mask: 0x01)                       */
40542  #define R_XSPI_INTE_CAFAILCSE_Pos        (28UL)         /*!< CAFAILCSE (Bit 28)                                    */
40543  #define R_XSPI_INTE_CAFAILCSE_Msk        (0x10000000UL) /*!< CAFAILCSE (Bitfield-Mask: 0x01)                       */
40544  #define R_XSPI_INTE_CASUCCSE_Pos         (30UL)         /*!< CASUCCSE (Bit 30)                                     */
40545  #define R_XSPI_INTE_CASUCCSE_Msk         (0x40000000UL) /*!< CASUCCSE (Bitfield-Mask: 0x01)                        */
40546 
40547 /* =========================================================================================================================== */
40548 /* ================                                           R_CEU                                           ================ */
40549 /* =========================================================================================================================== */
40550 
40551 /* =========================================================  CAPSR  ========================================================= */
40552  #define R_CEU_CAPSR_CE_Pos              (0UL)          /*!< CE (Bit 0)                                            */
40553  #define R_CEU_CAPSR_CE_Msk              (0x1UL)        /*!< CE (Bitfield-Mask: 0x01)                              */
40554  #define R_CEU_CAPSR_CPKIL_Pos           (16UL)         /*!< CPKIL (Bit 16)                                        */
40555  #define R_CEU_CAPSR_CPKIL_Msk           (0x10000UL)    /*!< CPKIL (Bitfield-Mask: 0x01)                           */
40556 /* =========================================================  CAPCR  ========================================================= */
40557  #define R_CEU_CAPCR_CTNCP_Pos           (16UL)         /*!< CTNCP (Bit 16)                                        */
40558  #define R_CEU_CAPCR_CTNCP_Msk           (0x10000UL)    /*!< CTNCP (Bitfield-Mask: 0x01)                           */
40559  #define R_CEU_CAPCR_MTCM_Pos            (20UL)         /*!< MTCM (Bit 20)                                         */
40560  #define R_CEU_CAPCR_MTCM_Msk            (0x300000UL)   /*!< MTCM (Bitfield-Mask: 0x03)                            */
40561  #define R_CEU_CAPCR_FDRP_Pos            (24UL)         /*!< FDRP (Bit 24)                                         */
40562  #define R_CEU_CAPCR_FDRP_Msk            (0xff000000UL) /*!< FDRP (Bitfield-Mask: 0xff)                            */
40563 /* =========================================================  CAMCR  ========================================================= */
40564  #define R_CEU_CAMCR_HDPOL_Pos           (0UL)          /*!< HDPOL (Bit 0)                                         */
40565  #define R_CEU_CAMCR_HDPOL_Msk           (0x1UL)        /*!< HDPOL (Bitfield-Mask: 0x01)                           */
40566  #define R_CEU_CAMCR_VDPOL_Pos           (1UL)          /*!< VDPOL (Bit 1)                                         */
40567  #define R_CEU_CAMCR_VDPOL_Msk           (0x2UL)        /*!< VDPOL (Bitfield-Mask: 0x01)                           */
40568  #define R_CEU_CAMCR_JPG_Pos             (4UL)          /*!< JPG (Bit 4)                                           */
40569  #define R_CEU_CAMCR_JPG_Msk             (0x30UL)       /*!< JPG (Bitfield-Mask: 0x03)                             */
40570  #define R_CEU_CAMCR_DTARY_Pos           (8UL)          /*!< DTARY (Bit 8)                                         */
40571  #define R_CEU_CAMCR_DTARY_Msk           (0x300UL)      /*!< DTARY (Bitfield-Mask: 0x03)                           */
40572  #define R_CEU_CAMCR_DTIF_Pos            (12UL)         /*!< DTIF (Bit 12)                                         */
40573  #define R_CEU_CAMCR_DTIF_Msk            (0x1000UL)     /*!< DTIF (Bitfield-Mask: 0x01)                            */
40574  #define R_CEU_CAMCR_FLDPOL_Pos          (16UL)         /*!< FLDPOL (Bit 16)                                       */
40575  #define R_CEU_CAMCR_FLDPOL_Msk          (0x10000UL)    /*!< FLDPOL (Bitfield-Mask: 0x01)                          */
40576  #define R_CEU_CAMCR_DSEL_Pos            (24UL)         /*!< DSEL (Bit 24)                                         */
40577  #define R_CEU_CAMCR_DSEL_Msk            (0x1000000UL)  /*!< DSEL (Bitfield-Mask: 0x01)                            */
40578  #define R_CEU_CAMCR_FLDSEL_Pos          (25UL)         /*!< FLDSEL (Bit 25)                                       */
40579  #define R_CEU_CAMCR_FLDSEL_Msk          (0x2000000UL)  /*!< FLDSEL (Bitfield-Mask: 0x01)                          */
40580  #define R_CEU_CAMCR_HDSEL_Pos           (26UL)         /*!< HDSEL (Bit 26)                                        */
40581  #define R_CEU_CAMCR_HDSEL_Msk           (0x4000000UL)  /*!< HDSEL (Bitfield-Mask: 0x01)                           */
40582  #define R_CEU_CAMCR_VDSEL_Pos           (27UL)         /*!< VDSEL (Bit 27)                                        */
40583  #define R_CEU_CAMCR_VDSEL_Msk           (0x8000000UL)  /*!< VDSEL (Bitfield-Mask: 0x01)                           */
40584 /* =========================================================  CMCYR  ========================================================= */
40585  #define R_CEU_CMCYR_HCYL_Pos            (0UL)          /*!< HCYL (Bit 0)                                          */
40586  #define R_CEU_CMCYR_HCYL_Msk            (0x3fffUL)     /*!< HCYL (Bitfield-Mask: 0x3fff)                          */
40587  #define R_CEU_CMCYR_VCYL_Pos            (16UL)         /*!< VCYL (Bit 16)                                         */
40588  #define R_CEU_CMCYR_VCYL_Msk            (0x3fff0000UL) /*!< VCYL (Bitfield-Mask: 0x3fff)                          */
40589 /* =========================================================  CAMOR  ========================================================= */
40590  #define R_CEU_CAMOR_HOFST_Pos           (0UL)          /*!< HOFST (Bit 0)                                         */
40591  #define R_CEU_CAMOR_HOFST_Msk           (0x1fffUL)     /*!< HOFST (Bitfield-Mask: 0x1fff)                         */
40592  #define R_CEU_CAMOR_VOFST_Pos           (16UL)         /*!< VOFST (Bit 16)                                        */
40593  #define R_CEU_CAMOR_VOFST_Msk           (0xfff0000UL)  /*!< VOFST (Bitfield-Mask: 0xfff)                          */
40594 /* =========================================================  CAPWR  ========================================================= */
40595  #define R_CEU_CAPWR_HWDTH_Pos           (0UL)          /*!< HWDTH (Bit 0)                                         */
40596  #define R_CEU_CAPWR_HWDTH_Msk           (0x1fffUL)     /*!< HWDTH (Bitfield-Mask: 0x1fff)                         */
40597  #define R_CEU_CAPWR_VWDTH_Pos           (16UL)         /*!< VWDTH (Bit 16)                                        */
40598  #define R_CEU_CAPWR_VWDTH_Msk           (0xfff0000UL)  /*!< VWDTH (Bitfield-Mask: 0xfff)                          */
40599 /* =========================================================  CAIFR  ========================================================= */
40600  #define R_CEU_CAIFR_FCI_Pos             (0UL)          /*!< FCI (Bit 0)                                           */
40601  #define R_CEU_CAIFR_FCI_Msk             (0x3UL)        /*!< FCI (Bitfield-Mask: 0x03)                             */
40602  #define R_CEU_CAIFR_CIM_Pos             (4UL)          /*!< CIM (Bit 4)                                           */
40603  #define R_CEU_CAIFR_CIM_Msk             (0x10UL)       /*!< CIM (Bitfield-Mask: 0x01)                             */
40604  #define R_CEU_CAIFR_IFS_Pos             (8UL)          /*!< IFS (Bit 8)                                           */
40605  #define R_CEU_CAIFR_IFS_Msk             (0x100UL)      /*!< IFS (Bitfield-Mask: 0x01)                             */
40606 /* ========================================================  CRCNTR  ========================================================= */
40607  #define R_CEU_CRCNTR_RC_Pos             (0UL)          /*!< RC (Bit 0)                                            */
40608  #define R_CEU_CRCNTR_RC_Msk             (0x1UL)        /*!< RC (Bitfield-Mask: 0x01)                              */
40609  #define R_CEU_CRCNTR_RS_Pos             (1UL)          /*!< RS (Bit 1)                                            */
40610  #define R_CEU_CRCNTR_RS_Msk             (0x2UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
40611  #define R_CEU_CRCNTR_RVS_Pos            (4UL)          /*!< RVS (Bit 4)                                           */
40612  #define R_CEU_CRCNTR_RVS_Msk            (0x10UL)       /*!< RVS (Bitfield-Mask: 0x01)                             */
40613 /* ========================================================  CRCMPR  ========================================================= */
40614  #define R_CEU_CRCMPR_RA_Pos             (0UL)          /*!< RA (Bit 0)                                            */
40615  #define R_CEU_CRCMPR_RA_Msk             (0x1UL)        /*!< RA (Bitfield-Mask: 0x01)                              */
40616 /* =========================================================  CFLCR  ========================================================= */
40617  #define R_CEU_CFLCR_HFRAC_Pos           (0UL)          /*!< HFRAC (Bit 0)                                         */
40618  #define R_CEU_CFLCR_HFRAC_Msk           (0xfffUL)      /*!< HFRAC (Bitfield-Mask: 0xfff)                          */
40619  #define R_CEU_CFLCR_HMANT_Pos           (12UL)         /*!< HMANT (Bit 12)                                        */
40620  #define R_CEU_CFLCR_HMANT_Msk           (0xf000UL)     /*!< HMANT (Bitfield-Mask: 0x0f)                           */
40621  #define R_CEU_CFLCR_VFRAC_Pos           (16UL)         /*!< VFRAC (Bit 16)                                        */
40622  #define R_CEU_CFLCR_VFRAC_Msk           (0xfff0000UL)  /*!< VFRAC (Bitfield-Mask: 0xfff)                          */
40623  #define R_CEU_CFLCR_VMANT_Pos           (28UL)         /*!< VMANT (Bit 28)                                        */
40624  #define R_CEU_CFLCR_VMANT_Msk           (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f)                           */
40625 /* =========================================================  CFSZR  ========================================================= */
40626  #define R_CEU_CFSZR_HFCLP_Pos           (0UL)          /*!< HFCLP (Bit 0)                                         */
40627  #define R_CEU_CFSZR_HFCLP_Msk           (0xfffUL)      /*!< HFCLP (Bitfield-Mask: 0xfff)                          */
40628  #define R_CEU_CFSZR_VFCLP_Pos           (16UL)         /*!< VFCLP (Bit 16)                                        */
40629  #define R_CEU_CFSZR_VFCLP_Msk           (0xfff0000UL)  /*!< VFCLP (Bitfield-Mask: 0xfff)                          */
40630 /* =========================================================  CDWDR  ========================================================= */
40631  #define R_CEU_CDWDR_CHDW_Pos            (0UL)          /*!< CHDW (Bit 0)                                          */
40632  #define R_CEU_CDWDR_CHDW_Msk            (0x1fffUL)     /*!< CHDW (Bitfield-Mask: 0x1fff)                          */
40633 /* =========================================================  CDAYR  ========================================================= */
40634  #define R_CEU_CDAYR_CAYR_Pos            (0UL)          /*!< CAYR (Bit 0)                                          */
40635  #define R_CEU_CDAYR_CAYR_Msk            (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff)                      */
40636 /* =========================================================  CDACR  ========================================================= */
40637  #define R_CEU_CDACR_CACR_Pos            (0UL)          /*!< CACR (Bit 0)                                          */
40638  #define R_CEU_CDACR_CACR_Msk            (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff)                      */
40639 /* =========================================================  CDBYR  ========================================================= */
40640  #define R_CEU_CDBYR_CBYR_Pos            (0UL)          /*!< CBYR (Bit 0)                                          */
40641  #define R_CEU_CDBYR_CBYR_Msk            (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff)                      */
40642 /* =========================================================  CDBCR  ========================================================= */
40643  #define R_CEU_CDBCR_CBCR_Pos            (0UL)          /*!< CBCR (Bit 0)                                          */
40644  #define R_CEU_CDBCR_CBCR_Msk            (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff)                      */
40645 /* =========================================================  CBDSR  ========================================================= */
40646  #define R_CEU_CBDSR_CBVS_Pos            (0UL)          /*!< CBVS (Bit 0)                                          */
40647  #define R_CEU_CBDSR_CBVS_Msk            (0x7fffffUL)   /*!< CBVS (Bitfield-Mask: 0x7fffff)                        */
40648 /* =========================================================  CFWCR  ========================================================= */
40649  #define R_CEU_CFWCR_FWE_Pos             (0UL)          /*!< FWE (Bit 0)                                           */
40650  #define R_CEU_CFWCR_FWE_Msk             (0x1UL)        /*!< FWE (Bitfield-Mask: 0x01)                             */
40651  #define R_CEU_CFWCR_FWV_Pos             (5UL)          /*!< FWV (Bit 5)                                           */
40652  #define R_CEU_CFWCR_FWV_Msk             (0xffffffe0UL) /*!< FWV (Bitfield-Mask: 0x7ffffff)                        */
40653 /* =========================================================  CLFCR  ========================================================= */
40654  #define R_CEU_CLFCR_LPF_Pos             (0UL)          /*!< LPF (Bit 0)                                           */
40655  #define R_CEU_CLFCR_LPF_Msk             (0x1UL)        /*!< LPF (Bitfield-Mask: 0x01)                             */
40656 /* =========================================================  CDOCR  ========================================================= */
40657  #define R_CEU_CDOCR_COBS_Pos            (0UL)          /*!< COBS (Bit 0)                                          */
40658  #define R_CEU_CDOCR_COBS_Msk            (0x1UL)        /*!< COBS (Bitfield-Mask: 0x01)                            */
40659  #define R_CEU_CDOCR_COWS_Pos            (1UL)          /*!< COWS (Bit 1)                                          */
40660  #define R_CEU_CDOCR_COWS_Msk            (0x2UL)        /*!< COWS (Bitfield-Mask: 0x01)                            */
40661  #define R_CEU_CDOCR_COLS_Pos            (2UL)          /*!< COLS (Bit 2)                                          */
40662  #define R_CEU_CDOCR_COLS_Msk            (0x4UL)        /*!< COLS (Bitfield-Mask: 0x01)                            */
40663  #define R_CEU_CDOCR_CDS_Pos             (4UL)          /*!< CDS (Bit 4)                                           */
40664  #define R_CEU_CDOCR_CDS_Msk             (0x10UL)       /*!< CDS (Bitfield-Mask: 0x01)                             */
40665  #define R_CEU_CDOCR_CBE_Pos             (16UL)         /*!< CBE (Bit 16)                                          */
40666  #define R_CEU_CDOCR_CBE_Msk             (0x10000UL)    /*!< CBE (Bitfield-Mask: 0x01)                             */
40667 /* =========================================================  CEIER  ========================================================= */
40668  #define R_CEU_CEIER_CPEIE_Pos           (0UL)          /*!< CPEIE (Bit 0)                                         */
40669  #define R_CEU_CEIER_CPEIE_Msk           (0x1UL)        /*!< CPEIE (Bitfield-Mask: 0x01)                           */
40670  #define R_CEU_CEIER_CFEIE_Pos           (1UL)          /*!< CFEIE (Bit 1)                                         */
40671  #define R_CEU_CEIER_CFEIE_Msk           (0x2UL)        /*!< CFEIE (Bitfield-Mask: 0x01)                           */
40672  #define R_CEU_CEIER_IGRWIE_Pos          (4UL)          /*!< IGRWIE (Bit 4)                                        */
40673  #define R_CEU_CEIER_IGRWIE_Msk          (0x10UL)       /*!< IGRWIE (Bitfield-Mask: 0x01)                          */
40674  #define R_CEU_CEIER_HDIE_Pos            (8UL)          /*!< HDIE (Bit 8)                                          */
40675  #define R_CEU_CEIER_HDIE_Msk            (0x100UL)      /*!< HDIE (Bitfield-Mask: 0x01)                            */
40676  #define R_CEU_CEIER_VDIE_Pos            (9UL)          /*!< VDIE (Bit 9)                                          */
40677  #define R_CEU_CEIER_VDIE_Msk            (0x200UL)      /*!< VDIE (Bitfield-Mask: 0x01)                            */
40678  #define R_CEU_CEIER_CPBE1IE_Pos         (12UL)         /*!< CPBE1IE (Bit 12)                                      */
40679  #define R_CEU_CEIER_CPBE1IE_Msk         (0x1000UL)     /*!< CPBE1IE (Bitfield-Mask: 0x01)                         */
40680  #define R_CEU_CEIER_CPBE2IE_Pos         (13UL)         /*!< CPBE2IE (Bit 13)                                      */
40681  #define R_CEU_CEIER_CPBE2IE_Msk         (0x2000UL)     /*!< CPBE2IE (Bitfield-Mask: 0x01)                         */
40682  #define R_CEU_CEIER_CPBE3IE_Pos         (14UL)         /*!< CPBE3IE (Bit 14)                                      */
40683  #define R_CEU_CEIER_CPBE3IE_Msk         (0x4000UL)     /*!< CPBE3IE (Bitfield-Mask: 0x01)                         */
40684  #define R_CEU_CEIER_CPBE4IE_Pos         (15UL)         /*!< CPBE4IE (Bit 15)                                      */
40685  #define R_CEU_CEIER_CPBE4IE_Msk         (0x8000UL)     /*!< CPBE4IE (Bitfield-Mask: 0x01)                         */
40686  #define R_CEU_CEIER_CDTOFIE_Pos         (16UL)         /*!< CDTOFIE (Bit 16)                                      */
40687  #define R_CEU_CEIER_CDTOFIE_Msk         (0x10000UL)    /*!< CDTOFIE (Bitfield-Mask: 0x01)                         */
40688  #define R_CEU_CEIER_IGHSIE_Pos          (17UL)         /*!< IGHSIE (Bit 17)                                       */
40689  #define R_CEU_CEIER_IGHSIE_Msk          (0x20000UL)    /*!< IGHSIE (Bitfield-Mask: 0x01)                          */
40690  #define R_CEU_CEIER_IGVSIE_Pos          (18UL)         /*!< IGVSIE (Bit 18)                                       */
40691  #define R_CEU_CEIER_IGVSIE_Msk          (0x40000UL)    /*!< IGVSIE (Bitfield-Mask: 0x01)                          */
40692  #define R_CEU_CEIER_VBPIE_Pos           (20UL)         /*!< VBPIE (Bit 20)                                        */
40693  #define R_CEU_CEIER_VBPIE_Msk           (0x100000UL)   /*!< VBPIE (Bitfield-Mask: 0x01)                           */
40694  #define R_CEU_CEIER_FWFIE_Pos           (23UL)         /*!< FWFIE (Bit 23)                                        */
40695  #define R_CEU_CEIER_FWFIE_Msk           (0x800000UL)   /*!< FWFIE (Bitfield-Mask: 0x01)                           */
40696  #define R_CEU_CEIER_NHDIE_Pos           (24UL)         /*!< NHDIE (Bit 24)                                        */
40697  #define R_CEU_CEIER_NHDIE_Msk           (0x1000000UL)  /*!< NHDIE (Bitfield-Mask: 0x01)                           */
40698  #define R_CEU_CEIER_NVDIE_Pos           (25UL)         /*!< NVDIE (Bit 25)                                        */
40699  #define R_CEU_CEIER_NVDIE_Msk           (0x2000000UL)  /*!< NVDIE (Bitfield-Mask: 0x01)                           */
40700 /* =========================================================  CETCR  ========================================================= */
40701  #define R_CEU_CETCR_CPE_Pos             (0UL)          /*!< CPE (Bit 0)                                           */
40702  #define R_CEU_CETCR_CPE_Msk             (0x1UL)        /*!< CPE (Bitfield-Mask: 0x01)                             */
40703  #define R_CEU_CETCR_CFE_Pos             (1UL)          /*!< CFE (Bit 1)                                           */
40704  #define R_CEU_CETCR_CFE_Msk             (0x2UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
40705  #define R_CEU_CETCR_IGRW_Pos            (4UL)          /*!< IGRW (Bit 4)                                          */
40706  #define R_CEU_CETCR_IGRW_Msk            (0x10UL)       /*!< IGRW (Bitfield-Mask: 0x01)                            */
40707  #define R_CEU_CETCR_HD_Pos              (8UL)          /*!< HD (Bit 8)                                            */
40708  #define R_CEU_CETCR_HD_Msk              (0x100UL)      /*!< HD (Bitfield-Mask: 0x01)                              */
40709  #define R_CEU_CETCR_VD_Pos              (9UL)          /*!< VD (Bit 9)                                            */
40710  #define R_CEU_CETCR_VD_Msk              (0x200UL)      /*!< VD (Bitfield-Mask: 0x01)                              */
40711  #define R_CEU_CETCR_CPBE1_Pos           (12UL)         /*!< CPBE1 (Bit 12)                                        */
40712  #define R_CEU_CETCR_CPBE1_Msk           (0x1000UL)     /*!< CPBE1 (Bitfield-Mask: 0x01)                           */
40713  #define R_CEU_CETCR_CPBE2_Pos           (13UL)         /*!< CPBE2 (Bit 13)                                        */
40714  #define R_CEU_CETCR_CPBE2_Msk           (0x2000UL)     /*!< CPBE2 (Bitfield-Mask: 0x01)                           */
40715  #define R_CEU_CETCR_CPBE3_Pos           (14UL)         /*!< CPBE3 (Bit 14)                                        */
40716  #define R_CEU_CETCR_CPBE3_Msk           (0x4000UL)     /*!< CPBE3 (Bitfield-Mask: 0x01)                           */
40717  #define R_CEU_CETCR_CPBE4_Pos           (15UL)         /*!< CPBE4 (Bit 15)                                        */
40718  #define R_CEU_CETCR_CPBE4_Msk           (0x8000UL)     /*!< CPBE4 (Bitfield-Mask: 0x01)                           */
40719  #define R_CEU_CETCR_CDTOF_Pos           (16UL)         /*!< CDTOF (Bit 16)                                        */
40720  #define R_CEU_CETCR_CDTOF_Msk           (0x10000UL)    /*!< CDTOF (Bitfield-Mask: 0x01)                           */
40721  #define R_CEU_CETCR_IGHS_Pos            (17UL)         /*!< IGHS (Bit 17)                                         */
40722  #define R_CEU_CETCR_IGHS_Msk            (0x20000UL)    /*!< IGHS (Bitfield-Mask: 0x01)                            */
40723  #define R_CEU_CETCR_IGVS_Pos            (18UL)         /*!< IGVS (Bit 18)                                         */
40724  #define R_CEU_CETCR_IGVS_Msk            (0x40000UL)    /*!< IGVS (Bitfield-Mask: 0x01)                            */
40725  #define R_CEU_CETCR_VBP_Pos             (20UL)         /*!< VBP (Bit 20)                                          */
40726  #define R_CEU_CETCR_VBP_Msk             (0x100000UL)   /*!< VBP (Bitfield-Mask: 0x01)                             */
40727  #define R_CEU_CETCR_FWF_Pos             (23UL)         /*!< FWF (Bit 23)                                          */
40728  #define R_CEU_CETCR_FWF_Msk             (0x800000UL)   /*!< FWF (Bitfield-Mask: 0x01)                             */
40729  #define R_CEU_CETCR_NHD_Pos             (24UL)         /*!< NHD (Bit 24)                                          */
40730  #define R_CEU_CETCR_NHD_Msk             (0x1000000UL)  /*!< NHD (Bitfield-Mask: 0x01)                             */
40731  #define R_CEU_CETCR_NVD_Pos             (25UL)         /*!< NVD (Bit 25)                                          */
40732  #define R_CEU_CETCR_NVD_Msk             (0x2000000UL)  /*!< NVD (Bitfield-Mask: 0x01)                             */
40733 /* =========================================================  CSTSR  ========================================================= */
40734  #define R_CEU_CSTSR_CPTON_Pos           (0UL)          /*!< CPTON (Bit 0)                                         */
40735  #define R_CEU_CSTSR_CPTON_Msk           (0x1UL)        /*!< CPTON (Bitfield-Mask: 0x01)                           */
40736  #define R_CEU_CSTSR_CPFLD_Pos           (16UL)         /*!< CPFLD (Bit 16)                                        */
40737  #define R_CEU_CSTSR_CPFLD_Msk           (0x10000UL)    /*!< CPFLD (Bitfield-Mask: 0x01)                           */
40738  #define R_CEU_CSTSR_CRST_Pos            (24UL)         /*!< CRST (Bit 24)                                         */
40739  #define R_CEU_CSTSR_CRST_Msk            (0x1000000UL)  /*!< CRST (Bitfield-Mask: 0x01)                            */
40740 /* =========================================================  CDSSR  ========================================================= */
40741  #define R_CEU_CDSSR_CDSS_Pos            (0UL)          /*!< CDSS (Bit 0)                                          */
40742  #define R_CEU_CDSSR_CDSS_Msk            (0xffffffffUL) /*!< CDSS (Bitfield-Mask: 0xffffffff)                      */
40743 /* ========================================================  CDAYR2  ========================================================= */
40744  #define R_CEU_CDAYR2_CAYR2_Pos          (0UL)          /*!< CAYR2 (Bit 0)                                         */
40745  #define R_CEU_CDAYR2_CAYR2_Msk          (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff)                     */
40746 /* ========================================================  CDACR2  ========================================================= */
40747  #define R_CEU_CDACR2_CACR2_Pos          (0UL)          /*!< CACR2 (Bit 0)                                         */
40748  #define R_CEU_CDACR2_CACR2_Msk          (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff)                     */
40749 /* ========================================================  CDBYR2  ========================================================= */
40750  #define R_CEU_CDBYR2_CBYR2_Pos          (0UL)          /*!< CBYR2 (Bit 0)                                         */
40751  #define R_CEU_CDBYR2_CBYR2_Msk          (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff)                     */
40752 /* ========================================================  CDBCR2  ========================================================= */
40753  #define R_CEU_CDBCR2_CBCR2_Pos          (0UL)          /*!< CBCR2 (Bit 0)                                         */
40754  #define R_CEU_CDBCR2_CBCR2_Msk          (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff)                     */
40755 /* ======================================================  AXIBUSCTL2  ======================================================= */
40756  #define R_CEU_AXIBUSCTL2_AWCACHE_Pos    (0UL)          /*!< AWCACHE (Bit 0)                                       */
40757  #define R_CEU_AXIBUSCTL2_AWCACHE_Msk    (0xfUL)        /*!< AWCACHE (Bitfield-Mask: 0x0f)                         */
40758 /* ========================================================  CAMOR_B  ======================================================== */
40759  #define R_CEU_CAMOR_B_HOFST_Pos         (0UL)          /*!< HOFST (Bit 0)                                         */
40760  #define R_CEU_CAMOR_B_HOFST_Msk         (0x1fffUL)     /*!< HOFST (Bitfield-Mask: 0x1fff)                         */
40761  #define R_CEU_CAMOR_B_VOFST_Pos         (16UL)         /*!< VOFST (Bit 16)                                        */
40762  #define R_CEU_CAMOR_B_VOFST_Msk         (0xfff0000UL)  /*!< VOFST (Bitfield-Mask: 0xfff)                          */
40763 /* ========================================================  CAPWR_B  ======================================================== */
40764  #define R_CEU_CAPWR_B_HWDTH_Pos         (0UL)          /*!< HWDTH (Bit 0)                                         */
40765  #define R_CEU_CAPWR_B_HWDTH_Msk         (0x1fffUL)     /*!< HWDTH (Bitfield-Mask: 0x1fff)                         */
40766  #define R_CEU_CAPWR_B_VWDTH_Pos         (16UL)         /*!< VWDTH (Bit 16)                                        */
40767  #define R_CEU_CAPWR_B_VWDTH_Msk         (0xfff0000UL)  /*!< VWDTH (Bitfield-Mask: 0xfff)                          */
40768 /* ========================================================  CFLCR_B  ======================================================== */
40769  #define R_CEU_CFLCR_B_HFRAC_Pos         (0UL)          /*!< HFRAC (Bit 0)                                         */
40770  #define R_CEU_CFLCR_B_HFRAC_Msk         (0xfffUL)      /*!< HFRAC (Bitfield-Mask: 0xfff)                          */
40771  #define R_CEU_CFLCR_B_HMANT_Pos         (12UL)         /*!< HMANT (Bit 12)                                        */
40772  #define R_CEU_CFLCR_B_HMANT_Msk         (0xf000UL)     /*!< HMANT (Bitfield-Mask: 0x0f)                           */
40773  #define R_CEU_CFLCR_B_VFRAC_Pos         (16UL)         /*!< VFRAC (Bit 16)                                        */
40774  #define R_CEU_CFLCR_B_VFRAC_Msk         (0xfff0000UL)  /*!< VFRAC (Bitfield-Mask: 0xfff)                          */
40775  #define R_CEU_CFLCR_B_VMANT_Pos         (28UL)         /*!< VMANT (Bit 28)                                        */
40776  #define R_CEU_CFLCR_B_VMANT_Msk         (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f)                           */
40777 /* ========================================================  CFSZR_B  ======================================================== */
40778  #define R_CEU_CFSZR_B_HFCLP_Pos         (0UL)          /*!< HFCLP (Bit 0)                                         */
40779  #define R_CEU_CFSZR_B_HFCLP_Msk         (0xfffUL)      /*!< HFCLP (Bitfield-Mask: 0xfff)                          */
40780  #define R_CEU_CFSZR_B_VFCLP_Pos         (16UL)         /*!< VFCLP (Bit 16)                                        */
40781  #define R_CEU_CFSZR_B_VFCLP_Msk         (0xfff0000UL)  /*!< VFCLP (Bitfield-Mask: 0xfff)                          */
40782 /* ========================================================  CDWDR_B  ======================================================== */
40783  #define R_CEU_CDWDR_B_CHDW_Pos          (0UL)          /*!< CHDW (Bit 0)                                          */
40784  #define R_CEU_CDWDR_B_CHDW_Msk          (0x1fffUL)     /*!< CHDW (Bitfield-Mask: 0x1fff)                          */
40785 /* ========================================================  CDAYR_B  ======================================================== */
40786  #define R_CEU_CDAYR_B_CAYR_Pos          (0UL)          /*!< CAYR (Bit 0)                                          */
40787  #define R_CEU_CDAYR_B_CAYR_Msk          (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff)                      */
40788 /* ========================================================  CDACR_B  ======================================================== */
40789  #define R_CEU_CDACR_B_CACR_Pos          (0UL)          /*!< CACR (Bit 0)                                          */
40790  #define R_CEU_CDACR_B_CACR_Msk          (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff)                      */
40791 /* ========================================================  CDBYR_B  ======================================================== */
40792  #define R_CEU_CDBYR_B_CBYR_Pos          (0UL)          /*!< CBYR (Bit 0)                                          */
40793  #define R_CEU_CDBYR_B_CBYR_Msk          (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff)                      */
40794 /* ========================================================  CDBCR_B  ======================================================== */
40795  #define R_CEU_CDBCR_B_CBCR_Pos          (0UL)          /*!< CBCR (Bit 0)                                          */
40796  #define R_CEU_CDBCR_B_CBCR_Msk          (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff)                      */
40797 /* ========================================================  CBDSR_B  ======================================================== */
40798  #define R_CEU_CBDSR_B_CBVS_Pos          (0UL)          /*!< CBVS (Bit 0)                                          */
40799  #define R_CEU_CBDSR_B_CBVS_Msk          (0x7fffffUL)   /*!< CBVS (Bitfield-Mask: 0x7fffff)                        */
40800 /* ========================================================  CLFCR_B  ======================================================== */
40801  #define R_CEU_CLFCR_B_LPF_Pos           (0UL)          /*!< LPF (Bit 0)                                           */
40802  #define R_CEU_CLFCR_B_LPF_Msk           (0x1UL)        /*!< LPF (Bitfield-Mask: 0x01)                             */
40803 /* ========================================================  CDOCR_B  ======================================================== */
40804  #define R_CEU_CDOCR_B_COBS_Pos          (0UL)          /*!< COBS (Bit 0)                                          */
40805  #define R_CEU_CDOCR_B_COBS_Msk          (0x1UL)        /*!< COBS (Bitfield-Mask: 0x01)                            */
40806  #define R_CEU_CDOCR_B_COWS_Pos          (1UL)          /*!< COWS (Bit 1)                                          */
40807  #define R_CEU_CDOCR_B_COWS_Msk          (0x2UL)        /*!< COWS (Bitfield-Mask: 0x01)                            */
40808  #define R_CEU_CDOCR_B_COLS_Pos          (2UL)          /*!< COLS (Bit 2)                                          */
40809  #define R_CEU_CDOCR_B_COLS_Msk          (0x4UL)        /*!< COLS (Bitfield-Mask: 0x01)                            */
40810  #define R_CEU_CDOCR_B_CDS_Pos           (4UL)          /*!< CDS (Bit 4)                                           */
40811  #define R_CEU_CDOCR_B_CDS_Msk           (0x10UL)       /*!< CDS (Bitfield-Mask: 0x01)                             */
40812  #define R_CEU_CDOCR_B_CBE_Pos           (16UL)         /*!< CBE (Bit 16)                                          */
40813  #define R_CEU_CDOCR_B_CBE_Msk           (0x10000UL)    /*!< CBE (Bitfield-Mask: 0x01)                             */
40814 /* =======================================================  CDAYR2_B  ======================================================== */
40815  #define R_CEU_CDAYR2_B_CAYR2_Pos        (0UL)          /*!< CAYR2 (Bit 0)                                         */
40816  #define R_CEU_CDAYR2_B_CAYR2_Msk        (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff)                     */
40817 /* =======================================================  CDACR2_B  ======================================================== */
40818  #define R_CEU_CDACR2_B_CACR2_Pos        (0UL)          /*!< CACR2 (Bit 0)                                         */
40819  #define R_CEU_CDACR2_B_CACR2_Msk        (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff)                     */
40820 /* =======================================================  CDBYR2_B  ======================================================== */
40821  #define R_CEU_CDBYR2_B_CBYR2_Pos        (0UL)          /*!< CBYR2 (Bit 0)                                         */
40822  #define R_CEU_CDBYR2_B_CBYR2_Msk        (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff)                     */
40823 /* =======================================================  CDBCR2_B  ======================================================== */
40824  #define R_CEU_CDBCR2_B_CBCR2_Pos        (0UL)          /*!< CBCR2 (Bit 0)                                         */
40825  #define R_CEU_CDBCR2_B_CBCR2_Msk        (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff)                     */
40826 /* ========================================================  CAMOR_M  ======================================================== */
40827  #define R_CEU_CAMOR_M_HOFST_Pos         (0UL)          /*!< HOFST (Bit 0)                                         */
40828  #define R_CEU_CAMOR_M_HOFST_Msk         (0x1fffUL)     /*!< HOFST (Bitfield-Mask: 0x1fff)                         */
40829  #define R_CEU_CAMOR_M_VOFST_Pos         (16UL)         /*!< VOFST (Bit 16)                                        */
40830  #define R_CEU_CAMOR_M_VOFST_Msk         (0xfff0000UL)  /*!< VOFST (Bitfield-Mask: 0xfff)                          */
40831 /* ========================================================  CAPWR_M  ======================================================== */
40832  #define R_CEU_CAPWR_M_HWDTH_Pos         (0UL)          /*!< HWDTH (Bit 0)                                         */
40833  #define R_CEU_CAPWR_M_HWDTH_Msk         (0x1fffUL)     /*!< HWDTH (Bitfield-Mask: 0x1fff)                         */
40834  #define R_CEU_CAPWR_M_VWDTH_Pos         (16UL)         /*!< VWDTH (Bit 16)                                        */
40835  #define R_CEU_CAPWR_M_VWDTH_Msk         (0xfff0000UL)  /*!< VWDTH (Bitfield-Mask: 0xfff)                          */
40836 /* ========================================================  CFLCR_M  ======================================================== */
40837  #define R_CEU_CFLCR_M_HFRAC_Pos         (0UL)          /*!< HFRAC (Bit 0)                                         */
40838  #define R_CEU_CFLCR_M_HFRAC_Msk         (0xfffUL)      /*!< HFRAC (Bitfield-Mask: 0xfff)                          */
40839  #define R_CEU_CFLCR_M_HMANT_Pos         (12UL)         /*!< HMANT (Bit 12)                                        */
40840  #define R_CEU_CFLCR_M_HMANT_Msk         (0xf000UL)     /*!< HMANT (Bitfield-Mask: 0x0f)                           */
40841  #define R_CEU_CFLCR_M_VFRAC_Pos         (16UL)         /*!< VFRAC (Bit 16)                                        */
40842  #define R_CEU_CFLCR_M_VFRAC_Msk         (0xfff0000UL)  /*!< VFRAC (Bitfield-Mask: 0xfff)                          */
40843  #define R_CEU_CFLCR_M_VMANT_Pos         (28UL)         /*!< VMANT (Bit 28)                                        */
40844  #define R_CEU_CFLCR_M_VMANT_Msk         (0xf0000000UL) /*!< VMANT (Bitfield-Mask: 0x0f)                           */
40845 /* ========================================================  CFSZR_M  ======================================================== */
40846  #define R_CEU_CFSZR_M_HFCLP_Pos         (0UL)          /*!< HFCLP (Bit 0)                                         */
40847  #define R_CEU_CFSZR_M_HFCLP_Msk         (0xfffUL)      /*!< HFCLP (Bitfield-Mask: 0xfff)                          */
40848  #define R_CEU_CFSZR_M_VFCLP_Pos         (16UL)         /*!< VFCLP (Bit 16)                                        */
40849  #define R_CEU_CFSZR_M_VFCLP_Msk         (0xfff0000UL)  /*!< VFCLP (Bitfield-Mask: 0xfff)                          */
40850 /* ========================================================  CDWDR_M  ======================================================== */
40851  #define R_CEU_CDWDR_M_CHDW_Pos          (0UL)          /*!< CHDW (Bit 0)                                          */
40852  #define R_CEU_CDWDR_M_CHDW_Msk          (0x1fffUL)     /*!< CHDW (Bitfield-Mask: 0x1fff)                          */
40853 /* ========================================================  CDAYR_M  ======================================================== */
40854  #define R_CEU_CDAYR_M_CAYR_Pos          (0UL)          /*!< CAYR (Bit 0)                                          */
40855  #define R_CEU_CDAYR_M_CAYR_Msk          (0xffffffffUL) /*!< CAYR (Bitfield-Mask: 0xffffffff)                      */
40856 /* ========================================================  CDACR_M  ======================================================== */
40857  #define R_CEU_CDACR_M_CACR_Pos          (0UL)          /*!< CACR (Bit 0)                                          */
40858  #define R_CEU_CDACR_M_CACR_Msk          (0xffffffffUL) /*!< CACR (Bitfield-Mask: 0xffffffff)                      */
40859 /* ========================================================  CDBYR_M  ======================================================== */
40860  #define R_CEU_CDBYR_M_CBYR_Pos          (0UL)          /*!< CBYR (Bit 0)                                          */
40861  #define R_CEU_CDBYR_M_CBYR_Msk          (0xffffffffUL) /*!< CBYR (Bitfield-Mask: 0xffffffff)                      */
40862 /* ========================================================  CDBCR_M  ======================================================== */
40863  #define R_CEU_CDBCR_M_CBCR_Pos          (0UL)          /*!< CBCR (Bit 0)                                          */
40864  #define R_CEU_CDBCR_M_CBCR_Msk          (0xffffffffUL) /*!< CBCR (Bitfield-Mask: 0xffffffff)                      */
40865 /* ========================================================  CBDSR_M  ======================================================== */
40866  #define R_CEU_CBDSR_M_CBVS_Pos          (0UL)          /*!< CBVS (Bit 0)                                          */
40867  #define R_CEU_CBDSR_M_CBVS_Msk          (0x7fffffUL)   /*!< CBVS (Bitfield-Mask: 0x7fffff)                        */
40868 /* ========================================================  CLFCR_M  ======================================================== */
40869  #define R_CEU_CLFCR_M_LPF_Pos           (0UL)          /*!< LPF (Bit 0)                                           */
40870  #define R_CEU_CLFCR_M_LPF_Msk           (0x1UL)        /*!< LPF (Bitfield-Mask: 0x01)                             */
40871 /* ========================================================  CDOCR_M  ======================================================== */
40872  #define R_CEU_CDOCR_M_COBS_Pos          (0UL)          /*!< COBS (Bit 0)                                          */
40873  #define R_CEU_CDOCR_M_COBS_Msk          (0x1UL)        /*!< COBS (Bitfield-Mask: 0x01)                            */
40874  #define R_CEU_CDOCR_M_COWS_Pos          (1UL)          /*!< COWS (Bit 1)                                          */
40875  #define R_CEU_CDOCR_M_COWS_Msk          (0x2UL)        /*!< COWS (Bitfield-Mask: 0x01)                            */
40876  #define R_CEU_CDOCR_M_COLS_Pos          (2UL)          /*!< COLS (Bit 2)                                          */
40877  #define R_CEU_CDOCR_M_COLS_Msk          (0x4UL)        /*!< COLS (Bitfield-Mask: 0x01)                            */
40878  #define R_CEU_CDOCR_M_CDS_Pos           (4UL)          /*!< CDS (Bit 4)                                           */
40879  #define R_CEU_CDOCR_M_CDS_Msk           (0x10UL)       /*!< CDS (Bitfield-Mask: 0x01)                             */
40880  #define R_CEU_CDOCR_M_CBE_Pos           (16UL)         /*!< CBE (Bit 16)                                          */
40881  #define R_CEU_CDOCR_M_CBE_Msk           (0x10000UL)    /*!< CBE (Bitfield-Mask: 0x01)                             */
40882 /* =======================================================  CDAYR2_M  ======================================================== */
40883  #define R_CEU_CDAYR2_M_CAYR2_Pos        (0UL)          /*!< CAYR2 (Bit 0)                                         */
40884  #define R_CEU_CDAYR2_M_CAYR2_Msk        (0xffffffffUL) /*!< CAYR2 (Bitfield-Mask: 0xffffffff)                     */
40885 /* =======================================================  CDACR2_M  ======================================================== */
40886  #define R_CEU_CDACR2_M_CACR2_Pos        (0UL)          /*!< CACR2 (Bit 0)                                         */
40887  #define R_CEU_CDACR2_M_CACR2_Msk        (0xffffffffUL) /*!< CACR2 (Bitfield-Mask: 0xffffffff)                     */
40888 /* =======================================================  CDBYR2_M  ======================================================== */
40889  #define R_CEU_CDBYR2_M_CBYR2_Pos        (0UL)          /*!< CBYR2 (Bit 0)                                         */
40890  #define R_CEU_CDBYR2_M_CBYR2_Msk        (0xffffffffUL) /*!< CBYR2 (Bitfield-Mask: 0xffffffff)                     */
40891 /* =======================================================  CDBCR2_M  ======================================================== */
40892  #define R_CEU_CDBCR2_M_CBCR2_Pos        (0UL)          /*!< CBCR2 (Bit 0)                                         */
40893  #define R_CEU_CDBCR2_M_CBCR2_Msk        (0xffffffffUL) /*!< CBCR2 (Bitfield-Mask: 0xffffffff)                     */
40894 
40895 /* =========================================================================================================================== */
40896 /* ================                                          R_ULPT0                                          ================ */
40897 /* =========================================================================================================================== */
40898 
40899 /* ========================================================  ULPTCNT  ======================================================== */
40900  #define R_ULPT0_ULPTCNT_ULPTCNT_Pos     (0UL)          /*!< ULPTCNT (Bit 0)                                       */
40901  #define R_ULPT0_ULPTCNT_ULPTCNT_Msk     (0xffffffffUL) /*!< ULPTCNT (Bitfield-Mask: 0xffffffff)                   */
40902 /* ========================================================  ULPTCMA  ======================================================== */
40903  #define R_ULPT0_ULPTCMA_ULPTCMA_Pos     (0UL)          /*!< ULPTCMA (Bit 0)                                       */
40904  #define R_ULPT0_ULPTCMA_ULPTCMA_Msk     (0xffffffffUL) /*!< ULPTCMA (Bitfield-Mask: 0xffffffff)                   */
40905 /* ========================================================  ULPTCMB  ======================================================== */
40906  #define R_ULPT0_ULPTCMB_ULPTCMB_Pos     (0UL)          /*!< ULPTCMB (Bit 0)                                       */
40907  #define R_ULPT0_ULPTCMB_ULPTCMB_Msk     (0xffffffffUL) /*!< ULPTCMB (Bitfield-Mask: 0xffffffff)                   */
40908 /* ========================================================  ULPTCR  ========================================================= */
40909  #define R_ULPT0_ULPTCR_TSTART_Pos       (0UL)          /*!< TSTART (Bit 0)                                        */
40910  #define R_ULPT0_ULPTCR_TSTART_Msk       (0x1UL)        /*!< TSTART (Bitfield-Mask: 0x01)                          */
40911  #define R_ULPT0_ULPTCR_TCSTF_Pos        (1UL)          /*!< TCSTF (Bit 1)                                         */
40912  #define R_ULPT0_ULPTCR_TCSTF_Msk        (0x2UL)        /*!< TCSTF (Bitfield-Mask: 0x01)                           */
40913  #define R_ULPT0_ULPTCR_TSTOP_Pos        (2UL)          /*!< TSTOP (Bit 2)                                         */
40914  #define R_ULPT0_ULPTCR_TSTOP_Msk        (0x4UL)        /*!< TSTOP (Bitfield-Mask: 0x01)                           */
40915  #define R_ULPT0_ULPTCR_TUNDF_Pos        (5UL)          /*!< TUNDF (Bit 5)                                         */
40916  #define R_ULPT0_ULPTCR_TUNDF_Msk        (0x20UL)       /*!< TUNDF (Bitfield-Mask: 0x01)                           */
40917  #define R_ULPT0_ULPTCR_TCMAF_Pos        (6UL)          /*!< TCMAF (Bit 6)                                         */
40918  #define R_ULPT0_ULPTCR_TCMAF_Msk        (0x40UL)       /*!< TCMAF (Bitfield-Mask: 0x01)                           */
40919  #define R_ULPT0_ULPTCR_TCMBF_Pos        (7UL)          /*!< TCMBF (Bit 7)                                         */
40920  #define R_ULPT0_ULPTCR_TCMBF_Msk        (0x80UL)       /*!< TCMBF (Bitfield-Mask: 0x01)                           */
40921 /* ========================================================  ULPTMR1  ======================================================== */
40922  #define R_ULPT0_ULPTMR1_TMOD1_Pos       (1UL)          /*!< TMOD1 (Bit 1)                                         */
40923  #define R_ULPT0_ULPTMR1_TMOD1_Msk       (0x2UL)        /*!< TMOD1 (Bitfield-Mask: 0x01)                           */
40924  #define R_ULPT0_ULPTMR1_TEDGPL_Pos      (3UL)          /*!< TEDGPL (Bit 3)                                        */
40925  #define R_ULPT0_ULPTMR1_TEDGPL_Msk      (0x8UL)        /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
40926  #define R_ULPT0_ULPTMR1_TCK1_Pos        (5UL)          /*!< TCK1 (Bit 5)                                          */
40927  #define R_ULPT0_ULPTMR1_TCK1_Msk        (0x20UL)       /*!< TCK1 (Bitfield-Mask: 0x01)                            */
40928 /* ========================================================  ULPTMR2  ======================================================== */
40929  #define R_ULPT0_ULPTMR2_CKS_Pos         (0UL)          /*!< CKS (Bit 0)                                           */
40930  #define R_ULPT0_ULPTMR2_CKS_Msk         (0x7UL)        /*!< CKS (Bitfield-Mask: 0x07)                             */
40931  #define R_ULPT0_ULPTMR2_LPM_Pos         (7UL)          /*!< LPM (Bit 7)                                           */
40932  #define R_ULPT0_ULPTMR2_LPM_Msk         (0x80UL)       /*!< LPM (Bitfield-Mask: 0x01)                             */
40933 /* ========================================================  ULPTMR3  ======================================================== */
40934  #define R_ULPT0_ULPTMR3_TCNTCTL_Pos     (0UL)          /*!< TCNTCTL (Bit 0)                                       */
40935  #define R_ULPT0_ULPTMR3_TCNTCTL_Msk     (0x1UL)        /*!< TCNTCTL (Bitfield-Mask: 0x01)                         */
40936  #define R_ULPT0_ULPTMR3_TEVPOL_Pos      (1UL)          /*!< TEVPOL (Bit 1)                                        */
40937  #define R_ULPT0_ULPTMR3_TEVPOL_Msk      (0x2UL)        /*!< TEVPOL (Bitfield-Mask: 0x01)                          */
40938  #define R_ULPT0_ULPTMR3_TOPOL_Pos       (2UL)          /*!< TOPOL (Bit 2)                                         */
40939  #define R_ULPT0_ULPTMR3_TOPOL_Msk       (0x4UL)        /*!< TOPOL (Bitfield-Mask: 0x01)                           */
40940  #define R_ULPT0_ULPTMR3_TEECTL_Pos      (4UL)          /*!< TEECTL (Bit 4)                                        */
40941  #define R_ULPT0_ULPTMR3_TEECTL_Msk      (0x30UL)       /*!< TEECTL (Bitfield-Mask: 0x03)                          */
40942  #define R_ULPT0_ULPTMR3_TEEPOL_Pos      (6UL)          /*!< TEEPOL (Bit 6)                                        */
40943  #define R_ULPT0_ULPTMR3_TEEPOL_Msk      (0xc0UL)       /*!< TEEPOL (Bitfield-Mask: 0x03)                          */
40944 /* ========================================================  ULPTIOC  ======================================================== */
40945  #define R_ULPT0_ULPTIOC_TOE_Pos         (2UL)          /*!< TOE (Bit 2)                                           */
40946  #define R_ULPT0_ULPTIOC_TOE_Msk         (0x4UL)        /*!< TOE (Bitfield-Mask: 0x01)                             */
40947  #define R_ULPT0_ULPTIOC_TIPF_Pos        (4UL)          /*!< TIPF (Bit 4)                                          */
40948  #define R_ULPT0_ULPTIOC_TIPF_Msk        (0x30UL)       /*!< TIPF (Bitfield-Mask: 0x03)                            */
40949  #define R_ULPT0_ULPTIOC_TIOGT0_Pos      (6UL)          /*!< TIOGT0 (Bit 6)                                        */
40950  #define R_ULPT0_ULPTIOC_TIOGT0_Msk      (0x40UL)       /*!< TIOGT0 (Bitfield-Mask: 0x01)                          */
40951 /* ========================================================  ULPTISR  ======================================================== */
40952  #define R_ULPT0_ULPTISR_RCCPSEL2_Pos    (2UL)          /*!< RCCPSEL2 (Bit 2)                                      */
40953  #define R_ULPT0_ULPTISR_RCCPSEL2_Msk    (0x4UL)        /*!< RCCPSEL2 (Bitfield-Mask: 0x01)                        */
40954 /* =======================================================  ULPTCMSR  ======================================================== */
40955  #define R_ULPT0_ULPTCMSR_TCMEA_Pos      (0UL)          /*!< TCMEA (Bit 0)                                         */
40956  #define R_ULPT0_ULPTCMSR_TCMEA_Msk      (0x1UL)        /*!< TCMEA (Bitfield-Mask: 0x01)                           */
40957  #define R_ULPT0_ULPTCMSR_TOEA_Pos       (1UL)          /*!< TOEA (Bit 1)                                          */
40958  #define R_ULPT0_ULPTCMSR_TOEA_Msk       (0x2UL)        /*!< TOEA (Bitfield-Mask: 0x01)                            */
40959  #define R_ULPT0_ULPTCMSR_TOPOLA_Pos     (2UL)          /*!< TOPOLA (Bit 2)                                        */
40960  #define R_ULPT0_ULPTCMSR_TOPOLA_Msk     (0x4UL)        /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
40961  #define R_ULPT0_ULPTCMSR_TCMEB_Pos      (4UL)          /*!< TCMEB (Bit 4)                                         */
40962  #define R_ULPT0_ULPTCMSR_TCMEB_Msk      (0x10UL)       /*!< TCMEB (Bitfield-Mask: 0x01)                           */
40963  #define R_ULPT0_ULPTCMSR_TOEB_Pos       (5UL)          /*!< TOEB (Bit 5)                                          */
40964  #define R_ULPT0_ULPTCMSR_TOEB_Msk       (0x20UL)       /*!< TOEB (Bitfield-Mask: 0x01)                            */
40965  #define R_ULPT0_ULPTCMSR_TOPOLB_Pos     (6UL)          /*!< TOPOLB (Bit 6)                                        */
40966  #define R_ULPT0_ULPTCMSR_TOPOLB_Msk     (0x40UL)       /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
40967 
40968 /* =========================================================================================================================== */
40969 /* ================                                        R_DEBUG_OCD                                        ================ */
40970 /* =========================================================================================================================== */
40971 
40972 /* =======================================================  FSBLSTATM  ======================================================= */
40973  #define R_DEBUG_OCD_FSBLSTATM_CS_Pos    (0UL)   /*!< CS (Bit 0)                                            */
40974  #define R_DEBUG_OCD_FSBLSTATM_CS_Msk    (0x1UL) /*!< CS (Bitfield-Mask: 0x01)                              */
40975  #define R_DEBUG_OCD_FSBLSTATM_RS_Pos    (1UL)   /*!< RS (Bit 1)                                            */
40976  #define R_DEBUG_OCD_FSBLSTATM_RS_Msk    (0x2UL) /*!< RS (Bitfield-Mask: 0x01)                              */
40977 
40978 /* =========================================================================================================================== */
40979 /* ================                                          R_DOTF                                           ================ */
40980 /* =========================================================================================================================== */
40981 
40982 /* ======================================================  CONVAREAST  ======================================================= */
40983  #define R_DOTF_CONVAREAST_CONVAREAST_Pos    (12UL)         /*!< CONVAREAST (Bit 12)                                   */
40984  #define R_DOTF_CONVAREAST_CONVAREAST_Msk    (0xfffff000UL) /*!< CONVAREAST (Bitfield-Mask: 0xfffff)                   */
40985 /* =======================================================  CONVAREAD  ======================================================= */
40986  #define R_DOTF_CONVAREAD_CONVAREAD_Pos      (12UL)         /*!< CONVAREAD (Bit 12)                                    */
40987  #define R_DOTF_CONVAREAD_CONVAREAD_Msk      (0xfffff000UL) /*!< CONVAREAD (Bitfield-Mask: 0xfffff)                    */
40988 /* =========================================================  REG00  ========================================================= */
40989  #define R_DOTF_REG00_B09_Pos                (9UL)          /*!< B09 (Bit 9)                                           */
40990  #define R_DOTF_REG00_B09_Msk                (0x200UL)      /*!< B09 (Bitfield-Mask: 0x01)                             */
40991  #define R_DOTF_REG00_B16_Pos                (16UL)         /*!< B16 (Bit 16)                                          */
40992  #define R_DOTF_REG00_B16_Msk                (0x10000UL)    /*!< B16 (Bitfield-Mask: 0x01)                             */
40993  #define R_DOTF_REG00_B17_Pos                (17UL)         /*!< B17 (Bit 17)                                          */
40994  #define R_DOTF_REG00_B17_Msk                (0x20000UL)    /*!< B17 (Bitfield-Mask: 0x01)                             */
40995  #define R_DOTF_REG00_B20_Pos                (20UL)         /*!< B20 (Bit 20)                                          */
40996  #define R_DOTF_REG00_B20_Msk                (0x100000UL)   /*!< B20 (Bitfield-Mask: 0x01)                             */
40997  #define R_DOTF_REG00_B24_Pos                (24UL)         /*!< B24 (Bit 24)                                          */
40998  #define R_DOTF_REG00_B24_Msk                (0x3000000UL)  /*!< B24 (Bitfield-Mask: 0x03)                             */
40999  #define R_DOTF_REG00_B28_Pos                (28UL)         /*!< B28 (Bit 28)                                          */
41000  #define R_DOTF_REG00_B28_Msk                (0x30000000UL) /*!< B28 (Bitfield-Mask: 0x03)                             */
41001 /* =========================================================  REG03  ========================================================= */
41002  #define R_DOTF_REG03_B00_Pos                (0UL)          /*!< B00 (Bit 0)                                           */
41003  #define R_DOTF_REG03_B00_Msk                (0xffffffffUL) /*!< B00 (Bitfield-Mask: 0xffffffff)                       */
41004 
41005 /* =========================================================================================================================== */
41006 /* ================                                          R_AGTX0                                          ================ */
41007 /* =========================================================================================================================== */
41008 
41009 /* =========================================================================================================================== */
41010 /* ================                                         R_DPHYCNT                                         ================ */
41011 /* =========================================================================================================================== */
41012 
41013 /* =======================================================  DPHYREFCR  ======================================================= */
41014  #define R_DPHYCNT_DPHYREFCR_RFREQ_Pos      (0UL)          /*!< RFREQ (Bit 0)                                         */
41015  #define R_DPHYCNT_DPHYREFCR_RFREQ_Msk      (0xffUL)       /*!< RFREQ (Bitfield-Mask: 0xff)                           */
41016 /* =======================================================  DPHYPLFCR  ======================================================= */
41017  #define R_DPHYCNT_DPHYPLFCR_IDIV_Pos       (0UL)          /*!< IDIV (Bit 0)                                          */
41018  #define R_DPHYCNT_DPHYPLFCR_IDIV_Msk       (0x3UL)        /*!< IDIV (Bitfield-Mask: 0x03)                            */
41019  #define R_DPHYCNT_DPHYPLFCR_NFMUL_Pos      (8UL)          /*!< NFMUL (Bit 8)                                         */
41020  #define R_DPHYCNT_DPHYPLFCR_NFMUL_Msk      (0x300UL)      /*!< NFMUL (Bitfield-Mask: 0x03)                           */
41021  #define R_DPHYCNT_DPHYPLFCR_NMUL_Pos       (16UL)         /*!< NMUL (Bit 16)                                         */
41022  #define R_DPHYCNT_DPHYPLFCR_NMUL_Msk       (0xff0000UL)   /*!< NMUL (Bitfield-Mask: 0xff)                            */
41023 /* =======================================================  DPHYPLOCR  ======================================================= */
41024  #define R_DPHYCNT_DPHYPLOCR_PLLSTP_Pos     (0UL)          /*!< PLLSTP (Bit 0)                                        */
41025  #define R_DPHYCNT_DPHYPLOCR_PLLSTP_Msk     (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
41026 /* =======================================================  DPHYESCCR  ======================================================= */
41027  #define R_DPHYCNT_DPHYESCCR_ESCDIV_Pos     (0UL)          /*!< ESCDIV (Bit 0)                                        */
41028  #define R_DPHYCNT_DPHYESCCR_ESCDIV_Msk     (0x1fUL)       /*!< ESCDIV (Bitfield-Mask: 0x1f)                          */
41029 /* =======================================================  DPHYPWRCR  ======================================================= */
41030  #define R_DPHYCNT_DPHYPWRCR_PWRSEN_Pos     (0UL)          /*!< PWRSEN (Bit 0)                                        */
41031  #define R_DPHYCNT_DPHYPWRCR_PWRSEN_Msk     (0x1UL)        /*!< PWRSEN (Bitfield-Mask: 0x01)                          */
41032 /* ========================================================  DPHYSFR  ======================================================== */
41033  #define R_DPHYCNT_DPHYSFR_PWRSF_Pos        (0UL)          /*!< PWRSF (Bit 0)                                         */
41034  #define R_DPHYCNT_DPHYSFR_PWRSF_Msk        (0x1UL)        /*!< PWRSF (Bitfield-Mask: 0x01)                           */
41035  #define R_DPHYCNT_DPHYSFR_PLLSF_Pos        (8UL)          /*!< PLLSF (Bit 8)                                         */
41036  #define R_DPHYCNT_DPHYSFR_PLLSF_Msk        (0x100UL)      /*!< PLLSF (Bitfield-Mask: 0x01)                           */
41037 /* ========================================================  DPHYOCR  ======================================================== */
41038  #define R_DPHYCNT_DPHYOCR_DPHYEN_Pos       (0UL)          /*!< DPHYEN (Bit 0)                                        */
41039  #define R_DPHYCNT_DPHYOCR_DPHYEN_Msk       (0x1UL)        /*!< DPHYEN (Bitfield-Mask: 0x01)                          */
41040 /* =======================================================  DPHYTIM1  ======================================================== */
41041  #define R_DPHYCNT_DPHYTIM1_TINIT_Pos       (0UL)          /*!< TINIT (Bit 0)                                         */
41042  #define R_DPHYCNT_DPHYTIM1_TINIT_Msk       (0x7ffffUL)    /*!< TINIT (Bitfield-Mask: 0x7ffff)                        */
41043 /* =======================================================  DPHYTIM2  ======================================================== */
41044  #define R_DPHYCNT_DPHYTIM2_TCLKPREP_Pos    (0UL)          /*!< TCLKPREP (Bit 0)                                      */
41045  #define R_DPHYCNT_DPHYTIM2_TCLKPREP_Msk    (0xffUL)       /*!< TCLKPREP (Bitfield-Mask: 0xff)                        */
41046 /* =======================================================  DPHYTIM3  ======================================================== */
41047  #define R_DPHYCNT_DPHYTIM3_THSPREP_Pos     (0UL)          /*!< THSPREP (Bit 0)                                       */
41048  #define R_DPHYCNT_DPHYTIM3_THSPREP_Msk     (0xffUL)       /*!< THSPREP (Bitfield-Mask: 0xff)                         */
41049 /* =======================================================  DPHYTIM4  ======================================================== */
41050  #define R_DPHYCNT_DPHYTIM4_TCLKZERO_Pos    (0UL)          /*!< TCLKZERO (Bit 0)                                      */
41051  #define R_DPHYCNT_DPHYTIM4_TCLKZERO_Msk    (0xffUL)       /*!< TCLKZERO (Bitfield-Mask: 0xff)                        */
41052  #define R_DPHYCNT_DPHYTIM4_TCLKPRE_Pos     (8UL)          /*!< TCLKPRE (Bit 8)                                       */
41053  #define R_DPHYCNT_DPHYTIM4_TCLKPRE_Msk     (0xff00UL)     /*!< TCLKPRE (Bitfield-Mask: 0xff)                         */
41054  #define R_DPHYCNT_DPHYTIM4_TCLKPOST_Pos    (16UL)         /*!< TCLKPOST (Bit 16)                                     */
41055  #define R_DPHYCNT_DPHYTIM4_TCLKPOST_Msk    (0xff0000UL)   /*!< TCLKPOST (Bitfield-Mask: 0xff)                        */
41056  #define R_DPHYCNT_DPHYTIM4_TCLKTRL_Pos     (24UL)         /*!< TCLKTRL (Bit 24)                                      */
41057  #define R_DPHYCNT_DPHYTIM4_TCLKTRL_Msk     (0xff000000UL) /*!< TCLKTRL (Bitfield-Mask: 0xff)                         */
41058 /* =======================================================  DPHYTIM5  ======================================================== */
41059  #define R_DPHYCNT_DPHYTIM5_THSZERO_Pos     (0UL)          /*!< THSZERO (Bit 0)                                       */
41060  #define R_DPHYCNT_DPHYTIM5_THSZERO_Msk     (0xffUL)       /*!< THSZERO (Bitfield-Mask: 0xff)                         */
41061  #define R_DPHYCNT_DPHYTIM5_THSTRL_Pos      (8UL)          /*!< THSTRL (Bit 8)                                        */
41062  #define R_DPHYCNT_DPHYTIM5_THSTRL_Msk      (0xff00UL)     /*!< THSTRL (Bitfield-Mask: 0xff)                          */
41063  #define R_DPHYCNT_DPHYTIM5_THSEXIT_Pos     (16UL)         /*!< THSEXIT (Bit 16)                                      */
41064  #define R_DPHYCNT_DPHYTIM5_THSEXIT_Msk     (0xff0000UL)   /*!< THSEXIT (Bitfield-Mask: 0xff)                         */
41065 /* =======================================================  DPHYTIM6  ======================================================== */
41066  #define R_DPHYCNT_DPHYTIM6_TLPX_Pos        (0UL)          /*!< TLPX (Bit 0)                                          */
41067  #define R_DPHYCNT_DPHYTIM6_TLPX_Msk        (0xffUL)       /*!< TLPX (Bitfield-Mask: 0xff)                            */
41068 
41069 /* =========================================================================================================================== */
41070 /* ================                                         R_DSILINK                                         ================ */
41071 /* =========================================================================================================================== */
41072 
41073 /* ==========================================================  ISR  ========================================================== */
41074  #define R_DSILINK_ISR_SQ0_Pos                   (0UL)          /*!< SQ0 (Bit 0)                                           */
41075  #define R_DSILINK_ISR_SQ0_Msk                   (0x1UL)        /*!< SQ0 (Bitfield-Mask: 0x01)                             */
41076  #define R_DSILINK_ISR_SQ1_Pos                   (4UL)          /*!< SQ1 (Bit 4)                                           */
41077  #define R_DSILINK_ISR_SQ1_Msk                   (0x10UL)       /*!< SQ1 (Bitfield-Mask: 0x01)                             */
41078  #define R_DSILINK_ISR_VM_Pos                    (8UL)          /*!< VM (Bit 8)                                            */
41079  #define R_DSILINK_ISR_VM_Msk                    (0x100UL)      /*!< VM (Bitfield-Mask: 0x01)                              */
41080  #define R_DSILINK_ISR_RCV_Pos                   (12UL)         /*!< RCV (Bit 12)                                          */
41081  #define R_DSILINK_ISR_RCV_Msk                   (0x1000UL)     /*!< RCV (Bitfield-Mask: 0x01)                             */
41082  #define R_DSILINK_ISR_FERR_Pos                  (16UL)         /*!< FERR (Bit 16)                                         */
41083  #define R_DSILINK_ISR_FERR_Msk                  (0x10000UL)    /*!< FERR (Bitfield-Mask: 0x01)                            */
41084  #define R_DSILINK_ISR_PPI_Pos                   (20UL)         /*!< PPI (Bit 20)                                          */
41085  #define R_DSILINK_ISR_PPI_Msk                   (0x100000UL)   /*!< PPI (Bitfield-Mask: 0x01)                             */
41086 /* ========================================================  LINKSR  ========================================================= */
41087  #define R_DSILINK_LINKSR_SQ0RUN_Pos             (0UL)          /*!< SQ0RUN (Bit 0)                                        */
41088  #define R_DSILINK_LINKSR_SQ0RUN_Msk             (0x1UL)        /*!< SQ0RUN (Bitfield-Mask: 0x01)                          */
41089  #define R_DSILINK_LINKSR_SQ1RUN_Pos             (4UL)          /*!< SQ1RUN (Bit 4)                                        */
41090  #define R_DSILINK_LINKSR_SQ1RUN_Msk             (0x10UL)       /*!< SQ1RUN (Bitfield-Mask: 0x01)                          */
41091  #define R_DSILINK_LINKSR_VRUN_Pos               (8UL)          /*!< VRUN (Bit 8)                                          */
41092  #define R_DSILINK_LINKSR_VRUN_Msk               (0x100UL)      /*!< VRUN (Bitfield-Mask: 0x01)                            */
41093  #define R_DSILINK_LINKSR_HSBUSY_Pos             (12UL)         /*!< HSBUSY (Bit 12)                                       */
41094  #define R_DSILINK_LINKSR_HSBUSY_Msk             (0x1000UL)     /*!< HSBUSY (Bitfield-Mask: 0x01)                          */
41095  #define R_DSILINK_LINKSR_LPBUSY_Pos             (13UL)         /*!< LPBUSY (Bit 13)                                       */
41096  #define R_DSILINK_LINKSR_LPBUSY_Msk             (0x2000UL)     /*!< LPBUSY (Bitfield-Mask: 0x01)                          */
41097 /* ========================================================  TXSETR  ========================================================= */
41098  #define R_DSILINK_TXSETR_NUMLANE_Pos            (0UL)          /*!< NUMLANE (Bit 0)                                       */
41099  #define R_DSILINK_TXSETR_NUMLANE_Msk            (0x3UL)        /*!< NUMLANE (Bitfield-Mask: 0x03)                         */
41100  #define R_DSILINK_TXSETR_CLEN_Pos               (8UL)          /*!< CLEN (Bit 8)                                          */
41101  #define R_DSILINK_TXSETR_CLEN_Msk               (0x100UL)      /*!< CLEN (Bitfield-Mask: 0x01)                            */
41102  #define R_DSILINK_TXSETR_DLEN_Pos               (9UL)          /*!< DLEN (Bit 9)                                          */
41103  #define R_DSILINK_TXSETR_DLEN_Msk               (0x200UL)      /*!< DLEN (Bitfield-Mask: 0x01)                            */
41104 /* =======================================================  HSCLKSETR  ======================================================= */
41105  #define R_DSILINK_HSCLKSETR_HSCLST_Pos          (0UL)          /*!< HSCLST (Bit 0)                                        */
41106  #define R_DSILINK_HSCLKSETR_HSCLST_Msk          (0x1UL)        /*!< HSCLST (Bitfield-Mask: 0x01)                          */
41107  #define R_DSILINK_HSCLKSETR_HSCLMD_Pos          (1UL)          /*!< HSCLMD (Bit 1)                                        */
41108  #define R_DSILINK_HSCLKSETR_HSCLMD_Msk          (0x2UL)        /*!< HSCLMD (Bitfield-Mask: 0x01)                          */
41109 /* =======================================================  ULPSSETR  ======================================================== */
41110  #define R_DSILINK_ULPSSETR_WKUP_Pos             (0UL)          /*!< WKUP (Bit 0)                                          */
41111  #define R_DSILINK_ULPSSETR_WKUP_Msk             (0xffUL)       /*!< WKUP (Bitfield-Mask: 0xff)                            */
41112 /* ========================================================  ULPSCR  ========================================================= */
41113  #define R_DSILINK_ULPSCR_CLENT_Pos              (24UL)         /*!< CLENT (Bit 24)                                        */
41114  #define R_DSILINK_ULPSCR_CLENT_Msk              (0x1000000UL)  /*!< CLENT (Bitfield-Mask: 0x01)                           */
41115  #define R_DSILINK_ULPSCR_CLEXIT_Pos             (25UL)         /*!< CLEXIT (Bit 25)                                       */
41116  #define R_DSILINK_ULPSCR_CLEXIT_Msk             (0x2000000UL)  /*!< CLEXIT (Bitfield-Mask: 0x01)                          */
41117  #define R_DSILINK_ULPSCR_DLENT_Pos              (28UL)         /*!< DLENT (Bit 28)                                        */
41118  #define R_DSILINK_ULPSCR_DLENT_Msk              (0x10000000UL) /*!< DLENT (Bitfield-Mask: 0x01)                           */
41119  #define R_DSILINK_ULPSCR_DLEXIT_Pos             (29UL)         /*!< DLEXIT (Bit 29)                                       */
41120  #define R_DSILINK_ULPSCR_DLEXIT_Msk             (0x20000000UL) /*!< DLEXIT (Bitfield-Mask: 0x01)                          */
41121 /* =========================================================  RSTCR  ========================================================= */
41122  #define R_DSILINK_RSTCR_SWRST_Pos               (0UL)          /*!< SWRST (Bit 0)                                         */
41123  #define R_DSILINK_RSTCR_SWRST_Msk               (0x1UL)        /*!< SWRST (Bitfield-Mask: 0x01)                           */
41124  #define R_DSILINK_RSTCR_FTXSTP_Pos              (16UL)         /*!< FTXSTP (Bit 16)                                       */
41125  #define R_DSILINK_RSTCR_FTXSTP_Msk              (0x10000UL)    /*!< FTXSTP (Bitfield-Mask: 0x01)                          */
41126 /* =========================================================  RSTSR  ========================================================= */
41127  #define R_DSILINK_RSTSR_RSTHS_Pos               (0UL)          /*!< RSTHS (Bit 0)                                         */
41128  #define R_DSILINK_RSTSR_RSTHS_Msk               (0x1UL)        /*!< RSTHS (Bitfield-Mask: 0x01)                           */
41129  #define R_DSILINK_RSTSR_RSTLP_Pos               (1UL)          /*!< RSTLP (Bit 1)                                         */
41130  #define R_DSILINK_RSTSR_RSTLP_Msk               (0x2UL)        /*!< RSTLP (Bitfield-Mask: 0x01)                           */
41131  #define R_DSILINK_RSTSR_RSTAPB_Pos              (2UL)          /*!< RSTAPB (Bit 2)                                        */
41132  #define R_DSILINK_RSTSR_RSTAPB_Msk              (0x4UL)        /*!< RSTAPB (Bitfield-Mask: 0x01)                          */
41133  #define R_DSILINK_RSTSR_RSTAXI_Pos              (3UL)          /*!< RSTAXI (Bit 3)                                        */
41134  #define R_DSILINK_RSTSR_RSTAXI_Msk              (0x8UL)        /*!< RSTAXI (Bitfield-Mask: 0x01)                          */
41135  #define R_DSILINK_RSTSR_RSTV_Pos                (4UL)          /*!< RSTV (Bit 4)                                          */
41136  #define R_DSILINK_RSTSR_RSTV_Msk                (0x10UL)       /*!< RSTV (Bitfield-Mask: 0x01)                            */
41137  #define R_DSILINK_RSTSR_DL0STP_Pos              (8UL)          /*!< DL0STP (Bit 8)                                        */
41138  #define R_DSILINK_RSTSR_DL0STP_Msk              (0x100UL)      /*!< DL0STP (Bitfield-Mask: 0x01)                          */
41139  #define R_DSILINK_RSTSR_DL1STP_Pos              (9UL)          /*!< DL1STP (Bit 9)                                        */
41140  #define R_DSILINK_RSTSR_DL1STP_Msk              (0x200UL)      /*!< DL1STP (Bitfield-Mask: 0x01)                          */
41141  #define R_DSILINK_RSTSR_DL0DIR_Pos              (15UL)         /*!< DL0DIR (Bit 15)                                       */
41142  #define R_DSILINK_RSTSR_DL0DIR_Msk              (0x8000UL)     /*!< DL0DIR (Bitfield-Mask: 0x01)                          */
41143 /* ========================================================  DSISETR  ======================================================== */
41144  #define R_DSILINK_DSISETR_MRPSZ_Pos             (0UL)          /*!< MRPSZ (Bit 0)                                         */
41145  #define R_DSILINK_DSISETR_MRPSZ_Msk             (0xffffUL)     /*!< MRPSZ (Bitfield-Mask: 0xffff)                         */
41146  #define R_DSILINK_DSISETR_ECCEN_Pos             (16UL)         /*!< ECCEN (Bit 16)                                        */
41147  #define R_DSILINK_DSISETR_ECCEN_Msk             (0x10000UL)    /*!< ECCEN (Bitfield-Mask: 0x01)                           */
41148  #define R_DSILINK_DSISETR_VC0CRCEN_Pos          (20UL)         /*!< VC0CRCEN (Bit 20)                                     */
41149  #define R_DSILINK_DSISETR_VC0CRCEN_Msk          (0x100000UL)   /*!< VC0CRCEN (Bitfield-Mask: 0x01)                        */
41150  #define R_DSILINK_DSISETR_VC1CRCEN_Pos          (21UL)         /*!< VC1CRCEN (Bit 21)                                     */
41151  #define R_DSILINK_DSISETR_VC1CRCEN_Msk          (0x200000UL)   /*!< VC1CRCEN (Bitfield-Mask: 0x01)                        */
41152  #define R_DSILINK_DSISETR_VC2CRCEN_Pos          (22UL)         /*!< VC2CRCEN (Bit 22)                                     */
41153  #define R_DSILINK_DSISETR_VC2CRCEN_Msk          (0x400000UL)   /*!< VC2CRCEN (Bitfield-Mask: 0x01)                        */
41154  #define R_DSILINK_DSISETR_VC3CRCEN_Pos          (23UL)         /*!< VC3CRCEN (Bit 23)                                     */
41155  #define R_DSILINK_DSISETR_VC3CRCEN_Msk          (0x800000UL)   /*!< VC3CRCEN (Bitfield-Mask: 0x01)                        */
41156  #define R_DSILINK_DSISETR_SCREN_Pos             (29UL)         /*!< SCREN (Bit 29)                                        */
41157  #define R_DSILINK_DSISETR_SCREN_Msk             (0x20000000UL) /*!< SCREN (Bitfield-Mask: 0x01)                           */
41158  #define R_DSILINK_DSISETR_EXTEMD_Pos            (30UL)         /*!< EXTEMD (Bit 30)                                       */
41159  #define R_DSILINK_DSISETR_EXTEMD_Msk            (0x40000000UL) /*!< EXTEMD (Bitfield-Mask: 0x01)                          */
41160  #define R_DSILINK_DSISETR_EOTPEN_Pos            (31UL)         /*!< EOTPEN (Bit 31)                                       */
41161  #define R_DSILINK_DSISETR_EOTPEN_Msk            (0x80000000UL) /*!< EOTPEN (Bitfield-Mask: 0x01)                          */
41162 /* ========================================================  TXPPD0R  ======================================================== */
41163  #define R_DSILINK_TXPPD0R_DATA0_Pos             (0UL)          /*!< DATA0 (Bit 0)                                         */
41164  #define R_DSILINK_TXPPD0R_DATA0_Msk             (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41165  #define R_DSILINK_TXPPD0R_DATA1_Pos             (8UL)          /*!< DATA1 (Bit 8)                                         */
41166  #define R_DSILINK_TXPPD0R_DATA1_Msk             (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41167  #define R_DSILINK_TXPPD0R_DATA2_Pos             (16UL)         /*!< DATA2 (Bit 16)                                        */
41168  #define R_DSILINK_TXPPD0R_DATA2_Msk             (0xff0000UL)   /*!< DATA2 (Bitfield-Mask: 0xff)                           */
41169  #define R_DSILINK_TXPPD0R_DATA3_Pos             (24UL)         /*!< DATA3 (Bit 24)                                        */
41170  #define R_DSILINK_TXPPD0R_DATA3_Msk             (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff)                           */
41171 /* ========================================================  TXPPD1R  ======================================================== */
41172  #define R_DSILINK_TXPPD1R_DATA4_Pos             (0UL)          /*!< DATA4 (Bit 0)                                         */
41173  #define R_DSILINK_TXPPD1R_DATA4_Msk             (0xffUL)       /*!< DATA4 (Bitfield-Mask: 0xff)                           */
41174  #define R_DSILINK_TXPPD1R_DATA5_Pos             (8UL)          /*!< DATA5 (Bit 8)                                         */
41175  #define R_DSILINK_TXPPD1R_DATA5_Msk             (0xff00UL)     /*!< DATA5 (Bitfield-Mask: 0xff)                           */
41176  #define R_DSILINK_TXPPD1R_DATA6_Pos             (16UL)         /*!< DATA6 (Bit 16)                                        */
41177  #define R_DSILINK_TXPPD1R_DATA6_Msk             (0xff0000UL)   /*!< DATA6 (Bitfield-Mask: 0xff)                           */
41178  #define R_DSILINK_TXPPD1R_DATA7_Pos             (24UL)         /*!< DATA7 (Bit 24)                                        */
41179  #define R_DSILINK_TXPPD1R_DATA7_Msk             (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff)                           */
41180 /* ========================================================  TXPPD2R  ======================================================== */
41181  #define R_DSILINK_TXPPD2R_DATA8_Pos             (0UL)          /*!< DATA8 (Bit 0)                                         */
41182  #define R_DSILINK_TXPPD2R_DATA8_Msk             (0xffUL)       /*!< DATA8 (Bitfield-Mask: 0xff)                           */
41183  #define R_DSILINK_TXPPD2R_DATA9_Pos             (8UL)          /*!< DATA9 (Bit 8)                                         */
41184  #define R_DSILINK_TXPPD2R_DATA9_Msk             (0xff00UL)     /*!< DATA9 (Bitfield-Mask: 0xff)                           */
41185  #define R_DSILINK_TXPPD2R_DATA10_Pos            (16UL)         /*!< DATA10 (Bit 16)                                       */
41186  #define R_DSILINK_TXPPD2R_DATA10_Msk            (0xff0000UL)   /*!< DATA10 (Bitfield-Mask: 0xff)                          */
41187  #define R_DSILINK_TXPPD2R_DATA11_Pos            (24UL)         /*!< DATA11 (Bit 24)                                       */
41188  #define R_DSILINK_TXPPD2R_DATA11_Msk            (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff)                          */
41189 /* ========================================================  TXPPD3R  ======================================================== */
41190  #define R_DSILINK_TXPPD3R_DATA12_Pos            (0UL)          /*!< DATA12 (Bit 0)                                        */
41191  #define R_DSILINK_TXPPD3R_DATA12_Msk            (0xffUL)       /*!< DATA12 (Bitfield-Mask: 0xff)                          */
41192  #define R_DSILINK_TXPPD3R_DATA13_Pos            (8UL)          /*!< DATA13 (Bit 8)                                        */
41193  #define R_DSILINK_TXPPD3R_DATA13_Msk            (0xff00UL)     /*!< DATA13 (Bitfield-Mask: 0xff)                          */
41194  #define R_DSILINK_TXPPD3R_DATA14_Pos            (16UL)         /*!< DATA14 (Bit 16)                                       */
41195  #define R_DSILINK_TXPPD3R_DATA14_Msk            (0xff0000UL)   /*!< DATA14 (Bitfield-Mask: 0xff)                          */
41196  #define R_DSILINK_TXPPD3R_DATA15_Pos            (24UL)         /*!< DATA15 (Bit 24)                                       */
41197  #define R_DSILINK_TXPPD3R_DATA15_Msk            (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff)                          */
41198 /* =========================================================  RXSR  ========================================================== */
41199  #define R_DSILINK_RXSR_BTAREND_Pos              (0UL)          /*!< BTAREND (Bit 0)                                       */
41200  #define R_DSILINK_RXSR_BTAREND_Msk              (0x1UL)        /*!< BTAREND (Bitfield-Mask: 0x01)                         */
41201  #define R_DSILINK_RXSR_LRXHTO_Pos               (1UL)          /*!< LRXHTO (Bit 1)                                        */
41202  #define R_DSILINK_RXSR_LRXHTO_Msk               (0x2UL)        /*!< LRXHTO (Bitfield-Mask: 0x01)                          */
41203  #define R_DSILINK_RXSR_TATO_Pos                 (2UL)          /*!< TATO (Bit 2)                                          */
41204  #define R_DSILINK_RXSR_TATO_Msk                 (0x4UL)        /*!< TATO (Bitfield-Mask: 0x01)                            */
41205  #define R_DSILINK_RXSR_RXRESP_Pos               (8UL)          /*!< RXRESP (Bit 8)                                        */
41206  #define R_DSILINK_RXSR_RXRESP_Msk               (0x100UL)      /*!< RXRESP (Bitfield-Mask: 0x01)                          */
41207  #define R_DSILINK_RXSR_RXEOTP_Pos               (10UL)         /*!< RXEOTP (Bit 10)                                       */
41208  #define R_DSILINK_RXSR_RXEOTP_Msk               (0x400UL)      /*!< RXEOTP (Bitfield-Mask: 0x01)                          */
41209  #define R_DSILINK_RXSR_RXTE_Pos                 (13UL)         /*!< RXTE (Bit 13)                                         */
41210  #define R_DSILINK_RXSR_RXTE_Msk                 (0x2000UL)     /*!< RXTE (Bitfield-Mask: 0x01)                            */
41211  #define R_DSILINK_RXSR_RXACK_Pos                (14UL)         /*!< RXACK (Bit 14)                                        */
41212  #define R_DSILINK_RXSR_RXACK_Msk                (0x4000UL)     /*!< RXACK (Bitfield-Mask: 0x01)                           */
41213  #define R_DSILINK_RXSR_EXTEDET_Pos              (15UL)         /*!< EXTEDET (Bit 15)                                      */
41214  #define R_DSILINK_RXSR_EXTEDET_Msk              (0x8000UL)     /*!< EXTEDET (Bitfield-Mask: 0x01)                         */
41215  #define R_DSILINK_RXSR_MLFERR_Pos               (16UL)         /*!< MLFERR (Bit 16)                                       */
41216  #define R_DSILINK_RXSR_MLFERR_Msk               (0x10000UL)    /*!< MLFERR (Bitfield-Mask: 0x01)                          */
41217  #define R_DSILINK_RXSR_ECCERRM_Pos              (17UL)         /*!< ECCERRM (Bit 17)                                      */
41218  #define R_DSILINK_RXSR_ECCERRM_Msk              (0x20000UL)    /*!< ECCERRM (Bitfield-Mask: 0x01)                         */
41219  #define R_DSILINK_RXSR_UNEXERR_Pos              (18UL)         /*!< UNEXERR (Bit 18)                                      */
41220  #define R_DSILINK_RXSR_UNEXERR_Msk              (0x40000UL)    /*!< UNEXERR (Bitfield-Mask: 0x01)                         */
41221  #define R_DSILINK_RXSR_WCERR_Pos                (20UL)         /*!< WCERR (Bit 20)                                        */
41222  #define R_DSILINK_RXSR_WCERR_Msk                (0x100000UL)   /*!< WCERR (Bitfield-Mask: 0x01)                           */
41223  #define R_DSILINK_RXSR_CRCERR_Pos               (21UL)         /*!< CRCERR (Bit 21)                                       */
41224  #define R_DSILINK_RXSR_CRCERR_Msk               (0x200000UL)   /*!< CRCERR (Bitfield-Mask: 0x01)                          */
41225  #define R_DSILINK_RXSR_IBERR_Pos                (22UL)         /*!< IBERR (Bit 22)                                        */
41226  #define R_DSILINK_RXSR_IBERR_Msk                (0x400000UL)   /*!< IBERR (Bitfield-Mask: 0x01)                           */
41227  #define R_DSILINK_RXSR_RXOVFERR_Pos             (23UL)         /*!< RXOVFERR (Bit 23)                                     */
41228  #define R_DSILINK_RXSR_RXOVFERR_Msk             (0x800000UL)   /*!< RXOVFERR (Bitfield-Mask: 0x01)                        */
41229  #define R_DSILINK_RXSR_PRTOERR_Pos              (24UL)         /*!< PRTOERR (Bit 24)                                      */
41230  #define R_DSILINK_RXSR_PRTOERR_Msk              (0x1000000UL)  /*!< PRTOERR (Bitfield-Mask: 0x01)                         */
41231  #define R_DSILINK_RXSR_NORESERR_Pos             (25UL)         /*!< NORESERR (Bit 25)                                     */
41232  #define R_DSILINK_RXSR_NORESERR_Msk             (0x2000000UL)  /*!< NORESERR (Bitfield-Mask: 0x01)                        */
41233  #define R_DSILINK_RXSR_RSIZEERR_Pos             (26UL)         /*!< RSIZEERR (Bit 26)                                     */
41234  #define R_DSILINK_RXSR_RSIZEERR_Msk             (0x4000000UL)  /*!< RSIZEERR (Bitfield-Mask: 0x01)                        */
41235  #define R_DSILINK_RXSR_ECCERRS_Pos              (28UL)         /*!< ECCERRS (Bit 28)                                      */
41236  #define R_DSILINK_RXSR_ECCERRS_Msk              (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01)                         */
41237  #define R_DSILINK_RXSR_RXAKE_Pos                (30UL)         /*!< RXAKE (Bit 30)                                        */
41238  #define R_DSILINK_RXSR_RXAKE_Msk                (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41239 /* =========================================================  RXSCR  ========================================================= */
41240  #define R_DSILINK_RXSCR_BTAREND_Pos             (0UL)          /*!< BTAREND (Bit 0)                                       */
41241  #define R_DSILINK_RXSCR_BTAREND_Msk             (0x1UL)        /*!< BTAREND (Bitfield-Mask: 0x01)                         */
41242  #define R_DSILINK_RXSCR_LRXHTO_Pos              (1UL)          /*!< LRXHTO (Bit 1)                                        */
41243  #define R_DSILINK_RXSCR_LRXHTO_Msk              (0x2UL)        /*!< LRXHTO (Bitfield-Mask: 0x01)                          */
41244  #define R_DSILINK_RXSCR_TATO_Pos                (2UL)          /*!< TATO (Bit 2)                                          */
41245  #define R_DSILINK_RXSCR_TATO_Msk                (0x4UL)        /*!< TATO (Bitfield-Mask: 0x01)                            */
41246  #define R_DSILINK_RXSCR_RXRESP_Pos              (8UL)          /*!< RXRESP (Bit 8)                                        */
41247  #define R_DSILINK_RXSCR_RXRESP_Msk              (0x100UL)      /*!< RXRESP (Bitfield-Mask: 0x01)                          */
41248  #define R_DSILINK_RXSCR_RXEOTP_Pos              (10UL)         /*!< RXEOTP (Bit 10)                                       */
41249  #define R_DSILINK_RXSCR_RXEOTP_Msk              (0x400UL)      /*!< RXEOTP (Bitfield-Mask: 0x01)                          */
41250  #define R_DSILINK_RXSCR_RXTE_Pos                (13UL)         /*!< RXTE (Bit 13)                                         */
41251  #define R_DSILINK_RXSCR_RXTE_Msk                (0x2000UL)     /*!< RXTE (Bitfield-Mask: 0x01)                            */
41252  #define R_DSILINK_RXSCR_RXACK_Pos               (14UL)         /*!< RXACK (Bit 14)                                        */
41253  #define R_DSILINK_RXSCR_RXACK_Msk               (0x4000UL)     /*!< RXACK (Bitfield-Mask: 0x01)                           */
41254  #define R_DSILINK_RXSCR_EXTEDET_Pos             (15UL)         /*!< EXTEDET (Bit 15)                                      */
41255  #define R_DSILINK_RXSCR_EXTEDET_Msk             (0x8000UL)     /*!< EXTEDET (Bitfield-Mask: 0x01)                         */
41256  #define R_DSILINK_RXSCR_MLFERR_Pos              (16UL)         /*!< MLFERR (Bit 16)                                       */
41257  #define R_DSILINK_RXSCR_MLFERR_Msk              (0x10000UL)    /*!< MLFERR (Bitfield-Mask: 0x01)                          */
41258  #define R_DSILINK_RXSCR_ECCERRM_Pos             (17UL)         /*!< ECCERRM (Bit 17)                                      */
41259  #define R_DSILINK_RXSCR_ECCERRM_Msk             (0x20000UL)    /*!< ECCERRM (Bitfield-Mask: 0x01)                         */
41260  #define R_DSILINK_RXSCR_UNEXERR_Pos             (18UL)         /*!< UNEXERR (Bit 18)                                      */
41261  #define R_DSILINK_RXSCR_UNEXERR_Msk             (0x40000UL)    /*!< UNEXERR (Bitfield-Mask: 0x01)                         */
41262  #define R_DSILINK_RXSCR_WCERR_Pos               (20UL)         /*!< WCERR (Bit 20)                                        */
41263  #define R_DSILINK_RXSCR_WCERR_Msk               (0x100000UL)   /*!< WCERR (Bitfield-Mask: 0x01)                           */
41264  #define R_DSILINK_RXSCR_CRCERR_Pos              (21UL)         /*!< CRCERR (Bit 21)                                       */
41265  #define R_DSILINK_RXSCR_CRCERR_Msk              (0x200000UL)   /*!< CRCERR (Bitfield-Mask: 0x01)                          */
41266  #define R_DSILINK_RXSCR_IBERR_Pos               (22UL)         /*!< IBERR (Bit 22)                                        */
41267  #define R_DSILINK_RXSCR_IBERR_Msk               (0x400000UL)   /*!< IBERR (Bitfield-Mask: 0x01)                           */
41268  #define R_DSILINK_RXSCR_RXOVFERR_Pos            (23UL)         /*!< RXOVFERR (Bit 23)                                     */
41269  #define R_DSILINK_RXSCR_RXOVFERR_Msk            (0x800000UL)   /*!< RXOVFERR (Bitfield-Mask: 0x01)                        */
41270  #define R_DSILINK_RXSCR_PRTOERR_Pos             (24UL)         /*!< PRTOERR (Bit 24)                                      */
41271  #define R_DSILINK_RXSCR_PRTOERR_Msk             (0x1000000UL)  /*!< PRTOERR (Bitfield-Mask: 0x01)                         */
41272  #define R_DSILINK_RXSCR_NORESERR_Pos            (25UL)         /*!< NORESERR (Bit 25)                                     */
41273  #define R_DSILINK_RXSCR_NORESERR_Msk            (0x2000000UL)  /*!< NORESERR (Bitfield-Mask: 0x01)                        */
41274  #define R_DSILINK_RXSCR_RSIZEERR_Pos            (26UL)         /*!< RSIZEERR (Bit 26)                                     */
41275  #define R_DSILINK_RXSCR_RSIZEERR_Msk            (0x4000000UL)  /*!< RSIZEERR (Bitfield-Mask: 0x01)                        */
41276  #define R_DSILINK_RXSCR_ECCERRS_Pos             (28UL)         /*!< ECCERRS (Bit 28)                                      */
41277  #define R_DSILINK_RXSCR_ECCERRS_Msk             (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01)                         */
41278  #define R_DSILINK_RXSCR_RXAKE_Pos               (30UL)         /*!< RXAKE (Bit 30)                                        */
41279  #define R_DSILINK_RXSCR_RXAKE_Msk               (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41280 /* =========================================================  RXIER  ========================================================= */
41281  #define R_DSILINK_RXIER_BTAREND_Pos             (0UL)          /*!< BTAREND (Bit 0)                                       */
41282  #define R_DSILINK_RXIER_BTAREND_Msk             (0x1UL)        /*!< BTAREND (Bitfield-Mask: 0x01)                         */
41283  #define R_DSILINK_RXIER_LRXHTO_Pos              (1UL)          /*!< LRXHTO (Bit 1)                                        */
41284  #define R_DSILINK_RXIER_LRXHTO_Msk              (0x2UL)        /*!< LRXHTO (Bitfield-Mask: 0x01)                          */
41285  #define R_DSILINK_RXIER_TATO_Pos                (2UL)          /*!< TATO (Bit 2)                                          */
41286  #define R_DSILINK_RXIER_TATO_Msk                (0x4UL)        /*!< TATO (Bitfield-Mask: 0x01)                            */
41287  #define R_DSILINK_RXIER_RXRESP_Pos              (8UL)          /*!< RXRESP (Bit 8)                                        */
41288  #define R_DSILINK_RXIER_RXRESP_Msk              (0x100UL)      /*!< RXRESP (Bitfield-Mask: 0x01)                          */
41289  #define R_DSILINK_RXIER_RXEOTP_Pos              (10UL)         /*!< RXEOTP (Bit 10)                                       */
41290  #define R_DSILINK_RXIER_RXEOTP_Msk              (0x400UL)      /*!< RXEOTP (Bitfield-Mask: 0x01)                          */
41291  #define R_DSILINK_RXIER_RXTE_Pos                (13UL)         /*!< RXTE (Bit 13)                                         */
41292  #define R_DSILINK_RXIER_RXTE_Msk                (0x2000UL)     /*!< RXTE (Bitfield-Mask: 0x01)                            */
41293  #define R_DSILINK_RXIER_RXACK_Pos               (14UL)         /*!< RXACK (Bit 14)                                        */
41294  #define R_DSILINK_RXIER_RXACK_Msk               (0x4000UL)     /*!< RXACK (Bitfield-Mask: 0x01)                           */
41295  #define R_DSILINK_RXIER_EXTEDET_Pos             (15UL)         /*!< EXTEDET (Bit 15)                                      */
41296  #define R_DSILINK_RXIER_EXTEDET_Msk             (0x8000UL)     /*!< EXTEDET (Bitfield-Mask: 0x01)                         */
41297  #define R_DSILINK_RXIER_MLFERR_Pos              (16UL)         /*!< MLFERR (Bit 16)                                       */
41298  #define R_DSILINK_RXIER_MLFERR_Msk              (0x10000UL)    /*!< MLFERR (Bitfield-Mask: 0x01)                          */
41299  #define R_DSILINK_RXIER_ECCERRM_Pos             (17UL)         /*!< ECCERRM (Bit 17)                                      */
41300  #define R_DSILINK_RXIER_ECCERRM_Msk             (0x20000UL)    /*!< ECCERRM (Bitfield-Mask: 0x01)                         */
41301  #define R_DSILINK_RXIER_UNEXERR_Pos             (18UL)         /*!< UNEXERR (Bit 18)                                      */
41302  #define R_DSILINK_RXIER_UNEXERR_Msk             (0x40000UL)    /*!< UNEXERR (Bitfield-Mask: 0x01)                         */
41303  #define R_DSILINK_RXIER_WCERR_Pos               (20UL)         /*!< WCERR (Bit 20)                                        */
41304  #define R_DSILINK_RXIER_WCERR_Msk               (0x100000UL)   /*!< WCERR (Bitfield-Mask: 0x01)                           */
41305  #define R_DSILINK_RXIER_CRCERR_Pos              (21UL)         /*!< CRCERR (Bit 21)                                       */
41306  #define R_DSILINK_RXIER_CRCERR_Msk              (0x200000UL)   /*!< CRCERR (Bitfield-Mask: 0x01)                          */
41307  #define R_DSILINK_RXIER_IBERR_Pos               (22UL)         /*!< IBERR (Bit 22)                                        */
41308  #define R_DSILINK_RXIER_IBERR_Msk               (0x400000UL)   /*!< IBERR (Bitfield-Mask: 0x01)                           */
41309  #define R_DSILINK_RXIER_RXOVFERR_Pos            (23UL)         /*!< RXOVFERR (Bit 23)                                     */
41310  #define R_DSILINK_RXIER_RXOVFERR_Msk            (0x800000UL)   /*!< RXOVFERR (Bitfield-Mask: 0x01)                        */
41311  #define R_DSILINK_RXIER_PRTOERR_Pos             (24UL)         /*!< PRTOERR (Bit 24)                                      */
41312  #define R_DSILINK_RXIER_PRTOERR_Msk             (0x1000000UL)  /*!< PRTOERR (Bitfield-Mask: 0x01)                         */
41313  #define R_DSILINK_RXIER_NORESERR_Pos            (25UL)         /*!< NORESERR (Bit 25)                                     */
41314  #define R_DSILINK_RXIER_NORESERR_Msk            (0x2000000UL)  /*!< NORESERR (Bitfield-Mask: 0x01)                        */
41315  #define R_DSILINK_RXIER_RSIZEERR_Pos            (26UL)         /*!< RSIZEERR (Bit 26)                                     */
41316  #define R_DSILINK_RXIER_RSIZEERR_Msk            (0x4000000UL)  /*!< RSIZEERR (Bitfield-Mask: 0x01)                        */
41317  #define R_DSILINK_RXIER_ECCERRS_Pos             (28UL)         /*!< ECCERRS (Bit 28)                                      */
41318  #define R_DSILINK_RXIER_ECCERRS_Msk             (0x10000000UL) /*!< ECCERRS (Bitfield-Mask: 0x01)                         */
41319  #define R_DSILINK_RXIER_RXAKE_Pos               (30UL)         /*!< RXAKE (Bit 30)                                        */
41320  #define R_DSILINK_RXIER_RXAKE_Msk               (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41321 /* ====================================================  PRESPTOBTASETR  ===================================================== */
41322  #define R_DSILINK_PRESPTOBTASETR_PRTBTA_Pos     (0UL)          /*!< PRTBTA (Bit 0)                                        */
41323  #define R_DSILINK_PRESPTOBTASETR_PRTBTA_Msk     (0xffffffffUL) /*!< PRTBTA (Bitfield-Mask: 0xffffffff)                    */
41324 /* =====================================================  PRESPTOLPSETR  ===================================================== */
41325  #define R_DSILINK_PRESPTOLPSETR_LPWTO_Pos       (0UL)          /*!< LPWTO (Bit 0)                                         */
41326  #define R_DSILINK_PRESPTOLPSETR_LPWTO_Msk       (0xffffUL)     /*!< LPWTO (Bitfield-Mask: 0xffff)                         */
41327  #define R_DSILINK_PRESPTOLPSETR_LPRTO_Pos       (16UL)         /*!< LPRTO (Bit 16)                                        */
41328  #define R_DSILINK_PRESPTOLPSETR_LPRTO_Msk       (0xffff0000UL) /*!< LPRTO (Bitfield-Mask: 0xffff)                         */
41329 /* =====================================================  PRESPTOHSSETR  ===================================================== */
41330  #define R_DSILINK_PRESPTOHSSETR_HSWTO_Pos       (0UL)          /*!< HSWTO (Bit 0)                                         */
41331  #define R_DSILINK_PRESPTOHSSETR_HSWTO_Msk       (0xffffUL)     /*!< HSWTO (Bitfield-Mask: 0xffff)                         */
41332  #define R_DSILINK_PRESPTOHSSETR_HSRTO_Pos       (16UL)         /*!< HSRTO (Bit 16)                                        */
41333  #define R_DSILINK_PRESPTOHSSETR_HSRTO_Msk       (0xffff0000UL) /*!< HSRTO (Bitfield-Mask: 0xffff)                         */
41334 /* =======================================================  AKEPLATIR  ======================================================= */
41335  #define R_DSILINK_AKEPLATIR_EREP_Pos            (0UL)          /*!< EREP (Bit 0)                                          */
41336  #define R_DSILINK_AKEPLATIR_EREP_Msk            (0xffffUL)     /*!< EREP (Bitfield-Mask: 0xffff)                          */
41337  #define R_DSILINK_AKEPLATIR_VC_Pos              (16UL)         /*!< VC (Bit 16)                                           */
41338  #define R_DSILINK_AKEPLATIR_VC_Msk              (0xf0000UL)    /*!< VC (Bitfield-Mask: 0x0f)                              */
41339 /* =======================================================  AKEPACMSR  ======================================================= */
41340  #define R_DSILINK_AKEPACMSR_AEREP_Pos           (0UL)          /*!< AEREP (Bit 0)                                         */
41341  #define R_DSILINK_AKEPACMSR_AEREP_Msk           (0xffffUL)     /*!< AEREP (Bitfield-Mask: 0xffff)                         */
41342  #define R_DSILINK_AKEPACMSR_AVC_Pos             (16UL)         /*!< AVC (Bit 16)                                          */
41343  #define R_DSILINK_AKEPACMSR_AVC_Msk             (0xf0000UL)    /*!< AVC (Bitfield-Mask: 0x0f)                             */
41344 /* ========================================================  AKEPSCR  ======================================================== */
41345  #define R_DSILINK_AKEPSCR_AEREP_Pos             (0UL)          /*!< AEREP (Bit 0)                                         */
41346  #define R_DSILINK_AKEPSCR_AEREP_Msk             (0xffffUL)     /*!< AEREP (Bitfield-Mask: 0xffff)                         */
41347  #define R_DSILINK_AKEPSCR_AVC_Pos               (16UL)         /*!< AVC (Bit 16)                                          */
41348  #define R_DSILINK_AKEPSCR_AVC_Msk               (0xf0000UL)    /*!< AVC (Bitfield-Mask: 0x0f)                             */
41349 /* ========================================================  RXRSSR  ========================================================= */
41350  #define R_DSILINK_RXRSSR_SLT0VLD_Pos            (0UL)          /*!< SLT0VLD (Bit 0)                                       */
41351  #define R_DSILINK_RXRSSR_SLT0VLD_Msk            (0x1UL)        /*!< SLT0VLD (Bitfield-Mask: 0x01)                         */
41352  #define R_DSILINK_RXRSSR_SLT1VLD_Pos            (1UL)          /*!< SLT1VLD (Bit 1)                                       */
41353  #define R_DSILINK_RXRSSR_SLT1VLD_Msk            (0x2UL)        /*!< SLT1VLD (Bitfield-Mask: 0x01)                         */
41354  #define R_DSILINK_RXRSSR_SLT2VLD_Pos            (2UL)          /*!< SLT2VLD (Bit 2)                                       */
41355  #define R_DSILINK_RXRSSR_SLT2VLD_Msk            (0x4UL)        /*!< SLT2VLD (Bitfield-Mask: 0x01)                         */
41356  #define R_DSILINK_RXRSSR_SLT3VLD_Pos            (3UL)          /*!< SLT3VLD (Bit 3)                                       */
41357  #define R_DSILINK_RXRSSR_SLT3VLD_Msk            (0x8UL)        /*!< SLT3VLD (Bitfield-Mask: 0x01)                         */
41358 /* ========================================================  RXRSSCR  ======================================================== */
41359  #define R_DSILINK_RXRSSCR_SLT0VLD_Pos           (0UL)          /*!< SLT0VLD (Bit 0)                                       */
41360  #define R_DSILINK_RXRSSCR_SLT0VLD_Msk           (0x1UL)        /*!< SLT0VLD (Bitfield-Mask: 0x01)                         */
41361  #define R_DSILINK_RXRSSCR_SLT1VLD_Pos           (1UL)          /*!< SLT1VLD (Bit 1)                                       */
41362  #define R_DSILINK_RXRSSCR_SLT1VLD_Msk           (0x2UL)        /*!< SLT1VLD (Bitfield-Mask: 0x01)                         */
41363  #define R_DSILINK_RXRSSCR_SLT2VLD_Pos           (2UL)          /*!< SLT2VLD (Bit 2)                                       */
41364  #define R_DSILINK_RXRSSCR_SLT2VLD_Msk           (0x4UL)        /*!< SLT2VLD (Bitfield-Mask: 0x01)                         */
41365  #define R_DSILINK_RXRSSCR_SLT3VLD_Pos           (3UL)          /*!< SLT3VLD (Bit 3)                                       */
41366  #define R_DSILINK_RXRSSCR_SLT3VLD_Msk           (0x8UL)        /*!< SLT3VLD (Bitfield-Mask: 0x01)                         */
41367 /* ======================================================  RXRINFOOWSR  ====================================================== */
41368  #define R_DSILINK_RXRINFOOWSR_SL0OW_Pos         (0UL)          /*!< SL0OW (Bit 0)                                         */
41369  #define R_DSILINK_RXRINFOOWSR_SL0OW_Msk         (0x1UL)        /*!< SL0OW (Bitfield-Mask: 0x01)                           */
41370  #define R_DSILINK_RXRINFOOWSR_SL1OW_Pos         (1UL)          /*!< SL1OW (Bit 1)                                         */
41371  #define R_DSILINK_RXRINFOOWSR_SL1OW_Msk         (0x2UL)        /*!< SL1OW (Bitfield-Mask: 0x01)                           */
41372  #define R_DSILINK_RXRINFOOWSR_SL2OW_Pos         (2UL)          /*!< SL2OW (Bit 2)                                         */
41373  #define R_DSILINK_RXRINFOOWSR_SL2OW_Msk         (0x4UL)        /*!< SL2OW (Bitfield-Mask: 0x01)                           */
41374  #define R_DSILINK_RXRINFOOWSR_SL3OW_Pos         (3UL)          /*!< SL3OW (Bit 3)                                         */
41375  #define R_DSILINK_RXRINFOOWSR_SL3OW_Msk         (0x8UL)        /*!< SL3OW (Bitfield-Mask: 0x01)                           */
41376 /* =====================================================  RXRINFOOWSCR  ====================================================== */
41377  #define R_DSILINK_RXRINFOOWSCR_SL0OW_Pos        (0UL)          /*!< SL0OW (Bit 0)                                         */
41378  #define R_DSILINK_RXRINFOOWSCR_SL0OW_Msk        (0x1UL)        /*!< SL0OW (Bitfield-Mask: 0x01)                           */
41379  #define R_DSILINK_RXRINFOOWSCR_SL1OW_Pos        (1UL)          /*!< SL1OW (Bit 1)                                         */
41380  #define R_DSILINK_RXRINFOOWSCR_SL1OW_Msk        (0x2UL)        /*!< SL1OW (Bitfield-Mask: 0x01)                           */
41381  #define R_DSILINK_RXRINFOOWSCR_SL2OW_Pos        (2UL)          /*!< SL2OW (Bit 2)                                         */
41382  #define R_DSILINK_RXRINFOOWSCR_SL2OW_Msk        (0x4UL)        /*!< SL2OW (Bitfield-Mask: 0x01)                           */
41383  #define R_DSILINK_RXRINFOOWSCR_SL3OW_Pos        (3UL)          /*!< SL3OW (Bit 3)                                         */
41384  #define R_DSILINK_RXRINFOOWSCR_SL3OW_Msk        (0x8UL)        /*!< SL3OW (Bitfield-Mask: 0x01)                           */
41385 /* ========================================================  RXRSS0R  ======================================================== */
41386  #define R_DSILINK_RXRSS0R_DATA0_Pos             (0UL)          /*!< DATA0 (Bit 0)                                         */
41387  #define R_DSILINK_RXRSS0R_DATA0_Msk             (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41388  #define R_DSILINK_RXRSS0R_DATA1_Pos             (8UL)          /*!< DATA1 (Bit 8)                                         */
41389  #define R_DSILINK_RXRSS0R_DATA1_Msk             (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41390  #define R_DSILINK_RXRSS0R_DT_Pos                (16UL)         /*!< DT (Bit 16)                                           */
41391  #define R_DSILINK_RXRSS0R_DT_Msk                (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
41392  #define R_DSILINK_RXRSS0R_VC_Pos                (22UL)         /*!< VC (Bit 22)                                           */
41393  #define R_DSILINK_RXRSS0R_VC_Msk                (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
41394  #define R_DSILINK_RXRSS0R_FMT_Pos               (24UL)         /*!< FMT (Bit 24)                                          */
41395  #define R_DSILINK_RXRSS0R_FMT_Msk               (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
41396  #define R_DSILINK_RXRSS0R_RXSUC_Pos             (25UL)         /*!< RXSUC (Bit 25)                                        */
41397  #define R_DSILINK_RXRSS0R_RXSUC_Msk             (0x2000000UL)  /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41398  #define R_DSILINK_RXRSS0R_RXFERR_Pos            (26UL)         /*!< RXFERR (Bit 26)                                       */
41399  #define R_DSILINK_RXRSS0R_RXFERR_Msk            (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41400  #define R_DSILINK_RXRSS0R_RXFAIL_Pos            (27UL)         /*!< RXFAIL (Bit 27)                                       */
41401  #define R_DSILINK_RXRSS0R_RXFAIL_Msk            (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41402  #define R_DSILINK_RXRSS0R_RXPFAIL_Pos           (28UL)         /*!< RXPFAIL (Bit 28)                                      */
41403  #define R_DSILINK_RXRSS0R_RXPFAIL_Msk           (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41404  #define R_DSILINK_RXRSS0R_RXCERR_Pos            (29UL)         /*!< RXCERR (Bit 29)                                       */
41405  #define R_DSILINK_RXRSS0R_RXCERR_Msk            (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41406  #define R_DSILINK_RXRSS0R_RXAKE_Pos             (30UL)         /*!< RXAKE (Bit 30)                                        */
41407  #define R_DSILINK_RXRSS0R_RXAKE_Msk             (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41408  #define R_DSILINK_RXRSS0R_INFOOW_Pos            (31UL)         /*!< INFOOW (Bit 31)                                       */
41409  #define R_DSILINK_RXRSS0R_INFOOW_Msk            (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41410 /* ========================================================  RXRSS1R  ======================================================== */
41411  #define R_DSILINK_RXRSS1R_DATA0_Pos             (0UL)          /*!< DATA0 (Bit 0)                                         */
41412  #define R_DSILINK_RXRSS1R_DATA0_Msk             (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41413  #define R_DSILINK_RXRSS1R_DATA1_Pos             (8UL)          /*!< DATA1 (Bit 8)                                         */
41414  #define R_DSILINK_RXRSS1R_DATA1_Msk             (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41415  #define R_DSILINK_RXRSS1R_DT_Pos                (16UL)         /*!< DT (Bit 16)                                           */
41416  #define R_DSILINK_RXRSS1R_DT_Msk                (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
41417  #define R_DSILINK_RXRSS1R_VC_Pos                (22UL)         /*!< VC (Bit 22)                                           */
41418  #define R_DSILINK_RXRSS1R_VC_Msk                (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
41419  #define R_DSILINK_RXRSS1R_FMT_Pos               (24UL)         /*!< FMT (Bit 24)                                          */
41420  #define R_DSILINK_RXRSS1R_FMT_Msk               (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
41421  #define R_DSILINK_RXRSS1R_RXSUC_Pos             (25UL)         /*!< RXSUC (Bit 25)                                        */
41422  #define R_DSILINK_RXRSS1R_RXSUC_Msk             (0x2000000UL)  /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41423  #define R_DSILINK_RXRSS1R_RXFERR_Pos            (26UL)         /*!< RXFERR (Bit 26)                                       */
41424  #define R_DSILINK_RXRSS1R_RXFERR_Msk            (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41425  #define R_DSILINK_RXRSS1R_RXFAIL_Pos            (27UL)         /*!< RXFAIL (Bit 27)                                       */
41426  #define R_DSILINK_RXRSS1R_RXFAIL_Msk            (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41427  #define R_DSILINK_RXRSS1R_RXPFAIL_Pos           (28UL)         /*!< RXPFAIL (Bit 28)                                      */
41428  #define R_DSILINK_RXRSS1R_RXPFAIL_Msk           (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41429  #define R_DSILINK_RXRSS1R_RXCERR_Pos            (29UL)         /*!< RXCERR (Bit 29)                                       */
41430  #define R_DSILINK_RXRSS1R_RXCERR_Msk            (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41431  #define R_DSILINK_RXRSS1R_RXAKE_Pos             (30UL)         /*!< RXAKE (Bit 30)                                        */
41432  #define R_DSILINK_RXRSS1R_RXAKE_Msk             (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41433  #define R_DSILINK_RXRSS1R_INFOOW_Pos            (31UL)         /*!< INFOOW (Bit 31)                                       */
41434  #define R_DSILINK_RXRSS1R_INFOOW_Msk            (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41435 /* ========================================================  RXRSS2R  ======================================================== */
41436  #define R_DSILINK_RXRSS2R_DATA0_Pos             (0UL)          /*!< DATA0 (Bit 0)                                         */
41437  #define R_DSILINK_RXRSS2R_DATA0_Msk             (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41438  #define R_DSILINK_RXRSS2R_DATA1_Pos             (8UL)          /*!< DATA1 (Bit 8)                                         */
41439  #define R_DSILINK_RXRSS2R_DATA1_Msk             (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41440  #define R_DSILINK_RXRSS2R_DT_Pos                (16UL)         /*!< DT (Bit 16)                                           */
41441  #define R_DSILINK_RXRSS2R_DT_Msk                (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
41442  #define R_DSILINK_RXRSS2R_VC_Pos                (22UL)         /*!< VC (Bit 22)                                           */
41443  #define R_DSILINK_RXRSS2R_VC_Msk                (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
41444  #define R_DSILINK_RXRSS2R_FMT_Pos               (24UL)         /*!< FMT (Bit 24)                                          */
41445  #define R_DSILINK_RXRSS2R_FMT_Msk               (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
41446  #define R_DSILINK_RXRSS2R_RXSUC_Pos             (25UL)         /*!< RXSUC (Bit 25)                                        */
41447  #define R_DSILINK_RXRSS2R_RXSUC_Msk             (0x2000000UL)  /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41448  #define R_DSILINK_RXRSS2R_RXFERR_Pos            (26UL)         /*!< RXFERR (Bit 26)                                       */
41449  #define R_DSILINK_RXRSS2R_RXFERR_Msk            (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41450  #define R_DSILINK_RXRSS2R_RXFAIL_Pos            (27UL)         /*!< RXFAIL (Bit 27)                                       */
41451  #define R_DSILINK_RXRSS2R_RXFAIL_Msk            (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41452  #define R_DSILINK_RXRSS2R_RXPFAIL_Pos           (28UL)         /*!< RXPFAIL (Bit 28)                                      */
41453  #define R_DSILINK_RXRSS2R_RXPFAIL_Msk           (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41454  #define R_DSILINK_RXRSS2R_RXCERR_Pos            (29UL)         /*!< RXCERR (Bit 29)                                       */
41455  #define R_DSILINK_RXRSS2R_RXCERR_Msk            (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41456  #define R_DSILINK_RXRSS2R_RXAKE_Pos             (30UL)         /*!< RXAKE (Bit 30)                                        */
41457  #define R_DSILINK_RXRSS2R_RXAKE_Msk             (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41458  #define R_DSILINK_RXRSS2R_INFOOW_Pos            (31UL)         /*!< INFOOW (Bit 31)                                       */
41459  #define R_DSILINK_RXRSS2R_INFOOW_Msk            (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41460 /* ========================================================  RXRSS3R  ======================================================== */
41461  #define R_DSILINK_RXRSS3R_DATA0_Pos             (0UL)          /*!< DATA0 (Bit 0)                                         */
41462  #define R_DSILINK_RXRSS3R_DATA0_Msk             (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41463  #define R_DSILINK_RXRSS3R_DATA1_Pos             (8UL)          /*!< DATA1 (Bit 8)                                         */
41464  #define R_DSILINK_RXRSS3R_DATA1_Msk             (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41465  #define R_DSILINK_RXRSS3R_DT_Pos                (16UL)         /*!< DT (Bit 16)                                           */
41466  #define R_DSILINK_RXRSS3R_DT_Msk                (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
41467  #define R_DSILINK_RXRSS3R_VC_Pos                (22UL)         /*!< VC (Bit 22)                                           */
41468  #define R_DSILINK_RXRSS3R_VC_Msk                (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
41469  #define R_DSILINK_RXRSS3R_FMT_Pos               (24UL)         /*!< FMT (Bit 24)                                          */
41470  #define R_DSILINK_RXRSS3R_FMT_Msk               (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
41471  #define R_DSILINK_RXRSS3R_RXSUC_Pos             (25UL)         /*!< RXSUC (Bit 25)                                        */
41472  #define R_DSILINK_RXRSS3R_RXSUC_Msk             (0x2000000UL)  /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41473  #define R_DSILINK_RXRSS3R_RXFERR_Pos            (26UL)         /*!< RXFERR (Bit 26)                                       */
41474  #define R_DSILINK_RXRSS3R_RXFERR_Msk            (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41475  #define R_DSILINK_RXRSS3R_RXFAIL_Pos            (27UL)         /*!< RXFAIL (Bit 27)                                       */
41476  #define R_DSILINK_RXRSS3R_RXFAIL_Msk            (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41477  #define R_DSILINK_RXRSS3R_RXPFAIL_Pos           (28UL)         /*!< RXPFAIL (Bit 28)                                      */
41478  #define R_DSILINK_RXRSS3R_RXPFAIL_Msk           (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41479  #define R_DSILINK_RXRSS3R_RXCERR_Pos            (29UL)         /*!< RXCERR (Bit 29)                                       */
41480  #define R_DSILINK_RXRSS3R_RXCERR_Msk            (0x20000000UL) /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41481  #define R_DSILINK_RXRSS3R_RXAKE_Pos             (30UL)         /*!< RXAKE (Bit 30)                                        */
41482  #define R_DSILINK_RXRSS3R_RXAKE_Msk             (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41483  #define R_DSILINK_RXRSS3R_INFOOW_Pos            (31UL)         /*!< INFOOW (Bit 31)                                       */
41484  #define R_DSILINK_RXRSS3R_INFOOW_Msk            (0x80000000UL) /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41485 /* =======================================================  RXRSS0R_L  ======================================================= */
41486  #define R_DSILINK_RXRSS0R_L_DATA0_Pos           (0UL)          /*!< DATA0 (Bit 0)                                         */
41487  #define R_DSILINK_RXRSS0R_L_DATA0_Msk           (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41488  #define R_DSILINK_RXRSS0R_L_DATA1_Pos           (8UL)          /*!< DATA1 (Bit 8)                                         */
41489  #define R_DSILINK_RXRSS0R_L_DATA1_Msk           (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41490 /* =======================================================  RXRSS1R_L  ======================================================= */
41491  #define R_DSILINK_RXRSS1R_L_DATA0_Pos           (0UL)          /*!< DATA0 (Bit 0)                                         */
41492  #define R_DSILINK_RXRSS1R_L_DATA0_Msk           (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41493  #define R_DSILINK_RXRSS1R_L_DATA1_Pos           (8UL)          /*!< DATA1 (Bit 8)                                         */
41494  #define R_DSILINK_RXRSS1R_L_DATA1_Msk           (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41495 /* =======================================================  RXRSS2R_L  ======================================================= */
41496  #define R_DSILINK_RXRSS2R_L_DATA0_Pos           (0UL)          /*!< DATA0 (Bit 0)                                         */
41497  #define R_DSILINK_RXRSS2R_L_DATA0_Msk           (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41498  #define R_DSILINK_RXRSS2R_L_DATA1_Pos           (8UL)          /*!< DATA1 (Bit 8)                                         */
41499  #define R_DSILINK_RXRSS2R_L_DATA1_Msk           (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41500 /* =======================================================  RXRSS3R_L  ======================================================= */
41501  #define R_DSILINK_RXRSS3R_L_DATA0_Pos           (0UL)          /*!< DATA0 (Bit 0)                                         */
41502  #define R_DSILINK_RXRSS3R_L_DATA0_Msk           (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41503  #define R_DSILINK_RXRSS3R_L_DATA1_Pos           (8UL)          /*!< DATA1 (Bit 8)                                         */
41504  #define R_DSILINK_RXRSS3R_L_DATA1_Msk           (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41505 /* ======================================================  RXRSS0R_LL  ======================================================= */
41506  #define R_DSILINK_RXRSS0R_LL_DATA0_Pos          (0UL)          /*!< DATA0 (Bit 0)                                         */
41507  #define R_DSILINK_RXRSS0R_LL_DATA0_Msk          (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41508 /* ======================================================  RXRSS1R_LL  ======================================================= */
41509  #define R_DSILINK_RXRSS1R_LL_DATA0_Pos          (0UL)          /*!< DATA0 (Bit 0)                                         */
41510  #define R_DSILINK_RXRSS1R_LL_DATA0_Msk          (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41511 /* ======================================================  RXRSS2R_LL  ======================================================= */
41512  #define R_DSILINK_RXRSS2R_LL_DATA0_Pos          (0UL)          /*!< DATA0 (Bit 0)                                         */
41513  #define R_DSILINK_RXRSS2R_LL_DATA0_Msk          (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41514 /* ======================================================  RXRSS3R_LL  ======================================================= */
41515  #define R_DSILINK_RXRSS3R_LL_DATA0_Pos          (0UL)          /*!< DATA0 (Bit 0)                                         */
41516  #define R_DSILINK_RXRSS3R_LL_DATA0_Msk          (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41517 /* ======================================================  RXRSS0R_LH  ======================================================= */
41518  #define R_DSILINK_RXRSS0R_LH_DATA1_Pos          (0UL)          /*!< DATA1 (Bit 0)                                         */
41519  #define R_DSILINK_RXRSS0R_LH_DATA1_Msk          (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41520 /* ======================================================  RXRSS1R_LH  ======================================================= */
41521  #define R_DSILINK_RXRSS1R_LH_DATA1_Pos          (0UL)          /*!< DATA1 (Bit 0)                                         */
41522  #define R_DSILINK_RXRSS1R_LH_DATA1_Msk          (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41523 /* ======================================================  RXRSS2R_LH  ======================================================= */
41524  #define R_DSILINK_RXRSS2R_LH_DATA1_Pos          (0UL)          /*!< DATA1 (Bit 0)                                         */
41525  #define R_DSILINK_RXRSS2R_LH_DATA1_Msk          (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41526 /* ======================================================  RXRSS3R_LH  ======================================================= */
41527  #define R_DSILINK_RXRSS3R_LH_DATA1_Pos          (0UL)          /*!< DATA1 (Bit 0)                                         */
41528  #define R_DSILINK_RXRSS3R_LH_DATA1_Msk          (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41529 /* =======================================================  RXRSS0R_H  ======================================================= */
41530  #define R_DSILINK_RXRSS0R_H_DT_Pos              (0UL)          /*!< DT (Bit 0)                                            */
41531  #define R_DSILINK_RXRSS0R_H_DT_Msk              (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
41532  #define R_DSILINK_RXRSS0R_H_VC_Pos              (6UL)          /*!< VC (Bit 6)                                            */
41533  #define R_DSILINK_RXRSS0R_H_VC_Msk              (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
41534  #define R_DSILINK_RXRSS0R_H_FMT_Pos             (8UL)          /*!< FMT (Bit 8)                                           */
41535  #define R_DSILINK_RXRSS0R_H_FMT_Msk             (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
41536  #define R_DSILINK_RXRSS0R_H_RXSUC_Pos           (9UL)          /*!< RXSUC (Bit 9)                                         */
41537  #define R_DSILINK_RXRSS0R_H_RXSUC_Msk           (0x200UL)      /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41538  #define R_DSILINK_RXRSS0R_H_RXFERR_Pos          (10UL)         /*!< RXFERR (Bit 10)                                       */
41539  #define R_DSILINK_RXRSS0R_H_RXFERR_Msk          (0x400UL)      /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41540  #define R_DSILINK_RXRSS0R_H_RXFAIL_Pos          (11UL)         /*!< RXFAIL (Bit 11)                                       */
41541  #define R_DSILINK_RXRSS0R_H_RXFAIL_Msk          (0x800UL)      /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41542  #define R_DSILINK_RXRSS0R_H_RXPFAIL_Pos         (12UL)         /*!< RXPFAIL (Bit 12)                                      */
41543  #define R_DSILINK_RXRSS0R_H_RXPFAIL_Msk         (0x1000UL)     /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41544  #define R_DSILINK_RXRSS0R_H_RXCERR_Pos          (13UL)         /*!< RXCERR (Bit 13)                                       */
41545  #define R_DSILINK_RXRSS0R_H_RXCERR_Msk          (0x2000UL)     /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41546  #define R_DSILINK_RXRSS0R_H_RXAKE_Pos           (14UL)         /*!< RXAKE (Bit 14)                                        */
41547  #define R_DSILINK_RXRSS0R_H_RXAKE_Msk           (0x4000UL)     /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41548  #define R_DSILINK_RXRSS0R_H_INFOOW_Pos          (15UL)         /*!< INFOOW (Bit 15)                                       */
41549  #define R_DSILINK_RXRSS0R_H_INFOOW_Msk          (0x8000UL)     /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41550 /* =======================================================  RXRSS1R_H  ======================================================= */
41551  #define R_DSILINK_RXRSS1R_H_DT_Pos              (0UL)          /*!< DT (Bit 0)                                            */
41552  #define R_DSILINK_RXRSS1R_H_DT_Msk              (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
41553  #define R_DSILINK_RXRSS1R_H_VC_Pos              (6UL)          /*!< VC (Bit 6)                                            */
41554  #define R_DSILINK_RXRSS1R_H_VC_Msk              (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
41555  #define R_DSILINK_RXRSS1R_H_FMT_Pos             (8UL)          /*!< FMT (Bit 8)                                           */
41556  #define R_DSILINK_RXRSS1R_H_FMT_Msk             (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
41557  #define R_DSILINK_RXRSS1R_H_RXSUC_Pos           (9UL)          /*!< RXSUC (Bit 9)                                         */
41558  #define R_DSILINK_RXRSS1R_H_RXSUC_Msk           (0x200UL)      /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41559  #define R_DSILINK_RXRSS1R_H_RXFERR_Pos          (10UL)         /*!< RXFERR (Bit 10)                                       */
41560  #define R_DSILINK_RXRSS1R_H_RXFERR_Msk          (0x400UL)      /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41561  #define R_DSILINK_RXRSS1R_H_RXFAIL_Pos          (11UL)         /*!< RXFAIL (Bit 11)                                       */
41562  #define R_DSILINK_RXRSS1R_H_RXFAIL_Msk          (0x800UL)      /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41563  #define R_DSILINK_RXRSS1R_H_RXPFAIL_Pos         (12UL)         /*!< RXPFAIL (Bit 12)                                      */
41564  #define R_DSILINK_RXRSS1R_H_RXPFAIL_Msk         (0x1000UL)     /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41565  #define R_DSILINK_RXRSS1R_H_RXCERR_Pos          (13UL)         /*!< RXCERR (Bit 13)                                       */
41566  #define R_DSILINK_RXRSS1R_H_RXCERR_Msk          (0x2000UL)     /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41567  #define R_DSILINK_RXRSS1R_H_RXAKE_Pos           (14UL)         /*!< RXAKE (Bit 14)                                        */
41568  #define R_DSILINK_RXRSS1R_H_RXAKE_Msk           (0x4000UL)     /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41569  #define R_DSILINK_RXRSS1R_H_INFOOW_Pos          (15UL)         /*!< INFOOW (Bit 15)                                       */
41570  #define R_DSILINK_RXRSS1R_H_INFOOW_Msk          (0x8000UL)     /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41571 /* =======================================================  RXRSS2R_H  ======================================================= */
41572  #define R_DSILINK_RXRSS2R_H_DT_Pos              (0UL)          /*!< DT (Bit 0)                                            */
41573  #define R_DSILINK_RXRSS2R_H_DT_Msk              (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
41574  #define R_DSILINK_RXRSS2R_H_VC_Pos              (6UL)          /*!< VC (Bit 6)                                            */
41575  #define R_DSILINK_RXRSS2R_H_VC_Msk              (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
41576  #define R_DSILINK_RXRSS2R_H_FMT_Pos             (8UL)          /*!< FMT (Bit 8)                                           */
41577  #define R_DSILINK_RXRSS2R_H_FMT_Msk             (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
41578  #define R_DSILINK_RXRSS2R_H_RXSUC_Pos           (9UL)          /*!< RXSUC (Bit 9)                                         */
41579  #define R_DSILINK_RXRSS2R_H_RXSUC_Msk           (0x200UL)      /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41580  #define R_DSILINK_RXRSS2R_H_RXFERR_Pos          (10UL)         /*!< RXFERR (Bit 10)                                       */
41581  #define R_DSILINK_RXRSS2R_H_RXFERR_Msk          (0x400UL)      /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41582  #define R_DSILINK_RXRSS2R_H_RXFAIL_Pos          (11UL)         /*!< RXFAIL (Bit 11)                                       */
41583  #define R_DSILINK_RXRSS2R_H_RXFAIL_Msk          (0x800UL)      /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41584  #define R_DSILINK_RXRSS2R_H_RXPFAIL_Pos         (12UL)         /*!< RXPFAIL (Bit 12)                                      */
41585  #define R_DSILINK_RXRSS2R_H_RXPFAIL_Msk         (0x1000UL)     /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41586  #define R_DSILINK_RXRSS2R_H_RXCERR_Pos          (13UL)         /*!< RXCERR (Bit 13)                                       */
41587  #define R_DSILINK_RXRSS2R_H_RXCERR_Msk          (0x2000UL)     /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41588  #define R_DSILINK_RXRSS2R_H_RXAKE_Pos           (14UL)         /*!< RXAKE (Bit 14)                                        */
41589  #define R_DSILINK_RXRSS2R_H_RXAKE_Msk           (0x4000UL)     /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41590  #define R_DSILINK_RXRSS2R_H_INFOOW_Pos          (15UL)         /*!< INFOOW (Bit 15)                                       */
41591  #define R_DSILINK_RXRSS2R_H_INFOOW_Msk          (0x8000UL)     /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41592 /* =======================================================  RXRSS3R_H  ======================================================= */
41593  #define R_DSILINK_RXRSS3R_H_DT_Pos              (0UL)          /*!< DT (Bit 0)                                            */
41594  #define R_DSILINK_RXRSS3R_H_DT_Msk              (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
41595  #define R_DSILINK_RXRSS3R_H_VC_Pos              (6UL)          /*!< VC (Bit 6)                                            */
41596  #define R_DSILINK_RXRSS3R_H_VC_Msk              (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
41597  #define R_DSILINK_RXRSS3R_H_FMT_Pos             (8UL)          /*!< FMT (Bit 8)                                           */
41598  #define R_DSILINK_RXRSS3R_H_FMT_Msk             (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
41599  #define R_DSILINK_RXRSS3R_H_RXSUC_Pos           (9UL)          /*!< RXSUC (Bit 9)                                         */
41600  #define R_DSILINK_RXRSS3R_H_RXSUC_Msk           (0x200UL)      /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41601  #define R_DSILINK_RXRSS3R_H_RXFERR_Pos          (10UL)         /*!< RXFERR (Bit 10)                                       */
41602  #define R_DSILINK_RXRSS3R_H_RXFERR_Msk          (0x400UL)      /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41603  #define R_DSILINK_RXRSS3R_H_RXFAIL_Pos          (11UL)         /*!< RXFAIL (Bit 11)                                       */
41604  #define R_DSILINK_RXRSS3R_H_RXFAIL_Msk          (0x800UL)      /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41605  #define R_DSILINK_RXRSS3R_H_RXPFAIL_Pos         (12UL)         /*!< RXPFAIL (Bit 12)                                      */
41606  #define R_DSILINK_RXRSS3R_H_RXPFAIL_Msk         (0x1000UL)     /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41607  #define R_DSILINK_RXRSS3R_H_RXCERR_Pos          (13UL)         /*!< RXCERR (Bit 13)                                       */
41608  #define R_DSILINK_RXRSS3R_H_RXCERR_Msk          (0x2000UL)     /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41609  #define R_DSILINK_RXRSS3R_H_RXAKE_Pos           (14UL)         /*!< RXAKE (Bit 14)                                        */
41610  #define R_DSILINK_RXRSS3R_H_RXAKE_Msk           (0x4000UL)     /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41611  #define R_DSILINK_RXRSS3R_H_INFOOW_Pos          (15UL)         /*!< INFOOW (Bit 15)                                       */
41612  #define R_DSILINK_RXRSS3R_H_INFOOW_Msk          (0x8000UL)     /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41613 /* ======================================================  RXRSS0R_HL  ======================================================= */
41614  #define R_DSILINK_RXRSS0R_HL_DT_Pos             (0UL)          /*!< DT (Bit 0)                                            */
41615  #define R_DSILINK_RXRSS0R_HL_DT_Msk             (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
41616  #define R_DSILINK_RXRSS0R_HL_VC_Pos             (6UL)          /*!< VC (Bit 6)                                            */
41617  #define R_DSILINK_RXRSS0R_HL_VC_Msk             (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
41618 /* ======================================================  RXRSS1R_HL  ======================================================= */
41619  #define R_DSILINK_RXRSS1R_HL_DT_Pos             (0UL)          /*!< DT (Bit 0)                                            */
41620  #define R_DSILINK_RXRSS1R_HL_DT_Msk             (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
41621  #define R_DSILINK_RXRSS1R_HL_VC_Pos             (6UL)          /*!< VC (Bit 6)                                            */
41622  #define R_DSILINK_RXRSS1R_HL_VC_Msk             (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
41623 /* ======================================================  RXRSS2R_HL  ======================================================= */
41624  #define R_DSILINK_RXRSS2R_HL_DT_Pos             (0UL)          /*!< DT (Bit 0)                                            */
41625  #define R_DSILINK_RXRSS2R_HL_DT_Msk             (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
41626  #define R_DSILINK_RXRSS2R_HL_VC_Pos             (6UL)          /*!< VC (Bit 6)                                            */
41627  #define R_DSILINK_RXRSS2R_HL_VC_Msk             (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
41628 /* ======================================================  RXRSS3R_HL  ======================================================= */
41629  #define R_DSILINK_RXRSS3R_HL_DT_Pos             (0UL)          /*!< DT (Bit 0)                                            */
41630  #define R_DSILINK_RXRSS3R_HL_DT_Msk             (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
41631  #define R_DSILINK_RXRSS3R_HL_VC_Pos             (6UL)          /*!< VC (Bit 6)                                            */
41632  #define R_DSILINK_RXRSS3R_HL_VC_Msk             (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
41633 /* ======================================================  RXRSS0R_HH  ======================================================= */
41634  #define R_DSILINK_RXRSS0R_HH_FMT_Pos            (0UL)          /*!< FMT (Bit 0)                                           */
41635  #define R_DSILINK_RXRSS0R_HH_FMT_Msk            (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
41636  #define R_DSILINK_RXRSS0R_HH_RXSUC_Pos          (1UL)          /*!< RXSUC (Bit 1)                                         */
41637  #define R_DSILINK_RXRSS0R_HH_RXSUC_Msk          (0x2UL)        /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41638  #define R_DSILINK_RXRSS0R_HH_RXFERR_Pos         (2UL)          /*!< RXFERR (Bit 2)                                        */
41639  #define R_DSILINK_RXRSS0R_HH_RXFERR_Msk         (0x4UL)        /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41640  #define R_DSILINK_RXRSS0R_HH_RXFAIL_Pos         (3UL)          /*!< RXFAIL (Bit 3)                                        */
41641  #define R_DSILINK_RXRSS0R_HH_RXFAIL_Msk         (0x8UL)        /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41642  #define R_DSILINK_RXRSS0R_HH_RXPFAIL_Pos        (4UL)          /*!< RXPFAIL (Bit 4)                                       */
41643  #define R_DSILINK_RXRSS0R_HH_RXPFAIL_Msk        (0x10UL)       /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41644  #define R_DSILINK_RXRSS0R_HH_RXCERR_Pos         (5UL)          /*!< RXCERR (Bit 5)                                        */
41645  #define R_DSILINK_RXRSS0R_HH_RXCERR_Msk         (0x20UL)       /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41646  #define R_DSILINK_RXRSS0R_HH_RXAKE_Pos          (6UL)          /*!< RXAKE (Bit 6)                                         */
41647  #define R_DSILINK_RXRSS0R_HH_RXAKE_Msk          (0x40UL)       /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41648  #define R_DSILINK_RXRSS0R_HH_INFOOW_Pos         (7UL)          /*!< INFOOW (Bit 7)                                        */
41649  #define R_DSILINK_RXRSS0R_HH_INFOOW_Msk         (0x80UL)       /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41650 /* ======================================================  RXRSS1R_HH  ======================================================= */
41651  #define R_DSILINK_RXRSS1R_HH_FMT_Pos            (0UL)          /*!< FMT (Bit 0)                                           */
41652  #define R_DSILINK_RXRSS1R_HH_FMT_Msk            (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
41653  #define R_DSILINK_RXRSS1R_HH_RXSUC_Pos          (1UL)          /*!< RXSUC (Bit 1)                                         */
41654  #define R_DSILINK_RXRSS1R_HH_RXSUC_Msk          (0x2UL)        /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41655  #define R_DSILINK_RXRSS1R_HH_RXFERR_Pos         (2UL)          /*!< RXFERR (Bit 2)                                        */
41656  #define R_DSILINK_RXRSS1R_HH_RXFERR_Msk         (0x4UL)        /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41657  #define R_DSILINK_RXRSS1R_HH_RXFAIL_Pos         (3UL)          /*!< RXFAIL (Bit 3)                                        */
41658  #define R_DSILINK_RXRSS1R_HH_RXFAIL_Msk         (0x8UL)        /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41659  #define R_DSILINK_RXRSS1R_HH_RXPFAIL_Pos        (4UL)          /*!< RXPFAIL (Bit 4)                                       */
41660  #define R_DSILINK_RXRSS1R_HH_RXPFAIL_Msk        (0x10UL)       /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41661  #define R_DSILINK_RXRSS1R_HH_RXCERR_Pos         (5UL)          /*!< RXCERR (Bit 5)                                        */
41662  #define R_DSILINK_RXRSS1R_HH_RXCERR_Msk         (0x20UL)       /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41663  #define R_DSILINK_RXRSS1R_HH_RXAKE_Pos          (6UL)          /*!< RXAKE (Bit 6)                                         */
41664  #define R_DSILINK_RXRSS1R_HH_RXAKE_Msk          (0x40UL)       /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41665  #define R_DSILINK_RXRSS1R_HH_INFOOW_Pos         (7UL)          /*!< INFOOW (Bit 7)                                        */
41666  #define R_DSILINK_RXRSS1R_HH_INFOOW_Msk         (0x80UL)       /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41667 /* ======================================================  RXRSS2R_HH  ======================================================= */
41668  #define R_DSILINK_RXRSS2R_HH_FMT_Pos            (0UL)          /*!< FMT (Bit 0)                                           */
41669  #define R_DSILINK_RXRSS2R_HH_FMT_Msk            (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
41670  #define R_DSILINK_RXRSS2R_HH_RXSUC_Pos          (1UL)          /*!< RXSUC (Bit 1)                                         */
41671  #define R_DSILINK_RXRSS2R_HH_RXSUC_Msk          (0x2UL)        /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41672  #define R_DSILINK_RXRSS2R_HH_RXFERR_Pos         (2UL)          /*!< RXFERR (Bit 2)                                        */
41673  #define R_DSILINK_RXRSS2R_HH_RXFERR_Msk         (0x4UL)        /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41674  #define R_DSILINK_RXRSS2R_HH_RXFAIL_Pos         (3UL)          /*!< RXFAIL (Bit 3)                                        */
41675  #define R_DSILINK_RXRSS2R_HH_RXFAIL_Msk         (0x8UL)        /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41676  #define R_DSILINK_RXRSS2R_HH_RXPFAIL_Pos        (4UL)          /*!< RXPFAIL (Bit 4)                                       */
41677  #define R_DSILINK_RXRSS2R_HH_RXPFAIL_Msk        (0x10UL)       /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41678  #define R_DSILINK_RXRSS2R_HH_RXCERR_Pos         (5UL)          /*!< RXCERR (Bit 5)                                        */
41679  #define R_DSILINK_RXRSS2R_HH_RXCERR_Msk         (0x20UL)       /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41680  #define R_DSILINK_RXRSS2R_HH_RXAKE_Pos          (6UL)          /*!< RXAKE (Bit 6)                                         */
41681  #define R_DSILINK_RXRSS2R_HH_RXAKE_Msk          (0x40UL)       /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41682  #define R_DSILINK_RXRSS2R_HH_INFOOW_Pos         (7UL)          /*!< INFOOW (Bit 7)                                        */
41683  #define R_DSILINK_RXRSS2R_HH_INFOOW_Msk         (0x80UL)       /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41684 /* ======================================================  RXRSS3R_HH  ======================================================= */
41685  #define R_DSILINK_RXRSS3R_HH_FMT_Pos            (0UL)          /*!< FMT (Bit 0)                                           */
41686  #define R_DSILINK_RXRSS3R_HH_FMT_Msk            (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
41687  #define R_DSILINK_RXRSS3R_HH_RXSUC_Pos          (1UL)          /*!< RXSUC (Bit 1)                                         */
41688  #define R_DSILINK_RXRSS3R_HH_RXSUC_Msk          (0x2UL)        /*!< RXSUC (Bitfield-Mask: 0x01)                           */
41689  #define R_DSILINK_RXRSS3R_HH_RXFERR_Pos         (2UL)          /*!< RXFERR (Bit 2)                                        */
41690  #define R_DSILINK_RXRSS3R_HH_RXFERR_Msk         (0x4UL)        /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41691  #define R_DSILINK_RXRSS3R_HH_RXFAIL_Pos         (3UL)          /*!< RXFAIL (Bit 3)                                        */
41692  #define R_DSILINK_RXRSS3R_HH_RXFAIL_Msk         (0x8UL)        /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41693  #define R_DSILINK_RXRSS3R_HH_RXPFAIL_Pos        (4UL)          /*!< RXPFAIL (Bit 4)                                       */
41694  #define R_DSILINK_RXRSS3R_HH_RXPFAIL_Msk        (0x10UL)       /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41695  #define R_DSILINK_RXRSS3R_HH_RXCERR_Pos         (5UL)          /*!< RXCERR (Bit 5)                                        */
41696  #define R_DSILINK_RXRSS3R_HH_RXCERR_Msk         (0x20UL)       /*!< RXCERR (Bitfield-Mask: 0x01)                          */
41697  #define R_DSILINK_RXRSS3R_HH_RXAKE_Pos          (6UL)          /*!< RXAKE (Bit 6)                                         */
41698  #define R_DSILINK_RXRSS3R_HH_RXAKE_Msk          (0x40UL)       /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41699  #define R_DSILINK_RXRSS3R_HH_INFOOW_Pos         (7UL)          /*!< INFOOW (Bit 7)                                        */
41700  #define R_DSILINK_RXRSS3R_HH_INFOOW_Msk         (0x80UL)       /*!< INFOOW (Bitfield-Mask: 0x01)                          */
41701 /* ========================================================  RXPPD0R  ======================================================== */
41702  #define R_DSILINK_RXPPD0R_DATA0_Pos             (0UL)          /*!< DATA0 (Bit 0)                                         */
41703  #define R_DSILINK_RXPPD0R_DATA0_Msk             (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
41704  #define R_DSILINK_RXPPD0R_DATA1_Pos             (8UL)          /*!< DATA1 (Bit 8)                                         */
41705  #define R_DSILINK_RXPPD0R_DATA1_Msk             (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
41706  #define R_DSILINK_RXPPD0R_DATA2_Pos             (16UL)         /*!< DATA2 (Bit 16)                                        */
41707  #define R_DSILINK_RXPPD0R_DATA2_Msk             (0xff0000UL)   /*!< DATA2 (Bitfield-Mask: 0xff)                           */
41708  #define R_DSILINK_RXPPD0R_DATA3_Pos             (24UL)         /*!< DATA3 (Bit 24)                                        */
41709  #define R_DSILINK_RXPPD0R_DATA3_Msk             (0xff000000UL) /*!< DATA3 (Bitfield-Mask: 0xff)                           */
41710 /* ========================================================  RXPPD1R  ======================================================== */
41711  #define R_DSILINK_RXPPD1R_DATA4_Pos             (0UL)          /*!< DATA4 (Bit 0)                                         */
41712  #define R_DSILINK_RXPPD1R_DATA4_Msk             (0xffUL)       /*!< DATA4 (Bitfield-Mask: 0xff)                           */
41713  #define R_DSILINK_RXPPD1R_DATA5_Pos             (8UL)          /*!< DATA5 (Bit 8)                                         */
41714  #define R_DSILINK_RXPPD1R_DATA5_Msk             (0xff00UL)     /*!< DATA5 (Bitfield-Mask: 0xff)                           */
41715  #define R_DSILINK_RXPPD1R_DATA6_Pos             (16UL)         /*!< DATA6 (Bit 16)                                        */
41716  #define R_DSILINK_RXPPD1R_DATA6_Msk             (0xff0000UL)   /*!< DATA6 (Bitfield-Mask: 0xff)                           */
41717  #define R_DSILINK_RXPPD1R_DATA7_Pos             (24UL)         /*!< DATA7 (Bit 24)                                        */
41718  #define R_DSILINK_RXPPD1R_DATA7_Msk             (0xff000000UL) /*!< DATA7 (Bitfield-Mask: 0xff)                           */
41719 /* ========================================================  RXPPD2R  ======================================================== */
41720  #define R_DSILINK_RXPPD2R_DATA8_Pos             (0UL)          /*!< DATA8 (Bit 0)                                         */
41721  #define R_DSILINK_RXPPD2R_DATA8_Msk             (0xffUL)       /*!< DATA8 (Bitfield-Mask: 0xff)                           */
41722  #define R_DSILINK_RXPPD2R_DATA9_Pos             (8UL)          /*!< DATA9 (Bit 8)                                         */
41723  #define R_DSILINK_RXPPD2R_DATA9_Msk             (0xff00UL)     /*!< DATA9 (Bitfield-Mask: 0xff)                           */
41724  #define R_DSILINK_RXPPD2R_DATA10_Pos            (16UL)         /*!< DATA10 (Bit 16)                                       */
41725  #define R_DSILINK_RXPPD2R_DATA10_Msk            (0xff0000UL)   /*!< DATA10 (Bitfield-Mask: 0xff)                          */
41726  #define R_DSILINK_RXPPD2R_DATA11_Pos            (24UL)         /*!< DATA11 (Bit 24)                                       */
41727  #define R_DSILINK_RXPPD2R_DATA11_Msk            (0xff000000UL) /*!< DATA11 (Bitfield-Mask: 0xff)                          */
41728 /* ========================================================  RXPPD3R  ======================================================== */
41729  #define R_DSILINK_RXPPD3R_DATA12_Pos            (0UL)          /*!< DATA12 (Bit 0)                                        */
41730  #define R_DSILINK_RXPPD3R_DATA12_Msk            (0xffUL)       /*!< DATA12 (Bitfield-Mask: 0xff)                          */
41731  #define R_DSILINK_RXPPD3R_DATA13_Pos            (8UL)          /*!< DATA13 (Bit 8)                                        */
41732  #define R_DSILINK_RXPPD3R_DATA13_Msk            (0xff00UL)     /*!< DATA13 (Bitfield-Mask: 0xff)                          */
41733  #define R_DSILINK_RXPPD3R_DATA14_Pos            (16UL)         /*!< DATA14 (Bit 16)                                       */
41734  #define R_DSILINK_RXPPD3R_DATA14_Msk            (0xff0000UL)   /*!< DATA14 (Bitfield-Mask: 0xff)                          */
41735  #define R_DSILINK_RXPPD3R_DATA15_Pos            (24UL)         /*!< DATA15 (Bit 24)                                       */
41736  #define R_DSILINK_RXPPD3R_DATA15_Msk            (0xff000000UL) /*!< DATA15 (Bitfield-Mask: 0xff)                          */
41737 /* ======================================================  HSTXTOSETR  ======================================================= */
41738  #define R_DSILINK_HSTXTOSETR_HTXTO_Pos          (0UL)          /*!< HTXTO (Bit 0)                                         */
41739  #define R_DSILINK_HSTXTOSETR_HTXTO_Msk          (0xffffffffUL) /*!< HTXTO (Bitfield-Mask: 0xffffffff)                     */
41740 /* ======================================================  LRXHTOSETR  ======================================================= */
41741  #define R_DSILINK_LRXHTOSETR_LRXHTO_Pos         (0UL)          /*!< LRXHTO (Bit 0)                                        */
41742  #define R_DSILINK_LRXHTOSETR_LRXHTO_Msk         (0xffffffffUL) /*!< LRXHTO (Bitfield-Mask: 0xffffffff)                    */
41743 /* =======================================================  TATOSETR  ======================================================== */
41744  #define R_DSILINK_TATOSETR_TATO_Pos             (0UL)          /*!< TATO (Bit 0)                                          */
41745  #define R_DSILINK_TATOSETR_TATO_Msk             (0xffffffffUL) /*!< TATO (Bitfield-Mask: 0xffffffff)                      */
41746 /* ========================================================  FERRSR  ========================================================= */
41747  #define R_DSILINK_FERRSR_HTXTO_Pos              (0UL)          /*!< HTXTO (Bit 0)                                         */
41748  #define R_DSILINK_FERRSR_HTXTO_Msk              (0x1UL)        /*!< HTXTO (Bitfield-Mask: 0x01)                           */
41749  #define R_DSILINK_FERRSR_LRXHTO_Pos             (1UL)          /*!< LRXHTO (Bit 1)                                        */
41750  #define R_DSILINK_FERRSR_LRXHTO_Msk             (0x2UL)        /*!< LRXHTO (Bitfield-Mask: 0x01)                          */
41751  #define R_DSILINK_FERRSR_TATO_Pos               (2UL)          /*!< TATO (Bit 2)                                          */
41752  #define R_DSILINK_FERRSR_TATO_Msk               (0x4UL)        /*!< TATO (Bitfield-Mask: 0x01)                            */
41753  #define R_DSILINK_FERRSR_ESCENT_Pos             (16UL)         /*!< ESCENT (Bit 16)                                       */
41754  #define R_DSILINK_FERRSR_ESCENT_Msk             (0x10000UL)    /*!< ESCENT (Bitfield-Mask: 0x01)                          */
41755  #define R_DSILINK_FERRSR_SYNCESC_Pos            (17UL)         /*!< SYNCESC (Bit 17)                                      */
41756  #define R_DSILINK_FERRSR_SYNCESC_Msk            (0x20000UL)    /*!< SYNCESC (Bitfield-Mask: 0x01)                         */
41757  #define R_DSILINK_FERRSR_CTRL_Pos               (18UL)         /*!< CTRL (Bit 18)                                         */
41758  #define R_DSILINK_FERRSR_CTRL_Msk               (0x40000UL)    /*!< CTRL (Bitfield-Mask: 0x01)                            */
41759  #define R_DSILINK_FERRSR_CLP0_Pos               (19UL)         /*!< CLP0 (Bit 19)                                         */
41760  #define R_DSILINK_FERRSR_CLP0_Msk               (0x80000UL)    /*!< CLP0 (Bitfield-Mask: 0x01)                            */
41761  #define R_DSILINK_FERRSR_CLP1_Pos               (20UL)         /*!< CLP1 (Bit 20)                                         */
41762  #define R_DSILINK_FERRSR_CLP1_Msk               (0x100000UL)   /*!< CLP1 (Bitfield-Mask: 0x01)                            */
41763  #define R_DSILINK_FERRSR_CLP0S_Pos              (27UL)         /*!< CLP0S (Bit 27)                                        */
41764  #define R_DSILINK_FERRSR_CLP0S_Msk              (0x8000000UL)  /*!< CLP0S (Bitfield-Mask: 0x01)                           */
41765  #define R_DSILINK_FERRSR_CLP1S_Pos              (28UL)         /*!< CLP1S (Bit 28)                                        */
41766  #define R_DSILINK_FERRSR_CLP1S_Msk              (0x10000000UL) /*!< CLP1S (Bitfield-Mask: 0x01)                           */
41767 /* ========================================================  FERRSCR  ======================================================== */
41768  #define R_DSILINK_FERRSCR_HTXTO_Pos             (0UL)          /*!< HTXTO (Bit 0)                                         */
41769  #define R_DSILINK_FERRSCR_HTXTO_Msk             (0x1UL)        /*!< HTXTO (Bitfield-Mask: 0x01)                           */
41770  #define R_DSILINK_FERRSCR_LRXHTO_Pos            (1UL)          /*!< LRXHTO (Bit 1)                                        */
41771  #define R_DSILINK_FERRSCR_LRXHTO_Msk            (0x2UL)        /*!< LRXHTO (Bitfield-Mask: 0x01)                          */
41772  #define R_DSILINK_FERRSCR_TATO_Pos              (2UL)          /*!< TATO (Bit 2)                                          */
41773  #define R_DSILINK_FERRSCR_TATO_Msk              (0x4UL)        /*!< TATO (Bitfield-Mask: 0x01)                            */
41774  #define R_DSILINK_FERRSCR_ESCENT_Pos            (16UL)         /*!< ESCENT (Bit 16)                                       */
41775  #define R_DSILINK_FERRSCR_ESCENT_Msk            (0x10000UL)    /*!< ESCENT (Bitfield-Mask: 0x01)                          */
41776  #define R_DSILINK_FERRSCR_SYNCESC_Pos           (17UL)         /*!< SYNCESC (Bit 17)                                      */
41777  #define R_DSILINK_FERRSCR_SYNCESC_Msk           (0x20000UL)    /*!< SYNCESC (Bitfield-Mask: 0x01)                         */
41778  #define R_DSILINK_FERRSCR_CTRL_Pos              (18UL)         /*!< CTRL (Bit 18)                                         */
41779  #define R_DSILINK_FERRSCR_CTRL_Msk              (0x40000UL)    /*!< CTRL (Bitfield-Mask: 0x01)                            */
41780  #define R_DSILINK_FERRSCR_CLP0_Pos              (19UL)         /*!< CLP0 (Bit 19)                                         */
41781  #define R_DSILINK_FERRSCR_CLP0_Msk              (0x80000UL)    /*!< CLP0 (Bitfield-Mask: 0x01)                            */
41782  #define R_DSILINK_FERRSCR_CLP1_Pos              (20UL)         /*!< CLP1 (Bit 20)                                         */
41783  #define R_DSILINK_FERRSCR_CLP1_Msk              (0x100000UL)   /*!< CLP1 (Bitfield-Mask: 0x01)                            */
41784 /* ========================================================  FERRIER  ======================================================== */
41785  #define R_DSILINK_FERRIER_HTXTO_Pos             (0UL)          /*!< HTXTO (Bit 0)                                         */
41786  #define R_DSILINK_FERRIER_HTXTO_Msk             (0x1UL)        /*!< HTXTO (Bitfield-Mask: 0x01)                           */
41787  #define R_DSILINK_FERRIER_LRXHTO_Pos            (1UL)          /*!< LRXHTO (Bit 1)                                        */
41788  #define R_DSILINK_FERRIER_LRXHTO_Msk            (0x2UL)        /*!< LRXHTO (Bitfield-Mask: 0x01)                          */
41789  #define R_DSILINK_FERRIER_TATO_Pos              (2UL)          /*!< TATO (Bit 2)                                          */
41790  #define R_DSILINK_FERRIER_TATO_Msk              (0x4UL)        /*!< TATO (Bitfield-Mask: 0x01)                            */
41791  #define R_DSILINK_FERRIER_ESCENT_Pos            (16UL)         /*!< ESCENT (Bit 16)                                       */
41792  #define R_DSILINK_FERRIER_ESCENT_Msk            (0x10000UL)    /*!< ESCENT (Bitfield-Mask: 0x01)                          */
41793  #define R_DSILINK_FERRIER_SYNCESC_Pos           (17UL)         /*!< SYNCESC (Bit 17)                                      */
41794  #define R_DSILINK_FERRIER_SYNCESC_Msk           (0x20000UL)    /*!< SYNCESC (Bitfield-Mask: 0x01)                         */
41795  #define R_DSILINK_FERRIER_CTRL_Pos              (18UL)         /*!< CTRL (Bit 18)                                         */
41796  #define R_DSILINK_FERRIER_CTRL_Msk              (0x40000UL)    /*!< CTRL (Bitfield-Mask: 0x01)                            */
41797  #define R_DSILINK_FERRIER_CLP0_Pos              (19UL)         /*!< CLP0 (Bit 19)                                         */
41798  #define R_DSILINK_FERRIER_CLP0_Msk              (0x80000UL)    /*!< CLP0 (Bitfield-Mask: 0x01)                            */
41799  #define R_DSILINK_FERRIER_CLP1_Pos              (20UL)         /*!< CLP1 (Bit 20)                                         */
41800  #define R_DSILINK_FERRIER_CLP1_Msk              (0x100000UL)   /*!< CLP1 (Bitfield-Mask: 0x01)                            */
41801 /* ======================================================  CLSTPTSETR  ======================================================= */
41802  #define R_DSILINK_CLSTPTSETR_CLKSTPT_Pos        (2UL)          /*!< CLKSTPT (Bit 2)                                       */
41803  #define R_DSILINK_CLSTPTSETR_CLKSTPT_Msk        (0xffcUL)      /*!< CLKSTPT (Bitfield-Mask: 0x3ff)                        */
41804  #define R_DSILINK_CLSTPTSETR_CLKBFHT_Pos        (16UL)         /*!< CLKBFHT (Bit 16)                                      */
41805  #define R_DSILINK_CLSTPTSETR_CLKBFHT_Msk        (0xff0000UL)   /*!< CLKBFHT (Bitfield-Mask: 0xff)                         */
41806  #define R_DSILINK_CLSTPTSETR_CLKKPT_Pos         (24UL)         /*!< CLKKPT (Bit 24)                                       */
41807  #define R_DSILINK_CLSTPTSETR_CLKKPT_Msk         (0xff000000UL) /*!< CLKKPT (Bitfield-Mask: 0xff)                          */
41808 /* ======================================================  LPTRNSTSETR  ====================================================== */
41809  #define R_DSILINK_LPTRNSTSETR_GOLPBKT_Pos       (0UL)          /*!< GOLPBKT (Bit 0)                                       */
41810  #define R_DSILINK_LPTRNSTSETR_GOLPBKT_Msk       (0x3ffUL)      /*!< GOLPBKT (Bitfield-Mask: 0x3ff)                        */
41811 /* =========================================================  PLSR  ========================================================== */
41812  #define R_DSILINK_PLSR_CLUAN_Pos                (0UL)          /*!< CLUAN (Bit 0)                                         */
41813  #define R_DSILINK_PLSR_CLUAN_Msk                (0x1UL)        /*!< CLUAN (Bitfield-Mask: 0x01)                           */
41814  #define R_DSILINK_PLSR_CLSTP_Pos                (1UL)          /*!< CLSTP (Bit 1)                                         */
41815  #define R_DSILINK_PLSR_CLSTP_Msk                (0x2UL)        /*!< CLSTP (Bitfield-Mask: 0x01)                           */
41816  #define R_DSILINK_PLSR_DL0RLE_Pos               (2UL)          /*!< DL0RLE (Bit 2)                                        */
41817  #define R_DSILINK_PLSR_DL0RLE_Msk               (0x4UL)        /*!< DL0RLE (Bitfield-Mask: 0x01)                          */
41818  #define R_DSILINK_PLSR_DL0RUE_Pos               (3UL)          /*!< DL0RUE (Bit 3)                                        */
41819  #define R_DSILINK_PLSR_DL0RUE_Msk               (0x8UL)        /*!< DL0RUE (Bitfield-Mask: 0x01)                          */
41820  #define R_DSILINK_PLSR_DL0UAN_Pos               (4UL)          /*!< DL0UAN (Bit 4)                                        */
41821  #define R_DSILINK_PLSR_DL0UAN_Msk               (0x10UL)       /*!< DL0UAN (Bitfield-Mask: 0x01)                          */
41822  #define R_DSILINK_PLSR_DL1UAN_Pos               (5UL)          /*!< DL1UAN (Bit 5)                                        */
41823  #define R_DSILINK_PLSR_DL1UAN_Msk               (0x20UL)       /*!< DL1UAN (Bitfield-Mask: 0x01)                          */
41824  #define R_DSILINK_PLSR_DL0STP_Pos               (8UL)          /*!< DL0STP (Bit 8)                                        */
41825  #define R_DSILINK_PLSR_DL0STP_Msk               (0x100UL)      /*!< DL0STP (Bitfield-Mask: 0x01)                          */
41826  #define R_DSILINK_PLSR_DL1STP_Pos               (9UL)          /*!< DL1STP (Bit 9)                                        */
41827  #define R_DSILINK_PLSR_DL1STP_Msk               (0x200UL)      /*!< DL1STP (Bitfield-Mask: 0x01)                          */
41828  #define R_DSILINK_PLSR_DL0RX2TX_Pos             (12UL)         /*!< DL0RX2TX (Bit 12)                                     */
41829  #define R_DSILINK_PLSR_DL0RX2TX_Msk             (0x1000UL)     /*!< DL0RX2TX (Bitfield-Mask: 0x01)                        */
41830  #define R_DSILINK_PLSR_DL0TX2RX_Pos             (13UL)         /*!< DL0TX2RX (Bit 13)                                     */
41831  #define R_DSILINK_PLSR_DL0TX2RX_Msk             (0x2000UL)     /*!< DL0TX2RX (Bitfield-Mask: 0x01)                        */
41832  #define R_DSILINK_PLSR_DL0DIR_Pos               (15UL)         /*!< DL0DIR (Bit 15)                                       */
41833  #define R_DSILINK_PLSR_DL0DIR_Msk               (0x8000UL)     /*!< DL0DIR (Bitfield-Mask: 0x01)                          */
41834  #define R_DSILINK_PLSR_CLULPENT_Pos             (24UL)         /*!< CLULPENT (Bit 24)                                     */
41835  #define R_DSILINK_PLSR_CLULPENT_Msk             (0x1000000UL)  /*!< CLULPENT (Bitfield-Mask: 0x01)                        */
41836  #define R_DSILINK_PLSR_CLULPEXT_Pos             (25UL)         /*!< CLULPEXT (Bit 25)                                     */
41837  #define R_DSILINK_PLSR_CLULPEXT_Msk             (0x2000000UL)  /*!< CLULPEXT (Bitfield-Mask: 0x01)                        */
41838  #define R_DSILINK_PLSR_CLLP2HS_Pos              (26UL)         /*!< CLLP2HS (Bit 26)                                      */
41839  #define R_DSILINK_PLSR_CLLP2HS_Msk              (0x4000000UL)  /*!< CLLP2HS (Bitfield-Mask: 0x01)                         */
41840  #define R_DSILINK_PLSR_CLHS2LP_Pos              (27UL)         /*!< CLHS2LP (Bit 27)                                      */
41841  #define R_DSILINK_PLSR_CLHS2LP_Msk              (0x8000000UL)  /*!< CLHS2LP (Bitfield-Mask: 0x01)                         */
41842  #define R_DSILINK_PLSR_DLULPENT_Pos             (28UL)         /*!< DLULPENT (Bit 28)                                     */
41843  #define R_DSILINK_PLSR_DLULPENT_Msk             (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01)                        */
41844  #define R_DSILINK_PLSR_DLULPEXT_Pos             (29UL)         /*!< DLULPEXT (Bit 29)                                     */
41845  #define R_DSILINK_PLSR_DLULPEXT_Msk             (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01)                        */
41846 /* =========================================================  PLSCR  ========================================================= */
41847  #define R_DSILINK_PLSCR_DL0RX2TX_Pos            (12UL)         /*!< DL0RX2TX (Bit 12)                                     */
41848  #define R_DSILINK_PLSCR_DL0RX2TX_Msk            (0x1000UL)     /*!< DL0RX2TX (Bitfield-Mask: 0x01)                        */
41849  #define R_DSILINK_PLSCR_DL0TX2RX_Pos            (13UL)         /*!< DL0TX2RX (Bit 13)                                     */
41850  #define R_DSILINK_PLSCR_DL0TX2RX_Msk            (0x2000UL)     /*!< DL0TX2RX (Bitfield-Mask: 0x01)                        */
41851  #define R_DSILINK_PLSCR_CLULPENT_Pos            (24UL)         /*!< CLULPENT (Bit 24)                                     */
41852  #define R_DSILINK_PLSCR_CLULPENT_Msk            (0x1000000UL)  /*!< CLULPENT (Bitfield-Mask: 0x01)                        */
41853  #define R_DSILINK_PLSCR_CLULPEXT_Pos            (25UL)         /*!< CLULPEXT (Bit 25)                                     */
41854  #define R_DSILINK_PLSCR_CLULPEXT_Msk            (0x2000000UL)  /*!< CLULPEXT (Bitfield-Mask: 0x01)                        */
41855  #define R_DSILINK_PLSCR_CLLP2HS_Pos             (26UL)         /*!< CLLP2HS (Bit 26)                                      */
41856  #define R_DSILINK_PLSCR_CLLP2HS_Msk             (0x4000000UL)  /*!< CLLP2HS (Bitfield-Mask: 0x01)                         */
41857  #define R_DSILINK_PLSCR_CLHS2LP_Pos             (27UL)         /*!< CLHS2LP (Bit 27)                                      */
41858  #define R_DSILINK_PLSCR_CLHS2LP_Msk             (0x8000000UL)  /*!< CLHS2LP (Bitfield-Mask: 0x01)                         */
41859  #define R_DSILINK_PLSCR_DLULPENT_Pos            (28UL)         /*!< DLULPENT (Bit 28)                                     */
41860  #define R_DSILINK_PLSCR_DLULPENT_Msk            (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01)                        */
41861  #define R_DSILINK_PLSCR_DLULPEXT_Pos            (29UL)         /*!< DLULPEXT (Bit 29)                                     */
41862  #define R_DSILINK_PLSCR_DLULPEXT_Msk            (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01)                        */
41863 /* =========================================================  PLIER  ========================================================= */
41864  #define R_DSILINK_PLIER_DL0RX2TX_Pos            (12UL)         /*!< DL0RX2TX (Bit 12)                                     */
41865  #define R_DSILINK_PLIER_DL0RX2TX_Msk            (0x1000UL)     /*!< DL0RX2TX (Bitfield-Mask: 0x01)                        */
41866  #define R_DSILINK_PLIER_DL0TX2RX_Pos            (13UL)         /*!< DL0TX2RX (Bit 13)                                     */
41867  #define R_DSILINK_PLIER_DL0TX2RX_Msk            (0x2000UL)     /*!< DL0TX2RX (Bitfield-Mask: 0x01)                        */
41868  #define R_DSILINK_PLIER_CLULPENT_Pos            (24UL)         /*!< CLULPENT (Bit 24)                                     */
41869  #define R_DSILINK_PLIER_CLULPENT_Msk            (0x1000000UL)  /*!< CLULPENT (Bitfield-Mask: 0x01)                        */
41870  #define R_DSILINK_PLIER_CLULPEXT_Pos            (25UL)         /*!< CLULPEXT (Bit 25)                                     */
41871  #define R_DSILINK_PLIER_CLULPEXT_Msk            (0x2000000UL)  /*!< CLULPEXT (Bitfield-Mask: 0x01)                        */
41872  #define R_DSILINK_PLIER_CLLP2HS_Pos             (26UL)         /*!< CLLP2HS (Bit 26)                                      */
41873  #define R_DSILINK_PLIER_CLLP2HS_Msk             (0x4000000UL)  /*!< CLLP2HS (Bitfield-Mask: 0x01)                         */
41874  #define R_DSILINK_PLIER_CLHS2LP_Pos             (27UL)         /*!< CLHS2LP (Bit 27)                                      */
41875  #define R_DSILINK_PLIER_CLHS2LP_Msk             (0x8000000UL)  /*!< CLHS2LP (Bitfield-Mask: 0x01)                         */
41876  #define R_DSILINK_PLIER_DLULPENT_Pos            (28UL)         /*!< DLULPENT (Bit 28)                                     */
41877  #define R_DSILINK_PLIER_DLULPENT_Msk            (0x10000000UL) /*!< DLULPENT (Bitfield-Mask: 0x01)                        */
41878  #define R_DSILINK_PLIER_DLULPEXT_Pos            (29UL)         /*!< DLULPEXT (Bit 29)                                     */
41879  #define R_DSILINK_PLIER_DLULPEXT_Msk            (0x20000000UL) /*!< DLULPEXT (Bitfield-Mask: 0x01)                        */
41880 /* ========================================================  VMSET0R  ======================================================== */
41881  #define R_DSILINK_VMSET0R_VSTART_Pos            (0UL)          /*!< VSTART (Bit 0)                                        */
41882  #define R_DSILINK_VMSET0R_VSTART_Msk            (0x1UL)        /*!< VSTART (Bitfield-Mask: 0x01)                          */
41883  #define R_DSILINK_VMSET0R_VSTOP_Pos             (1UL)          /*!< VSTOP (Bit 1)                                         */
41884  #define R_DSILINK_VMSET0R_VSTOP_Msk             (0x2UL)        /*!< VSTOP (Bitfield-Mask: 0x01)                           */
41885  #define R_DSILINK_VMSET0R_HSANOLP_Pos           (8UL)          /*!< HSANOLP (Bit 8)                                       */
41886  #define R_DSILINK_VMSET0R_HSANOLP_Msk           (0x100UL)      /*!< HSANOLP (Bitfield-Mask: 0x01)                         */
41887  #define R_DSILINK_VMSET0R_HBPNOLP_Pos           (9UL)          /*!< HBPNOLP (Bit 9)                                       */
41888  #define R_DSILINK_VMSET0R_HBPNOLP_Msk           (0x200UL)      /*!< HBPNOLP (Bitfield-Mask: 0x01)                         */
41889  #define R_DSILINK_VMSET0R_HFPNOLP_Pos           (10UL)         /*!< HFPNOLP (Bit 10)                                      */
41890  #define R_DSILINK_VMSET0R_HFPNOLP_Msk           (0x400UL)      /*!< HFPNOLP (Bitfield-Mask: 0x01)                         */
41891 /* ========================================================  VMSET1R  ======================================================== */
41892  #define R_DSILINK_VMSET1R_DLY_Pos               (2UL)          /*!< DLY (Bit 2)                                           */
41893  #define R_DSILINK_VMSET1R_DLY_Msk               (0x3ffcUL)     /*!< DLY (Bitfield-Mask: 0xfff)                            */
41894 /* =========================================================  VMSR  ========================================================== */
41895  #define R_DSILINK_VMSR_START_Pos                (0UL)          /*!< START (Bit 0)                                         */
41896  #define R_DSILINK_VMSR_START_Msk                (0x1UL)        /*!< START (Bitfield-Mask: 0x01)                           */
41897  #define R_DSILINK_VMSR_STOP_Pos                 (1UL)          /*!< STOP (Bit 1)                                          */
41898  #define R_DSILINK_VMSR_STOP_Msk                 (0x2UL)        /*!< STOP (Bitfield-Mask: 0x01)                            */
41899  #define R_DSILINK_VMSR_RUNNING_Pos              (2UL)          /*!< RUNNING (Bit 2)                                       */
41900  #define R_DSILINK_VMSR_RUNNING_Msk              (0x4UL)        /*!< RUNNING (Bitfield-Mask: 0x01)                         */
41901  #define R_DSILINK_VMSR_VIRDY_Pos                (3UL)          /*!< VIRDY (Bit 3)                                         */
41902  #define R_DSILINK_VMSR_VIRDY_Msk                (0x8UL)        /*!< VIRDY (Bitfield-Mask: 0x01)                           */
41903  #define R_DSILINK_VMSR_TIMERR_Pos               (20UL)         /*!< TIMERR (Bit 20)                                       */
41904  #define R_DSILINK_VMSR_TIMERR_Msk               (0x100000UL)   /*!< TIMERR (Bitfield-Mask: 0x01)                          */
41905  #define R_DSILINK_VMSR_VBUFUDF_Pos              (22UL)         /*!< VBUFUDF (Bit 22)                                      */
41906  #define R_DSILINK_VMSR_VBUFUDF_Msk              (0x400000UL)   /*!< VBUFUDF (Bitfield-Mask: 0x01)                         */
41907  #define R_DSILINK_VMSR_VBUFOVF_Pos              (23UL)         /*!< VBUFOVF (Bit 23)                                      */
41908  #define R_DSILINK_VMSR_VBUFOVF_Msk              (0x800000UL)   /*!< VBUFOVF (Bitfield-Mask: 0x01)                         */
41909 /* =========================================================  VMSCR  ========================================================= */
41910  #define R_DSILINK_VMSCR_START_Pos               (0UL)          /*!< START (Bit 0)                                         */
41911  #define R_DSILINK_VMSCR_START_Msk               (0x1UL)        /*!< START (Bitfield-Mask: 0x01)                           */
41912  #define R_DSILINK_VMSCR_STOP_Pos                (1UL)          /*!< STOP (Bit 1)                                          */
41913  #define R_DSILINK_VMSCR_STOP_Msk                (0x2UL)        /*!< STOP (Bitfield-Mask: 0x01)                            */
41914  #define R_DSILINK_VMSCR_VIRDY_Pos               (3UL)          /*!< VIRDY (Bit 3)                                         */
41915  #define R_DSILINK_VMSCR_VIRDY_Msk               (0x8UL)        /*!< VIRDY (Bitfield-Mask: 0x01)                           */
41916  #define R_DSILINK_VMSCR_TIMERR_Pos              (20UL)         /*!< TIMERR (Bit 20)                                       */
41917  #define R_DSILINK_VMSCR_TIMERR_Msk              (0x100000UL)   /*!< TIMERR (Bitfield-Mask: 0x01)                          */
41918  #define R_DSILINK_VMSCR_VBUFUDF_Pos             (22UL)         /*!< VBUFUDF (Bit 22)                                      */
41919  #define R_DSILINK_VMSCR_VBUFUDF_Msk             (0x400000UL)   /*!< VBUFUDF (Bitfield-Mask: 0x01)                         */
41920  #define R_DSILINK_VMSCR_VBUFOVF_Pos             (23UL)         /*!< VBUFOVF (Bit 23)                                      */
41921  #define R_DSILINK_VMSCR_VBUFOVF_Msk             (0x800000UL)   /*!< VBUFOVF (Bitfield-Mask: 0x01)                         */
41922 /* =========================================================  VMIER  ========================================================= */
41923  #define R_DSILINK_VMIER_START_Pos               (0UL)          /*!< START (Bit 0)                                         */
41924  #define R_DSILINK_VMIER_START_Msk               (0x1UL)        /*!< START (Bitfield-Mask: 0x01)                           */
41925  #define R_DSILINK_VMIER_STOP_Pos                (1UL)          /*!< STOP (Bit 1)                                          */
41926  #define R_DSILINK_VMIER_STOP_Msk                (0x2UL)        /*!< STOP (Bitfield-Mask: 0x01)                            */
41927  #define R_DSILINK_VMIER_VIRDY_Pos               (3UL)          /*!< VIRDY (Bit 3)                                         */
41928  #define R_DSILINK_VMIER_VIRDY_Msk               (0x8UL)        /*!< VIRDY (Bitfield-Mask: 0x01)                           */
41929  #define R_DSILINK_VMIER_TIMERR_Pos              (20UL)         /*!< TIMERR (Bit 20)                                       */
41930  #define R_DSILINK_VMIER_TIMERR_Msk              (0x100000UL)   /*!< TIMERR (Bitfield-Mask: 0x01)                          */
41931  #define R_DSILINK_VMIER_VBUFUDF_Pos             (22UL)         /*!< VBUFUDF (Bit 22)                                      */
41932  #define R_DSILINK_VMIER_VBUFUDF_Msk             (0x400000UL)   /*!< VBUFUDF (Bitfield-Mask: 0x01)                         */
41933  #define R_DSILINK_VMIER_VBUFOVF_Pos             (23UL)         /*!< VBUFOVF (Bit 23)                                      */
41934  #define R_DSILINK_VMIER_VBUFOVF_Msk             (0x800000UL)   /*!< VBUFOVF (Bitfield-Mask: 0x01)                         */
41935 /* =======================================================  VMPPSETR  ======================================================== */
41936  #define R_DSILINK_VMPPSETR_TXESYNC_Pos          (15UL)         /*!< TXESYNC (Bit 15)                                      */
41937  #define R_DSILINK_VMPPSETR_TXESYNC_Msk          (0x8000UL)     /*!< TXESYNC (Bitfield-Mask: 0x01)                         */
41938  #define R_DSILINK_VMPPSETR_DT_Pos               (16UL)         /*!< DT (Bit 16)                                           */
41939  #define R_DSILINK_VMPPSETR_DT_Msk               (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
41940  #define R_DSILINK_VMPPSETR_VC_Pos               (22UL)         /*!< VC (Bit 22)                                           */
41941  #define R_DSILINK_VMPPSETR_VC_Msk               (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
41942 /* =======================================================  VMVSSETR  ======================================================== */
41943  #define R_DSILINK_VMVSSETR_VSA_Pos              (0UL)          /*!< VSA (Bit 0)                                           */
41944  #define R_DSILINK_VMVSSETR_VSA_Msk              (0xfffUL)      /*!< VSA (Bitfield-Mask: 0xfff)                            */
41945  #define R_DSILINK_VMVSSETR_VSPOL_Pos            (15UL)         /*!< VSPOL (Bit 15)                                        */
41946  #define R_DSILINK_VMVSSETR_VSPOL_Msk            (0x8000UL)     /*!< VSPOL (Bitfield-Mask: 0x01)                           */
41947  #define R_DSILINK_VMVSSETR_VACT_Pos             (16UL)         /*!< VACT (Bit 16)                                         */
41948  #define R_DSILINK_VMVSSETR_VACT_Msk             (0x7fff0000UL) /*!< VACT (Bitfield-Mask: 0x7fff)                          */
41949 /* =======================================================  VMVPSETR  ======================================================== */
41950  #define R_DSILINK_VMVPSETR_VBP_Pos              (0UL)          /*!< VBP (Bit 0)                                           */
41951  #define R_DSILINK_VMVPSETR_VBP_Msk              (0x1fffUL)     /*!< VBP (Bitfield-Mask: 0x1fff)                           */
41952  #define R_DSILINK_VMVPSETR_VFP_Pos              (16UL)         /*!< VFP (Bit 16)                                          */
41953  #define R_DSILINK_VMVPSETR_VFP_Msk              (0x1fff0000UL) /*!< VFP (Bitfield-Mask: 0x1fff)                           */
41954 /* =======================================================  VMHSSETR  ======================================================== */
41955  #define R_DSILINK_VMHSSETR_HSA_Pos              (0UL)          /*!< HSA (Bit 0)                                           */
41956  #define R_DSILINK_VMHSSETR_HSA_Msk              (0xfffUL)      /*!< HSA (Bitfield-Mask: 0xfff)                            */
41957  #define R_DSILINK_VMHSSETR_HSPOL_Pos            (15UL)         /*!< HSPOL (Bit 15)                                        */
41958  #define R_DSILINK_VMHSSETR_HSPOL_Msk            (0x8000UL)     /*!< HSPOL (Bitfield-Mask: 0x01)                           */
41959  #define R_DSILINK_VMHSSETR_HACT_Pos             (16UL)         /*!< HACT (Bit 16)                                         */
41960  #define R_DSILINK_VMHSSETR_HACT_Msk             (0x7fff0000UL) /*!< HACT (Bitfield-Mask: 0x7fff)                          */
41961 /* =======================================================  VMHPSETR  ======================================================== */
41962  #define R_DSILINK_VMHPSETR_HBP_Pos              (0UL)          /*!< HBP (Bit 0)                                           */
41963  #define R_DSILINK_VMHPSETR_HBP_Msk              (0x1fffUL)     /*!< HBP (Bitfield-Mask: 0x1fff)                           */
41964  #define R_DSILINK_VMHPSETR_HFP_Pos              (16UL)         /*!< HFP (Bit 16)                                          */
41965  #define R_DSILINK_VMHPSETR_HFP_Msk              (0x1fff0000UL) /*!< HFP (Bitfield-Mask: 0x1fff)                           */
41966 /* ======================================================  SQCH0SET0R  ======================================================= */
41967  #define R_DSILINK_SQCH0SET0R_START_Pos          (0UL)          /*!< START (Bit 0)                                         */
41968  #define R_DSILINK_SQCH0SET0R_START_Msk          (0x1UL)        /*!< START (Bitfield-Mask: 0x01)                           */
41969 /* ========================================================  SQCH0SR  ======================================================== */
41970  #define R_DSILINK_SQCH0SR_RUNNING_Pos           (2UL)          /*!< RUNNING (Bit 2)                                       */
41971  #define R_DSILINK_SQCH0SR_RUNNING_Msk           (0x4UL)        /*!< RUNNING (Bitfield-Mask: 0x01)                         */
41972  #define R_DSILINK_SQCH0SR_AACTFIN_Pos           (4UL)          /*!< AACTFIN (Bit 4)                                       */
41973  #define R_DSILINK_SQCH0SR_AACTFIN_Msk           (0x10UL)       /*!< AACTFIN (Bitfield-Mask: 0x01)                         */
41974  #define R_DSILINK_SQCH0SR_ADESFIN_Pos           (8UL)          /*!< ADESFIN (Bit 8)                                       */
41975  #define R_DSILINK_SQCH0SR_ADESFIN_Msk           (0x100UL)      /*!< ADESFIN (Bitfield-Mask: 0x01)                         */
41976  #define R_DSILINK_SQCH0SR_DABORT_Pos            (16UL)         /*!< DABORT (Bit 16)                                       */
41977  #define R_DSILINK_SQCH0SR_DABORT_Msk            (0x10000UL)    /*!< DABORT (Bitfield-Mask: 0x01)                          */
41978  #define R_DSILINK_SQCH0SR_SIZEERR_Pos           (19UL)         /*!< SIZEERR (Bit 19)                                      */
41979  #define R_DSILINK_SQCH0SR_SIZEERR_Msk           (0x80000UL)    /*!< SIZEERR (Bitfield-Mask: 0x01)                         */
41980  #define R_DSILINK_SQCH0SR_TXIBERR_Pos           (24UL)         /*!< TXIBERR (Bit 24)                                      */
41981  #define R_DSILINK_SQCH0SR_TXIBERR_Msk           (0x1000000UL)  /*!< TXIBERR (Bitfield-Mask: 0x01)                         */
41982  #define R_DSILINK_SQCH0SR_RXFERR_Pos            (26UL)         /*!< RXFERR (Bit 26)                                       */
41983  #define R_DSILINK_SQCH0SR_RXFERR_Msk            (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
41984  #define R_DSILINK_SQCH0SR_RXFAIL_Pos            (27UL)         /*!< RXFAIL (Bit 27)                                       */
41985  #define R_DSILINK_SQCH0SR_RXFAIL_Msk            (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
41986  #define R_DSILINK_SQCH0SR_RXPFAIL_Pos           (28UL)         /*!< RXPFAIL (Bit 28)                                      */
41987  #define R_DSILINK_SQCH0SR_RXPFAIL_Msk           (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
41988  #define R_DSILINK_SQCH0SR_RXCORERR_Pos          (29UL)         /*!< RXCORERR (Bit 29)                                     */
41989  #define R_DSILINK_SQCH0SR_RXCORERR_Msk          (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01)                        */
41990  #define R_DSILINK_SQCH0SR_RXAKE_Pos             (30UL)         /*!< RXAKE (Bit 30)                                        */
41991  #define R_DSILINK_SQCH0SR_RXAKE_Msk             (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
41992 /* =======================================================  SQCH0SCR  ======================================================== */
41993  #define R_DSILINK_SQCH0SCR_AACTFIN_Pos          (4UL)          /*!< AACTFIN (Bit 4)                                       */
41994  #define R_DSILINK_SQCH0SCR_AACTFIN_Msk          (0x10UL)       /*!< AACTFIN (Bitfield-Mask: 0x01)                         */
41995  #define R_DSILINK_SQCH0SCR_ADESFIN_Pos          (8UL)          /*!< ADESFIN (Bit 8)                                       */
41996  #define R_DSILINK_SQCH0SCR_ADESFIN_Msk          (0x100UL)      /*!< ADESFIN (Bitfield-Mask: 0x01)                         */
41997  #define R_DSILINK_SQCH0SCR_DABORT_Pos           (16UL)         /*!< DABORT (Bit 16)                                       */
41998  #define R_DSILINK_SQCH0SCR_DABORT_Msk           (0x10000UL)    /*!< DABORT (Bitfield-Mask: 0x01)                          */
41999  #define R_DSILINK_SQCH0SCR_SIZEERR_Pos          (19UL)         /*!< SIZEERR (Bit 19)                                      */
42000  #define R_DSILINK_SQCH0SCR_SIZEERR_Msk          (0x80000UL)    /*!< SIZEERR (Bitfield-Mask: 0x01)                         */
42001  #define R_DSILINK_SQCH0SCR_TXIBERR_Pos          (24UL)         /*!< TXIBERR (Bit 24)                                      */
42002  #define R_DSILINK_SQCH0SCR_TXIBERR_Msk          (0x1000000UL)  /*!< TXIBERR (Bitfield-Mask: 0x01)                         */
42003  #define R_DSILINK_SQCH0SCR_RXFERR_Pos           (26UL)         /*!< RXFERR (Bit 26)                                       */
42004  #define R_DSILINK_SQCH0SCR_RXFERR_Msk           (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
42005  #define R_DSILINK_SQCH0SCR_RXFAIL_Pos           (27UL)         /*!< RXFAIL (Bit 27)                                       */
42006  #define R_DSILINK_SQCH0SCR_RXFAIL_Msk           (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
42007  #define R_DSILINK_SQCH0SCR_RXPFAIL_Pos          (28UL)         /*!< RXPFAIL (Bit 28)                                      */
42008  #define R_DSILINK_SQCH0SCR_RXPFAIL_Msk          (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
42009  #define R_DSILINK_SQCH0SCR_RXCORERR_Pos         (29UL)         /*!< RXCORERR (Bit 29)                                     */
42010  #define R_DSILINK_SQCH0SCR_RXCORERR_Msk         (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01)                        */
42011  #define R_DSILINK_SQCH0SCR_RXAKE_Pos            (30UL)         /*!< RXAKE (Bit 30)                                        */
42012  #define R_DSILINK_SQCH0SCR_RXAKE_Msk            (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
42013 /* =======================================================  SQCH0IER  ======================================================== */
42014  #define R_DSILINK_SQCH0IER_AACTFIN_Pos          (4UL)          /*!< AACTFIN (Bit 4)                                       */
42015  #define R_DSILINK_SQCH0IER_AACTFIN_Msk          (0x10UL)       /*!< AACTFIN (Bitfield-Mask: 0x01)                         */
42016  #define R_DSILINK_SQCH0IER_ADESFIN_Pos          (8UL)          /*!< ADESFIN (Bit 8)                                       */
42017  #define R_DSILINK_SQCH0IER_ADESFIN_Msk          (0x100UL)      /*!< ADESFIN (Bitfield-Mask: 0x01)                         */
42018  #define R_DSILINK_SQCH0IER_DABORT_Pos           (16UL)         /*!< DABORT (Bit 16)                                       */
42019  #define R_DSILINK_SQCH0IER_DABORT_Msk           (0x10000UL)    /*!< DABORT (Bitfield-Mask: 0x01)                          */
42020  #define R_DSILINK_SQCH0IER_SIZEERR_Pos          (19UL)         /*!< SIZEERR (Bit 19)                                      */
42021  #define R_DSILINK_SQCH0IER_SIZEERR_Msk          (0x80000UL)    /*!< SIZEERR (Bitfield-Mask: 0x01)                         */
42022  #define R_DSILINK_SQCH0IER_TXIBERR_Pos          (24UL)         /*!< TXIBERR (Bit 24)                                      */
42023  #define R_DSILINK_SQCH0IER_TXIBERR_Msk          (0x1000000UL)  /*!< TXIBERR (Bitfield-Mask: 0x01)                         */
42024  #define R_DSILINK_SQCH0IER_RXFERR_Pos           (26UL)         /*!< RXFERR (Bit 26)                                       */
42025  #define R_DSILINK_SQCH0IER_RXFERR_Msk           (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
42026  #define R_DSILINK_SQCH0IER_RXFAIL_Pos           (27UL)         /*!< RXFAIL (Bit 27)                                       */
42027  #define R_DSILINK_SQCH0IER_RXFAIL_Msk           (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
42028  #define R_DSILINK_SQCH0IER_RXPFAIL_Pos          (28UL)         /*!< RXPFAIL (Bit 28)                                      */
42029  #define R_DSILINK_SQCH0IER_RXPFAIL_Msk          (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
42030  #define R_DSILINK_SQCH0IER_RXCORERR_Pos         (29UL)         /*!< RXCORERR (Bit 29)                                     */
42031  #define R_DSILINK_SQCH0IER_RXCORERR_Msk         (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01)                        */
42032  #define R_DSILINK_SQCH0IER_RXAKE_Pos            (30UL)         /*!< RXAKE (Bit 30)                                        */
42033  #define R_DSILINK_SQCH0IER_RXAKE_Msk            (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
42034 /* ======================================================  SQCH1SET0R  ======================================================= */
42035  #define R_DSILINK_SQCH1SET0R_START_Pos          (0UL)          /*!< START (Bit 0)                                         */
42036  #define R_DSILINK_SQCH1SET0R_START_Msk          (0x1UL)        /*!< START (Bitfield-Mask: 0x01)                           */
42037 /* ========================================================  SQCH1SR  ======================================================== */
42038  #define R_DSILINK_SQCH1SR_RUNNING_Pos           (2UL)          /*!< RUNNING (Bit 2)                                       */
42039  #define R_DSILINK_SQCH1SR_RUNNING_Msk           (0x4UL)        /*!< RUNNING (Bitfield-Mask: 0x01)                         */
42040  #define R_DSILINK_SQCH1SR_AACTFIN_Pos           (4UL)          /*!< AACTFIN (Bit 4)                                       */
42041  #define R_DSILINK_SQCH1SR_AACTFIN_Msk           (0x10UL)       /*!< AACTFIN (Bitfield-Mask: 0x01)                         */
42042  #define R_DSILINK_SQCH1SR_ADESFIN_Pos           (8UL)          /*!< ADESFIN (Bit 8)                                       */
42043  #define R_DSILINK_SQCH1SR_ADESFIN_Msk           (0x100UL)      /*!< ADESFIN (Bitfield-Mask: 0x01)                         */
42044  #define R_DSILINK_SQCH1SR_DABORT_Pos            (16UL)         /*!< DABORT (Bit 16)                                       */
42045  #define R_DSILINK_SQCH1SR_DABORT_Msk            (0x10000UL)    /*!< DABORT (Bitfield-Mask: 0x01)                          */
42046  #define R_DSILINK_SQCH1SR_SIZEERR_Pos           (19UL)         /*!< SIZEERR (Bit 19)                                      */
42047  #define R_DSILINK_SQCH1SR_SIZEERR_Msk           (0x80000UL)    /*!< SIZEERR (Bitfield-Mask: 0x01)                         */
42048  #define R_DSILINK_SQCH1SR_TXIBERR_Pos           (24UL)         /*!< TXIBERR (Bit 24)                                      */
42049  #define R_DSILINK_SQCH1SR_TXIBERR_Msk           (0x1000000UL)  /*!< TXIBERR (Bitfield-Mask: 0x01)                         */
42050  #define R_DSILINK_SQCH1SR_RXFERR_Pos            (26UL)         /*!< RXFERR (Bit 26)                                       */
42051  #define R_DSILINK_SQCH1SR_RXFERR_Msk            (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
42052  #define R_DSILINK_SQCH1SR_RXFAIL_Pos            (27UL)         /*!< RXFAIL (Bit 27)                                       */
42053  #define R_DSILINK_SQCH1SR_RXFAIL_Msk            (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
42054  #define R_DSILINK_SQCH1SR_RXPFAIL_Pos           (28UL)         /*!< RXPFAIL (Bit 28)                                      */
42055  #define R_DSILINK_SQCH1SR_RXPFAIL_Msk           (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
42056  #define R_DSILINK_SQCH1SR_RXCORERR_Pos          (29UL)         /*!< RXCORERR (Bit 29)                                     */
42057  #define R_DSILINK_SQCH1SR_RXCORERR_Msk          (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01)                        */
42058  #define R_DSILINK_SQCH1SR_RXAKE_Pos             (30UL)         /*!< RXAKE (Bit 30)                                        */
42059  #define R_DSILINK_SQCH1SR_RXAKE_Msk             (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
42060 /* =======================================================  SQCH1SCR  ======================================================== */
42061  #define R_DSILINK_SQCH1SCR_AACTFIN_Pos          (4UL)          /*!< AACTFIN (Bit 4)                                       */
42062  #define R_DSILINK_SQCH1SCR_AACTFIN_Msk          (0x10UL)       /*!< AACTFIN (Bitfield-Mask: 0x01)                         */
42063  #define R_DSILINK_SQCH1SCR_ADESFIN_Pos          (8UL)          /*!< ADESFIN (Bit 8)                                       */
42064  #define R_DSILINK_SQCH1SCR_ADESFIN_Msk          (0x100UL)      /*!< ADESFIN (Bitfield-Mask: 0x01)                         */
42065  #define R_DSILINK_SQCH1SCR_DABORT_Pos           (16UL)         /*!< DABORT (Bit 16)                                       */
42066  #define R_DSILINK_SQCH1SCR_DABORT_Msk           (0x10000UL)    /*!< DABORT (Bitfield-Mask: 0x01)                          */
42067  #define R_DSILINK_SQCH1SCR_SIZEERR_Pos          (19UL)         /*!< SIZEERR (Bit 19)                                      */
42068  #define R_DSILINK_SQCH1SCR_SIZEERR_Msk          (0x80000UL)    /*!< SIZEERR (Bitfield-Mask: 0x01)                         */
42069  #define R_DSILINK_SQCH1SCR_TXIBERR_Pos          (24UL)         /*!< TXIBERR (Bit 24)                                      */
42070  #define R_DSILINK_SQCH1SCR_TXIBERR_Msk          (0x1000000UL)  /*!< TXIBERR (Bitfield-Mask: 0x01)                         */
42071  #define R_DSILINK_SQCH1SCR_RXFERR_Pos           (26UL)         /*!< RXFERR (Bit 26)                                       */
42072  #define R_DSILINK_SQCH1SCR_RXFERR_Msk           (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
42073  #define R_DSILINK_SQCH1SCR_RXFAIL_Pos           (27UL)         /*!< RXFAIL (Bit 27)                                       */
42074  #define R_DSILINK_SQCH1SCR_RXFAIL_Msk           (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
42075  #define R_DSILINK_SQCH1SCR_RXPFAIL_Pos          (28UL)         /*!< RXPFAIL (Bit 28)                                      */
42076  #define R_DSILINK_SQCH1SCR_RXPFAIL_Msk          (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
42077  #define R_DSILINK_SQCH1SCR_RXCORERR_Pos         (29UL)         /*!< RXCORERR (Bit 29)                                     */
42078  #define R_DSILINK_SQCH1SCR_RXCORERR_Msk         (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01)                        */
42079  #define R_DSILINK_SQCH1SCR_RXAKE_Pos            (30UL)         /*!< RXAKE (Bit 30)                                        */
42080  #define R_DSILINK_SQCH1SCR_RXAKE_Msk            (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
42081 /* =======================================================  SQCH1IER  ======================================================== */
42082  #define R_DSILINK_SQCH1IER_AACTFIN_Pos          (4UL)          /*!< AACTFIN (Bit 4)                                       */
42083  #define R_DSILINK_SQCH1IER_AACTFIN_Msk          (0x10UL)       /*!< AACTFIN (Bitfield-Mask: 0x01)                         */
42084  #define R_DSILINK_SQCH1IER_ADESFIN_Pos          (8UL)          /*!< ADESFIN (Bit 8)                                       */
42085  #define R_DSILINK_SQCH1IER_ADESFIN_Msk          (0x100UL)      /*!< ADESFIN (Bitfield-Mask: 0x01)                         */
42086  #define R_DSILINK_SQCH1IER_DABORT_Pos           (16UL)         /*!< DABORT (Bit 16)                                       */
42087  #define R_DSILINK_SQCH1IER_DABORT_Msk           (0x10000UL)    /*!< DABORT (Bitfield-Mask: 0x01)                          */
42088  #define R_DSILINK_SQCH1IER_SIZEERR_Pos          (19UL)         /*!< SIZEERR (Bit 19)                                      */
42089  #define R_DSILINK_SQCH1IER_SIZEERR_Msk          (0x80000UL)    /*!< SIZEERR (Bitfield-Mask: 0x01)                         */
42090  #define R_DSILINK_SQCH1IER_TXIBERR_Pos          (24UL)         /*!< TXIBERR (Bit 24)                                      */
42091  #define R_DSILINK_SQCH1IER_TXIBERR_Msk          (0x1000000UL)  /*!< TXIBERR (Bitfield-Mask: 0x01)                         */
42092  #define R_DSILINK_SQCH1IER_RXFERR_Pos           (26UL)         /*!< RXFERR (Bit 26)                                       */
42093  #define R_DSILINK_SQCH1IER_RXFERR_Msk           (0x4000000UL)  /*!< RXFERR (Bitfield-Mask: 0x01)                          */
42094  #define R_DSILINK_SQCH1IER_RXFAIL_Pos           (27UL)         /*!< RXFAIL (Bit 27)                                       */
42095  #define R_DSILINK_SQCH1IER_RXFAIL_Msk           (0x8000000UL)  /*!< RXFAIL (Bitfield-Mask: 0x01)                          */
42096  #define R_DSILINK_SQCH1IER_RXPFAIL_Pos          (28UL)         /*!< RXPFAIL (Bit 28)                                      */
42097  #define R_DSILINK_SQCH1IER_RXPFAIL_Msk          (0x10000000UL) /*!< RXPFAIL (Bitfield-Mask: 0x01)                         */
42098  #define R_DSILINK_SQCH1IER_RXCORERR_Pos         (29UL)         /*!< RXCORERR (Bit 29)                                     */
42099  #define R_DSILINK_SQCH1IER_RXCORERR_Msk         (0x20000000UL) /*!< RXCORERR (Bitfield-Mask: 0x01)                        */
42100  #define R_DSILINK_SQCH1IER_RXAKE_Pos            (30UL)         /*!< RXAKE (Bit 30)                                        */
42101  #define R_DSILINK_SQCH1IER_RXAKE_Msk            (0x40000000UL) /*!< RXAKE (Bitfield-Mask: 0x01)                           */
42102 /* ======================================================  SQCH0DSC0AR  ====================================================== */
42103  #define R_DSILINK_SQCH0DSC0AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42104  #define R_DSILINK_SQCH0DSC0AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42105  #define R_DSILINK_SQCH0DSC0AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42106  #define R_DSILINK_SQCH0DSC0AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42107  #define R_DSILINK_SQCH0DSC0AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42108  #define R_DSILINK_SQCH0DSC0AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42109  #define R_DSILINK_SQCH0DSC0AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42110  #define R_DSILINK_SQCH0DSC0AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42111  #define R_DSILINK_SQCH0DSC0AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42112  #define R_DSILINK_SQCH0DSC0AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42113  #define R_DSILINK_SQCH0DSC0AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42114  #define R_DSILINK_SQCH0DSC0AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42115  #define R_DSILINK_SQCH0DSC0AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42116  #define R_DSILINK_SQCH0DSC0AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42117  #define R_DSILINK_SQCH0DSC0AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42118  #define R_DSILINK_SQCH0DSC0AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42119 /* ======================================================  SQCH0DSC1AR  ====================================================== */
42120  #define R_DSILINK_SQCH0DSC1AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42121  #define R_DSILINK_SQCH0DSC1AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42122  #define R_DSILINK_SQCH0DSC1AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42123  #define R_DSILINK_SQCH0DSC1AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42124  #define R_DSILINK_SQCH0DSC1AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42125  #define R_DSILINK_SQCH0DSC1AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42126  #define R_DSILINK_SQCH0DSC1AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42127  #define R_DSILINK_SQCH0DSC1AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42128  #define R_DSILINK_SQCH0DSC1AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42129  #define R_DSILINK_SQCH0DSC1AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42130  #define R_DSILINK_SQCH0DSC1AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42131  #define R_DSILINK_SQCH0DSC1AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42132  #define R_DSILINK_SQCH0DSC1AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42133  #define R_DSILINK_SQCH0DSC1AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42134  #define R_DSILINK_SQCH0DSC1AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42135  #define R_DSILINK_SQCH0DSC1AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42136 /* ======================================================  SQCH0DSC2AR  ====================================================== */
42137  #define R_DSILINK_SQCH0DSC2AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42138  #define R_DSILINK_SQCH0DSC2AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42139  #define R_DSILINK_SQCH0DSC2AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42140  #define R_DSILINK_SQCH0DSC2AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42141  #define R_DSILINK_SQCH0DSC2AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42142  #define R_DSILINK_SQCH0DSC2AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42143  #define R_DSILINK_SQCH0DSC2AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42144  #define R_DSILINK_SQCH0DSC2AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42145  #define R_DSILINK_SQCH0DSC2AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42146  #define R_DSILINK_SQCH0DSC2AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42147  #define R_DSILINK_SQCH0DSC2AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42148  #define R_DSILINK_SQCH0DSC2AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42149  #define R_DSILINK_SQCH0DSC2AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42150  #define R_DSILINK_SQCH0DSC2AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42151  #define R_DSILINK_SQCH0DSC2AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42152  #define R_DSILINK_SQCH0DSC2AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42153 /* ======================================================  SQCH0DSC3AR  ====================================================== */
42154  #define R_DSILINK_SQCH0DSC3AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42155  #define R_DSILINK_SQCH0DSC3AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42156  #define R_DSILINK_SQCH0DSC3AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42157  #define R_DSILINK_SQCH0DSC3AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42158  #define R_DSILINK_SQCH0DSC3AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42159  #define R_DSILINK_SQCH0DSC3AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42160  #define R_DSILINK_SQCH0DSC3AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42161  #define R_DSILINK_SQCH0DSC3AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42162  #define R_DSILINK_SQCH0DSC3AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42163  #define R_DSILINK_SQCH0DSC3AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42164  #define R_DSILINK_SQCH0DSC3AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42165  #define R_DSILINK_SQCH0DSC3AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42166  #define R_DSILINK_SQCH0DSC3AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42167  #define R_DSILINK_SQCH0DSC3AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42168  #define R_DSILINK_SQCH0DSC3AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42169  #define R_DSILINK_SQCH0DSC3AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42170 /* ======================================================  SQCH0DSC4AR  ====================================================== */
42171  #define R_DSILINK_SQCH0DSC4AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42172  #define R_DSILINK_SQCH0DSC4AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42173  #define R_DSILINK_SQCH0DSC4AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42174  #define R_DSILINK_SQCH0DSC4AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42175  #define R_DSILINK_SQCH0DSC4AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42176  #define R_DSILINK_SQCH0DSC4AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42177  #define R_DSILINK_SQCH0DSC4AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42178  #define R_DSILINK_SQCH0DSC4AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42179  #define R_DSILINK_SQCH0DSC4AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42180  #define R_DSILINK_SQCH0DSC4AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42181  #define R_DSILINK_SQCH0DSC4AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42182  #define R_DSILINK_SQCH0DSC4AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42183  #define R_DSILINK_SQCH0DSC4AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42184  #define R_DSILINK_SQCH0DSC4AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42185  #define R_DSILINK_SQCH0DSC4AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42186  #define R_DSILINK_SQCH0DSC4AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42187 /* ======================================================  SQCH0DSC5AR  ====================================================== */
42188  #define R_DSILINK_SQCH0DSC5AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42189  #define R_DSILINK_SQCH0DSC5AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42190  #define R_DSILINK_SQCH0DSC5AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42191  #define R_DSILINK_SQCH0DSC5AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42192  #define R_DSILINK_SQCH0DSC5AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42193  #define R_DSILINK_SQCH0DSC5AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42194  #define R_DSILINK_SQCH0DSC5AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42195  #define R_DSILINK_SQCH0DSC5AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42196  #define R_DSILINK_SQCH0DSC5AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42197  #define R_DSILINK_SQCH0DSC5AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42198  #define R_DSILINK_SQCH0DSC5AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42199  #define R_DSILINK_SQCH0DSC5AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42200  #define R_DSILINK_SQCH0DSC5AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42201  #define R_DSILINK_SQCH0DSC5AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42202  #define R_DSILINK_SQCH0DSC5AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42203  #define R_DSILINK_SQCH0DSC5AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42204 /* ======================================================  SQCH0DSC6AR  ====================================================== */
42205  #define R_DSILINK_SQCH0DSC6AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42206  #define R_DSILINK_SQCH0DSC6AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42207  #define R_DSILINK_SQCH0DSC6AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42208  #define R_DSILINK_SQCH0DSC6AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42209  #define R_DSILINK_SQCH0DSC6AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42210  #define R_DSILINK_SQCH0DSC6AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42211  #define R_DSILINK_SQCH0DSC6AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42212  #define R_DSILINK_SQCH0DSC6AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42213  #define R_DSILINK_SQCH0DSC6AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42214  #define R_DSILINK_SQCH0DSC6AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42215  #define R_DSILINK_SQCH0DSC6AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42216  #define R_DSILINK_SQCH0DSC6AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42217  #define R_DSILINK_SQCH0DSC6AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42218  #define R_DSILINK_SQCH0DSC6AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42219  #define R_DSILINK_SQCH0DSC6AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42220  #define R_DSILINK_SQCH0DSC6AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42221 /* ======================================================  SQCH0DSC7AR  ====================================================== */
42222  #define R_DSILINK_SQCH0DSC7AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42223  #define R_DSILINK_SQCH0DSC7AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42224  #define R_DSILINK_SQCH0DSC7AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42225  #define R_DSILINK_SQCH0DSC7AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42226  #define R_DSILINK_SQCH0DSC7AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42227  #define R_DSILINK_SQCH0DSC7AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42228  #define R_DSILINK_SQCH0DSC7AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42229  #define R_DSILINK_SQCH0DSC7AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42230  #define R_DSILINK_SQCH0DSC7AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42231  #define R_DSILINK_SQCH0DSC7AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42232  #define R_DSILINK_SQCH0DSC7AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42233  #define R_DSILINK_SQCH0DSC7AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42234  #define R_DSILINK_SQCH0DSC7AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42235  #define R_DSILINK_SQCH0DSC7AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42236  #define R_DSILINK_SQCH0DSC7AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42237  #define R_DSILINK_SQCH0DSC7AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42238 /* =====================================================  SQCH0DSC0AR_L  ===================================================== */
42239  #define R_DSILINK_SQCH0DSC0AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
42240  #define R_DSILINK_SQCH0DSC0AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42241  #define R_DSILINK_SQCH0DSC0AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
42242  #define R_DSILINK_SQCH0DSC0AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42243 /* =====================================================  SQCH0DSC1AR_L  ===================================================== */
42244  #define R_DSILINK_SQCH0DSC1AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
42245  #define R_DSILINK_SQCH0DSC1AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42246  #define R_DSILINK_SQCH0DSC1AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
42247  #define R_DSILINK_SQCH0DSC1AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42248 /* =====================================================  SQCH0DSC2AR_L  ===================================================== */
42249  #define R_DSILINK_SQCH0DSC2AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
42250  #define R_DSILINK_SQCH0DSC2AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42251  #define R_DSILINK_SQCH0DSC2AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
42252  #define R_DSILINK_SQCH0DSC2AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42253 /* =====================================================  SQCH0DSC3AR_L  ===================================================== */
42254  #define R_DSILINK_SQCH0DSC3AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
42255  #define R_DSILINK_SQCH0DSC3AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42256  #define R_DSILINK_SQCH0DSC3AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
42257  #define R_DSILINK_SQCH0DSC3AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42258 /* =====================================================  SQCH0DSC4AR_L  ===================================================== */
42259  #define R_DSILINK_SQCH0DSC4AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
42260  #define R_DSILINK_SQCH0DSC4AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42261  #define R_DSILINK_SQCH0DSC4AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
42262  #define R_DSILINK_SQCH0DSC4AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42263 /* =====================================================  SQCH0DSC5AR_L  ===================================================== */
42264  #define R_DSILINK_SQCH0DSC5AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
42265  #define R_DSILINK_SQCH0DSC5AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42266  #define R_DSILINK_SQCH0DSC5AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
42267  #define R_DSILINK_SQCH0DSC5AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42268 /* =====================================================  SQCH0DSC6AR_L  ===================================================== */
42269  #define R_DSILINK_SQCH0DSC6AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
42270  #define R_DSILINK_SQCH0DSC6AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42271  #define R_DSILINK_SQCH0DSC6AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
42272  #define R_DSILINK_SQCH0DSC6AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42273 /* =====================================================  SQCH0DSC7AR_L  ===================================================== */
42274  #define R_DSILINK_SQCH0DSC7AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
42275  #define R_DSILINK_SQCH0DSC7AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42276  #define R_DSILINK_SQCH0DSC7AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
42277  #define R_DSILINK_SQCH0DSC7AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42278 /* ====================================================  SQCH0DSC0AR_LL  ===================================================== */
42279  #define R_DSILINK_SQCH0DSC0AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
42280  #define R_DSILINK_SQCH0DSC0AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42281 /* ====================================================  SQCH0DSC1AR_LL  ===================================================== */
42282  #define R_DSILINK_SQCH0DSC1AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
42283  #define R_DSILINK_SQCH0DSC1AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42284 /* ====================================================  SQCH0DSC2AR_LL  ===================================================== */
42285  #define R_DSILINK_SQCH0DSC2AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
42286  #define R_DSILINK_SQCH0DSC2AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42287 /* ====================================================  SQCH0DSC3AR_LL  ===================================================== */
42288  #define R_DSILINK_SQCH0DSC3AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
42289  #define R_DSILINK_SQCH0DSC3AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42290 /* ====================================================  SQCH0DSC4AR_LL  ===================================================== */
42291  #define R_DSILINK_SQCH0DSC4AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
42292  #define R_DSILINK_SQCH0DSC4AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42293 /* ====================================================  SQCH0DSC5AR_LL  ===================================================== */
42294  #define R_DSILINK_SQCH0DSC5AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
42295  #define R_DSILINK_SQCH0DSC5AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42296 /* ====================================================  SQCH0DSC6AR_LL  ===================================================== */
42297  #define R_DSILINK_SQCH0DSC6AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
42298  #define R_DSILINK_SQCH0DSC6AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42299 /* ====================================================  SQCH0DSC7AR_LL  ===================================================== */
42300  #define R_DSILINK_SQCH0DSC7AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
42301  #define R_DSILINK_SQCH0DSC7AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42302 /* ====================================================  SQCH0DSC0AR_LH  ===================================================== */
42303  #define R_DSILINK_SQCH0DSC0AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
42304  #define R_DSILINK_SQCH0DSC0AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42305 /* ====================================================  SQCH0DSC1AR_LH  ===================================================== */
42306  #define R_DSILINK_SQCH0DSC1AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
42307  #define R_DSILINK_SQCH0DSC1AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42308 /* ====================================================  SQCH0DSC2AR_LH  ===================================================== */
42309  #define R_DSILINK_SQCH0DSC2AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
42310  #define R_DSILINK_SQCH0DSC2AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42311 /* ====================================================  SQCH0DSC3AR_LH  ===================================================== */
42312  #define R_DSILINK_SQCH0DSC3AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
42313  #define R_DSILINK_SQCH0DSC3AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42314 /* ====================================================  SQCH0DSC4AR_LH  ===================================================== */
42315  #define R_DSILINK_SQCH0DSC4AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
42316  #define R_DSILINK_SQCH0DSC4AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42317 /* ====================================================  SQCH0DSC5AR_LH  ===================================================== */
42318  #define R_DSILINK_SQCH0DSC5AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
42319  #define R_DSILINK_SQCH0DSC5AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42320 /* ====================================================  SQCH0DSC6AR_LH  ===================================================== */
42321  #define R_DSILINK_SQCH0DSC6AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
42322  #define R_DSILINK_SQCH0DSC6AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42323 /* ====================================================  SQCH0DSC7AR_LH  ===================================================== */
42324  #define R_DSILINK_SQCH0DSC7AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
42325  #define R_DSILINK_SQCH0DSC7AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42326 /* =====================================================  SQCH0DSC0AR_H  ===================================================== */
42327  #define R_DSILINK_SQCH0DSC0AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
42328  #define R_DSILINK_SQCH0DSC0AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42329  #define R_DSILINK_SQCH0DSC0AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
42330  #define R_DSILINK_SQCH0DSC0AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42331  #define R_DSILINK_SQCH0DSC0AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
42332  #define R_DSILINK_SQCH0DSC0AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
42333  #define R_DSILINK_SQCH0DSC0AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
42334  #define R_DSILINK_SQCH0DSC0AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
42335  #define R_DSILINK_SQCH0DSC0AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
42336  #define R_DSILINK_SQCH0DSC0AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
42337  #define R_DSILINK_SQCH0DSC0AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
42338  #define R_DSILINK_SQCH0DSC0AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
42339 /* =====================================================  SQCH0DSC1AR_H  ===================================================== */
42340  #define R_DSILINK_SQCH0DSC1AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
42341  #define R_DSILINK_SQCH0DSC1AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42342  #define R_DSILINK_SQCH0DSC1AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
42343  #define R_DSILINK_SQCH0DSC1AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42344  #define R_DSILINK_SQCH0DSC1AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
42345  #define R_DSILINK_SQCH0DSC1AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
42346  #define R_DSILINK_SQCH0DSC1AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
42347  #define R_DSILINK_SQCH0DSC1AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
42348  #define R_DSILINK_SQCH0DSC1AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
42349  #define R_DSILINK_SQCH0DSC1AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
42350  #define R_DSILINK_SQCH0DSC1AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
42351  #define R_DSILINK_SQCH0DSC1AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
42352 /* =====================================================  SQCH0DSC2AR_H  ===================================================== */
42353  #define R_DSILINK_SQCH0DSC2AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
42354  #define R_DSILINK_SQCH0DSC2AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42355  #define R_DSILINK_SQCH0DSC2AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
42356  #define R_DSILINK_SQCH0DSC2AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42357  #define R_DSILINK_SQCH0DSC2AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
42358  #define R_DSILINK_SQCH0DSC2AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
42359  #define R_DSILINK_SQCH0DSC2AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
42360  #define R_DSILINK_SQCH0DSC2AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
42361  #define R_DSILINK_SQCH0DSC2AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
42362  #define R_DSILINK_SQCH0DSC2AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
42363  #define R_DSILINK_SQCH0DSC2AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
42364  #define R_DSILINK_SQCH0DSC2AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
42365 /* =====================================================  SQCH0DSC3AR_H  ===================================================== */
42366  #define R_DSILINK_SQCH0DSC3AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
42367  #define R_DSILINK_SQCH0DSC3AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42368  #define R_DSILINK_SQCH0DSC3AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
42369  #define R_DSILINK_SQCH0DSC3AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42370  #define R_DSILINK_SQCH0DSC3AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
42371  #define R_DSILINK_SQCH0DSC3AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
42372  #define R_DSILINK_SQCH0DSC3AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
42373  #define R_DSILINK_SQCH0DSC3AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
42374  #define R_DSILINK_SQCH0DSC3AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
42375  #define R_DSILINK_SQCH0DSC3AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
42376  #define R_DSILINK_SQCH0DSC3AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
42377  #define R_DSILINK_SQCH0DSC3AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
42378 /* =====================================================  SQCH0DSC4AR_H  ===================================================== */
42379  #define R_DSILINK_SQCH0DSC4AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
42380  #define R_DSILINK_SQCH0DSC4AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42381  #define R_DSILINK_SQCH0DSC4AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
42382  #define R_DSILINK_SQCH0DSC4AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42383  #define R_DSILINK_SQCH0DSC4AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
42384  #define R_DSILINK_SQCH0DSC4AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
42385  #define R_DSILINK_SQCH0DSC4AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
42386  #define R_DSILINK_SQCH0DSC4AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
42387  #define R_DSILINK_SQCH0DSC4AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
42388  #define R_DSILINK_SQCH0DSC4AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
42389  #define R_DSILINK_SQCH0DSC4AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
42390  #define R_DSILINK_SQCH0DSC4AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
42391 /* =====================================================  SQCH0DSC5AR_H  ===================================================== */
42392  #define R_DSILINK_SQCH0DSC5AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
42393  #define R_DSILINK_SQCH0DSC5AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42394  #define R_DSILINK_SQCH0DSC5AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
42395  #define R_DSILINK_SQCH0DSC5AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42396  #define R_DSILINK_SQCH0DSC5AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
42397  #define R_DSILINK_SQCH0DSC5AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
42398  #define R_DSILINK_SQCH0DSC5AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
42399  #define R_DSILINK_SQCH0DSC5AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
42400  #define R_DSILINK_SQCH0DSC5AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
42401  #define R_DSILINK_SQCH0DSC5AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
42402  #define R_DSILINK_SQCH0DSC5AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
42403  #define R_DSILINK_SQCH0DSC5AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
42404 /* =====================================================  SQCH0DSC6AR_H  ===================================================== */
42405  #define R_DSILINK_SQCH0DSC6AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
42406  #define R_DSILINK_SQCH0DSC6AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42407  #define R_DSILINK_SQCH0DSC6AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
42408  #define R_DSILINK_SQCH0DSC6AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42409  #define R_DSILINK_SQCH0DSC6AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
42410  #define R_DSILINK_SQCH0DSC6AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
42411  #define R_DSILINK_SQCH0DSC6AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
42412  #define R_DSILINK_SQCH0DSC6AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
42413  #define R_DSILINK_SQCH0DSC6AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
42414  #define R_DSILINK_SQCH0DSC6AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
42415  #define R_DSILINK_SQCH0DSC6AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
42416  #define R_DSILINK_SQCH0DSC6AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
42417 /* =====================================================  SQCH0DSC7AR_H  ===================================================== */
42418  #define R_DSILINK_SQCH0DSC7AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
42419  #define R_DSILINK_SQCH0DSC7AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42420  #define R_DSILINK_SQCH0DSC7AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
42421  #define R_DSILINK_SQCH0DSC7AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42422  #define R_DSILINK_SQCH0DSC7AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
42423  #define R_DSILINK_SQCH0DSC7AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
42424  #define R_DSILINK_SQCH0DSC7AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
42425  #define R_DSILINK_SQCH0DSC7AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
42426  #define R_DSILINK_SQCH0DSC7AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
42427  #define R_DSILINK_SQCH0DSC7AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
42428  #define R_DSILINK_SQCH0DSC7AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
42429  #define R_DSILINK_SQCH0DSC7AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
42430 /* ====================================================  SQCH0DSC0AR_HL  ===================================================== */
42431  #define R_DSILINK_SQCH0DSC0AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
42432  #define R_DSILINK_SQCH0DSC0AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42433  #define R_DSILINK_SQCH0DSC0AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
42434  #define R_DSILINK_SQCH0DSC0AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42435 /* ====================================================  SQCH0DSC1AR_HL  ===================================================== */
42436  #define R_DSILINK_SQCH0DSC1AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
42437  #define R_DSILINK_SQCH0DSC1AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42438  #define R_DSILINK_SQCH0DSC1AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
42439  #define R_DSILINK_SQCH0DSC1AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42440 /* ====================================================  SQCH0DSC2AR_HL  ===================================================== */
42441  #define R_DSILINK_SQCH0DSC2AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
42442  #define R_DSILINK_SQCH0DSC2AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42443  #define R_DSILINK_SQCH0DSC2AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
42444  #define R_DSILINK_SQCH0DSC2AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42445 /* ====================================================  SQCH0DSC3AR_HL  ===================================================== */
42446  #define R_DSILINK_SQCH0DSC3AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
42447  #define R_DSILINK_SQCH0DSC3AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42448  #define R_DSILINK_SQCH0DSC3AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
42449  #define R_DSILINK_SQCH0DSC3AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42450 /* ====================================================  SQCH0DSC4AR_HL  ===================================================== */
42451  #define R_DSILINK_SQCH0DSC4AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
42452  #define R_DSILINK_SQCH0DSC4AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42453  #define R_DSILINK_SQCH0DSC4AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
42454  #define R_DSILINK_SQCH0DSC4AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42455 /* ====================================================  SQCH0DSC5AR_HL  ===================================================== */
42456  #define R_DSILINK_SQCH0DSC5AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
42457  #define R_DSILINK_SQCH0DSC5AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42458  #define R_DSILINK_SQCH0DSC5AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
42459  #define R_DSILINK_SQCH0DSC5AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42460 /* ====================================================  SQCH0DSC6AR_HL  ===================================================== */
42461  #define R_DSILINK_SQCH0DSC6AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
42462  #define R_DSILINK_SQCH0DSC6AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42463  #define R_DSILINK_SQCH0DSC6AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
42464  #define R_DSILINK_SQCH0DSC6AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42465 /* ====================================================  SQCH0DSC7AR_HL  ===================================================== */
42466  #define R_DSILINK_SQCH0DSC7AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
42467  #define R_DSILINK_SQCH0DSC7AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
42468  #define R_DSILINK_SQCH0DSC7AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
42469  #define R_DSILINK_SQCH0DSC7AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
42470 /* ====================================================  SQCH0DSC0AR_HH  ===================================================== */
42471  #define R_DSILINK_SQCH0DSC0AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
42472  #define R_DSILINK_SQCH0DSC0AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
42473  #define R_DSILINK_SQCH0DSC0AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
42474  #define R_DSILINK_SQCH0DSC0AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
42475  #define R_DSILINK_SQCH0DSC0AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
42476  #define R_DSILINK_SQCH0DSC0AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
42477  #define R_DSILINK_SQCH0DSC0AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
42478  #define R_DSILINK_SQCH0DSC0AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
42479 /* ====================================================  SQCH0DSC1AR_HH  ===================================================== */
42480  #define R_DSILINK_SQCH0DSC1AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
42481  #define R_DSILINK_SQCH0DSC1AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
42482  #define R_DSILINK_SQCH0DSC1AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
42483  #define R_DSILINK_SQCH0DSC1AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
42484  #define R_DSILINK_SQCH0DSC1AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
42485  #define R_DSILINK_SQCH0DSC1AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
42486  #define R_DSILINK_SQCH0DSC1AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
42487  #define R_DSILINK_SQCH0DSC1AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
42488 /* ====================================================  SQCH0DSC2AR_HH  ===================================================== */
42489  #define R_DSILINK_SQCH0DSC2AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
42490  #define R_DSILINK_SQCH0DSC2AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
42491  #define R_DSILINK_SQCH0DSC2AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
42492  #define R_DSILINK_SQCH0DSC2AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
42493  #define R_DSILINK_SQCH0DSC2AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
42494  #define R_DSILINK_SQCH0DSC2AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
42495  #define R_DSILINK_SQCH0DSC2AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
42496  #define R_DSILINK_SQCH0DSC2AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
42497 /* ====================================================  SQCH0DSC3AR_HH  ===================================================== */
42498  #define R_DSILINK_SQCH0DSC3AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
42499  #define R_DSILINK_SQCH0DSC3AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
42500  #define R_DSILINK_SQCH0DSC3AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
42501  #define R_DSILINK_SQCH0DSC3AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
42502  #define R_DSILINK_SQCH0DSC3AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
42503  #define R_DSILINK_SQCH0DSC3AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
42504  #define R_DSILINK_SQCH0DSC3AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
42505  #define R_DSILINK_SQCH0DSC3AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
42506 /* ====================================================  SQCH0DSC4AR_HH  ===================================================== */
42507  #define R_DSILINK_SQCH0DSC4AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
42508  #define R_DSILINK_SQCH0DSC4AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
42509  #define R_DSILINK_SQCH0DSC4AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
42510  #define R_DSILINK_SQCH0DSC4AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
42511  #define R_DSILINK_SQCH0DSC4AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
42512  #define R_DSILINK_SQCH0DSC4AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
42513  #define R_DSILINK_SQCH0DSC4AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
42514  #define R_DSILINK_SQCH0DSC4AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
42515 /* ====================================================  SQCH0DSC5AR_HH  ===================================================== */
42516  #define R_DSILINK_SQCH0DSC5AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
42517  #define R_DSILINK_SQCH0DSC5AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
42518  #define R_DSILINK_SQCH0DSC5AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
42519  #define R_DSILINK_SQCH0DSC5AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
42520  #define R_DSILINK_SQCH0DSC5AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
42521  #define R_DSILINK_SQCH0DSC5AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
42522  #define R_DSILINK_SQCH0DSC5AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
42523  #define R_DSILINK_SQCH0DSC5AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
42524 /* ====================================================  SQCH0DSC6AR_HH  ===================================================== */
42525  #define R_DSILINK_SQCH0DSC6AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
42526  #define R_DSILINK_SQCH0DSC6AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
42527  #define R_DSILINK_SQCH0DSC6AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
42528  #define R_DSILINK_SQCH0DSC6AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
42529  #define R_DSILINK_SQCH0DSC6AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
42530  #define R_DSILINK_SQCH0DSC6AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
42531  #define R_DSILINK_SQCH0DSC6AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
42532  #define R_DSILINK_SQCH0DSC6AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
42533 /* ====================================================  SQCH0DSC7AR_HH  ===================================================== */
42534  #define R_DSILINK_SQCH0DSC7AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
42535  #define R_DSILINK_SQCH0DSC7AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
42536  #define R_DSILINK_SQCH0DSC7AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
42537  #define R_DSILINK_SQCH0DSC7AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
42538  #define R_DSILINK_SQCH0DSC7AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
42539  #define R_DSILINK_SQCH0DSC7AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
42540  #define R_DSILINK_SQCH0DSC7AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
42541  #define R_DSILINK_SQCH0DSC7AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
42542 /* ======================================================  SQCH0DSC0BR  ====================================================== */
42543  #define R_DSILINK_SQCH0DSC0BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
42544  #define R_DSILINK_SQCH0DSC0BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
42545 /* ======================================================  SQCH0DSC1BR  ====================================================== */
42546  #define R_DSILINK_SQCH0DSC1BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
42547  #define R_DSILINK_SQCH0DSC1BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
42548 /* ======================================================  SQCH0DSC2BR  ====================================================== */
42549  #define R_DSILINK_SQCH0DSC2BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
42550  #define R_DSILINK_SQCH0DSC2BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
42551 /* ======================================================  SQCH0DSC3BR  ====================================================== */
42552  #define R_DSILINK_SQCH0DSC3BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
42553  #define R_DSILINK_SQCH0DSC3BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
42554 /* ======================================================  SQCH0DSC4BR  ====================================================== */
42555  #define R_DSILINK_SQCH0DSC4BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
42556  #define R_DSILINK_SQCH0DSC4BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
42557 /* ======================================================  SQCH0DSC5BR  ====================================================== */
42558  #define R_DSILINK_SQCH0DSC5BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
42559  #define R_DSILINK_SQCH0DSC5BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
42560 /* ======================================================  SQCH0DSC6BR  ====================================================== */
42561  #define R_DSILINK_SQCH0DSC6BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
42562  #define R_DSILINK_SQCH0DSC6BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
42563 /* ======================================================  SQCH0DSC7BR  ====================================================== */
42564  #define R_DSILINK_SQCH0DSC7BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
42565  #define R_DSILINK_SQCH0DSC7BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
42566 /* ======================================================  SQCH0DSC0CR  ====================================================== */
42567  #define R_DSILINK_SQCH0DSC0CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
42568  #define R_DSILINK_SQCH0DSC0CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42569  #define R_DSILINK_SQCH0DSC0CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
42570  #define R_DSILINK_SQCH0DSC0CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42571  #define R_DSILINK_SQCH0DSC0CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
42572  #define R_DSILINK_SQCH0DSC0CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42573 /* ======================================================  SQCH0DSC1CR  ====================================================== */
42574  #define R_DSILINK_SQCH0DSC1CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
42575  #define R_DSILINK_SQCH0DSC1CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42576  #define R_DSILINK_SQCH0DSC1CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
42577  #define R_DSILINK_SQCH0DSC1CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42578  #define R_DSILINK_SQCH0DSC1CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
42579  #define R_DSILINK_SQCH0DSC1CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42580 /* ======================================================  SQCH0DSC2CR  ====================================================== */
42581  #define R_DSILINK_SQCH0DSC2CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
42582  #define R_DSILINK_SQCH0DSC2CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42583  #define R_DSILINK_SQCH0DSC2CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
42584  #define R_DSILINK_SQCH0DSC2CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42585  #define R_DSILINK_SQCH0DSC2CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
42586  #define R_DSILINK_SQCH0DSC2CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42587 /* ======================================================  SQCH0DSC3CR  ====================================================== */
42588  #define R_DSILINK_SQCH0DSC3CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
42589  #define R_DSILINK_SQCH0DSC3CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42590  #define R_DSILINK_SQCH0DSC3CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
42591  #define R_DSILINK_SQCH0DSC3CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42592  #define R_DSILINK_SQCH0DSC3CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
42593  #define R_DSILINK_SQCH0DSC3CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42594 /* ======================================================  SQCH0DSC4CR  ====================================================== */
42595  #define R_DSILINK_SQCH0DSC4CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
42596  #define R_DSILINK_SQCH0DSC4CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42597  #define R_DSILINK_SQCH0DSC4CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
42598  #define R_DSILINK_SQCH0DSC4CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42599  #define R_DSILINK_SQCH0DSC4CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
42600  #define R_DSILINK_SQCH0DSC4CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42601 /* ======================================================  SQCH0DSC5CR  ====================================================== */
42602  #define R_DSILINK_SQCH0DSC5CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
42603  #define R_DSILINK_SQCH0DSC5CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42604  #define R_DSILINK_SQCH0DSC5CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
42605  #define R_DSILINK_SQCH0DSC5CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42606  #define R_DSILINK_SQCH0DSC5CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
42607  #define R_DSILINK_SQCH0DSC5CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42608 /* ======================================================  SQCH0DSC6CR  ====================================================== */
42609  #define R_DSILINK_SQCH0DSC6CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
42610  #define R_DSILINK_SQCH0DSC6CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42611  #define R_DSILINK_SQCH0DSC6CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
42612  #define R_DSILINK_SQCH0DSC6CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42613  #define R_DSILINK_SQCH0DSC6CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
42614  #define R_DSILINK_SQCH0DSC6CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42615 /* ======================================================  SQCH0DSC7CR  ====================================================== */
42616  #define R_DSILINK_SQCH0DSC7CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
42617  #define R_DSILINK_SQCH0DSC7CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42618  #define R_DSILINK_SQCH0DSC7CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
42619  #define R_DSILINK_SQCH0DSC7CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42620  #define R_DSILINK_SQCH0DSC7CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
42621  #define R_DSILINK_SQCH0DSC7CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42622 /* =====================================================  SQCH0DSC0CR_L  ===================================================== */
42623  #define R_DSILINK_SQCH0DSC0CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
42624  #define R_DSILINK_SQCH0DSC0CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42625 /* =====================================================  SQCH0DSC1CR_L  ===================================================== */
42626  #define R_DSILINK_SQCH0DSC1CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
42627  #define R_DSILINK_SQCH0DSC1CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42628 /* =====================================================  SQCH0DSC2CR_L  ===================================================== */
42629  #define R_DSILINK_SQCH0DSC2CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
42630  #define R_DSILINK_SQCH0DSC2CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42631 /* =====================================================  SQCH0DSC3CR_L  ===================================================== */
42632  #define R_DSILINK_SQCH0DSC3CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
42633  #define R_DSILINK_SQCH0DSC3CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42634 /* =====================================================  SQCH0DSC4CR_L  ===================================================== */
42635  #define R_DSILINK_SQCH0DSC4CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
42636  #define R_DSILINK_SQCH0DSC4CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42637 /* =====================================================  SQCH0DSC5CR_L  ===================================================== */
42638  #define R_DSILINK_SQCH0DSC5CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
42639  #define R_DSILINK_SQCH0DSC5CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42640 /* =====================================================  SQCH0DSC6CR_L  ===================================================== */
42641  #define R_DSILINK_SQCH0DSC6CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
42642  #define R_DSILINK_SQCH0DSC6CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42643 /* =====================================================  SQCH0DSC7CR_L  ===================================================== */
42644  #define R_DSILINK_SQCH0DSC7CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
42645  #define R_DSILINK_SQCH0DSC7CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42646 /* ====================================================  SQCH0DSC0CR_LL  ===================================================== */
42647  #define R_DSILINK_SQCH0DSC0CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
42648  #define R_DSILINK_SQCH0DSC0CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42649 /* ====================================================  SQCH0DSC1CR_LL  ===================================================== */
42650  #define R_DSILINK_SQCH0DSC1CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
42651  #define R_DSILINK_SQCH0DSC1CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42652 /* ====================================================  SQCH0DSC2CR_LL  ===================================================== */
42653  #define R_DSILINK_SQCH0DSC2CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
42654  #define R_DSILINK_SQCH0DSC2CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42655 /* ====================================================  SQCH0DSC3CR_LL  ===================================================== */
42656  #define R_DSILINK_SQCH0DSC3CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
42657  #define R_DSILINK_SQCH0DSC3CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42658 /* ====================================================  SQCH0DSC4CR_LL  ===================================================== */
42659  #define R_DSILINK_SQCH0DSC4CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
42660  #define R_DSILINK_SQCH0DSC4CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42661 /* ====================================================  SQCH0DSC5CR_LL  ===================================================== */
42662  #define R_DSILINK_SQCH0DSC5CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
42663  #define R_DSILINK_SQCH0DSC5CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42664 /* ====================================================  SQCH0DSC6CR_LL  ===================================================== */
42665  #define R_DSILINK_SQCH0DSC6CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
42666  #define R_DSILINK_SQCH0DSC6CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42667 /* ====================================================  SQCH0DSC7CR_LL  ===================================================== */
42668  #define R_DSILINK_SQCH0DSC7CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
42669  #define R_DSILINK_SQCH0DSC7CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
42670 /* =====================================================  SQCH0DSC0CR_H  ===================================================== */
42671  #define R_DSILINK_SQCH0DSC0CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
42672  #define R_DSILINK_SQCH0DSC0CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42673  #define R_DSILINK_SQCH0DSC0CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
42674  #define R_DSILINK_SQCH0DSC0CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42675 /* =====================================================  SQCH0DSC1CR_H  ===================================================== */
42676  #define R_DSILINK_SQCH0DSC1CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
42677  #define R_DSILINK_SQCH0DSC1CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42678  #define R_DSILINK_SQCH0DSC1CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
42679  #define R_DSILINK_SQCH0DSC1CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42680 /* =====================================================  SQCH0DSC2CR_H  ===================================================== */
42681  #define R_DSILINK_SQCH0DSC2CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
42682  #define R_DSILINK_SQCH0DSC2CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42683  #define R_DSILINK_SQCH0DSC2CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
42684  #define R_DSILINK_SQCH0DSC2CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42685 /* =====================================================  SQCH0DSC3CR_H  ===================================================== */
42686  #define R_DSILINK_SQCH0DSC3CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
42687  #define R_DSILINK_SQCH0DSC3CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42688  #define R_DSILINK_SQCH0DSC3CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
42689  #define R_DSILINK_SQCH0DSC3CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42690 /* =====================================================  SQCH0DSC4CR_H  ===================================================== */
42691  #define R_DSILINK_SQCH0DSC4CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
42692  #define R_DSILINK_SQCH0DSC4CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42693  #define R_DSILINK_SQCH0DSC4CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
42694  #define R_DSILINK_SQCH0DSC4CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42695 /* =====================================================  SQCH0DSC5CR_H  ===================================================== */
42696  #define R_DSILINK_SQCH0DSC5CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
42697  #define R_DSILINK_SQCH0DSC5CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42698  #define R_DSILINK_SQCH0DSC5CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
42699  #define R_DSILINK_SQCH0DSC5CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42700 /* =====================================================  SQCH0DSC6CR_H  ===================================================== */
42701  #define R_DSILINK_SQCH0DSC6CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
42702  #define R_DSILINK_SQCH0DSC6CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42703  #define R_DSILINK_SQCH0DSC6CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
42704  #define R_DSILINK_SQCH0DSC6CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42705 /* =====================================================  SQCH0DSC7CR_H  ===================================================== */
42706  #define R_DSILINK_SQCH0DSC7CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
42707  #define R_DSILINK_SQCH0DSC7CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42708  #define R_DSILINK_SQCH0DSC7CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
42709  #define R_DSILINK_SQCH0DSC7CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42710 /* ====================================================  SQCH0DSC0CR_HL  ===================================================== */
42711  #define R_DSILINK_SQCH0DSC0CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
42712  #define R_DSILINK_SQCH0DSC0CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42713 /* ====================================================  SQCH0DSC1CR_HL  ===================================================== */
42714  #define R_DSILINK_SQCH0DSC1CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
42715  #define R_DSILINK_SQCH0DSC1CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42716 /* ====================================================  SQCH0DSC2CR_HL  ===================================================== */
42717  #define R_DSILINK_SQCH0DSC2CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
42718  #define R_DSILINK_SQCH0DSC2CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42719 /* ====================================================  SQCH0DSC3CR_HL  ===================================================== */
42720  #define R_DSILINK_SQCH0DSC3CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
42721  #define R_DSILINK_SQCH0DSC3CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42722 /* ====================================================  SQCH0DSC4CR_HL  ===================================================== */
42723  #define R_DSILINK_SQCH0DSC4CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
42724  #define R_DSILINK_SQCH0DSC4CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42725 /* ====================================================  SQCH0DSC5CR_HL  ===================================================== */
42726  #define R_DSILINK_SQCH0DSC5CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
42727  #define R_DSILINK_SQCH0DSC5CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42728 /* ====================================================  SQCH0DSC6CR_HL  ===================================================== */
42729  #define R_DSILINK_SQCH0DSC6CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
42730  #define R_DSILINK_SQCH0DSC6CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42731 /* ====================================================  SQCH0DSC7CR_HL  ===================================================== */
42732  #define R_DSILINK_SQCH0DSC7CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
42733  #define R_DSILINK_SQCH0DSC7CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
42734 /* ====================================================  SQCH0DSC0CR_HH  ===================================================== */
42735  #define R_DSILINK_SQCH0DSC0CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
42736  #define R_DSILINK_SQCH0DSC0CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42737 /* ====================================================  SQCH0DSC1CR_HH  ===================================================== */
42738  #define R_DSILINK_SQCH0DSC1CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
42739  #define R_DSILINK_SQCH0DSC1CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42740 /* ====================================================  SQCH0DSC2CR_HH  ===================================================== */
42741  #define R_DSILINK_SQCH0DSC2CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
42742  #define R_DSILINK_SQCH0DSC2CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42743 /* ====================================================  SQCH0DSC3CR_HH  ===================================================== */
42744  #define R_DSILINK_SQCH0DSC3CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
42745  #define R_DSILINK_SQCH0DSC3CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42746 /* ====================================================  SQCH0DSC4CR_HH  ===================================================== */
42747  #define R_DSILINK_SQCH0DSC4CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
42748  #define R_DSILINK_SQCH0DSC4CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42749 /* ====================================================  SQCH0DSC5CR_HH  ===================================================== */
42750  #define R_DSILINK_SQCH0DSC5CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
42751  #define R_DSILINK_SQCH0DSC5CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42752 /* ====================================================  SQCH0DSC6CR_HH  ===================================================== */
42753  #define R_DSILINK_SQCH0DSC6CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
42754  #define R_DSILINK_SQCH0DSC6CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42755 /* ====================================================  SQCH0DSC7CR_HH  ===================================================== */
42756  #define R_DSILINK_SQCH0DSC7CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
42757  #define R_DSILINK_SQCH0DSC7CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
42758 /* ======================================================  SQCH0DSC0DR  ====================================================== */
42759  #define R_DSILINK_SQCH0DSC0DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
42760  #define R_DSILINK_SQCH0DSC0DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
42761 /* ======================================================  SQCH0DSC1DR  ====================================================== */
42762  #define R_DSILINK_SQCH0DSC1DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
42763  #define R_DSILINK_SQCH0DSC1DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
42764 /* ======================================================  SQCH0DSC2DR  ====================================================== */
42765  #define R_DSILINK_SQCH0DSC2DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
42766  #define R_DSILINK_SQCH0DSC2DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
42767 /* ======================================================  SQCH0DSC3DR  ====================================================== */
42768  #define R_DSILINK_SQCH0DSC3DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
42769  #define R_DSILINK_SQCH0DSC3DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
42770 /* ======================================================  SQCH0DSC4DR  ====================================================== */
42771  #define R_DSILINK_SQCH0DSC4DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
42772  #define R_DSILINK_SQCH0DSC4DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
42773 /* ======================================================  SQCH0DSC5DR  ====================================================== */
42774  #define R_DSILINK_SQCH0DSC5DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
42775  #define R_DSILINK_SQCH0DSC5DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
42776 /* ======================================================  SQCH0DSC6DR  ====================================================== */
42777  #define R_DSILINK_SQCH0DSC6DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
42778  #define R_DSILINK_SQCH0DSC6DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
42779 /* ======================================================  SQCH0DSC7DR  ====================================================== */
42780  #define R_DSILINK_SQCH0DSC7DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
42781  #define R_DSILINK_SQCH0DSC7DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
42782 /* =====================================================  SQCH0DSC0DR_L  ===================================================== */
42783  #define R_DSILINK_SQCH0DSC0DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42784  #define R_DSILINK_SQCH0DSC0DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42785 /* =====================================================  SQCH0DSC1DR_L  ===================================================== */
42786  #define R_DSILINK_SQCH0DSC1DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42787  #define R_DSILINK_SQCH0DSC1DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42788 /* =====================================================  SQCH0DSC2DR_L  ===================================================== */
42789  #define R_DSILINK_SQCH0DSC2DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42790  #define R_DSILINK_SQCH0DSC2DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42791 /* =====================================================  SQCH0DSC3DR_L  ===================================================== */
42792  #define R_DSILINK_SQCH0DSC3DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42793  #define R_DSILINK_SQCH0DSC3DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42794 /* =====================================================  SQCH0DSC4DR_L  ===================================================== */
42795  #define R_DSILINK_SQCH0DSC4DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42796  #define R_DSILINK_SQCH0DSC4DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42797 /* =====================================================  SQCH0DSC5DR_L  ===================================================== */
42798  #define R_DSILINK_SQCH0DSC5DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42799  #define R_DSILINK_SQCH0DSC5DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42800 /* =====================================================  SQCH0DSC6DR_L  ===================================================== */
42801  #define R_DSILINK_SQCH0DSC6DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42802  #define R_DSILINK_SQCH0DSC6DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42803 /* =====================================================  SQCH0DSC7DR_L  ===================================================== */
42804  #define R_DSILINK_SQCH0DSC7DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42805  #define R_DSILINK_SQCH0DSC7DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42806 /* ====================================================  SQCH0DSC0DR_LL  ===================================================== */
42807  #define R_DSILINK_SQCH0DSC0DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42808  #define R_DSILINK_SQCH0DSC0DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42809 /* ====================================================  SQCH0DSC1DR_LL  ===================================================== */
42810  #define R_DSILINK_SQCH0DSC1DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42811  #define R_DSILINK_SQCH0DSC1DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42812 /* ====================================================  SQCH0DSC2DR_LL  ===================================================== */
42813  #define R_DSILINK_SQCH0DSC2DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42814  #define R_DSILINK_SQCH0DSC2DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42815 /* ====================================================  SQCH0DSC3DR_LL  ===================================================== */
42816  #define R_DSILINK_SQCH0DSC3DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42817  #define R_DSILINK_SQCH0DSC3DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42818 /* ====================================================  SQCH0DSC4DR_LL  ===================================================== */
42819  #define R_DSILINK_SQCH0DSC4DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42820  #define R_DSILINK_SQCH0DSC4DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42821 /* ====================================================  SQCH0DSC5DR_LL  ===================================================== */
42822  #define R_DSILINK_SQCH0DSC5DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42823  #define R_DSILINK_SQCH0DSC5DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42824 /* ====================================================  SQCH0DSC6DR_LL  ===================================================== */
42825  #define R_DSILINK_SQCH0DSC6DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42826  #define R_DSILINK_SQCH0DSC6DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42827 /* ====================================================  SQCH0DSC7DR_LL  ===================================================== */
42828  #define R_DSILINK_SQCH0DSC7DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42829  #define R_DSILINK_SQCH0DSC7DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42830 /* ====================================================  SQCH0DSC0DR_LH  ===================================================== */
42831  #define R_DSILINK_SQCH0DSC0DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42832  #define R_DSILINK_SQCH0DSC0DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42833 /* ====================================================  SQCH0DSC1DR_LH  ===================================================== */
42834  #define R_DSILINK_SQCH0DSC1DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42835  #define R_DSILINK_SQCH0DSC1DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42836 /* ====================================================  SQCH0DSC2DR_LH  ===================================================== */
42837  #define R_DSILINK_SQCH0DSC2DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42838  #define R_DSILINK_SQCH0DSC2DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42839 /* ====================================================  SQCH0DSC3DR_LH  ===================================================== */
42840  #define R_DSILINK_SQCH0DSC3DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42841  #define R_DSILINK_SQCH0DSC3DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42842 /* ====================================================  SQCH0DSC4DR_LH  ===================================================== */
42843  #define R_DSILINK_SQCH0DSC4DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42844  #define R_DSILINK_SQCH0DSC4DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42845 /* ====================================================  SQCH0DSC5DR_LH  ===================================================== */
42846  #define R_DSILINK_SQCH0DSC5DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42847  #define R_DSILINK_SQCH0DSC5DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42848 /* ====================================================  SQCH0DSC6DR_LH  ===================================================== */
42849  #define R_DSILINK_SQCH0DSC6DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42850  #define R_DSILINK_SQCH0DSC6DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42851 /* ====================================================  SQCH0DSC7DR_LH  ===================================================== */
42852  #define R_DSILINK_SQCH0DSC7DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42853  #define R_DSILINK_SQCH0DSC7DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42854 /* =====================================================  SQCH0DSC0DR_H  ===================================================== */
42855  #define R_DSILINK_SQCH0DSC0DR_H_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42856  #define R_DSILINK_SQCH0DSC0DR_H_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42857 /* =====================================================  SQCH0DSC1DR_H  ===================================================== */
42858  #define R_DSILINK_SQCH0DSC1DR_H_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42859  #define R_DSILINK_SQCH0DSC1DR_H_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42860 /* =====================================================  SQCH0DSC2DR_H  ===================================================== */
42861  #define R_DSILINK_SQCH0DSC2DR_H_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42862  #define R_DSILINK_SQCH0DSC2DR_H_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42863 /* =====================================================  SQCH0DSC3DR_H  ===================================================== */
42864  #define R_DSILINK_SQCH0DSC3DR_H_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42865  #define R_DSILINK_SQCH0DSC3DR_H_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42866 /* =====================================================  SQCH0DSC4DR_H  ===================================================== */
42867  #define R_DSILINK_SQCH0DSC4DR_H_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42868  #define R_DSILINK_SQCH0DSC4DR_H_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42869 /* =====================================================  SQCH0DSC5DR_H  ===================================================== */
42870  #define R_DSILINK_SQCH0DSC5DR_H_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42871  #define R_DSILINK_SQCH0DSC5DR_H_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42872 /* =====================================================  SQCH0DSC6DR_H  ===================================================== */
42873  #define R_DSILINK_SQCH0DSC6DR_H_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42874  #define R_DSILINK_SQCH0DSC6DR_H_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42875 /* =====================================================  SQCH0DSC7DR_H  ===================================================== */
42876  #define R_DSILINK_SQCH0DSC7DR_H_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
42877  #define R_DSILINK_SQCH0DSC7DR_H_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
42878 /* ====================================================  SQCH0DSC0DR_HL  ===================================================== */
42879  #define R_DSILINK_SQCH0DSC0DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42880  #define R_DSILINK_SQCH0DSC0DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42881 /* ====================================================  SQCH0DSC1DR_HL  ===================================================== */
42882  #define R_DSILINK_SQCH0DSC1DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42883  #define R_DSILINK_SQCH0DSC1DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42884 /* ====================================================  SQCH0DSC2DR_HL  ===================================================== */
42885  #define R_DSILINK_SQCH0DSC2DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42886  #define R_DSILINK_SQCH0DSC2DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42887 /* ====================================================  SQCH0DSC3DR_HL  ===================================================== */
42888  #define R_DSILINK_SQCH0DSC3DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42889  #define R_DSILINK_SQCH0DSC3DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42890 /* ====================================================  SQCH0DSC4DR_HL  ===================================================== */
42891  #define R_DSILINK_SQCH0DSC4DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42892  #define R_DSILINK_SQCH0DSC4DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42893 /* ====================================================  SQCH0DSC5DR_HL  ===================================================== */
42894  #define R_DSILINK_SQCH0DSC5DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42895  #define R_DSILINK_SQCH0DSC5DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42896 /* ====================================================  SQCH0DSC6DR_HL  ===================================================== */
42897  #define R_DSILINK_SQCH0DSC6DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42898  #define R_DSILINK_SQCH0DSC6DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42899 /* ====================================================  SQCH0DSC7DR_HL  ===================================================== */
42900  #define R_DSILINK_SQCH0DSC7DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42901  #define R_DSILINK_SQCH0DSC7DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42902 /* ====================================================  SQCH0DSC0DR_HH  ===================================================== */
42903  #define R_DSILINK_SQCH0DSC0DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42904  #define R_DSILINK_SQCH0DSC0DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42905 /* ====================================================  SQCH0DSC1DR_HH  ===================================================== */
42906  #define R_DSILINK_SQCH0DSC1DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42907  #define R_DSILINK_SQCH0DSC1DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42908 /* ====================================================  SQCH0DSC2DR_HH  ===================================================== */
42909  #define R_DSILINK_SQCH0DSC2DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42910  #define R_DSILINK_SQCH0DSC2DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42911 /* ====================================================  SQCH0DSC3DR_HH  ===================================================== */
42912  #define R_DSILINK_SQCH0DSC3DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42913  #define R_DSILINK_SQCH0DSC3DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42914 /* ====================================================  SQCH0DSC4DR_HH  ===================================================== */
42915  #define R_DSILINK_SQCH0DSC4DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42916  #define R_DSILINK_SQCH0DSC4DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42917 /* ====================================================  SQCH0DSC5DR_HH  ===================================================== */
42918  #define R_DSILINK_SQCH0DSC5DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42919  #define R_DSILINK_SQCH0DSC5DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42920 /* ====================================================  SQCH0DSC6DR_HH  ===================================================== */
42921  #define R_DSILINK_SQCH0DSC6DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42922  #define R_DSILINK_SQCH0DSC6DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42923 /* ====================================================  SQCH0DSC7DR_HH  ===================================================== */
42924  #define R_DSILINK_SQCH0DSC7DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
42925  #define R_DSILINK_SQCH0DSC7DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
42926 /* ======================================================  SQCH1DSC0AR  ====================================================== */
42927  #define R_DSILINK_SQCH1DSC0AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42928  #define R_DSILINK_SQCH1DSC0AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42929  #define R_DSILINK_SQCH1DSC0AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42930  #define R_DSILINK_SQCH1DSC0AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42931  #define R_DSILINK_SQCH1DSC0AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42932  #define R_DSILINK_SQCH1DSC0AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42933  #define R_DSILINK_SQCH1DSC0AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42934  #define R_DSILINK_SQCH1DSC0AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42935  #define R_DSILINK_SQCH1DSC0AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42936  #define R_DSILINK_SQCH1DSC0AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42937  #define R_DSILINK_SQCH1DSC0AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42938  #define R_DSILINK_SQCH1DSC0AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42939  #define R_DSILINK_SQCH1DSC0AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42940  #define R_DSILINK_SQCH1DSC0AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42941  #define R_DSILINK_SQCH1DSC0AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42942  #define R_DSILINK_SQCH1DSC0AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42943 /* ======================================================  SQCH1DSC1AR  ====================================================== */
42944  #define R_DSILINK_SQCH1DSC1AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42945  #define R_DSILINK_SQCH1DSC1AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42946  #define R_DSILINK_SQCH1DSC1AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42947  #define R_DSILINK_SQCH1DSC1AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42948  #define R_DSILINK_SQCH1DSC1AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42949  #define R_DSILINK_SQCH1DSC1AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42950  #define R_DSILINK_SQCH1DSC1AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42951  #define R_DSILINK_SQCH1DSC1AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42952  #define R_DSILINK_SQCH1DSC1AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42953  #define R_DSILINK_SQCH1DSC1AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42954  #define R_DSILINK_SQCH1DSC1AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42955  #define R_DSILINK_SQCH1DSC1AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42956  #define R_DSILINK_SQCH1DSC1AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42957  #define R_DSILINK_SQCH1DSC1AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42958  #define R_DSILINK_SQCH1DSC1AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42959  #define R_DSILINK_SQCH1DSC1AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42960 /* ======================================================  SQCH1DSC2AR  ====================================================== */
42961  #define R_DSILINK_SQCH1DSC2AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42962  #define R_DSILINK_SQCH1DSC2AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42963  #define R_DSILINK_SQCH1DSC2AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42964  #define R_DSILINK_SQCH1DSC2AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42965  #define R_DSILINK_SQCH1DSC2AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42966  #define R_DSILINK_SQCH1DSC2AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42967  #define R_DSILINK_SQCH1DSC2AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42968  #define R_DSILINK_SQCH1DSC2AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42969  #define R_DSILINK_SQCH1DSC2AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42970  #define R_DSILINK_SQCH1DSC2AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42971  #define R_DSILINK_SQCH1DSC2AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42972  #define R_DSILINK_SQCH1DSC2AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42973  #define R_DSILINK_SQCH1DSC2AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42974  #define R_DSILINK_SQCH1DSC2AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42975  #define R_DSILINK_SQCH1DSC2AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42976  #define R_DSILINK_SQCH1DSC2AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42977 /* ======================================================  SQCH1DSC3AR  ====================================================== */
42978  #define R_DSILINK_SQCH1DSC3AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42979  #define R_DSILINK_SQCH1DSC3AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42980  #define R_DSILINK_SQCH1DSC3AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42981  #define R_DSILINK_SQCH1DSC3AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42982  #define R_DSILINK_SQCH1DSC3AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
42983  #define R_DSILINK_SQCH1DSC3AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
42984  #define R_DSILINK_SQCH1DSC3AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
42985  #define R_DSILINK_SQCH1DSC3AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
42986  #define R_DSILINK_SQCH1DSC3AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
42987  #define R_DSILINK_SQCH1DSC3AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
42988  #define R_DSILINK_SQCH1DSC3AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
42989  #define R_DSILINK_SQCH1DSC3AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
42990  #define R_DSILINK_SQCH1DSC3AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
42991  #define R_DSILINK_SQCH1DSC3AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
42992  #define R_DSILINK_SQCH1DSC3AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
42993  #define R_DSILINK_SQCH1DSC3AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
42994 /* ======================================================  SQCH1DSC4AR  ====================================================== */
42995  #define R_DSILINK_SQCH1DSC4AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
42996  #define R_DSILINK_SQCH1DSC4AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
42997  #define R_DSILINK_SQCH1DSC4AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
42998  #define R_DSILINK_SQCH1DSC4AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
42999  #define R_DSILINK_SQCH1DSC4AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
43000  #define R_DSILINK_SQCH1DSC4AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
43001  #define R_DSILINK_SQCH1DSC4AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
43002  #define R_DSILINK_SQCH1DSC4AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
43003  #define R_DSILINK_SQCH1DSC4AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
43004  #define R_DSILINK_SQCH1DSC4AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
43005  #define R_DSILINK_SQCH1DSC4AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
43006  #define R_DSILINK_SQCH1DSC4AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
43007  #define R_DSILINK_SQCH1DSC4AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
43008  #define R_DSILINK_SQCH1DSC4AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
43009  #define R_DSILINK_SQCH1DSC4AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
43010  #define R_DSILINK_SQCH1DSC4AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
43011 /* ======================================================  SQCH1DSC5AR  ====================================================== */
43012  #define R_DSILINK_SQCH1DSC5AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
43013  #define R_DSILINK_SQCH1DSC5AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43014  #define R_DSILINK_SQCH1DSC5AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
43015  #define R_DSILINK_SQCH1DSC5AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43016  #define R_DSILINK_SQCH1DSC5AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
43017  #define R_DSILINK_SQCH1DSC5AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
43018  #define R_DSILINK_SQCH1DSC5AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
43019  #define R_DSILINK_SQCH1DSC5AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
43020  #define R_DSILINK_SQCH1DSC5AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
43021  #define R_DSILINK_SQCH1DSC5AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
43022  #define R_DSILINK_SQCH1DSC5AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
43023  #define R_DSILINK_SQCH1DSC5AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
43024  #define R_DSILINK_SQCH1DSC5AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
43025  #define R_DSILINK_SQCH1DSC5AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
43026  #define R_DSILINK_SQCH1DSC5AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
43027  #define R_DSILINK_SQCH1DSC5AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
43028 /* ======================================================  SQCH1DSC6AR  ====================================================== */
43029  #define R_DSILINK_SQCH1DSC6AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
43030  #define R_DSILINK_SQCH1DSC6AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43031  #define R_DSILINK_SQCH1DSC6AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
43032  #define R_DSILINK_SQCH1DSC6AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43033  #define R_DSILINK_SQCH1DSC6AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
43034  #define R_DSILINK_SQCH1DSC6AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
43035  #define R_DSILINK_SQCH1DSC6AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
43036  #define R_DSILINK_SQCH1DSC6AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
43037  #define R_DSILINK_SQCH1DSC6AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
43038  #define R_DSILINK_SQCH1DSC6AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
43039  #define R_DSILINK_SQCH1DSC6AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
43040  #define R_DSILINK_SQCH1DSC6AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
43041  #define R_DSILINK_SQCH1DSC6AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
43042  #define R_DSILINK_SQCH1DSC6AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
43043  #define R_DSILINK_SQCH1DSC6AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
43044  #define R_DSILINK_SQCH1DSC6AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
43045 /* ======================================================  SQCH1DSC7AR  ====================================================== */
43046  #define R_DSILINK_SQCH1DSC7AR_DATA0_Pos         (0UL)          /*!< DATA0 (Bit 0)                                         */
43047  #define R_DSILINK_SQCH1DSC7AR_DATA0_Msk         (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43048  #define R_DSILINK_SQCH1DSC7AR_DATA1_Pos         (8UL)          /*!< DATA1 (Bit 8)                                         */
43049  #define R_DSILINK_SQCH1DSC7AR_DATA1_Msk         (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43050  #define R_DSILINK_SQCH1DSC7AR_DT_Pos            (16UL)         /*!< DT (Bit 16)                                           */
43051  #define R_DSILINK_SQCH1DSC7AR_DT_Msk            (0x3f0000UL)   /*!< DT (Bitfield-Mask: 0x3f)                              */
43052  #define R_DSILINK_SQCH1DSC7AR_VC_Pos            (22UL)         /*!< VC (Bit 22)                                           */
43053  #define R_DSILINK_SQCH1DSC7AR_VC_Msk            (0xc00000UL)   /*!< VC (Bitfield-Mask: 0x03)                              */
43054  #define R_DSILINK_SQCH1DSC7AR_FMT_Pos           (24UL)         /*!< FMT (Bit 24)                                          */
43055  #define R_DSILINK_SQCH1DSC7AR_FMT_Msk           (0x1000000UL)  /*!< FMT (Bitfield-Mask: 0x01)                             */
43056  #define R_DSILINK_SQCH1DSC7AR_SPD_Pos           (25UL)         /*!< SPD (Bit 25)                                          */
43057  #define R_DSILINK_SQCH1DSC7AR_SPD_Msk           (0x2000000UL)  /*!< SPD (Bitfield-Mask: 0x01)                             */
43058  #define R_DSILINK_SQCH1DSC7AR_BTA_Pos           (26UL)         /*!< BTA (Bit 26)                                          */
43059  #define R_DSILINK_SQCH1DSC7AR_BTA_Msk           (0xc000000UL)  /*!< BTA (Bitfield-Mask: 0x03)                             */
43060  #define R_DSILINK_SQCH1DSC7AR_NXACT_Pos         (28UL)         /*!< NXACT (Bit 28)                                        */
43061  #define R_DSILINK_SQCH1DSC7AR_NXACT_Msk         (0x30000000UL) /*!< NXACT (Bitfield-Mask: 0x03)                           */
43062 /* =====================================================  SQCH1DSC0AR_L  ===================================================== */
43063  #define R_DSILINK_SQCH1DSC0AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
43064  #define R_DSILINK_SQCH1DSC0AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43065  #define R_DSILINK_SQCH1DSC0AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
43066  #define R_DSILINK_SQCH1DSC0AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43067 /* =====================================================  SQCH1DSC1AR_L  ===================================================== */
43068  #define R_DSILINK_SQCH1DSC1AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
43069  #define R_DSILINK_SQCH1DSC1AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43070  #define R_DSILINK_SQCH1DSC1AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
43071  #define R_DSILINK_SQCH1DSC1AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43072 /* =====================================================  SQCH1DSC2AR_L  ===================================================== */
43073  #define R_DSILINK_SQCH1DSC2AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
43074  #define R_DSILINK_SQCH1DSC2AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43075  #define R_DSILINK_SQCH1DSC2AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
43076  #define R_DSILINK_SQCH1DSC2AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43077 /* =====================================================  SQCH1DSC3AR_L  ===================================================== */
43078  #define R_DSILINK_SQCH1DSC3AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
43079  #define R_DSILINK_SQCH1DSC3AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43080  #define R_DSILINK_SQCH1DSC3AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
43081  #define R_DSILINK_SQCH1DSC3AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43082 /* =====================================================  SQCH1DSC4AR_L  ===================================================== */
43083  #define R_DSILINK_SQCH1DSC4AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
43084  #define R_DSILINK_SQCH1DSC4AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43085  #define R_DSILINK_SQCH1DSC4AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
43086  #define R_DSILINK_SQCH1DSC4AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43087 /* =====================================================  SQCH1DSC5AR_L  ===================================================== */
43088  #define R_DSILINK_SQCH1DSC5AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
43089  #define R_DSILINK_SQCH1DSC5AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43090  #define R_DSILINK_SQCH1DSC5AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
43091  #define R_DSILINK_SQCH1DSC5AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43092 /* =====================================================  SQCH1DSC6AR_L  ===================================================== */
43093  #define R_DSILINK_SQCH1DSC6AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
43094  #define R_DSILINK_SQCH1DSC6AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43095  #define R_DSILINK_SQCH1DSC6AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
43096  #define R_DSILINK_SQCH1DSC6AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43097 /* =====================================================  SQCH1DSC7AR_L  ===================================================== */
43098  #define R_DSILINK_SQCH1DSC7AR_L_DATA0_Pos       (0UL)          /*!< DATA0 (Bit 0)                                         */
43099  #define R_DSILINK_SQCH1DSC7AR_L_DATA0_Msk       (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43100  #define R_DSILINK_SQCH1DSC7AR_L_DATA1_Pos       (8UL)          /*!< DATA1 (Bit 8)                                         */
43101  #define R_DSILINK_SQCH1DSC7AR_L_DATA1_Msk       (0xff00UL)     /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43102 /* ====================================================  SQCH1DSC0AR_LL  ===================================================== */
43103  #define R_DSILINK_SQCH1DSC0AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
43104  #define R_DSILINK_SQCH1DSC0AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43105 /* ====================================================  SQCH1DSC1AR_LL  ===================================================== */
43106  #define R_DSILINK_SQCH1DSC1AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
43107  #define R_DSILINK_SQCH1DSC1AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43108 /* ====================================================  SQCH1DSC2AR_LL  ===================================================== */
43109  #define R_DSILINK_SQCH1DSC2AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
43110  #define R_DSILINK_SQCH1DSC2AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43111 /* ====================================================  SQCH1DSC3AR_LL  ===================================================== */
43112  #define R_DSILINK_SQCH1DSC3AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
43113  #define R_DSILINK_SQCH1DSC3AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43114 /* ====================================================  SQCH1DSC4AR_LL  ===================================================== */
43115  #define R_DSILINK_SQCH1DSC4AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
43116  #define R_DSILINK_SQCH1DSC4AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43117 /* ====================================================  SQCH1DSC5AR_LL  ===================================================== */
43118  #define R_DSILINK_SQCH1DSC5AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
43119  #define R_DSILINK_SQCH1DSC5AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43120 /* ====================================================  SQCH1DSC6AR_LL  ===================================================== */
43121  #define R_DSILINK_SQCH1DSC6AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
43122  #define R_DSILINK_SQCH1DSC6AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43123 /* ====================================================  SQCH1DSC7AR_LL  ===================================================== */
43124  #define R_DSILINK_SQCH1DSC7AR_LL_DATA0_Pos      (0UL)          /*!< DATA0 (Bit 0)                                         */
43125  #define R_DSILINK_SQCH1DSC7AR_LL_DATA0_Msk      (0xffUL)       /*!< DATA0 (Bitfield-Mask: 0xff)                           */
43126 /* ====================================================  SQCH1DSC0AR_LH  ===================================================== */
43127  #define R_DSILINK_SQCH1DSC0AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
43128  #define R_DSILINK_SQCH1DSC0AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43129 /* ====================================================  SQCH1DSC1AR_LH  ===================================================== */
43130  #define R_DSILINK_SQCH1DSC1AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
43131  #define R_DSILINK_SQCH1DSC1AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43132 /* ====================================================  SQCH1DSC2AR_LH  ===================================================== */
43133  #define R_DSILINK_SQCH1DSC2AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
43134  #define R_DSILINK_SQCH1DSC2AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43135 /* ====================================================  SQCH1DSC3AR_LH  ===================================================== */
43136  #define R_DSILINK_SQCH1DSC3AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
43137  #define R_DSILINK_SQCH1DSC3AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43138 /* ====================================================  SQCH1DSC4AR_LH  ===================================================== */
43139  #define R_DSILINK_SQCH1DSC4AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
43140  #define R_DSILINK_SQCH1DSC4AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43141 /* ====================================================  SQCH1DSC5AR_LH  ===================================================== */
43142  #define R_DSILINK_SQCH1DSC5AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
43143  #define R_DSILINK_SQCH1DSC5AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43144 /* ====================================================  SQCH1DSC6AR_LH  ===================================================== */
43145  #define R_DSILINK_SQCH1DSC6AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
43146  #define R_DSILINK_SQCH1DSC6AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43147 /* ====================================================  SQCH1DSC7AR_LH  ===================================================== */
43148  #define R_DSILINK_SQCH1DSC7AR_LH_DATA1_Pos      (0UL)          /*!< DATA1 (Bit 0)                                         */
43149  #define R_DSILINK_SQCH1DSC7AR_LH_DATA1_Msk      (0xffUL)       /*!< DATA1 (Bitfield-Mask: 0xff)                           */
43150 /* =====================================================  SQCH1DSC0AR_H  ===================================================== */
43151  #define R_DSILINK_SQCH1DSC0AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
43152  #define R_DSILINK_SQCH1DSC0AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43153  #define R_DSILINK_SQCH1DSC0AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
43154  #define R_DSILINK_SQCH1DSC0AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43155  #define R_DSILINK_SQCH1DSC0AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
43156  #define R_DSILINK_SQCH1DSC0AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
43157  #define R_DSILINK_SQCH1DSC0AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
43158  #define R_DSILINK_SQCH1DSC0AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
43159  #define R_DSILINK_SQCH1DSC0AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
43160  #define R_DSILINK_SQCH1DSC0AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
43161  #define R_DSILINK_SQCH1DSC0AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
43162  #define R_DSILINK_SQCH1DSC0AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
43163 /* =====================================================  SQCH1DSC1AR_H  ===================================================== */
43164  #define R_DSILINK_SQCH1DSC1AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
43165  #define R_DSILINK_SQCH1DSC1AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43166  #define R_DSILINK_SQCH1DSC1AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
43167  #define R_DSILINK_SQCH1DSC1AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43168  #define R_DSILINK_SQCH1DSC1AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
43169  #define R_DSILINK_SQCH1DSC1AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
43170  #define R_DSILINK_SQCH1DSC1AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
43171  #define R_DSILINK_SQCH1DSC1AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
43172  #define R_DSILINK_SQCH1DSC1AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
43173  #define R_DSILINK_SQCH1DSC1AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
43174  #define R_DSILINK_SQCH1DSC1AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
43175  #define R_DSILINK_SQCH1DSC1AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
43176 /* =====================================================  SQCH1DSC2AR_H  ===================================================== */
43177  #define R_DSILINK_SQCH1DSC2AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
43178  #define R_DSILINK_SQCH1DSC2AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43179  #define R_DSILINK_SQCH1DSC2AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
43180  #define R_DSILINK_SQCH1DSC2AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43181  #define R_DSILINK_SQCH1DSC2AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
43182  #define R_DSILINK_SQCH1DSC2AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
43183  #define R_DSILINK_SQCH1DSC2AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
43184  #define R_DSILINK_SQCH1DSC2AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
43185  #define R_DSILINK_SQCH1DSC2AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
43186  #define R_DSILINK_SQCH1DSC2AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
43187  #define R_DSILINK_SQCH1DSC2AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
43188  #define R_DSILINK_SQCH1DSC2AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
43189 /* =====================================================  SQCH1DSC3AR_H  ===================================================== */
43190  #define R_DSILINK_SQCH1DSC3AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
43191  #define R_DSILINK_SQCH1DSC3AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43192  #define R_DSILINK_SQCH1DSC3AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
43193  #define R_DSILINK_SQCH1DSC3AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43194  #define R_DSILINK_SQCH1DSC3AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
43195  #define R_DSILINK_SQCH1DSC3AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
43196  #define R_DSILINK_SQCH1DSC3AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
43197  #define R_DSILINK_SQCH1DSC3AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
43198  #define R_DSILINK_SQCH1DSC3AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
43199  #define R_DSILINK_SQCH1DSC3AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
43200  #define R_DSILINK_SQCH1DSC3AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
43201  #define R_DSILINK_SQCH1DSC3AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
43202 /* =====================================================  SQCH1DSC4AR_H  ===================================================== */
43203  #define R_DSILINK_SQCH1DSC4AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
43204  #define R_DSILINK_SQCH1DSC4AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43205  #define R_DSILINK_SQCH1DSC4AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
43206  #define R_DSILINK_SQCH1DSC4AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43207  #define R_DSILINK_SQCH1DSC4AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
43208  #define R_DSILINK_SQCH1DSC4AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
43209  #define R_DSILINK_SQCH1DSC4AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
43210  #define R_DSILINK_SQCH1DSC4AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
43211  #define R_DSILINK_SQCH1DSC4AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
43212  #define R_DSILINK_SQCH1DSC4AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
43213  #define R_DSILINK_SQCH1DSC4AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
43214  #define R_DSILINK_SQCH1DSC4AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
43215 /* =====================================================  SQCH1DSC5AR_H  ===================================================== */
43216  #define R_DSILINK_SQCH1DSC5AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
43217  #define R_DSILINK_SQCH1DSC5AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43218  #define R_DSILINK_SQCH1DSC5AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
43219  #define R_DSILINK_SQCH1DSC5AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43220  #define R_DSILINK_SQCH1DSC5AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
43221  #define R_DSILINK_SQCH1DSC5AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
43222  #define R_DSILINK_SQCH1DSC5AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
43223  #define R_DSILINK_SQCH1DSC5AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
43224  #define R_DSILINK_SQCH1DSC5AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
43225  #define R_DSILINK_SQCH1DSC5AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
43226  #define R_DSILINK_SQCH1DSC5AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
43227  #define R_DSILINK_SQCH1DSC5AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
43228 /* =====================================================  SQCH1DSC6AR_H  ===================================================== */
43229  #define R_DSILINK_SQCH1DSC6AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
43230  #define R_DSILINK_SQCH1DSC6AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43231  #define R_DSILINK_SQCH1DSC6AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
43232  #define R_DSILINK_SQCH1DSC6AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43233  #define R_DSILINK_SQCH1DSC6AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
43234  #define R_DSILINK_SQCH1DSC6AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
43235  #define R_DSILINK_SQCH1DSC6AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
43236  #define R_DSILINK_SQCH1DSC6AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
43237  #define R_DSILINK_SQCH1DSC6AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
43238  #define R_DSILINK_SQCH1DSC6AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
43239  #define R_DSILINK_SQCH1DSC6AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
43240  #define R_DSILINK_SQCH1DSC6AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
43241 /* =====================================================  SQCH1DSC7AR_H  ===================================================== */
43242  #define R_DSILINK_SQCH1DSC7AR_H_DT_Pos          (0UL)          /*!< DT (Bit 0)                                            */
43243  #define R_DSILINK_SQCH1DSC7AR_H_DT_Msk          (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43244  #define R_DSILINK_SQCH1DSC7AR_H_VC_Pos          (6UL)          /*!< VC (Bit 6)                                            */
43245  #define R_DSILINK_SQCH1DSC7AR_H_VC_Msk          (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43246  #define R_DSILINK_SQCH1DSC7AR_H_FMT_Pos         (8UL)          /*!< FMT (Bit 8)                                           */
43247  #define R_DSILINK_SQCH1DSC7AR_H_FMT_Msk         (0x100UL)      /*!< FMT (Bitfield-Mask: 0x01)                             */
43248  #define R_DSILINK_SQCH1DSC7AR_H_SPD_Pos         (9UL)          /*!< SPD (Bit 9)                                           */
43249  #define R_DSILINK_SQCH1DSC7AR_H_SPD_Msk         (0x200UL)      /*!< SPD (Bitfield-Mask: 0x01)                             */
43250  #define R_DSILINK_SQCH1DSC7AR_H_BTA_Pos         (10UL)         /*!< BTA (Bit 10)                                          */
43251  #define R_DSILINK_SQCH1DSC7AR_H_BTA_Msk         (0xc00UL)      /*!< BTA (Bitfield-Mask: 0x03)                             */
43252  #define R_DSILINK_SQCH1DSC7AR_H_NXACT_Pos       (12UL)         /*!< NXACT (Bit 12)                                        */
43253  #define R_DSILINK_SQCH1DSC7AR_H_NXACT_Msk       (0x3000UL)     /*!< NXACT (Bitfield-Mask: 0x03)                           */
43254 /* ====================================================  SQCH1DSC0AR_HL  ===================================================== */
43255  #define R_DSILINK_SQCH1DSC0AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
43256  #define R_DSILINK_SQCH1DSC0AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43257  #define R_DSILINK_SQCH1DSC0AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
43258  #define R_DSILINK_SQCH1DSC0AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43259 /* ====================================================  SQCH1DSC1AR_HL  ===================================================== */
43260  #define R_DSILINK_SQCH1DSC1AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
43261  #define R_DSILINK_SQCH1DSC1AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43262  #define R_DSILINK_SQCH1DSC1AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
43263  #define R_DSILINK_SQCH1DSC1AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43264 /* ====================================================  SQCH1DSC2AR_HL  ===================================================== */
43265  #define R_DSILINK_SQCH1DSC2AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
43266  #define R_DSILINK_SQCH1DSC2AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43267  #define R_DSILINK_SQCH1DSC2AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
43268  #define R_DSILINK_SQCH1DSC2AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43269 /* ====================================================  SQCH1DSC3AR_HL  ===================================================== */
43270  #define R_DSILINK_SQCH1DSC3AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
43271  #define R_DSILINK_SQCH1DSC3AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43272  #define R_DSILINK_SQCH1DSC3AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
43273  #define R_DSILINK_SQCH1DSC3AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43274 /* ====================================================  SQCH1DSC4AR_HL  ===================================================== */
43275  #define R_DSILINK_SQCH1DSC4AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
43276  #define R_DSILINK_SQCH1DSC4AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43277  #define R_DSILINK_SQCH1DSC4AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
43278  #define R_DSILINK_SQCH1DSC4AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43279 /* ====================================================  SQCH1DSC5AR_HL  ===================================================== */
43280  #define R_DSILINK_SQCH1DSC5AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
43281  #define R_DSILINK_SQCH1DSC5AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43282  #define R_DSILINK_SQCH1DSC5AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
43283  #define R_DSILINK_SQCH1DSC5AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43284 /* ====================================================  SQCH1DSC6AR_HL  ===================================================== */
43285  #define R_DSILINK_SQCH1DSC6AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
43286  #define R_DSILINK_SQCH1DSC6AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43287  #define R_DSILINK_SQCH1DSC6AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
43288  #define R_DSILINK_SQCH1DSC6AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43289 /* ====================================================  SQCH1DSC7AR_HL  ===================================================== */
43290  #define R_DSILINK_SQCH1DSC7AR_HL_DT_Pos         (0UL)          /*!< DT (Bit 0)                                            */
43291  #define R_DSILINK_SQCH1DSC7AR_HL_DT_Msk         (0x3fUL)       /*!< DT (Bitfield-Mask: 0x3f)                              */
43292  #define R_DSILINK_SQCH1DSC7AR_HL_VC_Pos         (6UL)          /*!< VC (Bit 6)                                            */
43293  #define R_DSILINK_SQCH1DSC7AR_HL_VC_Msk         (0xc0UL)       /*!< VC (Bitfield-Mask: 0x03)                              */
43294 /* ====================================================  SQCH1DSC0AR_HH  ===================================================== */
43295  #define R_DSILINK_SQCH1DSC0AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
43296  #define R_DSILINK_SQCH1DSC0AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
43297  #define R_DSILINK_SQCH1DSC0AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
43298  #define R_DSILINK_SQCH1DSC0AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
43299  #define R_DSILINK_SQCH1DSC0AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
43300  #define R_DSILINK_SQCH1DSC0AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
43301  #define R_DSILINK_SQCH1DSC0AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
43302  #define R_DSILINK_SQCH1DSC0AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
43303 /* ====================================================  SQCH1DSC1AR_HH  ===================================================== */
43304  #define R_DSILINK_SQCH1DSC1AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
43305  #define R_DSILINK_SQCH1DSC1AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
43306  #define R_DSILINK_SQCH1DSC1AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
43307  #define R_DSILINK_SQCH1DSC1AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
43308  #define R_DSILINK_SQCH1DSC1AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
43309  #define R_DSILINK_SQCH1DSC1AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
43310  #define R_DSILINK_SQCH1DSC1AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
43311  #define R_DSILINK_SQCH1DSC1AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
43312 /* ====================================================  SQCH1DSC2AR_HH  ===================================================== */
43313  #define R_DSILINK_SQCH1DSC2AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
43314  #define R_DSILINK_SQCH1DSC2AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
43315  #define R_DSILINK_SQCH1DSC2AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
43316  #define R_DSILINK_SQCH1DSC2AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
43317  #define R_DSILINK_SQCH1DSC2AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
43318  #define R_DSILINK_SQCH1DSC2AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
43319  #define R_DSILINK_SQCH1DSC2AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
43320  #define R_DSILINK_SQCH1DSC2AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
43321 /* ====================================================  SQCH1DSC3AR_HH  ===================================================== */
43322  #define R_DSILINK_SQCH1DSC3AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
43323  #define R_DSILINK_SQCH1DSC3AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
43324  #define R_DSILINK_SQCH1DSC3AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
43325  #define R_DSILINK_SQCH1DSC3AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
43326  #define R_DSILINK_SQCH1DSC3AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
43327  #define R_DSILINK_SQCH1DSC3AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
43328  #define R_DSILINK_SQCH1DSC3AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
43329  #define R_DSILINK_SQCH1DSC3AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
43330 /* ====================================================  SQCH1DSC4AR_HH  ===================================================== */
43331  #define R_DSILINK_SQCH1DSC4AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
43332  #define R_DSILINK_SQCH1DSC4AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
43333  #define R_DSILINK_SQCH1DSC4AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
43334  #define R_DSILINK_SQCH1DSC4AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
43335  #define R_DSILINK_SQCH1DSC4AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
43336  #define R_DSILINK_SQCH1DSC4AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
43337  #define R_DSILINK_SQCH1DSC4AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
43338  #define R_DSILINK_SQCH1DSC4AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
43339 /* ====================================================  SQCH1DSC5AR_HH  ===================================================== */
43340  #define R_DSILINK_SQCH1DSC5AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
43341  #define R_DSILINK_SQCH1DSC5AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
43342  #define R_DSILINK_SQCH1DSC5AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
43343  #define R_DSILINK_SQCH1DSC5AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
43344  #define R_DSILINK_SQCH1DSC5AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
43345  #define R_DSILINK_SQCH1DSC5AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
43346  #define R_DSILINK_SQCH1DSC5AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
43347  #define R_DSILINK_SQCH1DSC5AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
43348 /* ====================================================  SQCH1DSC6AR_HH  ===================================================== */
43349  #define R_DSILINK_SQCH1DSC6AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
43350  #define R_DSILINK_SQCH1DSC6AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
43351  #define R_DSILINK_SQCH1DSC6AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
43352  #define R_DSILINK_SQCH1DSC6AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
43353  #define R_DSILINK_SQCH1DSC6AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
43354  #define R_DSILINK_SQCH1DSC6AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
43355  #define R_DSILINK_SQCH1DSC6AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
43356  #define R_DSILINK_SQCH1DSC6AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
43357 /* ====================================================  SQCH1DSC7AR_HH  ===================================================== */
43358  #define R_DSILINK_SQCH1DSC7AR_HH_FMT_Pos        (0UL)          /*!< FMT (Bit 0)                                           */
43359  #define R_DSILINK_SQCH1DSC7AR_HH_FMT_Msk        (0x1UL)        /*!< FMT (Bitfield-Mask: 0x01)                             */
43360  #define R_DSILINK_SQCH1DSC7AR_HH_SPD_Pos        (1UL)          /*!< SPD (Bit 1)                                           */
43361  #define R_DSILINK_SQCH1DSC7AR_HH_SPD_Msk        (0x2UL)        /*!< SPD (Bitfield-Mask: 0x01)                             */
43362  #define R_DSILINK_SQCH1DSC7AR_HH_BTA_Pos        (2UL)          /*!< BTA (Bit 2)                                           */
43363  #define R_DSILINK_SQCH1DSC7AR_HH_BTA_Msk        (0xcUL)        /*!< BTA (Bitfield-Mask: 0x03)                             */
43364  #define R_DSILINK_SQCH1DSC7AR_HH_NXACT_Pos      (4UL)          /*!< NXACT (Bit 4)                                         */
43365  #define R_DSILINK_SQCH1DSC7AR_HH_NXACT_Msk      (0x30UL)       /*!< NXACT (Bitfield-Mask: 0x03)                           */
43366 /* ======================================================  SQCH1DSC0BR  ====================================================== */
43367  #define R_DSILINK_SQCH1DSC0BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
43368  #define R_DSILINK_SQCH1DSC0BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
43369 /* ======================================================  SQCH1DSC1BR  ====================================================== */
43370  #define R_DSILINK_SQCH1DSC1BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
43371  #define R_DSILINK_SQCH1DSC1BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
43372 /* ======================================================  SQCH1DSC2BR  ====================================================== */
43373  #define R_DSILINK_SQCH1DSC2BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
43374  #define R_DSILINK_SQCH1DSC2BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
43375 /* ======================================================  SQCH1DSC3BR  ====================================================== */
43376  #define R_DSILINK_SQCH1DSC3BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
43377  #define R_DSILINK_SQCH1DSC3BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
43378 /* ======================================================  SQCH1DSC4BR  ====================================================== */
43379  #define R_DSILINK_SQCH1DSC4BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
43380  #define R_DSILINK_SQCH1DSC4BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
43381 /* ======================================================  SQCH1DSC5BR  ====================================================== */
43382  #define R_DSILINK_SQCH1DSC5BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
43383  #define R_DSILINK_SQCH1DSC5BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
43384 /* ======================================================  SQCH1DSC6BR  ====================================================== */
43385  #define R_DSILINK_SQCH1DSC6BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
43386  #define R_DSILINK_SQCH1DSC6BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
43387 /* ======================================================  SQCH1DSC7BR  ====================================================== */
43388  #define R_DSILINK_SQCH1DSC7BR_DTSEL_Pos         (24UL)         /*!< DTSEL (Bit 24)                                        */
43389  #define R_DSILINK_SQCH1DSC7BR_DTSEL_Msk         (0x3000000UL)  /*!< DTSEL (Bitfield-Mask: 0x03)                           */
43390 /* ======================================================  SQCH1DSC0CR  ====================================================== */
43391  #define R_DSILINK_SQCH1DSC0CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
43392  #define R_DSILINK_SQCH1DSC0CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43393  #define R_DSILINK_SQCH1DSC0CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
43394  #define R_DSILINK_SQCH1DSC0CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43395  #define R_DSILINK_SQCH1DSC0CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
43396  #define R_DSILINK_SQCH1DSC0CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43397 /* ======================================================  SQCH1DSC1CR  ====================================================== */
43398  #define R_DSILINK_SQCH1DSC1CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
43399  #define R_DSILINK_SQCH1DSC1CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43400  #define R_DSILINK_SQCH1DSC1CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
43401  #define R_DSILINK_SQCH1DSC1CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43402  #define R_DSILINK_SQCH1DSC1CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
43403  #define R_DSILINK_SQCH1DSC1CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43404 /* ======================================================  SQCH1DSC2CR  ====================================================== */
43405  #define R_DSILINK_SQCH1DSC2CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
43406  #define R_DSILINK_SQCH1DSC2CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43407  #define R_DSILINK_SQCH1DSC2CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
43408  #define R_DSILINK_SQCH1DSC2CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43409  #define R_DSILINK_SQCH1DSC2CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
43410  #define R_DSILINK_SQCH1DSC2CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43411 /* ======================================================  SQCH1DSC3CR  ====================================================== */
43412  #define R_DSILINK_SQCH1DSC3CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
43413  #define R_DSILINK_SQCH1DSC3CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43414  #define R_DSILINK_SQCH1DSC3CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
43415  #define R_DSILINK_SQCH1DSC3CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43416  #define R_DSILINK_SQCH1DSC3CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
43417  #define R_DSILINK_SQCH1DSC3CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43418 /* ======================================================  SQCH1DSC4CR  ====================================================== */
43419  #define R_DSILINK_SQCH1DSC4CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
43420  #define R_DSILINK_SQCH1DSC4CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43421  #define R_DSILINK_SQCH1DSC4CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
43422  #define R_DSILINK_SQCH1DSC4CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43423  #define R_DSILINK_SQCH1DSC4CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
43424  #define R_DSILINK_SQCH1DSC4CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43425 /* ======================================================  SQCH1DSC5CR  ====================================================== */
43426  #define R_DSILINK_SQCH1DSC5CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
43427  #define R_DSILINK_SQCH1DSC5CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43428  #define R_DSILINK_SQCH1DSC5CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
43429  #define R_DSILINK_SQCH1DSC5CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43430  #define R_DSILINK_SQCH1DSC5CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
43431  #define R_DSILINK_SQCH1DSC5CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43432 /* ======================================================  SQCH1DSC6CR  ====================================================== */
43433  #define R_DSILINK_SQCH1DSC6CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
43434  #define R_DSILINK_SQCH1DSC6CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43435  #define R_DSILINK_SQCH1DSC6CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
43436  #define R_DSILINK_SQCH1DSC6CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43437  #define R_DSILINK_SQCH1DSC6CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
43438  #define R_DSILINK_SQCH1DSC6CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43439 /* ======================================================  SQCH1DSC7CR  ====================================================== */
43440  #define R_DSILINK_SQCH1DSC7CR_FINACT_Pos        (0UL)          /*!< FINACT (Bit 0)                                        */
43441  #define R_DSILINK_SQCH1DSC7CR_FINACT_Msk        (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43442  #define R_DSILINK_SQCH1DSC7CR_AUXOP_Pos         (22UL)         /*!< AUXOP (Bit 22)                                        */
43443  #define R_DSILINK_SQCH1DSC7CR_AUXOP_Msk         (0x400000UL)   /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43444  #define R_DSILINK_SQCH1DSC7CR_ACTCODE_Pos       (24UL)         /*!< ACTCODE (Bit 24)                                      */
43445  #define R_DSILINK_SQCH1DSC7CR_ACTCODE_Msk       (0xff000000UL) /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43446 /* =====================================================  SQCH1DSC0CR_L  ===================================================== */
43447  #define R_DSILINK_SQCH1DSC0CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
43448  #define R_DSILINK_SQCH1DSC0CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43449 /* =====================================================  SQCH1DSC1CR_L  ===================================================== */
43450  #define R_DSILINK_SQCH1DSC1CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
43451  #define R_DSILINK_SQCH1DSC1CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43452 /* =====================================================  SQCH1DSC2CR_L  ===================================================== */
43453  #define R_DSILINK_SQCH1DSC2CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
43454  #define R_DSILINK_SQCH1DSC2CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43455 /* =====================================================  SQCH1DSC3CR_L  ===================================================== */
43456  #define R_DSILINK_SQCH1DSC3CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
43457  #define R_DSILINK_SQCH1DSC3CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43458 /* =====================================================  SQCH1DSC4CR_L  ===================================================== */
43459  #define R_DSILINK_SQCH1DSC4CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
43460  #define R_DSILINK_SQCH1DSC4CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43461 /* =====================================================  SQCH1DSC5CR_L  ===================================================== */
43462  #define R_DSILINK_SQCH1DSC5CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
43463  #define R_DSILINK_SQCH1DSC5CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43464 /* =====================================================  SQCH1DSC6CR_L  ===================================================== */
43465  #define R_DSILINK_SQCH1DSC6CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
43466  #define R_DSILINK_SQCH1DSC6CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43467 /* =====================================================  SQCH1DSC7CR_L  ===================================================== */
43468  #define R_DSILINK_SQCH1DSC7CR_L_FINACT_Pos      (0UL)          /*!< FINACT (Bit 0)                                        */
43469  #define R_DSILINK_SQCH1DSC7CR_L_FINACT_Msk      (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43470 /* ====================================================  SQCH1DSC0CR_LL  ===================================================== */
43471  #define R_DSILINK_SQCH1DSC0CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
43472  #define R_DSILINK_SQCH1DSC0CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43473 /* ====================================================  SQCH1DSC1CR_LL  ===================================================== */
43474  #define R_DSILINK_SQCH1DSC1CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
43475  #define R_DSILINK_SQCH1DSC1CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43476 /* ====================================================  SQCH1DSC2CR_LL  ===================================================== */
43477  #define R_DSILINK_SQCH1DSC2CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
43478  #define R_DSILINK_SQCH1DSC2CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43479 /* ====================================================  SQCH1DSC3CR_LL  ===================================================== */
43480  #define R_DSILINK_SQCH1DSC3CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
43481  #define R_DSILINK_SQCH1DSC3CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43482 /* ====================================================  SQCH1DSC4CR_LL  ===================================================== */
43483  #define R_DSILINK_SQCH1DSC4CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
43484  #define R_DSILINK_SQCH1DSC4CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43485 /* ====================================================  SQCH1DSC5CR_LL  ===================================================== */
43486  #define R_DSILINK_SQCH1DSC5CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
43487  #define R_DSILINK_SQCH1DSC5CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43488 /* ====================================================  SQCH1DSC6CR_LL  ===================================================== */
43489  #define R_DSILINK_SQCH1DSC6CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
43490  #define R_DSILINK_SQCH1DSC6CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43491 /* ====================================================  SQCH1DSC7CR_LL  ===================================================== */
43492  #define R_DSILINK_SQCH1DSC7CR_LL_FINACT_Pos     (0UL)          /*!< FINACT (Bit 0)                                        */
43493  #define R_DSILINK_SQCH1DSC7CR_LL_FINACT_Msk     (0x1UL)        /*!< FINACT (Bitfield-Mask: 0x01)                          */
43494 /* =====================================================  SQCH1DSC0CR_H  ===================================================== */
43495  #define R_DSILINK_SQCH1DSC0CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
43496  #define R_DSILINK_SQCH1DSC0CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43497  #define R_DSILINK_SQCH1DSC0CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
43498  #define R_DSILINK_SQCH1DSC0CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43499 /* =====================================================  SQCH1DSC1CR_H  ===================================================== */
43500  #define R_DSILINK_SQCH1DSC1CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
43501  #define R_DSILINK_SQCH1DSC1CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43502  #define R_DSILINK_SQCH1DSC1CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
43503  #define R_DSILINK_SQCH1DSC1CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43504 /* =====================================================  SQCH1DSC2CR_H  ===================================================== */
43505  #define R_DSILINK_SQCH1DSC2CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
43506  #define R_DSILINK_SQCH1DSC2CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43507  #define R_DSILINK_SQCH1DSC2CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
43508  #define R_DSILINK_SQCH1DSC2CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43509 /* =====================================================  SQCH1DSC3CR_H  ===================================================== */
43510  #define R_DSILINK_SQCH1DSC3CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
43511  #define R_DSILINK_SQCH1DSC3CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43512  #define R_DSILINK_SQCH1DSC3CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
43513  #define R_DSILINK_SQCH1DSC3CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43514 /* =====================================================  SQCH1DSC4CR_H  ===================================================== */
43515  #define R_DSILINK_SQCH1DSC4CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
43516  #define R_DSILINK_SQCH1DSC4CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43517  #define R_DSILINK_SQCH1DSC4CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
43518  #define R_DSILINK_SQCH1DSC4CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43519 /* =====================================================  SQCH1DSC5CR_H  ===================================================== */
43520  #define R_DSILINK_SQCH1DSC5CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
43521  #define R_DSILINK_SQCH1DSC5CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43522  #define R_DSILINK_SQCH1DSC5CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
43523  #define R_DSILINK_SQCH1DSC5CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43524 /* =====================================================  SQCH1DSC6CR_H  ===================================================== */
43525  #define R_DSILINK_SQCH1DSC6CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
43526  #define R_DSILINK_SQCH1DSC6CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43527  #define R_DSILINK_SQCH1DSC6CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
43528  #define R_DSILINK_SQCH1DSC6CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43529 /* =====================================================  SQCH1DSC7CR_H  ===================================================== */
43530  #define R_DSILINK_SQCH1DSC7CR_H_AUXOP_Pos       (6UL)          /*!< AUXOP (Bit 6)                                         */
43531  #define R_DSILINK_SQCH1DSC7CR_H_AUXOP_Msk       (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43532  #define R_DSILINK_SQCH1DSC7CR_H_ACTCODE_Pos     (8UL)          /*!< ACTCODE (Bit 8)                                       */
43533  #define R_DSILINK_SQCH1DSC7CR_H_ACTCODE_Msk     (0xff00UL)     /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43534 /* ====================================================  SQCH1DSC0CR_HL  ===================================================== */
43535  #define R_DSILINK_SQCH1DSC0CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
43536  #define R_DSILINK_SQCH1DSC0CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43537 /* ====================================================  SQCH1DSC1CR_HL  ===================================================== */
43538  #define R_DSILINK_SQCH1DSC1CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
43539  #define R_DSILINK_SQCH1DSC1CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43540 /* ====================================================  SQCH1DSC2CR_HL  ===================================================== */
43541  #define R_DSILINK_SQCH1DSC2CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
43542  #define R_DSILINK_SQCH1DSC2CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43543 /* ====================================================  SQCH1DSC3CR_HL  ===================================================== */
43544  #define R_DSILINK_SQCH1DSC3CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
43545  #define R_DSILINK_SQCH1DSC3CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43546 /* ====================================================  SQCH1DSC4CR_HL  ===================================================== */
43547  #define R_DSILINK_SQCH1DSC4CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
43548  #define R_DSILINK_SQCH1DSC4CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43549 /* ====================================================  SQCH1DSC5CR_HL  ===================================================== */
43550  #define R_DSILINK_SQCH1DSC5CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
43551  #define R_DSILINK_SQCH1DSC5CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43552 /* ====================================================  SQCH1DSC6CR_HL  ===================================================== */
43553  #define R_DSILINK_SQCH1DSC6CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
43554  #define R_DSILINK_SQCH1DSC6CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43555 /* ====================================================  SQCH1DSC7CR_HL  ===================================================== */
43556  #define R_DSILINK_SQCH1DSC7CR_HL_AUXOP_Pos      (6UL)          /*!< AUXOP (Bit 6)                                         */
43557  #define R_DSILINK_SQCH1DSC7CR_HL_AUXOP_Msk      (0x40UL)       /*!< AUXOP (Bitfield-Mask: 0x01)                           */
43558 /* ====================================================  SQCH1DSC0CR_HH  ===================================================== */
43559  #define R_DSILINK_SQCH1DSC0CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
43560  #define R_DSILINK_SQCH1DSC0CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43561 /* ====================================================  SQCH1DSC1CR_HH  ===================================================== */
43562  #define R_DSILINK_SQCH1DSC1CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
43563  #define R_DSILINK_SQCH1DSC1CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43564 /* ====================================================  SQCH1DSC2CR_HH  ===================================================== */
43565  #define R_DSILINK_SQCH1DSC2CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
43566  #define R_DSILINK_SQCH1DSC2CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43567 /* ====================================================  SQCH1DSC3CR_HH  ===================================================== */
43568  #define R_DSILINK_SQCH1DSC3CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
43569  #define R_DSILINK_SQCH1DSC3CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43570 /* ====================================================  SQCH1DSC4CR_HH  ===================================================== */
43571  #define R_DSILINK_SQCH1DSC4CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
43572  #define R_DSILINK_SQCH1DSC4CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43573 /* ====================================================  SQCH1DSC5CR_HH  ===================================================== */
43574  #define R_DSILINK_SQCH1DSC5CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
43575  #define R_DSILINK_SQCH1DSC5CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43576 /* ====================================================  SQCH1DSC6CR_HH  ===================================================== */
43577  #define R_DSILINK_SQCH1DSC6CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
43578  #define R_DSILINK_SQCH1DSC6CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43579 /* ====================================================  SQCH1DSC7CR_HH  ===================================================== */
43580  #define R_DSILINK_SQCH1DSC7CR_HH_ACTCODE_Pos    (0UL)          /*!< ACTCODE (Bit 0)                                       */
43581  #define R_DSILINK_SQCH1DSC7CR_HH_ACTCODE_Msk    (0xffUL)       /*!< ACTCODE (Bitfield-Mask: 0xff)                         */
43582 /* ======================================================  SQCH1DSC0DR  ====================================================== */
43583  #define R_DSILINK_SQCH1DSC0DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
43584  #define R_DSILINK_SQCH1DSC0DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
43585 /* ======================================================  SQCH1DSC1DR  ====================================================== */
43586  #define R_DSILINK_SQCH1DSC1DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
43587  #define R_DSILINK_SQCH1DSC1DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
43588 /* ======================================================  SQCH1DSC2DR  ====================================================== */
43589  #define R_DSILINK_SQCH1DSC2DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
43590  #define R_DSILINK_SQCH1DSC2DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
43591 /* ======================================================  SQCH1DSC3DR  ====================================================== */
43592  #define R_DSILINK_SQCH1DSC3DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
43593  #define R_DSILINK_SQCH1DSC3DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
43594 /* ======================================================  SQCH1DSC4DR  ====================================================== */
43595  #define R_DSILINK_SQCH1DSC4DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
43596  #define R_DSILINK_SQCH1DSC4DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
43597 /* ======================================================  SQCH1DSC5DR  ====================================================== */
43598  #define R_DSILINK_SQCH1DSC5DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
43599  #define R_DSILINK_SQCH1DSC5DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
43600 /* ======================================================  SQCH1DSC6DR  ====================================================== */
43601  #define R_DSILINK_SQCH1DSC6DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
43602  #define R_DSILINK_SQCH1DSC6DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
43603 /* ======================================================  SQCH1DSC7DR  ====================================================== */
43604  #define R_DSILINK_SQCH1DSC7DR_LADDR_Pos         (0UL)          /*!< LADDR (Bit 0)                                         */
43605  #define R_DSILINK_SQCH1DSC7DR_LADDR_Msk         (0xffffffffUL) /*!< LADDR (Bitfield-Mask: 0xffffffff)                     */
43606 /* =====================================================  SQCH1DSC0DR_L  ===================================================== */
43607  #define R_DSILINK_SQCH1DSC0DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
43608  #define R_DSILINK_SQCH1DSC0DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
43609 /* =====================================================  SQCH1DSC1DR_L  ===================================================== */
43610  #define R_DSILINK_SQCH1DSC1DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
43611  #define R_DSILINK_SQCH1DSC1DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
43612 /* =====================================================  SQCH1DSC2DR_L  ===================================================== */
43613  #define R_DSILINK_SQCH1DSC2DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
43614  #define R_DSILINK_SQCH1DSC2DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
43615 /* =====================================================  SQCH1DSC3DR_L  ===================================================== */
43616  #define R_DSILINK_SQCH1DSC3DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
43617  #define R_DSILINK_SQCH1DSC3DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
43618 /* =====================================================  SQCH1DSC4DR_L  ===================================================== */
43619  #define R_DSILINK_SQCH1DSC4DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
43620  #define R_DSILINK_SQCH1DSC4DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
43621 /* =====================================================  SQCH1DSC5DR_L  ===================================================== */
43622  #define R_DSILINK_SQCH1DSC5DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
43623  #define R_DSILINK_SQCH1DSC5DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
43624 /* =====================================================  SQCH1DSC6DR_L  ===================================================== */
43625  #define R_DSILINK_SQCH1DSC6DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
43626  #define R_DSILINK_SQCH1DSC6DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
43627 /* =====================================================  SQCH1DSC7DR_L  ===================================================== */
43628  #define R_DSILINK_SQCH1DSC7DR_L_LADDR_Pos       (0UL)          /*!< LADDR (Bit 0)                                         */
43629  #define R_DSILINK_SQCH1DSC7DR_L_LADDR_Msk       (0xffffUL)     /*!< LADDR (Bitfield-Mask: 0xffff)                         */
43630 /* ====================================================  SQCH1DSC0DR_LL  ===================================================== */
43631  #define R_DSILINK_SQCH1DSC0DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43632  #define R_DSILINK_SQCH1DSC0DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43633 /* ====================================================  SQCH1DSC1DR_LL  ===================================================== */
43634  #define R_DSILINK_SQCH1DSC1DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43635  #define R_DSILINK_SQCH1DSC1DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43636 /* ====================================================  SQCH1DSC2DR_LL  ===================================================== */
43637  #define R_DSILINK_SQCH1DSC2DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43638  #define R_DSILINK_SQCH1DSC2DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43639 /* ====================================================  SQCH1DSC3DR_LL  ===================================================== */
43640  #define R_DSILINK_SQCH1DSC3DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43641  #define R_DSILINK_SQCH1DSC3DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43642 /* ====================================================  SQCH1DSC4DR_LL  ===================================================== */
43643  #define R_DSILINK_SQCH1DSC4DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43644  #define R_DSILINK_SQCH1DSC4DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43645 /* ====================================================  SQCH1DSC5DR_LL  ===================================================== */
43646  #define R_DSILINK_SQCH1DSC5DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43647  #define R_DSILINK_SQCH1DSC5DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43648 /* ====================================================  SQCH1DSC6DR_LL  ===================================================== */
43649  #define R_DSILINK_SQCH1DSC6DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43650  #define R_DSILINK_SQCH1DSC6DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43651 /* ====================================================  SQCH1DSC7DR_LL  ===================================================== */
43652  #define R_DSILINK_SQCH1DSC7DR_LL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43653  #define R_DSILINK_SQCH1DSC7DR_LL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43654 /* ====================================================  SQCH1DSC0DR_LH  ===================================================== */
43655  #define R_DSILINK_SQCH1DSC0DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43656  #define R_DSILINK_SQCH1DSC0DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43657 /* ====================================================  SQCH1DSC1DR_LH  ===================================================== */
43658  #define R_DSILINK_SQCH1DSC1DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43659  #define R_DSILINK_SQCH1DSC1DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43660 /* ====================================================  SQCH1DSC2DR_LH  ===================================================== */
43661  #define R_DSILINK_SQCH1DSC2DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43662  #define R_DSILINK_SQCH1DSC2DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43663 /* ====================================================  SQCH1DSC3DR_LH  ===================================================== */
43664  #define R_DSILINK_SQCH1DSC3DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43665  #define R_DSILINK_SQCH1DSC3DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43666 /* ====================================================  SQCH1DSC4DR_LH  ===================================================== */
43667  #define R_DSILINK_SQCH1DSC4DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43668  #define R_DSILINK_SQCH1DSC4DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43669 /* ====================================================  SQCH1DSC5DR_LH  ===================================================== */
43670  #define R_DSILINK_SQCH1DSC5DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43671  #define R_DSILINK_SQCH1DSC5DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43672 /* ====================================================  SQCH1DSC6DR_LH  ===================================================== */
43673  #define R_DSILINK_SQCH1DSC6DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43674  #define R_DSILINK_SQCH1DSC6DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43675 /* ====================================================  SQCH1DSC7DR_LH  ===================================================== */
43676  #define R_DSILINK_SQCH1DSC7DR_LH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43677  #define R_DSILINK_SQCH1DSC7DR_LH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43678 /* ====================================================  SQCH1DSC0DR_HL  ===================================================== */
43679  #define R_DSILINK_SQCH1DSC0DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43680  #define R_DSILINK_SQCH1DSC0DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43681 /* ====================================================  SQCH1DSC1DR_HL  ===================================================== */
43682  #define R_DSILINK_SQCH1DSC1DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43683  #define R_DSILINK_SQCH1DSC1DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43684 /* ====================================================  SQCH1DSC2DR_HL  ===================================================== */
43685  #define R_DSILINK_SQCH1DSC2DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43686  #define R_DSILINK_SQCH1DSC2DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43687 /* ====================================================  SQCH1DSC3DR_HL  ===================================================== */
43688  #define R_DSILINK_SQCH1DSC3DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43689  #define R_DSILINK_SQCH1DSC3DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43690 /* ====================================================  SQCH1DSC4DR_HL  ===================================================== */
43691  #define R_DSILINK_SQCH1DSC4DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43692  #define R_DSILINK_SQCH1DSC4DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43693 /* ====================================================  SQCH1DSC5DR_HL  ===================================================== */
43694  #define R_DSILINK_SQCH1DSC5DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43695  #define R_DSILINK_SQCH1DSC5DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43696 /* ====================================================  SQCH1DSC6DR_HL  ===================================================== */
43697  #define R_DSILINK_SQCH1DSC6DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43698  #define R_DSILINK_SQCH1DSC6DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43699 /* ====================================================  SQCH1DSC7DR_HL  ===================================================== */
43700  #define R_DSILINK_SQCH1DSC7DR_HL_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43701  #define R_DSILINK_SQCH1DSC7DR_HL_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43702 /* ====================================================  SQCH1DSC0DR_HH  ===================================================== */
43703  #define R_DSILINK_SQCH1DSC0DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43704  #define R_DSILINK_SQCH1DSC0DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43705 /* ====================================================  SQCH1DSC1DR_HH  ===================================================== */
43706  #define R_DSILINK_SQCH1DSC1DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43707  #define R_DSILINK_SQCH1DSC1DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43708 /* ====================================================  SQCH1DSC2DR_HH  ===================================================== */
43709  #define R_DSILINK_SQCH1DSC2DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43710  #define R_DSILINK_SQCH1DSC2DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43711 /* ====================================================  SQCH1DSC3DR_HH  ===================================================== */
43712  #define R_DSILINK_SQCH1DSC3DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43713  #define R_DSILINK_SQCH1DSC3DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43714 /* ====================================================  SQCH1DSC4DR_HH  ===================================================== */
43715  #define R_DSILINK_SQCH1DSC4DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43716  #define R_DSILINK_SQCH1DSC4DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43717 /* ====================================================  SQCH1DSC5DR_HH  ===================================================== */
43718  #define R_DSILINK_SQCH1DSC5DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43719  #define R_DSILINK_SQCH1DSC5DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43720 /* ====================================================  SQCH1DSC6DR_HH  ===================================================== */
43721  #define R_DSILINK_SQCH1DSC6DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43722  #define R_DSILINK_SQCH1DSC6DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43723 /* ====================================================  SQCH1DSC7DR_HH  ===================================================== */
43724  #define R_DSILINK_SQCH1DSC7DR_HH_LADDR_Pos      (0UL)          /*!< LADDR (Bit 0)                                         */
43725  #define R_DSILINK_SQCH1DSC7DR_HH_LADDR_Msk      (0xffUL)       /*!< LADDR (Bitfield-Mask: 0xff)                           */
43726 
43727 /* =========================================================================================================================== */
43728 /* ================                                          R_FLAD                                           ================ */
43729 /* =========================================================================================================================== */
43730 
43731 /* ========================================================  FCKMHZ  ========================================================= */
43732  #define R_FLAD_FCKMHZ_FCKMHZ_Pos    (0UL)    /*!< FCKMHZ (Bit 0)                                        */
43733  #define R_FLAD_FCKMHZ_FCKMHZ_Msk    (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff)                          */
43734 
43735 /* =========================================================================================================================== */
43736 /* ================                                      R_OFS_DATAFLASH                                      ================ */
43737 /* =========================================================================================================================== */
43738 
43739 /* =======================================================  FSBLCTRL0  ======================================================= */
43740  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos        (0UL)     /*!< FSBLEN (Bit 0)                                        */
43741  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Msk        (0x7UL)   /*!< FSBLEN (Bitfield-Mask: 0x07)                          */
43742  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos    (3UL)     /*!< FSBLSKIPSW (Bit 3)                                    */
43743  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Msk    (0x38UL)  /*!< FSBLSKIPSW (Bitfield-Mask: 0x07)                      */
43744  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos    (6UL)     /*!< FSBLSKIPDS (Bit 6)                                    */
43745  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Msk    (0x1c0UL) /*!< FSBLSKIPDS (Bitfield-Mask: 0x07)                      */
43746  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos       (9UL)     /*!< FSBLCLK (Bit 9)                                       */
43747  #define R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Msk       (0xe00UL) /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */
43748 /* =======================================================  FSBLCTRL1  ======================================================= */
43749  #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos      (0UL)     /*!< FSBLEXMD (Bit 0)                                      */
43750  #define R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Msk      (0x3UL)   /*!< FSBLEXMD (Bitfield-Mask: 0x03)                        */
43751 /* =======================================================  FSBLCTRL2  ======================================================= */
43752  #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos        (0UL)     /*!< PORTPN (Bit 0)                                        */
43753  #define R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Msk        (0xfUL)   /*!< PORTPN (Bitfield-Mask: 0x0f)                          */
43754  #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos        (4UL)     /*!< PORTGN (Bit 4)                                        */
43755  #define R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Msk        (0x1f0UL) /*!< PORTGN (Bitfield-Mask: 0x1f)                          */
43756 /* =========================================================  SACC0  ========================================================= */
43757 /* =========================================================  SACC1  ========================================================= */
43758 /* =========================================================  SAMR  ========================================================== */
43759 /* =======================================================  HOEMRTPK  ======================================================== */
43760 /* =========================================================  ARCLS  ========================================================= */
43761  #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Pos          (0UL)          /*!< ARCS_LK (Bit 0)                                       */
43762  #define R_OFS_DATAFLASH_ARCLS_ARCS_LK_Msk          (0x1UL)        /*!< ARCS_LK (Bitfield-Mask: 0x01)                         */
43763  #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Pos         (1UL)          /*!< ARCNS_LK (Bit 1)                                      */
43764  #define R_OFS_DATAFLASH_ARCLS_ARCNS_LK_Msk         (0x1eUL)       /*!< ARCNS_LK (Bitfield-Mask: 0x0f)                        */
43765  #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Pos         (5UL)          /*!< ARCBL_LK (Bit 5)                                      */
43766  #define R_OFS_DATAFLASH_ARCLS_ARCBL_LK_Msk         (0x20UL)       /*!< ARCBL_LK (Bitfield-Mask: 0x01)                        */
43767 /* =========================================================  ARCCS  ========================================================= */
43768  #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Pos        (0UL)          /*!< CNF_ARCNS (Bit 0)                                     */
43769  #define R_OFS_DATAFLASH_ARCCS_CNF_ARCNS_Msk        (0x3UL)        /*!< CNF_ARCNS (Bitfield-Mask: 0x03)                       */
43770 /* ========================================================  ARC_SEC  ======================================================== */
43771  #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Pos        (0UL)          /*!< ARC_SEC (Bit 0)                                       */
43772  #define R_OFS_DATAFLASH_ARC_SEC_ARC_SEC_Msk        (0xffffffffUL) /*!< ARC_SEC (Bitfield-Mask: 0xffffffff)                   */
43773 /* =======================================================  ARC_NSEC  ======================================================== */
43774  #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Pos      (0UL)          /*!< ARC_NSEC (Bit 0)                                      */
43775  #define R_OFS_DATAFLASH_ARC_NSEC_ARC_NSEC_Msk      (0xffffffffUL) /*!< ARC_NSEC (Bitfield-Mask: 0xffffffff)                  */
43776 /* =======================================================  ARC_OEMBL  ======================================================= */
43777  #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Pos    (0UL)          /*!< ARC_OEMBL (Bit 0)                                     */
43778  #define R_OFS_DATAFLASH_ARC_OEMBL_ARC_OEMBL_Msk    (0xffffffffUL) /*!< ARC_OEMBL (Bitfield-Mask: 0xffffffff)                 */
43779 
43780 /** @} */ /* End of group PosMask_peripherals */
43781 
43782  #ifdef __cplusplus
43783 }
43784  #endif
43785 
43786 #endif                                 /* R7FA8D1BH_H */
43787 
43788 /** @} */ /* End of group R7FA8D1BH */
43789 
43790 /** @} */ /* End of group Renesas */
43791