1 /*
2  * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5  *
6  * @file     ./out/R7FA6M5BH.h
7  * @brief    CMSIS HeaderFile
8  * @version  1.10.08
9  */
10 
11 /** @addtogroup Renesas Electronics Corporation
12  * @{
13  */
14 
15 /** @addtogroup R7FA6M5BH
16  * @{
17  */
18 
19 #ifndef R7FA6M5BH_H
20  #define R7FA6M5BH_H
21 
22  #ifdef __cplusplus
23 extern "C" {
24  #endif
25 
26 /** @addtogroup Configuration_of_CMSIS
27  * @{
28  */
29 
30 /* =========================================================================================================================== */
31 /* ================                                Interrupt Number Definition                                ================ */
32 /* =========================================================================================================================== */
33 
34 /* =========================================================================================================================== */
35 /* ================                           Processor and Core Peripheral Section                           ================ */
36 /* =========================================================================================================================== */
37 
38 /* ==========================  Configuration of the ARM Cortex-M33 Processor and Core Peripherals  =========================== */
39  #define __CM33_REV                0x0004U /*!< CM33 Core Revision                                                        */
40  #define __NVIC_PRIO_BITS          4       /*!< Number of Bits used for Priority Levels                                   */
41  #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used                              */
42  #define __VTOR_PRESENT            1       /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
43  #define __MPU_PRESENT             1       /*!< MPU present                                                               */
44  #define __FPU_PRESENT             1       /*!< FPU present                                                               */
45  #define __FPU_DP                  0       /*!< Double Precision FPU                                                      */
46  #define __DSP_PRESENT             1       /*!< DSP extension present                                                     */
47  #define __SAUREGION_PRESENT       0       /*!< SAU region present                                                        */
48 
49 /** @} */ /* End of group Configuration_of_CMSIS */
50 
51  #include "core_cm33.h"                    /*!< ARM Cortex-M33 processor and core peripherals                             */
52  #include "system.h"                       /*!< R7FA6M5BH System                                                          */
53 
54  #ifndef __IM                              /*!< Fallback for older CMSIS versions                                         */
55   #define __IM     __I
56  #endif
57  #ifndef __OM                              /*!< Fallback for older CMSIS versions                                         */
58   #define __OM     __O
59  #endif
60  #ifndef __IOM                             /*!< Fallback for older CMSIS versions                                         */
61   #define __IOM    __IO
62  #endif
63 
64 /* ========================================  Start of section using anonymous unions  ======================================== */
65  #if defined(__CC_ARM)
66   #pragma push
67   #pragma anon_unions
68  #elif defined(__ICCARM__)
69   #pragma language=extended
70  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
71   #pragma clang diagnostic push
72   #pragma clang diagnostic ignored "-Wc11-extensions"
73   #pragma clang diagnostic ignored "-Wreserved-id-macro"
74   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
75   #pragma clang diagnostic ignored "-Wnested-anon-types"
76  #elif defined(__GNUC__)
77 
78 /* anonymous unions are enabled by default */
79  #elif defined(__TMS470__)
80 
81 /* anonymous unions are enabled by default */
82  #elif defined(__TASKING__)
83   #pragma warning 586
84  #elif defined(__CSMC__)
85 
86 /* anonymous unions are enabled by default */
87  #else
88   #warning Not supported compiler type
89  #endif
90 
91 /* =========================================================================================================================== */
92 /* ================                              Device Specific Cluster Section                              ================ */
93 /* =========================================================================================================================== */
94 
95 /** @addtogroup Device_Peripheral_clusters
96  * @{
97  */
98 
99 /**
100  * @brief R_BUS_CSa [CSa] (CS Registers)
101  */
102 typedef struct
103 {
104     __IM uint16_t RESERVED;
105 
106     union
107     {
108         __IOM uint16_t MOD;            /*!< (@ 0x00000002) Mode Register                                              */
109 
110         struct
111         {
112             __IOM uint16_t WRMOD : 1;  /*!< [0..0] Write Access Mode Select                                           */
113             uint16_t             : 2;
114             __IOM uint16_t EWENB : 1;  /*!< [3..3] External Wait Enable                                               */
115             uint16_t             : 4;
116             __IOM uint16_t PRENB : 1;  /*!< [8..8] Page Read Access Enable                                            */
117             __IOM uint16_t PWENB : 1;  /*!< [9..9] Page Write Access Enable                                           */
118             uint16_t             : 5;
119             __IOM uint16_t PRMOD : 1;  /*!< [15..15] Page Read Access Mode Select                                     */
120         } MOD_b;
121     };
122 
123     union
124     {
125         __IOM uint32_t WCR1;             /*!< (@ 0x00000004) Wait Control Register 1                                    */
126 
127         struct
128         {
129             __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait Select                                       */
130             uint32_t                : 5;
131             __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait Select                                       */
132             uint32_t                : 5;
133             __IOM uint32_t CSWWAIT  : 5; /*!< [20..16] Normal Write Cycle Wait Select                                   */
134             uint32_t                : 3;
135             __IOM uint32_t CSRWAIT  : 5; /*!< [28..24] Normal Read Cycle Wait Select                                    */
136             uint32_t                : 3;
137         } WCR1_b;
138     };
139 
140     union
141     {
142         __IOM uint32_t WCR2;           /*!< (@ 0x00000008) Wait Control Register 2                                    */
143 
144         struct
145         {
146             __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select                              */
147             uint32_t              : 1;
148             __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select                             */
149             uint32_t              : 1;
150             __IOM uint32_t WDOFF  : 3; /*!< [10..8] Write Data Output Extension Cycle Select                          */
151             uint32_t              : 1;
152             __IOM uint32_t AWAIT  : 2; /*!< [13..12] CS Assert Wait Select                                            */
153             uint32_t              : 2;
154             __IOM uint32_t RDON   : 3; /*!< [18..16] RD Assert Wait Select                                            */
155             uint32_t              : 1;
156             __IOM uint32_t WRON   : 3; /*!< [22..20] WR Assert Wait Select                                            */
157             uint32_t              : 1;
158             __IOM uint32_t WDON   : 3; /*!< [26..24] Write Data Output Wait Select                                    */
159             uint32_t              : 1;
160             __IOM uint32_t CSON   : 3; /*!< [30..28] CS Assert Wait Select                                            */
161             uint32_t              : 1;
162         } WCR2_b;
163     };
164     __IM uint32_t RESERVED1;
165 } R_BUS_CSa_Type;                      /*!< Size = 16 (0x10)                                                          */
166 
167 /**
168  * @brief R_BUS_CSb [CSb] (CS Registers)
169  */
170 typedef struct
171 {
172     __IM uint16_t RESERVED;
173 
174     union
175     {
176         __IOM uint16_t CR;             /*!< (@ 0x00000002) Control Register                                           */
177 
178         struct
179         {
180             __IOM uint16_t EXENB : 1;  /*!< [0..0] Operation Enable                                                   */
181             uint16_t             : 3;
182             __IOM uint16_t BSIZE : 2;  /*!< [5..4] External Bus Width Select                                          */
183             uint16_t             : 2;
184             __IOM uint16_t EMODE : 1;  /*!< [8..8] Endian Mode                                                        */
185             uint16_t             : 3;
186             __IOM uint16_t MPXEN : 1;  /*!< [12..12] Address/Data Multiplexed I/O Interface Select                    */
187             uint16_t             : 3;
188         } CR_b;
189     };
190     __IM uint16_t RESERVED1[3];
191 
192     union
193     {
194         __IOM uint16_t REC;            /*!< (@ 0x0000000A) Recovery Cycle Register                                    */
195 
196         struct
197         {
198             __IOM uint16_t RRCV : 4;   /*!< [3..0] Read Recovery                                                      */
199             uint16_t            : 4;
200             __IOM uint16_t WRCV : 4;   /*!< [11..8] Write Recovery                                                    */
201             uint16_t            : 4;
202         } REC_b;
203     };
204     __IM uint16_t RESERVED2[2];
205 } R_BUS_CSb_Type;                      /*!< Size = 16 (0x10)                                                          */
206 
207 /**
208  * @brief R_BUS_SDRAM [SDRAM] (SDRAM Registers)
209  */
210 typedef struct
211 {
212     union
213     {
214         __IOM uint8_t SDCCR;           /*!< (@ 0x00000000) SDC Control Register                                       */
215 
216         struct
217         {
218             __IOM uint8_t EXENB : 1;   /*!< [0..0] Operation Enable                                                   */
219             uint8_t             : 3;
220             __IOM uint8_t BSIZE : 2;   /*!< [5..4] SDRAM Bus Width Select                                             */
221             uint8_t             : 2;
222         } SDCCR_b;
223     };
224 
225     union
226     {
227         __IOM uint8_t SDCMOD;          /*!< (@ 0x00000001) SDC Mode Register                                          */
228 
229         struct
230         {
231             __IOM uint8_t EMODE : 1;   /*!< [0..0] Endian Mode                                                        */
232             uint8_t             : 7;
233         } SDCMOD_b;
234     };
235 
236     union
237     {
238         __IOM uint8_t SDAMOD;          /*!< (@ 0x00000002) SDRAM Access Mode Register                                 */
239 
240         struct
241         {
242             __IOM uint8_t BE : 1;      /*!< [0..0] Continuous Access Enable                                           */
243             uint8_t          : 7;
244         } SDAMOD_b;
245     };
246     __IM uint8_t  RESERVED;
247     __IM uint32_t RESERVED1[3];
248 
249     union
250     {
251         __IOM uint8_t SDSELF;          /*!< (@ 0x00000010) SDRAM Self-Refresh Control Register                        */
252 
253         struct
254         {
255             __IOM uint8_t SFEN : 1;    /*!< [0..0] SDRAM Self-Refresh Enable                                          */
256             uint8_t            : 7;
257         } SDSELF_b;
258     };
259     __IM uint8_t  RESERVED2;
260     __IM uint16_t RESERVED3;
261 
262     union
263     {
264         __IOM uint16_t SDRFCR;         /*!< (@ 0x00000014) SDRAM Refresh Control Register                             */
265 
266         struct
267         {
268             __IOM uint16_t RFC  : 12;  /*!< [11..0] Auto-Refresh Request Interval Setting                             */
269             __IOM uint16_t REFW : 4;   /*!< [15..12] Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count
270                                         *   Setting. ( REFW+1 Cycles )                                                */
271         } SDRFCR_b;
272     };
273 
274     union
275     {
276         __IOM uint8_t SDRFEN;          /*!< (@ 0x00000016) SDRAM Auto-Refresh Control Register                        */
277 
278         struct
279         {
280             __IOM uint8_t RFEN : 1;    /*!< [0..0] Auto-Refresh Operation Enable                                      */
281             uint8_t            : 7;
282         } SDRFEN_b;
283     };
284     __IM uint8_t  RESERVED4;
285     __IM uint32_t RESERVED5[2];
286 
287     union
288     {
289         __IOM uint8_t SDICR;           /*!< (@ 0x00000020) SDRAM Initialization Sequence Control Register             */
290 
291         struct
292         {
293             __IOM uint8_t INIRQ : 1;   /*!< [0..0] Initialization Sequence Start                                      */
294             uint8_t             : 7;
295         } SDICR_b;
296     };
297     __IM uint8_t  RESERVED6;
298     __IM uint16_t RESERVED7;
299 
300     union
301     {
302         __IOM uint16_t SDIR;           /*!< (@ 0x00000024) SDRAM Initialization Register                              */
303 
304         struct
305         {
306             __IOM uint16_t ARFI : 4;   /*!< [3..0] Initialization Auto-Refresh Interval ( PRF+3 cycles )              */
307             __IOM uint16_t ARFC : 4;   /*!< [7..4] Initialization Auto-Refresh Count                                  */
308             __IOM uint16_t PRC  : 3;   /*!< [10..8] Initialization Precharge Cycle Count ( PRF+3 cycles
309                                         *   )                                                                         */
310             uint16_t : 5;
311         } SDIR_b;
312     };
313     __IM uint16_t RESERVED8;
314     __IM uint32_t RESERVED9[6];
315 
316     union
317     {
318         __IOM uint8_t SDADR;           /*!< (@ 0x00000040) SDRAM Address Register                                     */
319 
320         struct
321         {
322             __IOM uint8_t MXC : 2;     /*!< [1..0] Address Multiplex Select                                           */
323             uint8_t           : 6;
324         } SDADR_b;
325     };
326     __IM uint8_t  RESERVED10;
327     __IM uint16_t RESERVED11;
328 
329     union
330     {
331         __IOM uint32_t SDTR;           /*!< (@ 0x00000044) SDRAM Timing Register                                      */
332 
333         struct
334         {
335             __IOM uint32_t CL  : 3;    /*!< [2..0] SDRAMC Column Latency                                              */
336             uint32_t           : 5;
337             __IOM uint32_t WR  : 1;    /*!< [8..8] Write Recovery Interval                                            */
338             __IOM uint32_t RP  : 3;    /*!< [11..9] Row Precharge Interval ( RP+1 cycles )                            */
339             __IOM uint32_t RCD : 2;    /*!< [13..12] Row Column Latency ( RCD+1 cycles )                              */
340             uint32_t           : 2;
341             __IOM uint32_t RAS : 3;    /*!< [18..16] Row Active Interval                                              */
342             uint32_t           : 13;
343         } SDTR_b;
344     };
345 
346     union
347     {
348         __IOM uint16_t SDMOD;          /*!< (@ 0x00000048) SDRAM Mode Register                                        */
349 
350         struct
351         {
352             __IOM uint16_t MR : 15;    /*!< [14..0] Mode Register Setting                                             */
353             uint16_t          : 1;
354         } SDMOD_b;
355     };
356     __IM uint16_t RESERVED12;
357     __IM uint32_t RESERVED13;
358 
359     union
360     {
361         __IM uint8_t SDSR;             /*!< (@ 0x00000050) SDRAM Status Register                                      */
362 
363         struct
364         {
365             __IM uint8_t MRSST : 1;    /*!< [0..0] Mode Register Setting Status                                       */
366             uint8_t            : 2;
367             __IM uint8_t INIST : 1;    /*!< [3..3] Initialization Status                                              */
368             __IM uint8_t SRFST : 1;    /*!< [4..4] Self-Refresh Transition/Recovery Status                            */
369             uint8_t            : 3;
370         } SDSR_b;
371     };
372     __IM uint8_t  RESERVED14;
373     __IM uint16_t RESERVED15;
374 } R_BUS_SDRAM_Type;                    /*!< Size = 84 (0x54)                                                          */
375 
376 /**
377  * @brief R_BUS_BUSERRa [BUSERRa] (Bus Error Registers)
378  */
379 typedef struct
380 {
381     union
382     {
383         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Error Address Register                                 */
384 
385         struct
386         {
387             __IM uint32_t BERAD : 32;  /*!< [31..0] Bus Error Address                                                 */
388         } ADD_b;
389     };
390 
391     union
392     {
393         union
394         {
395             __IM uint8_t STAT;            /*!< (@ 0x00000004) Bus Error Status Register                                  */
396 
397             struct
398             {
399                 __IM uint8_t ACCSTAT : 1; /*!< [0..0] Error access status                                                */
400                 uint8_t              : 6;
401                 __IM uint8_t ERRSTAT : 1; /*!< [7..7] Bus Error Status                                                   */
402             } STAT_b;
403         };
404 
405         union
406         {
407             __IM uint8_t RW;             /*!< (@ 0x00000004) Bus Error Read Write                                       */
408 
409             struct
410             {
411                 __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access Read/Write Status                                     */
412                 uint8_t             : 7;
413             } RW_b;
414         };
415     };
416     __IM uint8_t  RESERVED;
417     __IM uint16_t RESERVED1;
418     __IM uint32_t RESERVED2[2];
419 } R_BUS_BUSERRa_Type;                  /*!< Size = 16 (0x10)                                                          */
420 
421 /**
422  * @brief R_BUS_BTZFERR [BTZFERR] (Bus TZF Error Registers)
423  */
424 typedef struct
425 {
426     union
427     {
428         __IM uint32_t ADD;               /*!< (@ 0x00000000) BUS TZF Error Address                                      */
429 
430         struct
431         {
432             __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error Address                                */
433         } ADD_b;
434     };
435 
436     union
437     {
438         __IM uint8_t RW;               /*!< (@ 0x00000004) BUS TZF Error Read Write                                   */
439 
440         struct
441         {
442             __IM uint8_t TRWSTAT : 1;  /*!< [0..0] TrustZone filter error access Read/Write Status                    */
443             uint8_t              : 7;
444         } RW_b;
445     };
446     __IM uint8_t  RESERVED;
447     __IM uint16_t RESERVED1;
448     __IM uint32_t RESERVED2[2];
449 } R_BUS_BTZFERR_Type;                  /*!< Size = 16 (0x10)                                                          */
450 
451 /**
452  * @brief R_BUS_BUSERRb [BUSERRb] (Bus Error Registers)
453  */
454 typedef struct
455 {
456     union
457     {
458         __IM uint8_t STAT;              /*!< (@ 0x00000000) Bus Error Status Register                                  */
459 
460         struct
461         {
462             __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave Bus Error Status.                                            */
463             __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
464             uint8_t                : 1;
465             __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status.                                           */
466             __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal Address Access Error Status.                               */
467             __IM uint8_t MSERRSTAT : 1; /*!< [5..5] Master Security Attribution Unit Error Status.                     */
468             uint8_t                : 2;
469         } STAT_b;
470     };
471     __IM uint8_t RESERVED[7];
472 
473     union
474     {
475         __IOM uint8_t CLR;              /*!< (@ 0x00000008) Bus Error Clear Register                                   */
476 
477         struct
478         {
479             __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave Bus Error Clear.                                             */
480             __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Status.                               */
481             uint8_t                : 1;
482             __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear.                                            */
483             __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear.                                */
484             __IOM uint8_t MSERRCLR : 1; /*!< [5..5] Master Security Attribution Unit Error Clear.                      */
485             uint8_t                : 2;
486         } CLR_b;
487     };
488     __IM uint8_t RESERVED1[7];
489 } R_BUS_BUSERRb_Type;                  /*!< Size = 16 (0x10)                                                          */
490 
491 /**
492  * @brief R_BUS_DMACDTCERR [DMACDTCERR] (DMAC/DTC Error Registers)
493  */
494 typedef struct
495 {
496     __IM uint8_t RESERVED[36];
497 
498     union
499     {
500         __IM uint8_t STAT;              /*!< (@ 0x00000024) DMAC/DTC Error Status Register                             */
501 
502         struct
503         {
504             __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status                               */
505             uint8_t                : 7;
506         } STAT_b;
507     };
508     __IM uint8_t RESERVED1[7];
509 
510     union
511     {
512         __IOM uint8_t CLR;              /*!< (@ 0x0000002C) DMAC/DTC Error Clear Register                              */
513 
514         struct
515         {
516             __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear                                */
517             uint8_t                : 7;
518         } CLR_b;
519     };
520 } R_BUS_DMACDTCERR_Type;                /*!< Size = 45 (0x2d)                                                          */
521 
522 /**
523  * @brief R_BUS_BUSSABT0 [BUSSABT0] (Bus Slave Arbitration Control 0 Registers)
524  */
525 typedef struct
526 {
527     __IM uint32_t RESERVED[2];
528 
529     union
530     {
531         __IOM uint32_t MRE0BI;         /*!< (@ 0x00000008) Bus Slave Arbitration Control Register                     */
532 
533         struct
534         {
535             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
536             uint32_t            : 31;
537         } MRE0BI_b;
538     };
539     __IM uint32_t RESERVED1;
540 
541     union
542     {
543         __IOM uint32_t FLBI;           /*!< (@ 0x00000010) Bus Slave Arbitration Control Register                     */
544 
545         struct
546         {
547             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
548             uint32_t            : 31;
549         } FLBI_b;
550     };
551     __IM uint32_t RESERVED2[3];
552 
553     union
554     {
555         __IOM uint32_t S0BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
556 
557         struct
558         {
559             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
560             uint32_t            : 31;
561         } S0BI_b;
562     };
563     __IM uint32_t RESERVED3;
564 
565     union
566     {
567         __IOM uint32_t S1BI;           /*!< (@ 0x00000028) Bus Slave Arbitration Control Register                     */
568 
569         struct
570         {
571             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
572             uint32_t            : 31;
573         } S1BI_b;
574     };
575     __IM uint32_t RESERVED4;
576 
577     union
578     {
579         __IOM uint32_t S2BI;           /*!< (@ 0x00000030) Bus Slave Arbitration Control Register                     */
580 
581         struct
582         {
583             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
584             uint32_t            : 31;
585         } S2BI_b;
586     };
587     __IM uint32_t RESERVED5;
588 
589     union
590     {
591         __IOM uint32_t S3BI;           /*!< (@ 0x00000038) Bus Slave Arbitration Control Register                     */
592 
593         struct
594         {
595             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
596             uint32_t            : 31;
597         } S3BI_b;
598     };
599     __IM uint32_t RESERVED6[3];
600 
601     union
602     {
603         __IOM uint32_t STBYSBI;        /*!< (@ 0x00000048) Bus Slave Arbitration Control Register                     */
604 
605         struct
606         {
607             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
608             uint32_t            : 31;
609         } STBYSBI_b;
610     };
611     __IM uint32_t RESERVED7;
612 
613     union
614     {
615         union
616         {
617             __IOM uint32_t ECBI;         /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
618 
619             struct
620             {
621                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
622                 uint32_t            : 31;
623             } ECBI_b;
624         };
625 
626         union
627         {
628             __IOM uint32_t SPI0BI;       /*!< (@ 0x00000050) Bus Slave Arbitration Control Register                     */
629 
630             struct
631             {
632                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
633                 uint32_t            : 31;
634             } SPI0BI_b;
635         };
636     };
637     __IM uint32_t RESERVED8;
638 
639     union
640     {
641         union
642         {
643             __IOM uint32_t EOBI;         /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
644 
645             struct
646             {
647                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
648                 uint32_t            : 31;
649             } EOBI_b;
650         };
651 
652         union
653         {
654             __IOM uint32_t SPI1BI;       /*!< (@ 0x00000058) Bus Slave Arbitration Control Register                     */
655 
656             struct
657             {
658                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
659                 uint32_t            : 31;
660             } SPI1BI_b;
661         };
662     };
663     __IM uint32_t RESERVED9;
664 
665     union
666     {
667         __IOM uint32_t PBBI;           /*!< (@ 0x00000060) Bus Slave Arbitration Control Register                     */
668 
669         struct
670         {
671             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
672             uint32_t            : 31;
673         } PBBI_b;
674     };
675     __IM uint32_t RESERVED10;
676 
677     union
678     {
679         union
680         {
681             __IOM uint32_t PABI;         /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
682 
683             struct
684             {
685                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
686                 uint32_t            : 31;
687             } PABI_b;
688         };
689 
690         union
691         {
692             __IOM uint32_t CPU0SAHBI;    /*!< (@ 0x00000068) Bus Slave Arbitration Control Register                     */
693 
694             struct
695             {
696                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
697                 uint32_t            : 31;
698             } CPU0SAHBI_b;
699         };
700     };
701     __IM uint32_t RESERVED11;
702 
703     union
704     {
705         union
706         {
707             __IOM uint32_t PIBI;         /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
708 
709             struct
710             {
711                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
712                 uint32_t            : 31;
713             } PIBI_b;
714         };
715 
716         union
717         {
718             __IOM uint32_t CPU1TCMBI;    /*!< (@ 0x00000070) Bus Slave Arbitration Control Register                     */
719 
720             struct
721             {
722                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for slave.                                      */
723                 uint32_t            : 31;
724             } CPU1TCMBI_b;
725         };
726     };
727     __IM uint32_t RESERVED12;
728 
729     union
730     {
731         __IOM uint32_t PSBI;           /*!< (@ 0x00000078) Bus Slave Arbitration Control Register                     */
732 
733         struct
734         {
735             __IOM uint32_t ARBS : 1;   /*!< [0..0] Arbitration Select for slave.                                      */
736             uint32_t            : 31;
737         } PSBI_b;
738     };
739 } R_BUS_BUSSABT0_Type;                 /*!< Size = 124 (0x7c)                                                         */
740 
741 /**
742  * @brief R_BUS_BUSSABT1 [BUSSABT1] (Bus Slave Arbitration Control 1 Registers)
743  */
744 typedef struct
745 {
746     union
747     {
748         union
749         {
750             __IOM uint32_t FHBI;         /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
751 
752             struct
753             {
754                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
755                 uint32_t            : 30;
756             } FHBI_b;
757         };
758 
759         union
760         {
761             __IOM uint32_t MRC0BI;       /*!< (@ 0x00000000) Bus Slave Arbitration Control Register                     */
762 
763             struct
764             {
765                 __IOM uint32_t ARBS : 2; /*!< [1..0] Arbitration Select for slave.                                      */
766                 uint32_t            : 30;
767             } MRC0BI_b;
768         };
769     };
770     __IM uint32_t RESERVED[5];
771 
772     union
773     {
774         __IOM uint32_t S0BI;           /*!< (@ 0x00000018) Bus Slave Arbitration Control Register                     */
775 
776         struct
777         {
778             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
779             uint32_t            : 30;
780         } S0BI_b;
781     };
782     __IM uint32_t RESERVED1;
783 
784     union
785     {
786         __IOM uint32_t S1BI;           /*!< (@ 0x00000020) Bus Slave Arbitration Control Register                     */
787 
788         struct
789         {
790             __IOM uint32_t ARBS : 2;   /*!< [1..0] Arbitration Select for slave.                                      */
791             uint32_t            : 30;
792         } S1BI_b;
793     };
794 } R_BUS_BUSSABT1_Type;                 /*!< Size = 36 (0x24)                                                          */
795 
796 /**
797  * @brief R_BUS_BMSAERR [BMSAERR] (Bus Master Security Attribution Unit Error Address and Read/Write Status registers.)
798  */
799 typedef struct
800 {
801     union
802     {
803         __IM uint32_t ADD;             /*!< (@ 0x00000000) Bus Master Security Attribution Unit Error Address.        */
804 
805         struct
806         {
807             __IM uint32_t MSERAD : 32; /*!< [31..0] Bus Master Security Attribution Unit Error Address.               */
808         } ADD_b;
809     };
810 
811     union
812     {
813         __IM uint8_t RW;                /*!< (@ 0x00000004) BUS Master Security Attribution Unit Error Read
814                                          *                  Write.                                                     */
815 
816         struct
817         {
818             __IM uint8_t MSARWSTAT : 1; /*!< [0..0] Master Security Attribution Unit error access Read/Write
819                                          *   Status.                                                                   */
820             uint8_t : 7;
821         } RW_b;
822     };
823     __IM uint8_t  RESERVED;
824     __IM uint16_t RESERVED1;
825     __IM uint32_t RESERVED2[2];
826 } R_BUS_BMSAERR_Type;                  /*!< Size = 16 (0x10)                                                          */
827 
828 /**
829  * @brief R_BUS_OAD [OAD] (Bus Operation After Detection Registers)
830  */
831 typedef struct
832 {
833     union
834     {
835         __IOM uint16_t BUSOAD;           /*!< (@ 0x00000000) Bus Operation After Detection Register                     */
836 
837         struct
838         {
839             __IOM uint16_t ILERROAD : 1; /*!< [0..0] Illegal address access error operation after detection.            */
840             __IOM uint16_t SLERROAD : 1; /*!< [1..1] Slave bus error operation after detection.                         */
841             __IOM uint16_t BWERROAD : 1; /*!< [2..2] Bufferable write error operation after detection.                  */
842             uint16_t                : 13;
843         } BUSOAD_b;
844     };
845     __IM uint16_t RESERVED;
846 
847     union
848     {
849         __IOM uint16_t BUSOADPT;        /*!< (@ 0x00000004) BUS Operation After Detection Protect Register.            */
850 
851         struct
852         {
853             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of BUSOAD register.                                     */
854             uint16_t               : 7;
855             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
856         } BUSOADPT_b;
857     };
858     __IM uint16_t RESERVED1[5];
859 
860     union
861     {
862         __IOM uint16_t MSAOAD;         /*!< (@ 0x00000010) Master Security Attribution Operation After Detection
863                                         *                  Register.                                                  */
864 
865         struct
866         {
867             __IOM uint16_t OAD : 1;    /*!< [0..0] Master Security Attribution operation after detection.             */
868             uint16_t           : 7;
869             __OM uint16_t KEY  : 8;    /*!< [15..8] Key Code.                                                         */
870         } MSAOAD_b;
871     };
872     __IM uint16_t RESERVED2;
873 
874     union
875     {
876         __IOM uint16_t MSAPT;           /*!< (@ 0x00000014) Master Security Attribution Protect Register.              */
877 
878         struct
879         {
880             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of MSAOAD register.                                     */
881             uint16_t               : 7;
882             __OM uint16_t KEY      : 8; /*!< [15..8] Key code                                                          */
883         } MSAPT_b;
884     };
885 } R_BUS_OAD_Type;                       /*!< Size = 22 (0x16)                                                          */
886 
887 /**
888  * @brief R_BUS_MBWERR [MBWERR] (Master Bufferable Write Error Registers)
889  */
890 typedef struct
891 {
892     union
893     {
894         __IM uint32_t STAT;            /*!< (@ 0x00000000) Bufferable Write Error Status Register                     */
895 
896         struct
897         {
898             __IM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error in 0.                                       */
899             __IM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error in 1.                                       */
900             __IM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error in 2.                                       */
901             __IM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error in 3.                                       */
902             __IM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error in 4.                                       */
903             __IM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error in 5.                                       */
904             __IM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error in 6.                                       */
905             __IM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error in 7.                                       */
906             __IM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error in 8.                                       */
907             __IM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error in 9.                                       */
908             __IM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error in 10.                                    */
909             __IM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error in 11.                                    */
910             __IM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error in 12.                                    */
911             __IM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error in 13.                                    */
912             __IM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error in 14.                                    */
913             __IM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error in 15.                                    */
914             __IM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error in 16.                                    */
915             __IM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error in 17.                                    */
916             __IM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error in 18.                                    */
917             __IM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error in 19.                                    */
918             __IM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error in 20.                                    */
919             __IM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error in 21.                                    */
920             __IM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error in 22.                                    */
921             __IM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error in 23.                                    */
922             __IM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error in 24.                                    */
923             __IM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error in 25.                                    */
924             __IM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error in 26.                                    */
925             __IM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error in 27.                                    */
926             __IM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error in 28.                                    */
927             __IM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error in 29.                                    */
928             __IM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error in 30.                                    */
929             __IM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error in 31.                                    */
930         } STAT_b;
931     };
932     __IM uint32_t RESERVED;
933 
934     union
935     {
936         __IOM uint32_t CLR;             /*!< (@ 0x00000008) Bufferable Write Error Clear Register.                     */
937 
938         struct
939         {
940             __IOM uint32_t BWERR0  : 1; /*!< [0..0] Bufferable Write Error Clear for 0.                                */
941             __IOM uint32_t BWERR1  : 1; /*!< [1..1] Bufferable Write Error Clear for 1.                                */
942             __IOM uint32_t BWERR2  : 1; /*!< [2..2] Bufferable Write Error Clear for 2.                                */
943             __IOM uint32_t BWERR3  : 1; /*!< [3..3] Bufferable Write Error Clear for 3.                                */
944             __IOM uint32_t BWERR4  : 1; /*!< [4..4] Bufferable Write Error Clear for 4.                                */
945             __IOM uint32_t BWERR5  : 1; /*!< [5..5] Bufferable Write Error Clear for 5.                                */
946             __IOM uint32_t BWERR6  : 1; /*!< [6..6] Bufferable Write Error Clear for 6.                                */
947             __IOM uint32_t BWERR7  : 1; /*!< [7..7] Bufferable Write Error Clear for 7.                                */
948             __IOM uint32_t BWERR8  : 1; /*!< [8..8] Bufferable Write Error Clear for 8.                                */
949             __IOM uint32_t BWERR9  : 1; /*!< [9..9] Bufferable Write Error Clear for 9.                                */
950             __IOM uint32_t BWERR10 : 1; /*!< [10..10] Bufferable Write Error Clear for 10.                             */
951             __IOM uint32_t BWERR11 : 1; /*!< [11..11] Bufferable Write Error Clear for 11.                             */
952             __IOM uint32_t BWERR12 : 1; /*!< [12..12] Bufferable Write Error Clear for 12.                             */
953             __IOM uint32_t BWERR13 : 1; /*!< [13..13] Bufferable Write Error Clear for 13.                             */
954             __IOM uint32_t BWERR14 : 1; /*!< [14..14] Bufferable Write Error Clear for 14.                             */
955             __IOM uint32_t BWERR15 : 1; /*!< [15..15] Bufferable Write Error Clear for 15.                             */
956             __IOM uint32_t BWERR16 : 1; /*!< [16..16] Bufferable Write Error Clear for 16.                             */
957             __IOM uint32_t BWERR17 : 1; /*!< [17..17] Bufferable Write Error Clear for 17.                             */
958             __IOM uint32_t BWERR18 : 1; /*!< [18..18] Bufferable Write Error Clear for 18.                             */
959             __IOM uint32_t BWERR19 : 1; /*!< [19..19] Bufferable Write Error Clear for 19.                             */
960             __IOM uint32_t BWERR20 : 1; /*!< [20..20] Bufferable Write Error Clear for 20.                             */
961             __IOM uint32_t BWERR21 : 1; /*!< [21..21] Bufferable Write Error Clear for 21.                             */
962             __IOM uint32_t BWERR22 : 1; /*!< [22..22] Bufferable Write Error Clear for 22.                             */
963             __IOM uint32_t BWERR23 : 1; /*!< [23..23] Bufferable Write Error Clear for 23.                             */
964             __IOM uint32_t BWERR24 : 1; /*!< [24..24] Bufferable Write Error Clear for 24.                             */
965             __IOM uint32_t BWERR25 : 1; /*!< [25..25] Bufferable Write Error Clear for 25.                             */
966             __IOM uint32_t BWERR26 : 1; /*!< [26..26] Bufferable Write Error Clear for 26.                             */
967             __IOM uint32_t BWERR27 : 1; /*!< [27..27] Bufferable Write Error Clear for 27.                             */
968             __IOM uint32_t BWERR28 : 1; /*!< [28..28] Bufferable Write Error Clear for 28.                             */
969             __IOM uint32_t BWERR29 : 1; /*!< [29..29] Bufferable Write Error Clear for 29.                             */
970             __IOM uint32_t BWERR30 : 1; /*!< [30..30] Bufferable Write Error Clear for 30.                             */
971             __IOM uint32_t BWERR31 : 1; /*!< [31..31] Bufferable Write Error Clear for 31.                             */
972         } CLR_b;
973     };
974 } R_BUS_MBWERR_Type;                    /*!< Size = 12 (0xc)                                                           */
975 
976 /**
977  * @brief R_BUS_BUSM [BUSM] (Master Bus Control Registers)
978  */
979 typedef struct
980 {
981     union
982     {
983         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Master Bus Control Register                                */
984 
985         struct
986         {
987             uint16_t             : 15;
988             __IOM uint16_t IERES : 1;  /*!< [15..15] Ignore Error Responses                                           */
989         } CNT_b;
990     };
991     __IM uint16_t RESERVED;
992 } R_BUS_BUSM_Type;                     /*!< Size = 4 (0x4)                                                            */
993 
994 /**
995  * @brief R_BUS_BUSS [BUSS] (Slave Bus Control Register Array)
996  */
997 typedef struct
998 {
999     union
1000     {
1001         __IOM uint16_t CNT;            /*!< (@ 0x00000000) Slave Bus Control Register                                 */
1002 
1003         struct
1004         {
1005             __IOM uint16_t ARBS   : 2; /*!< [1..0] Arbitration Select                                                 */
1006             uint16_t              : 2;
1007             __IOM uint16_t ARBMET : 2; /*!< [5..4] Arbitration Method                                                 */
1008             uint16_t              : 10;
1009         } CNT_b;
1010     };
1011     __IM uint16_t RESERVED;
1012 } R_BUS_BUSS_Type;                     /*!< Size = 4 (0x4)                                                            */
1013 
1014 /**
1015  * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status)
1016  */
1017 typedef struct
1018 {
1019     union
1020     {
1021         __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register             */
1022 
1023         struct
1024         {
1025             __IOM uint32_t NBRP   : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler                                */
1026             __IOM uint32_t NSJW   : 7;  /*!< [16..10] Resynchronization Jump Width                                     */
1027             __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Timing Segment 1                                                 */
1028             __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Timing Segment 2                                                 */
1029         } NCFG_b;
1030     };
1031 
1032     union
1033     {
1034         __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel Control Registers                                  */
1035 
1036         struct
1037         {
1038             __IOM uint32_t CHMDC   : 2; /*!< [1..0] Channel Mode Control                                               */
1039             __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Sleep Request                                              */
1040             __IOM uint32_t RTBO    : 1; /*!< [3..3] Return from Bus-Off                                                */
1041             uint32_t               : 4;
1042             __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
1043             __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
1044             __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
1045             __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
1046             __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
1047             __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
1048             __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
1049             __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
1050             __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission abort Interrupt Enable                              */
1051             __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable               */
1052             __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable          */
1053             __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
1054                                          *   enable                                                                    */
1055             uint32_t            : 1;
1056             __IOM uint32_t BOM  : 2;    /*!< [22..21] Channel Bus-Off Mode                                             */
1057             __IOM uint32_t ERRD : 1;    /*!< [23..23] Channel Error Display                                            */
1058             __IOM uint32_t CTME : 1;    /*!< [24..24] Channel Test Mode Enable                                         */
1059             __IOM uint32_t CTMS : 2;    /*!< [26..25] Channel Test Mode Select                                         */
1060             __IOM uint32_t TRWE : 1;    /*!< [27..27] TEC/REC Write Enable                                             */
1061             __IOM uint32_t TRH  : 1;    /*!< [28..28] TEC/REC Hold                                                     */
1062             __IOM uint32_t TRR  : 1;    /*!< [29..29] TEC/REC Reset                                                    */
1063             __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test                                                   */
1064             __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode                                        */
1065         } CTR_b;
1066     };
1067 
1068     union
1069     {
1070         __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel Status Registers                                   */
1071 
1072         struct
1073         {
1074             __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel RESET Status                                               */
1075             __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel HALT Status                                                */
1076             __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status                                               */
1077             __IM uint32_t  EPSTS   : 1; /*!< [3..3] Channel Error Passive Status                                       */
1078             __IM uint32_t  BOSTS   : 1; /*!< [4..4] Channel Bus-Off Status                                             */
1079             __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Channel Transmit Status                                            */
1080             __IM uint32_t  RECSTS  : 1; /*!< [6..6] Channel Receive Status                                             */
1081             __IM uint32_t  COMSTS  : 1; /*!< [7..7] Channel Communication Status                                       */
1082             __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
1083             uint32_t               : 7;
1084             __IM uint32_t  REC     : 8; /*!< [23..16] Reception Error Count                                            */
1085             __IOM uint32_t TEC     : 8; /*!< [31..24] Transmission Error Count                                         */
1086         } STS_b;
1087     };
1088 
1089     union
1090     {
1091         __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel Error Flag Registers                               */
1092 
1093         struct
1094         {
1095             __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
1096             __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
1097             __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
1098             __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
1099             __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
1100             __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
1101             __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
1102             __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
1103             __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error                                                        */
1104             __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error                                                         */
1105             __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error                                                */
1106             __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error                                                        */
1107             __IOM uint32_t B1ERR : 1;  /*!< [12..12] Bit 1 Error                                                      */
1108             __IOM uint32_t B0ERR : 1;  /*!< [13..13] Bit 0 Error                                                      */
1109             __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error                                      */
1110             uint32_t             : 1;
1111             __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value                                               */
1112             uint32_t             : 1;
1113         } ERFL_b;
1114     };
1115 } R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
1116 
1117 /**
1118  * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
1119  */
1120 typedef struct
1121 {
1122     union
1123     {
1124         __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register                */
1125 
1126         struct
1127         {
1128             __IOM uint32_t DBRP   : 8; /*!< [7..0] Channel Data Baud Rate Prescaler                                   */
1129             __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1                                                  */
1130             uint32_t              : 3;
1131             __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2                                                 */
1132             uint32_t              : 4;
1133             __IOM uint32_t DSJW   : 4; /*!< [27..24] Resynchronization Jump Width                                     */
1134             uint32_t              : 4;
1135         } DCFG_b;
1136     };
1137 
1138     union
1139     {
1140         __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel CAN-FD Configuration Register                      */
1141 
1142         struct
1143         {
1144             __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
1145             uint32_t              : 5;
1146             __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration                */
1147             __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
1148             __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
1149             uint32_t              : 5;
1150             __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
1151             __IOM uint32_t GWEN   : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable            */
1152             __IOM uint32_t GWFDF  : 1; /*!< [25..25] Gateway FDF configuration bit                                    */
1153             __IOM uint32_t GWBRS  : 1; /*!< [26..26] Gateway BRS configuration bit                                    */
1154             uint32_t              : 1;
1155             __IOM uint32_t FDOE   : 1; /*!< [28..28] FD only enable                                                   */
1156             __IOM uint32_t REFE   : 1; /*!< [29..29] RX edge filter enable                                            */
1157             __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN only enable                                        */
1158             __IOM uint32_t CFDTE  : 1; /*!< [31..31] CAN-FD frame Distinction enable                                  */
1159         } FDCFG_b;
1160     };
1161 
1162     union
1163     {
1164         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel CAN-FD Control Register                            */
1165 
1166         struct
1167         {
1168             __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
1169             __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
1170             uint32_t              : 30;
1171         } FDCTR_b;
1172     };
1173 
1174     union
1175     {
1176         __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel CAN-FD Status Register                             */
1177 
1178         struct
1179         {
1180             __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
1181             __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error occurrence counter overflow                                  */
1182             __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful occurrence counter overflow                             */
1183             uint32_t             : 5;
1184             __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
1185             __IM uint32_t  EOC   : 8;  /*!< [23..16] Error occurrence counter register                                */
1186             __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful occurrence counter register                           */
1187         } FDSTS_b;
1188     };
1189 
1190     union
1191     {
1192         __IOM uint32_t FDCRC;          /*!< (@ 0x00000010) Channel CAN-FD CRC Register                                */
1193 
1194         struct
1195         {
1196             __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value                                                */
1197             uint32_t             : 3;
1198             __IM uint32_t SCNT   : 4;  /*!< [27..24] Stuff bit count                                                  */
1199             uint32_t             : 4;
1200         } FDCRC_b;
1201     };
1202     __IM uint32_t RESERVED;
1203 
1204     union
1205     {
1206         __IOM uint32_t BLCT;           /*!< (@ 0x00000018) Channel Bus load Control Register                          */
1207 
1208         struct
1209         {
1210             __IOM uint32_t BLCE : 1;   /*!< [0..0] BUS Load counter Enable                                            */
1211             uint32_t            : 7;
1212             __OM uint32_t BLCLD : 1;   /*!< [8..8] BUS Load counter load                                              */
1213             uint32_t            : 23;
1214         } BLCT_b;
1215     };
1216 
1217     union
1218     {
1219         __IOM uint32_t BLSTS;          /*!< (@ 0x0000001C) Channel Bus load Status Register                           */
1220 
1221         struct
1222         {
1223             uint32_t          : 3;
1224             __IM uint32_t BLC : 29;    /*!< [31..3] BUS Load counter Status                                           */
1225         } BLSTS_b;
1226     };
1227 } R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
1228 
1229 /**
1230  * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
1231  */
1232 typedef struct
1233 {
1234     union
1235     {
1236         __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers                 */
1237 
1238         struct
1239         {
1240             __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
1241             __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
1242             __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
1243             __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
1244         } ID_b;
1245     };
1246 
1247     union
1248     {
1249         __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers               */
1250 
1251         struct
1252         {
1253             __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
1254             __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
1255             __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
1256             __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
1257         } M_b;
1258     };
1259 
1260     union
1261     {
1262         __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers          */
1263 
1264         struct
1265         {
1266             __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
1267             __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination
1268                                           *   0                                                                         */
1269             __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination
1270                                           *   1                                                                         */
1271             __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination
1272                                           *   2                                                                         */
1273             __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
1274             __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
1275                                           *   Pointer                                                                   */
1276             uint32_t               : 2;
1277             __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
1278             __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field                      */
1279         } P0_b;
1280     };
1281 
1282     union
1283     {
1284         __IOM uint32_t P1;               /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers          */
1285 
1286         struct
1287         {
1288             __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer              */
1289             uint32_t               : 18;
1290         } P1_b;
1291     };
1292 } R_CANFD_CFDGAFL_Type;                  /*!< Size = 16 (0x10)                                                          */
1293 
1294 /**
1295  * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
1296  */
1297 typedef struct
1298 {
1299     union
1300     {
1301         __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
1302 
1303         struct
1304         {
1305             __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
1306             __IM uint32_t BN   : 7;    /*!< [9..3] Buffer No.                                                         */
1307             uint32_t           : 5;
1308             __IM uint32_t TGW  : 1;    /*!< [15..15] Transmit Gateway Buffer indication                               */
1309             __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
1310         } ACC0_b;
1311     };
1312 
1313     union
1314     {
1315         __IOM uint32_t ACC1;           /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
1316 
1317         struct
1318         {
1319             __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
1320             __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
1321             uint32_t           : 14;
1322         } ACC1_b;
1323     };
1324 } R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
1325 
1326 /**
1327  * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers)
1328  */
1329 typedef struct
1330 {
1331     union
1332     {
1333         __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
1334 
1335         struct
1336         {
1337             __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
1338             uint32_t            : 1;
1339             __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Frame                                      */
1340             __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
1341         } ID_b;
1342     };
1343 
1344     union
1345     {
1346         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
1347 
1348         struct
1349         {
1350             __IM uint32_t RMTS  : 16;  /*!< [15..0] RX Message Buffer Timestamp Field                                 */
1351             uint32_t            : 12;
1352             __IM uint32_t RMDLC : 4;   /*!< [31..28] RX Message Buffer DLC Field                                      */
1353         } PTR_b;
1354     };
1355 
1356     union
1357     {
1358         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
1359 
1360         struct
1361         {
1362             __IM uint32_t RMESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1363             __IM uint32_t RMBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1364             __IM uint32_t RMFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1365             uint32_t            : 5;
1366             __IM uint32_t RMIFL : 2;   /*!< [9..8] RX Message Buffer Information Label Field                          */
1367             uint32_t            : 6;
1368             __IM uint32_t RMPTR : 16;  /*!< [31..16] RX Message Buffer Pointer Field                                  */
1369         } FDSTS_b;
1370     };
1371 
1372     union
1373     {
1374         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers                     */
1375 
1376         struct
1377         {
1378             __IM uint8_t RMDB : 8;     /*!< [7..0] RX Message Buffer Data Byte                                        */
1379         } DF_b[64];
1380     };
1381     __IM uint32_t RESERVED[13];
1382 } R_CANFD_CFDRM_Type;                  /*!< Size = 128 (0x80)                                                         */
1383 
1384 /**
1385  * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
1386  */
1387 typedef struct
1388 {
1389     union
1390     {
1391         __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register                                 */
1392 
1393         struct
1394         {
1395             __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
1396             uint32_t            : 1;
1397             __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR Frame                                         */
1398             __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE Bit                                           */
1399         } ID_b;
1400     };
1401 
1402     union
1403     {
1404         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register                            */
1405 
1406         struct
1407         {
1408             __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Field                                           */
1409             uint32_t            : 12;
1410             __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
1411         } PTR_b;
1412     };
1413 
1414     union
1415     {
1416         __IM uint32_t FDSTS;           /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register                      */
1417 
1418         struct
1419         {
1420             __IM uint32_t RFESI : 1;   /*!< [0..0] Error State Indicator bit                                          */
1421             __IM uint32_t RFBRS : 1;   /*!< [1..1] Bit Rate Switch bit                                                */
1422             __IM uint32_t RFFDF : 1;   /*!< [2..2] CAN FD Format bit                                                  */
1423             uint32_t            : 5;
1424             __IM uint32_t RFIFL : 2;   /*!< [9..8] RX FIFO Buffer Information Label Field                             */
1425             uint32_t            : 6;
1426             __IM uint32_t RFPTR : 16;  /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
1427         } FDSTS_b;
1428     };
1429 
1430     union
1431     {
1432         __IM uint8_t DF[64];           /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers                        */
1433 
1434         struct
1435         {
1436             __IM uint8_t RFDB : 8;     /*!< [7..0] RX FIFO Buffer Data Byte                                           */
1437         } DF_b[64];
1438     };
1439     __IM uint32_t RESERVED[13];
1440 } R_CANFD_CFDRF_Type;                  /*!< Size = 128 (0x80)                                                         */
1441 
1442 /**
1443  * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
1444  */
1445 typedef struct
1446 {
1447     union
1448     {
1449         __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
1450 
1451         struct
1452         {
1453             __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
1454             uint32_t             : 1;
1455             __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR Frame                                     */
1456             __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE Bit                                       */
1457         } ID_b;
1458     };
1459 
1460     union
1461     {
1462         __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register                        */
1463 
1464         struct
1465         {
1466             __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Field                                       */
1467             uint32_t             : 12;
1468             __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
1469         } PTR_b;
1470     };
1471 
1472     union
1473     {
1474         __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register                  */
1475 
1476         struct
1477         {
1478             __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1479             __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1480             __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1481             uint32_t             : 5;
1482             __IOM uint32_t CFIFL : 2;  /*!< [9..8] Common FIFO Buffer Information Label Field                         */
1483             uint32_t             : 6;
1484             __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
1485         } FDSTS_b;
1486     };
1487 
1488     union
1489     {
1490         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers                    */
1491 
1492         struct
1493         {
1494             __IOM uint8_t CFDB : 8;    /*!< [7..0] Common FIFO Buffer Data Byte                                       */
1495         } DF_b[64];
1496     };
1497     __IM uint32_t RESERVED[13];
1498 } R_CANFD_CFDCF_Type;                  /*!< Size = 128 (0x80)                                                         */
1499 
1500 /**
1501  * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers)
1502  */
1503 typedef struct
1504 {
1505     union
1506     {
1507         __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register                              */
1508 
1509         struct
1510         {
1511             __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
1512             uint32_t             : 1;
1513             __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR Frame                                      */
1514             __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE Bit                                        */
1515         } ID_b;
1516     };
1517 
1518     union
1519     {
1520         __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register                         */
1521 
1522         struct
1523         {
1524             __IOM uint32_t TMTS  : 16; /*!< [15..0] TX Message Buffer Timestamp Field                                 */
1525             uint32_t             : 12;
1526             __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
1527         } PTR_b;
1528     };
1529 
1530     union
1531     {
1532         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register                  */
1533 
1534         struct
1535         {
1536             __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
1537             __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
1538             __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
1539             uint32_t             : 5;
1540             __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
1541             uint32_t             : 6;
1542             __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
1543         } FDCTR_b;
1544     };
1545 
1546     union
1547     {
1548         __IOM uint8_t DF[64];          /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers                     */
1549 
1550         struct
1551         {
1552             __IOM uint8_t TMDB : 8;    /*!< [7..0] TX Message Buffer Data Byte                                        */
1553         } DF_b[64];
1554     };
1555     __IM uint32_t RESERVED[13];
1556 } R_CANFD_CFDTM_Type;                  /*!< Size = 128 (0x80)                                                         */
1557 
1558 /**
1559  * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register)
1560  */
1561 typedef struct
1562 {
1563     union
1564     {
1565         __IOM uint8_t BY;              /*!< (@ 0x00000000) Event Link Software Event Generation Register              */
1566 
1567         struct
1568         {
1569             __OM uint8_t SEG : 1;      /*!< [0..0] Software Event Generation                                          */
1570             uint8_t          : 5;
1571             __IOM uint8_t WE : 1;      /*!< [6..6] SEG Bit Write Enable                                               */
1572             __OM uint8_t  WI : 1;      /*!< [7..7] ELSEGR Register Write Disable                                      */
1573         } BY_b;
1574     };
1575     __IM uint8_t RESERVED;
1576 } R_ELC_ELSEGR_Type;                   /*!< Size = 2 (0x2)                                                            */
1577 
1578 /**
1579  * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..22])
1580  */
1581 typedef struct
1582 {
1583     union
1584     {
1585         __IOM uint16_t HA;             /*!< (@ 0x00000000) Event Link Setting Register                                */
1586 
1587         struct
1588         {
1589             __IOM uint16_t ELS : 9;    /*!< [8..0] Event Link Select                                                  */
1590             uint16_t           : 7;
1591         } HA_b;
1592     };
1593     __IM uint16_t RESERVED;
1594 } R_ELC_ELSR_Type;                     /*!< Size = 4 (0x4)                                                            */
1595 
1596 /**
1597  * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
1598  */
1599 typedef struct
1600 {
1601     union
1602     {
1603         __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L                                   */
1604 
1605         struct
1606         {
1607             __IOM uint8_t SVA : 8;     /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit
1608                                         *   Address = { SVA9,SVA8,SVA[7:0] }                                          */
1609         } L_b;
1610     };
1611 
1612     union
1613     {
1614         __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U                                   */
1615 
1616         struct
1617         {
1618             __IOM uint8_t FS   : 1;    /*!< [0..0] 7-Bit/10-Bit Address Format Selection                              */
1619             __IOM uint8_t SVA8 : 1;    /*!< [1..1] 10-Bit Address(bit8)                                               */
1620             __IOM uint8_t SVA9 : 1;    /*!< [2..2] 10-Bit Address(bit9)                                               */
1621             uint8_t            : 5;
1622         } U_b;
1623     };
1624 } R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
1625 
1626 /**
1627  * @brief R_MPU_MMPU_GROUP_REGION [REGION] (Address region control)
1628  */
1629 typedef struct
1630 {
1631     union
1632     {
1633         __IOM uint16_t AC;             /*!< (@ 0x00000000) Access Control Register                                    */
1634 
1635         struct
1636         {
1637             __IOM uint16_t ENABLE : 1; /*!< [0..0] Region enable                                                      */
1638             __IOM uint16_t RP     : 1; /*!< [1..1] Read protection                                                    */
1639             __IOM uint16_t WP     : 1; /*!< [2..2] Write protection                                                   */
1640             __IOM uint16_t PP     : 1; /*!< [3..3] Privilege protection                                               */
1641             uint16_t              : 12;
1642         } AC_b;
1643     };
1644     __IM uint16_t RESERVED;
1645 
1646     union
1647     {
1648         __IOM uint32_t S;              /*!< (@ 0x00000004) Start Address Register                                     */
1649 
1650         struct
1651         {
1652             __IOM uint32_t MMPUS : 32; /*!< [31..0] Address where the region starts, for use in region determination.
1653                                         *   NOTE: Some low-order bits are fixed to 0.                                 */
1654         } S_b;
1655     };
1656 
1657     union
1658     {
1659         __IOM uint32_t E;              /*!< (@ 0x00000008) End Address Register                                       */
1660 
1661         struct
1662         {
1663             __IOM uint32_t MMPUE : 32; /*!< [31..0] Region end address registerAddress where the region
1664                                         *   end, for use in region determination. NOTE: Some low-order
1665                                         *   bits are fixed to 1.                                                      */
1666         } E_b;
1667     };
1668     __IM uint32_t RESERVED1;
1669 } R_MPU_MMPU_GROUP_REGION_Type;        /*!< Size = 16 (0x10)                                                          */
1670 
1671 /**
1672  * @brief R_MPU_MMPU_GROUP [GROUP] ([DMAC0..NPU] MMPU Registers)
1673  */
1674 typedef struct
1675 {
1676     union
1677     {
1678         __IOM uint16_t EN;             /*!< (@ 0x00000000) MMPU enable register                                       */
1679 
1680         struct
1681         {
1682             __IOM uint16_t ENABLE : 1; /*!< [0..0] Bus master MPU of DMAC enable                                      */
1683             uint16_t              : 7;
1684             __OM uint16_t KEY     : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1685                                         *   stored.                                                                   */
1686         } EN_b;
1687     };
1688     __IM uint16_t RESERVED;
1689 
1690     union
1691     {
1692         __IOM uint16_t ENPT;            /*!< (@ 0x00000004) MMPU enable protect register                               */
1693 
1694         struct
1695         {
1696             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register EN                                          */
1697             uint16_t               : 7;
1698             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1699                                          *   stored.                                                                   */
1700         } ENPT_b;
1701     };
1702     __IM uint16_t RESERVED1;
1703 
1704     union
1705     {
1706         __IOM uint16_t RPT;             /*!< (@ 0x00000008) MMPU Regions Protect Register Non-Secure                   */
1707 
1708         struct
1709         {
1710             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
1711             uint16_t               : 7;
1712             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1713                                          *   stored.                                                                   */
1714         } RPT_b;
1715     };
1716     __IM uint16_t RESERVED2;
1717 
1718     union
1719     {
1720         __IOM uint16_t RPT_SEC;         /*!< (@ 0x0000000C) MMPU Regions Protect Register Secure (DMAC only)           */
1721 
1722         struct
1723         {
1724             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
1725             uint16_t               : 7;
1726             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1727                                          *   stored.                                                                   */
1728         } RPT_SEC_b;
1729     };
1730     __IM uint16_t RESERVED3;
1731     __IM uint32_t RESERVED4[60];
1732     __IOM R_MPU_MMPU_GROUP_REGION_Type REGION[8]; /*!< (@ 0x00000100) Address region control                                     */
1733     __IM uint32_t RESERVED5[32];
1734 } R_MPU_MMPU_GROUP_Type;                          /*!< Size = 512 (0x200)                                                        */
1735 
1736 /**
1737  * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor)
1738  */
1739 typedef struct
1740 {
1741     union
1742     {
1743         __IOM uint16_t OAD;            /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection
1744                                         *                  Register                                                   */
1745 
1746         struct
1747         {
1748             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
1749             uint16_t           : 7;
1750             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
1751                                         *   stored.                                                                   */
1752         } OAD_b;
1753     };
1754     __IM uint16_t RESERVED;
1755 
1756     union
1757     {
1758         __IOM uint16_t CTL;            /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register              */
1759 
1760         struct
1761         {
1762             __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable                                       */
1763             uint16_t              : 7;
1764             __IOM uint16_t ERROR  : 1; /*!< [8..8] Stack Pointer Monitor Error Flag                                   */
1765             uint16_t              : 7;
1766         } CTL_b;
1767     };
1768 
1769     union
1770     {
1771         __IOM uint16_t PT;              /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register                  */
1772 
1773         struct
1774         {
1775             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE)           */
1776             uint16_t               : 7;
1777             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
1778                                          *   stored.                                                                   */
1779         } PT_b;
1780     };
1781 
1782     union
1783     {
1784         __IOM uint32_t SA;                /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register               */
1785 
1786         struct
1787         {
1788             __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region
1789                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF
1790                                            *   The low-order 2 bits are fixed to 0.                                      */
1791         } SA_b;
1792     };
1793 
1794     union
1795     {
1796         __IOM uint32_t EA;                /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register                 */
1797 
1798         struct
1799         {
1800             __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region
1801                                            *   starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF
1802                                            *   The low-order 2 bits are fixed to 1.                                      */
1803         } EA_b;
1804     };
1805 } R_MPU_SPMON_SP_Type;                    /*!< Size = 16 (0x10)                                                          */
1806 
1807 /**
1808  * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects)
1809  */
1810 typedef struct
1811 {
1812     union
1813     {
1814         union
1815         {
1816             __IOM uint32_t PmnPFS;        /*!< (@ 0x00000000) Pin Function Control Register                              */
1817 
1818             struct
1819             {
1820                 __IOM uint32_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1821                 __IM uint32_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1822                 __IOM uint32_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1823                 uint32_t             : 1;
1824                 __IOM uint32_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1825                 __IOM uint32_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1826                 __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1827                 uint32_t             : 3;
1828                 __IOM uint32_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
1829                 __IOM uint32_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
1830                 __IOM uint32_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
1831                 __IOM uint32_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
1832                 __IOM uint32_t PMR   : 1; /*!< [16..16] Port Mode Control                                                */
1833                 uint32_t             : 7;
1834                 __IOM uint32_t PSEL  : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral
1835                                            *   function. For individual pin functions, see the MPC table                 */
1836                 uint32_t : 3;
1837             } PmnPFS_b;
1838         };
1839 
1840         struct
1841         {
1842             union
1843             {
1844                 struct
1845                 {
1846                     __IM uint16_t RESERVED;
1847 
1848                     union
1849                     {
1850                         __IOM uint16_t PmnPFS_HA;     /*!< (@ 0x00000002) Pin Function Control Register                              */
1851 
1852                         struct
1853                         {
1854                             __IOM uint16_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1855                             __IM uint16_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1856                             __IOM uint16_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1857                             uint16_t             : 1;
1858                             __IOM uint16_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1859                             __IOM uint16_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1860                             __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1861                             uint16_t             : 3;
1862                             __IOM uint16_t DSCR  : 2; /*!< [11..10] Drive Strength Control Register                                  */
1863                             __IOM uint16_t EOFR  : 2; /*!< [13..12] Event on Falling/Rising                                          */
1864                             __IOM uint16_t ISEL  : 1; /*!< [14..14] IRQ input enable                                                 */
1865                             __IOM uint16_t ASEL  : 1; /*!< [15..15] Analog Input enable                                              */
1866                         } PmnPFS_HA_b;
1867                     };
1868                 };
1869 
1870                 struct
1871                 {
1872                     __IM uint16_t RESERVED1;
1873                     __IM uint8_t  RESERVED2;
1874 
1875                     union
1876                     {
1877                         __IOM uint8_t PmnPFS_BY;     /*!< (@ 0x00000003) Pin Function Control Register                              */
1878 
1879                         struct
1880                         {
1881                             __IOM uint8_t PODR  : 1; /*!< [0..0] Port Output Data                                                   */
1882                             __IM uint8_t  PIDR  : 1; /*!< [1..1] Port Input Data                                                    */
1883                             __IOM uint8_t PDR   : 1; /*!< [2..2] Port Direction                                                     */
1884                             uint8_t             : 1;
1885                             __IOM uint8_t PCR   : 1; /*!< [4..4] Pull-up Control                                                    */
1886                             __IOM uint8_t PIM   : 1; /*!< [5..5] Port Input Mode Control                                            */
1887                             __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control                                       */
1888                             uint8_t             : 1;
1889                         } PmnPFS_BY_b;
1890                     };
1891                 };
1892             };
1893         };
1894     };
1895 } R_PFS_PORT_PIN_Type;                 /*!< Size = 4 (0x4)                                                            */
1896 
1897 /**
1898  * @brief R_PFS_PORT [PORT] (Port [0..14])
1899  */
1900 typedef struct
1901 {
1902     __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects                                       */
1903 } R_PFS_PORT_Type;                     /*!< Size = 64 (0x40)                                                          */
1904 
1905 /**
1906  * @brief R_PFS_VLSEL [VLSEL] (VLSEL)
1907  */
1908 typedef struct
1909 {
1910     __IM uint8_t RESERVED[389];
1911 
1912     union
1913     {
1914         __IOM uint8_t VL1SEL;          /*!< (@ 0x00000185) VL1 Select Control Register                                */
1915 
1916         struct
1917         {
1918             __IOM uint8_t SELVL : 1;   /*!< [0..0] VL1 Voltage Connection Switching Control                           */
1919             uint8_t             : 7;
1920         } VL1SEL_b;
1921     };
1922 } R_PFS_VLSEL_Type;                    /*!< Size = 390 (0x186)                                                        */
1923 
1924 /**
1925  * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register)
1926  */
1927 typedef struct
1928 {
1929     __IOM uint16_t PMSAR;              /*!< (@ 0x00000000) Port Security Attribution Register                         */
1930 } R_PMISC_PMSAR_Type;                  /*!< Size = 2 (0x2)                                                            */
1931 
1932 /**
1933  * @brief R_RTC_RTCCR [RTCCR] (Time Capture Control Register)
1934  */
1935 typedef struct
1936 {
1937     union
1938     {
1939         __IOM uint8_t RTCCR;           /*!< (@ 0x00000000) Time Capture Control Register                              */
1940 
1941         struct
1942         {
1943             __IOM uint8_t TCCT : 2;    /*!< [1..0] Time Capture Control                                               */
1944             __IM uint8_t  TCST : 1;    /*!< [2..2] Time Capture Status                                                */
1945             uint8_t            : 1;
1946             __IOM uint8_t TCNF : 2;    /*!< [5..4] Time Capture Noise Filter Control                                  */
1947             uint8_t            : 1;
1948             __IOM uint8_t TCEN : 1;    /*!< [7..7] Time Capture Event Input Pin Enable                                */
1949         } RTCCR_b;
1950     };
1951     __IM uint8_t RESERVED;
1952 } R_RTC_RTCCR_Type;                    /*!< Size = 2 (0x2)                                                            */
1953 
1954 /**
1955  * @brief R_RTC_CP [CP] (Capture registers)
1956  */
1957 typedef struct
1958 {
1959     __IM uint8_t RESERVED[2];
1960 
1961     union
1962     {
1963         union
1964         {
1965             __IM uint8_t RSEC;          /*!< (@ 0x00000002) Second Capture Register                                    */
1966 
1967             struct
1968             {
1969                 __IM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Capture Capture value for the ones place of
1970                                          *   seconds                                                                   */
1971                 __IM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Capture Capture value for the tens place of
1972                                          *   seconds                                                                   */
1973                 uint8_t : 1;
1974             } RSEC_b;
1975         };
1976 
1977         union
1978         {
1979             __IM uint8_t BCNT0;           /*!< (@ 0x00000002) BCNT0 Capture Register                                     */
1980 
1981             struct
1982             {
1983                 __IM uint8_t BCNT0CP : 8; /*!< [7..0] BCNT0CP is a read-only register that captures the BCNT0
1984                                            *   value when a time capture event is detected.                              */
1985             } BCNT0_b;
1986         };
1987     };
1988     __IM uint8_t RESERVED1;
1989 
1990     union
1991     {
1992         union
1993         {
1994             __IM uint8_t RMIN;          /*!< (@ 0x00000004) Minute Capture Register                                    */
1995 
1996             struct
1997             {
1998                 __IM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
1999                                          *   minutes                                                                   */
2000                 __IM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Capture Capture value for the tens place of
2001                                          *   minutes                                                                   */
2002                 uint8_t : 1;
2003             } RMIN_b;
2004         };
2005 
2006         union
2007         {
2008             __IM uint8_t BCNT1;           /*!< (@ 0x00000004) BCNT1 Capture Register                                     */
2009 
2010             struct
2011             {
2012                 __IM uint8_t BCNT1CP : 8; /*!< [7..0] BCNT1CP is a read-only register that captures the BCNT1
2013                                            *   value when a time capture event is detected.                              */
2014             } BCNT1_b;
2015         };
2016     };
2017     __IM uint8_t RESERVED2;
2018 
2019     union
2020     {
2021         union
2022         {
2023             __IM uint8_t RHR;          /*!< (@ 0x00000006) Hour Capture Register                                      */
2024 
2025             struct
2026             {
2027                 __IM uint8_t HR1 : 4;  /*!< [3..0] 1-Minute Capture Capture value for the ones place of
2028                                         *   minutes                                                                   */
2029                 __IM uint8_t HR10 : 2; /*!< [5..4] 10-Minute Capture Capture value for the tens place of
2030                                         *   minutes                                                                   */
2031                 __IM uint8_t PM : 1;   /*!< [6..6] A.m./p.m. select for time counter setting.                         */
2032                 uint8_t         : 1;
2033             } RHR_b;
2034         };
2035 
2036         union
2037         {
2038             __IM uint8_t BCNT2;           /*!< (@ 0x00000006) BCNT2 Capture Register                                     */
2039 
2040             struct
2041             {
2042                 __IM uint8_t BCNT2CP : 8; /*!< [7..0] BCNT2CP is a read-only register that captures the BCNT2
2043                                            *   value when a time capture event is detected.                              */
2044             } BCNT2_b;
2045         };
2046     };
2047     __IM uint8_t RESERVED3[3];
2048 
2049     union
2050     {
2051         union
2052         {
2053             __IM uint8_t RDAY;           /*!< (@ 0x0000000A) Date Capture Register                                      */
2054 
2055             struct
2056             {
2057                 __IM uint8_t DATE1  : 4; /*!< [3..0] 1-Day Capture Capture value for the ones place of minutes          */
2058                 __IM uint8_t DATE10 : 2; /*!< [5..4] 10-Day Capture Capture value for the tens place of minutes         */
2059                 uint8_t             : 2;
2060             } RDAY_b;
2061         };
2062 
2063         union
2064         {
2065             __IM uint8_t BCNT3;           /*!< (@ 0x0000000A) BCNT3 Capture Register                                     */
2066 
2067             struct
2068             {
2069                 __IM uint8_t BCNT3CP : 8; /*!< [7..0] BCNT3CP is a read-only register that captures the BCNT3
2070                                            *   value when a time capture event is detected.                              */
2071             } BCNT3_b;
2072         };
2073     };
2074     __IM uint8_t RESERVED4;
2075 
2076     union
2077     {
2078         __IM uint8_t RMON;             /*!< (@ 0x0000000C) Month Capture Register                                     */
2079 
2080         struct
2081         {
2082             __IM uint8_t MON1  : 4;    /*!< [3..0] 1-Month Capture Capture value for the ones place of months         */
2083             __IM uint8_t MON10 : 1;    /*!< [4..4] 10-Month Capture Capture value for the tens place of
2084                                         *   months                                                                    */
2085             uint8_t : 3;
2086         } RMON_b;
2087     };
2088     __IM uint8_t RESERVED5[3];
2089 } R_RTC_CP_Type;                       /*!< Size = 16 (0x10)                                                          */
2090 
2091 /**
2092  * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
2093  */
2094 typedef struct
2095 {
2096     union
2097     {
2098         __IOM uint16_t E;              /*!< (@ 0x00000000) Pipe Transaction Counter Enable Register                   */
2099 
2100         struct
2101         {
2102             uint16_t             : 8;
2103             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
2104             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
2105             uint16_t             : 6;
2106         } E_b;
2107     };
2108 
2109     union
2110     {
2111         __IOM uint16_t N;               /*!< (@ 0x00000002) Pipe Transaction Counter Register                          */
2112 
2113         struct
2114         {
2115             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
2116         } N_b;
2117     };
2118 } R_USB_FS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
2119 
2120 /**
2121  * @brief R_USB_HS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers)
2122  */
2123 typedef struct
2124 {
2125     union
2126     {
2127         __IOM uint16_t E;              /*!< (@ 0x00000000) PIPE Transaction Counter Enable Register                   */
2128 
2129         struct
2130         {
2131             uint16_t             : 8;
2132             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter ClearSetting this bit to 1 allows
2133                                         *   clearing the transaction counter to 0.                                    */
2134             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter EnableEnables or disables the transaction
2135                                         *   counter function.                                                         */
2136             uint16_t : 6;
2137         } E_b;
2138     };
2139 
2140     union
2141     {
2142         __IOM uint16_t N;               /*!< (@ 0x00000002) PIPE Transaction Counter Register                          */
2143 
2144         struct
2145         {
2146             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction CounterWhen writing to: Specify the number
2147                                          *   of total packets (number of transactions) to be received
2148                                          *   by the relevant PIPE.When read from: When TRENB = 0: Indicate
2149                                          *   the specified number of transactions.When TRENB = 1: Indicate
2150                                          *   the number of currently counted transactions.                             */
2151         } N_b;
2152     };
2153 } R_USB_HS0_PIPE_TR_Type;               /*!< Size = 4 (0x4)                                                            */
2154 
2155 /**
2156  * @brief R_AGTX0_AGT16_CTRL [CTRL] (CTRL)
2157  */
2158 typedef struct
2159 {
2160     union
2161     {
2162         __IOM uint8_t AGTCR;           /*!< (@ 0x00000000) AGT Control Register                                       */
2163 
2164         struct
2165         {
2166             __IOM uint8_t TSTART : 1;  /*!< [0..0] AGT count start                                                    */
2167             __IM uint8_t  TCSTF  : 1;  /*!< [1..1] AGT count status flag                                              */
2168             __OM uint8_t  TSTOP  : 1;  /*!< [2..2] AGT count forced stop                                              */
2169             uint8_t              : 1;
2170             __IOM uint8_t TEDGF  : 1;  /*!< [4..4] Active edge judgment flag                                          */
2171             __IOM uint8_t TUNDF  : 1;  /*!< [5..5] Underflow flag                                                     */
2172             __IOM uint8_t TCMAF  : 1;  /*!< [6..6] Compare match A flag                                               */
2173             __IOM uint8_t TCMBF  : 1;  /*!< [7..7] Compare match B flag                                               */
2174         } AGTCR_b;
2175     };
2176 
2177     union
2178     {
2179         __IOM uint8_t AGTMR1;          /*!< (@ 0x00000001) AGT Mode Register 1                                        */
2180 
2181         struct
2182         {
2183             __IOM uint8_t TMOD   : 3;  /*!< [2..0] Operating mode                                                     */
2184             __IOM uint8_t TEDGPL : 1;  /*!< [3..3] Edge polarity                                                      */
2185             __IOM uint8_t TCK    : 3;  /*!< [6..4] Count source                                                       */
2186             uint8_t              : 1;
2187         } AGTMR1_b;
2188     };
2189 
2190     union
2191     {
2192         __IOM uint8_t AGTMR2;          /*!< (@ 0x00000002) AGT Mode Register 2                                        */
2193 
2194         struct
2195         {
2196             __IOM uint8_t CKS : 3;     /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division
2197                                         *   ratio                                                                     */
2198             uint8_t           : 4;
2199             __IOM uint8_t LPM : 1;     /*!< [7..7] Low Power Mode                                                     */
2200         } AGTMR2_b;
2201     };
2202 
2203     union
2204     {
2205         __IOM uint8_t AGTIOSEL_ALT;    /*!< (@ 0x00000003) AGT Pin Select Register                                    */
2206 
2207         struct
2208         {
2209             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
2210             uint8_t            : 2;
2211             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
2212             uint8_t            : 3;
2213         } AGTIOSEL_ALT_b;
2214     };
2215 
2216     union
2217     {
2218         __IOM uint8_t AGTIOC;          /*!< (@ 0x00000004) AGT I/O Control Register                                   */
2219 
2220         struct
2221         {
2222             __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating
2223                                         *   mode.                                                                     */
2224             uint8_t             : 1;
2225             __IOM uint8_t TOE   : 1;   /*!< [2..2] AGTOn output enable                                                */
2226             uint8_t             : 1;
2227             __IOM uint8_t TIPF  : 2;   /*!< [5..4] Input filter                                                       */
2228             __IOM uint8_t TIOGT : 2;   /*!< [7..6] Count control                                                      */
2229         } AGTIOC_b;
2230     };
2231 
2232     union
2233     {
2234         __IOM uint8_t AGTISR;          /*!< (@ 0x00000005) AGT Event Pin Select Register                              */
2235 
2236         struct
2237         {
2238             uint8_t            : 2;
2239             __IOM uint8_t EEPS : 1;    /*!< [2..2] AGTEE polarty selection                                            */
2240             uint8_t            : 5;
2241         } AGTISR_b;
2242     };
2243 
2244     union
2245     {
2246         __IOM uint8_t AGTCMSR;         /*!< (@ 0x00000006) AGT Compare Match Function Select Register                 */
2247 
2248         struct
2249         {
2250             __IOM uint8_t TCMEA  : 1;  /*!< [0..0] Compare match A register enable                                    */
2251             __IOM uint8_t TOEA   : 1;  /*!< [1..1] AGTOA output enable                                                */
2252             __IOM uint8_t TOPOLA : 1;  /*!< [2..2] AGTOA polarity select                                              */
2253             uint8_t              : 1;
2254             __IOM uint8_t TCMEB  : 1;  /*!< [4..4] Compare match B register enable                                    */
2255             __IOM uint8_t TOEB   : 1;  /*!< [5..5] AGTOB output enable                                                */
2256             __IOM uint8_t TOPOLB : 1;  /*!< [6..6] AGTOB polarity select                                              */
2257             uint8_t              : 1;
2258         } AGTCMSR_b;
2259     };
2260 
2261     union
2262     {
2263         __IOM uint8_t AGTIOSEL;        /*!< (@ 0x00000007) AGT Pin Select Register                                    */
2264 
2265         struct
2266         {
2267             __IOM uint8_t SEL  : 2;    /*!< [1..0] AGTIO pin select                                                   */
2268             uint8_t            : 2;
2269             __IOM uint8_t TIES : 1;    /*!< [4..4] AGTIO input enable                                                 */
2270             uint8_t            : 3;
2271         } AGTIOSEL_b;
2272     };
2273 } R_AGTX0_AGT16_CTRL_Type;             /*!< Size = 8 (0x8)                                                            */
2274 
2275 /**
2276  * @brief R_AGTX0_AGT16 [AGT16] (AGT (16-bit) peripheral registers)
2277  */
2278 typedef struct
2279 {
2280     union
2281     {
2282         __IOM uint16_t AGT;            /*!< (@ 0x00000000) AGT Counter Register                                       */
2283 
2284         struct
2285         {
2286             __IOM uint16_t AGT : 16;   /*!< [15..0] 16bit counter and reload register. NOTE : When 1 is
2287                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
2288                                         *   counter is forcibly stopped and set to FFFFH.                             */
2289         } AGT_b;
2290     };
2291 
2292     union
2293     {
2294         __IOM uint16_t AGTCMA;          /*!< (@ 0x00000002) AGT Compare Match A Register                               */
2295 
2296         struct
2297         {
2298             __IOM uint16_t AGTCMA : 16; /*!< [15..0] AGT Compare Match A data is stored.NOTE : When 1 is
2299                                          *   written to the TSTOP bit in the AGTCRn register, set to
2300                                          *   FFFFH                                                                     */
2301         } AGTCMA_b;
2302     };
2303 
2304     union
2305     {
2306         __IOM uint16_t AGTCMB;          /*!< (@ 0x00000004) AGT Compare Match B Register                               */
2307 
2308         struct
2309         {
2310             __IOM uint16_t AGTCMB : 16; /*!< [15..0] AGT Compare Match B data is stored.NOTE : When 1 is
2311                                          *   written to the TSTOP bit in the AGTCR register, set to
2312                                          *   FFFFH                                                                     */
2313         } AGTCMB_b;
2314     };
2315     __IM uint16_t                 RESERVED;
2316     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x00000008) CTRL                                                       */
2317 } R_AGTX0_AGT16_Type;                   /*!< Size = 16 (0x10)                                                          */
2318 
2319 /**
2320  * @brief R_AGTX0_AGT32 [AGT32] (AGTW (32-bit) peripheral registers)
2321  */
2322 typedef struct
2323 {
2324     union
2325     {
2326         __IOM uint32_t AGT;            /*!< (@ 0x00000000) AGT 32-bit Counter Register                                */
2327 
2328         struct
2329         {
2330             __IOM uint32_t AGT : 32;   /*!< [31..0] 32bit counter and reload register. NOTE : When 1 is
2331                                         *   written to the TSTOP bit in the AGTCRn register, the 16-bit
2332                                         *   counter is forcibly stopped and set to FFFFH.                             */
2333         } AGT_b;
2334     };
2335 
2336     union
2337     {
2338         __IOM uint32_t AGTCMA;          /*!< (@ 0x00000004) AGT Compare Match A Register                               */
2339 
2340         struct
2341         {
2342             __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is
2343                                          *   written to the TSTOP bit in the AGTCRn register, set to
2344                                          *   FFFFH                                                                     */
2345         } AGTCMA_b;
2346     };
2347 
2348     union
2349     {
2350         __IOM uint32_t AGTCMB;          /*!< (@ 0x00000008) AGT Compare Match B Register                               */
2351 
2352         struct
2353         {
2354             __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is
2355                                          *   written to the TSTOP bit in the AGTCR register, set to
2356                                          *   FFFFH                                                                     */
2357         } AGTCMB_b;
2358     };
2359     __IOM R_AGTX0_AGT16_CTRL_Type CTRL; /*!< (@ 0x0000000C) CTRL                                                       */
2360 } R_AGTX0_AGT32_Type;                   /*!< Size = 20 (0x14)                                                          */
2361 
2362 /** @} */ /* End of group Device_Peripheral_clusters */
2363 
2364 /* =========================================================================================================================== */
2365 /* ================                            Device Specific Peripheral Section                             ================ */
2366 /* =========================================================================================================================== */
2367 
2368 /** @addtogroup Device_Peripheral_peripherals
2369  * @{
2370  */
2371 
2372 /* =========================================================================================================================== */
2373 /* ================                                          R_ADC0                                           ================ */
2374 /* =========================================================================================================================== */
2375 
2376 /**
2377  * @brief A/D Converter (R_ADC0)
2378  */
2379 
2380 typedef struct                         /*!< (@ 0x40170000) R_ADC0 Structure                                           */
2381 {
2382     union
2383     {
2384         __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
2385 
2386         struct
2387         {
2388             __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog
2389                                         *   input channel for double triggered operation. The setting
2390                                         *   is only effective while double trigger mode is selected.                  */
2391             uint16_t              : 1;
2392             __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
2393             __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
2394             __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
2395             __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
2396             __IOM uint16_t ADHSC  : 1; /*!< [10..10] A/D Conversion Operation Mode Select                             */
2397             uint16_t              : 1;
2398             __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
2399             __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
2400             __IOM uint16_t ADST   : 1; /*!< [15..15] A/D Conversion Start                                             */
2401         } ADCSR_b;
2402     };
2403 
2404     union
2405     {
2406         __IOM uint8_t ADREF;           /*!< (@ 0x00000002) A/D status register                                        */
2407 
2408         struct
2409         {
2410             __IOM uint8_t ADF : 1;     /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes
2411                                         *   '1' while scanning.                                                       */
2412             uint8_t              : 6;
2413             __IM uint8_t ADSCACT : 1;  /*!< [7..7] Scanning status bit                                                */
2414         } ADREF_b;
2415     };
2416 
2417     union
2418     {
2419         __IOM uint8_t ADEXREF;         /*!< (@ 0x00000003) A/D enhancing status register                              */
2420 
2421         struct
2422         {
2423             __IOM uint8_t GBADF : 1;   /*!< [0..0] Group B scanning end flag bit.                                     */
2424             uint8_t             : 7;
2425         } ADEXREF_b;
2426     };
2427 
2428     union
2429     {
2430         __IOM uint16_t ADANSA[2];      /*!< (@ 0x00000004) A/D Channel Select Register                                */
2431 
2432         struct
2433         {
2434             __IOM uint16_t ANSA0  : 1; /*!< [0..0] AN Input Select                                                    */
2435             __IOM uint16_t ANSA1  : 1; /*!< [1..1] AN Input Select                                                    */
2436             __IOM uint16_t ANSA2  : 1; /*!< [2..2] AN Input Select                                                    */
2437             __IOM uint16_t ANSA3  : 1; /*!< [3..3] AN Input Select                                                    */
2438             __IOM uint16_t ANSA4  : 1; /*!< [4..4] AN Input Select                                                    */
2439             __IOM uint16_t ANSA5  : 1; /*!< [5..5] AN Input Select                                                    */
2440             __IOM uint16_t ANSA6  : 1; /*!< [6..6] AN Input Select                                                    */
2441             __IOM uint16_t ANSA7  : 1; /*!< [7..7] AN Input Select                                                    */
2442             __IOM uint16_t ANSA8  : 1; /*!< [8..8] AN Input Select                                                    */
2443             __IOM uint16_t ANSA9  : 1; /*!< [9..9] AN Input Select                                                    */
2444             __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select                                                  */
2445             __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select                                                  */
2446             __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select                                                  */
2447             __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select                                                  */
2448             __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select                                                  */
2449             __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select                                                  */
2450         } ADANSA_b[2];
2451     };
2452 
2453     union
2454     {
2455         __IOM uint16_t ADADS[2];       /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel
2456                                         *                  Select Register                                            */
2457 
2458         struct
2459         {
2460             __IOM uint16_t ADS0  : 1;  /*!< [0..0] A/D-Converted Value Addition/Average Channel Select                */
2461             __IOM uint16_t ADS1  : 1;  /*!< [1..1] A/D-Converted Value Addition/Average Channel Select                */
2462             __IOM uint16_t ADS2  : 1;  /*!< [2..2] A/D-Converted Value Addition/Average Channel Select                */
2463             __IOM uint16_t ADS3  : 1;  /*!< [3..3] A/D-Converted Value Addition/Average Channel Select                */
2464             __IOM uint16_t ADS4  : 1;  /*!< [4..4] A/D-Converted Value Addition/Average Channel Select                */
2465             __IOM uint16_t ADS5  : 1;  /*!< [5..5] A/D-Converted Value Addition/Average Channel Select                */
2466             __IOM uint16_t ADS6  : 1;  /*!< [6..6] A/D-Converted Value Addition/Average Channel Select                */
2467             __IOM uint16_t ADS7  : 1;  /*!< [7..7] A/D-Converted Value Addition/Average Channel Select                */
2468             __IOM uint16_t ADS8  : 1;  /*!< [8..8] A/D-Converted Value Addition/Average Channel Select                */
2469             __IOM uint16_t ADS9  : 1;  /*!< [9..9] A/D-Converted Value Addition/Average Channel Select                */
2470             __IOM uint16_t ADS10 : 1;  /*!< [10..10] A/D-Converted Value Addition/Average Channel Select              */
2471             __IOM uint16_t ADS11 : 1;  /*!< [11..11] A/D-Converted Value Addition/Average Channel Select              */
2472             __IOM uint16_t ADS12 : 1;  /*!< [12..12] A/D-Converted Value Addition/Average Channel Select              */
2473             __IOM uint16_t ADS13 : 1;  /*!< [13..13] A/D-Converted Value Addition/Average Channel Select              */
2474             __IOM uint16_t ADS14 : 1;  /*!< [14..14] A/D-Converted Value Addition/Average Channel Select              */
2475             __IOM uint16_t ADS15 : 1;  /*!< [15..15] A/D-Converted Value Addition/Average Channel Select              */
2476         } ADADS_b[2];
2477     };
2478 
2479     union
2480     {
2481         __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
2482                                         *                  Register                                                   */
2483 
2484         struct
2485         {
2486             __IOM uint8_t ADC : 3;     /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid
2487                                         *   at the only setting of ADC[2:0] bits = 001b or 011b. When
2488                                         *   average mode is selected by setting the ADADC.AVEE bit
2489                                         *   to 1, do not set the addition count to three times (ADADC.ADC[2:0]
2490                                         *   = 010b)                                                                   */
2491             uint8_t            : 4;
2492             __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected
2493                                         *   by setting the ADADC.AVEE bit to 0, set the addition count
2494                                         *   to 1, 2, 3, 4 or 16-time conversion. 16-time conversion
2495                                         *   can only be used with 12-bit accuracy selected. NOTE: AVEE
2496                                         *   bit is valid at the only setting of ADC[2:0] bits = 001b
2497                                         *   or 011b. When average mode is selected by setting the ADADC.AVEE
2498                                         *   bit to 1, do not set the addition count to three times
2499                                         *   (ADADC.ADC[2:0] = 010b)                                                   */
2500         } ADADC_b;
2501     };
2502     __IM uint8_t RESERVED;
2503 
2504     union
2505     {
2506         __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
2507 
2508         struct
2509         {
2510             uint16_t               : 1;
2511             __IOM uint16_t ADPRC   : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
2512             uint16_t               : 1;
2513             __IOM uint16_t DCE     : 1; /*!< [4..4] Discharge Enable                                                   */
2514             __IOM uint16_t ACE     : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
2515             uint16_t               : 2;
2516             __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select                           */
2517             __IOM uint16_t DIAGLD  : 1; /*!< [10..10] Self-Diagnosis Mode Select                                       */
2518             __IOM uint16_t DIAGM   : 1; /*!< [11..11] Self-Diagnosis Enable                                            */
2519             uint16_t               : 2;
2520             __IOM uint16_t ADINV   : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select           */
2521             __IOM uint16_t ADRFMT  : 1; /*!< [15..15] A/D Data Register Format Select                                  */
2522         } ADCER_b;
2523     };
2524 
2525     union
2526     {
2527         __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
2528 
2529         struct
2530         {
2531             __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect
2532                                         *   the A/D conversion start trigger for group B in group scan
2533                                         *   mode.                                                                     */
2534             uint16_t            : 2;
2535             __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion
2536                                         *   start trigger in single scan mode and continuous mode.
2537                                         *   In group scan mode, the A/D conversion start trigger for
2538                                         *   group A is selected.                                                      */
2539             uint16_t : 2;
2540         } ADSTRGR_b;
2541     };
2542 
2543     union
2544     {
2545         __IOM uint16_t ADEXICR;        /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register             */
2546 
2547         struct
2548         {
2549             __IOM uint16_t TSSAD : 1;  /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average
2550                                         *   Mode Select                                                               */
2551             __IOM uint16_t OCSAD : 1;  /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average
2552                                         *   Mode Select                                                               */
2553             uint16_t            : 6;
2554             __IOM uint16_t TSSA : 1;   /*!< [8..8] Temperature Sensor Output A/D Conversion Select                    */
2555             __IOM uint16_t OCSA : 1;   /*!< [9..9] Internal Reference Voltage A/D Conversion Select                   */
2556             __IOM uint16_t TSSB : 1;   /*!< [10..10] Temperature Sensor Output A/D Conversion Select for
2557                                         *   Group B in group scan mode.                                               */
2558             __IOM uint16_t OCSB : 1;   /*!< [11..11] Internal Reference Voltage A/D Conversion Select for
2559                                         *   Group B in group scan mode.                                               */
2560             uint16_t             : 2;
2561             __IOM uint16_t EXSEL : 1;  /*!< [14..14] Extended Analog Input Select                                     */
2562             __IOM uint16_t EXOEN : 1;  /*!< [15..15] Extended Analog Output Control                                   */
2563         } ADEXICR_b;
2564     };
2565 
2566     union
2567     {
2568         __IOM uint16_t ADANSB[2];      /*!< (@ 0x00000014) A/D Channel Select Register B                              */
2569 
2570         struct
2571         {
2572             __IOM uint16_t ANSB0  : 1; /*!< [0..0] AN Input Select                                                    */
2573             __IOM uint16_t ANSB1  : 1; /*!< [1..1] AN Input Select                                                    */
2574             __IOM uint16_t ANSB2  : 1; /*!< [2..2] AN Input Select                                                    */
2575             __IOM uint16_t ANSB3  : 1; /*!< [3..3] AN Input Select                                                    */
2576             __IOM uint16_t ANSB4  : 1; /*!< [4..4] AN Input Select                                                    */
2577             __IOM uint16_t ANSB5  : 1; /*!< [5..5] AN Input Select                                                    */
2578             __IOM uint16_t ANSB6  : 1; /*!< [6..6] AN Input Select                                                    */
2579             __IOM uint16_t ANSB7  : 1; /*!< [7..7] AN Input Select                                                    */
2580             __IOM uint16_t ANSB8  : 1; /*!< [8..8] AN Input Select                                                    */
2581             __IOM uint16_t ANSB9  : 1; /*!< [9..9] AN Input Select                                                    */
2582             __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select                                                  */
2583             __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select                                                  */
2584             __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select                                                  */
2585             __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select                                                  */
2586             __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select                                                  */
2587             __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select                                                  */
2588         } ADANSB_b[2];
2589     };
2590 
2591     union
2592     {
2593         __IM uint16_t ADDBLDR;          /*!< (@ 0x00000018) A/D Data Duplication Register                              */
2594 
2595         struct
2596         {
2597             __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2598                                          *   result of A/D conversion in response to the second trigger
2599                                          *   in double trigger mode.                                                   */
2600         } ADDBLDR_b;
2601     };
2602 
2603     union
2604     {
2605         __IM uint16_t ADTSDR;          /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register                       */
2606 
2607         struct
2608         {
2609             __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2610                                         *   A/D conversion result of temperature sensor output.                       */
2611         } ADTSDR_b;
2612     };
2613 
2614     union
2615     {
2616         __IM uint16_t ADOCDR;          /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register               */
2617 
2618         struct
2619         {
2620             __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the
2621                                         *   A/D result of internal reference voltage.                                 */
2622         } ADOCDR_b;
2623     };
2624 
2625     union
2626     {
2627         union
2628         {
2629             __IM uint16_t ADRD_RIGHT;     /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified           */
2630 
2631             struct
2632             {
2633                 __IM uint16_t AD : 14;    /*!< [13..0] A/D-converted value (right-justified)The format for
2634                                            *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
2635                 __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status                                            */
2636             } ADRD_RIGHT_b;
2637         };
2638 
2639         union
2640         {
2641             __IM uint16_t ADRD_LEFT;       /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified            */
2642 
2643             struct
2644             {
2645                 __IM uint16_t DIAGST : 2;  /*!< [1..0] Self-Diagnosis Status                                              */
2646                 __IM uint16_t AD     : 14; /*!< [15..2] A/D-converted value (right-justified)The format for
2647                                             *   data determine ADCER.ADRFMT and ADCER.ADPRC.                              */
2648             } ADRD_LEFT_b;
2649         };
2650     };
2651 
2652     union
2653     {
2654         __IM uint16_t ADDR[29];        /*!< (@ 0x00000020) A/D Data Register                                          */
2655 
2656         struct
2657         {
2658             __IM uint16_t ADDR : 16;   /*!< [15..0] The ADDR register is a 16-bit read-only registers for
2659                                         *   storing the result of A/D conversion.                                     */
2660         } ADDR_b[29];
2661     };
2662     __IM uint16_t RESERVED1;
2663     __IM uint32_t RESERVED2;
2664     __IM uint16_t RESERVED3;
2665 
2666     union
2667     {
2668         __IOM uint8_t ADAMPOFF;        /*!< (@ 0x00000062) A/D RRAMP off state register                               */
2669 
2670         struct
2671         {
2672             __IOM uint8_t OPOFF : 8;   /*!< [7..0] OPOFF                                                              */
2673         } ADAMPOFF_b;
2674     };
2675 
2676     union
2677     {
2678         __IOM uint8_t ADTSTPR;         /*!< (@ 0x00000063) A/D Test Protecting Release Register                       */
2679 
2680         struct
2681         {
2682             __IOM uint8_t PRO  : 1;    /*!< [0..0] Test register protecting bit.                                      */
2683             __IOM uint8_t B0WI : 1;    /*!< [1..1] Bit 0 writing permission bit.                                      */
2684             uint8_t            : 6;
2685         } ADTSTPR_b;
2686     };
2687 
2688     union
2689     {
2690         __IOM uint16_t ADDDACER;       /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register                        */
2691 
2692         struct
2693         {
2694             __IOM uint16_t WRION  : 5; /*!< [4..0] WRION                                                              */
2695             uint16_t              : 3;
2696             __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF                                                            */
2697             uint16_t              : 2;
2698             __IOM uint16_t ADHS   : 1; /*!< [15..15] ADHS                                                             */
2699         } ADDDACER_b;
2700     };
2701 
2702     union
2703     {
2704         __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register               */
2705 
2706         struct
2707         {
2708             __IOM uint16_t SSTSH : 8;  /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time
2709                                         *   Setting Set the sampling time (4 to 255 states)                           */
2710             __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select                               */
2711             __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select                               */
2712             __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select                             */
2713             uint16_t              : 5;
2714         } ADSHCR_b;
2715     };
2716 
2717     union
2718     {
2719         __IOM uint16_t ADEXTSTR;       /*!< (@ 0x00000068) A/D Enhancing Test Register                                */
2720 
2721         struct
2722         {
2723             __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit
2724                                         *   only for channel.                                                         */
2725             uint16_t             : 1;
2726             __IOM uint16_t SWTST : 2;  /*!< [5..4] Test selection bit for pressure switch.                            */
2727             uint16_t             : 2;
2728             __IOM uint16_t SHTRM : 2;  /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit
2729                                         *   for adjustment to hardening of process.                                   */
2730             uint16_t              : 1;
2731             __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator
2732                                         *   power save bit for A/D hard macro to hardening of process.                */
2733             __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim
2734                                         *   bit for A/D hard macro to hardening of process.                           */
2735             __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim
2736                                         *   bit for A/D hard macro to hardening of process.                           */
2737         } ADEXTSTR_b;
2738     };
2739 
2740     union
2741     {
2742         __IOM uint16_t ADTSTRA;           /*!< (@ 0x0000006A) A/D Test Register A                                        */
2743 
2744         struct
2745         {
2746             __IOM uint16_t ATBUSSEL : 1;  /*!< [0..0] Analog test bus selection bit.                                     */
2747             __IOM uint16_t TSTSWREF : 3;  /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit
2748                                            *   amplifier test.Refreshing the pressure switch that opens
2749                                            *   for the DAC output voltage charge period when the amplifier
2750                                            *   of the S&H circuit is tested only for the channel is set.                 */
2751             uint16_t            : 1;
2752             __IOM uint16_t OCSW : 1;      /*!< [5..5] Internal reference voltage analog switch test control
2753                                            *   bit.                                                                      */
2754             __IOM uint16_t TSSW : 1;      /*!< [6..6] Temperature sensor output analogue switch test control
2755                                            *   bit                                                                       */
2756             uint16_t                 : 1;
2757             __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog
2758                                            *   module Details are described to the bit explanation.                      */
2759             __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the
2760                                            *   bit explanation.                                                          */
2761         } ADTSTRA_b;
2762     };
2763 
2764     union
2765     {
2766         __IOM uint16_t ADTSTRB;        /*!< (@ 0x0000006C) A/D Test Register B                                        */
2767 
2768         struct
2769         {
2770             __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It
2771                                         *   corresponds to ADVAL 14:0 input of A/D analog module.                     */
2772             uint16_t : 1;
2773         } ADTSTRB_b;
2774     };
2775 
2776     union
2777     {
2778         __IOM uint16_t ADTSTRC;         /*!< (@ 0x0000006E) A/D Test Register C                                        */
2779 
2780         struct
2781         {
2782             __IOM uint16_t ADMD : 8;    /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D
2783                                          *   analog module.                                                            */
2784             uint16_t               : 4;
2785             __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit.              */
2786             uint16_t               : 3;
2787         } ADTSTRC_b;
2788     };
2789 
2790     union
2791     {
2792         __IOM uint16_t ADTSTRD;         /*!< (@ 0x00000070) A/D Test Register D                                        */
2793 
2794         struct
2795         {
2796             __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It
2797                                          *   corresponds to ADVAL 16 input of A/D analog module.                       */
2798             uint16_t : 15;
2799         } ADTSTRD_b;
2800     };
2801 
2802     union
2803     {
2804         __IOM uint16_t ADSWTSTR0;      /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0                 */
2805 
2806         struct
2807         {
2808             __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit.                                   */
2809             __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit.                                   */
2810             __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit.                                   */
2811             __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit.                                   */
2812             __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit.                                   */
2813             __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit.                                   */
2814             uint16_t              : 10;
2815         } ADSWTSTR0_b;
2816     };
2817 
2818     union
2819     {
2820         __IOM uint16_t ADSWTSTR1;      /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1                 */
2821 
2822         struct
2823         {
2824             __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit.                                   */
2825             __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit.                                   */
2826             __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit.                                   */
2827             __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit.                                   */
2828             __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit.                                   */
2829             __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit.                                   */
2830             uint16_t              : 10;
2831         } ADSWTSTR1_b;
2832     };
2833 
2834     union
2835     {
2836         __IOM uint16_t ADSWTSTR2;        /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2                 */
2837 
2838         struct
2839         {
2840             __IOM uint16_t EX0SW : 1;    /*!< [0..0] Test control of 0 enhancing input channel switches bit
2841                                           *   (ANEX0 switch)                                                            */
2842             __IOM uint16_t EX1SW : 1;    /*!< [1..1] Test control of one enhancing input channel switch bit
2843                                           *   (ANEX1 switch).                                                           */
2844             uint16_t                : 2;
2845             __IOM uint16_t SHBYPS0  : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0.                          */
2846             __IOM uint16_t SHBYPS1  : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1.                          */
2847             __IOM uint16_t SHBYPS2  : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2.                          */
2848             uint16_t                : 1;
2849             __IOM uint16_t GRP0SW   : 1; /*!< [8..8] Test control of 0 group switches bit.                              */
2850             __IOM uint16_t GRP1SW   : 1; /*!< [9..9] Test control of one group switch bit.                              */
2851             __IOM uint16_t GRP2SW   : 1; /*!< [10..10] Test control of two group switches bit                           */
2852             __IOM uint16_t GRP3SW   : 1; /*!< [11..11] Test control of two group switches bit                           */
2853             __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1                */
2854             uint16_t                : 3;
2855         } ADSWTSTR2_b;
2856     };
2857     __IM uint16_t RESERVED4;
2858 
2859     union
2860     {
2861         __IOM uint8_t ADDISCR;         /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register               */
2862 
2863         struct
2864         {
2865             __IOM uint8_t ADNDIS : 4;  /*!< [3..0] The charging time                                                  */
2866             __IOM uint8_t CHARGE : 1;  /*!< [4..4] Selection of Precharge or Discharge                                */
2867             uint8_t              : 3;
2868         } ADDISCR_b;
2869     };
2870 
2871     union
2872     {
2873         __IOM uint8_t ADSWCR;          /*!< (@ 0x0000007B) A/D Pressure Switch Control Register                       */
2874 
2875         struct
2876         {
2877             __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing
2878                                         *   the pressure switch in A/D analog module is set.                          */
2879             uint8_t               : 1;
2880             __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting                          */
2881             uint8_t               : 1;
2882         } ADSWCR_b;
2883     };
2884 
2885     union
2886     {
2887         __IOM uint8_t ADSHMSR;         /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register         */
2888 
2889         struct
2890         {
2891             __IOM uint8_t SHMD : 1;    /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode
2892                                         *   Select                                                                    */
2893             uint8_t : 7;
2894         } ADSHMSR_b;
2895     };
2896 
2897     union
2898     {
2899         __IOM uint8_t ADICR;           /*!< (@ 0x0000007D) A/D Interrupt Control Register                             */
2900 
2901         struct
2902         {
2903             __IOM uint8_t ADIC : 2;    /*!< [1..0] A/D Interrupt Control                                              */
2904             uint8_t            : 6;
2905         } ADICR_b;
2906     };
2907 
2908     union
2909     {
2910         __IOM uint8_t ADACSR;          /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register              */
2911 
2912         struct
2913         {
2914             uint8_t             : 1;
2915             __IOM uint8_t ADSAC : 1;   /*!< [1..1] Successive Approximation Control Setting                           */
2916             uint8_t             : 6;
2917         } ADACSR_b;
2918     };
2919     __IM uint8_t RESERVED5;
2920 
2921     union
2922     {
2923         __IOM uint16_t ADGSPCR;         /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
2924 
2925         struct
2926         {
2927             __IOM uint16_t PGS : 1;     /*!< [0..0] Group A priority control setting bit.Note: When the PGS
2928                                          *   bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be
2929                                          *   set to 01b (group scan mode). If the bits are set to any
2930                                          *   other values, proper operation is not guaranteed.                         */
2931             __IOM uint16_t GBRSCN : 1;  /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved
2932                                          *   when PGS = 0.)                                                            */
2933             uint16_t               : 6;
2934             __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B.                        */
2935             uint16_t               : 6;
2936             __IOM uint16_t GBRP    : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when
2937                                          *   PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit
2938                                          *   has been set to 1, single scan is performed continuously
2939                                          *   for group B regardless of the setting of the GBRSCN bit.                  */
2940         } ADGSPCR_b;
2941     };
2942 
2943     union
2944     {
2945         __IM uint16_t ADGSCS;          /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group
2946                                         *                  Scan)                                                      */
2947 
2948         struct
2949         {
2950             __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan                                     */
2951             __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan                                    */
2952         } ADGSCS_b;
2953     };
2954 
2955     union
2956     {
2957         __IM uint16_t ADDBLDRA;          /*!< (@ 0x00000084) A/D Data Duplexing Register A                              */
2958 
2959         struct
2960         {
2961             __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
2962                                           *   the result of A/D conversion in response to the respective
2963                                           *   triggers during extended operation in double trigger mode.                */
2964         } ADDBLDRA_b;
2965     };
2966 
2967     union
2968     {
2969         __IM uint16_t ADDBLDRB;          /*!< (@ 0x00000086) A/D Data Duplexing Register B                              */
2970 
2971         struct
2972         {
2973             __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing
2974                                           *   the result of A/D conversion in response to the respective
2975                                           *   triggers during extended operation in double trigger mode.                */
2976         } ADDBLDRB_b;
2977     };
2978 
2979     union
2980     {
2981         __IOM uint8_t ADSER;           /*!< (@ 0x00000088) A/D Sampling Extension Register                            */
2982 
2983         struct
2984         {
2985             uint8_t             : 7;
2986             __IOM uint8_t SMPEX : 1;   /*!< [7..7] Sampling extension control                                         */
2987         } ADSER_b;
2988     };
2989     __IM uint8_t RESERVED6;
2990 
2991     union
2992     {
2993         __IOM uint8_t ADHVREFCNT;      /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage
2994                                         *                  Control Register                                           */
2995 
2996         struct
2997         {
2998             __IOM uint8_t HVSEL : 2;   /*!< [1..0] High-Potential Reference Voltage Select                            */
2999             uint8_t             : 2;
3000             __IOM uint8_t LVSEL : 1;   /*!< [4..4] Low-Potential Reference Voltage Select                             */
3001             uint8_t             : 2;
3002             __IOM uint8_t ADSLP : 1;   /*!< [7..7] Sleep                                                              */
3003         } ADHVREFCNT_b;
3004     };
3005     __IM uint8_t RESERVED7;
3006 
3007     union
3008     {
3009         __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor
3010                                         *                  Register                                                   */
3011 
3012         struct
3013         {
3014             __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitorThis bit indicates the combination
3015                                         *   result.This bit is valid when both window A operation and
3016                                         *   window B operation are enabled.                                           */
3017             uint8_t              : 3;
3018             __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparison Result Monitor A                                        */
3019             __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparison Result Monitor B                                        */
3020             uint8_t              : 2;
3021         } ADWINMON_b;
3022     };
3023     __IM uint8_t  RESERVED8;
3024     __IM uint16_t RESERVED9;
3025 
3026     union
3027     {
3028         __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
3029 
3030         struct
3031         {
3032             __IOM uint16_t CMPAB : 2;  /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits
3033                                         *   are valid when both window A and window B are enabled (CMPAE
3034                                         *   = 1 and CMPBE = 1).                                                       */
3035             uint16_t              : 7;
3036             __IOM uint16_t CMPBE  : 1; /*!< [9..9] Compare Window B Operation Enable                                  */
3037             uint16_t              : 1;
3038             __IOM uint16_t CMPAE  : 1; /*!< [11..11] Compare Window A Operation Enable                                */
3039             uint16_t              : 1;
3040             __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable                                       */
3041             __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function Setting                                          */
3042             __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable                                       */
3043         } ADCMPCR_b;
3044     };
3045 
3046     union
3047     {
3048         __IOM uint8_t ADCMPANSER;      /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input
3049                                         *                  Select Register                                            */
3050 
3051         struct
3052         {
3053             __IOM uint8_t CMPTSA : 1;  /*!< [0..0] Temperature sensor output Compare selection bit.                   */
3054             __IOM uint8_t CMPOCA : 1;  /*!< [1..1] Internal reference voltage Compare selection bit.                  */
3055             uint8_t              : 6;
3056         } ADCMPANSER_b;
3057     };
3058 
3059     union
3060     {
3061         __IOM uint8_t ADCMPLER;        /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input
3062                                         *                  Comparison Condition Setting Register                      */
3063 
3064         struct
3065         {
3066             __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison
3067                                         *   Condition Select                                                          */
3068             __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition
3069                                         *   Select                                                                    */
3070             uint8_t : 6;
3071         } ADCMPLER_b;
3072     };
3073 
3074     union
3075     {
3076         __IOM uint16_t ADCMPANSR[2];     /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
3077                                           *                  Register                                                   */
3078 
3079         struct
3080         {
3081             __IOM uint16_t CMPCHA0  : 1; /*!< [0..0] AN Input Select                                                    */
3082             __IOM uint16_t CMPCHA1  : 1; /*!< [1..1] AN Input Select                                                    */
3083             __IOM uint16_t CMPCHA2  : 1; /*!< [2..2] AN Input Select                                                    */
3084             __IOM uint16_t CMPCHA3  : 1; /*!< [3..3] AN Input Select                                                    */
3085             __IOM uint16_t CMPCHA4  : 1; /*!< [4..4] AN Input Select                                                    */
3086             __IOM uint16_t CMPCHA5  : 1; /*!< [5..5] AN Input Select                                                    */
3087             __IOM uint16_t CMPCHA6  : 1; /*!< [6..6] AN Input Select                                                    */
3088             __IOM uint16_t CMPCHA7  : 1; /*!< [7..7] AN Input Select                                                    */
3089             __IOM uint16_t CMPCHA8  : 1; /*!< [8..8] AN Input Select                                                    */
3090             __IOM uint16_t CMPCHA9  : 1; /*!< [9..9] AN Input Select                                                    */
3091             __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select                                                  */
3092             __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select                                                  */
3093             __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select                                                  */
3094             __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select                                                  */
3095             __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select                                                  */
3096             __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select                                                  */
3097         } ADCMPANSR_b[2];
3098     };
3099 
3100     union
3101     {
3102         __IOM uint16_t ADCMPLR[2];        /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
3103                                            *                  Setting Register                                           */
3104 
3105         struct
3106         {
3107             __IOM uint16_t CMPLCHA0  : 1; /*!< [0..0] Comparison condition of input                                      */
3108             __IOM uint16_t CMPLCHA1  : 1; /*!< [1..1] Comparison condition of input                                      */
3109             __IOM uint16_t CMPLCHA2  : 1; /*!< [2..2] Comparison condition of input                                      */
3110             __IOM uint16_t CMPLCHA3  : 1; /*!< [3..3] Comparison condition of input                                      */
3111             __IOM uint16_t CMPLCHA4  : 1; /*!< [4..4] Comparison condition of input                                      */
3112             __IOM uint16_t CMPLCHA5  : 1; /*!< [5..5] Comparison condition of input                                      */
3113             __IOM uint16_t CMPLCHA6  : 1; /*!< [6..6] Comparison condition of input                                      */
3114             __IOM uint16_t CMPLCHA7  : 1; /*!< [7..7] Comparison condition of input                                      */
3115             __IOM uint16_t CMPLCHA8  : 1; /*!< [8..8] Comparison condition of input                                      */
3116             __IOM uint16_t CMPLCHA9  : 1; /*!< [9..9] Comparison condition of input                                      */
3117             __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input                                    */
3118             __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input                                    */
3119             __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input                                    */
3120             __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input                                    */
3121             __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input                                    */
3122             __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input                                    */
3123         } ADCMPLR_b[2];
3124     };
3125 
3126     union
3127     {
3128         __IOM uint16_t ADCMPDR0;          /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level
3129                                            *                  Setting Register                                           */
3130 
3131         struct
3132         {
3133             __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the
3134                                            *   compare window A function is used. ADCMPDR0 sets the lower-side
3135                                            *   level of window A.                                                        */
3136         } ADCMPDR0_b;
3137     };
3138 
3139     union
3140     {
3141         __IOM uint16_t ADCMPDR1;          /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level
3142                                            *                  Setting Register                                           */
3143 
3144         struct
3145         {
3146             __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the
3147                                            *   compare window A function is used. ADCMPDR1 sets the upper-side
3148                                            *   level of window A..                                                       */
3149         } ADCMPDR1_b;
3150     };
3151 
3152     union
3153     {
3154         __IOM uint16_t ADCMPSR[2];         /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status
3155                                             *                  Register                                                   */
3156 
3157         struct
3158         {
3159             __IOM uint16_t CMPSTCHA0  : 1; /*!< [0..0] Compare window A flag of input                                     */
3160             __IOM uint16_t CMPSTCHA1  : 1; /*!< [1..1] Compare window A flag of input                                     */
3161             __IOM uint16_t CMPSTCHA2  : 1; /*!< [2..2] Compare window A flag of input                                     */
3162             __IOM uint16_t CMPSTCHA3  : 1; /*!< [3..3] Compare window A flag of input                                     */
3163             __IOM uint16_t CMPSTCHA4  : 1; /*!< [4..4] Compare window A flag of input                                     */
3164             __IOM uint16_t CMPSTCHA5  : 1; /*!< [5..5] Compare window A flag of input                                     */
3165             __IOM uint16_t CMPSTCHA6  : 1; /*!< [6..6] Compare window A flag of input                                     */
3166             __IOM uint16_t CMPSTCHA7  : 1; /*!< [7..7] Compare window A flag of input                                     */
3167             __IOM uint16_t CMPSTCHA8  : 1; /*!< [8..8] Compare window A flag of input                                     */
3168             __IOM uint16_t CMPSTCHA9  : 1; /*!< [9..9] Compare window A flag of input                                     */
3169             __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input                                   */
3170             __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input                                   */
3171             __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input                                   */
3172             __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input                                   */
3173             __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input                                   */
3174             __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input                                   */
3175         } ADCMPSR_b[2];
3176     };
3177 
3178     union
3179     {
3180         __IOM uint8_t ADCMPSER;         /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input
3181                                          *                  Channel Status Register                                    */
3182 
3183         struct
3184         {
3185             __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag
3186                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
3187                                          *   this bit indicates the temperature sensor output comparison
3188                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
3189                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
3190                                          *   time.                                                                     */
3191             __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag
3192                                          *   When window A operation is enabled (ADCMPCR.CMPAE = 1b),
3193                                          *   this bit indicates the temperature sensor output comparison
3194                                          *   result. When window A operation is disabled (ADCMPCR.CMPAE
3195                                          *   = 0b), comparison conditions for CMPSTTSA are not met any
3196                                          *   time.                                                                     */
3197             uint8_t : 6;
3198         } ADCMPSER_b;
3199     };
3200     __IM uint8_t RESERVED10;
3201 
3202     union
3203     {
3204         __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection
3205                                         *                  Register                                                   */
3206 
3207         struct
3208         {
3209             __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Compare window B channel selection bit.The channel that
3210                                         *   compares it on the condition of compare window B is selected.             */
3211             uint8_t             : 1;
3212             __IOM uint8_t CMPLB : 1;   /*!< [7..7] Compare window B Compare condition setting bit.                    */
3213         } ADCMPBNSR_b;
3214     };
3215     __IM uint8_t RESERVED11;
3216 
3217     union
3218     {
3219         __IOM uint16_t ADWINLLB;          /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
3220                                            *                  Setting Register                                           */
3221 
3222         struct
3223         {
3224             __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is
3225                                            *   used to set the lower level of the window B.                              */
3226         } ADWINLLB_b;
3227     };
3228 
3229     union
3230     {
3231         __IOM uint16_t ADWINULB;          /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
3232                                            *                  Setting Register                                           */
3233 
3234         struct
3235         {
3236             __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is
3237                                            *   used to set the higher level of the window B.                             */
3238         } ADWINULB_b;
3239     };
3240 
3241     union
3242     {
3243         __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
3244 
3245         struct
3246         {
3247             __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Compare window B flag.It is a status flag that shows
3248                                         *   the comparative result of CH (AN000-AN027, temperature
3249                                         *   sensor, and internal reference voltage) made the object
3250                                         *   of window B relation condition.                                           */
3251             uint8_t : 7;
3252         } ADCMPBSR_b;
3253     };
3254     __IM uint8_t  RESERVED12;
3255     __IM uint16_t RESERVED13;
3256 
3257     union
3258     {
3259         __IM uint16_t ADBUF0;          /*!< (@ 0x000000B0) A/D Data Buffer Register 0                                 */
3260 
3261         struct
3262         {
3263             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3264                                         *   registers that sequentially store all A/D converted values.
3265                                         *   The automatic clear function is not applied to these registers.           */
3266         } ADBUF0_b;
3267     };
3268 
3269     union
3270     {
3271         __IM uint16_t ADBUF1;          /*!< (@ 0x000000B2) A/D Data Buffer Register 1                                 */
3272 
3273         struct
3274         {
3275             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3276                                         *   registers that sequentially store all A/D converted values.
3277                                         *   The automatic clear function is not applied to these registers.           */
3278         } ADBUF1_b;
3279     };
3280 
3281     union
3282     {
3283         __IM uint16_t ADBUF2;          /*!< (@ 0x000000B4) A/D Data Buffer Register 2                                 */
3284 
3285         struct
3286         {
3287             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3288                                         *   registers that sequentially store all A/D converted values.
3289                                         *   The automatic clear function is not applied to these registers.           */
3290         } ADBUF2_b;
3291     };
3292 
3293     union
3294     {
3295         __IM uint16_t ADBUF3;          /*!< (@ 0x000000B6) A/D Data Buffer Register 3                                 */
3296 
3297         struct
3298         {
3299             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3300                                         *   registers that sequentially store all A/D converted values.
3301                                         *   The automatic clear function is not applied to these registers.           */
3302         } ADBUF3_b;
3303     };
3304 
3305     union
3306     {
3307         __IM uint16_t ADBUF4;          /*!< (@ 0x000000B8) A/D Data Buffer Register 4                                 */
3308 
3309         struct
3310         {
3311             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3312                                         *   registers that sequentially store all A/D converted values.
3313                                         *   The automatic clear function is not applied to these registers.           */
3314         } ADBUF4_b;
3315     };
3316 
3317     union
3318     {
3319         __IM uint16_t ADBUF5;          /*!< (@ 0x000000BA) A/D Data Buffer Register 5                                 */
3320 
3321         struct
3322         {
3323             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3324                                         *   registers that sequentially store all A/D converted values.
3325                                         *   The automatic clear function is not applied to these registers.           */
3326         } ADBUF5_b;
3327     };
3328 
3329     union
3330     {
3331         __IM uint16_t ADBUF6;          /*!< (@ 0x000000BC) A/D Data Buffer Register 6                                 */
3332 
3333         struct
3334         {
3335             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3336                                         *   registers that sequentially store all A/D converted values.
3337                                         *   The automatic clear function is not applied to these registers.           */
3338         } ADBUF6_b;
3339     };
3340 
3341     union
3342     {
3343         __IM uint16_t ADBUF7;          /*!< (@ 0x000000BE) A/D Data Buffer Register 7                                 */
3344 
3345         struct
3346         {
3347             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3348                                         *   registers that sequentially store all A/D converted values.
3349                                         *   The automatic clear function is not applied to these registers.           */
3350         } ADBUF7_b;
3351     };
3352 
3353     union
3354     {
3355         __IM uint16_t ADBUF8;          /*!< (@ 0x000000C0) A/D Data Buffer Register 8                                 */
3356 
3357         struct
3358         {
3359             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3360                                         *   registers that sequentially store all A/D converted values.
3361                                         *   The automatic clear function is not applied to these registers.           */
3362         } ADBUF8_b;
3363     };
3364 
3365     union
3366     {
3367         __IM uint16_t ADBUF9;          /*!< (@ 0x000000C2) A/D Data Buffer Register 9                                 */
3368 
3369         struct
3370         {
3371             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3372                                         *   registers that sequentially store all A/D converted values.
3373                                         *   The automatic clear function is not applied to these registers.           */
3374         } ADBUF9_b;
3375     };
3376 
3377     union
3378     {
3379         __IM uint16_t ADBUF10;         /*!< (@ 0x000000C4) A/D Data Buffer Register 10                                */
3380 
3381         struct
3382         {
3383             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3384                                         *   registers that sequentially store all A/D converted values.
3385                                         *   The automatic clear function is not applied to these registers.           */
3386         } ADBUF10_b;
3387     };
3388 
3389     union
3390     {
3391         __IM uint16_t ADBUF11;         /*!< (@ 0x000000C6) A/D Data Buffer Register 11                                */
3392 
3393         struct
3394         {
3395             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3396                                         *   registers that sequentially store all A/D converted values.
3397                                         *   The automatic clear function is not applied to these registers.           */
3398         } ADBUF11_b;
3399     };
3400 
3401     union
3402     {
3403         __IM uint16_t ADBUF12;         /*!< (@ 0x000000C8) A/D Data Buffer Register 12                                */
3404 
3405         struct
3406         {
3407             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3408                                         *   registers that sequentially store all A/D converted values.
3409                                         *   The automatic clear function is not applied to these registers.           */
3410         } ADBUF12_b;
3411     };
3412 
3413     union
3414     {
3415         __IM uint16_t ADBUF13;         /*!< (@ 0x000000CA) A/D Data Buffer Register 13                                */
3416 
3417         struct
3418         {
3419             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3420                                         *   registers that sequentially store all A/D converted values.
3421                                         *   The automatic clear function is not applied to these registers.           */
3422         } ADBUF13_b;
3423     };
3424 
3425     union
3426     {
3427         __IM uint16_t ADBUF14;         /*!< (@ 0x000000CC) A/D Data Buffer Register 14                                */
3428 
3429         struct
3430         {
3431             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3432                                         *   registers that sequentially store all A/D converted values.
3433                                         *   The automatic clear function is not applied to these registers.           */
3434         } ADBUF14_b;
3435     };
3436 
3437     union
3438     {
3439         __IM uint16_t ADBUF15;         /*!< (@ 0x000000CE) A/D Data Buffer Register 15                                */
3440 
3441         struct
3442         {
3443             __IM uint16_t ADBUF : 16;  /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only
3444                                         *   registers that sequentially store all A/D converted values.
3445                                         *   The automatic clear function is not applied to these registers.           */
3446         } ADBUF15_b;
3447     };
3448 
3449     union
3450     {
3451         __IOM uint8_t ADBUFEN;         /*!< (@ 0x000000D0) A/D Data Buffer Enable Register                            */
3452 
3453         struct
3454         {
3455             __IOM uint8_t BUFEN : 1;   /*!< [0..0] Data Buffer Enable                                                 */
3456             uint8_t             : 7;
3457         } ADBUFEN_b;
3458     };
3459     __IM uint8_t RESERVED14;
3460 
3461     union
3462     {
3463         __IOM uint8_t ADBUFPTR;        /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register                           */
3464 
3465         struct
3466         {
3467             __IM uint8_t BUFPTR : 4;   /*!< [3..0] Data Buffer PointerThese bits indicate the number of
3468                                         *   data buffer to which the next A/D converted data is transferred.          */
3469             __IM uint8_t PTROVF : 1;   /*!< [4..4] Pointer Overflow Flag                                              */
3470             uint8_t             : 3;
3471         } ADBUFPTR_b;
3472     };
3473     __IM uint8_t  RESERVED15;
3474     __IM uint32_t RESERVED16[2];
3475     __IM uint8_t  RESERVED17;
3476 
3477     union
3478     {
3479         __IOM uint8_t ADSSTRL;         /*!< (@ 0x000000DD) A/D Sampling State Register L                              */
3480 
3481         struct
3482         {
3483             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (AN016-AN027)                                */
3484         } ADSSTRL_b;
3485     };
3486 
3487     union
3488     {
3489         __IOM uint8_t ADSSTRT;         /*!< (@ 0x000000DE) A/D Sampling State Register T                              */
3490 
3491         struct
3492         {
3493             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (temperature sensor output)                  */
3494         } ADSSTRT_b;
3495     };
3496 
3497     union
3498     {
3499         __IOM uint8_t ADSSTRO;         /*!< (@ 0x000000DF) A/D Sampling State Register O                              */
3500 
3501         struct
3502         {
3503             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting (Internal reference voltage)                 */
3504         } ADSSTRO_b;
3505     };
3506 
3507     union
3508     {
3509         __IOM uint8_t ADSSTR[16];      /*!< (@ 0x000000E0) A/D Sampling State Registers                               */
3510 
3511         struct
3512         {
3513             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling time setting                                              */
3514         } ADSSTR_b[16];
3515     };
3516 
3517     union
3518     {
3519         __IOM uint16_t ADANIM;         /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register                     */
3520 
3521         struct
3522         {
3523             __IOM uint16_t ANIM0 : 1;  /*!< [0..0] Analog Channel Input Mode Select                                   */
3524             __IOM uint16_t ANIM1 : 1;  /*!< [1..1] Analog Channel Input Mode Select                                   */
3525             __IOM uint16_t ANIM2 : 1;  /*!< [2..2] Analog Channel Input Mode Select                                   */
3526             __IOM uint16_t ANIM3 : 1;  /*!< [3..3] Analog Channel Input Mode Select                                   */
3527             uint16_t             : 12;
3528         } ADANIM_b;
3529     };
3530 
3531     union
3532     {
3533         __IOM uint8_t ADCALEXE;        /*!< (@ 0x000000F2) A/D Calibration Execution Register                         */
3534 
3535         struct
3536         {
3537             uint8_t              : 6;
3538             __IM uint8_t  CALMON : 1;  /*!< [6..6] Calibration Status Flag                                            */
3539             __IOM uint8_t CALEXE : 1;  /*!< [7..7] Calibration Start                                                  */
3540         } ADCALEXE_b;
3541     };
3542     __IM uint8_t RESERVED18;
3543 
3544     union
3545     {
3546         __IOM uint8_t VREFAMPCNT;        /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control
3547                                           *                  Register                                                   */
3548 
3549         struct
3550         {
3551             __IOM uint8_t OLDETEN   : 1; /*!< [0..0] OLDET Enable                                                       */
3552             __IOM uint8_t VREFADCG  : 2; /*!< [2..1] VREFADC Output Voltage Control                                     */
3553             __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable                                                    */
3554             __IOM uint8_t BGREN     : 1; /*!< [4..4] BGR Enable                                                         */
3555             uint8_t                 : 2;
3556             __IOM uint8_t ADSLP     : 1; /*!< [7..7] Sleep                                                              */
3557         } VREFAMPCNT_b;
3558     };
3559     __IM uint8_t  RESERVED19;
3560     __IM uint16_t RESERVED20;
3561 
3562     union
3563     {
3564         __IOM uint16_t ADRD;           /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register                           */
3565 
3566         struct
3567         {
3568             __IM uint16_t AD : 16;     /*!< [15..0] Converted Value 15 to 0                                           */
3569         } ADRD_b;
3570     };
3571 
3572     union
3573     {
3574         __IM uint8_t ADRST;            /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register                        */
3575 
3576         struct
3577         {
3578             __IM uint8_t DIAGST : 2;   /*!< [1..0] Self-Diagnosis Status                                              */
3579             uint8_t             : 6;
3580         } ADRST_b;
3581     };
3582     __IM uint8_t  RESERVED21;
3583     __IM uint32_t RESERVED22[41];
3584 
3585     union
3586     {
3587         __IOM uint16_t ADPGACR;           /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register           */
3588 
3589         struct
3590         {
3591             __IOM uint16_t P000SEL0  : 1; /*!< [0..0] A through amplifier is enable for PGA P000                         */
3592             __IOM uint16_t P000SEL1  : 1; /*!< [1..1] The amplifier passing is enable for PGA P000                       */
3593             __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000                                  */
3594             __IOM uint16_t P000GEN   : 1; /*!< [3..3] PGA P000 gain setting and enable bit                               */
3595             __IOM uint16_t P001SEL0  : 1; /*!< [4..4] A through amplifier is enable for PGA P001                         */
3596             __IOM uint16_t P001SEL1  : 1; /*!< [5..5] The amplifier passing is enable for PGA P001                       */
3597             __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001                                  */
3598             __IOM uint16_t P001GEN   : 1; /*!< [7..7] PGA P001 gain setting and enable bit                               */
3599             __IOM uint16_t P002SEL0  : 1; /*!< [8..8] A through amplifier is enable for PGA P002                         */
3600             __IOM uint16_t P002SEL1  : 1; /*!< [9..9] The amplifier passing is enable for PGA P002                       */
3601             __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002                                */
3602             __IOM uint16_t P002GEN   : 1; /*!< [11..11] PGA P002 gain setting and enable bit                             */
3603             __IOM uint16_t P003SEL0  : 1; /*!< [12..12] A through amplifier is enable for PGA P003                       */
3604             __IOM uint16_t P003SEL1  : 1; /*!< [13..13] The amplifier passing is enable for PGA P003                     */
3605             __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003                                */
3606             __IOM uint16_t P003GEN   : 1; /*!< [15..15] PGA P003 gain setting and enable bit                             */
3607         } ADPGACR_b;
3608     };
3609 
3610     union
3611     {
3612         __IOM uint16_t ADPGAGS0;         /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting
3613                                           *                  Register 0                                                 */
3614 
3615         struct
3616         {
3617             __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=
3618                                           *   b) when the shingle end is input and each PGA P000 is set.
3619                                           *   When the differential motion is input, (ADPGSDCR0.P000GEN=1b)
3620                                           *   sets the gain magnification when the differential motion
3621                                           *   is input by the combination with ADPGSDCR0.P000DG 1:0.                    */
3622             __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=
3623                                           *   b) when the shingle end is input and each PGA P001 is set.
3624                                           *   When the differential motion is input, (ADPGSDCR0.P001GEN=1b)
3625                                           *   sets the gain magnification when the differential motion
3626                                           *   is input by the combination with ADPGSDCR0.P001DG 1:0.                    */
3627             __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of
3628                                           *   (ADPGSDCR0.P002GEN=0b) when the shingle end is input and
3629                                           *   each PGA P002 is set. When the differential motion is input,
3630                                           *   (ADPGSDCR0.P002GEN=1b) sets the gain magnification when
3631                                           *   the differential motion is input by the combination with
3632                                           *   ADPGSDCR0.P002DG 1:0.                                                     */
3633             __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of
3634                                           *   (ADPGSDCR0.P003GEN=0b) when the shingle end is input and
3635                                           *   each PGA P003 is set. When the differential motion is input,
3636                                           *   (ADPGSDCR0.P003GEN=1b) sets the gain magnification when
3637                                           *   the differential motion is input by the combination with
3638                                           *   ADPGSDCR0.P003DG 1:0.                                                     */
3639         } ADPGAGS0_b;
3640     };
3641     __IM uint32_t RESERVED23[3];
3642 
3643     union
3644     {
3645         __IOM uint16_t ADPGADCR0;       /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential
3646                                          *                  Input Control Register                                     */
3647 
3648         struct
3649         {
3650             __IOM uint16_t P000DG : 2;  /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these
3651                                          *   bits are used, set {P000DEN, P000GEN} to 11b.                             */
3652             uint16_t               : 1;
3653             __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable                                     */
3654             __IOM uint16_t P001DG  : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these
3655                                          *   bits are used, set {P001DEN, P001GEN} to 11b.                             */
3656             uint16_t               : 1;
3657             __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable                                     */
3658             __IOM uint16_t P002DG  : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these
3659                                          *   bits are used, set {P002DEN, P002GEN} to 11b.                             */
3660             uint16_t               : 1;
3661             __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable                                   */
3662             __IOM uint16_t P003DG  : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these
3663                                          *   bits are used, set {P003DEN, P003GEN} to 11b.                             */
3664             uint16_t               : 1;
3665             __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable                                   */
3666         } ADPGADCR0_b;
3667     };
3668     __IM uint16_t RESERVED24;
3669 
3670     union
3671     {
3672         __IOM uint8_t ADPGADBS0;       /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential
3673                                         *                  Input Bias Select Register 0                               */
3674 
3675         struct
3676         {
3677             __IOM uint8_t P0BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage
3678                                         *   SelectNOTE: This bit selects the input bias voltage value
3679                                         *   when differential inputs are used.                                        */
3680             uint8_t : 7;
3681         } ADPGADBS0_b;
3682     };
3683 
3684     union
3685     {
3686         __IOM uint8_t ADPGADBS1;       /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential
3687                                         *                  Input Bias Select Register 1                               */
3688 
3689         struct
3690         {
3691             __IOM uint8_t P3BIAS : 1;  /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE:
3692                                         *   This bit selects the input bias voltage value when differential
3693                                         *   inputs are used.                                                          */
3694             uint8_t : 7;
3695         } ADPGADBS1_b;
3696     };
3697     __IM uint16_t RESERVED25;
3698     __IM uint32_t RESERVED26[10];
3699 
3700     union
3701     {
3702         __IOM uint32_t ADREFMON;       /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register            */
3703 
3704         struct
3705         {
3706             __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable                                          */
3707             uint32_t              : 13;
3708             __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit.                                    */
3709             uint32_t              : 12;
3710         } ADREFMON_b;
3711     };
3712 } R_ADC0_Type;                         /*!< Size = 484 (0x1e4)                                                        */
3713 
3714 /* =========================================================================================================================== */
3715 /* ================                                          R_PSCU                                           ================ */
3716 /* =========================================================================================================================== */
3717 
3718 /**
3719  * @brief Peripheral Security Control Unit (R_PSCU)
3720  */
3721 
3722 typedef struct                         /*!< (@ 0x400E0000) R_PSCU Structure                                           */
3723 {
3724     __IM uint32_t RESERVED;
3725 
3726     union
3727     {
3728         __IOM uint32_t PSARB;          /*!< (@ 0x00000004) Peripheral Security Attribution Register B                 */
3729 
3730         struct
3731         {
3732             uint32_t               : 1;
3733             __IOM uint32_t PSARB1  : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution               */
3734             __IOM uint32_t PSARB2  : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution               */
3735             __IOM uint32_t PSARB3  : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution                */
3736             uint32_t               : 2;
3737             __IM uint32_t  PSARB6  : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution               */
3738             __IOM uint32_t PSARB7  : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution               */
3739             __IOM uint32_t PSARB8  : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution               */
3740             __IOM uint32_t PSARB9  : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution               */
3741             uint32_t               : 1;
3742             __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution           */
3743             __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution           */
3744             uint32_t               : 2;
3745             __IM uint32_t PSARB15  : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0
3746                                          *   bit security attribution                                                  */
3747             __IM uint32_t PSARB16  : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution            */
3748             uint32_t               : 1;
3749             __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution           */
3750             __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution           */
3751             uint32_t               : 2;
3752             __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution            */
3753             __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution            */
3754             __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution            */
3755             __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution            */
3756             __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution            */
3757             __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution            */
3758             __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution            */
3759             __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution            */
3760             __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution            */
3761             __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution            */
3762         } PSARB_b;
3763     };
3764 
3765     union
3766     {
3767         __IOM uint32_t PSARC;           /*!< (@ 0x00000008) Peripheral Security Attribution Register C                 */
3768 
3769         struct
3770         {
3771             __IOM uint32_t PSARC0  : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution                */
3772             __IOM uint32_t PSARC1  : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution                */
3773             uint32_t               : 1;
3774             __IOM uint32_t PSARC3  : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution               */
3775             uint32_t               : 4;
3776             __IOM uint32_t PSARC8  : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution              */
3777             uint32_t               : 3;
3778             __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution           */
3779             __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution             */
3780             uint32_t               : 6;
3781             __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution             */
3782             uint32_t               : 6;
3783             __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution          */
3784             uint32_t               : 3;
3785             __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution            */
3786         } PSARC_b;
3787     };
3788 
3789     union
3790     {
3791         __IOM uint32_t PSARD;           /*!< (@ 0x0000000C) Peripheral Security Attribution Register D                 */
3792 
3793         struct
3794         {
3795             __IOM uint32_t PSARD0  : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution               */
3796             __IOM uint32_t PSARD1  : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution               */
3797             __IOM uint32_t PSARD2  : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution               */
3798             __IOM uint32_t PSARD3  : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution               */
3799             uint32_t               : 7;
3800             __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution            */
3801             __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution            */
3802             __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution            */
3803             __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution            */
3804             __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution            */
3805             __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution            */
3806             uint32_t               : 2;
3807             __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution          */
3808             __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution          */
3809             uint32_t               : 1;
3810             __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution             */
3811             uint32_t               : 2;
3812             __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution         */
3813             __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution         */
3814             __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution         */
3815             __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution         */
3816             uint32_t               : 3;
3817         } PSARD_b;
3818     };
3819 
3820     union
3821     {
3822         __IOM uint32_t PSARE;           /*!< (@ 0x00000010) Peripheral Security Attribution Register E                 */
3823 
3824         struct
3825         {
3826             __IOM uint32_t PSARE0  : 1; /*!< [0..0] WDT security attribution                                           */
3827             __IOM uint32_t PSARE1  : 1; /*!< [1..1] IWDT security attribution                                          */
3828             __IOM uint32_t PSARE2  : 1; /*!< [2..2] RTC security attribution                                           */
3829             uint32_t               : 11;
3830             __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution            */
3831             __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution            */
3832             uint32_t               : 6;
3833             __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution            */
3834             __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution            */
3835             __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution            */
3836             __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution            */
3837             __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution            */
3838             __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution            */
3839             __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution            */
3840             __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution            */
3841             __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution            */
3842             __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution            */
3843         } PSARE_b;
3844     };
3845 
3846     union
3847     {
3848         __IOM uint32_t MSSAR;          /*!< (@ 0x00000014) Module Stop Security Attribution Register                  */
3849 
3850         struct
3851         {
3852             __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution                       */
3853             __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution                       */
3854             __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution                        */
3855             __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution                        */
3856             uint32_t              : 28;
3857         } MSSAR_b;
3858     };
3859 
3860     union
3861     {
3862         __IOM uint32_t CFSAMONA;       /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register
3863                                         *                  A                                                          */
3864 
3865         struct
3866         {
3867             uint32_t            : 15;
3868             __IOM uint32_t CFS2 : 9;   /*!< [23..15] Code Flash Secure area 2                                         */
3869             uint32_t            : 8;
3870         } CFSAMONA_b;
3871     };
3872 
3873     union
3874     {
3875         __IOM uint32_t CFSAMONB;       /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register
3876                                         *                  B                                                          */
3877 
3878         struct
3879         {
3880             uint32_t            : 10;
3881             __IOM uint32_t CFS1 : 14;  /*!< [23..10] Code Flash Secure area 1                                         */
3882             uint32_t            : 8;
3883         } CFSAMONB_b;
3884     };
3885 
3886     union
3887     {
3888         __IOM uint32_t DFSAMON;        /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register           */
3889 
3890         struct
3891         {
3892             uint32_t           : 10;
3893             __IOM uint32_t DFS : 6;    /*!< [15..10] Data flash Secure area                                           */
3894             uint32_t           : 16;
3895         } DFSAMON_b;
3896     };
3897 
3898     union
3899     {
3900         __IOM uint32_t SSAMONA;        /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A               */
3901 
3902         struct
3903         {
3904             uint32_t           : 13;
3905             __IOM uint32_t SS2 : 8;    /*!< [20..13] SRAM Secure area 2                                               */
3906             uint32_t           : 11;
3907         } SSAMONA_b;
3908     };
3909 
3910     union
3911     {
3912         __IOM uint32_t SSAMONB;        /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B               */
3913 
3914         struct
3915         {
3916             uint32_t           : 10;
3917             __IOM uint32_t SS1 : 11;   /*!< [20..10] SRAM secure area 1                                               */
3918             uint32_t           : 11;
3919         } SSAMONB_b;
3920     };
3921 
3922     union
3923     {
3924         __IM uint32_t DLMMON;          /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register         */
3925 
3926         struct
3927         {
3928             __IM uint32_t DLMMON : 4;  /*!< [3..0] Device Lifecycle Management State Monitor                          */
3929             uint32_t             : 28;
3930         } DLMMON_b;
3931     };
3932 } R_PSCU_Type;                         /*!< Size = 48 (0x30)                                                          */
3933 
3934 /* =========================================================================================================================== */
3935 /* ================                                           R_BUS                                           ================ */
3936 /* =========================================================================================================================== */
3937 
3938 /**
3939  * @brief Bus Interface (R_BUS)
3940  */
3941 
3942 typedef struct                          /*!< (@ 0x40003000) R_BUS Structure                                            */
3943 {
3944     __IOM R_BUS_CSa_Type CSa[8];        /*!< (@ 0x00000000) CS Registers                                               */
3945     __IM uint32_t        RESERVED[480];
3946     __IOM R_BUS_CSb_Type CSb[8];        /*!< (@ 0x00000800) CS Registers                                               */
3947 
3948     union
3949     {
3950         __IOM uint16_t CSRECEN;         /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register                */
3951 
3952         struct
3953         {
3954             __IOM uint16_t RCVEN0  : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable                       */
3955             __IOM uint16_t RCVEN1  : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable                       */
3956             __IOM uint16_t RCVEN2  : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable                       */
3957             __IOM uint16_t RCVEN3  : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable                       */
3958             __IOM uint16_t RCVEN4  : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable                       */
3959             __IOM uint16_t RCVEN5  : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable                       */
3960             __IOM uint16_t RCVEN6  : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable                       */
3961             __IOM uint16_t RCVEN7  : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable                       */
3962             __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable                    */
3963             __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable                    */
3964             __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3965             __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3966             __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3967             __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3968             __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3969             __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable                  */
3970         } CSRECEN_b;
3971     };
3972     __IM uint16_t          RESERVED1;
3973     __IM uint32_t          RESERVED2[223];
3974     __IOM R_BUS_SDRAM_Type SDRAM;      /*!< (@ 0x00000C00) SDRAM Registers                                            */
3975     __IM uint32_t          RESERVED3[235];
3976 
3977     union
3978     {
3979         __IOM R_BUS_OAD_Type  OAD;     /*!< (@ 0x00001000) Bus Operation After Detection Registers                    */
3980         __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Registers                               */
3981     };
3982     __IM uint32_t RESERVED4[58];
3983 
3984     union
3985     {
3986         union
3987         {
3988             __IOM uint32_t BUSMABT;      /*!< (@ 0x00001100) Bus Master Arbitration Control Register.                   */
3989 
3990             struct
3991             {
3992                 __IOM uint32_t ARBS : 1; /*!< [0..0] Arbitration Select for GDSSBI.                                     */
3993                 uint32_t            : 31;
3994             } BUSMABT_b;
3995         };
3996         __IOM R_BUS_BUSS_Type BUSS[18];  /*!< (@ 0x00001100) Slave Bus Control Register Array                           */
3997     };
3998     __IM uint32_t RESERVED5[46];
3999 
4000     union
4001     {
4002         __IOM R_BUS_BUSSABT0_Type BUSSABT0; /*!< (@ 0x00001200) Bus Slave Arbitration Control 0 Registers                  */
4003         __IOM R_BUS_BUSSABT1_Type BUSSABT1; /*!< (@ 0x00001200) Bus Slave Arbitration Control 1 Registers                  */
4004     };
4005     __IM uint32_t RESERVED6[33];
4006 
4007     union
4008     {
4009         __IOM uint32_t BUSDIVBYP;        /*!< (@ 0x00001300) Bus Divider Bypass Register.                               */
4010 
4011         struct
4012         {
4013             __IOM uint32_t EDMABPE  : 1; /*!< [0..0] Divider for EDMACBI bypass enable.                                 */
4014             uint32_t                : 2;
4015             __IOM uint32_t GDSSBPE  : 1; /*!< [3..3] Divider for GDSSBI bypass enable.                                  */
4016             uint32_t                : 12;
4017             __IOM uint32_t CPU0SBPE : 1; /*!< [16..16] Divider for CPUSAHBI bypass enable.                              */
4018             uint32_t                : 15;
4019         } BUSDIVBYP_b;
4020     };
4021     __IM uint32_t            RESERVED7[319];
4022     __IOM R_BUS_BUSERRa_Type BUSERRa[12]; /*!< (@ 0x00001800) Bus Error Registers                                        */
4023     __IM uint32_t            RESERVED8[16];
4024 
4025     union
4026     {
4027         __IOM R_BUS_BTZFERR_Type BTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers                                    */
4028         __IOM R_BUS_BMSAERR_Type BMSAERR[9]; /*!< (@ 0x00001900) Bus Master Security Attribution Unit Error Address
4029                                               *                  and Read/Write Status registers.                           */
4030     };
4031     __IM uint32_t RESERVED9[28];
4032 
4033     union
4034     {
4035         __IOM R_BUS_BUSERRb_Type    BUSERRb[12]; /*!< (@ 0x00001A00) Bus Error Registers                                        */
4036         __IOM R_BUS_DMACDTCERR_Type DMACDTCERR;  /*!< (@ 0x00001A00) DMAC/DTC Error Registers                                   */
4037     };
4038     __IM uint32_t           RESERVED10[16];
4039     __IOM R_BUS_MBWERR_Type MBWERR;              /*!< (@ 0x00001B00) Master Bufferable Write Error Registers                    */
4040     __IM uint32_t           RESERVED11[5];
4041     __IOM R_BUS_MBWERR_Type SBWERR;              /*!< (@ 0x00001B20) Slave Bufferable Write Error Registers                     */
4042 } R_BUS_Type;                                    /*!< Size = 6956 (0x1b2c)                                                      */
4043 
4044 /* =========================================================================================================================== */
4045 /* ================                                           R_CAC                                           ================ */
4046 /* =========================================================================================================================== */
4047 
4048 /**
4049  * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC)
4050  */
4051 
4052 typedef struct                         /*!< (@ 0x40083600) R_CAC Structure                                            */
4053 {
4054     union
4055     {
4056         __IOM uint8_t CACR0;           /*!< (@ 0x00000000) CAC Control Register 0                                     */
4057 
4058         struct
4059         {
4060             __IOM uint8_t CFME : 1;    /*!< [0..0] Clock Frequency Measurement Enable.                                */
4061             uint8_t            : 7;
4062         } CACR0_b;
4063     };
4064 
4065     union
4066     {
4067         __IOM uint8_t CACR1;           /*!< (@ 0x00000001) CAC Control Register 1                                     */
4068 
4069         struct
4070         {
4071             __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable                                            */
4072             __IOM uint8_t FMCS    : 3; /*!< [3..1] Measurement Target Clock Select                                    */
4073             __IOM uint8_t TCSS    : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select           */
4074             __IOM uint8_t EDGES   : 2; /*!< [7..6] Valid Edge Select                                                  */
4075         } CACR1_b;
4076     };
4077 
4078     union
4079     {
4080         __IOM uint8_t CACR2;           /*!< (@ 0x00000002) CAC Control Register 2                                     */
4081 
4082         struct
4083         {
4084             __IOM uint8_t RPS  : 1;    /*!< [0..0] Reference Signal Select                                            */
4085             __IOM uint8_t RSCS : 3;    /*!< [3..1] Measurement Reference Clock Select                                 */
4086             __IOM uint8_t RCDS : 2;    /*!< [5..4] Measurement Reference Clock Frequency Division Ratio
4087                                         *   Select                                                                    */
4088             __IOM uint8_t DFS : 2;     /*!< [7..6] Digital Filter Selection                                           */
4089         } CACR2_b;
4090     };
4091 
4092     union
4093     {
4094         __IOM uint8_t CAICR;           /*!< (@ 0x00000003) CAC Interrupt Control Register                             */
4095 
4096         struct
4097         {
4098             __IOM uint8_t FERRIE : 1;  /*!< [0..0] Frequency Error Interrupt Request Enable                           */
4099             __IOM uint8_t MENDIE : 1;  /*!< [1..1] Measurement End Interrupt Request Enable                           */
4100             __IOM uint8_t OVFIE  : 1;  /*!< [2..2] Overflow Interrupt Request Enable                                  */
4101             uint8_t              : 1;
4102             __OM uint8_t FERRFCL : 1;  /*!< [4..4] FERRF Clear                                                        */
4103             __OM uint8_t MENDFCL : 1;  /*!< [5..5] MENDF Clear                                                        */
4104             __OM uint8_t OVFFCL  : 1;  /*!< [6..6] OVFF Clear                                                         */
4105             uint8_t              : 1;
4106         } CAICR_b;
4107     };
4108 
4109     union
4110     {
4111         __IM uint8_t CASTR;            /*!< (@ 0x00000004) CAC Status Register                                        */
4112 
4113         struct
4114         {
4115             __IM uint8_t FERRF : 1;    /*!< [0..0] Frequency Error Flag                                               */
4116             __IM uint8_t MENDF : 1;    /*!< [1..1] Measurement End Flag                                               */
4117             __IM uint8_t OVFF  : 1;    /*!< [2..2] Counter Overflow Flag                                              */
4118             uint8_t            : 5;
4119         } CASTR_b;
4120     };
4121     __IM uint8_t RESERVED;
4122 
4123     union
4124     {
4125         __IOM uint16_t CAULVR;          /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register                     */
4126 
4127         struct
4128         {
4129             __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores
4130                                          *   the upper-limit value of the frequency.                                   */
4131         } CAULVR_b;
4132     };
4133 
4134     union
4135     {
4136         __IOM uint16_t CALLVR;          /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register                     */
4137 
4138         struct
4139         {
4140             __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores
4141                                          *   the lower-limit value of the frequency.                                   */
4142         } CALLVR_b;
4143     };
4144 
4145     union
4146     {
4147         __IM uint16_t CACNTBR;          /*!< (@ 0x0000000A) CAC Counter Buffer Register                                */
4148 
4149         struct
4150         {
4151             __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains
4152                                          *   the counter value at the time a valid reference signal
4153                                          *   edge is input                                                             */
4154         } CACNTBR_b;
4155     };
4156 } R_CAC_Type;                           /*!< Size = 12 (0xc)                                                           */
4157 
4158 /* =========================================================================================================================== */
4159 /* ================                                          R_CANFD                                          ================ */
4160 /* =========================================================================================================================== */
4161 
4162 /**
4163  * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD)
4164  */
4165 
4166 typedef struct                         /*!< (@ 0x400B0000) R_CANFD Structure                                          */
4167 {
4168     __IOM R_CANFD_CFDC_Type CFDC[2];   /*!< (@ 0x00000000) Channel Control/Status                                     */
4169     __IM uint32_t           RESERVED[25];
4170 
4171     union
4172     {
4173         __IOM uint32_t CFDGCFG;         /*!< (@ 0x00000084) Global Configuration Register                              */
4174 
4175         struct
4176         {
4177             __IOM uint32_t TPRI   : 1;  /*!< [0..0] Transmission Priority                                              */
4178             __IOM uint32_t DCE    : 1;  /*!< [1..1] DLC Check Enable                                                   */
4179             __IOM uint32_t DRE    : 1;  /*!< [2..2] DLC Replacement Enable                                             */
4180             __IOM uint32_t MME    : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
4181             __IOM uint32_t DCS    : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
4182             __IOM uint32_t CMPOC  : 1;  /*!< [5..5] CAN-FD message Payload overflow configuration                      */
4183             uint32_t              : 2;
4184             __IOM uint32_t TSP    : 4;  /*!< [11..8] Timestamp Prescaler                                               */
4185             __IOM uint32_t TSSS   : 1;  /*!< [12..12] Timestamp Source Select                                          */
4186             __IOM uint32_t TSBTCS : 3;  /*!< [15..13] Timestamp Bit Time Channel Select                                */
4187             __IOM uint32_t ITRCP  : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
4188         } CFDGCFG_b;
4189     };
4190 
4191     union
4192     {
4193         __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000088) Global Control Register                                    */
4194 
4195         struct
4196         {
4197             __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
4198             __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
4199             uint32_t               : 5;
4200             __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC check Interrupt Enable                                         */
4201             __IOM uint32_t MEIE    : 1; /*!< [9..9] Message lost Error Interrupt Enable                                */
4202             __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
4203             __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable            */
4204             uint32_t               : 2;
4205             __IOM uint32_t QMEIE   : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable                          */
4206             __IOM uint32_t MOWEIE  : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable                 */
4207             __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
4208             __IOM uint32_t TSWR    : 1; /*!< [17..17] Timestamp Write                                                  */
4209             uint32_t               : 14;
4210         } CFDGCTR_b;
4211     };
4212 
4213     union
4214     {
4215         __IOM uint32_t CFDGSTS;         /*!< (@ 0x0000008C) Global Status Register                                     */
4216 
4217         struct
4218         {
4219             __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
4220             __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
4221             __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
4222             __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation                                          */
4223             uint32_t               : 28;
4224         } CFDGSTS_b;
4225     };
4226 
4227     union
4228     {
4229         __IOM uint32_t CFDGERFL;          /*!< (@ 0x00000090) Global Error Flag Register                                 */
4230 
4231         struct
4232         {
4233             __IOM uint32_t DEF       : 1; /*!< [0..0] DLC Error Flag                                                     */
4234             __IM uint32_t  MES       : 1; /*!< [1..1] Message Lost Error Status                                          */
4235             __IM uint32_t  THLES     : 1; /*!< [2..2] TX History List Entry Lost Error Status                            */
4236             __IOM uint32_t CMPOF     : 1; /*!< [3..3] CAN-FD message payload overflow Flag                               */
4237             __IM uint32_t  QOWES     : 1; /*!< [4..4] TXQ Message overwrite Error Status                                 */
4238             __IM uint32_t  OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status                                       */
4239             __IM uint32_t  QMES      : 1; /*!< [6..6] TXQ Message Lost Error Status                                      */
4240             uint32_t                 : 1;
4241             __IOM uint32_t RXSFAIL0  : 1; /*!< [8..8] RX Scan Fail of Channel 0                                          */
4242             __IOM uint32_t RXSFAIL1  : 1; /*!< [9..9] RX Scan Fail of Channel 1                                          */
4243             uint32_t                 : 6;
4244             __IOM uint32_t EEF0      : 1; /*!< [16..16] ECC Error Flag for Channel 0                                     */
4245             __IOM uint32_t EEF1      : 1; /*!< [17..17] ECC Error Flag for Channel 1                                     */
4246             uint32_t                 : 14;
4247         } CFDGERFL_b;
4248     };
4249 
4250     union
4251     {
4252         __IOM uint32_t CFDGTSC;        /*!< (@ 0x00000094) Global Timestamp Counter Register                          */
4253 
4254         struct
4255         {
4256             __IM uint32_t TS : 16;     /*!< [15..0] Timestamp Value                                                   */
4257             uint32_t         : 16;
4258         } CFDGTSC_b;
4259     };
4260 
4261     union
4262     {
4263         __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register       */
4264 
4265         struct
4266         {
4267             __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
4268             uint32_t              : 4;
4269             __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
4270             uint32_t              : 23;
4271         } CFDGAFLECTR_b;
4272     };
4273 
4274     union
4275     {
4276         __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register
4277                                         *                  0                                                          */
4278 
4279         struct
4280         {
4281             __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
4282             uint32_t            : 7;
4283             __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
4284             uint32_t            : 7;
4285         } CFDGAFLCFG0_b;
4286     };
4287     __IM uint32_t RESERVED1[3];
4288 
4289     union
4290     {
4291         __IOM uint32_t CFDRMNB;        /*!< (@ 0x000000AC) RX Message Buffer Number Register                          */
4292 
4293         struct
4294         {
4295             __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
4296             __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
4297             uint32_t             : 21;
4298         } CFDRMNB_b;
4299     };
4300 
4301     union
4302     {
4303         __IOM uint32_t CFDRMND0;       /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0                      */
4304 
4305         struct
4306         {
4307             __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status                                 */
4308         } CFDRMND0_b;
4309     };
4310     __IM uint32_t RESERVED2[3];
4311 
4312     union
4313     {
4314         __IOM uint32_t CFDRFCC[8];     /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers                  */
4315 
4316         struct
4317         {
4318             __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
4319             __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
4320             uint32_t              : 2;
4321             __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration                            */
4322             uint32_t              : 1;
4323             __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
4324             uint32_t              : 1;
4325             __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
4326             __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
4327             __IOM uint32_t RFFIE  : 1; /*!< [16..16] RX FIFO Full interrupt Enable                                    */
4328             uint32_t              : 15;
4329         } CFDRFCC_b[8];
4330     };
4331 
4332     union
4333     {
4334         __IOM uint32_t CFDRFSTS[8];    /*!< (@ 0x000000E0) RX FIFO Status Registers                                   */
4335 
4336         struct
4337         {
4338             __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
4339             __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
4340             __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
4341             __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
4342             uint32_t             : 4;
4343             __IM uint32_t  RFMC  : 8;  /*!< [15..8] RX FIFO Message Count                                             */
4344             __IOM uint32_t RFFIF : 1;  /*!< [16..16] RX FIFO Full Interrupt Flag                                      */
4345             uint32_t             : 15;
4346         } CFDRFSTS_b[8];
4347     };
4348 
4349     union
4350     {
4351         __IOM uint32_t CFDRFPCTR[8];   /*!< (@ 0x00000100) RX FIFO Pointer Control Registers                          */
4352 
4353         struct
4354         {
4355             __OM uint32_t RFPC : 8;    /*!< [7..0] RX FIFO Pointer Control                                            */
4356             uint32_t           : 24;
4357         } CFDRFPCTR_b[8];
4358     };
4359 
4360     union
4361     {
4362         __IOM uint32_t CFDCFCC[6];     /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers              */
4363 
4364         struct
4365         {
4366             __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
4367             __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
4368             __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
4369             uint32_t              : 1;
4370             __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data size configuration                        */
4371             uint32_t              : 1;
4372             __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
4373             __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
4374             __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
4375             __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
4376             __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
4377             __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
4378             __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
4379             __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
4380         } CFDCFCC_b[6];
4381     };
4382     __IM uint32_t RESERVED3[18];
4383 
4384     union
4385     {
4386         __IOM uint32_t CFDCFCCE[6];      /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement
4387                                           *                  Registers                                                  */
4388 
4389         struct
4390         {
4391             __IOM uint32_t CFFIE    : 1; /*!< [0..0] Common FIFO Full interrupt Enable                                  */
4392             __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable                   */
4393             __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable                */
4394             uint32_t                : 5;
4395             __IOM uint32_t CFMOWM   : 1; /*!< [8..8] Common FIFO message overwrite mode                                 */
4396             uint32_t                : 7;
4397             __IOM uint32_t CFBME    : 1; /*!< [16..16] Common FIFO Buffering Mode Enable                                */
4398             uint32_t                : 15;
4399         } CFDCFCCE_b[6];
4400     };
4401     __IM uint32_t RESERVED4[18];
4402 
4403     union
4404     {
4405         __IOM uint32_t CFDCFSTS[6];      /*!< (@ 0x000001E0) Common FIFO Status Registers                               */
4406 
4407         struct
4408         {
4409             __IM uint32_t  CFEMP    : 1; /*!< [0..0] Common FIFO Empty                                                  */
4410             __IM uint32_t  CFFLL    : 1; /*!< [1..1] Common FIFO Full                                                   */
4411             __IOM uint32_t CFMLT    : 1; /*!< [2..2] Common FIFO Message Lost                                           */
4412             __IOM uint32_t CFRXIF   : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
4413             __IOM uint32_t CFTXIF   : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
4414             uint32_t                : 3;
4415             __IM uint32_t  CFMC     : 8; /*!< [15..8] Common FIFO Message Count                                         */
4416             __IOM uint32_t CFFIF    : 1; /*!< [16..16] Common FIFO Full Interrupt Flag                                  */
4417             __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag                   */
4418             __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag                */
4419             uint32_t                : 5;
4420             __IOM uint32_t CFMOW    : 1; /*!< [24..24] Common FIFO message overwrite                                    */
4421             uint32_t                : 7;
4422         } CFDCFSTS_b[6];
4423     };
4424     __IM uint32_t RESERVED5[18];
4425 
4426     union
4427     {
4428         __IOM uint32_t CFDCFPCTR[6];   /*!< (@ 0x00000240) Common FIFO Pointer Control Registers                      */
4429 
4430         struct
4431         {
4432             __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
4433             uint32_t           : 24;
4434         } CFDCFPCTR_b[6];
4435     };
4436     __IM uint32_t RESERVED6[18];
4437 
4438     union
4439     {
4440         __IM uint32_t CFDFESTS;        /*!< (@ 0x000002A0) FIFO Empty Status Register                                 */
4441 
4442         struct
4443         {
4444             __IM uint32_t RFXEMP : 8;  /*!< [7..0] RX FIF0 Empty Status                                               */
4445             __IM uint32_t CFXEMP : 6;  /*!< [13..8] Common FIF0 Empty Status                                          */
4446             uint32_t             : 18;
4447         } CFDFESTS_b;
4448     };
4449 
4450     union
4451     {
4452         __IM uint32_t CFDFFSTS;        /*!< (@ 0x000002A4) FIFO Full Status Register                                  */
4453 
4454         struct
4455         {
4456             __IM uint32_t RFXFLL : 8;  /*!< [7..0] RX FIF0 Full Status                                                */
4457             __IM uint32_t CFXFLL : 6;  /*!< [13..8] Common FIF0 Full Status                                           */
4458             uint32_t             : 18;
4459         } CFDFFSTS_b;
4460     };
4461 
4462     union
4463     {
4464         __IM uint32_t CFDFMSTS;        /*!< (@ 0x000002A8) FIFO Message Lost Status Register                          */
4465 
4466         struct
4467         {
4468             __IM uint32_t RFXMLT : 8;  /*!< [7..0] RX FIFO Msg Lost Status                                            */
4469             __IM uint32_t CFXMLT : 6;  /*!< [13..8] Common FIFO Msg Lost Status                                       */
4470             uint32_t             : 18;
4471         } CFDFMSTS_b;
4472     };
4473 
4474     union
4475     {
4476         __IOM uint32_t CFDRFISTS;      /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register                     */
4477 
4478         struct
4479         {
4480             __IM uint32_t RFXIF   : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status                                   */
4481             uint32_t              : 8;
4482             __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status                            */
4483             uint32_t              : 8;
4484         } CFDRFISTS_b;
4485     };
4486 
4487     union
4488     {
4489         __IOM uint32_t CFDCFRISTS;     /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register              */
4490 
4491         struct
4492         {
4493             __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status                           */
4494             uint32_t              : 26;
4495         } CFDCFRISTS_b;
4496     };
4497 
4498     union
4499     {
4500         __IOM uint32_t CFDCFTISTS;     /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register              */
4501 
4502         struct
4503         {
4504             __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status                           */
4505             uint32_t              : 26;
4506         } CFDCFTISTS_b;
4507     };
4508 
4509     union
4510     {
4511         __IM uint32_t CFDCFOFRISTS;      /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status
4512                                           *                  Register                                                   */
4513 
4514         struct
4515         {
4516             __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status                 */
4517             uint32_t                : 26;
4518         } CFDCFOFRISTS_b;
4519     };
4520 
4521     union
4522     {
4523         __IM uint32_t CFDCFOFTISTS;      /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status
4524                                           *                  Register                                                   */
4525 
4526         struct
4527         {
4528             __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status                 */
4529             uint32_t                : 26;
4530         } CFDCFOFTISTS_b;
4531     };
4532 
4533     union
4534     {
4535         __IM uint32_t CFDCFMOWSTS;     /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register             */
4536 
4537         struct
4538         {
4539             __IM uint32_t CFXMOW : 6;  /*!< [5..0] Common FIFO [x] Massage overwrite status                           */
4540             uint32_t             : 26;
4541         } CFDCFMOWSTS_b;
4542     };
4543 
4544     union
4545     {
4546         __IM uint32_t CFDFFFSTS;       /*!< (@ 0x000002C4) FIFO FDC Full Status Register                              */
4547 
4548         struct
4549         {
4550             __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status                                      */
4551             __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status                                 */
4552             uint32_t              : 18;
4553         } CFDFFFSTS_b;
4554     };
4555     __IM uint32_t RESERVED7[2];
4556 
4557     union
4558     {
4559         __IOM uint8_t CFDTMC[128];     /*!< (@ 0x000002D0) TX Message Buffer Control Registers                        */
4560 
4561         struct
4562         {
4563             __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
4564             __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission abort Request                       */
4565             __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
4566             uint8_t             : 5;
4567         } CFDTMC_b[128];
4568     };
4569     __IM uint32_t RESERVED8[288];
4570 
4571     union
4572     {
4573         __IOM uint8_t CFDTMSTS[128];   /*!< (@ 0x000007D0) TX Message Buffer Status Registers                         */
4574 
4575         struct
4576         {
4577             __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
4578             __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
4579             __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
4580             __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored              */
4581             uint8_t              : 3;
4582         } CFDTMSTS_b[128];
4583     };
4584     __IM uint32_t RESERVED9[288];
4585 
4586     union
4587     {
4588         __IM uint32_t CFDTMTRSTS[4];       /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status
4589                                             *                  Register                                                   */
4590 
4591         struct
4592         {
4593             __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status                      */
4594             uint32_t                  : 24;
4595         } CFDTMTRSTS_b[4];
4596     };
4597     __IM uint32_t RESERVED10[36];
4598 
4599     union
4600     {
4601         __IM uint32_t CFDTMTARSTS[4];       /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request
4602                                              *                  Status Register                                            */
4603 
4604         struct
4605         {
4606             __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status                */
4607             uint32_t                   : 24;
4608         } CFDTMTARSTS_b[4];
4609     };
4610     __IM uint32_t RESERVED11[36];
4611 
4612     union
4613     {
4614         __IM uint32_t CFDTMTCSTS[4];       /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status
4615                                             *                  Register                                                   */
4616 
4617         struct
4618         {
4619             __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status                   */
4620             uint32_t                  : 24;
4621         } CFDTMTCSTS_b[4];
4622     };
4623     __IM uint32_t RESERVED12[36];
4624 
4625     union
4626     {
4627         __IM uint32_t CFDTMTASTS[4];       /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register       */
4628 
4629         struct
4630         {
4631             __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status                        */
4632             uint32_t                  : 24;
4633         } CFDTMTASTS_b[4];
4634     };
4635     __IM uint32_t RESERVED13[36];
4636 
4637     union
4638     {
4639         __IOM uint32_t CFDTMIEC[4];    /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration
4640                                         *                  Register                                                   */
4641 
4642         struct
4643         {
4644             __IOM uint32_t TMIEg : 8;  /*!< [7..0] TX Message Buffer Interrupt Enable                                 */
4645             uint32_t             : 24;
4646         } CFDTMIEC_b[4];
4647     };
4648     __IM uint32_t RESERVED14[40];
4649 
4650     union
4651     {
4652         __IOM uint32_t CFDTXQCC0[2];      /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0               */
4653 
4654         struct
4655         {
4656             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
4657             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
4658             uint32_t                 : 3;
4659             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4660             uint32_t                 : 1;
4661             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4662             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
4663             uint32_t                 : 3;
4664             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full interrupt Enable                                        */
4665             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
4666             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
4667             uint32_t                 : 13;
4668         } CFDTXQCC0_b[2];
4669     };
4670     __IM uint32_t RESERVED15[6];
4671 
4672     union
4673     {
4674         __IOM uint32_t CFDTXQSTS0[2];     /*!< (@ 0x00001020) TX Queue Status Registers 0                                */
4675 
4676         struct
4677         {
4678             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
4679             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
4680             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4681             uint32_t                 : 5;
4682             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
4683             uint32_t                 : 2;
4684             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
4685             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
4686             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
4687             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
4688             uint32_t                 : 12;
4689         } CFDTXQSTS0_b[2];
4690     };
4691     __IM uint32_t RESERVED16[6];
4692 
4693     union
4694     {
4695         __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0                       */
4696 
4697         struct
4698         {
4699             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4700             uint32_t            : 24;
4701         } CFDTXQPCTR0_b[2];
4702     };
4703     __IM uint32_t RESERVED17[6];
4704 
4705     union
4706     {
4707         __IOM uint32_t CFDTXQCC1[2];      /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1               */
4708 
4709         struct
4710         {
4711             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
4712             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
4713             uint32_t                 : 3;
4714             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4715             uint32_t                 : 1;
4716             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4717             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
4718             uint32_t                 : 3;
4719             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
4720             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
4721             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
4722             uint32_t                 : 13;
4723         } CFDTXQCC1_b[2];
4724     };
4725     __IM uint32_t RESERVED18[6];
4726 
4727     union
4728     {
4729         __IOM uint32_t CFDTXQSTS1[2];     /*!< (@ 0x00001080) TX Queue Status Registers 1                                */
4730 
4731         struct
4732         {
4733             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
4734             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
4735             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4736             uint32_t                 : 5;
4737             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
4738             uint32_t                 : 2;
4739             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
4740             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
4741             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
4742             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
4743             uint32_t                 : 12;
4744         } CFDTXQSTS1_b[2];
4745     };
4746     __IM uint32_t RESERVED19[6];
4747 
4748     union
4749     {
4750         __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1                       */
4751 
4752         struct
4753         {
4754             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4755             uint32_t            : 24;
4756         } CFDTXQPCTR1_b[2];
4757     };
4758     __IM uint32_t RESERVED20[6];
4759 
4760     union
4761     {
4762         __IOM uint32_t CFDTXQCC2[2];      /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2               */
4763 
4764         struct
4765         {
4766             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
4767             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
4768             uint32_t                 : 3;
4769             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4770             uint32_t                 : 1;
4771             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4772             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
4773             uint32_t                 : 3;
4774             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full interrupt Enable                                        */
4775             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
4776             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
4777             uint32_t                 : 13;
4778         } CFDTXQCC2_b[2];
4779     };
4780     __IM uint32_t RESERVED21[6];
4781 
4782     union
4783     {
4784         __IOM uint32_t CFDTXQSTS2[2];     /*!< (@ 0x000010E0) TX Queue Status Registers 2                                */
4785 
4786         struct
4787         {
4788             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
4789             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
4790             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4791             uint32_t                 : 5;
4792             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
4793             uint32_t                 : 2;
4794             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
4795             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
4796             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
4797             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
4798             uint32_t                 : 12;
4799         } CFDTXQSTS2_b[2];
4800     };
4801     __IM uint32_t RESERVED22[6];
4802 
4803     union
4804     {
4805         __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2                       */
4806 
4807         struct
4808         {
4809             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4810             uint32_t            : 24;
4811         } CFDTXQPCTR2_b[2];
4812     };
4813     __IM uint32_t RESERVED23[6];
4814 
4815     union
4816     {
4817         __IOM uint32_t CFDTXQCC3[2];      /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3               */
4818 
4819         struct
4820         {
4821             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
4822             uint32_t                 : 4;
4823             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4824             uint32_t                 : 1;
4825             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4826             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
4827             uint32_t                 : 5;
4828             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
4829             uint32_t                 : 13;
4830         } CFDTXQCC3_b[2];
4831     };
4832     __IM uint32_t RESERVED24[6];
4833 
4834     union
4835     {
4836         __IOM uint32_t CFDTXQSTS3[2];     /*!< (@ 0x00001140) TX Queue Status Registers 3                                */
4837 
4838         struct
4839         {
4840             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
4841             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
4842             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4843             uint32_t                 : 5;
4844             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
4845             uint32_t                 : 4;
4846             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
4847             uint32_t                 : 13;
4848         } CFDTXQSTS3_b[2];
4849     };
4850     __IM uint32_t RESERVED25[6];
4851 
4852     union
4853     {
4854         __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3                       */
4855 
4856         struct
4857         {
4858             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4859             uint32_t            : 24;
4860         } CFDTXQPCTR3_b[2];
4861     };
4862     __IM uint32_t RESERVED26[6];
4863 
4864     union
4865     {
4866         __IM uint32_t CFDTXQESTS;      /*!< (@ 0x00001180) TX Queue Empty Status Register                             */
4867 
4868         struct
4869         {
4870             __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status                                                   */
4871             uint32_t              : 24;
4872         } CFDTXQESTS_b;
4873     };
4874 
4875     union
4876     {
4877         __IOM uint32_t CFDTXQFISTS;     /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register                    */
4878 
4879         struct
4880         {
4881             __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0                            */
4882             uint32_t               : 1;
4883             __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1                            */
4884             uint32_t               : 25;
4885         } CFDTXQFISTS_b;
4886     };
4887 
4888     union
4889     {
4890         __IOM uint32_t CFDTXQMSTS;     /*!< (@ 0x00001188) TX Queue Message Lost Status Register                      */
4891 
4892         struct
4893         {
4894             __IM uint32_t TXQ0ML : 3;  /*!< [2..0] TXQ message lost Status for channel 0                              */
4895             uint32_t             : 1;
4896             __IM uint32_t TXQ1ML : 3;  /*!< [6..4] TXQ message lost Status for channel 1                              */
4897             uint32_t             : 25;
4898         } CFDTXQMSTS_b;
4899     };
4900     __IM uint32_t RESERVED27;
4901 
4902     union
4903     {
4904         __IOM uint32_t CFDTXQISTS;     /*!< (@ 0x00001190) TX Queue Interrupt Status Register                         */
4905 
4906         struct
4907         {
4908             __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0                            */
4909             __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1                            */
4910             uint32_t              : 24;
4911         } CFDTXQISTS_b;
4912     };
4913 
4914     union
4915     {
4916         __IOM uint32_t CFDTXQOFTISTS;     /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register            */
4917 
4918         struct
4919         {
4920             __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0               */
4921             __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1               */
4922             uint32_t                 : 24;
4923         } CFDTXQOFTISTS_b;
4924     };
4925 
4926     union
4927     {
4928         __IOM uint32_t CFDTXQOFRISTS;     /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register            */
4929 
4930         struct
4931         {
4932             __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag                             */
4933             uint32_t                 : 1;
4934             __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag                             */
4935             uint32_t                 : 25;
4936         } CFDTXQOFRISTS_b;
4937     };
4938 
4939     union
4940     {
4941         __IM uint32_t CFDTXQFSTS;      /*!< (@ 0x0000119C) TX Queue Full Status Register                              */
4942 
4943         struct
4944         {
4945             __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0                                 */
4946             __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1                                 */
4947             uint32_t              : 24;
4948         } CFDTXQFSTS_b;
4949     };
4950     __IM uint32_t RESERVED28[24];
4951 
4952     union
4953     {
4954         __IOM uint32_t CFDTHLCC[2];    /*!< (@ 0x00001200) TX History List Configuration / Control Register           */
4955 
4956         struct
4957         {
4958             __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
4959             uint32_t              : 7;
4960             __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
4961             __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
4962             __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
4963             __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable                              */
4964             uint32_t              : 20;
4965         } CFDTHLCC_b[2];
4966     };
4967     __IM uint32_t RESERVED29[6];
4968 
4969     union
4970     {
4971         __IOM uint32_t CFDTHLSTS[2];   /*!< (@ 0x00001220) TX History List Status Register                            */
4972 
4973         struct
4974         {
4975             __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
4976             __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
4977             __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
4978             __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
4979             uint32_t              : 4;
4980             __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
4981             uint32_t              : 18;
4982         } CFDTHLSTS_b[2];
4983     };
4984     __IM uint32_t RESERVED30[6];
4985 
4986     union
4987     {
4988         __IOM uint32_t CFDTHLPCTR[2];  /*!< (@ 0x00001240) TX History List Pointer Control Registers                  */
4989 
4990         struct
4991         {
4992             __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
4993             uint32_t            : 24;
4994         } CFDTHLPCTR_b[2];
4995     };
4996     __IM uint32_t RESERVED31[46];
4997 
4998     union
4999     {
5000         __IOM uint32_t CFDGTINTSTS0;   /*!< (@ 0x00001300) Global TX Interrupt Status Register 0                      */
5001 
5002         struct
5003         {
5004             __IM uint32_t TSIF0   : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
5005             __IM uint32_t TAIF0   : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
5006             __IM uint32_t TQIF0   : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
5007             __IM uint32_t CFTIF0  : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
5008             __IM uint32_t THIF0   : 1; /*!< [4..4] TX History List Interrupt Channel 0                                */
5009             __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel
5010                                         *   0                                                                         */
5011             __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel
5012                                         *   0                                                                         */
5013             uint32_t              : 1;
5014             __IM uint32_t TSIF1   : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1                             */
5015             __IM uint32_t TAIF1   : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1                                  */
5016             __IM uint32_t TQIF1   : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1                                */
5017             __IM uint32_t CFTIF1  : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1                     */
5018             __IM uint32_t THIF1   : 1; /*!< [12..12] TX History List Interrupt Channel 1                              */
5019             __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel
5020                                         *   1                                                                         */
5021             __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel
5022                                         *   1                                                                         */
5023             uint32_t : 17;
5024         } CFDGTINTSTS0_b;
5025     };
5026     __IM uint32_t RESERVED32;
5027 
5028     union
5029     {
5030         __IOM uint32_t CFDGTSTCFG;     /*!< (@ 0x00001308) Global Test Configuration Register                         */
5031 
5032         struct
5033         {
5034             __IOM uint32_t ICBCE : 2;  /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable          */
5035             uint32_t             : 14;
5036             __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
5037             uint32_t             : 6;
5038         } CFDGTSTCFG_b;
5039     };
5040 
5041     union
5042     {
5043         __IOM uint32_t CFDGTSTCTR;      /*!< (@ 0x0000130C) Global Test Control Register                               */
5044 
5045         struct
5046         {
5047             __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable                    */
5048             uint32_t               : 1;
5049             __IOM uint32_t RTME    : 1; /*!< [2..2] RAM Test Mode Enable                                               */
5050             uint32_t               : 29;
5051         } CFDGTSTCTR_b;
5052     };
5053     __IM uint32_t RESERVED33;
5054 
5055     union
5056     {
5057         __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x00001314) Global FD Configuration register                           */
5058 
5059         struct
5060         {
5061             __IOM uint32_t RPED   : 1; /*!< [0..0] RES bit Protocol exception disable                                 */
5062             uint32_t              : 7;
5063             __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration                                    */
5064             uint32_t              : 22;
5065         } CFDGFDCFG_b;
5066     };
5067     __IM uint32_t RESERVED34;
5068 
5069     union
5070     {
5071         __IOM uint32_t CFDGLOCKK;      /*!< (@ 0x0000131C) Global Lock Key Register                                   */
5072 
5073         struct
5074         {
5075             __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
5076             uint32_t           : 16;
5077         } CFDGLOCKK_b;
5078     };
5079 
5080     union
5081     {
5082         __IOM uint32_t CFDGLOTB;       /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register            */
5083 
5084         struct
5085         {
5086             __IOM uint32_t OTBFE  : 1; /*!< [0..0] OTB FIFO Enable                                                    */
5087             uint32_t              : 7;
5088             __IM uint32_t  OTBEMP : 1; /*!< [8..8] OTB FIFO Empty                                                     */
5089             __IM uint32_t  OTBFLL : 1; /*!< [9..9] OTB FIFO Full                                                      */
5090             __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost                                            */
5091             __IM uint32_t  OTBMC  : 5; /*!< [15..11] OTB FIFO Message Count                                           */
5092             uint32_t              : 16;
5093         } CFDGLOTB_b;
5094     };
5095 
5096     union
5097     {
5098         __IOM uint32_t CFDGAFLIGNENT;  /*!< (@ 0x00001324) Global AFL Ignore Entry Register                           */
5099 
5100         struct
5101         {
5102             __IOM uint32_t IRN : 9;    /*!< [8..0] Ignore Rule Number                                                 */
5103             uint32_t           : 7;
5104             __IOM uint32_t ICN : 3;    /*!< [18..16] Ignore Channel Number                                            */
5105             uint32_t           : 13;
5106         } CFDGAFLIGNENT_b;
5107     };
5108 
5109     union
5110     {
5111         __IOM uint32_t CFDGAFLIGNCTR;  /*!< (@ 0x00001328) Global AFL Ignore Control Register                         */
5112 
5113         struct
5114         {
5115             __IOM uint32_t IREN : 1;   /*!< [0..0] Ignore Rule Enable                                                 */
5116             uint32_t            : 7;
5117             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
5118             uint32_t            : 16;
5119         } CFDGAFLIGNCTR_b;
5120     };
5121     __IM uint32_t RESERVED35;
5122 
5123     union
5124     {
5125         __IOM uint32_t CFDCDTCT;        /*!< (@ 0x00001330) DMA Transfer Control Register                              */
5126 
5127         struct
5128         {
5129             __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0                                   */
5130             __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1                                   */
5131             __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2                                   */
5132             __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3                                   */
5133             __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4                                   */
5134             __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5                                   */
5135             __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6                                   */
5136             __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7                                   */
5137             __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0                 */
5138             __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1                 */
5139             uint32_t               : 22;
5140         } CFDCDTCT_b;
5141     };
5142 
5143     union
5144     {
5145         __IM uint32_t CFDCDTSTS;         /*!< (@ 0x00001334) DMA Transfer Status Register                               */
5146 
5147         struct
5148         {
5149             __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
5150             __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
5151             __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2                                  */
5152             __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3                                  */
5153             __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4                                  */
5154             __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5                                  */
5155             __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6                                  */
5156             __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7                                  */
5157             __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel
5158                                           *   0                                                                         */
5159             __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel
5160                                           *   1                                                                         */
5161             uint32_t : 22;
5162         } CFDCDTSTS_b;
5163     };
5164     __IM uint32_t RESERVED36[2];
5165 
5166     union
5167     {
5168         __IOM uint32_t CFDCDTTCT;        /*!< (@ 0x00001340) DMA TX Transfer Control Register                           */
5169 
5170         struct
5171         {
5172             __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0                      */
5173             __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1                      */
5174             uint32_t                : 6;
5175             __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0                      */
5176             __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1                      */
5177             uint32_t                : 6;
5178             __IOM uint32_t CFDMAE0  : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel
5179                                           *   0                                                                         */
5180             __IOM uint32_t CFDMAE1 : 1;  /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel
5181                                           *   1                                                                         */
5182             uint32_t : 14;
5183         } CFDCDTTCT_b;
5184     };
5185 
5186     union
5187     {
5188         __IOM uint32_t CFDCDTTSTS;        /*!< (@ 0x00001344) DMA TX Transfer Status Register                            */
5189 
5190         struct
5191         {
5192             __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0                       */
5193             __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1                       */
5194             uint32_t                 : 6;
5195             __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0                       */
5196             __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1                       */
5197             uint32_t                 : 6;
5198             __IM uint32_t CFDMASTS0  : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel
5199                                            *   0                                                                         */
5200             __IM uint32_t CFDMASTS1 : 1;  /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel
5201                                            *   1                                                                         */
5202             uint32_t : 14;
5203         } CFDCDTTSTS_b;
5204     };
5205     __IM uint32_t RESERVED37[2];
5206 
5207     union
5208     {
5209         __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register                        */
5210 
5211         struct
5212         {
5213             __IM uint32_t QFIF    : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n                                  */
5214             uint32_t              : 5;
5215             __IM uint32_t QOFRIF  : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n                         */
5216             uint32_t              : 5;
5217             __IM uint32_t CFRIF   : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n                          */
5218             uint32_t              : 5;
5219             __IM uint32_t CFRFIF  : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n              */
5220             uint32_t              : 1;
5221             __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n                */
5222             uint32_t              : 1;
5223         } CFDGRINTSTS_b[2];
5224     };
5225     __IM uint32_t RESERVED38[10];
5226 
5227     union
5228     {
5229         __IOM uint32_t CFDGRSTC;       /*!< (@ 0x00001380) Global SW reset Register                                   */
5230 
5231         struct
5232         {
5233             __IOM uint32_t SRST : 1;   /*!< [0..0] SW reset                                                           */
5234             uint32_t            : 7;
5235             __OM uint32_t KEY   : 8;   /*!< [15..8] Key code                                                          */
5236             uint32_t            : 16;
5237         } CFDGRSTC_b;
5238     };
5239     __IM uint32_t              RESERVED39[31];
5240     __IOM R_CANFD_CFDC2_Type   CFDC2[2];    /*!< (@ 0x00001400) Channel Configuration Registers                            */
5241     __IM uint32_t              RESERVED40[240];
5242     __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers                    */
5243     __IM uint32_t              RESERVED41[448];
5244     __IOM R_CANFD_CFDRM_Type   CFDRM[32];   /*!< (@ 0x00002000) RX Message Buffer Access Registers                         */
5245     __IM uint32_t              RESERVED42[3072];
5246     __IOM R_CANFD_CFDRF_Type   CFDRF[8];    /*!< (@ 0x00006000) RX FIFO Access Registers                                   */
5247     __IOM R_CANFD_CFDCF_Type   CFDCF[6];    /*!< (@ 0x00006400) Common FIFO Access Registers                               */
5248     __IM uint32_t              RESERVED43[1600];
5249     __IOM R_CANFD_CFDTHL_Type  CFDTHL[2];   /*!< (@ 0x00008000) Channel TX History List                                    */
5250     __IM uint32_t              RESERVED44[252];
5251 
5252     union
5253     {
5254         __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00008400) RAM Test Page Access Registers                             */
5255 
5256         struct
5257         {
5258             __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
5259         } CFDRPGACC_b[64];
5260     };
5261     __IM uint32_t            RESERVED45[7872];
5262     __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers                         */
5263 } R_CANFD_Type;                          /*!< Size = 81920 (0x14000)                                                    */
5264 
5265 /* =========================================================================================================================== */
5266 /* ================                                           R_CRC                                           ================ */
5267 /* =========================================================================================================================== */
5268 
5269 /**
5270  * @brief Cyclic Redundancy Check (CRC) Calculator (R_CRC)
5271  */
5272 
5273 typedef struct                         /*!< (@ 0x40108000) R_CRC Structure                                            */
5274 {
5275     union
5276     {
5277         __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register0                                      */
5278 
5279         struct
5280         {
5281             __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
5282             uint8_t              : 3;
5283             __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
5284             __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
5285         } CRCCR0_b;
5286     };
5287 
5288     union
5289     {
5290         __IOM uint8_t CRCCR1;          /*!< (@ 0x00000001) CRC Control Register1                                      */
5291 
5292         struct
5293         {
5294             uint8_t              : 6;
5295             __IOM uint8_t CRCSWR : 1;  /*!< [6..6] Snoop-on-write/read switch bit                                     */
5296             __IOM uint8_t CRCSEN : 1;  /*!< [7..7] Snoop enable bit                                                   */
5297         } CRCCR1_b;
5298     };
5299     __IM uint16_t RESERVED;
5300 
5301     union
5302     {
5303         union
5304         {
5305             __IOM uint32_t CRCDIR;          /*!< (@ 0x00000004) CRC Data Input Register                                    */
5306 
5307             struct
5308             {
5309                 __IOM uint32_t CRCDIR : 32; /*!< [31..0] Calculation input Data (Case of CRC-32, CRC-32C )                 */
5310             } CRCDIR_b;
5311         };
5312 
5313         union
5314         {
5315             __IOM uint8_t CRCDIR_BY;         /*!< (@ 0x00000004) CRC Data Input Register (byte access)                      */
5316 
5317             struct
5318             {
5319                 __IOM uint8_t CRCDIR_BY : 8; /*!< [7..0] Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
5320                                               *   )                                                                         */
5321             } CRCDIR_BY_b;
5322         };
5323     };
5324 
5325     union
5326     {
5327         union
5328         {
5329             __IOM uint32_t CRCDOR;          /*!< (@ 0x00000008) CRC Data Output Register                                   */
5330 
5331             struct
5332             {
5333                 __IOM uint32_t CRCDOR : 32; /*!< [31..0] Calculation output Data (Case of CRC-32, CRC-32C )                */
5334             } CRCDOR_b;
5335         };
5336 
5337         union
5338         {
5339             __IOM uint16_t CRCDOR_HA;          /*!< (@ 0x00000008) CRC Data Output Register (halfword access)                 */
5340 
5341             struct
5342             {
5343                 __IOM uint16_t CRCDOR_HA : 16; /*!< [15..0] Calculation output Data (Case of CRC-16 or CRC-CCITT
5344                                                 *   )                                                                         */
5345             } CRCDOR_HA_b;
5346         };
5347 
5348         union
5349         {
5350             __IOM uint8_t CRCDOR_BY;         /*!< (@ 0x00000008) CRC Data Output Register(byte access)                      */
5351 
5352             struct
5353             {
5354                 __IOM uint8_t CRCDOR_BY : 8; /*!< [7..0] Calculation output Data (Case of CRC-8 )                           */
5355             } CRCDOR_BY_b;
5356         };
5357     };
5358 
5359     union
5360     {
5361         __IOM uint16_t CRCSAR;         /*!< (@ 0x0000000C) Snoop Address Register                                     */
5362 
5363         struct
5364         {
5365             __IOM uint16_t CRCSA : 14; /*!< [13..0] snoop address bitSet the I/O register address to snoop            */
5366             uint16_t             : 2;
5367         } CRCSAR_b;
5368     };
5369     __IM uint16_t RESERVED1;
5370 } R_CRC_Type;                          /*!< Size = 16 (0x10)                                                          */
5371 
5372 /* =========================================================================================================================== */
5373 /* ================                                          R_CTSU                                           ================ */
5374 /* =========================================================================================================================== */
5375 
5376 /**
5377  * @brief Capacitive Touch Sensing Unit (R_CTSU)
5378  */
5379 
5380 typedef struct                            /*!< (@ 0x400D0000) R_CTSU Structure                                           */
5381 {
5382     union
5383     {
5384         __IOM uint8_t CTSUCR0;            /*!< (@ 0x00000000) CTSU Control Register 0                                    */
5385 
5386         struct
5387         {
5388             __IOM uint8_t CTSUSTRT   : 1; /*!< [0..0] CTSU Measurement Operation Start                                   */
5389             __IOM uint8_t CTSUCAP    : 1; /*!< [1..1] CTSU Measurement Operation Start Trigger Select                    */
5390             __IOM uint8_t CTSUSNZ    : 1; /*!< [2..2] CTSU Wait State Power-Saving Enable                                */
5391             __IOM uint8_t CTSUIOC    : 1; /*!< [3..3] CTSU Transmit Pin Control                                          */
5392             __IOM uint8_t CTSUINIT   : 1; /*!< [4..4] CTSU Control Block Initialization                                  */
5393             uint8_t                  : 2;
5394             __IOM uint8_t CTSUTXVSEL : 1; /*!< [7..7] CTSU Transmission power supply selection                           */
5395         } CTSUCR0_b;
5396     };
5397 
5398     union
5399     {
5400         __IOM uint8_t CTSUCR1;            /*!< (@ 0x00000001) CTSU Control Register 1                                    */
5401 
5402         struct
5403         {
5404             __IOM uint8_t CTSUPON    : 1; /*!< [0..0] CTSU Power Supply Enable                                           */
5405             __IOM uint8_t CTSUCSW    : 1; /*!< [1..1] CTSU LPF Capacitance Charging Control                              */
5406             __IOM uint8_t CTSUATUNE0 : 1; /*!< [2..2] CTSU Power Supply Operating Mode Setting                           */
5407             __IOM uint8_t CTSUATUNE1 : 1; /*!< [3..3] CTSU Power Supply Capacity Adjustment                              */
5408             __IOM uint8_t CTSUCLK    : 2; /*!< [5..4] CTSU Operating Clock Select                                        */
5409             __IOM uint8_t CTSUMD     : 2; /*!< [7..6] CTSU Measurement Mode Select                                       */
5410         } CTSUCR1_b;
5411     };
5412 
5413     union
5414     {
5415         __IOM uint8_t CTSUSDPRS;           /*!< (@ 0x00000002) CTSU Synchronous Noise Reduction Setting Register          */
5416 
5417         struct
5418         {
5419             __IOM uint8_t CTSUPRRATIO : 4; /*!< [3..0] CTSU Measurement Time and Pulse Count AdjustmentRecommended
5420                                             *   setting: 3 (0011b)                                                        */
5421             __IOM uint8_t CTSUPRMODE : 2;  /*!< [5..4] CTSU Base Period and Pulse Count Setting                           */
5422             __IOM uint8_t CTSUSOFF   : 1;  /*!< [6..6] CTSU High-Pass Noise Reduction Function Off Setting                */
5423             uint8_t                  : 1;
5424         } CTSUSDPRS_b;
5425     };
5426 
5427     union
5428     {
5429         __IOM uint8_t CTSUSST;         /*!< (@ 0x00000003) CTSU Sensor Stabilization Wait Control Register            */
5430 
5431         struct
5432         {
5433             __IOM uint8_t CTSUSST : 8; /*!< [7..0] CTSU Sensor Stabilization Wait ControlNOTE: The value
5434                                         *   of these bits should be fixed to 00010000b.                               */
5435         } CTSUSST_b;
5436     };
5437 
5438     union
5439     {
5440         __IOM uint8_t CTSUMCH0;         /*!< (@ 0x00000004) CTSU Measurement Channel Register 0                        */
5441 
5442         struct
5443         {
5444             __IOM uint8_t CTSUMCH0 : 6; /*!< [5..0] CTSU Measurement Channel 0.Note1: Writing to these bits
5445                                          *   is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0]
5446                                          *   bits = 00b).Note2: If the value of CTSUMCH0 was set to
5447                                          *   b'111111 in mode other than self-capacitor single scan
5448                                          *   mode, the measurement is stopped.                                         */
5449             uint8_t : 2;
5450         } CTSUMCH0_b;
5451     };
5452 
5453     union
5454     {
5455         __IOM uint8_t CTSUMCH1;        /*!< (@ 0x00000005) CTSU Measurement Channel Register 1                        */
5456 
5457         struct
5458         {
5459             __IM uint8_t CTSUMCH1 : 6; /*!< [5..0] CTSU Measurement Channel 1Note1: If the value of CTSUMCH1
5460                                         *   was set to b'111111, the measurement is stopped.                          */
5461             uint8_t : 2;
5462         } CTSUMCH1_b;
5463     };
5464 
5465     union
5466     {
5467         __IOM uint8_t CTSUCHAC[5];     /*!< (@ 0x00000006) CTSU Channel Enable Control Register                       */
5468 
5469         struct
5470         {
5471             __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Enable Control                                        */
5472             __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Enable Control                                        */
5473             __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Enable Control                                        */
5474             __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Enable Control                                        */
5475             __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Enable Control                                        */
5476             __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Enable Control                                        */
5477             __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Enable Control                                        */
5478             __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Enable Control                                        */
5479         } CTSUCHAC_b[5];
5480     };
5481 
5482     union
5483     {
5484         __IOM uint8_t CTSUCHTRC[5];    /*!< (@ 0x0000000B) CTSU Channel Transmit/Receive Control Register             */
5485 
5486         struct
5487         {
5488             __IOM uint8_t TS0 : 1;     /*!< [0..0] CTSU Channel Transmit/Receive Control                              */
5489             __IOM uint8_t TS1 : 1;     /*!< [1..1] CTSU Channel Transmit/Receive Control                              */
5490             __IOM uint8_t TS2 : 1;     /*!< [2..2] CTSU Channel Transmit/Receive Control                              */
5491             __IOM uint8_t TS3 : 1;     /*!< [3..3] CTSU Channel Transmit/Receive Control                              */
5492             __IOM uint8_t TS4 : 1;     /*!< [4..4] CTSU Channel Transmit/Receive Control                              */
5493             __IOM uint8_t TS5 : 1;     /*!< [5..5] CTSU Channel Transmit/Receive Control                              */
5494             __IOM uint8_t TS6 : 1;     /*!< [6..6] CTSU Channel Transmit/Receive Control                              */
5495             __IOM uint8_t TS7 : 1;     /*!< [7..7] CTSU Channel Transmit/Receive Control                              */
5496         } CTSUCHTRC_b[5];
5497     };
5498 
5499     union
5500     {
5501         __IOM uint8_t CTSUDCLKC;         /*!< (@ 0x00000010) CTSU High-Pass Noise Reduction Control Register            */
5502 
5503         struct
5504         {
5505             __IOM uint8_t CTSUSSMOD : 2; /*!< [1..0] CTSU Diffusion Clock Mode SelectNOTE: This bit should
5506                                           *   be set to 00b.                                                            */
5507             uint8_t                 : 2;
5508             __IOM uint8_t CTSUSSCNT : 2; /*!< [5..4] CTSU Diffusion Clock Mode ControlNOTE: This bit should
5509                                           *   be set to 11b.                                                            */
5510             uint8_t : 2;
5511         } CTSUDCLKC_b;
5512     };
5513 
5514     union
5515     {
5516         __IOM uint8_t CTSUST;           /*!< (@ 0x00000011) CTSU Status Register                                       */
5517 
5518         struct
5519         {
5520             __IM uint8_t CTSUSTC   : 3; /*!< [2..0] CTSU Measurement Status Counter                                    */
5521             uint8_t                : 1;
5522             __IM uint8_t  CTSUDTSR : 1; /*!< [4..4] CTSU Data Transfer Status Flag                                     */
5523             __IOM uint8_t CTSUSOVF : 1; /*!< [5..5] CTSU Sensor Counter Overflow Flag                                  */
5524             __IOM uint8_t CTSUROVF : 1; /*!< [6..6] CTSU Reference Counter Overflow Flag                               */
5525             __IM uint8_t  CTSUPS   : 1; /*!< [7..7] CTSU Mutual Capacitance Status Flag                                */
5526         } CTSUST_b;
5527     };
5528 
5529     union
5530     {
5531         __IOM uint16_t CTSUSSC;        /*!< (@ 0x00000012) CTSU High-Pass Noise Reduction Spectrum Diffusion
5532                                         *                  Control Register                                           */
5533 
5534         struct
5535         {
5536             uint16_t                 : 8;
5537             __IOM uint16_t CTSUSSDIV : 4; /*!< [11..8] CTSU Spectrum Diffusion Frequency Division Setting                */
5538             uint16_t                 : 4;
5539         } CTSUSSC_b;
5540     };
5541 
5542     union
5543     {
5544         __IOM uint16_t CTSUSO0;          /*!< (@ 0x00000014) CTSU Sensor Offset Register 0                              */
5545 
5546         struct
5547         {
5548             __IOM uint16_t CTSUSO : 10;  /*!< [9..0] CTSU Sensor Offset AdjustmentCurrent offset amount is
5549                                           *   CTSUSO ( 0 to 1023 )                                                      */
5550             __IOM uint16_t CTSUSNUM : 6; /*!< [15..10] CTSU Measurement Count Setting                                   */
5551         } CTSUSO0_b;
5552     };
5553 
5554     union
5555     {
5556         __IOM uint16_t CTSUSO1;           /*!< (@ 0x00000016) CTSU Sensor Offset Register 1                              */
5557 
5558         struct
5559         {
5560             __IOM uint16_t CTSURICOA : 8; /*!< [7..0] CTSU Reference ICO Current AdjustmentCurrent offset amount
5561                                            *   is CTSUSO ( 0 to 255 )                                                    */
5562             __IOM uint16_t CTSUSDPA : 5;  /*!< [12..8] CTSU Base Clock SettingOperating clock divided by (
5563                                            *   CTSUSDPA + 1 ) x 2                                                        */
5564             __IOM uint16_t CTSUICOG : 2;  /*!< [14..13] CTSU ICO Gain Adjustment                                         */
5565             uint16_t                : 1;
5566         } CTSUSO1_b;
5567     };
5568 
5569     union
5570     {
5571         __IM uint16_t CTSUSC;          /*!< (@ 0x00000018) CTSU Sensor Counter                                        */
5572 
5573         struct
5574         {
5575             __IM uint16_t CTSUSC : 16; /*!< [15..0] CTSU Sensor CounterThese bits indicate the measurement
5576                                         *   result of the CTSU. These bits indicate FFFFh when an overflow
5577                                         *   occurs.                                                                   */
5578         } CTSUSC_b;
5579     };
5580 
5581     union
5582     {
5583         __IM uint16_t CTSURC;          /*!< (@ 0x0000001A) CTSU Reference Counter                                     */
5584 
5585         struct
5586         {
5587             __IM uint16_t CTSURC : 16; /*!< [15..0] CTSU Reference CounterThese bits indicate the measurement
5588                                         *   result of the reference ICO.These bits indicate FFFFh when
5589                                         *   an overflow occurs.                                                       */
5590         } CTSURC_b;
5591     };
5592 
5593     union
5594     {
5595         __IM uint16_t CTSUERRS;             /*!< (@ 0x0000001C) CTSU Error Status Register                                 */
5596 
5597         struct
5598         {
5599             __IOM uint16_t CTSUSPMD    : 2; /*!< [1..0] Calibration Mode                                                   */
5600             __IOM uint16_t CTSUTSOD    : 1; /*!< [2..2] TS Pin Fixed Output                                                */
5601             __IOM uint16_t CTSUDRV     : 1; /*!< [3..3] Calibration Setting 1                                              */
5602             uint16_t                   : 2;
5603             __IOM uint16_t CTSUCLKSEL1 : 1; /*!< [6..6] Calibration Setting 3                                              */
5604             __IOM uint16_t CTSUTSOC    : 1; /*!< [7..7] Calibration Setting 2                                              */
5605             uint16_t                   : 7;
5606             __IM uint16_t CTSUICOMP    : 1; /*!< [15..15] TSCAP Voltage Error Monitor                                      */
5607         } CTSUERRS_b;
5608     };
5609     __IM uint16_t RESERVED;
5610     __IOM uint8_t CTSUTRMR;                 /*!< (@ 0x00000020) CTSU Reference Current Calibration Register                */
5611     __IM uint8_t  RESERVED1;
5612     __IM uint16_t RESERVED2;
5613 } R_CTSU_Type;                              /*!< Size = 36 (0x24)                                                          */
5614 
5615 /* =========================================================================================================================== */
5616 /* ================                                           R_DAC                                           ================ */
5617 /* =========================================================================================================================== */
5618 
5619 /**
5620  * @brief D/A Converter (R_DAC)
5621  */
5622 
5623 typedef struct                         /*!< (@ 0x40171000) R_DAC Structure                                            */
5624 {
5625     union
5626     {
5627         __IOM uint16_t DADR[2];        /*!< (@ 0x00000000) D/A Data Register                                          */
5628 
5629         struct
5630         {
5631             __IOM uint16_t DADR : 16;  /*!< [15..0] D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
5632                                         *   4 bits are fixed to 0: right justified format. When DADPR.DPSEL
5633                                         *   = 1, the low-order 4 bits are fixed to 0: left justified
5634                                         *   format.                                                                   */
5635         } DADR_b[2];
5636     };
5637 
5638     union
5639     {
5640         __IOM uint8_t DACR;            /*!< (@ 0x00000004) D/A Control Register                                       */
5641 
5642         struct
5643         {
5644             uint8_t             : 5;
5645             __IOM uint8_t DAE   : 1;   /*!< [5..5] D/A Enable                                                         */
5646             __IOM uint8_t DAOE0 : 1;   /*!< [6..6] D/A Output Enable 0                                                */
5647             __IOM uint8_t DAOE1 : 1;   /*!< [7..7] D/A Output Enable 0                                                */
5648         } DACR_b;
5649     };
5650 
5651     union
5652     {
5653         __IOM uint8_t DADPR;           /*!< (@ 0x00000005) DADR0 Format Select Register                               */
5654 
5655         struct
5656         {
5657             uint8_t             : 7;
5658             __IOM uint8_t DPSEL : 1;   /*!< [7..7] DADRm Format Select                                                */
5659         } DADPR_b;
5660     };
5661 
5662     union
5663     {
5664         __IOM uint8_t DAADSCR;         /*!< (@ 0x00000006) D/A-A/D Synchronous Start Control Register                 */
5665 
5666         struct
5667         {
5668             uint8_t              : 7;
5669             __IOM uint8_t DAADST : 1;  /*!< [7..7] D/A-A/D Synchronous Conversion                                     */
5670         } DAADSCR_b;
5671     };
5672 
5673     union
5674     {
5675         __IOM uint8_t DAVREFCR;        /*!< (@ 0x00000007) D/A VREF Control Register                                  */
5676 
5677         struct
5678         {
5679             __IOM uint8_t REF : 3;     /*!< [2..0] D/A Reference Voltage Select                                       */
5680             uint8_t           : 5;
5681         } DAVREFCR_b;
5682     };
5683 
5684     union
5685     {
5686         __IOM uint8_t DAAMPCR;         /*!< (@ 0x00000008) D/A Output Amplifier Control Register                      */
5687 
5688         struct
5689         {
5690             uint8_t              : 6;
5691             __IOM uint8_t DAAMP0 : 1;  /*!< [6..6] Amplifier Control                                                  */
5692             __IOM uint8_t DAAMP1 : 1;  /*!< [7..7] Amplifier Control                                                  */
5693         } DAAMPCR_b;
5694     };
5695 
5696     union
5697     {
5698         __IOM uint8_t DAPC;            /*!< (@ 0x00000009) D/A Switch Charge Pump Control Register                    */
5699 
5700         struct
5701         {
5702             __IOM uint8_t PUMPEN : 1;  /*!< [0..0] Charge Pump Enable                                                 */
5703             uint8_t              : 7;
5704         } DAPC_b;
5705     };
5706     __IM uint16_t RESERVED[9];
5707 
5708     union
5709     {
5710         __IOM uint8_t DAASWCR;         /*!< (@ 0x0000001C) D/A Amplifier Stabilization Wait Control Register          */
5711 
5712         struct
5713         {
5714             uint8_t              : 6;
5715             __IOM uint8_t DAASW0 : 1;  /*!< [6..6] Set the DAASW0 bit to 1 in the initialization procedure
5716                                         *   to wait for stabilization of the output amplifier of D/A
5717                                         *   channel 0. When DAASW0 is set to 1, D/A conversion operates,
5718                                         *   but the conversion result D/A is not output from channel
5719                                         *   0. When the DAASW0 bit is 0, the stabilization wait time
5720                                         *   stops, and the D/A conversion result of channel 0 is output
5721                                         *   through the output amplifier.                                             */
5722             __IOM uint8_t DAASW1 : 1;  /*!< [7..7] Set the DAASW1 bit to 1 in the initialization procedure
5723                                         *   to wait for stabilization of the output amplifier of D/A
5724                                         *   channel 1. When DAASW1 is set to 1, D/A conversion operates,
5725                                         *   but the conversion result D/A is not output from channel
5726                                         *   1. When the DAASW1 bit is 0, the stabilization wait time
5727                                         *   stops, and the D/A conversion result of channel 1 is output
5728                                         *   through the output amplifier.                                             */
5729         } DAASWCR_b;
5730     };
5731     __IM uint8_t  RESERVED1;
5732     __IM uint16_t RESERVED2[2129];
5733 
5734     union
5735     {
5736         __IOM uint8_t DAADUSR;          /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register                   */
5737 
5738         struct
5739         {
5740             __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for
5741                                          *   D/A and A/D synchronous conversions. Set bit [0] to 1 to
5742                                          *   select unit 0 as the target synchronous unit for the MCU.
5743                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
5744                                          *   conversions, select the target unit in this register in
5745                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
5746                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
5747                                          *   is set to 0.                                                              */
5748             __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for
5749                                          *   D/A and A/D synchronous conversions. Set bit [1] to 1 to
5750                                          *   select unit 1 as the target synchronous unit for the MCU.
5751                                          *   When setting the DAADSCR.DAADST bit to 1 for synchronous
5752                                          *   conversions, select the target unit in this register in
5753                                          *   advance. Only set the DAADUSR register while the ADCSR.ADST
5754                                          *   bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit
5755                                          *   is set to 0.                                                              */
5756             uint8_t : 6;
5757         } DAADUSR_b;
5758     };
5759     __IM uint8_t  RESERVED3;
5760     __IM uint16_t RESERVED4;
5761 } R_DAC_Type;                          /*!< Size = 4292 (0x10c4)                                                      */
5762 
5763 /* =========================================================================================================================== */
5764 /* ================                                          R_DEBUG                                          ================ */
5765 /* =========================================================================================================================== */
5766 
5767 /**
5768  * @brief Debug Function (R_DEBUG)
5769  */
5770 
5771 typedef struct                         /*!< (@ 0x4001B000) R_DEBUG Structure                                          */
5772 {
5773     union
5774     {
5775         __IM uint32_t DBGSTR;          /*!< (@ 0x00000000) Debug Status Register                                      */
5776 
5777         struct
5778         {
5779             uint32_t                   : 28;
5780             __IM uint32_t CDBGPWRUPREQ : 1; /*!< [28..28] Debug power-up request                                           */
5781             __IM uint32_t CDBGPWRUPACK : 1; /*!< [29..29] Debug power-up acknowledge                                       */
5782             uint32_t                   : 2;
5783         } DBGSTR_b;
5784     };
5785     __IM uint32_t RESERVED[3];
5786 
5787     union
5788     {
5789         __IOM uint32_t DBGSTOPCR;             /*!< (@ 0x00000010) Debug Stop Control Register                                */
5790 
5791         struct
5792         {
5793             __IOM uint32_t DBGSTOP_IWDT  : 1; /*!< [0..0] Mask bit for IWDT reset/interrupt                                  */
5794             __IOM uint32_t DBGSTOP_WDT   : 1; /*!< [1..1] Mask bit for WDT reset/interrupt                                   */
5795             uint32_t                     : 12;
5796             __IOM uint32_t DBGSTOP_TIM   : 1; /*!< [14..14] Mask bit for RTC, TAU reset/interrupt                            */
5797             __IOM uint32_t DBGSTOP_SIR   : 1; /*!< [15..15] Mask bit for SAU, IICA, PORT_IRQ0-5 reset/interrupt              */
5798             __IOM uint32_t DBGSTOP_LVD0  : 1; /*!< [16..16] Mask bit for LVD reset/interupt                                  */
5799             __IOM uint32_t DBGSTOP_LVD1  : 1; /*!< [17..17] Mask bit for LVD reset/interupt                                  */
5800             __IOM uint32_t DBGSTOP_LVD2  : 1; /*!< [18..18] Mask bit for LVD reset/interupt                                  */
5801             uint32_t                     : 5;
5802             __IOM uint32_t DBGSTOP_RPER  : 1; /*!< [24..24] Mask bit for SRAM parity error                                   */
5803             __IOM uint32_t DBGSTOP_RECCR : 1; /*!< [25..25] Mask bit for SRAM ECC error                                      */
5804             uint32_t                     : 5;
5805             __IOM uint32_t DBGSTOP_CPER  : 1; /*!< [31..31] Mask bit for Cache SRAM parity error reset/interrupt             */
5806         } DBGSTOPCR_b;
5807     };
5808     __IM uint32_t RESERVED1[123];
5809 
5810     union
5811     {
5812         __IOM uint32_t FSBLSTAT;       /*!< (@ 0x00000200) First Stage Boot Loader Status Register                    */
5813 
5814         struct
5815         {
5816             __IOM uint32_t CS     : 1; /*!< [0..0] FSBL completion status.                                            */
5817             __IOM uint32_t RS     : 1; /*!< [1..1] FSBL result status.                                                */
5818             uint32_t              : 6;
5819             __IM uint32_t FSBLCLK : 3; /*!< [10..8] System clock frequency selection during FSBL execution            */
5820             uint32_t              : 21;
5821         } FSBLSTAT_b;
5822     };
5823 } R_DEBUG_Type;                        /*!< Size = 516 (0x204)                                                        */
5824 
5825 /* =========================================================================================================================== */
5826 /* ================                                           R_DMA                                           ================ */
5827 /* =========================================================================================================================== */
5828 
5829 /**
5830  * @brief DMA Controller Common (R_DMA)
5831  */
5832 
5833 typedef struct                         /*!< (@ 0x40005200) R_DMA Structure                                            */
5834 {
5835     union
5836     {
5837         __IOM uint8_t DMAST;           /*!< (@ 0x00000000) DMAC Module Activation Register                            */
5838 
5839         struct
5840         {
5841             __IOM uint8_t DMST : 1;    /*!< [0..0] DMAC Operation Enable                                              */
5842             uint8_t            : 7;
5843         } DMAST_b;
5844     };
5845     __IM uint8_t  RESERVED;
5846     __IM uint16_t RESERVED1;
5847     __IM uint32_t RESERVED2[15];
5848 
5849     union
5850     {
5851         __IOM uint32_t DMECHR;          /*!< (@ 0x00000040) DMAC Error Channel Register                                */
5852 
5853         struct
5854         {
5855             __IM uint32_t DMECH    : 3; /*!< [2..0] DMAC Error channel                                                 */
5856             uint32_t               : 5;
5857             __IM uint32_t DMECHSAM : 1; /*!< [8..8] DMAC Error channel Security Attribution Monitor                    */
5858             uint32_t               : 7;
5859             __IOM uint32_t DMESTA  : 1; /*!< [16..16] DMAC Error Status                                                */
5860             uint32_t               : 15;
5861         } DMECHR_b;
5862     };
5863     __IM uint32_t RESERVED3[15];
5864 
5865     union
5866     {
5867         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000080) DMAC Event Link Setting Register                           */
5868 
5869         struct
5870         {
5871             __IOM uint32_t DELS : 9;   /*!< [8..0] DMAC Event Link Select                                             */
5872             uint32_t            : 7;
5873             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
5874                                         *   IR flag is prohibited.                                                    */
5875             uint32_t : 15;
5876         } DELSR_b[8];
5877     };
5878 } R_DMA_Type;                          /*!< Size = 160 (0xa0)                                                         */
5879 
5880 /* =========================================================================================================================== */
5881 /* ================                                          R_DMAC0                                          ================ */
5882 /* =========================================================================================================================== */
5883 
5884 /**
5885  * @brief DMA Controller (R_DMAC0)
5886  */
5887 
5888 typedef struct                         /*!< (@ 0x40005000) R_DMAC0 Structure                                          */
5889 {
5890     union
5891     {
5892         __IOM uint32_t DMSAR;          /*!< (@ 0x00000000) DMA Source Address Register                                */
5893 
5894         struct
5895         {
5896             __IOM uint32_t DMSAR : 32; /*!< [31..0] Specifies the transfer source start address.                      */
5897         } DMSAR_b;
5898     };
5899 
5900     union
5901     {
5902         __IOM uint32_t DMDAR;          /*!< (@ 0x00000004) DMA Destination Address Register                           */
5903 
5904         struct
5905         {
5906             __IOM uint32_t DMDAR : 32; /*!< [31..0] Specifies the transfer destination start address.                 */
5907         } DMDAR_b;
5908     };
5909 
5910     union
5911     {
5912         __IOM uint32_t DMCRA;           /*!< (@ 0x00000008) DMA Transfer Count Register                                */
5913 
5914         struct
5915         {
5916             __IOM uint32_t DMCRAL : 16; /*!< [15..0] Lower bits of transfer count                                      */
5917             __IOM uint32_t DMCRAH : 10; /*!< [25..16] Upper bits of transfer count                                     */
5918             uint32_t              : 6;
5919         } DMCRA_b;
5920     };
5921 
5922     union
5923     {
5924         __IOM uint32_t DMCRB;           /*!< (@ 0x0000000C) DMA Block Transfer Count Register                          */
5925 
5926         struct
5927         {
5928             __IOM uint32_t DMCRBL : 16; /*!< [15..0] Functions as a number of block, repeat or repeat-block
5929                                          *   transfer counter.                                                         */
5930             __IOM uint32_t DMCRBH : 16; /*!< [31..16] Specifies the number of block transfer operations or
5931                                          *   repeat transfer operations.                                               */
5932         } DMCRB_b;
5933     };
5934 
5935     union
5936     {
5937         __IOM uint16_t DMTMD;          /*!< (@ 0x00000010) DMA Transfer Mode Register                                 */
5938 
5939         struct
5940         {
5941             __IOM uint16_t DCTG : 2;   /*!< [1..0] Transfer Request Source Select                                     */
5942             uint16_t            : 6;
5943             __IOM uint16_t SZ   : 2;   /*!< [9..8] Transfer Data Size Select                                          */
5944             __IOM uint16_t TKP  : 1;   /*!< [10..10] Transfer Keeping                                                 */
5945             uint16_t            : 1;
5946             __IOM uint16_t DTS  : 2;   /*!< [13..12] Repeat Area Select                                               */
5947             __IOM uint16_t MD   : 2;   /*!< [15..14] Transfer Mode Select                                             */
5948         } DMTMD_b;
5949     };
5950     __IM uint8_t RESERVED;
5951 
5952     union
5953     {
5954         __IOM uint8_t DMINT;           /*!< (@ 0x00000013) DMA Interrupt Setting Register                             */
5955 
5956         struct
5957         {
5958             __IOM uint8_t DARIE : 1;   /*!< [0..0] Destination Address Extended Repeat Area Overflow Interrupt
5959                                         *   Enable                                                                    */
5960             __IOM uint8_t SARIE : 1;   /*!< [1..1] Source Address Extended Repeat Area Overflow Interrupt
5961                                         *   Enable                                                                    */
5962             __IOM uint8_t RPTIE : 1;   /*!< [2..2] Repeat Size End Interrupt Enable                                   */
5963             __IOM uint8_t ESIE  : 1;   /*!< [3..3] Transfer Escape End Interrupt Enable                               */
5964             __IOM uint8_t DTIE  : 1;   /*!< [4..4] Transfer End Interrupt Enable                                      */
5965             uint8_t             : 3;
5966         } DMINT_b;
5967     };
5968 
5969     union
5970     {
5971         __IOM uint16_t DMAMD;          /*!< (@ 0x00000014) DMA Address Mode Register                                  */
5972 
5973         struct
5974         {
5975             __IOM uint16_t DARA : 5;   /*!< [4..0] Destination Address Extended Repeat Area Specifies the
5976                                         *   extended repeat area on the destination address. For details
5977                                         *   on the settings.                                                          */
5978             __IOM uint16_t DADR : 1;   /*!< [5..5] Destination Address Update Select After Reload                     */
5979             __IOM uint16_t DM   : 2;   /*!< [7..6] Destination Address Update Mode                                    */
5980             __IOM uint16_t SARA : 5;   /*!< [12..8] Source Address Extended Repeat Area Specifies the extended
5981                                         *   repeat area on the source address. For details on the settings.           */
5982             __IOM uint16_t SADR : 1;   /*!< [13..13] Source Address Update Select After Reload                        */
5983             __IOM uint16_t SM   : 2;   /*!< [15..14] Source Address Update Mode                                       */
5984         } DMAMD_b;
5985     };
5986     __IM uint16_t RESERVED1;
5987 
5988     union
5989     {
5990         __IOM uint32_t DMOFR;          /*!< (@ 0x00000018) DMA Offset Register                                        */
5991 
5992         struct
5993         {
5994             __IOM uint32_t DMOFR : 32; /*!< [31..0] Specifies the offset when offset addition is selected
5995                                         *   as the address update mode for transfer source or destination.            */
5996         } DMOFR_b;
5997     };
5998 
5999     union
6000     {
6001         __IOM uint8_t DMCNT;           /*!< (@ 0x0000001C) DMA Transfer Enable Register                               */
6002 
6003         struct
6004         {
6005             __IOM uint8_t DTE : 1;     /*!< [0..0] DMA Transfer Enable                                                */
6006             uint8_t           : 7;
6007         } DMCNT_b;
6008     };
6009 
6010     union
6011     {
6012         __IOM uint8_t DMREQ;           /*!< (@ 0x0000001D) DMA Software Start Register                                */
6013 
6014         struct
6015         {
6016             __IOM uint8_t SWREQ : 1;   /*!< [0..0] DMA Software Start                                                 */
6017             uint8_t             : 3;
6018             __IOM uint8_t CLRS  : 1;   /*!< [4..4] DMA Software Start Bit Auto Clear Select                           */
6019             uint8_t             : 3;
6020         } DMREQ_b;
6021     };
6022 
6023     union
6024     {
6025         __IOM uint8_t DMSTS;            /*!< (@ 0x0000001E) DMA Status Register                                        */
6026 
6027         struct
6028         {
6029             __IOM uint8_t ESIF : 1;     /*!< [0..0] Transfer Escape End Interrupt Flag                                 */
6030             uint8_t            : 3;
6031             __IOM uint8_t DTIF : 1;     /*!< [4..4] Transfer End Interrupt Flag                                        */
6032             uint8_t            : 2;
6033             __IM uint8_t ACT   : 1;     /*!< [7..7] DMA Active Flag                                                    */
6034         } DMSTS_b;
6035     };
6036     __IM uint8_t   RESERVED2;
6037     __IOM uint32_t DMSRR;               /*!< (@ 0x00000020) DMA Source Reload Address Register                         */
6038     __IOM uint32_t DMDRR;               /*!< (@ 0x00000024) DMA Destination Reload Address Register                    */
6039 
6040     union
6041     {
6042         __IOM uint32_t DMSBS;           /*!< (@ 0x00000028) DMA Source Buffer Size Register                            */
6043 
6044         struct
6045         {
6046             __IOM uint32_t DMSBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
6047                                          *   mode                                                                      */
6048             __IOM uint32_t DMSBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
6049                                          *   mode                                                                      */
6050         } DMSBS_b;
6051     };
6052 
6053     union
6054     {
6055         __IOM uint32_t DMDBS;           /*!< (@ 0x0000002C) DMA Destination Buffer Size Register                       */
6056 
6057         struct
6058         {
6059             __IOM uint32_t DMDBSL : 16; /*!< [15..0] Functions as data transfer counter in repeat-block transfer
6060                                          *   mode                                                                      */
6061             __IOM uint32_t DMDBSH : 16; /*!< [31..16] Specifies the repeat-area size in repeat-block transfer
6062                                          *   mode                                                                      */
6063         } DMDBS_b;
6064     };
6065 
6066     union
6067     {
6068         __IOM uint8_t DMBWR;           /*!< (@ 0x00000030) DMA Bufferable Write Enable Register                       */
6069 
6070         struct
6071         {
6072             __IOM uint8_t BWE : 1;     /*!< [0..0] Bufferable Write Enable                                            */
6073             uint8_t           : 7;
6074         } DMBWR_b;
6075     };
6076     __IM uint8_t  RESERVED3;
6077     __IM uint16_t RESERVED4;
6078 } R_DMAC0_Type;                        /*!< Size = 52 (0x34)                                                          */
6079 
6080 /* =========================================================================================================================== */
6081 /* ================                                           R_DOC                                           ================ */
6082 /* =========================================================================================================================== */
6083 
6084 /**
6085  * @brief Data Operation Circuit (R_DOC)
6086  */
6087 
6088 typedef struct                         /*!< (@ 0x40109000) R_DOC Structure                                            */
6089 {
6090     union
6091     {
6092         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
6093 
6094         struct
6095         {
6096             __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
6097             __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
6098             uint8_t               : 2;
6099             __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
6100             __IOM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Clear                                                        */
6101             uint8_t               : 1;
6102         } DOCR_b;
6103     };
6104     __IM uint8_t RESERVED;
6105 
6106     union
6107     {
6108         __IOM uint16_t DODIR;          /*!< (@ 0x00000002) DOC Data Input Register                                    */
6109 
6110         struct
6111         {
6112             __IOM uint16_t DODIR : 16; /*!< [15..0] 16-bit read-write register in which 16-bit data for
6113                                         *   use in the operations are stored.                                         */
6114         } DODIR_b;
6115     };
6116 
6117     union
6118     {
6119         __IOM uint16_t DODSR;          /*!< (@ 0x00000004) DOC Data Setting Register                                  */
6120 
6121         struct
6122         {
6123             __IOM uint16_t DODSR : 16; /*!< [15..0] This register stores 16-bit data for use as a reference
6124                                         *   in data comparison mode. This register also stores the
6125                                         *   results of operations in data addition and data subtraction
6126                                         *   modes.                                                                    */
6127         } DODSR_b;
6128     };
6129 } R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
6130 
6131 /* =========================================================================================================================== */
6132 /* ================                                           R_DTC                                           ================ */
6133 /* =========================================================================================================================== */
6134 
6135 /**
6136  * @brief Data Transfer Controller (R_DTC)
6137  */
6138 
6139 typedef struct                         /*!< (@ 0x40005400) R_DTC Structure                                            */
6140 {
6141     union
6142     {
6143         __IOM uint8_t DTCCR;           /*!< (@ 0x00000000) DTC Control Register                                       */
6144 
6145         struct
6146         {
6147             uint8_t           : 4;
6148             __IOM uint8_t RRS : 1;     /*!< [4..4] DTC Transfer Information Read Skip Enable.                         */
6149             uint8_t           : 3;
6150         } DTCCR_b;
6151     };
6152     __IM uint8_t  RESERVED;
6153     __IM uint16_t RESERVED1;
6154 
6155     union
6156     {
6157         __IOM uint32_t DTCVBR;          /*!< (@ 0x00000004) DTC Vector Base Register                                   */
6158 
6159         struct
6160         {
6161             __IOM uint32_t DTCVBR : 32; /*!< [31..0] DTC Vector Base Address.Note: A value cannot be set
6162                                          *   in the lower-order 10 bits. These bits are fixed to 0.                    */
6163         } DTCVBR_b;
6164     };
6165     __IM uint32_t RESERVED2;
6166 
6167     union
6168     {
6169         __IOM uint8_t DTCST;           /*!< (@ 0x0000000C) DTC Module Start Register                                  */
6170 
6171         struct
6172         {
6173             __IOM uint8_t DTCST : 1;   /*!< [0..0] DTC Module Start                                                   */
6174             uint8_t             : 7;
6175         } DTCST_b;
6176     };
6177     __IM uint8_t RESERVED3;
6178 
6179     union
6180     {
6181         __IM uint16_t DTCSTS;          /*!< (@ 0x0000000E) DTC Status Register                                        */
6182 
6183         struct
6184         {
6185             __IM uint16_t VECN : 8;    /*!< [7..0] DTC-Activating Vector Number MonitoringThese bits indicate
6186                                         *   the vector number for the activating source when DTC transfer
6187                                         *   is in progress.The value is only valid if DTC transfer
6188                                         *   is in progress (the value of the ACT flag is 1)                           */
6189             uint16_t          : 7;
6190             __IM uint16_t ACT : 1;     /*!< [15..15] DTC Active Flag                                                  */
6191         } DTCSTS_b;
6192     };
6193 
6194     union
6195     {
6196         __IOM uint8_t DTCCR_SEC;       /*!< (@ 0x00000010) DTC Control Register for secure Region                     */
6197 
6198         struct
6199         {
6200             uint8_t            : 4;
6201             __IOM uint8_t RRSS : 1;    /*!< [4..4] DTC Transfer Information Read Skip Enable for Secure               */
6202             uint8_t            : 3;
6203         } DTCCR_SEC_b;
6204     };
6205     __IM uint8_t   RESERVED4;
6206     __IM uint16_t  RESERVED5;
6207     __IOM uint32_t DTCVBR_SEC;         /*!< (@ 0x00000014) DTC Vector Base Register for secure Region                 */
6208     __IM uint32_t  RESERVED6[2];
6209 
6210     union
6211     {
6212         __IOM uint32_t DTEVR;          /*!< (@ 0x00000020) DTC Error Vector Register                                  */
6213 
6214         struct
6215         {
6216             __IM uint32_t DTEV    : 8; /*!< [7..0] DTC Error Vector Number                                            */
6217             __IM uint32_t DTEVSAM : 1; /*!< [8..8] DTC Error Vector Number SA Monitor                                 */
6218             uint32_t              : 7;
6219             __IOM uint32_t DTESTA : 1; /*!< [16..16] DTC Error Status Flag                                            */
6220             uint32_t              : 15;
6221         } DTEVR_b;
6222     };
6223 } R_DTC_Type;                          /*!< Size = 36 (0x24)                                                          */
6224 
6225 /* =========================================================================================================================== */
6226 /* ================                                           R_ELC                                           ================ */
6227 /* =========================================================================================================================== */
6228 
6229 /**
6230  * @brief Event Link Controller (R_ELC)
6231  */
6232 
6233 typedef struct                         /*!< (@ 0x40082000) R_ELC Structure                                            */
6234 {
6235     union
6236     {
6237         __IOM uint8_t ELCR;            /*!< (@ 0x00000000) Event Link Controller Register                             */
6238 
6239         struct
6240         {
6241             uint8_t             : 7;
6242             __IOM uint8_t ELCON : 1;   /*!< [7..7] All Event Link Enable                                              */
6243         } ELCR_b;
6244     };
6245     __IM uint8_t            RESERVED;
6246     __IOM R_ELC_ELSEGR_Type ELSEGR[2]; /*!< (@ 0x00000002) Event Link Software Event Generation Register              */
6247     __IM uint16_t           RESERVED1[5];
6248     __IOM R_ELC_ELSR_Type   ELSR[23];  /*!< (@ 0x00000010) Event Link Setting Register [0..22]                        */
6249     __IM uint16_t           RESERVED2[4];
6250 
6251     union
6252     {
6253         __IOM uint16_t ELCSARA;         /*!< (@ 0x00000074) Event Link Controller Security Attribution Register
6254                                          *                  A                                                          */
6255 
6256         struct
6257         {
6258             __IOM uint16_t ELCR    : 1; /*!< [0..0] Event Link Controller RegisterSecurity Attribution                 */
6259             __IOM uint16_t ELSEGR0 : 1; /*!< [1..1] Event Link Software Event Generation Register 0 Security
6260                                          *   Attribution                                                               */
6261             __IOM uint16_t ELSEGR1 : 1; /*!< [2..2] Event Link Software Event Generation Register 1Security
6262                                          *   Attribution                                                               */
6263             uint16_t : 13;
6264         } ELCSARA_b;
6265     };
6266     __IM uint16_t RESERVED3;
6267 
6268     union
6269     {
6270         __IOM uint16_t ELCSARB;        /*!< (@ 0x00000078) Event Link Controller Security Attribution Register
6271                                         *                  B                                                          */
6272 
6273         struct
6274         {
6275             __IOM uint16_t ELSR0  : 1; /*!< [0..0] Event Link Setting Register 0Security Attribution                  */
6276             __IOM uint16_t ELSR1  : 1; /*!< [1..1] Event Link Setting Register 1Security Attribution                  */
6277             __IOM uint16_t ELSR2  : 1; /*!< [2..2] Event Link Setting Register 2Security Attribution                  */
6278             __IOM uint16_t ELSR3  : 1; /*!< [3..3] Event Link Setting Register 3Security Attribution                  */
6279             __IOM uint16_t ELSR4  : 1; /*!< [4..4] Event Link Setting Register 4Security Attribution                  */
6280             __IOM uint16_t ELSR5  : 1; /*!< [5..5] Event Link Setting Register 5Security Attribution                  */
6281             __IOM uint16_t ELSR6  : 1; /*!< [6..6] Event Link Setting Register 6Security Attribution                  */
6282             __IOM uint16_t ELSR7  : 1; /*!< [7..7] Event Link Setting Register 7Security Attribution                  */
6283             __IOM uint16_t ELSR8  : 1; /*!< [8..8] Event Link Setting Register 8Security Attribution                  */
6284             __IOM uint16_t ELSR9  : 1; /*!< [9..9] Event Link Setting Register 9Security Attribution                  */
6285             __IOM uint16_t ELSR10 : 1; /*!< [10..10] Event Link Setting Register 10Security Attribution               */
6286             __IOM uint16_t ELSR11 : 1; /*!< [11..11] Event Link Setting Register 11Security Attribution               */
6287             __IOM uint16_t ELSR12 : 1; /*!< [12..12] Event Link Setting Register 12Security Attribution               */
6288             __IOM uint16_t ELSR13 : 1; /*!< [13..13] Event Link Setting Register 13Security Attribution               */
6289             __IOM uint16_t ELSR14 : 1; /*!< [14..14] Event Link Setting Register 14Security Attribution               */
6290             __IOM uint16_t ELSR15 : 1; /*!< [15..15] Event Link Setting Register 15Security Attribution               */
6291         } ELCSARB_b;
6292     };
6293     __IM uint16_t RESERVED4;
6294 
6295     union
6296     {
6297         __IOM uint16_t ELCSARC;        /*!< (@ 0x0000007C) Event Link Controller Security Attribution Register
6298                                         *                  C                                                          */
6299 
6300         struct
6301         {
6302             __IOM uint16_t ELSR16 : 1; /*!< [0..0] Event Link Setting Register 16Security Attribution                 */
6303             __IOM uint16_t ELSR17 : 1; /*!< [1..1] Event Link Setting Register 17Security Attribution                 */
6304             __IOM uint16_t ELSR18 : 1; /*!< [2..2] Event Link Setting Register 18Security Attribution                 */
6305             uint16_t              : 13;
6306         } ELCSARC_b;
6307     };
6308 } R_ELC_Type;                          /*!< Size = 126 (0x7e)                                                         */
6309 
6310 /* =========================================================================================================================== */
6311 /* ================                                         R_ETHERC0                                         ================ */
6312 /* =========================================================================================================================== */
6313 
6314 /**
6315  * @brief Ethernet MAC Controller (R_ETHERC0)
6316  */
6317 
6318 typedef struct                         /*!< (@ 0x40114100) R_ETHERC0 Structure                                        */
6319 {
6320     union
6321     {
6322         __IOM uint32_t ECMR;           /*!< (@ 0x00000000) ETHERC Mode Register                                       */
6323 
6324         struct
6325         {
6326             __IOM uint32_t PRM   : 1;  /*!< [0..0] Promiscuous Mode                                                   */
6327             __IOM uint32_t DM    : 1;  /*!< [1..1] Duplex Mode                                                        */
6328             __IOM uint32_t RTM   : 1;  /*!< [2..2] Bit Rate                                                           */
6329             __IOM uint32_t ILB   : 1;  /*!< [3..3] Internal Loopback Mode                                             */
6330             uint32_t             : 1;
6331             __IOM uint32_t TE    : 1;  /*!< [5..5] Transmission Enable                                                */
6332             __IOM uint32_t RE    : 1;  /*!< [6..6] Reception Enable                                                   */
6333             uint32_t             : 2;
6334             __IOM uint32_t MPDE  : 1;  /*!< [9..9] Magic Packet Detection Enable                                      */
6335             uint32_t             : 2;
6336             __IOM uint32_t PRCEF : 1;  /*!< [12..12] CRC Error Frame Receive Mode                                     */
6337             uint32_t             : 3;
6338             __IOM uint32_t TXF   : 1;  /*!< [16..16] Transmit Flow Control Operating Mode                             */
6339             __IOM uint32_t RXF   : 1;  /*!< [17..17] Receive Flow Control Operating Mode                              */
6340             __IOM uint32_t PFR   : 1;  /*!< [18..18] PAUSE Frame Receive Mode                                         */
6341             __IOM uint32_t ZPF   : 1;  /*!< [19..19] 0 Time PAUSE Frame Enable                                        */
6342             __IOM uint32_t TPC   : 1;  /*!< [20..20] PAUSE Frame Transmit                                             */
6343             uint32_t             : 11;
6344         } ECMR_b;
6345     };
6346     __IM uint32_t RESERVED;
6347 
6348     union
6349     {
6350         __IOM uint32_t RFLR;           /*!< (@ 0x00000008) Receive Frame Maximum Length Register                      */
6351 
6352         struct
6353         {
6354             __IOM uint32_t RFL : 12;   /*!< [11..0] Receive Frame Maximum LengthThe set value becomes the
6355                                         *   maximum frame length. The minimum value that can be set
6356                                         *   is 1,518 bytes, and the maximum value that can be set is
6357                                         *   2,048 bytes. Values that are less than 1,518 bytes are
6358                                         *   regarded as 1,518 bytes, and values larger than 2,048 bytes
6359                                         *   are regarded as 2,048 bytes.                                              */
6360             uint32_t : 20;
6361         } RFLR_b;
6362     };
6363     __IM uint32_t RESERVED1;
6364 
6365     union
6366     {
6367         __IOM uint32_t ECSR;           /*!< (@ 0x00000010) ETHERC Status Register                                     */
6368 
6369         struct
6370         {
6371             __IOM uint32_t ICD   : 1;  /*!< [0..0] False Carrier Detect Flag                                          */
6372             __IOM uint32_t MPD   : 1;  /*!< [1..1] Magic Packet Detect Flag                                           */
6373             __IOM uint32_t LCHNG : 1;  /*!< [2..2] LCHNG Link Signal Change Flag                                      */
6374             uint32_t             : 1;
6375             __IOM uint32_t PSRTO : 1;  /*!< [4..4] PAUSE Frame Retransmit Over Flag                                   */
6376             __IOM uint32_t BFR   : 1;  /*!< [5..5] Continuous Broadcast Frame Reception Flag                          */
6377             uint32_t             : 26;
6378         } ECSR_b;
6379     };
6380     __IM uint32_t RESERVED2;
6381 
6382     union
6383     {
6384         __IOM uint32_t ECSIPR;          /*!< (@ 0x00000018) ETHERC Interrupt Enable Register                           */
6385 
6386         struct
6387         {
6388             __IOM uint32_t ICDIP   : 1; /*!< [0..0] False Carrier Detect Interrupt Enable                              */
6389             __IOM uint32_t MPDIP   : 1; /*!< [1..1] Magic Packet Detect Interrupt Enable                               */
6390             __IOM uint32_t LCHNGIP : 1; /*!< [2..2] LINK Signal Change Interrupt Enable                                */
6391             uint32_t               : 1;
6392             __IOM uint32_t PSRTOIP : 1; /*!< [4..4] PAUSE Frame Retransmit Over Interrupt Enable                       */
6393             __IOM uint32_t BFSIPR  : 1; /*!< [5..5] Continuous Broadcast Frame Reception Interrupt Enable              */
6394             uint32_t               : 26;
6395         } ECSIPR_b;
6396     };
6397     __IM uint32_t RESERVED3;
6398 
6399     union
6400     {
6401         __IOM uint32_t PIR;            /*!< (@ 0x00000020) PHY Interface Register                                     */
6402 
6403         struct
6404         {
6405             __IOM uint32_t MDC : 1;    /*!< [0..0] MII/RMII Management Data ClockThe MDC bit value is output
6406                                         *   from the ETn_MDC pin to supply the management data clock
6407                                         *   to the MII or RMII.                                                       */
6408             __IOM uint32_t MMD : 1;    /*!< [1..1] MII/RMII Management Mode                                           */
6409             __IOM uint32_t MDO : 1;    /*!< [2..2] MII/RMII Management Data-OutThe MDO bit value is output
6410                                         *   from the ETn_MDIO pin when the MMD bit is 1 (write). The
6411                                         *   value is not output when the MMD bit is 0 (read).                         */
6412             __IM uint32_t MDI : 1;     /*!< [3..3] MII/RMII Management Data-InThis bit indicates the level
6413                                         *   of the ETn_MDIO pin. The write value should be 0.                         */
6414             uint32_t : 28;
6415         } PIR_b;
6416     };
6417     __IM uint32_t RESERVED4;
6418 
6419     union
6420     {
6421         __IM uint32_t PSR;             /*!< (@ 0x00000028) PHY Status Register                                        */
6422 
6423         struct
6424         {
6425             __IM uint32_t LMON : 1;    /*!< [0..0] ETn_LINKSTA Pin Status FlagThe link status can be read
6426                                         *   by connecting the link signal output from the PHY-LSI to
6427                                         *   the ETn_LINKSTA pin. For details on the polarity, refer
6428                                         *   to the specifications of the connected PHY-LSI.                           */
6429             uint32_t : 31;
6430         } PSR_b;
6431     };
6432     __IM uint32_t RESERVED5[5];
6433 
6434     union
6435     {
6436         __IOM uint32_t RDMLR;          /*!< (@ 0x00000040) Random Number Generation Counter Upper Limit
6437                                         *                  Setting Register                                           */
6438 
6439         struct
6440         {
6441             __IOM uint32_t RMD : 20;   /*!< [19..0] Random Number Generation Counter                                  */
6442             uint32_t           : 12;
6443         } RDMLR_b;
6444     };
6445     __IM uint32_t RESERVED6[3];
6446 
6447     union
6448     {
6449         __IOM uint32_t IPGR;           /*!< (@ 0x00000050) IPG Register                                               */
6450 
6451         struct
6452         {
6453             __IOM uint32_t IPG : 5;    /*!< [4..0] Interpacket Gap Range:'16bit time(0x00)'-'140bit time(0x1F)'       */
6454             uint32_t           : 27;
6455         } IPGR_b;
6456     };
6457 
6458     union
6459     {
6460         __IOM uint32_t APR;            /*!< (@ 0x00000054) Automatic PAUSE Frame Register                             */
6461 
6462         struct
6463         {
6464             __IOM uint32_t AP : 16;    /*!< [15..0] Automatic PAUSE Time SettingThese bits set the value
6465                                         *   of the pause_time parameter for a PAUSE frame that is automatically
6466                                         *   transmitted. Transmission is not performed until the set
6467                                         *   value multiplied by 512 bit time has elapsed.                             */
6468             uint32_t : 16;
6469         } APR_b;
6470     };
6471 
6472     union
6473     {
6474         __OM uint32_t MPR;             /*!< (@ 0x00000058) Manual PAUSE Frame Register                                */
6475 
6476         struct
6477         {
6478             __OM uint32_t MP : 16;     /*!< [15..0] Manual PAUSE Time SettingThese bits set the value of
6479                                         *   the pause_time parameter for a PAUSE frame that is manually
6480                                         *   transmitted. Transmission is not performed until the set
6481                                         *   value multiplied by 512 bit time has elapsed. The read
6482                                         *   value is undefined.                                                       */
6483             uint32_t : 16;
6484         } MPR_b;
6485     };
6486     __IM uint32_t RESERVED7;
6487 
6488     union
6489     {
6490         __IM uint32_t RFCF;            /*!< (@ 0x00000060) Received PAUSE Frame Counter                               */
6491 
6492         struct
6493         {
6494             __IM uint32_t RPAUSE : 8;  /*!< [7..0] Received PAUSE Frame CountNumber of received PAUSE frames          */
6495             uint32_t             : 24;
6496         } RFCF_b;
6497     };
6498 
6499     union
6500     {
6501         __IOM uint32_t TPAUSER;         /*!< (@ 0x00000064) PAUSE Frame Retransmit Count Setting Register              */
6502 
6503         struct
6504         {
6505             __IOM uint32_t TPAUSE : 16; /*!< [15..0] Automatic PAUSE Frame Retransmit Setting                          */
6506             uint32_t              : 16;
6507         } TPAUSER_b;
6508     };
6509     __IM uint32_t TPAUSECR;             /*!< (@ 0x00000068) PAUSE Frame Retransmit Counter                             */
6510 
6511     union
6512     {
6513         __IOM uint32_t BCFRR;           /*!< (@ 0x0000006C) Broadcast Frame Receive Count Setting Register             */
6514 
6515         struct
6516         {
6517             __IOM uint32_t BCF : 16;    /*!< [15..0] Broadcast Frame Continuous Receive Count Setting                  */
6518             uint32_t           : 16;
6519         } BCFRR_b;
6520     };
6521     __IM uint32_t RESERVED8[20];
6522 
6523     union
6524     {
6525         __IOM uint32_t MAHR;           /*!< (@ 0x000000C0) MAC Address Upper Bit Register                             */
6526 
6527         struct
6528         {
6529             __IOM uint32_t MAHR : 32;  /*!< [31..0] MAC Address Upper Bit RegisterThe MAHR register sets
6530                                         *   the upper 32 bits (b47 to b16) of the 48-bit MAC address.                 */
6531         } MAHR_b;
6532     };
6533     __IM uint32_t RESERVED9;
6534 
6535     union
6536     {
6537         __IOM uint32_t MALR;           /*!< (@ 0x000000C8) MAC Address Lower Bit Register                             */
6538 
6539         struct
6540         {
6541             __IOM uint32_t MALR : 16;  /*!< [15..0] MAC Address Lower Bit RegisterThe MALR register sets
6542                                         *   the lower 16 bits of the 48-bit MAC address.                              */
6543             uint32_t : 16;
6544         } MALR_b;
6545     };
6546     __IM uint32_t RESERVED10;
6547 
6548     union
6549     {
6550         __IOM uint32_t TROCR;          /*!< (@ 0x000000D0) Transmit Retry Over Counter Register                       */
6551 
6552         struct
6553         {
6554             __IOM uint32_t TROCR : 32; /*!< [31..0] Transmit Retry Over Counter RegisterThe TROCR register
6555                                         *   is a counter indicating the number of frames that fail
6556                                         *   to be retransmitted.                                                      */
6557         } TROCR_b;
6558     };
6559     __IOM uint32_t CDCR;               /*!< (@ 0x000000D4) Late Collision Detect Counter Register                     */
6560 
6561     union
6562     {
6563         __IOM uint32_t LCCR;           /*!< (@ 0x000000D8) Lost Carrier Counter Register                              */
6564 
6565         struct
6566         {
6567             __IOM uint32_t LCCR : 32;  /*!< [31..0] Lost Carrier Counter RegisterThe LCCR register is a
6568                                         *   counter indicating the number of times a loss of carrier
6569                                         *   is detected during frame transmission.                                    */
6570         } LCCR_b;
6571     };
6572 
6573     union
6574     {
6575         __IOM uint32_t CNDCR;          /*!< (@ 0x000000DC) Carrier Not Detect Counter Register                        */
6576 
6577         struct
6578         {
6579             __IOM uint32_t CNDCR : 32; /*!< [31..0] Carrier Not Detect Counter RegisterThe CNDCR register
6580                                         *   is a counter indicating the number of times a carrier is
6581                                         *   not detected during preamble transmission.                                */
6582         } CNDCR_b;
6583     };
6584     __IM uint32_t RESERVED11;
6585 
6586     union
6587     {
6588         __IOM uint32_t CEFCR;          /*!< (@ 0x000000E4) CRC Error Frame Receive Counter Register                   */
6589 
6590         struct
6591         {
6592             __IOM uint32_t CEFCR : 32; /*!< [31..0] CRC Error Frame Receive Counter RegisterThe CEFCR register
6593                                         *   is a counter indicating the number of received frames where
6594                                         *   a CRC error has been detected.                                            */
6595         } CEFCR_b;
6596     };
6597 
6598     union
6599     {
6600         __IOM uint32_t FRECR;          /*!< (@ 0x000000E8) Frame Receive Error Counter Register                       */
6601 
6602         struct
6603         {
6604             __IOM uint32_t FRECR : 32; /*!< [31..0] Frame Receive Error Counter RegisterThe FRECR register
6605                                         *   is a counter indicating the number of times a frame receive
6606                                         *   error has occurred.                                                       */
6607         } FRECR_b;
6608     };
6609 
6610     union
6611     {
6612         __IOM uint32_t TSFRCR;          /*!< (@ 0x000000EC) Too-Short Frame Receive Counter Register                   */
6613 
6614         struct
6615         {
6616             __IOM uint32_t TSFRCR : 32; /*!< [31..0] Too-Short Frame Receive Counter RegisterThe TSFRCR register
6617                                          *   is a counter indicating the number of times a short frame
6618                                          *   that is shorter than 64 bytes has been received.                          */
6619         } TSFRCR_b;
6620     };
6621 
6622     union
6623     {
6624         __IOM uint32_t TLFRCR;          /*!< (@ 0x000000F0) Too-Long Frame Receive Counter Register                    */
6625 
6626         struct
6627         {
6628             __IOM uint32_t TLFRCR : 32; /*!< [31..0] Too-Long Frame Receive Counter RegisterThe TLFRCR register
6629                                          *   is a counter indicating the number of times a long frame
6630                                          *   that is longer than the RFLR register value has been received.            */
6631         } TLFRCR_b;
6632     };
6633 
6634     union
6635     {
6636         __IOM uint32_t RFCR;           /*!< (@ 0x000000F4) Received Alignment Error Frame Counter Register            */
6637 
6638         struct
6639         {
6640             __IOM uint32_t RFCR : 32;  /*!< [31..0] Received Alignment Error Frame Counter RegisterThe RFCR
6641                                         *   register is a counter indicating the number of times a
6642                                         *   frame has been received with the alignment error (frame
6643                                         *   is not an integral number of octets).                                     */
6644         } RFCR_b;
6645     };
6646 
6647     union
6648     {
6649         __IOM uint32_t MAFCR;          /*!< (@ 0x000000F8) Multicast Address Frame Receive Counter Register           */
6650 
6651         struct
6652         {
6653             __IOM uint32_t MAFCR : 32; /*!< [31..0] Multicast Address Frame Receive Counter RegisterThe
6654                                         *   MAFCR register is a counter indicating the number of times
6655                                         *   a frame where the multicast address is set has been received.             */
6656         } MAFCR_b;
6657     };
6658 } R_ETHERC0_Type;                      /*!< Size = 252 (0xfc)                                                         */
6659 
6660 /* =========================================================================================================================== */
6661 /* ================                                      R_ETHERC_EDMAC                                       ================ */
6662 /* =========================================================================================================================== */
6663 
6664 /**
6665  * @brief Ethernet DMA Controller (R_ETHERC_EDMAC)
6666  */
6667 
6668 typedef struct                         /*!< (@ 0x40114000) R_ETHERC_EDMAC Structure                                   */
6669 {
6670     union
6671     {
6672         __IOM uint32_t EDMR;           /*!< (@ 0x00000000) EDMAC Mode Register                                        */
6673 
6674         struct
6675         {
6676             __OM uint32_t SWR : 1;     /*!< [0..0] Software Reset                                                     */
6677             uint32_t          : 3;
6678             __IOM uint32_t DL : 2;     /*!< [5..4] Transmit/Receive DescriptorLength                                  */
6679             __IOM uint32_t DE : 1;     /*!< [6..6] Big Endian Mode/Little Endian ModeNOTE: This setting
6680                                         *   applies to data for the transmit/receive buffer. It does
6681                                         *   not apply to transmit/receive descriptors and registers.                  */
6682             uint32_t : 25;
6683         } EDMR_b;
6684     };
6685     __IM uint32_t RESERVED;
6686 
6687     union
6688     {
6689         __IOM uint32_t EDTRR;          /*!< (@ 0x00000008) EDMAC Transmit Request Register                            */
6690 
6691         struct
6692         {
6693             __OM uint32_t TR : 1;      /*!< [0..0] Transmit Request                                                   */
6694             uint32_t         : 31;
6695         } EDTRR_b;
6696     };
6697     __IM uint32_t RESERVED1;
6698 
6699     union
6700     {
6701         __IOM uint32_t EDRRR;          /*!< (@ 0x00000010) EDMAC Receive Request Register                             */
6702 
6703         struct
6704         {
6705             __IOM uint32_t RR : 1;     /*!< [0..0] Receive Request                                                    */
6706             uint32_t          : 31;
6707         } EDRRR_b;
6708     };
6709     __IM uint32_t RESERVED2;
6710 
6711     union
6712     {
6713         __IOM uint32_t TDLAR;          /*!< (@ 0x00000018) Transmit Descriptor List Start Address Register            */
6714 
6715         struct
6716         {
6717             __IOM uint32_t TDLAR : 32; /*!< [31..0] The start address of the transmit descriptor list is
6718                                         *   set. Set the start address according to the descriptor
6719                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
6720                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
6721                                         *   boundary: Lower 6 bits = 000000b                                          */
6722         } TDLAR_b;
6723     };
6724     __IM uint32_t RESERVED3;
6725 
6726     union
6727     {
6728         __IOM uint32_t RDLAR;          /*!< (@ 0x00000020) Receive Descriptor List Start Address Register             */
6729 
6730         struct
6731         {
6732             __IOM uint32_t RDLAR : 32; /*!< [31..0] The start address of the receive descriptor list is
6733                                         *   set. Set the start address according to the descriptor
6734                                         *   length selected by the EDMR.DL[1:0] bits.16-byte boundary:
6735                                         *   Lower 4 bits = 0000b32-byte boundary: Lower 5 bits = 00000b64-byte
6736                                         *   boundary: Lower 6 bits = 000000b                                          */
6737         } RDLAR_b;
6738     };
6739     __IM uint32_t RESERVED4;
6740 
6741     union
6742     {
6743         __IOM uint32_t EESR;           /*!< (@ 0x00000028) ETHERC/EDMAC Status Register                               */
6744 
6745         struct
6746         {
6747             __IOM uint32_t CERF : 1;   /*!< [0..0] CRC Error Flag                                                     */
6748             __IOM uint32_t PRE  : 1;   /*!< [1..1] PHY-LSI Receive Error Flag                                         */
6749             __IOM uint32_t RTSF : 1;   /*!< [2..2] Frame-Too-Short Error Flag                                         */
6750             __IOM uint32_t RTLF : 1;   /*!< [3..3] Frame-Too-Long Error Flag                                          */
6751             __IOM uint32_t RRF  : 1;   /*!< [4..4] Alignment Error Flag                                               */
6752             uint32_t            : 2;
6753             __IOM uint32_t RMAF : 1;   /*!< [7..7] Multicast Address Frame Receive Flag                               */
6754             __IOM uint32_t TRO  : 1;   /*!< [8..8] Transmit Retry Over Flag                                           */
6755             __IOM uint32_t CD   : 1;   /*!< [9..9] Late Collision Detect Flag                                         */
6756             __IOM uint32_t DLC  : 1;   /*!< [10..10] Loss of Carrier Detect Flag                                      */
6757             __IOM uint32_t CND  : 1;   /*!< [11..11] Carrier Not Detect Flag                                          */
6758             uint32_t            : 4;
6759             __IOM uint32_t RFOF : 1;   /*!< [16..16] Receive FIFO Overflow Flag                                       */
6760             __IOM uint32_t RDE  : 1;   /*!< [17..17] Receive Descriptor Empty Flag                                    */
6761             __IOM uint32_t FR   : 1;   /*!< [18..18] Frame Receive Flag                                               */
6762             __IOM uint32_t TFUF : 1;   /*!< [19..19] Transmit FIFO Underflow Flag                                     */
6763             __IOM uint32_t TDE  : 1;   /*!< [20..20] Transmit Descriptor Empty Flag                                   */
6764             __IOM uint32_t TC   : 1;   /*!< [21..21] Frame Transfer Complete Flag                                     */
6765             __IM uint32_t  ECI  : 1;   /*!< [22..22] ETHERC Status Register Source FlagNOTE: When the source
6766                                         *   in the ETHERCn.ECSR register is cleared, the ECI flag is
6767                                         *   also cleared.                                                             */
6768             __IOM uint32_t ADE   : 1;  /*!< [23..23] Address Error Flag                                               */
6769             __IOM uint32_t RFCOF : 1;  /*!< [24..24] Receive Frame Counter Overflow Flag                              */
6770             __IOM uint32_t RABT  : 1;  /*!< [25..25] Receive Abort Detect Flag                                        */
6771             __IOM uint32_t TABT  : 1;  /*!< [26..26] Transmit Abort Detect Flag                                       */
6772             uint32_t             : 3;
6773             __IOM uint32_t TWB   : 1;  /*!< [30..30] Write-Back Complete Flag                                         */
6774             uint32_t             : 1;
6775         } EESR_b;
6776     };
6777     __IM uint32_t RESERVED5;
6778 
6779     union
6780     {
6781         __IOM uint32_t EESIPR;          /*!< (@ 0x00000030) ETHERC/EDMAC Status Interrupt Enable Register              */
6782 
6783         struct
6784         {
6785             __IOM uint32_t CERFIP  : 1; /*!< [0..0] CRC Error Interrupt Request Enable                                 */
6786             __IOM uint32_t PREIP   : 1; /*!< [1..1] PHY-LSI Receive Error Interrupt Request Enable                     */
6787             __IOM uint32_t RTSFIP  : 1; /*!< [2..2] Frame-Too-Short Error Interrupt Request Enable                     */
6788             __IOM uint32_t RTLFIP  : 1; /*!< [3..3] Frame-Too-Long Error Interrupt Request Enable                      */
6789             __IOM uint32_t RRFIP   : 1; /*!< [4..4] Alignment Error Interrupt Request Enable                           */
6790             uint32_t               : 2;
6791             __IOM uint32_t RMAFIP  : 1; /*!< [7..7] Multicast Address Frame Receive Interrupt Request Enable           */
6792             __IOM uint32_t TROIP   : 1; /*!< [8..8] Transmit Retry Over Interrupt Request Enable                       */
6793             __IOM uint32_t CDIP    : 1; /*!< [9..9] Late Collision Detect Interrupt Request Enable                     */
6794             __IOM uint32_t DLCIP   : 1; /*!< [10..10] Loss of Carrier Detect Interrupt Request Enable                  */
6795             __IOM uint32_t CNDIP   : 1; /*!< [11..11] Carrier Not Detect Interrupt Request Enable                      */
6796             uint32_t               : 4;
6797             __IOM uint32_t RFOFIP  : 1; /*!< [16..16] Receive FIFO Overflow Interrupt Request Enable                   */
6798             __IOM uint32_t RDEIP   : 1; /*!< [17..17] Receive Descriptor Empty Interrupt Request Enable                */
6799             __IOM uint32_t FRIP    : 1; /*!< [18..18] Frame Receive Interrupt Request Enable                           */
6800             __IOM uint32_t TFUFIP  : 1; /*!< [19..19] Transmit FIFO Underflow Interrupt Request Enable                 */
6801             __IOM uint32_t TDEIP   : 1; /*!< [20..20] Transmit Descriptor Empty Interrupt Request Enable               */
6802             __IOM uint32_t TCIP    : 1; /*!< [21..21] Frame Transfer Complete Interrupt Request Enable                 */
6803             __IOM uint32_t ECIIP   : 1; /*!< [22..22] ETHERC Status Register Source Interrupt Request Enable           */
6804             __IOM uint32_t ADEIP   : 1; /*!< [23..23] Address Error Interrupt Request Enable                           */
6805             __IOM uint32_t RFCOFIP : 1; /*!< [24..24] Receive Frame Counter Overflow Interrupt Request Enable          */
6806             __IOM uint32_t RABTIP  : 1; /*!< [25..25] Receive Abort Detect Interrupt Request Enable                    */
6807             __IOM uint32_t TABTIP  : 1; /*!< [26..26] Transmit Abort Detect Interrupt Request Enable                   */
6808             uint32_t               : 3;
6809             __IOM uint32_t TWBIP   : 1; /*!< [30..30] Write-Back Complete Interrupt Request Enable                     */
6810             uint32_t               : 1;
6811         } EESIPR_b;
6812     };
6813     __IM uint32_t RESERVED6;
6814 
6815     union
6816     {
6817         __IOM uint32_t TRSCER;         /*!< (@ 0x00000038) ETHERC/EDMAC Transmit/Receive Status Copy Enable
6818                                         *                  Register                                                   */
6819 
6820         struct
6821         {
6822             uint32_t              : 4;
6823             __IOM uint32_t RRFCE  : 1; /*!< [4..4] RRF Flag Copy Enable                                               */
6824             uint32_t              : 2;
6825             __IOM uint32_t RMAFCE : 1; /*!< [7..7] RMAF Flag Copy Enable                                              */
6826             uint32_t              : 24;
6827         } TRSCER_b;
6828     };
6829     __IM uint32_t RESERVED7;
6830 
6831     union
6832     {
6833         __IOM uint32_t RMFCR;          /*!< (@ 0x00000040) Missed-Frame Counter Register                              */
6834 
6835         struct
6836         {
6837             __IOM uint32_t MFC : 16;   /*!< [15..0] Missed-Frame CounterThese bits indicate the number of
6838                                         *   frames that are discarded and not transferred to the receive
6839                                         *   buffer during reception.                                                  */
6840             uint32_t : 16;
6841         } RMFCR_b;
6842     };
6843     __IM uint32_t RESERVED8;
6844 
6845     union
6846     {
6847         __IOM uint32_t TFTR;           /*!< (@ 0x00000048) Transmit FIFO Threshold Register                           */
6848 
6849         struct
6850         {
6851             __IOM uint32_t TFT : 11;   /*!< [10..0] Transmit FIFO Threshold00Dh to 200h: The threshold is
6852                                         *   the set value multiplied by 4. Example: 00Dh: 52 bytes
6853                                         *   040h: 256 bytes 100h: 1024 bytes 200h: 2048 bytes                         */
6854             uint32_t : 21;
6855         } TFTR_b;
6856     };
6857     __IM uint32_t RESERVED9;
6858 
6859     union
6860     {
6861         __IOM uint32_t FDR;            /*!< (@ 0x00000050) Transmit FIFO Threshold Register                           */
6862 
6863         struct
6864         {
6865             __IOM uint32_t RFD : 5;    /*!< [4..0] Transmit FIFO Depth                                                */
6866             uint32_t           : 3;
6867             __IOM uint32_t TFD : 5;    /*!< [12..8] Receive FIFO Depth                                                */
6868             uint32_t           : 19;
6869         } FDR_b;
6870     };
6871     __IM uint32_t RESERVED10;
6872 
6873     union
6874     {
6875         __IOM uint32_t RMCR;           /*!< (@ 0x00000058) Receive Method Control Register                            */
6876 
6877         struct
6878         {
6879             __IOM uint32_t RNR : 1;    /*!< [0..0] Receive Request Reset                                              */
6880             uint32_t           : 31;
6881         } RMCR_b;
6882     };
6883     __IM uint32_t RESERVED11[2];
6884 
6885     union
6886     {
6887         __IOM uint32_t TFUCR;          /*!< (@ 0x00000064) Transmit FIFO Underflow Counter                            */
6888 
6889         struct
6890         {
6891             __IOM uint32_t UNDER : 16; /*!< [15..0] Transmit FIFO Underflow CountThese bits indicate how
6892                                         *   many times the transmit FIFO has underflowed. The counter
6893                                         *   stops when the counter value reaches FFFFh.                               */
6894             uint32_t : 16;
6895         } TFUCR_b;
6896     };
6897 
6898     union
6899     {
6900         __IOM uint32_t RFOCR;          /*!< (@ 0x00000068) Receive FIFO Overflow Counter                              */
6901 
6902         struct
6903         {
6904             __IOM uint32_t OVER : 16;  /*!< [15..0] Receive FIFO Overflow CountThese bits indicate how many
6905                                         *   times the receive FIFO has overflowed. The counter stops
6906                                         *   when the counter value reaches FFFFh.                                     */
6907             uint32_t : 16;
6908         } RFOCR_b;
6909     };
6910 
6911     union
6912     {
6913         __IOM uint32_t IOSR;           /*!< (@ 0x0000006C) Independent Output Signal Setting Register                 */
6914 
6915         struct
6916         {
6917             __IOM uint32_t ELB : 1;    /*!< [0..0] External Loopback Mode                                             */
6918             uint32_t           : 31;
6919         } IOSR_b;
6920     };
6921 
6922     union
6923     {
6924         __IOM uint32_t FCFTR;          /*!< (@ 0x00000070) Flow Control Start FIFO Threshold Setting Register         */
6925 
6926         struct
6927         {
6928             __IOM uint32_t RFDO : 3;   /*!< [2..0] Receive FIFO Data PAUSE Output Threshold(When (RFDO+1)x256-32
6929                                         *   bytes of data is stored in the receive FIFO.)                             */
6930             uint32_t            : 13;
6931             __IOM uint32_t RFFO : 3;   /*!< [18..16] Receive FIFO Frame PAUSE Output Threshold(When ((RFFO+1)x2)
6932                                         *   receive frames have been stored in the receive FIFO.)                     */
6933             uint32_t : 13;
6934         } FCFTR_b;
6935     };
6936     __IM uint32_t RESERVED12;
6937 
6938     union
6939     {
6940         __IOM uint32_t RPADIR;         /*!< (@ 0x00000078) Receive Data Padding Insert Register                       */
6941 
6942         struct
6943         {
6944             __IOM uint32_t PADR : 6;   /*!< [5..0] Padding Slot                                                       */
6945             uint32_t            : 10;
6946             __IOM uint32_t PADS : 2;   /*!< [17..16] Padding Size                                                     */
6947             uint32_t            : 14;
6948         } RPADIR_b;
6949     };
6950 
6951     union
6952     {
6953         __IOM uint32_t TRIMD;          /*!< (@ 0x0000007C) Transmit Interrupt Setting Register                        */
6954 
6955         struct
6956         {
6957             __IOM uint32_t TIS : 1;    /*!< [0..0] Transmit Interrupt EnableSet the EESR.TWB flag to 1 in
6958                                         *   the mode selected by the TIM bit to notify an interrupt.                  */
6959             uint32_t           : 3;
6960             __IOM uint32_t TIM : 1;    /*!< [4..4] Transmit Interrupt Mode                                            */
6961             uint32_t           : 27;
6962         } TRIMD_b;
6963     };
6964     __IM uint32_t RESERVED13[18];
6965 
6966     union
6967     {
6968         __IOM uint32_t RBWAR;          /*!< (@ 0x000000C8) Receive Buffer Write Address Register                      */
6969 
6970         struct
6971         {
6972             __IM uint32_t RBWAR : 32;  /*!< [31..0] Receive Buffer Write Address RegisterThe RBWAR register
6973                                         *   indicates the last address that the EDMAC has written data
6974                                         *   to when writing to the receive buffer.Refer to the address
6975                                         *   indicated by the RBWAR register to recognize which address
6976                                         *   in the receive buffer the EDMAC is writing data to. Note
6977                                         *   that the address that the EDMAC is outputting to the receive
6978                                         *   buffer may not match the read value of the RBWAR register
6979                                         *   during data reception.                                                    */
6980         } RBWAR_b;
6981     };
6982 
6983     union
6984     {
6985         __IOM uint32_t RDFAR;          /*!< (@ 0x000000CC) Receive Descriptor Fetch Address Register                  */
6986 
6987         struct
6988         {
6989             __IM uint32_t RDFAR : 32;  /*!< [31..0] Receive Descriptor Fetch Address RegisterThe RDFAR register
6990                                         *   indicates the start address of the last fetched receive
6991                                         *   descriptor when the EDMAC fetches descriptor information
6992                                         *   from the receive descriptor.Refer to the address indicated
6993                                         *   by the RDFAR register to recognize which receive descriptor
6994                                         *   information the EDMAC is using for the current processing.
6995                                         *   Note that the address of the receive descriptor that the
6996                                         *   EDMAC fetches may not match the read value of the RDFAR
6997                                         *   register during data reception.                                           */
6998         } RDFAR_b;
6999     };
7000     __IM uint32_t RESERVED14;
7001 
7002     union
7003     {
7004         __IOM uint32_t TBRAR;          /*!< (@ 0x000000D4) Transmit Buffer Read Address Register                      */
7005 
7006         struct
7007         {
7008             __IM uint32_t TBRAR : 32;  /*!< [31..0] Transmit Buffer Read Address RegisterThe TBRAR register
7009                                         *   indicates the last address that the EDMAC has read data
7010                                         *   from when reading data from the transmit buffer.Refer to
7011                                         *   the address indicated by the TBRAR register to recognize
7012                                         *   which address in the transmit buffer the EDMAC is reading
7013                                         *   from. Note that the address that the EDMAC is outputting
7014                                         *   to the transmit buffer may not match the read value of
7015                                         *   the TBRAR register.                                                       */
7016         } TBRAR_b;
7017     };
7018 
7019     union
7020     {
7021         __IM uint32_t TDFAR;           /*!< (@ 0x000000D8) Transmit Descriptor Fetch Address Register                 */
7022 
7023         struct
7024         {
7025             __IM uint32_t TDFAR : 32;  /*!< [31..0] Transmit Descriptor Fetch Address RegisterThe TDFAR
7026                                         *   register indicates the start address of the last fetched
7027                                         *   transmit descriptor when the EDMAC fetches descriptor information
7028                                         *   from the transmit descriptor.Refer to the address indicated
7029                                         *   by the TDFAR register to recognize which transmit descriptor
7030                                         *   information the EDMAC is using for the current processing.
7031                                         *   Note that the address of the transmit descriptor that the
7032                                         *   EDMAC fetches may not match the read value of the TDFAR
7033                                         *   register.                                                                 */
7034         } TDFAR_b;
7035     };
7036 } R_ETHERC_EDMAC_Type;                 /*!< Size = 220 (0xdc)                                                         */
7037 
7038 /* =========================================================================================================================== */
7039 /* ================                                       R_FACI_HP_CMD                                       ================ */
7040 /* =========================================================================================================================== */
7041 
7042 /**
7043  * @brief Flash Application Command Interface Command-Issuing Area (R_FACI_HP_CMD)
7044  */
7045 
7046 typedef struct                         /*!< (@ 0x407E0000) R_FACI_HP_CMD Structure                                    */
7047 {
7048     union
7049     {
7050         __IOM uint16_t FACI_CMD16;     /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
7051         __IOM uint8_t  FACI_CMD8;      /*!< (@ 0x00000000) FACI Command Issuing Area (halfword access)                */
7052     };
7053 } R_FACI_HP_CMD_Type;                  /*!< Size = 2 (0x2)                                                            */
7054 
7055 /* =========================================================================================================================== */
7056 /* ================                                         R_FACI_HP                                         ================ */
7057 /* =========================================================================================================================== */
7058 
7059 /**
7060  * @brief Flash Application Command Interface (R_FACI_HP)
7061  */
7062 
7063 typedef struct                         /*!< (@ 0x407FE000) R_FACI_HP Structure                                        */
7064 {
7065     __IM uint32_t RESERVED[4];
7066 
7067     union
7068     {
7069         __IOM uint8_t FASTAT;          /*!< (@ 0x00000010) Flash Access Status                                        */
7070 
7071         struct
7072         {
7073             uint8_t             : 3;
7074             __IOM uint8_t DFAE  : 1;   /*!< [3..3] Data Flash Access Error                                            */
7075             __IM uint8_t  CMDLK : 1;   /*!< [4..4] Command Lock                                                       */
7076             uint8_t             : 2;
7077             __IOM uint8_t CFAE  : 1;   /*!< [7..7] Code Flash Access Error                                            */
7078         } FASTAT_b;
7079     };
7080     __IM uint8_t  RESERVED1;
7081     __IM uint16_t RESERVED2;
7082 
7083     union
7084     {
7085         __IOM uint8_t FAEINT;          /*!< (@ 0x00000014) Flash Access Error Interrupt Enable                        */
7086 
7087         struct
7088         {
7089             uint8_t               : 3;
7090             __IOM uint8_t DFAEIE  : 1; /*!< [3..3] Data Flash Access Error Interrupt Enable                           */
7091             __IOM uint8_t CMDLKIE : 1; /*!< [4..4] Command Lock Interrupt Enable                                      */
7092             uint8_t               : 2;
7093             __IOM uint8_t CFAEIE  : 1; /*!< [7..7] Code Flash Access Error Interrupt Enable                           */
7094         } FAEINT_b;
7095     };
7096     __IM uint8_t  RESERVED3;
7097     __IM uint16_t RESERVED4;
7098 
7099     union
7100     {
7101         __IOM uint8_t FRDYIE;          /*!< (@ 0x00000018) Flash Ready Interrupt Enable                               */
7102 
7103         struct
7104         {
7105             __IOM uint8_t FRDYIE : 1;  /*!< [0..0] FRDY Interrupt Enable                                              */
7106             uint8_t              : 7;
7107         } FRDYIE_b;
7108     };
7109     __IM uint8_t  RESERVED5;
7110     __IM uint16_t RESERVED6;
7111     __IM uint32_t RESERVED7[5];
7112 
7113     union
7114     {
7115         __IOM uint32_t FSADDR;         /*!< (@ 0x00000030) Flash Start Address                                        */
7116 
7117         struct
7118         {
7119             __IOM uint32_t FSA : 32;   /*!< [31..0] Start Address of Flash Sequencer Command Target Area
7120                                         *   These bits can be written when FRDY bit of FSTATR register
7121                                         *   is '1'. Writing to these bits in FRDY = '0' is ignored.                   */
7122         } FSADDR_b;
7123     };
7124 
7125     union
7126     {
7127         __IOM uint32_t FEADDR;         /*!< (@ 0x00000034) Flash End Address                                          */
7128 
7129         struct
7130         {
7131             __IOM uint32_t FEA : 32;   /*!< [31..0] End Address of Flash Sequencer Command Target Area Specifies
7132                                         *   end address of target area in 'Blank Check' command. These
7133                                         *   bits can be written when FRDY bit of FSTATR register is
7134                                         *   '1'. Writing to these bits in FRDY = '0' is ignored.                      */
7135         } FEADDR_b;
7136     };
7137     __IM uint32_t RESERVED8[3];
7138 
7139     union
7140     {
7141         __IOM uint16_t FMEPROT;        /*!< (@ 0x00000044) Flash P/E Mode Entry Protection Register                   */
7142 
7143         struct
7144         {
7145             __IOM uint16_t CEPROT : 1; /*!< [0..0] Code Flash P/E Mode Entry ProtectionWriting to this bit
7146                                         *   is only possible when the FRDY bit in the FSTATR register
7147                                         *   is 1. Writing to this bit while the FRDY bit = 0 isignored.Writing
7148                                         *   to this bit is only possible when 16 bits are written and
7149                                         *   the value written to the KEY bits is D9h.Written values
7150                                         *   are not retained by these bits (always read as 0x00).Only
7151                                         *   secure access can write to this register. Both secure access
7152                                         *   and non-secure read access are allowed. Non-secure writeaccess
7153                                         *   is denied, but TrustZo                                                    */
7154             uint16_t          : 7;
7155             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
7156         } FMEPROT_b;
7157     };
7158     __IM uint16_t RESERVED9;
7159     __IM uint32_t RESERVED10[12];
7160 
7161     union
7162     {
7163         __IOM uint16_t FBPROT0;        /*!< (@ 0x00000078) Flash Block Protection Register                            */
7164 
7165         struct
7166         {
7167             __IOM uint16_t BPCN0 : 1;  /*!< [0..0] Block Protection for Non-secure CancelThis bit can be
7168                                         *   written when the FRDY bit in the FSTATR register is 1.
7169                                         *   Writing to this bit is ignored when the FRDY bit is 0.Writing
7170                                         *   to this bit is only possible when 16 bits are written and
7171                                         *   the value written to the KEY[7:0] bits is 0x78.Written
7172                                         *   values are not retained by these bits (always read as 0x00).              */
7173             uint16_t          : 7;
7174             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
7175         } FBPROT0_b;
7176     };
7177     __IM uint16_t RESERVED11;
7178 
7179     union
7180     {
7181         __IOM uint16_t FBPROT1;        /*!< (@ 0x0000007C) Flash Block Protection for Secure Register                 */
7182 
7183         struct
7184         {
7185             __IOM uint16_t BPCN1 : 1;  /*!< [0..0] Block Protection for Secure CancelWriting to this bit
7186                                         *   is only possible when the FRDY bit in the FSTATR register
7187                                         *   is 1. Writing to this bit while FRDY bit = 0 is ignored.Writing
7188                                         *   to this bit is only possible when 16 bits are written and
7189                                         *   the value written to the KEY[7:0] bits is 0xB1.Written
7190                                         *   values are not retained by these bits (always read as 0x00).              */
7191             uint16_t          : 7;
7192             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
7193         } FBPROT1_b;
7194     };
7195     __IM uint16_t RESERVED12;
7196 
7197     union
7198     {
7199         __IM uint32_t FSTATR;          /*!< (@ 0x00000080) Flash Status                                               */
7200 
7201         struct
7202         {
7203             uint32_t                 : 6;
7204             __IM uint32_t FLWEERR    : 1; /*!< [6..6] Flash Write/Erase Protect Error Flag                               */
7205             uint32_t                 : 1;
7206             __IM uint32_t PRGSPD     : 1; /*!< [8..8] Programming-Suspended Status                                       */
7207             __IM uint32_t ERSSPD     : 1; /*!< [9..9] Erasure-Suspended Status                                           */
7208             __IM uint32_t DBFULL     : 1; /*!< [10..10] Data Buffer Full                                                 */
7209             __IM uint32_t SUSRDY     : 1; /*!< [11..11] Suspend Ready                                                    */
7210             __IM uint32_t PRGERR     : 1; /*!< [12..12] Programming Error                                                */
7211             __IM uint32_t ERSERR     : 1; /*!< [13..13] Erasure Error                                                    */
7212             __IM uint32_t ILGLERR    : 1; /*!< [14..14] Illegal Command Error                                            */
7213             __IM uint32_t FRDY       : 1; /*!< [15..15] Flash Ready                                                      */
7214             uint32_t                 : 4;
7215             __IM uint32_t  OTERR     : 1; /*!< [20..20] Other Error                                                      */
7216             __IOM uint32_t SECERR    : 1; /*!< [21..21] Security Error                                                   */
7217             __IM uint32_t  FESETERR  : 1; /*!< [22..22] FENTRY Setting Error                                             */
7218             __IM uint32_t  ILGCOMERR : 1; /*!< [23..23] Illegal Command Error                                            */
7219             uint32_t                 : 8;
7220         } FSTATR_b;
7221     };
7222 
7223     union
7224     {
7225         __IOM uint16_t FENTRYR;         /*!< (@ 0x00000084) Program/Erase Mode Entry                                   */
7226 
7227         struct
7228         {
7229             __IOM uint16_t FENTRYC : 1; /*!< [0..0] Code Flash P/E Mode Entry These bits can be written when
7230                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
7231                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
7232                                          *   only when this register is accessed in 16-bit size and
7233                                          *   H'AA is written to KEY bits                                               */
7234             uint16_t               : 6;
7235             __IOM uint16_t FENTRYD : 1; /*!< [7..7] Data Flash P/E Mode Entry These bits can be written when
7236                                          *   FRDY bit in FSTATR register is '1'. Writing to this bit
7237                                          *   in FRDY = '0' is ignored. Writing to these bits is enabled
7238                                          *   only when this register is accessed in 16-bit size and
7239                                          *   H'AA is written to KEY bits.                                              */
7240             __OM uint16_t KEY : 8;      /*!< [15..8] KEY Code                                                          */
7241         } FENTRYR_b;
7242     };
7243     __IM uint16_t RESERVED13;
7244     __IM uint32_t RESERVED14;
7245 
7246     union
7247     {
7248         __IOM uint16_t FSUINITR;       /*!< (@ 0x0000008C) Flash Sequencer Set-up Initialize                          */
7249 
7250         struct
7251         {
7252             __IOM uint16_t SUINIT : 1; /*!< [0..0] Set-up Initialization This bit can be written when FRDY
7253                                         *   bit of FSTATR register is '1'. Writing to this bit in FRDY
7254                                         *   = '0' is ignored. Writing to these bits is enabled only
7255                                         *   when this register is accessed in 16-bit size and H'2D
7256                                         *   is written to KEY bits.                                                   */
7257             uint16_t          : 7;
7258             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
7259         } FSUINITR_b;
7260     };
7261     __IM uint16_t RESERVED15;
7262     __IM uint32_t RESERVED16[4];
7263 
7264     union
7265     {
7266         __IM uint16_t FCMDR;           /*!< (@ 0x000000A0) Flash Sequencer Command                                    */
7267 
7268         struct
7269         {
7270             __IM uint16_t PCMDR : 8;   /*!< [7..0] Previous Command Register                                          */
7271             __IM uint16_t CMDR  : 8;   /*!< [15..8] Command Register                                                  */
7272         } FCMDR_b;
7273     };
7274     __IM uint16_t RESERVED17;
7275     __IM uint32_t RESERVED18[11];
7276 
7277     union
7278     {
7279         __IOM uint8_t FBCCNT;          /*!< (@ 0x000000D0) Blank Check Control                                        */
7280 
7281         struct
7282         {
7283             __IOM uint8_t BCDIR : 1;   /*!< [0..0] Blank Check Direction                                              */
7284             uint8_t             : 7;
7285         } FBCCNT_b;
7286     };
7287     __IM uint8_t  RESERVED19;
7288     __IM uint16_t RESERVED20;
7289 
7290     union
7291     {
7292         __IM uint8_t FBCSTAT;          /*!< (@ 0x000000D4) Blank Check Status                                         */
7293 
7294         struct
7295         {
7296             __IM uint8_t BCST : 1;     /*!< [0..0] Blank Check Status Bit                                             */
7297             uint8_t           : 7;
7298         } FBCSTAT_b;
7299     };
7300     __IM uint8_t  RESERVED21;
7301     __IM uint16_t RESERVED22;
7302 
7303     union
7304     {
7305         __IM uint32_t FPSADDR;         /*!< (@ 0x000000D8) Programmed Area Start Address                              */
7306 
7307         struct
7308         {
7309             __IM uint32_t PSADR : 19;  /*!< [18..0] Programmed Area Start Address NOTE: Indicates address
7310                                         *   of the first programmed data which is found in 'Blank Check'
7311                                         *   command execution.                                                        */
7312             uint32_t : 13;
7313         } FPSADDR_b;
7314     };
7315 
7316     union
7317     {
7318         __IM uint32_t FAWMON;          /*!< (@ 0x000000DC) Flash Access Window Monitor                                */
7319 
7320         struct
7321         {
7322             __IM uint32_t FAWS : 11;   /*!< [10..0] Start Sector Address for Access Window NOTE: These bits
7323                                         *   indicate the start sector address for setting the access
7324                                         *   window that is located in the configuration area.                         */
7325             uint32_t           : 4;
7326             __IM uint32_t FSPR : 1;    /*!< [15..15] Protection Flag of programming the Access Window, Boot
7327                                         *   Flag and Temporary Boot Swap Control and 'Config Clear'
7328                                         *   command execution                                                         */
7329             __IM uint32_t FAWE : 11;   /*!< [26..16] End Sector Address for Access Window NOTE: These bits
7330                                         *   indicate the end sector address for setting the access
7331                                         *   window that is located in the configuration area.                         */
7332             uint32_t            : 4;
7333             __IM uint32_t BTFLG : 1;   /*!< [31..31] Flag of Start-Up area select for Boot Swap                       */
7334         } FAWMON_b;
7335     };
7336 
7337     union
7338     {
7339         __IOM uint16_t FCPSR;           /*!< (@ 0x000000E0) FCU Process Switch                                         */
7340 
7341         struct
7342         {
7343             __IOM uint16_t ESUSPMD : 1; /*!< [0..0] Erasure-Suspended Mode                                             */
7344             uint16_t               : 15;
7345         } FCPSR_b;
7346     };
7347     __IM uint16_t RESERVED23;
7348 
7349     union
7350     {
7351         __IOM uint16_t FPCKAR;         /*!< (@ 0x000000E4) Flash Sequencer Processing Clock Frequency Notification    */
7352 
7353         struct
7354         {
7355             __IOM uint16_t PCKA : 8;   /*!< [7..0] Flash Sequencer Processing Clock Frequency These bits
7356                                         *   can be written when FRDY bit in FSTATR register is '1'.
7357                                         *   Writing to this bit in FRDY = '0' is ignored. Writing to
7358                                         *   these bits is enabled only when this register is accessed
7359                                         *   in 16-bit size and H'1E is written to KEY bits.                           */
7360             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
7361         } FPCKAR_b;
7362     };
7363     __IM uint16_t RESERVED24;
7364 
7365     union
7366     {
7367         __IOM uint16_t FSUACR;         /*!< (@ 0x000000E8) Flash Start-Up Area Control Register                       */
7368 
7369         struct
7370         {
7371             __IOM uint16_t SAS : 2;    /*!< [1..0] Start Up Area Select These bits can be written when FRDY
7372                                         *   bit in FSTATR register is '1'. Writing to this bit in FRDY
7373                                         *   = '0' is ignored. Writing to these bits is enabled only
7374                                         *   when this register is accessed in 16-bit size and H'66
7375                                         *   is written to KEY bits.                                                   */
7376             uint16_t          : 6;
7377             __OM uint16_t KEY : 8;     /*!< [15..8] KEY Code                                                          */
7378         } FSUACR_b;
7379     };
7380     __IM uint16_t RESERVED25;
7381 } R_FACI_HP_Type;                      /*!< Size = 236 (0xec)                                                         */
7382 
7383 /* =========================================================================================================================== */
7384 /* ================                                         R_FCACHE                                          ================ */
7385 /* =========================================================================================================================== */
7386 
7387 /**
7388  * @brief Flash Memory Cache (R_FCACHE)
7389  */
7390 
7391 typedef struct                         /*!< (@ 0x4001C000) R_FCACHE Structure                                         */
7392 {
7393     __IM uint16_t RESERVED[128];
7394 
7395     union
7396     {
7397         __IOM uint16_t FCACHEE;          /*!< (@ 0x00000100) Flash Cache Enable Register                                */
7398 
7399         struct
7400         {
7401             __IOM uint16_t FCACHEEN : 1; /*!< [0..0] FCACHE Enable                                                      */
7402             uint16_t                : 15;
7403         } FCACHEE_b;
7404     };
7405     __IM uint16_t RESERVED1;
7406 
7407     union
7408     {
7409         __IOM uint16_t FCACHEIV;         /*!< (@ 0x00000104) Flash Cache Invalidate Register                            */
7410 
7411         struct
7412         {
7413             __IOM uint16_t FCACHEIV : 1; /*!< [0..0] Flash Cache Invalidate Register                                    */
7414             uint16_t                : 15;
7415         } FCACHEIV_b;
7416     };
7417     __IM uint16_t RESERVED2[11];
7418 
7419     union
7420     {
7421         __IOM uint8_t FLWT;            /*!< (@ 0x0000011C) Flash Wait Cycle Register                                  */
7422 
7423         struct
7424         {
7425             __IOM uint8_t FLWT : 3;    /*!< [2..0] Flash Wait Cycle                                                   */
7426             uint8_t            : 5;
7427         } FLWT_b;
7428     };
7429     __IM uint8_t  RESERVED3;
7430     __IM uint16_t RESERVED4[17];
7431 
7432     union
7433     {
7434         __IOM uint16_t FSAR;             /*!< (@ 0x00000140) Flash Security Attribution Register                        */
7435 
7436         struct
7437         {
7438             __IOM uint16_t FLWTSA   : 1; /*!< [0..0] FLWT Security Attribution                                          */
7439             uint16_t                : 7;
7440             __IOM uint16_t FCKMHZSA : 1; /*!< [8..8] FCKMHZ Security Attribution                                        */
7441             uint16_t                : 7;
7442         } FSAR_b;
7443     };
7444 } R_FCACHE_Type;                         /*!< Size = 322 (0x142)                                                        */
7445 
7446 /* =========================================================================================================================== */
7447 /* ================                                          R_GPT0                                           ================ */
7448 /* =========================================================================================================================== */
7449 
7450 /**
7451  * @brief General PWM Timer (R_GPT0)
7452  */
7453 
7454 typedef struct                         /*!< (@ 0x40169000) R_GPT0 Structure                                           */
7455 {
7456     union
7457     {
7458         __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
7459 
7460         struct
7461         {
7462             __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disable                                             */
7463             __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disable                                      */
7464             __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disable                                      */
7465             __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disable                                       */
7466             __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
7467             uint32_t             : 3;
7468             __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
7469             uint32_t             : 16;
7470         } GTWP_b;
7471     };
7472 
7473     union
7474     {
7475         __IOM uint32_t GTSTR;           /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
7476 
7477         struct
7478         {
7479             __IOM uint32_t CSTRT0 : 1;  /*!< [0..0] Channel GTCNT Count StartRead data shows each channel's
7480                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7481                                          *   means counter running.                                                    */
7482             __IOM uint32_t CSTRT1 : 1;  /*!< [1..1] Channel GTCNT Count StartRead data shows each channel's
7483                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7484                                          *   means counter running.                                                    */
7485             __IOM uint32_t CSTRT2 : 1;  /*!< [2..2] Channel GTCNT Count StartRead data shows each channel's
7486                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7487                                          *   means counter running.                                                    */
7488             __IOM uint32_t CSTRT3 : 1;  /*!< [3..3] Channel GTCNT Count StartRead data shows each channel's
7489                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7490                                          *   means counter running.                                                    */
7491             __IOM uint32_t CSTRT4 : 1;  /*!< [4..4] Channel GTCNT Count StartRead data shows each channel's
7492                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7493                                          *   means counter running.                                                    */
7494             __IOM uint32_t CSTRT5 : 1;  /*!< [5..5] Channel GTCNT Count StartRead data shows each channel's
7495                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7496                                          *   means counter running.                                                    */
7497             __IOM uint32_t CSTRT6 : 1;  /*!< [6..6] Channel GTCNT Count StartRead data shows each channel's
7498                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7499                                          *   means counter running.                                                    */
7500             __IOM uint32_t CSTRT7 : 1;  /*!< [7..7] Channel GTCNT Count StartRead data shows each channel's
7501                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7502                                          *   means counter running.                                                    */
7503             __IOM uint32_t CSTRT8 : 1;  /*!< [8..8] Channel GTCNT Count StartRead data shows each channel's
7504                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7505                                          *   means counter running.                                                    */
7506             __IOM uint32_t CSTRT9 : 1;  /*!< [9..9] Channel GTCNT Count StartRead data shows each channel's
7507                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7508                                          *   means counter running.                                                    */
7509             __IOM uint32_t CSTRT10 : 1; /*!< [10..10] Channel GTCNT Count StartRead data shows each channel's
7510                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7511                                          *   means counter running.                                                    */
7512             __IOM uint32_t CSTRT11 : 1; /*!< [11..11] Channel GTCNT Count StartRead data shows each channel's
7513                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7514                                          *   means counter running.                                                    */
7515             __IOM uint32_t CSTRT12 : 1; /*!< [12..12] Channel GTCNT Count StartRead data shows each channel's
7516                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7517                                          *   means counter running.                                                    */
7518             __IOM uint32_t CSTRT13 : 1; /*!< [13..13] Channel GTCNT Count StartRead data shows each channel's
7519                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7520                                          *   means counter running.                                                    */
7521             __IOM uint32_t CSTRT14 : 1; /*!< [14..14] Channel GTCNT Count StartRead data shows each channel's
7522                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7523                                          *   means counter running.                                                    */
7524             __IOM uint32_t CSTRT15 : 1; /*!< [15..15] Channel GTCNT Count StartRead data shows each channel's
7525                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7526                                          *   means counter running.                                                    */
7527             __IOM uint32_t CSTRT16 : 1; /*!< [16..16] Channel GTCNT Count StartRead data shows each channel's
7528                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7529                                          *   means counter running.                                                    */
7530             __IOM uint32_t CSTRT17 : 1; /*!< [17..17] Channel GTCNT Count StartRead data shows each channel's
7531                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7532                                          *   means counter running.                                                    */
7533             __IOM uint32_t CSTRT18 : 1; /*!< [18..18] Channel GTCNT Count StartRead data shows each channel's
7534                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7535                                          *   means counter running.                                                    */
7536             __IOM uint32_t CSTRT19 : 1; /*!< [19..19] Channel GTCNT Count StartRead data shows each channel's
7537                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7538                                          *   means counter running.                                                    */
7539             __IOM uint32_t CSTRT20 : 1; /*!< [20..20] Channel GTCNT Count StartRead data shows each channel's
7540                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7541                                          *   means counter running.                                                    */
7542             __IOM uint32_t CSTRT21 : 1; /*!< [21..21] Channel GTCNT Count StartRead data shows each channel's
7543                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7544                                          *   means counter running.                                                    */
7545             __IOM uint32_t CSTRT22 : 1; /*!< [22..22] Channel GTCNT Count StartRead data shows each channel's
7546                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7547                                          *   means counter running.                                                    */
7548             __IOM uint32_t CSTRT23 : 1; /*!< [23..23] Channel GTCNT Count StartRead data shows each channel's
7549                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7550                                          *   means counter running.                                                    */
7551             __IOM uint32_t CSTRT24 : 1; /*!< [24..24] Channel GTCNT Count StartRead data shows each channel's
7552                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7553                                          *   means counter running.                                                    */
7554             __IOM uint32_t CSTRT25 : 1; /*!< [25..25] Channel GTCNT Count StartRead data shows each channel's
7555                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7556                                          *   means counter running.                                                    */
7557             __IOM uint32_t CSTRT26 : 1; /*!< [26..26] Channel GTCNT Count StartRead data shows each channel's
7558                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7559                                          *   means counter running.                                                    */
7560             __IOM uint32_t CSTRT27 : 1; /*!< [27..27] Channel GTCNT Count StartRead data shows each channel's
7561                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7562                                          *   means counter running.                                                    */
7563             __IOM uint32_t CSTRT28 : 1; /*!< [28..28] Channel GTCNT Count StartRead data shows each channel's
7564                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7565                                          *   means counter running.                                                    */
7566             __IOM uint32_t CSTRT29 : 1; /*!< [29..29] Channel GTCNT Count StartRead data shows each channel's
7567                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7568                                          *   means counter running.                                                    */
7569             __IOM uint32_t CSTRT30 : 1; /*!< [30..30] Channel GTCNT Count StartRead data shows each channel's
7570                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7571                                          *   means counter running.                                                    */
7572             __IOM uint32_t CSTRT31 : 1; /*!< [31..31] Channel GTCNT Count StartRead data shows each channel's
7573                                          *   counter status (GTCR.CST bit). 0 means counter stop. 1
7574                                          *   means counter running.                                                    */
7575         } GTSTR_b;
7576     };
7577 
7578     union
7579     {
7580         __IOM uint32_t GTSTP;           /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
7581 
7582         struct
7583         {
7584             __IOM uint32_t CSTOP0 : 1;  /*!< [0..0] Channel GTCNT Count StopRead data shows each channel's
7585                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7586                                          *   1 means counter stop.                                                     */
7587             __IOM uint32_t CSTOP1 : 1;  /*!< [1..1] Channel GTCNT Count StopRead data shows each channel's
7588                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7589                                          *   1 means counter stop.                                                     */
7590             __IOM uint32_t CSTOP2 : 1;  /*!< [2..2] Channel GTCNT Count StopRead data shows each channel's
7591                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7592                                          *   1 means counter stop.                                                     */
7593             __IOM uint32_t CSTOP3 : 1;  /*!< [3..3] Channel GTCNT Count StopRead data shows each channel's
7594                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7595                                          *   1 means counter stop.                                                     */
7596             __IOM uint32_t CSTOP4 : 1;  /*!< [4..4] Channel GTCNT Count StopRead data shows each channel's
7597                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7598                                          *   1 means counter stop.                                                     */
7599             __IOM uint32_t CSTOP5 : 1;  /*!< [5..5] Channel GTCNT Count StopRead data shows each channel's
7600                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7601                                          *   1 means counter stop.                                                     */
7602             __IOM uint32_t CSTOP6 : 1;  /*!< [6..6] Channel GTCNT Count StopRead data shows each channel's
7603                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7604                                          *   1 means counter stop.                                                     */
7605             __IOM uint32_t CSTOP7 : 1;  /*!< [7..7] Channel GTCNT Count StopRead data shows each channel's
7606                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7607                                          *   1 means counter stop.                                                     */
7608             __IOM uint32_t CSTOP8 : 1;  /*!< [8..8] Channel GTCNT Count StopRead data shows each channel's
7609                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7610                                          *   1 means counter stop.                                                     */
7611             __IOM uint32_t CSTOP9 : 1;  /*!< [9..9] Channel GTCNT Count StopRead data shows each channel's
7612                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7613                                          *   1 means counter stop.                                                     */
7614             __IOM uint32_t CSTOP10 : 1; /*!< [10..10] Channel GTCNT Count StopRead data shows each channel's
7615                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7616                                          *   1 means counter stop.                                                     */
7617             __IOM uint32_t CSTOP11 : 1; /*!< [11..11] Channel GTCNT Count StopRead data shows each channel's
7618                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7619                                          *   1 means counter stop.                                                     */
7620             __IOM uint32_t CSTOP12 : 1; /*!< [12..12] Channel GTCNT Count StopRead data shows each channel's
7621                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7622                                          *   1 means counter stop.                                                     */
7623             __IOM uint32_t CSTOP13 : 1; /*!< [13..13] Channel GTCNT Count StopRead data shows each channel's
7624                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7625                                          *   1 means counter stop.                                                     */
7626             __IOM uint32_t CSTOP14 : 1; /*!< [14..14] Channel GTCNT Count StopRead data shows each channel's
7627                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7628                                          *   1 means counter stop.                                                     */
7629             __IOM uint32_t CSTOP15 : 1; /*!< [15..15] Channel GTCNT Count StopRead data shows each channel's
7630                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7631                                          *   1 means counter stop.                                                     */
7632             __IOM uint32_t CSTOP16 : 1; /*!< [16..16] Channel GTCNT Count StopRead data shows each channel's
7633                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7634                                          *   1 means counter stop.                                                     */
7635             __IOM uint32_t CSTOP17 : 1; /*!< [17..17] Channel GTCNT Count StopRead data shows each channel's
7636                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7637                                          *   1 means counter stop.                                                     */
7638             __IOM uint32_t CSTOP18 : 1; /*!< [18..18] Channel GTCNT Count StopRead data shows each channel's
7639                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7640                                          *   1 means counter stop.                                                     */
7641             __IOM uint32_t CSTOP19 : 1; /*!< [19..19] Channel GTCNT Count StopRead data shows each channel's
7642                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7643                                          *   1 means counter stop.                                                     */
7644             __IOM uint32_t CSTOP20 : 1; /*!< [20..20] Channel GTCNT Count StopRead data shows each channel's
7645                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7646                                          *   1 means counter stop.                                                     */
7647             __IOM uint32_t CSTOP21 : 1; /*!< [21..21] Channel GTCNT Count StopRead data shows each channel's
7648                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7649                                          *   1 means counter stop.                                                     */
7650             __IOM uint32_t CSTOP22 : 1; /*!< [22..22] Channel GTCNT Count StopRead data shows each channel's
7651                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7652                                          *   1 means counter stop.                                                     */
7653             __IOM uint32_t CSTOP23 : 1; /*!< [23..23] Channel GTCNT Count StopRead data shows each channel's
7654                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7655                                          *   1 means counter stop.                                                     */
7656             __IOM uint32_t CSTOP24 : 1; /*!< [24..24] Channel GTCNT Count StopRead data shows each channel's
7657                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7658                                          *   1 means counter stop.                                                     */
7659             __IOM uint32_t CSTOP25 : 1; /*!< [25..25] Channel GTCNT Count StopRead data shows each channel's
7660                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7661                                          *   1 means counter stop.                                                     */
7662             __IOM uint32_t CSTOP26 : 1; /*!< [26..26] Channel GTCNT Count StopRead data shows each channel's
7663                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7664                                          *   1 means counter stop.                                                     */
7665             __IOM uint32_t CSTOP27 : 1; /*!< [27..27] Channel GTCNT Count StopRead data shows each channel's
7666                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7667                                          *   1 means counter stop.                                                     */
7668             __IOM uint32_t CSTOP28 : 1; /*!< [28..28] Channel GTCNT Count StopRead data shows each channel's
7669                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7670                                          *   1 means counter stop.                                                     */
7671             __IOM uint32_t CSTOP29 : 1; /*!< [29..29] Channel GTCNT Count StopRead data shows each channel's
7672                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7673                                          *   1 means counter stop.                                                     */
7674             __IOM uint32_t CSTOP30 : 1; /*!< [30..30] Channel GTCNT Count StopRead data shows each channel's
7675                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7676                                          *   1 means counter stop.                                                     */
7677             __IOM uint32_t CSTOP31 : 1; /*!< [31..31] Channel GTCNT Count StopRead data shows each channel's
7678                                          *   counter status (GTCR.CST bit). 0 means counter runnning.
7679                                          *   1 means counter stop.                                                     */
7680         } GTSTP_b;
7681     };
7682 
7683     union
7684     {
7685         __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
7686 
7687         struct
7688         {
7689             __OM uint32_t CCLR0  : 1;  /*!< [0..0] Channel GTCNT Count Clear                                          */
7690             __OM uint32_t CCLR1  : 1;  /*!< [1..1] Channel GTCNT Count Clear                                          */
7691             __OM uint32_t CCLR2  : 1;  /*!< [2..2] Channel GTCNT Count Clear                                          */
7692             __OM uint32_t CCLR3  : 1;  /*!< [3..3] Channel GTCNT Count Clear                                          */
7693             __OM uint32_t CCLR4  : 1;  /*!< [4..4] Channel GTCNT Count Clear                                          */
7694             __OM uint32_t CCLR5  : 1;  /*!< [5..5] Channel GTCNT Count Clear                                          */
7695             __OM uint32_t CCLR6  : 1;  /*!< [6..6] Channel GTCNT Count Clear                                          */
7696             __OM uint32_t CCLR7  : 1;  /*!< [7..7] Channel GTCNT Count Clear                                          */
7697             __OM uint32_t CCLR8  : 1;  /*!< [8..8] Channel GTCNT Count Clear                                          */
7698             __OM uint32_t CCLR9  : 1;  /*!< [9..9] Channel GTCNT Count Clear                                          */
7699             __OM uint32_t CCLR10 : 1;  /*!< [10..10] Channel GTCNT Count Clear                                        */
7700             __OM uint32_t CCLR11 : 1;  /*!< [11..11] Channel GTCNT Count Clear                                        */
7701             __OM uint32_t CCLR12 : 1;  /*!< [12..12] Channel GTCNT Count Clear                                        */
7702             __OM uint32_t CCLR13 : 1;  /*!< [13..13] Channel GTCNT Count Clear                                        */
7703             __OM uint32_t CCLR14 : 1;  /*!< [14..14] Channel GTCNT Count Clear                                        */
7704             __OM uint32_t CCLR15 : 1;  /*!< [15..15] Channel GTCNT Count Clear                                        */
7705             __OM uint32_t CCLR16 : 1;  /*!< [16..16] Channel GTCNT Count Clear                                        */
7706             __OM uint32_t CCLR17 : 1;  /*!< [17..17] Channel GTCNT Count Clear                                        */
7707             __OM uint32_t CCLR18 : 1;  /*!< [18..18] Channel GTCNT Count Clear                                        */
7708             __OM uint32_t CCLR19 : 1;  /*!< [19..19] Channel GTCNT Count Clear                                        */
7709             __OM uint32_t CCLR20 : 1;  /*!< [20..20] Channel GTCNT Count Clear                                        */
7710             __OM uint32_t CCLR21 : 1;  /*!< [21..21] Channel GTCNT Count Clear                                        */
7711             __OM uint32_t CCLR22 : 1;  /*!< [22..22] Channel GTCNT Count Clear                                        */
7712             __OM uint32_t CCLR23 : 1;  /*!< [23..23] Channel GTCNT Count Clear                                        */
7713             __OM uint32_t CCLR24 : 1;  /*!< [24..24] Channel GTCNT Count Clear                                        */
7714             __OM uint32_t CCLR25 : 1;  /*!< [25..25] Channel GTCNT Count Clear                                        */
7715             __OM uint32_t CCLR26 : 1;  /*!< [26..26] Channel GTCNT Count Clear                                        */
7716             __OM uint32_t CCLR27 : 1;  /*!< [27..27] Channel GTCNT Count Clear                                        */
7717             __OM uint32_t CCLR28 : 1;  /*!< [28..28] Channel GTCNT Count Clear                                        */
7718             __OM uint32_t CCLR29 : 1;  /*!< [29..29] Channel GTCNT Count Clear                                        */
7719             __OM uint32_t CCLR30 : 1;  /*!< [30..30] Channel GTCNT Count Clear                                        */
7720             __OM uint32_t CCLR31 : 1;  /*!< [31..31] Channel GTCNT Count Clear                                        */
7721         } GTCLR_b;
7722     };
7723 
7724     union
7725     {
7726         __IOM uint32_t GTSSR;            /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
7727 
7728         struct
7729         {
7730             __IOM uint32_t SSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Start Enable                */
7731             __IOM uint32_t SSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Start Enable               */
7732             __IOM uint32_t SSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Start Enable                */
7733             __IOM uint32_t SSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Start Enable               */
7734             __IOM uint32_t SSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Start Enable                */
7735             __IOM uint32_t SSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Start Enable               */
7736             __IOM uint32_t SSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Start Enable                */
7737             __IOM uint32_t SSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Start Enable               */
7738             __IOM uint32_t SSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7739                                           *   Counter Start Enable                                                      */
7740             __IOM uint32_t SSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7741                                           *   Counter Start Enable                                                      */
7742             __IOM uint32_t SSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7743                                           *   Counter Start Enable                                                      */
7744             __IOM uint32_t SSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7745                                           *   Counter Start Enable                                                      */
7746             __IOM uint32_t SSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7747                                           *   Counter Start Enable                                                      */
7748             __IOM uint32_t SSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7749                                           *   Counter Start Enable                                                      */
7750             __IOM uint32_t SSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7751                                           *   Counter Start Enable                                                      */
7752             __IOM uint32_t SSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7753                                           *   Counter Start Enable                                                      */
7754             __IOM uint32_t SSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Start Enable                        */
7755             __IOM uint32_t SSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Start Enable                        */
7756             __IOM uint32_t SSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Start Enable                        */
7757             __IOM uint32_t SSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Start Enable                        */
7758             __IOM uint32_t SSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Start Enable                        */
7759             __IOM uint32_t SSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Start Enable                        */
7760             __IOM uint32_t SSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Start Enable                        */
7761             __IOM uint32_t SSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Start Enable                        */
7762             uint32_t              : 7;
7763             __IOM uint32_t CSTRT  : 1;   /*!< [31..31] Software Source Counter Start Enable                             */
7764         } GTSSR_b;
7765     };
7766 
7767     union
7768     {
7769         __IOM uint32_t GTPSR;            /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
7770 
7771         struct
7772         {
7773             __IOM uint32_t PSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7774             __IOM uint32_t PSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Stop Enable                */
7775             __IOM uint32_t PSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7776             __IOM uint32_t PSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Stop Enable                */
7777             __IOM uint32_t PSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7778             __IOM uint32_t PSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Stop Enable                */
7779             __IOM uint32_t PSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Stop Enable                 */
7780             __IOM uint32_t PSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Stop Enable                */
7781             __IOM uint32_t PSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7782                                           *   Counter Stop Enable                                                       */
7783             __IOM uint32_t PSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7784                                           *   Counter Stop Enable                                                       */
7785             __IOM uint32_t PSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7786                                           *   Counter Stop Enable                                                       */
7787             __IOM uint32_t PSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7788                                           *   Counter Stop Enable                                                       */
7789             __IOM uint32_t PSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7790                                           *   Counter Stop Enable                                                       */
7791             __IOM uint32_t PSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7792                                           *   Counter Stop Enable                                                       */
7793             __IOM uint32_t PSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7794                                           *   Counter Stop Enable                                                       */
7795             __IOM uint32_t PSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7796                                           *   Counter Stop Enable                                                       */
7797             __IOM uint32_t PSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Stop Enable                        */
7798             __IOM uint32_t PSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Stop Enable                        */
7799             __IOM uint32_t PSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Stop Enable                        */
7800             __IOM uint32_t PSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Stop Enable                        */
7801             __IOM uint32_t PSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Stop Enable                        */
7802             __IOM uint32_t PSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Stop Enable                        */
7803             __IOM uint32_t PSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Stop Enable                        */
7804             __IOM uint32_t PSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Stop Enable                        */
7805             uint32_t              : 7;
7806             __IOM uint32_t CSTOP  : 1;   /*!< [31..31] Software Source Counter Stop Enable                              */
7807         } GTPSR_b;
7808     };
7809 
7810     union
7811     {
7812         __IOM uint32_t GTCSR;            /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
7813 
7814         struct
7815         {
7816             __IOM uint32_t CSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Clear Enable                */
7817             __IOM uint32_t CSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Clear Enable               */
7818             __IOM uint32_t CSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Clear Enable                */
7819             __IOM uint32_t CSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Clear Enable               */
7820             __IOM uint32_t CSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Clear Enable                */
7821             __IOM uint32_t CSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Clear Enable               */
7822             __IOM uint32_t CSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Clear Enable                */
7823             __IOM uint32_t CSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Clear Enable               */
7824             __IOM uint32_t CSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7825                                           *   Counter Clear Enable                                                      */
7826             __IOM uint32_t CSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7827                                           *   Counter Clear Enable                                                      */
7828             __IOM uint32_t CSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7829                                           *   Counter Clear Enable                                                      */
7830             __IOM uint32_t CSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7831                                           *   Counter Clear Enable                                                      */
7832             __IOM uint32_t CSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7833                                           *   Counter Clear Enable                                                      */
7834             __IOM uint32_t CSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7835                                           *   Counter Clear Enable                                                      */
7836             __IOM uint32_t CSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7837                                           *   Counter Clear Enable                                                      */
7838             __IOM uint32_t CSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7839                                           *   Counter Clear Enable                                                      */
7840             __IOM uint32_t CSELCA : 1;   /*!< [16..16] ELC_GPTA Event Source Counter Clear Enable                       */
7841             __IOM uint32_t CSELCB : 1;   /*!< [17..17] ELC_GPTA Event Source Counter Clear Enable                       */
7842             __IOM uint32_t CSELCC : 1;   /*!< [18..18] ELC_GPTA Event Source Counter Clear Enable                       */
7843             __IOM uint32_t CSELCD : 1;   /*!< [19..19] ELC_GPTA Event Source Counter Clear Enable                       */
7844             __IOM uint32_t CSELCE : 1;   /*!< [20..20] ELC_GPTA Event Source Counter Clear Enable                       */
7845             __IOM uint32_t CSELCF : 1;   /*!< [21..21] ELC_GPTA Event Source Counter Clear Enable                       */
7846             __IOM uint32_t CSELCG : 1;   /*!< [22..22] ELC_GPTA Event Source Counter Clear Enable                       */
7847             __IOM uint32_t CSELCH : 1;   /*!< [23..23] ELC_GPTA Event Source Counter Clear Enable                       */
7848             __IOM uint32_t CSCMSC : 3;   /*!< [26..24] Compare Match/Input Capture/Synchronous counter clearing
7849                                           *   Source Counter Clear Enable.                                              */
7850             __IOM uint32_t CP1CCE : 1;   /*!< [27..27] Complementary PWM mode1 Crest Source Counter Clear
7851                                           *   Enable (This bit is only available in GPT324 to GPT329.
7852                                           *   In GPT320 to GPT323, this bit is read as 0. The write value
7853                                           *   should be 0.)                                                             */
7854             uint32_t            : 3;
7855             __IOM uint32_t CCLR : 1;     /*!< [31..31] Software Source Counter Clear Enable                             */
7856         } GTCSR_b;
7857     };
7858 
7859     union
7860     {
7861         __IOM uint32_t GTUPSR;           /*!< (@ 0x0000001C) General PWM Timer Up Count Source Select Register          */
7862 
7863         struct
7864         {
7865             __IOM uint32_t USGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7866             __IOM uint32_t USGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7867             __IOM uint32_t USGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7868             __IOM uint32_t USGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7869             __IOM uint32_t USGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7870             __IOM uint32_t USGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7871             __IOM uint32_t USGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Up Enable             */
7872             __IOM uint32_t USGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Up Enable            */
7873             __IOM uint32_t USCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7874                                           *   Counter Count Up Enable                                                   */
7875             __IOM uint32_t USCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7876                                           *   Counter Count Up Enable                                                   */
7877             __IOM uint32_t USCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7878                                           *   Counter Count Up Enable                                                   */
7879             __IOM uint32_t USCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7880                                           *   Counter Count Up Enable                                                   */
7881             __IOM uint32_t USCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7882                                           *   Counter Count Up Enable                                                   */
7883             __IOM uint32_t USCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7884                                           *   Counter Count Up Enable                                                   */
7885             __IOM uint32_t USCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7886                                           *   Counter Count Up Enable                                                   */
7887             __IOM uint32_t USCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7888                                           *   Counter Count Up Enable                                                   */
7889             __IOM uint32_t USELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Up Enable                     */
7890             __IOM uint32_t USELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Up Enable                     */
7891             __IOM uint32_t USELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Up Enable                     */
7892             __IOM uint32_t USELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Up Enable                     */
7893             __IOM uint32_t USELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Up Enable                     */
7894             __IOM uint32_t USELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Up Enable                     */
7895             __IOM uint32_t USELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Up Enable                     */
7896             __IOM uint32_t USELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Up Enable                     */
7897             __IOM uint32_t USILVL : 4;   /*!< [27..24] External Input Level Source Count-Up Enable                      */
7898             uint32_t              : 4;
7899         } GTUPSR_b;
7900     };
7901 
7902     union
7903     {
7904         __IOM uint32_t GTDNSR;           /*!< (@ 0x00000020) General PWM Timer Down Count Source Select Register        */
7905 
7906         struct
7907         {
7908             __IOM uint32_t DSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7909             __IOM uint32_t DSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7910             __IOM uint32_t DSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7911             __IOM uint32_t DSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7912             __IOM uint32_t DSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7913             __IOM uint32_t DSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7914             __IOM uint32_t DSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source Counter Count Down Enable           */
7915             __IOM uint32_t DSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source Counter Count Down Enable          */
7916             __IOM uint32_t DSCARBL  : 1; /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7917                                           *   Counter Count Down Enable                                                 */
7918             __IOM uint32_t DSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7919                                           *   Counter Count Down Enable                                                 */
7920             __IOM uint32_t DSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7921                                           *   Counter Count Down Enable                                                 */
7922             __IOM uint32_t DSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7923                                           *   Counter Count Down Enable                                                 */
7924             __IOM uint32_t DSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7925                                           *   Counter Count Down Enable                                                 */
7926             __IOM uint32_t DSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7927                                           *   Counter Count Down Enable                                                 */
7928             __IOM uint32_t DSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7929                                           *   Counter Count Down Enable                                                 */
7930             __IOM uint32_t DSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7931                                           *   Counter Count Down Enable                                                 */
7932             __IOM uint32_t DSELCA : 1;   /*!< [16..16] ELC_GPT Event Source Counter Count Down Enable                   */
7933             __IOM uint32_t DSELCB : 1;   /*!< [17..17] ELC_GPT Event Source Counter Count Down Enable                   */
7934             __IOM uint32_t DSELCC : 1;   /*!< [18..18] ELC_GPT Event Source Counter Count Down Enable                   */
7935             __IOM uint32_t DSELCD : 1;   /*!< [19..19] ELC_GPT Event Source Counter Count Down Enable                   */
7936             __IOM uint32_t DSELCE : 1;   /*!< [20..20] ELC_GPT Event Source Counter Count Down Enable                   */
7937             __IOM uint32_t DSELCF : 1;   /*!< [21..21] ELC_GPT Event Source Counter Count Down Enable                   */
7938             __IOM uint32_t DSELCG : 1;   /*!< [22..22] ELC_GPT Event Source Counter Count Down Enable                   */
7939             __IOM uint32_t DSELCH : 1;   /*!< [23..23] ELC_GPT Event Source Counter Count Down Enable                   */
7940             __IOM uint32_t DSILVL : 4;   /*!< [27..24] External Input Level Source Count-Down Enable                    */
7941             uint32_t              : 4;
7942         } GTDNSR_b;
7943     };
7944 
7945     union
7946     {
7947         __IOM uint32_t GTICASR;          /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
7948                                           *                  Register A                                                 */
7949 
7950         struct
7951         {
7952             __IOM uint32_t ASGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7953             __IOM uint32_t ASGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRA Input Capture
7954                                           *   Enable                                                                    */
7955             __IOM uint32_t ASGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7956             __IOM uint32_t ASGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRA Input Capture
7957                                           *   Enable                                                                    */
7958             __IOM uint32_t ASGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7959             __IOM uint32_t ASGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRA Input Capture
7960                                           *   Enable                                                                    */
7961             __IOM uint32_t ASGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRA Input Capture Enable         */
7962             __IOM uint32_t ASGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRA Input Capture
7963                                           *   Enable                                                                    */
7964             __IOM uint32_t ASCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
7965                                           *   GTCCRA Input Capture Enable                                               */
7966             __IOM uint32_t ASCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
7967                                           *   GTCCRA Input Capture Enable                                               */
7968             __IOM uint32_t ASCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
7969                                           *   GTCCRA Input Capture Enable                                               */
7970             __IOM uint32_t ASCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
7971                                           *   GTCCRA Input Capture Enable                                               */
7972             __IOM uint32_t ASCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
7973                                           *   GTCCRA Input Capture Enable                                               */
7974             __IOM uint32_t ASCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
7975                                           *   GTCCRA Input Capture Enable                                               */
7976             __IOM uint32_t ASCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
7977                                           *   GTCCRA Input Capture Enable                                               */
7978             __IOM uint32_t ASCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
7979                                           *   GTCCRA Input Capture Enable                                               */
7980             __IOM uint32_t ASELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7981             __IOM uint32_t ASELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7982             __IOM uint32_t ASELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7983             __IOM uint32_t ASELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7984             __IOM uint32_t ASELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7985             __IOM uint32_t ASELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7986             __IOM uint32_t ASELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7987             __IOM uint32_t ASELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRA Input Capture Enable                 */
7988             uint32_t              : 8;
7989         } GTICASR_b;
7990     };
7991 
7992     union
7993     {
7994         __IOM uint32_t GTICBSR;          /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
7995                                           *                  Register B                                                 */
7996 
7997         struct
7998         {
7999             __IOM uint32_t BSGTRGAR : 1; /*!< [0..0] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
8000             __IOM uint32_t BSGTRGAF : 1; /*!< [1..1] GTETRG Pin Falling Input Source GTCCRB Input Capture
8001                                           *   Enable                                                                    */
8002             __IOM uint32_t BSGTRGBR : 1; /*!< [2..2] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
8003             __IOM uint32_t BSGTRGBF : 1; /*!< [3..3] GTETRG Pin Falling Input Source GTCCRB Input Capture
8004                                           *   Enable                                                                    */
8005             __IOM uint32_t BSGTRGCR : 1; /*!< [4..4] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
8006             __IOM uint32_t BSGTRGCF : 1; /*!< [5..5] GTETRG Pin Falling Input Source GTCCRB Input Capture
8007                                           *   Enable                                                                    */
8008             __IOM uint32_t BSGTRGDR : 1; /*!< [6..6] GTETRG Pin Rising Input Source GTCCRB Input Capture Enable         */
8009             __IOM uint32_t BSGTRGDF : 1; /*!< [7..7] GTETRG Pin Falling Input Source GTCCRB Input Capture
8010                                           *   Enable                                                                    */
8011             __IOM uint32_t BSCARBL : 1;  /*!< [8..8] GTIOCA Pin Rising Input during GTIOCB Value Low Source
8012                                           *   GTCCRB Input Capture Enable                                               */
8013             __IOM uint32_t BSCARBH : 1;  /*!< [9..9] GTIOCA Pin Rising Input during GTIOCB Value High Source
8014                                           *   GTCCRB Input Capture Enable                                               */
8015             __IOM uint32_t BSCAFBL : 1;  /*!< [10..10] GTIOCA Pin Falling Input during GTIOCB Value Low Source
8016                                           *   GTCCRB Input Capture Enable                                               */
8017             __IOM uint32_t BSCAFBH : 1;  /*!< [11..11] GTIOCA Pin Falling Input during GTIOCB Value High Source
8018                                           *   GTCCRB Input Capture Enable                                               */
8019             __IOM uint32_t BSCBRAL : 1;  /*!< [12..12] GTIOCB Pin Rising Input during GTIOCA Value Low Source
8020                                           *   GTCCRB Input Capture Enable                                               */
8021             __IOM uint32_t BSCBRAH : 1;  /*!< [13..13] GTIOCB Pin Rising Input during GTIOCA Value High Source
8022                                           *   GTCCRB Input Capture Enable                                               */
8023             __IOM uint32_t BSCBFAL : 1;  /*!< [14..14] GTIOCB Pin Falling Input during GTIOCA Value Low Source
8024                                           *   GTCCRB Input Capture Enable                                               */
8025             __IOM uint32_t BSCBFAH : 1;  /*!< [15..15] GTIOCB Pin Falling Input during GTIOCA Value High Source
8026                                           *   GTCCRB Input Capture Enable                                               */
8027             __IOM uint32_t BSELCA : 1;   /*!< [16..16] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8028             __IOM uint32_t BSELCB : 1;   /*!< [17..17] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8029             __IOM uint32_t BSELCC : 1;   /*!< [18..18] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8030             __IOM uint32_t BSELCD : 1;   /*!< [19..19] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8031             __IOM uint32_t BSELCE : 1;   /*!< [20..20] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8032             __IOM uint32_t BSELCF : 1;   /*!< [21..21] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8033             __IOM uint32_t BSELCG : 1;   /*!< [22..22] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8034             __IOM uint32_t BSELCH : 1;   /*!< [23..23] ELC_GPT Event Source GTCCRB Input Capture Enable                 */
8035             uint32_t              : 8;
8036         } GTICBSR_b;
8037     };
8038 
8039     union
8040     {
8041         __IOM uint32_t GTCR;            /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
8042 
8043         struct
8044         {
8045             __IOM uint32_t CST     : 1; /*!< [0..0] Count Start                                                        */
8046             uint32_t               : 7;
8047             __IOM uint32_t ICDS    : 1; /*!< [8..8] Input Capture Operation Select During Count Stop                   */
8048             __IOM uint32_t SCGTIOC : 1; /*!< [9..9] GTIOC input Source Synchronous Clear Enable                        */
8049             __IOM uint32_t SSCGRP  : 2; /*!< [11..10] Synchronous Set/Clear Group Select                               */
8050             __IOM uint32_t CPSCD   : 1; /*!< [12..12] Complementary PWM Mode Synchronous Clear Disable                 */
8051             uint32_t               : 2;
8052             __IOM uint32_t SSCEN   : 1; /*!< [15..15] Synchronous Set/Clear Enable                                     */
8053             __IOM uint32_t MD      : 4; /*!< [19..16] Mode Select                                                      */
8054             uint32_t               : 3;
8055             __IOM uint32_t TPCS    : 4; /*!< [26..23] Timer Prescaler Select                                           */
8056             __IOM uint32_t CKEG    : 2; /*!< [28..27] Clock Edge Select                                                */
8057             uint32_t               : 3;
8058         } GTCR_b;
8059     };
8060 
8061     union
8062     {
8063         __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
8064                                         *                  Register                                                   */
8065 
8066         struct
8067         {
8068             __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
8069             __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
8070             uint32_t              : 14;
8071             __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCA Output Duty Setting                                       */
8072             __IOM uint32_t OADTYF : 1; /*!< [18..18] Forcible GTIOCA Output Duty Setting                              */
8073             __IOM uint32_t OADTYR : 1; /*!< [19..19] GTIOCA Output Value Selecting after Releasing 0 percent/100
8074                                         *   percent Duty Setting                                                      */
8075             uint32_t              : 4;
8076             __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCB Output Duty Setting                                       */
8077             __IOM uint32_t OBDTYF : 1; /*!< [26..26] Forcible GTIOCB Output Duty Setting                              */
8078             __IOM uint32_t OBDTYR : 1; /*!< [27..27] GTIOCB Output Value Selecting after Releasing 0 percent/100
8079                                         *   percent Duty Setting                                                      */
8080             uint32_t : 4;
8081         } GTUDDTYC_b;
8082     };
8083 
8084     union
8085     {
8086         __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
8087 
8088         struct
8089         {
8090             __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCA Pin Function Select                                         */
8091             __IOM uint32_t CPSCIR : 1; /*!< [5..5] Complementary PWM Mode Initial Output at Synchronous
8092                                         *   Clear Disable.(This bit is only available in GPT324 to
8093                                         *   GPT329. In GPT320 to GPT323, this bit is read as 0. The
8094                                         *   write value should be 0.)                                                 */
8095             __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCA Pin Output Value Setting at the Count Stop                  */
8096             __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCA Pin Output Setting at the Start/Stop Count                  */
8097             __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCA Pin Output Enable                                           */
8098             __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCA Pin Disable Value Setting                                  */
8099             __IOM uint32_t OAEOCD : 1; /*!< [11..11] GTCCRA Compare Match Cycle End Output Invalidate.(This
8100                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
8101                                         *   GPT323, this bit is read as 0. The write value should be
8102                                         *   0.)                                                                       */
8103             __IOM uint32_t PSYE   : 1; /*!< [12..12] PWM Synchronous output Enable                                    */
8104             __IOM uint32_t NFAEN  : 1; /*!< [13..13] Noise Filter A Enable                                            */
8105             __IOM uint32_t NFCSA  : 2; /*!< [15..14] Noise Filter A Sampling Clock Select                             */
8106             __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCB Pin Function Select                                       */
8107             uint32_t              : 1;
8108             __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCB Pin Output Value Setting at the Count Stop                */
8109             __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCB Pin Output Setting at the Start/Stop Count                */
8110             __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCB Pin Output Enable                                         */
8111             __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCB Pin Disable Value Setting                                 */
8112             __IOM uint32_t OBEOCD : 1; /*!< [27..27] GTCCRB Compare Match Cycle End Output Invalidate.(This
8113                                         *   bit is only available in GPT324 to GPT329. In GPT320 to
8114                                         *   GPT323, this bit is read as 0. The write value should be
8115                                         *   0.)                                                                       */
8116             uint32_t             : 1;
8117             __IOM uint32_t NFBEN : 1;  /*!< [29..29] Noise Filter B Enable                                            */
8118             __IOM uint32_t NFCSB : 2;  /*!< [31..30] Noise Filter B Sampling Clock Select                             */
8119         } GTIOR_b;
8120     };
8121 
8122     union
8123     {
8124         __IOM uint32_t GTINTAD;        /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
8125 
8126         struct
8127         {
8128             uint32_t            : 8;
8129             __IOM uint32_t SCFA : 1;     /*!< [8..8] GTCCRn Register Compare Match/Input Capture Source Synchronous
8130                                           *   Clear Enable                                                              */
8131             __IOM uint32_t SCFB : 1;     /*!< [9..9] GTCCRn Register Compare Match/Input Capture Source Synchronous
8132                                           *   Clear Enable                                                              */
8133             __IOM uint32_t SCFC : 1;     /*!< [10..10] GTCCRn Register Compare Match/Input Capture Source
8134                                           *   Synchronous Clear Enable                                                  */
8135             __IOM uint32_t SCFD : 1;     /*!< [11..11] GTCCRn Register Compare Match/Input Capture Source
8136                                           *   Synchronous Clear Enable                                                  */
8137             __IOM uint32_t SCFE : 1;     /*!< [12..12] GTCCRn Register Compare Match/Input Capture Source
8138                                           *   Synchronous Clear Enable                                                  */
8139             __IOM uint32_t SCFF : 1;     /*!< [13..13] GTCCRn Register Compare Match/Input Capture Source
8140                                           *   Synchronous Clear Enable                                                  */
8141             __IOM uint32_t SCFPO    : 1; /*!< [14..14] Overflow Source Synchronous Clear Enable                         */
8142             __IOM uint32_t SCFPU    : 1; /*!< [15..15] Underflow Source Synchronous Clear Enable                        */
8143             __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
8144                                           *   Start Request Enable                                                      */
8145             __IOM uint32_t ADTRADEN : 1; /*!< [17..17] GTADTRn Register Compare Match (Down-Counting) A/D
8146                                           *   Conversion Start Request Enable                                           */
8147             __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] GTADTRn Register Compare Match (Up-Counting) A/D Conversion
8148                                           *   Start Request Enable                                                      */
8149             __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] GTADTRn Register Compare Match (Down-Counting) A/D
8150                                           *   Conversion Start Request Enable                                           */
8151             uint32_t               : 4;
8152             __IOM uint32_t GRP     : 2;  /*!< [25..24] Output Disable Source Select                                     */
8153             uint32_t               : 2;
8154             __IOM uint32_t GRPDTE  : 1;  /*!< [28..28] Dead Time Error Output Disable Request Enable                    */
8155             __IOM uint32_t GRPABH  : 1;  /*!< [29..29] Same Time Output Level High Disable Request Enable               */
8156             __IOM uint32_t GRPABL  : 1;  /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
8157             __IOM uint32_t GTINTPC : 1;  /*!< [31..31] Period Count Function Finish Interrupt Enable                    */
8158         } GTINTAD_b;
8159     };
8160 
8161     union
8162     {
8163         __IOM uint32_t GTST;            /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
8164 
8165         struct
8166         {
8167             __IOM uint32_t TCFA  : 1;   /*!< [0..0] Input Capture/Compare Match Flag A                                 */
8168             __IOM uint32_t TCFB  : 1;   /*!< [1..1] Input Capture/Compare Match Flag B                                 */
8169             __IOM uint32_t TCFC  : 1;   /*!< [2..2] Input Compare Match Flag C                                         */
8170             __IOM uint32_t TCFD  : 1;   /*!< [3..3] Input Compare Match Flag D                                         */
8171             __IOM uint32_t TCFE  : 1;   /*!< [4..4] Input Compare Match Flag E                                         */
8172             __IOM uint32_t TCFF  : 1;   /*!< [5..5] Input Compare Match Flag F                                         */
8173             __IOM uint32_t TCFPO : 1;   /*!< [6..6] Overflow Flag                                                      */
8174             __IOM uint32_t TCFPU : 1;   /*!< [7..7] Underflow Flag                                                     */
8175             __IM uint32_t  ITCNT : 3;   /*!< [10..8] GTCIV/GTCIU Interrupt Skipping Count Counter(Counter
8176                                          *   for counting the number of times a timer interrupt has
8177                                          *   been skipped.)                                                            */
8178             uint32_t               : 4;
8179             __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
8180             __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Compare Match (Up-Counting) A/D Converter Start
8181                                          *   Request Interrupt Enable                                                  */
8182             __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Compare Match(Down-Counting) A/D Convertor
8183                                          *   Start Request Flag                                                        */
8184             __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Compare Match(Up-Counting) A/D Convertor Start
8185                                          *   Request Flag                                                              */
8186             __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Compare Match(Down-Counting) A/D Convertor
8187                                          *   Start Request Flag                                                        */
8188             uint32_t             : 4;
8189             __IM uint32_t ODF    : 1;   /*!< [24..24] Output Disable Flag                                              */
8190             uint32_t             : 3;
8191             __IM uint32_t  DTEF  : 1;   /*!< [28..28] Dead Time Error Flag                                             */
8192             __IM uint32_t  OABHF : 1;   /*!< [29..29] Same Time Output Level High Disable Request Enable               */
8193             __IM uint32_t  OABLF : 1;   /*!< [30..30] Same Time Output Level Low Disable Request Enable                */
8194             __IOM uint32_t PCF   : 1;   /*!< [31..31] Period Count Function Finish Flag                                */
8195         } GTST_b;
8196     };
8197 
8198     union
8199     {
8200         __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
8201 
8202         struct
8203         {
8204             __IOM uint32_t BD0     : 1; /*!< [0..0] BD[0]: GTCCR Buffer Operation Disable                              */
8205             __IOM uint32_t BD1     : 1; /*!< [1..1] BD[1]: GTPR Buffer Operation Disable                               */
8206             __IOM uint32_t BD2     : 1; /*!< [2..2] BD[2]: GTADTR Buffer Operation DisableBD                           */
8207             __IOM uint32_t BD3     : 1; /*!< [3..3] BD[3]: GTDV Buffer Operation DisableBD[2]                          */
8208             uint32_t               : 4;
8209             __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRn Register Double Buffer Repeat Operation Enable              */
8210             uint32_t               : 1;
8211             __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRn Register Double Buffer Repeat Operation Enable            */
8212             uint32_t               : 5;
8213             __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Buffer Operation                                          */
8214             __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Buffer Operation                                          */
8215             __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Buffer Operation                                            */
8216             __OM uint32_t  CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Forcible Buffer OperationThis bit
8217                                          *   is read as 0.                                                             */
8218             uint32_t             : 1;
8219             __IOM uint32_t ADTTA : 2;   /*!< [25..24] GTADTRA Buffer Transfer Timing Select in the Triangle
8220                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
8221                                          *   at an underflow (in down-counting) or overflow (in up-counting)
8222                                          *   is performed.                                                             */
8223             __IOM uint32_t ADTDA : 1;   /*!< [26..26] GTADTRA Double Buffer Operation                                  */
8224             uint32_t             : 1;
8225             __IOM uint32_t ADTTB : 2;   /*!< [29..28] GTADTRB Buffer Transfer Timing Select in the Triangle
8226                                          *   wavesNOTE: In the Saw waves, values other than 0 0: Transfer
8227                                          *   at an underflow (in down-counting) or overflow (in up-counting)
8228                                          *   is performed.                                                             */
8229             __IOM uint32_t ADTDB : 1;   /*!< [30..30] GTADTRB Double Buffer Operation                                  */
8230             uint32_t             : 1;
8231         } GTBER_b;
8232     };
8233 
8234     union
8235     {
8236         __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
8237                                         *                  Start Request Skipping Setting Register                    */
8238 
8239         struct
8240         {
8241             __IOM uint32_t ITLA  : 1;  /*!< [0..0] GTCCRA Compare Match/Input Capture Interrupt Link                  */
8242             __IOM uint32_t ITLB  : 1;  /*!< [1..1] GTCCRB Compare Match/Input Capture Interrupt Link                  */
8243             __IOM uint32_t ITLC  : 1;  /*!< [2..2] GTCCRC Compare Match Interrupt Link                                */
8244             __IOM uint32_t ITLD  : 1;  /*!< [3..3] GTCCRD Compare Match Interrupt Link                                */
8245             __IOM uint32_t ITLE  : 1;  /*!< [4..4] GTCCRE Compare Match Interrupt Link                                */
8246             __IOM uint32_t ITLF  : 1;  /*!< [5..5] GTCCRF Compare Match Interrupt Link                                */
8247             __IOM uint32_t IVTC  : 2;  /*!< [7..6] GPT_OVF/GPT_UDF Interrupt Skipping Function Select                 */
8248             __IOM uint32_t IVTT  : 3;  /*!< [10..8] GPT_OVF/GPT_UDF Interrupt Skipping Count Select                   */
8249             uint32_t             : 1;
8250             __IOM uint32_t ADTAL : 1;  /*!< [12..12] GTADTRA A/D Converter Start Request Link                         */
8251             uint32_t             : 1;
8252             __IOM uint32_t ADTBL : 1;  /*!< [14..14] GTADTRB A/D Converter Start Request Link                         */
8253             uint32_t             : 17;
8254         } GTITC_b;
8255     };
8256 
8257     union
8258     {
8259         __IOM uint32_t GTCNT;          /*!< (@ 0x00000048) General PWM Timer Counter                                  */
8260 
8261         struct
8262         {
8263             __IOM uint32_t GTCNT : 32; /*!< [31..0] Counter                                                           */
8264         } GTCNT_b;
8265     };
8266 
8267     union
8268     {
8269         __IOM uint32_t GTCCR[6];       /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register                 */
8270 
8271         struct
8272         {
8273             __IOM uint32_t GTCCR : 32; /*!< [31..0] Compare Capture Register A                                        */
8274         } GTCCR_b[6];
8275     };
8276 
8277     union
8278     {
8279         __IOM uint32_t GTPR;           /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
8280 
8281         struct
8282         {
8283             __IOM uint32_t GTPR : 32;  /*!< [31..0] Cycle Setting Register                                            */
8284         } GTPR_b;
8285     };
8286 
8287     union
8288     {
8289         __IOM uint32_t GTPBR;          /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
8290 
8291         struct
8292         {
8293             __IOM uint32_t GTPBR : 32; /*!< [31..0] Cycle Setting Buffer Register                                     */
8294         } GTPBR_b;
8295     };
8296 
8297     union
8298     {
8299         __IOM uint32_t GTPDBR;          /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
8300                                          *                  Register                                                   */
8301 
8302         struct
8303         {
8304             __IOM uint32_t GTPDBR : 32; /*!< [31..0] Cycle Setting Double-Buffer Register                              */
8305         } GTPDBR_b;
8306     };
8307 
8308     union
8309     {
8310         __IOM uint32_t GTADTRA;          /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A              */
8311 
8312         struct
8313         {
8314             __IOM uint32_t GTADTRA : 32; /*!< [31..0] A/D Converter Start Request Timing Register A                     */
8315         } GTADTRA_b;
8316     };
8317 
8318     union
8319     {
8320         __IOM uint32_t GTADTBRA;          /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
8321                                            *                  A                                                          */
8322 
8323         struct
8324         {
8325             __IOM uint32_t GTADTBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register A              */
8326         } GTADTBRA_b;
8327     };
8328 
8329     union
8330     {
8331         __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
8332                                             *                  Register A                                                 */
8333 
8334         struct
8335         {
8336             __IOM uint32_t GTADTDBRA : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
8337                                             *   A                                                                         */
8338         } GTADTDBRA_b;
8339     };
8340 
8341     union
8342     {
8343         __IOM uint32_t GTADTRB;          /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B              */
8344 
8345         struct
8346         {
8347             __IOM uint32_t GTADTRB : 32; /*!< [31..0] A/D Converter Start Request Timing Register B                     */
8348         } GTADTRB_b;
8349     };
8350 
8351     union
8352     {
8353         __IOM uint32_t GTADTBRB;          /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
8354                                            *                  B                                                          */
8355 
8356         struct
8357         {
8358             __IOM uint32_t GTADTBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Buffer Register B              */
8359         } GTADTBRB_b;
8360     };
8361 
8362     union
8363     {
8364         __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
8365                                             *                  Register B                                                 */
8366 
8367         struct
8368         {
8369             __IOM uint32_t GTADTDBRB : 32; /*!< [31..0] A/D Converter Start Request Timing Double-Buffer Register
8370                                             *   B                                                                         */
8371         } GTADTDBRB_b;
8372     };
8373 
8374     union
8375     {
8376         __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
8377 
8378         struct
8379         {
8380             __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
8381             uint32_t             : 3;
8382             __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Buffer Operation Enable                                      */
8383             __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Buffer Operation Enable                                      */
8384             uint32_t             : 2;
8385             __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Setting                                                      */
8386             uint32_t             : 23;
8387         } GTDTCR_b;
8388     };
8389 
8390     union
8391     {
8392         __IOM uint32_t GTDVU;          /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U               */
8393 
8394         struct
8395         {
8396             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Value Register U                                        */
8397         } GTDVU_b;
8398     };
8399 
8400     union
8401     {
8402         __IOM uint32_t GTDVD;          /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D               */
8403 
8404         struct
8405         {
8406             __IOM uint32_t GTDVD : 32; /*!< [31..0] Dead Time Value Register D                                        */
8407         } GTDVD_b;
8408     };
8409 
8410     union
8411     {
8412         __IOM uint32_t GTDBU;          /*!< (@ 0x00000094) General PWM Timer Dead Time Buffer Register U              */
8413 
8414         struct
8415         {
8416             __IOM uint32_t GTDVU : 32; /*!< [31..0] Dead Time Buffer Register U                                       */
8417         } GTDBU_b;
8418     };
8419 
8420     union
8421     {
8422         __IOM uint32_t GTDBD;          /*!< (@ 0x00000098) General PWM Timer Dead Time Buffer Register D              */
8423 
8424         struct
8425         {
8426             __IOM uint32_t GTDBD : 32; /*!< [31..0] Dead Time Buffer Register D                                       */
8427         } GTDBD_b;
8428     };
8429 
8430     union
8431     {
8432         __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
8433                                         *                  Status Register                                            */
8434 
8435         struct
8436         {
8437             __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
8438             uint32_t          : 30;
8439         } GTSOS_b;
8440     };
8441 
8442     union
8443     {
8444         __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
8445                                         *                  Temporary Release Register                                 */
8446 
8447         struct
8448         {
8449             __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
8450             uint32_t            : 31;
8451         } GTSOTR_b;
8452     };
8453 
8454     union
8455     {
8456         __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
8457                                          *                  Signal Monitoring Register                                 */
8458 
8459         struct
8460         {
8461             __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
8462             uint32_t               : 6;
8463             __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
8464                                          *   Enabling                                                                  */
8465             uint32_t               : 7;
8466             __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
8467             uint32_t               : 6;
8468             __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
8469                                          *   Enabling                                                                  */
8470             uint32_t : 7;
8471         } GTADSMR_b;
8472     };
8473 
8474     union
8475     {
8476         __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
8477                                            *                  Counter Control Register                                   */
8478 
8479         struct
8480         {
8481             __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
8482             uint32_t               : 2;
8483             __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
8484             uint32_t               : 4;
8485             __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
8486             __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
8487                                            *   select                                                                    */
8488             uint32_t                 : 2;
8489             __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
8490             __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
8491             __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
8492         } GTEITC_b;
8493     };
8494 
8495     union
8496     {
8497         __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
8498                                         *                  Setting Register 1                                         */
8499 
8500         struct
8501         {
8502             __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match/Input Capture Interrupt
8503                                         *   Extended Skipping Function Select                                         */
8504             uint32_t             : 1;
8505             __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match/Input Capture Interrupt
8506                                         *   Extended Skipping Function Select                                         */
8507             uint32_t             : 1;
8508             __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match Interrupt Extended Skipping
8509                                         *   Function Select                                                           */
8510             uint32_t             : 1;
8511             __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match Interrupt Extended Skipping
8512                                         *   Function Select                                                           */
8513             uint32_t             : 1;
8514             __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match Interrupt Extended Skipping
8515                                         *   Function Select                                                           */
8516             uint32_t             : 1;
8517             __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match Interrupt Extended Skipping
8518                                         *   Function Select                                                           */
8519             uint32_t             : 1;
8520             __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
8521             uint32_t             : 1;
8522             __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
8523             uint32_t             : 1;
8524         } GTEITLI1_b;
8525     };
8526 
8527     union
8528     {
8529         __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
8530                                         *                  Setting Register 2                                         */
8531 
8532         struct
8533         {
8534             __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA Register A/D Conversion Start Request Extended
8535                                         *   Skipping Function Select                                                  */
8536             uint32_t              : 1;
8537             __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB Register A/D Conversion Start Request Extended
8538                                         *   Skipping Function Select                                                  */
8539             uint32_t : 25;
8540         } GTEITLI2_b;
8541     };
8542 
8543     union
8544     {
8545         __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
8546                                          *                  Setting Register                                           */
8547 
8548         struct
8549         {
8550             __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
8551                                          *   Select                                                                    */
8552             uint32_t              : 1;
8553             __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
8554                                          *   Select                                                                    */
8555             uint32_t              : 1;
8556             __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
8557                                          *   Select                                                                    */
8558             uint32_t               : 5;
8559             __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
8560                                          *   Function Select                                                           */
8561             uint32_t               : 1;
8562             __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
8563                                          *   Function Select                                                           */
8564             uint32_t               : 1;
8565             __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
8566                                          *   Select                                                                    */
8567             uint32_t               : 1;
8568             __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
8569                                          *   Select                                                                    */
8570             uint32_t : 1;
8571         } GTEITLB_b;
8572     };
8573 
8574     union
8575     {
8576         __IOM uint32_t GTICLF;           /*!< (@ 0x000000B8) General PWM Timer Inter Channel Logical Operation
8577                                           *                  Function Setting Register                                  */
8578 
8579         struct
8580         {
8581             __IOM uint32_t ICLFA    : 3; /*!< [2..0] GTIOCnA Output Logical Operation Function Select                   */
8582             uint32_t                : 1;
8583             __IOM uint32_t ICLFSELC : 6; /*!< [9..4] Inter Channel Signal C Select                                      */
8584             uint32_t                : 6;
8585             __IOM uint32_t ICLFB    : 3; /*!< [18..16] GTIOCnB Output Logical Operation Function Select                 */
8586             uint32_t                : 1;
8587             __IOM uint32_t ICLFSELD : 6; /*!< [25..20] Inter Channel Signal D Select                                    */
8588             uint32_t                : 6;
8589         } GTICLF_b;
8590     };
8591 
8592     union
8593     {
8594         __IOM uint32_t GTPC;           /*!< (@ 0x000000BC) General PWM Timer Period Count Register                    */
8595 
8596         struct
8597         {
8598             __IOM uint32_t PCEN : 1;   /*!< [0..0] Period Count Function Enable                                       */
8599             uint32_t            : 7;
8600             __IOM uint32_t ASTP : 1;   /*!< [8..8] Automatic Stop Function Enable                                     */
8601             uint32_t            : 7;
8602             __IOM uint32_t PCNT : 12;  /*!< [27..16] Period Counter                                                   */
8603             uint32_t            : 4;
8604         } GTPC_b;
8605     };
8606     __IM uint32_t RESERVED[4];
8607 
8608     union
8609     {
8610         __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
8611                                          *                  Control Channel Select Register                            */
8612 
8613         struct
8614         {
8615             __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
8616                                          *   Select                                                                    */
8617             __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
8618                                          *   Select                                                                    */
8619             __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
8620                                          *   Select                                                                    */
8621             __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
8622                                          *   Select                                                                    */
8623             __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
8624                                          *   Select                                                                    */
8625             __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
8626                                          *   Select                                                                    */
8627             __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
8628                                          *   Select                                                                    */
8629             __IOM uint32_t SECSEL7 : 1; /*!< [7..7] Channel 7 Operation Enable Bit Simultaneous Control Channel
8630                                          *   Select                                                                    */
8631             __IOM uint32_t SECSEL8 : 1; /*!< [8..8] Channel 8 Operation Enable Bit Simultaneous Control Channel
8632                                          *   Select                                                                    */
8633             __IOM uint32_t SECSEL9 : 1; /*!< [9..9] Channel 9 Operation Enable Bit Simultaneous Control Channel
8634                                          *   Select                                                                    */
8635             uint32_t : 22;
8636         } GTSECSR_b;
8637     };
8638 
8639     union
8640     {
8641         __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
8642                                         *                  Control Register                                           */
8643 
8644         struct
8645         {
8646             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
8647             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
8648             __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
8649             __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
8650             uint32_t             : 4;
8651             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
8652             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
8653             __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
8654             __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
8655             uint32_t             : 4;
8656             __IOM uint32_t SPCE  : 1;  /*!< [16..16] Period Count Function Simultaneous Enable                        */
8657             __IOM uint32_t SSCE  : 1;  /*!< [17..17] Synchronous Set/Clear Simultaneous Enable                        */
8658             uint32_t             : 6;
8659             __IOM uint32_t SPCD  : 1;  /*!< [24..24] Period Count Function Simultaneous Disable                       */
8660             __IOM uint32_t SSCD  : 1;  /*!< [25..25] Synchronous Set/Clear Simultaneous Disable                       */
8661             uint32_t             : 6;
8662         } GTSECR_b;
8663     };
8664     __IM uint32_t RESERVED1[2];
8665 
8666     union
8667     {
8668         __IOM uint32_t GTBER2;         /*!< (@ 0x000000E0) General PWM Timer Buffer Enable Register 2                 */
8669 
8670         struct
8671         {
8672             __IOM uint32_t CCTCA : 1;  /*!< [0..0] Counter Clear Source GTCCRA Register Buffer Transfer
8673                                         *   Disable                                                                   */
8674             __IOM uint32_t CCTCB : 1;  /*!< [1..1] Counter Clear Source GTCCRB Register Buffer Transfer
8675                                         *   Disable                                                                   */
8676             __IOM uint32_t CCTPR  : 1; /*!< [2..2] Counter Clear Source GTPR Register Buffer Transfer Disable         */
8677             __IOM uint32_t CCTADA : 1; /*!< [3..3] Counter Clear Source GTADTRA Register Buffer Transfer
8678                                         *   Disable                                                                   */
8679             __IOM uint32_t CCTADB : 1; /*!< [4..4] Counter Clear Source GTADTRB Register Buffer Transfer
8680                                         *   Disable                                                                   */
8681             __IOM uint32_t CCTDV : 1;  /*!< [5..5] Counter Clear Source GTDVU/GTDVD Register Buffer Transfer
8682                                         *   Disable                                                                   */
8683             uint32_t             : 2;
8684             __IOM uint32_t CMTCA : 2;  /*!< [9..8] Compare Match Source GTCCRA Register Buffer Transfer
8685                                         *   Enable                                                                    */
8686             __IOM uint32_t CMTCB : 2;  /*!< [11..10] Compare Match Source GTCCRB Register Buffer Transfer
8687                                         *   Enable                                                                    */
8688             uint32_t              : 1;
8689             __IOM uint32_t CMTADA : 1; /*!< [13..13] Compare Match Source GTADTRA Register Buffer Transfer
8690                                         *   Enable                                                                    */
8691             __IOM uint32_t CMTADB : 1; /*!< [14..14] Compare Match Source GTADTRA Register Buffer Transfer
8692                                         *   Enable                                                                    */
8693             uint32_t             : 1;
8694             __IOM uint32_t CPTCA : 1;  /*!< [16..16] Overflow/Underflow Source GTCCRA Register Buffer Transfer
8695                                         *   Disable                                                                   */
8696             __IOM uint32_t CPTCB : 1;  /*!< [17..17] Overflow/Underflow Source GTCCRB Register Buffer Transfer
8697                                         *   Disable                                                                   */
8698             __IOM uint32_t CPTPR : 1;  /*!< [18..18] Overflow/Underflow Source GTPR Register Buffer Transfer
8699                                         *   Disable                                                                   */
8700             __IOM uint32_t CPTADA : 1; /*!< [19..19] Overflow/Underflow Source GTADTRA Register Buffer Transfer
8701                                         *   Disable                                                                   */
8702             __IOM uint32_t CPTADB : 1; /*!< [20..20] Overflow/Underflow Source GTADTRB Register Buffer Transfer
8703                                         *   Disable                                                                   */
8704             __IOM uint32_t CPTDV : 1;  /*!< [21..21] Overflow/Underflow Source GTDVU/GTDVD Register Buffer
8705                                         *   Transfer Disable                                                          */
8706             uint32_t             : 2;
8707             __IOM uint32_t CP3DB : 1;  /*!< [24..24] Complementary PWM mode 3,4 Double Buffer select                  */
8708             __IOM uint32_t CPBTD : 1;  /*!< [25..25] Complementary PWM mode Buffer Transfer Disable                   */
8709             __IOM uint32_t OLTTA : 2;  /*!< [27..26] GTIOCnA Output Level Buffer Transfer Timing Select               */
8710             __IOM uint32_t OLTTB : 2;  /*!< [29..28] GTIOCnB Output Level Buffer Transfer Timing Select               */
8711             uint32_t             : 2;
8712         } GTBER2_b;
8713     };
8714 
8715     union
8716     {
8717         __IOM uint32_t GTOLBR;         /*!< (@ 0x000000E4) General PWM Timer Output Level Buffer Register             */
8718 
8719         struct
8720         {
8721             __IOM uint32_t GTIOAB : 5; /*!< [4..0] GTIOA buffer bits                                                  */
8722             uint32_t              : 11;
8723             __IOM uint32_t GTIOBB : 5; /*!< [20..16] GTIOBB buffer bits                                               */
8724             uint32_t              : 11;
8725         } GTOLBR_b;
8726     };
8727     __IM uint32_t RESERVED2;
8728 
8729     union
8730     {
8731         __IOM uint32_t GTICCR;         /*!< (@ 0x000000EC) General PWM Timer Inter Channel Cooperation Input
8732                                         *                  Capture Control Register                                   */
8733 
8734         struct
8735         {
8736             __IOM uint32_t ICAFA : 1;  /*!< [0..0] Forwarding GTCCRA register Compare Match/Input Capture
8737                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
8738             __IOM uint32_t ICAFB : 1;  /*!< [1..1] Forwarding GTCCRB register Compare Match/Input Capture
8739                                         *   to Other Channel GTCCRA Input Capture Source Enable                       */
8740             __IOM uint32_t ICAFC : 1;  /*!< [2..2] Forwarding GTCCRC register Compare Match Capture to Other
8741                                         *   Channel GTCCRA Input Capture Source Enable                                */
8742             __IOM uint32_t ICAFD : 1;  /*!< [3..3] Forwarding GTCCRD register Compare Match Capture to Other
8743                                         *   Channel GTCCRA Input Capture Source Enable                                */
8744             __IOM uint32_t ICAFE : 1;  /*!< [4..4] Forwarding GTCCRE register Compare Match Capture to Other
8745                                         *   Channel GTCCRA Input Capture Source Enable                                */
8746             __IOM uint32_t ICAFF : 1;  /*!< [5..5] Forwarding GTCCRF register Compare Match Capture to Other
8747                                         *   Channel GTCCRA Input Capture Source Enable                                */
8748             __IOM uint32_t ICAFPO : 1; /*!< [6..6] Forwarding Overflow to Other Channel GTCCRA Input Capture
8749                                         *   Source Enable                                                             */
8750             __IOM uint32_t ICAFPU : 1; /*!< [7..7] Forwarding Underflow to Other Channel GTCCRA Input Capture
8751                                         *   Source Enable                                                             */
8752             __IOM uint32_t ICACLK : 1; /*!< [8..8] Forwarding Count Clock to Other Channel GTCCRA Input
8753                                         *   Capture Source Enable                                                     */
8754             uint32_t              : 5;
8755             __IOM uint32_t ICAGRP : 2; /*!< [15..14] GTCCRA Input Capture Group Select                                */
8756             __IOM uint32_t ICBFA  : 1; /*!< [16..16] Forwarding GTCCRA register Compare Match/Input Capture
8757                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
8758             __IOM uint32_t ICBFB : 1;  /*!< [17..17] Forwarding GTCCRB register Compare Match/Input Capture
8759                                         *   to Other Channel GTCCRB Input Capture Source Enable                       */
8760             __IOM uint32_t ICBFC : 1;  /*!< [18..18] Forwarding GTCCRC register Compare Match Capture to
8761                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8762             __IOM uint32_t ICBFD : 1;  /*!< [19..19] Forwarding GTCCRD register Compare Match Capture to
8763                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8764             __IOM uint32_t ICBFE : 1;  /*!< [20..20] Forwarding GTCCRE register Compare Match Capture to
8765                                         *   Other Channel GTCCRb Input Capture Source Enable                          */
8766             __IOM uint32_t ICBFF : 1;  /*!< [21..21] Forwarding GTCCRF register Compare Match Capture to
8767                                         *   Other Channel GTCCRB Input Capture Source Enable                          */
8768             __IOM uint32_t ICBFPO : 1; /*!< [22..22] Forwarding Overflow to Other Channel GTCCRB Input Capture
8769                                         *   Source Enable                                                             */
8770             __IOM uint32_t ICBFPU : 1; /*!< [23..23] Forwarding Underflow to Other Channel GTCCRB Input
8771                                         *   Capture Source Enable                                                     */
8772             __IOM uint32_t ICBCLK : 1; /*!< [24..24] Forwarding Count Clock to Other Channel GTCCRB Input
8773                                         *   Capture Source Enable                                                     */
8774             uint32_t              : 5;
8775             __IOM uint32_t ICBGRP : 2; /*!< [31..30] GTCCRB Input Capture Group Select                                */
8776         } GTICCR_b;
8777     };
8778 } R_GPT0_Type;                         /*!< Size = 240 (0xf0)                                                         */
8779 
8780 /* =========================================================================================================================== */
8781 /* ================                                         R_GPT_OPS                                         ================ */
8782 /* =========================================================================================================================== */
8783 
8784 /**
8785  * @brief Output Phase Switching for GPT (R_GPT_OPS)
8786  */
8787 
8788 typedef struct                         /*!< (@ 0x40169A00) R_GPT_OPS Structure                                        */
8789 {
8790     union
8791     {
8792         __IOM uint32_t OPSCR;          /*!< (@ 0x00000000) Output Phase Switching Control Register                    */
8793 
8794         struct
8795         {
8796             __IOM uint32_t UF : 1;     /*!< [0..0] Input Phase Soft Setting WFThis bit sets the input phase
8797                                         *   by the software settings.This bit setting is valid when
8798                                         *   the OPSCR.FB bit = 1.                                                     */
8799             __IOM uint32_t VF : 1;     /*!< [1..1] Input Phase Soft Setting VFThis bit sets the input phase
8800                                         *   by the software settings.This bit setting is valid when
8801                                         *   the OPSCR.FB bit = 1.                                                     */
8802             __IOM uint32_t WF : 1;     /*!< [2..2] Input Phase Soft Setting UFThis bit sets the input phase
8803                                         *   by the software settings.This bit setting is valid when
8804                                         *   the OPSCR.FB bit = 1.                                                     */
8805             uint32_t        : 1;
8806             __IM uint32_t U : 1;       /*!< [4..4] Input U-Phase MonitorThis bit monitors the state of the
8807                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8808                                         *   e settings (UF/VF/WF)                                                     */
8809             __IM uint32_t V : 1;       /*!< [5..5] Input V-Phase MonitorThis bit monitors the state of the
8810                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8811                                         *   e settings (UF/VF/WF)                                                     */
8812             __IM uint32_t W : 1;       /*!< [6..6] Input W-Phase MonitorThis bit monitors the state of the
8813                                         *   input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Softwa
8814                                         *   e settings (UF/VF/WF)                                                     */
8815             uint32_t          : 1;
8816             __IOM uint32_t EN : 1;     /*!< [8..8] Enable-Phase Output Control                                        */
8817             uint32_t          : 7;
8818             __IOM uint32_t FB : 1;     /*!< [16..16] External Feedback Signal EnableThis bit selects the
8819                                         *   input phase from the software settings and external input.                */
8820             __IOM uint32_t P     : 1;  /*!< [17..17] Positive-Phase Output (P) Control                                */
8821             __IOM uint32_t N     : 1;  /*!< [18..18] Negative-Phase Output (N) Control                                */
8822             __IOM uint32_t INV   : 1;  /*!< [19..19] Invert-Phase Output Control                                      */
8823             __IOM uint32_t RV    : 1;  /*!< [20..20] Output phase rotation direction reversal                         */
8824             __IOM uint32_t ALIGN : 1;  /*!< [21..21] Input phase alignment                                            */
8825             uint32_t             : 2;
8826             __IOM uint32_t GRP   : 2;  /*!< [25..24] Output disabled source selection                                 */
8827             __IOM uint32_t GODF  : 1;  /*!< [26..26] Group output disable function                                    */
8828             uint32_t             : 2;
8829             __IOM uint32_t NFEN  : 1;  /*!< [29..29] External Input Noise Filter Enable                               */
8830             __IOM uint32_t NFCS  : 2;  /*!< [31..30] External Input Noise Filter Clock selectionNoise filter
8831                                         *   sampling clock setting of the external input.                             */
8832         } OPSCR_b;
8833     };
8834 } R_GPT_OPS_Type;                      /*!< Size = 4 (0x4)                                                            */
8835 
8836 /* =========================================================================================================================== */
8837 /* ================                                        R_GPT_POEG0                                        ================ */
8838 /* =========================================================================================================================== */
8839 
8840 /**
8841  * @brief Port Output Enable for GPT (R_GPT_POEG0)
8842  */
8843 
8844 typedef struct                          /*!< (@ 0x4008A000) R_GPT_POEG0 Structure                                      */
8845 {
8846     union
8847     {
8848         __IOM uint32_t POEGG;           /*!< (@ 0x00000000) POEG Group Setting Register                                */
8849 
8850         struct
8851         {
8852             __IOM uint32_t PIDF  : 1;   /*!< [0..0] Port Input Detection Flag                                          */
8853             __IOM uint32_t IOCF  : 1;   /*!< [1..1] Real Time Overcurrent Detection Flag                               */
8854             __IOM uint32_t OSTPF : 1;   /*!< [2..2] Oscillation Stop Detection Flag                                    */
8855             __IOM uint32_t SSF   : 1;   /*!< [3..3] Software Stop Flag                                                 */
8856             __IOM uint32_t PIDE  : 1;   /*!< [4..4] Port Input Detection Enable. Note: Can be modified only
8857                                          *   once after a reset.                                                       */
8858             __IOM uint32_t IOCE : 1;    /*!< [5..5] Enable for GPT Output-Disable Request. Note: Can be modified
8859                                          *   only once after a reset.                                                  */
8860             __IOM uint32_t OSTPE : 1;   /*!< [6..6] Oscillation Stop Detection Enable. Note: Can be modified
8861                                          *   only once after a reset.                                                  */
8862             uint32_t             : 1;
8863             __IOM uint32_t CDRE0 : 1;   /*!< [8..8] Comparator Disable Request Enable. Note: Can be modified
8864                                          *   only once after a reset.                                                  */
8865             __IOM uint32_t CDRE1 : 1;   /*!< [9..9] Comparator Disable Request Enable. Note: Can be modified
8866                                          *   only once after a reset.                                                  */
8867             __IOM uint32_t CDRE2 : 1;   /*!< [10..10] Comparator Disable Request Enable. Note: Can be modified
8868                                          *   only once after a reset.                                                  */
8869             __IOM uint32_t CDRE3 : 1;   /*!< [11..11] Comparator Disable Request Enable. Note: Can be modified
8870                                          *   only once after a reset.                                                  */
8871             __IOM uint32_t CDRE4 : 1;   /*!< [12..12] Comparator Disable Request Enable. Note: Can be modified
8872                                          *   only once after a reset.                                                  */
8873             __IOM uint32_t CDRE5 : 1;   /*!< [13..13] Comparator Disable Request Enable. Note: Can be modified
8874                                          *   only once after a reset.                                                  */
8875             uint32_t               : 2;
8876             __IM uint32_t ST       : 1; /*!< [16..16] GTETRG Input Status Flag                                         */
8877             uint32_t               : 7;
8878             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 Error Detection Flag                                      */
8879             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 Error Detection Flag                                      */
8880             __IOM uint32_t DERR0E  : 1; /*!< [26..26] DSMIF0 Error Detection Enable                                    */
8881             __IOM uint32_t DERR1E  : 1; /*!< [27..27] DSMIF1 Error Detection Enable                                    */
8882             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRG Input Reverse                                             */
8883             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise Filter Enable                                              */
8884             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise Filter Clock Select                                        */
8885         } POEGG_b;
8886     };
8887     __IM uint32_t RESERVED[15];
8888 
8889     union
8890     {
8891         __IOM uint16_t GTONCWP;        /*!< (@ 0x00000040) GPT Output Stopping Control Group Write Protection
8892                                         *                  Register                                                   */
8893 
8894         struct
8895         {
8896             __IOM uint16_t WP    : 1;  /*!< [0..0] Register Writing Disable                                           */
8897             uint16_t             : 7;
8898             __IOM uint16_t PRKEY : 8;  /*!< [15..8] Key Code                                                          */
8899         } GTONCWP_b;
8900     };
8901     __IM uint16_t RESERVED1;
8902 
8903     union
8904     {
8905         __IOM uint16_t GTONCCR;        /*!< (@ 0x00000044) GPT Output Stopping Control Group Controlling
8906                                         *                  Register                                                   */
8907 
8908         struct
8909         {
8910             __IOM uint16_t NE  : 1;    /*!< [0..0] Direct Stopping Request Setting                                    */
8911             uint16_t           : 3;
8912             __IOM uint16_t NFS : 4;    /*!< [7..4] Direct Stopping Request Selection                                  */
8913             __IOM uint16_t NFV : 1;    /*!< [8..8] Direct Stopping Request Active Sense                               */
8914             uint16_t           : 7;
8915         } GTONCCR_b;
8916     };
8917     __IM uint16_t RESERVED2;
8918 } R_GPT_POEG0_Type;                    /*!< Size = 72 (0x48)                                                          */
8919 
8920 /* =========================================================================================================================== */
8921 /* ================                                           R_ICU                                           ================ */
8922 /* =========================================================================================================================== */
8923 
8924 /**
8925  * @brief Interrupt Controller Unit (R_ICU)
8926  */
8927 
8928 typedef struct                         /*!< (@ 0x40006000) R_ICU Structure                                            */
8929 {
8930     union
8931     {
8932         __IOM uint8_t IRQCR[16];       /*!< (@ 0x00000000) IRQ Control Register [0..15]                               */
8933 
8934         struct
8935         {
8936             __IOM uint8_t IRQMD   : 2; /*!< [1..0] IRQ Detection Sense Select                                         */
8937             uint8_t               : 2;
8938             __IOM uint8_t FCLKSEL : 2; /*!< [5..4] IRQ Digital Filter Sampling Clock Select                           */
8939             uint8_t               : 1;
8940             __IOM uint8_t FLTEN   : 1; /*!< [7..7] IRQ Digital Filter Enable                                          */
8941         } IRQCR_b[16];
8942     };
8943     __IM uint32_t RESERVED[60];
8944 
8945     union
8946     {
8947         __IOM uint8_t NMICR;            /*!< (@ 0x00000100) NMI Pin Interrupt Control Register                         */
8948 
8949         struct
8950         {
8951             __IOM uint8_t NMIMD    : 1; /*!< [0..0] NMI Detection Set                                                  */
8952             uint8_t                : 3;
8953             __IOM uint8_t NFCLKSEL : 2; /*!< [5..4] NMI Digital Filter Sampling Clock Select                           */
8954             uint8_t                : 1;
8955             __IOM uint8_t NFLTEN   : 1; /*!< [7..7] NMI Digital Filter Enable                                          */
8956         } NMICR_b;
8957     };
8958     __IM uint8_t  RESERVED1;
8959     __IM uint16_t RESERVED2;
8960     __IM uint32_t RESERVED3[7];
8961 
8962     union
8963     {
8964         __IOM uint16_t NMIER;           /*!< (@ 0x00000120) Non-Maskable Interrupt Enable Register                     */
8965 
8966         struct
8967         {
8968             __IOM uint16_t IWDTEN  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Interrupt Enable                      */
8969             __IOM uint16_t WDTEN   : 1; /*!< [1..1] WDT Underflow/Refresh Error Interrupt Enable                       */
8970             __IOM uint16_t LVD1EN  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Enable                              */
8971             __IOM uint16_t LVD2EN  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Enable                              */
8972             __IOM uint16_t VBATTEN : 1; /*!< [4..4] VBATT monitor Interrupt Enable                                     */
8973             uint16_t               : 1;
8974             __IOM uint16_t OSTEN   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Enable                        */
8975             __IOM uint16_t NMIEN   : 1; /*!< [7..7] NMI Pin Interrupt Enable                                           */
8976             __IOM uint16_t RPEEN   : 1; /*!< [8..8] RAM Parity Error Interrupt Enable                                  */
8977             __IOM uint16_t RECCEN  : 1; /*!< [9..9] RAM ECC Error Interrupt Enable                                     */
8978             __IOM uint16_t BUSSEN  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Enable                             */
8979             __IOM uint16_t BUSMEN  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Enable                            */
8980             __IOM uint16_t SPEEN   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Enable                       */
8981             __IOM uint16_t TZFEN   : 1; /*!< [13..13] TZFEN                                                            */
8982             uint16_t               : 1;
8983             __IOM uint16_t CPEEN   : 1; /*!< [15..15] CPEEN                                                            */
8984         } NMIER_b;
8985     };
8986     __IM uint16_t RESERVED4;
8987     __IM uint32_t RESERVED5[3];
8988 
8989     union
8990     {
8991         __IOM uint16_t NMICLR;          /*!< (@ 0x00000130) Non-Maskable Interrupt Status Clear Register               */
8992 
8993         struct
8994         {
8995             __OM uint16_t IWDTCLR  : 1; /*!< [0..0] IWDT Clear                                                         */
8996             __OM uint16_t WDTCLR   : 1; /*!< [1..1] WDT Clear                                                          */
8997             __OM uint16_t LVD1CLR  : 1; /*!< [2..2] LVD1 Clear                                                         */
8998             __OM uint16_t LVD2CLR  : 1; /*!< [3..3] LVD2 Clear                                                         */
8999             __OM uint16_t VBATTCLR : 1; /*!< [4..4] VBATT Clear                                                        */
9000             uint16_t               : 1;
9001             __OM uint16_t  OSTCLR  : 1; /*!< [6..6] OST Clear                                                          */
9002             __OM uint16_t  NMICLR  : 1; /*!< [7..7] NMI Clear                                                          */
9003             __OM uint16_t  RPECLR  : 1; /*!< [8..8] SRAM Parity Error Clear                                            */
9004             __OM uint16_t  RECCCLR : 1; /*!< [9..9] SRAM ECC Error Clear                                               */
9005             __OM uint16_t  BUSSCLR : 1; /*!< [10..10] Bus Slave Error Clear                                            */
9006             __OM uint16_t  BUSMCLR : 1; /*!< [11..11] Bus Master Error Clear                                           */
9007             __OM uint16_t  SPECLR  : 1; /*!< [12..12] CPU Stack Pointer Monitor Interrupt Clear                        */
9008             __IOM uint16_t TZFCLR  : 1; /*!< [13..13] TZFCLR                                                           */
9009             uint16_t               : 1;
9010             __IOM uint16_t CPECLR  : 1; /*!< [15..15] CPECLR                                                           */
9011         } NMICLR_b;
9012     };
9013     __IM uint16_t RESERVED6;
9014     __IM uint32_t RESERVED7[3];
9015 
9016     union
9017     {
9018         __IM uint16_t NMISR;           /*!< (@ 0x00000140) Non-Maskable Interrupt Status Register                     */
9019 
9020         struct
9021         {
9022             __IM uint16_t IWDTST  : 1; /*!< [0..0] IWDT Underflow/Refresh Error Status Flag                           */
9023             __IM uint16_t WDTST   : 1; /*!< [1..1] WDT Underflow/Refresh Error Status Flag                            */
9024             __IM uint16_t LVD1ST  : 1; /*!< [2..2] Voltage-Monitoring 1 Interrupt Status Flag                         */
9025             __IM uint16_t LVD2ST  : 1; /*!< [3..3] Voltage-Monitoring 2 Interrupt Status Flag                         */
9026             __IM uint16_t VBATTST : 1; /*!< [4..4] VBATT monitor Interrupt Status Flag                                */
9027             uint16_t              : 1;
9028             __IM uint16_t OSTST   : 1; /*!< [6..6] Oscillation Stop Detection Interrupt Status Flag                   */
9029             __IM uint16_t NMIST   : 1; /*!< [7..7] NMI Status Flag                                                    */
9030             __IM uint16_t RPEST   : 1; /*!< [8..8] RAM Parity Error Interrupt Status Flag                             */
9031             __IM uint16_t RECCST  : 1; /*!< [9..9] RAM ECC Error Interrupt Status Flag                                */
9032             __IM uint16_t BUSSST  : 1; /*!< [10..10] MPU Bus Slave Error Interrupt Status Flag                        */
9033             __IM uint16_t BUSMST  : 1; /*!< [11..11] MPU Bus Master Error Interrupt Status Flag                       */
9034             __IM uint16_t SPEST   : 1; /*!< [12..12] CPU Stack pointer monitor Interrupt Status Flag                  */
9035             __IM uint16_t TZFST   : 1; /*!< [13..13] TZFST                                                            */
9036             uint16_t              : 1;
9037             __IM uint16_t CPEST   : 1; /*!< [15..15] CPEST                                                            */
9038         } NMISR_b;
9039     };
9040     __IM uint16_t RESERVED8;
9041     __IM uint32_t RESERVED9[23];
9042 
9043     union
9044     {
9045         __IOM uint32_t WUPEN;                /*!< (@ 0x000001A0) Wake Up Interrupt Enable Register                          */
9046 
9047         struct
9048         {
9049             __IOM uint32_t IRQWUPEN0    : 1; /*!< [0..0] IRQ interrupt S/W standby returns enable                           */
9050             __IOM uint32_t IRQWUPEN1    : 1; /*!< [1..1] IRQ interrupt S/W standby returns enable                           */
9051             __IOM uint32_t IRQWUPEN2    : 1; /*!< [2..2] IRQ interrupt S/W standby returns enable                           */
9052             __IOM uint32_t IRQWUPEN3    : 1; /*!< [3..3] IRQ interrupt S/W standby returns enable                           */
9053             __IOM uint32_t IRQWUPEN4    : 1; /*!< [4..4] IRQ interrupt S/W standby returns enable                           */
9054             __IOM uint32_t IRQWUPEN5    : 1; /*!< [5..5] IRQ interrupt S/W standby returns enable                           */
9055             __IOM uint32_t IRQWUPEN6    : 1; /*!< [6..6] IRQ interrupt S/W standby returns enable                           */
9056             __IOM uint32_t IRQWUPEN7    : 1; /*!< [7..7] IRQ interrupt S/W standby returns enable                           */
9057             __IOM uint32_t IRQWUPEN8    : 1; /*!< [8..8] IRQ interrupt S/W standby returns enable                           */
9058             __IOM uint32_t IRQWUPEN9    : 1; /*!< [9..9] IRQ interrupt S/W standby returns enable                           */
9059             __IOM uint32_t IRQWUPEN10   : 1; /*!< [10..10] IRQ interrupt S/W standby returns enable                         */
9060             __IOM uint32_t IRQWUPEN11   : 1; /*!< [11..11] IRQ interrupt S/W standby returns enable                         */
9061             __IOM uint32_t IRQWUPEN12   : 1; /*!< [12..12] IRQ interrupt S/W standby returns enable                         */
9062             __IOM uint32_t IRQWUPEN13   : 1; /*!< [13..13] IRQ interrupt S/W standby returns enable                         */
9063             __IOM uint32_t IRQWUPEN14   : 1; /*!< [14..14] IRQ interrupt S/W standby returns enable                         */
9064             __IOM uint32_t IRQWUPEN15   : 1; /*!< [15..15] IRQ interrupt S/W standby returns enable                         */
9065             __IOM uint32_t IWDTWUPEN    : 1; /*!< [16..16] IWDT interrupt S/W standby returns enable                        */
9066             __IOM uint32_t KEYWUPEN     : 1; /*!< [17..17] Key interrupt S/W standby returns enable                         */
9067             __IOM uint32_t LVD1WUPEN    : 1; /*!< [18..18] LVD1 interrupt S/W standby returns enable                        */
9068             __IOM uint32_t LVD2WUPEN    : 1; /*!< [19..19] LVD2 interrupt S/W standby returns enable                        */
9069             __IOM uint32_t VBATTWUPEN   : 1; /*!< [20..20] VBATT monitor interrupt S/W standby returns enable               */
9070             uint32_t                    : 1;
9071             __IOM uint32_t ACMPHS0WUPEN : 1; /*!< [22..22] ACMPHS0 interrupt S/W standby returns enable bit                 */
9072             __IOM uint32_t ACMPLP0WUPEN : 1; /*!< [23..23] ACMPLP0 interrupt S/W standby returns enable                     */
9073             __IOM uint32_t RTCALMWUPEN  : 1; /*!< [24..24] RTC alarm interrupt S/W standby returns enable                   */
9074             __IOM uint32_t RTCPRDWUPEN  : 1; /*!< [25..25] RCT period interrupt S/W standby returns enable                  */
9075             __IOM uint32_t USBHSWUPEN   : 1; /*!< [26..26] USBHS interrupt S/W standby returns enable bit                   */
9076             __IOM uint32_t USBFSWUPEN   : 1; /*!< [27..27] USBFS interrupt S/W standby returns enable                       */
9077             __IOM uint32_t AGT1UDWUPEN  : 1; /*!< [28..28] AGT1 underflow interrupt S/W standby returns enable              */
9078             __IOM uint32_t AGT1CAWUPEN  : 1; /*!< [29..29] AGT1 compare match A interrupt S/W standby returns
9079                                               *   enable                                                                    */
9080             __IOM uint32_t AGT1CBWUPEN : 1;  /*!< [30..30] AGT1 compare match B interrupt S/W standby returns
9081                                               *   enable                                                                    */
9082             __IOM uint32_t IIC0WUPEN : 1;    /*!< [31..31] IIC0 address match interrupt S/W standby returns enable          */
9083         } WUPEN_b;
9084     };
9085 
9086     union
9087     {
9088         __IOM uint32_t WUPEN1;              /*!< (@ 0x000001A4) Wake Up interrupt enable register 1                        */
9089 
9090         struct
9091         {
9092             __IOM uint32_t AGT3UDWUPEN : 1; /*!< [0..0] AGT3 underflow interrupt S/W standby returns enable bit            */
9093             __IOM uint32_t AGT3CAWUPEN : 1; /*!< [1..1] AGT3 compare match A interrupt S/W standby returns enable
9094                                              *   bit                                                                       */
9095             __IOM uint32_t AGT3CBWUPEN : 1; /*!< [2..2] AGT3 compare match B interrupt S/W standby returns enable
9096                                              *   bit                                                                       */
9097             uint32_t : 29;
9098         } WUPEN1_b;
9099     };
9100     __IM uint32_t RESERVED10[6];
9101 
9102     union
9103     {
9104         __IOM uint8_t IELEN;            /*!< (@ 0x000001C0) ICU event Enable Register                                  */
9105 
9106         struct
9107         {
9108             __IOM uint8_t RTCINTEN : 1; /*!< [0..0] RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit
9109                                          *   = 1)                                                                      */
9110             __IOM uint8_t IELEN : 1;    /*!< [1..1] Parts Asynchronous Interrupts Enable except RTC (when
9111                                          *   LPOPTEN bit = 1)                                                          */
9112             uint8_t : 6;
9113         } IELEN_b;
9114     };
9115     __IM uint8_t  RESERVED11;
9116     __IM uint16_t RESERVED12;
9117     __IM uint32_t RESERVED13[15];
9118 
9119     union
9120     {
9121         __IOM uint16_t SELSR0;         /*!< (@ 0x00000200) Snooze Event Link Setting Register                         */
9122 
9123         struct
9124         {
9125             __IOM uint16_t SELS : 9;   /*!< [8..0] SYS Event Link Select                                              */
9126             uint16_t            : 7;
9127         } SELSR0_b;
9128     };
9129     __IM uint16_t RESERVED14;
9130     __IM uint32_t RESERVED15[31];
9131 
9132     union
9133     {
9134         __IOM uint32_t DELSR[8];       /*!< (@ 0x00000280) DMAC Event Link Setting Register                           */
9135 
9136         struct
9137         {
9138             __IOM uint32_t DELS : 9;   /*!< [8..0] Event selection to DMAC Start request                              */
9139             uint32_t            : 7;
9140             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag for DMAC NOTE: Writing 1 to the
9141                                         *   IR flag is prohibited.                                                    */
9142             uint32_t : 15;
9143         } DELSR_b[8];
9144     };
9145     __IM uint32_t RESERVED16[24];
9146 
9147     union
9148     {
9149         __IOM uint32_t IELSR[96];      /*!< (@ 0x00000300) ICU Event Link Setting Register [0..95]                    */
9150 
9151         struct
9152         {
9153             __IOM uint32_t IELS : 9;   /*!< [8..0] ICU Event selection to NVICSet the number for the event
9154                                         *   signal to be linked .                                                     */
9155             uint32_t            : 7;
9156             __IOM uint32_t IR   : 1;   /*!< [16..16] Interrupt Status Flag                                            */
9157             uint32_t            : 7;
9158             __IOM uint32_t DTCE : 1;   /*!< [24..24] DTC Activation Enable                                            */
9159             uint32_t            : 7;
9160         } IELSR_b[96];
9161     };
9162 } R_ICU_Type;                          /*!< Size = 1152 (0x480)                                                       */
9163 
9164 /* =========================================================================================================================== */
9165 /* ================                                          R_IIC0                                           ================ */
9166 /* =========================================================================================================================== */
9167 
9168 /**
9169  * @brief I2C Bus Interface (R_IIC0)
9170  */
9171 
9172 typedef struct                         /*!< (@ 0x4009F000) R_IIC0 Structure                                           */
9173 {
9174     union
9175     {
9176         __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
9177 
9178         struct
9179         {
9180             __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
9181             __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
9182             __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
9183             __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
9184             __IOM uint8_t SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
9185             __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
9186             __IOM uint8_t IICRST : 1;  /*!< [6..6] I2C Bus Interface Internal ResetNote:If an internal reset
9187                                         *   is initiated using the IICRST bit for a bus hang-up occurred
9188                                         *   during communication with the master device in slave mode,
9189                                         *   the states may become different between the slave device
9190                                         *   and the master device (due to the difference in the bit
9191                                         *   counter information).                                                     */
9192             __IOM uint8_t ICE : 1;     /*!< [7..7] I2C Bus Interface Enable                                           */
9193         } ICCR1_b;
9194     };
9195 
9196     union
9197     {
9198         __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
9199 
9200         struct
9201         {
9202             uint8_t          : 1;
9203             __IOM uint8_t ST : 1;      /*!< [1..1] Start Condition Issuance RequestSet the ST bit to 1 (start
9204                                         *   condition issuance request) when the BBSY flag is set to
9205                                         *   0 (bus free state).                                                       */
9206             __IOM uint8_t RS : 1;      /*!< [2..2] Restart Condition Issuance RequestNote: Do not set the
9207                                         *   RS bit to 1 while issuing a stop condition.                               */
9208             __IOM uint8_t SP : 1;      /*!< [3..3] Stop Condition Issuance RequestNote: Writing to the SP
9209                                         *   bit is not possible while the setting of the BBSY flag
9210                                         *   is 0 (bus free state).Note: Do not set the SP bit to 1
9211                                         *   while a restart condition is being issued.                                */
9212             uint8_t            : 1;
9213             __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
9214             __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
9215             __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
9216         } ICCR2_b;
9217     };
9218 
9219     union
9220     {
9221         __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
9222 
9223         struct
9224         {
9225             __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
9226             __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect(This bit is read as 1.)                           */
9227             __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB
9228                                         *   / 2^CKS )                                                                 */
9229             __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
9230         } ICMR1_b;
9231     };
9232 
9233     union
9234     {
9235         __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
9236 
9237         struct
9238         {
9239             __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
9240             __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
9241             __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
9242             uint8_t            : 1;
9243             __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
9244             __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
9245         } ICMR2_b;
9246     };
9247 
9248     union
9249     {
9250         __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
9251 
9252         struct
9253         {
9254             __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Selection                                       */
9255             __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
9256             __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
9257             __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
9258             __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Selection                                     */
9259             __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAITNote: When the value of the WAIT bit is to be read,
9260                                         *   be sure to read the ICDRR beforehand.                                     */
9261             __IOM uint8_t SMBS : 1;    /*!< [7..7] SMBus/I2C Bus Selection                                            */
9262         } ICMR3_b;
9263     };
9264 
9265     union
9266     {
9267         __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
9268 
9269         struct
9270         {
9271             __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
9272             __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
9273             __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
9274             __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
9275             __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
9276             __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
9277             __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
9278             __IOM uint8_t FMPE  : 1;   /*!< [7..7] Fast-mode Plus Enable                                              */
9279         } ICFER_b;
9280     };
9281 
9282     union
9283     {
9284         __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
9285 
9286         struct
9287         {
9288             __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
9289             __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
9290             __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
9291             __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
9292             uint8_t             : 1;
9293             __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device-ID Address Detection Enable                                 */
9294             uint8_t             : 1;
9295             __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
9296         } ICSER_b;
9297     };
9298 
9299     union
9300     {
9301         __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
9302 
9303         struct
9304         {
9305             __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
9306             __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
9307             __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
9308             __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
9309             __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
9310             __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
9311             __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
9312             __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
9313         } ICIER_b;
9314     };
9315 
9316     union
9317     {
9318         __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
9319 
9320         struct
9321         {
9322             __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
9323             __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
9324             __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
9325             __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
9326             uint8_t            : 1;
9327             __IOM uint8_t DID  : 1;    /*!< [5..5] Device-ID Address Detection Flag                                   */
9328             uint8_t            : 1;
9329             __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
9330         } ICSR1_b;
9331     };
9332 
9333     union
9334     {
9335         __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
9336 
9337         struct
9338         {
9339             __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
9340             __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
9341             __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
9342             __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
9343             __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
9344             __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
9345             __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
9346             __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
9347         } ICSR2_b;
9348     };
9349     __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
9350 
9351     union
9352     {
9353         __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
9354 
9355         struct
9356         {
9357             __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period(Low-level period of SCL clock)           */
9358             uint8_t           : 3;
9359         } ICBRL_b;
9360     };
9361 
9362     union
9363     {
9364         __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
9365 
9366         struct
9367         {
9368             __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period(High-level period of SCL clock)         */
9369             uint8_t           : 3;
9370         } ICBRH_b;
9371     };
9372 
9373     union
9374     {
9375         __IOM uint8_t ICDRT;           /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
9376 
9377         struct
9378         {
9379             __IOM uint8_t ICDRT : 8;   /*!< [7..0] 8-bit read-write register that stores transmit data.               */
9380         } ICDRT_b;
9381     };
9382 
9383     union
9384     {
9385         __IM uint8_t ICDRR;            /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
9386 
9387         struct
9388         {
9389             __IM uint8_t ICDRR : 8;    /*!< [7..0] 8-bit register that stores the received data                       */
9390         } ICDRR_b;
9391     };
9392     __IM uint8_t RESERVED[2];
9393 
9394     union
9395     {
9396         __IOM uint8_t ICWUR;           /*!< (@ 0x00000016) I2C Bus Wake Up Unit Register                              */
9397 
9398         struct
9399         {
9400             __IOM uint8_t WUAFA : 1;   /*!< [0..0] Wakeup Analog Filter Additional Selection                          */
9401             uint8_t             : 3;
9402             __IOM uint8_t WUACK : 1;   /*!< [4..4] ACK bit for Wakeup Mode                                            */
9403             __IOM uint8_t WUF   : 1;   /*!< [5..5] Wakeup Event Occurrence Flag                                       */
9404             __IOM uint8_t WUIE  : 1;   /*!< [6..6] Wakeup Interrupt Request Enable                                    */
9405             __IOM uint8_t WUE   : 1;   /*!< [7..7] Wakeup Function Enable                                             */
9406         } ICWUR_b;
9407     };
9408 
9409     union
9410     {
9411         __IOM uint8_t ICWUR2;          /*!< (@ 0x00000017) I2C Bus Wake up Unit Register 2                            */
9412 
9413         struct
9414         {
9415             __IOM uint8_t WUSEN  : 1;  /*!< [0..0] Wake-up Function Synchronous Enable                                */
9416             __IM uint8_t  WUASYF : 1;  /*!< [1..1] Wake-up Function Asynchronous Operation Status Flag                */
9417             __IM uint8_t  WUSYF  : 1;  /*!< [2..2] Wake-up Function Synchronous Operation Status Flag                 */
9418             uint8_t              : 5;
9419         } ICWUR2_b;
9420     };
9421 } R_IIC0_Type;                         /*!< Size = 24 (0x18)                                                          */
9422 
9423 /* =========================================================================================================================== */
9424 /* ================                                          R_IWDT                                           ================ */
9425 /* =========================================================================================================================== */
9426 
9427 /**
9428  * @brief Independent Watchdog Timer (R_IWDT)
9429  */
9430 
9431 typedef struct                         /*!< (@ 0x40083200) R_IWDT Structure                                           */
9432 {
9433     union
9434     {
9435         __IOM uint8_t IWDTRR;          /*!< (@ 0x00000000) IWDT Refresh Register                                      */
9436 
9437         struct
9438         {
9439             __IOM uint8_t IWDTRR : 8;  /*!< [7..0] The counter is refreshed by writing 0x00 and then writing
9440                                         *   0xFF to this register.                                                    */
9441         } IWDTRR_b;
9442     };
9443     __IM uint8_t RESERVED;
9444 
9445     union
9446     {
9447         __IOM uint16_t IWDTCR;         /*!< (@ 0x00000002) IWDT Control Register                                      */
9448 
9449         struct
9450         {
9451             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
9452             uint16_t            : 2;
9453             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
9454             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
9455             uint16_t            : 2;
9456             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
9457             uint16_t            : 2;
9458         } IWDTCR_b;
9459     };
9460 
9461     union
9462     {
9463         __IOM uint16_t IWDTSR;          /*!< (@ 0x00000004) IWDT Status Register                                       */
9464 
9465         struct
9466         {
9467             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
9468             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
9469             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
9470         } IWDTSR_b;
9471     };
9472 
9473     union
9474     {
9475         __IOM uint8_t IWDTRCR;         /*!< (@ 0x00000006) IWDT Reset Control Register                                */
9476 
9477         struct
9478         {
9479             uint8_t               : 7;
9480             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
9481         } IWDTRCR_b;
9482     };
9483     __IM uint8_t RESERVED1;
9484 
9485     union
9486     {
9487         __IOM uint8_t IWDTCSTPR;       /*!< (@ 0x00000008) IWDT Count Stop Control Register                           */
9488 
9489         struct
9490         {
9491             uint8_t              : 7;
9492             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
9493         } IWDTCSTPR_b;
9494     };
9495     __IM uint8_t  RESERVED2;
9496     __IM uint16_t RESERVED3;
9497 } R_IWDT_Type;                         /*!< Size = 12 (0xc)                                                           */
9498 
9499 /* =========================================================================================================================== */
9500 /* ================                                          R_I3C0                                           ================ */
9501 /* =========================================================================================================================== */
9502 
9503 /**
9504  * @brief I3C Bus Interface (R_I3C0)
9505  */
9506 
9507 typedef struct                         /*!< (@ 0x4011F000) R_I3C0 Structure                                           */
9508 {
9509     union
9510     {
9511         __IOM uint32_t PRTS;           /*!< (@ 0x00000000) Protocol Selection Register                                */
9512 
9513         struct
9514         {
9515             __IOM uint32_t PRTMD : 1;  /*!< [0..0] Protocol Mode                                                      */
9516             uint32_t             : 31;
9517         } PRTS_b;
9518     };
9519     __IM uint32_t RESERVED[3];
9520 
9521     union
9522     {
9523         __IOM uint32_t CECTL;          /*!< (@ 0x00000010) Clock Enable Control Resisters                             */
9524 
9525         struct
9526         {
9527             __IOM uint32_t CLKE : 1;   /*!< [0..0] Clock Enable                                                       */
9528             uint32_t            : 31;
9529         } CECTL_b;
9530     };
9531 
9532     union
9533     {
9534         __IOM uint32_t BCTL;             /*!< (@ 0x00000014) Bus Control Register                                       */
9535 
9536         struct
9537         {
9538             __IOM uint32_t INCBA    : 1; /*!< [0..0] Include I3C Broadcast Address                                      */
9539             uint32_t                : 6;
9540             __IOM uint32_t BMDS     : 1; /*!< [7..7] Bus Mode Selection                                                 */
9541             __IOM uint32_t HJACKCTL : 1; /*!< [8..8] Hot-Join Acknowledge Control                                       */
9542             uint32_t                : 20;
9543             __IOM uint32_t ABT      : 1; /*!< [29..29] Abort                                                            */
9544             __IOM uint32_t RSM      : 1; /*!< [30..30] Resume                                                           */
9545             __IOM uint32_t BUSE     : 1; /*!< [31..31] Bus Enable                                                       */
9546         } BCTL_b;
9547     };
9548 
9549     union
9550     {
9551         __IOM uint32_t MSDVAD;         /*!< (@ 0x00000018) Master Device Address Register                             */
9552 
9553         struct
9554         {
9555             uint32_t              : 16;
9556             __IOM uint32_t MDYAD  : 7; /*!< [22..16] Master Dynamic Address                                           */
9557             uint32_t              : 8;
9558             __IOM uint32_t MDYADV : 1; /*!< [31..31] Master Dynamic Address Valid                                     */
9559         } MSDVAD_b;
9560     };
9561     __IM uint32_t RESERVED1;
9562 
9563     union
9564     {
9565         __IOM uint32_t RSTCTL;          /*!< (@ 0x00000020) Reset Control Register                                     */
9566 
9567         struct
9568         {
9569             __IOM uint32_t RI3CRST : 1; /*!< [0..0] I3C Software Reset                                                 */
9570             __IOM uint32_t CMDQRST : 1; /*!< [1..1] Command Queue Software Reset                                       */
9571             __IOM uint32_t RSPQRST : 1; /*!< [2..2] Response Queue Software Reset                                      */
9572             __IOM uint32_t TDBRST  : 1; /*!< [3..3] Transmit Data Buffer Software Reset                                */
9573             __IOM uint32_t RDBRST  : 1; /*!< [4..4] Receive Data Buffer Software Reset                                 */
9574             __IOM uint32_t IBIQRST : 1; /*!< [5..5] IBI Queue Software Reset                                           */
9575             __IOM uint32_t RSQRST  : 1; /*!< [6..6] Receive Status Queue Software Reset                                */
9576             uint32_t               : 9;
9577             __IOM uint32_t INTLRST : 1; /*!< [16..16] Internal Software Reset                                          */
9578             uint32_t               : 15;
9579         } RSTCTL_b;
9580     };
9581 
9582     union
9583     {
9584         __IOM uint32_t PRSST;          /*!< (@ 0x00000024) Present State Register                                     */
9585 
9586         struct
9587         {
9588             uint32_t              : 2;
9589             __IOM uint32_t CRMS   : 1; /*!< [2..2] Current Master                                                     */
9590             uint32_t              : 1;
9591             __IM uint32_t TRMD    : 1; /*!< [4..4] Transmit/Receive Mode                                              */
9592             uint32_t              : 2;
9593             __OM uint32_t PRSSTWP : 1; /*!< [7..7] Present State Write Protect                                        */
9594             uint32_t              : 24;
9595         } PRSST_b;
9596     };
9597     __IM uint32_t RESERVED2[2];
9598 
9599     union
9600     {
9601         __IOM uint32_t INST;           /*!< (@ 0x00000030) Internal Status Register                                   */
9602 
9603         struct
9604         {
9605             uint32_t            : 10;
9606             __IOM uint32_t INEF : 1;   /*!< [10..10] Internal Error Flag                                              */
9607             uint32_t            : 21;
9608         } INST_b;
9609     };
9610 
9611     union
9612     {
9613         __IOM uint32_t INSTE;          /*!< (@ 0x00000034) Internal Status Enable Register                            */
9614 
9615         struct
9616         {
9617             uint32_t            : 10;
9618             __IOM uint32_t INEE : 1;   /*!< [10..10] Internal Error Enable                                            */
9619             uint32_t            : 21;
9620         } INSTE_b;
9621     };
9622 
9623     union
9624     {
9625         __IOM uint32_t INIE;           /*!< (@ 0x00000038) Internal Interrupt Enable Register                         */
9626 
9627         struct
9628         {
9629             uint32_t             : 10;
9630             __IOM uint32_t INEIE : 1;  /*!< [10..10] Internal Error Interrupt Enable                                  */
9631             uint32_t             : 21;
9632         } INIE_b;
9633     };
9634 
9635     union
9636     {
9637         __IOM uint32_t INSTFC;         /*!< (@ 0x0000003C) Internal Status Force Register                             */
9638 
9639         struct
9640         {
9641             uint32_t            : 10;
9642             __OM uint32_t INEFC : 1;   /*!< [10..10] Internal Error Force                                             */
9643             uint32_t            : 21;
9644         } INSTFC_b;
9645     };
9646     __IM uint32_t RESERVED3;
9647 
9648     union
9649     {
9650         __IM uint32_t DVCT;            /*!< (@ 0x00000044) Device Characteristic Table Register                       */
9651 
9652         struct
9653         {
9654             uint32_t          : 19;
9655             __IM uint32_t IDX : 5;     /*!< [23..19] DCT Table Index                                                  */
9656             uint32_t          : 8;
9657         } DVCT_b;
9658     };
9659     __IM uint32_t RESERVED4[4];
9660 
9661     union
9662     {
9663         __IOM uint32_t IBINCTL;          /*!< (@ 0x00000058) IBI Notify Control Register                                */
9664 
9665         struct
9666         {
9667             __IOM uint32_t NRHJCTL  : 1; /*!< [0..0] Notify Rejected Hot-Join Control                                   */
9668             __IOM uint32_t NRMRCTL  : 1; /*!< [1..1] Notify Rejected Master Request Control                             */
9669             uint32_t                : 1;
9670             __IOM uint32_t NRSIRCTL : 1; /*!< [3..3] Notify Rejected Slave Interrupt Request Control                    */
9671             uint32_t                : 28;
9672         } IBINCTL_b;
9673     };
9674     __IM uint32_t RESERVED5;
9675 
9676     union
9677     {
9678         __IOM uint32_t BFCTL;          /*!< (@ 0x00000060) Bus Function Control Register                              */
9679 
9680         struct
9681         {
9682             __IOM uint32_t MALE   : 1; /*!< [0..0] Master Arbitration-Lost Detection Enable                           */
9683             __IOM uint32_t NALE   : 1; /*!< [1..1] NACK Transmission Arbitration-Lost Detection Enable                */
9684             __IOM uint32_t SALE   : 1; /*!< [2..2] Slave Arbitration-Lost Detection Enable                            */
9685             uint32_t              : 5;
9686             __IOM uint32_t SCSYNE : 1; /*!< [8..8] SCL Synchronous Circuit Enable                                     */
9687             uint32_t              : 3;
9688             __IOM uint32_t SMBS   : 1; /*!< [12..12] SMBus/I2C Bus Selection                                          */
9689             uint32_t              : 1;
9690             __IOM uint32_t FMPE   : 1; /*!< [14..14] Fast-mode Plus Enable                                            */
9691             __IOM uint32_t HSME   : 1; /*!< [15..15] High Speed Mode Enable                                           */
9692             uint32_t              : 16;
9693         } BFCTL_b;
9694     };
9695 
9696     union
9697     {
9698         __IOM uint32_t SVCTL;          /*!< (@ 0x00000064) Slave Control Register                                     */
9699 
9700         struct
9701         {
9702             __IOM uint32_t GCAE  : 1;  /*!< [0..0] General Call Address Enable                                        */
9703             uint32_t             : 4;
9704             __IOM uint32_t HSMCE : 1;  /*!< [5..5] Hs-mode Master Code Enable                                         */
9705             __IOM uint32_t DVIDE : 1;  /*!< [6..6] Device-ID Address Enable                                           */
9706             uint32_t             : 8;
9707             __IOM uint32_t HOAE  : 1;  /*!< [15..15] Host Address Enable                                              */
9708             __IOM uint32_t SVAEn : 1;  /*!< [16..16] Slave Address Enable n (n = 0)                                   */
9709             uint32_t             : 15;
9710         } SVCTL_b;
9711     };
9712     __IM uint32_t RESERVED6[2];
9713 
9714     union
9715     {
9716         __IOM uint32_t REFCKCTL;        /*!< (@ 0x00000070) Reference Clock Control Register                           */
9717 
9718         struct
9719         {
9720             __IOM uint32_t IREFCKS : 3; /*!< [2..0] Internal Reference Clock Selection                                 */
9721             uint32_t               : 29;
9722         } REFCKCTL_b;
9723     };
9724 
9725     union
9726     {
9727         __IOM uint32_t STDBR;          /*!< (@ 0x00000074) Standard Bit Rate Register                                 */
9728 
9729         struct
9730         {
9731             __IOM uint32_t SBRLO  : 8; /*!< [7..0] Count value of the Low-level period of SCL clock                   */
9732             __IOM uint32_t SBRHO  : 8; /*!< [15..8] Count value of the High-level period of SCL clock                 */
9733             __IOM uint32_t SBRLP  : 6; /*!< [21..16] Standard Bit Rate Low-level Period Push-Pull                     */
9734             uint32_t              : 2;
9735             __IOM uint32_t SBRHP  : 6; /*!< [29..24] Standard Bit Rate High-Level Period Push-Pull                    */
9736             uint32_t              : 1;
9737             __IOM uint32_t DSBRPO : 1; /*!< [31..31] Double the Standard Bit Rate Period for Open-Drain               */
9738         } STDBR_b;
9739     };
9740 
9741     union
9742     {
9743         __IOM uint32_t EXTBR;          /*!< (@ 0x00000078) Extended Bit Rate Register                                 */
9744 
9745         struct
9746         {
9747             __IOM uint32_t EBRLO : 8;  /*!< [7..0] Extended Bit Rate Low-Level Period Open-Drain                      */
9748             __IOM uint32_t EBRHO : 8;  /*!< [15..8] Extended Bit Rate High-Level Period Open-Drain                    */
9749             __IOM uint32_t EBRLP : 6;  /*!< [21..16] Extended Bit Rate Low-Level Period Push-Pull                     */
9750             uint32_t             : 2;
9751             __IOM uint32_t EBRHP : 6;  /*!< [29..24] Extended Bit Rate Low-Level Period Push-Pull                     */
9752             uint32_t             : 2;
9753         } EXTBR_b;
9754     };
9755 
9756     union
9757     {
9758         __IOM uint32_t BFRECDT;        /*!< (@ 0x0000007C) Bus Free Condition Detection Time Register                 */
9759 
9760         struct
9761         {
9762             __IOM uint32_t FRECYC : 9; /*!< [8..0] Bus Free Condition Detection Cycle                                 */
9763             uint32_t              : 23;
9764         } BFRECDT_b;
9765     };
9766 
9767     union
9768     {
9769         __IOM uint32_t BAVLCDT;        /*!< (@ 0x00000080) Bus Available Condition Detection Time Register            */
9770 
9771         struct
9772         {
9773             __IOM uint32_t AVLCYC : 9; /*!< [8..0] Bus Available Condition Detection Cycle                            */
9774             uint32_t              : 23;
9775         } BAVLCDT_b;
9776     };
9777 
9778     union
9779     {
9780         __IOM uint32_t BIDLCDT;         /*!< (@ 0x00000084) Bus Idle Condition Detection Time Register                 */
9781 
9782         struct
9783         {
9784             __IOM uint32_t IDLCYC : 18; /*!< [17..0] Bus Idle Condition Detection Cycle                                */
9785             uint32_t              : 14;
9786         } BIDLCDT_b;
9787     };
9788 
9789     union
9790     {
9791         __IOM uint32_t OUTCTL;         /*!< (@ 0x00000088) Output Control Register                                    */
9792 
9793         struct
9794         {
9795             __IOM uint32_t SDOC   : 1; /*!< [0..0] SDA Output Control                                                 */
9796             __IOM uint32_t SCOC   : 1; /*!< [1..1] SCL Output Control                                                 */
9797             __OM uint32_t  SOCWP  : 1; /*!< [2..2] SCL/SDA Output Control Write Protect                               */
9798             uint32_t              : 1;
9799             __IOM uint32_t EXCYC  : 1; /*!< [4..4] Extra SCL Clock Cycle Output                                       */
9800             uint32_t              : 3;
9801             __IOM uint32_t SDOD   : 3; /*!< [10..8] SDA Output Delay                                                  */
9802             uint32_t              : 4;
9803             __IOM uint32_t SDODCS : 1; /*!< [15..15] SDA Output Delay Clock Source Selection                          */
9804             uint32_t              : 16;
9805         } OUTCTL_b;
9806     };
9807 
9808     union
9809     {
9810         __IOM uint32_t INCTL;          /*!< (@ 0x0000008C) Input Control Register                                     */
9811 
9812         struct
9813         {
9814             __IOM uint32_t DNFS : 4;   /*!< [3..0] Digital Noise Filter Stage Selection                               */
9815             __IOM uint32_t DNFE : 1;   /*!< [4..4] Digital Noise Filter Circuit Enable                                */
9816             uint32_t            : 27;
9817         } INCTL_b;
9818     };
9819 
9820     union
9821     {
9822         __IOM uint32_t TMOCTL;         /*!< (@ 0x00000090) Timeout Control Register                                   */
9823 
9824         struct
9825         {
9826             __IOM uint32_t TODTS  : 2; /*!< [1..0] Timeout Detection Time Selection                                   */
9827             uint32_t              : 2;
9828             __IOM uint32_t TOLCTL : 1; /*!< [4..4] Timeout L Count Control                                            */
9829             __IOM uint32_t TOHCTL : 1; /*!< [5..5] Timeout H Count Control                                            */
9830             __IOM uint32_t TOMDS  : 2; /*!< [7..6] Timeout Operation Mode Selection                                   */
9831             uint32_t              : 24;
9832         } TMOCTL_b;
9833     };
9834     __IM uint32_t RESERVED7;
9835 
9836     union
9837     {
9838         __IOM uint32_t WUCTL;           /*!< (@ 0x00000098) Wake Up Unit Control Register                              */
9839 
9840         struct
9841         {
9842             __IOM uint32_t WUACKS  : 1; /*!< [0..0] Wake-Up Acknowledge Selection                                      */
9843             uint32_t               : 3;
9844             __IOM uint32_t WUANFS  : 1; /*!< [4..4] Wake-Up Analog Noise Filter Selection                              */
9845             uint32_t               : 1;
9846             __IOM uint32_t WUFSYNE : 1; /*!< [6..6] Wake-Up function PCLKA Synchronous Enable                          */
9847             __IOM uint32_t WUFE    : 1; /*!< [7..7] Wake-Up function Enable.                                           */
9848             uint32_t               : 24;
9849         } WUCTL_b;
9850     };
9851     __IM uint32_t RESERVED8;
9852 
9853     union
9854     {
9855         __IOM uint32_t ACKCTL;         /*!< (@ 0x000000A0) Acknowledge Control Register                               */
9856 
9857         struct
9858         {
9859             __IM uint32_t  ACKR   : 1; /*!< [0..0] Acknowledge Reception                                              */
9860             __IOM uint32_t ACKT   : 1; /*!< [1..1] Acknowledge Transmission                                           */
9861             __OM uint32_t  ACKTWP : 1; /*!< [2..2] ACKT Write Protect                                                 */
9862             uint32_t              : 29;
9863         } ACKCTL_b;
9864     };
9865 
9866     union
9867     {
9868         __IOM uint32_t SCSTRCTL;       /*!< (@ 0x000000A4) SCL Stretch Control Register                               */
9869 
9870         struct
9871         {
9872             __IOM uint32_t ACKTWE : 1; /*!< [0..0] Acknowledge Transmission Wait Enable                               */
9873             __IOM uint32_t RWE    : 1; /*!< [1..1] Receive Wait Enable                                                */
9874             uint32_t              : 30;
9875         } SCSTRCTL_b;
9876     };
9877     __IM uint32_t RESERVED9[2];
9878 
9879     union
9880     {
9881         __IOM uint32_t SCSTLCTL;        /*!< (@ 0x000000B0) SCL Stalling Control Register                              */
9882 
9883         struct
9884         {
9885             __IOM uint32_t STLCYC : 16; /*!< [15..0] Stalling Cycle                                                    */
9886             uint32_t              : 12;
9887             __IOM uint32_t AAPE   : 1;  /*!< [28..28] Assigend Address Phase Enable                                    */
9888             __IOM uint32_t TRAPE  : 1;  /*!< [29..29] Transition Phase Enable                                          */
9889             __IOM uint32_t PARPE  : 1;  /*!< [30..30] Parity Phase Enable                                              */
9890             __IOM uint32_t ACKPE  : 1;  /*!< [31..31] ACK phase Enable                                                 */
9891         } SCSTLCTL_b;
9892     };
9893     __IM uint32_t RESERVED10[3];
9894 
9895     union
9896     {
9897         __IOM uint32_t SVTDLG0;        /*!< (@ 0x000000C0) Slave Transfer Data Length Register 0                      */
9898 
9899         struct
9900         {
9901             uint32_t             : 16;
9902             __IOM uint32_t STDLG : 16; /*!< [31..16] Slave Transfer Data Length                                       */
9903         } SVTDLG0_b;
9904     };
9905     __IM uint32_t RESERVED11[31];
9906 
9907     union
9908     {
9909         __IOM uint32_t CNDCTL;         /*!< (@ 0x00000140) Condition Control Register                                 */
9910 
9911         struct
9912         {
9913             __IOM uint32_t STCND : 1;  /*!< [0..0] START (S) Condition Issuance                                       */
9914             __IOM uint32_t SRCND : 1;  /*!< [1..1] Repeated START (Sr) Condition Issuance                             */
9915             __IOM uint32_t SPCND : 1;  /*!< [2..2] STOP (P) Condition Issuance                                        */
9916             uint32_t             : 29;
9917         } CNDCTL_b;
9918     };
9919     __IM uint32_t  RESERVED12[3];
9920     __OM uint32_t  NCMDQP;             /*!< (@ 0x00000150) Normal Command Queue Port Register                         */
9921     __IM uint32_t  NRSPQP;             /*!< (@ 0x00000154) Normal Response Queue Port Register                        */
9922     __IOM uint32_t NTDTBP0;            /*!< (@ 0x00000158) Normal Transfer Data Buffer Port Register 0                */
9923     __IM uint32_t  RESERVED13[8];
9924     __IOM uint32_t NIBIQP;             /*!< (@ 0x0000017C) Normal IBI Queue Port Register                             */
9925     __IM uint32_t  NRSQP;              /*!< (@ 0x00000180) Normal Receive Status Queue Port Register                  */
9926     __IM uint32_t  RESERVED14[3];
9927 
9928     union
9929     {
9930         __IOM uint32_t NQTHCTL;         /*!< (@ 0x00000190) Normal Queue Threshold Control Register                    */
9931 
9932         struct
9933         {
9934             __IOM uint32_t CMDQTH  : 8; /*!< [7..0] Normal Command Ready Queue Threshold                               */
9935             __IOM uint32_t RSPQTH  : 8; /*!< [15..8] Normal Response Queue Threshold                                   */
9936             __IOM uint32_t IBIDSSZ : 8; /*!< [23..16] Normal IBI Data Segment Size                                     */
9937             __IOM uint32_t IBIQTH  : 8; /*!< [31..24] Normal IBI Queue Threshold                                       */
9938         } NQTHCTL_b;
9939     };
9940 
9941     union
9942     {
9943         __IOM uint32_t NTBTHCTL0;      /*!< (@ 0x00000194) Normal Transfer Data Buffer Threshold Control
9944                                         *                  Register 0                                                 */
9945 
9946         struct
9947         {
9948             __IOM uint32_t TXDBTH : 3; /*!< [2..0] Normal Transmit Data Buffer Threshold                              */
9949             uint32_t              : 5;
9950             __IOM uint32_t RXDBTH : 3; /*!< [10..8] Normal Receive Data Buffer Threshold                              */
9951             uint32_t              : 5;
9952             __IOM uint32_t TXSTTH : 3; /*!< [18..16] Normal Tx Start Threshold                                        */
9953             uint32_t              : 5;
9954             __IOM uint32_t RXSTTH : 3; /*!< [26..24] Normal Rx Start Threshold                                        */
9955             uint32_t              : 5;
9956         } NTBTHCTL0_b;
9957     };
9958     __IM uint32_t RESERVED15[10];
9959 
9960     union
9961     {
9962         __IOM uint32_t NRQTHCTL;       /*!< (@ 0x000001C0) Normal Receive Status Queue Threshold Control
9963                                         *                  Register                                                   */
9964 
9965         struct
9966         {
9967             __IOM uint32_t RSQTH : 8;  /*!< [7..0] Normal Receive Status Queue Threshold                              */
9968             uint32_t             : 24;
9969         } NRQTHCTL_b;
9970     };
9971     __IM uint32_t RESERVED16[3];
9972 
9973     union
9974     {
9975         __IOM uint32_t BST;             /*!< (@ 0x000001D0) Bus Status Register                                        */
9976 
9977         struct
9978         {
9979             __IOM uint32_t STCNDDF : 1; /*!< [0..0] START condition Detection Flag                                     */
9980             __IOM uint32_t SPCNDDF : 1; /*!< [1..1] STOP condition Detection Flag                                      */
9981             __IOM uint32_t HDREXDF : 1; /*!< [2..2] HDR Exit Pattern Detection Flag                                    */
9982             uint32_t               : 1;
9983             __IOM uint32_t NACKDF  : 1; /*!< [4..4] NACK Detection Flag                                                */
9984             uint32_t               : 3;
9985             __IOM uint32_t TENDF   : 1; /*!< [8..8] Transmit End Flag                                                  */
9986             uint32_t               : 7;
9987             __IOM uint32_t ALF     : 1; /*!< [16..16] Arbitration Lost Flag                                            */
9988             uint32_t               : 3;
9989             __IOM uint32_t TODF    : 1; /*!< [20..20] Timeout Detection Flag                                           */
9990             uint32_t               : 11;
9991         } BST_b;
9992     };
9993 
9994     union
9995     {
9996         __IOM uint32_t BSTE;            /*!< (@ 0x000001D4) Bus Status Enable Register                                 */
9997 
9998         struct
9999         {
10000             __IOM uint32_t STCNDDE : 1; /*!< [0..0] START condition Detection Enable                                   */
10001             __IOM uint32_t SPCNDDE : 1; /*!< [1..1] STOP condition Detection Enable                                    */
10002             __IOM uint32_t HDREXDE : 1; /*!< [2..2] HDR Exit Pattern Detection Enable                                  */
10003             uint32_t               : 1;
10004             __IOM uint32_t NACKDE  : 1; /*!< [4..4] NACK Detection Enable                                              */
10005             uint32_t               : 3;
10006             __IOM uint32_t TENDE   : 1; /*!< [8..8] Transmit End Enable                                                */
10007             uint32_t               : 7;
10008             __IOM uint32_t ALE     : 1; /*!< [16..16] Arbitration Lost Enable                                          */
10009             uint32_t               : 3;
10010             __IOM uint32_t TODE    : 1; /*!< [20..20] Timeout Detection Enable                                         */
10011             uint32_t               : 11;
10012         } BSTE_b;
10013     };
10014 
10015     union
10016     {
10017         __IOM uint32_t BIE;              /*!< (@ 0x000001D8) Bus Interrupt Enable Register                              */
10018 
10019         struct
10020         {
10021             __IOM uint32_t STCNDDIE : 1; /*!< [0..0] START condition Detection Interrupt Enable                         */
10022             __IOM uint32_t SPCNDDIE : 1; /*!< [1..1] STOP condition Detection Interrupt Enable                          */
10023             __IOM uint32_t HDREXDIE : 1; /*!< [2..2] HDR Exit Pattern Detection Interrupt Enable                        */
10024             uint32_t                : 1;
10025             __IOM uint32_t NACKDIE  : 1; /*!< [4..4] NACK Detection Interrupt Enable                                    */
10026             uint32_t                : 3;
10027             __IOM uint32_t TENDIE   : 1; /*!< [8..8] Transmit End Interrupt Enable                                      */
10028             uint32_t                : 7;
10029             __IOM uint32_t ALIE     : 1; /*!< [16..16] Arbitration Lost Interrupt Enable                                */
10030             uint32_t                : 3;
10031             __IOM uint32_t TODIE    : 1; /*!< [20..20] Timeout Detection Interrupt Enable                               */
10032             uint32_t                : 11;
10033         } BIE_b;
10034     };
10035 
10036     union
10037     {
10038         __IOM uint32_t BSTFC;           /*!< (@ 0x000001DC) Bus Status Force Register                                  */
10039 
10040         struct
10041         {
10042             __OM uint32_t STCNDDFC : 1; /*!< [0..0] START condition Detection Force                                    */
10043             __OM uint32_t SPCNDDFC : 1; /*!< [1..1] STOP condition Detection Force                                     */
10044             __OM uint32_t HDREXDFC : 1; /*!< [2..2] HDR Exit Pattern Detection Force                                   */
10045             uint32_t               : 1;
10046             __OM uint32_t NACKDFC  : 1; /*!< [4..4] NACK Detection Force                                               */
10047             uint32_t               : 3;
10048             __OM uint32_t TENDFC   : 1; /*!< [8..8] Transmit End Force                                                 */
10049             uint32_t               : 7;
10050             __OM uint32_t ALFC     : 1; /*!< [16..16] Arbitration Lost Force                                           */
10051             uint32_t               : 3;
10052             __OM uint32_t TODFC    : 1; /*!< [20..20] Timeout Detection Force                                          */
10053             uint32_t               : 11;
10054         } BSTFC_b;
10055     };
10056 
10057     union
10058     {
10059         __IOM uint32_t NTST;            /*!< (@ 0x000001E0) Normal Transfer Status Register                            */
10060 
10061         struct
10062         {
10063             __IOM uint32_t TDBEF0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Flag 0                           */
10064             __IOM uint32_t RDBFF0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Flag 0                             */
10065             __IOM uint32_t IBIQEFF : 1; /*!< [2..2] Normal IBI Queue Empty/Full Flag                                   */
10066             __IOM uint32_t CMDQEF  : 1; /*!< [3..3] Normal Command Queue Empty Flag                                    */
10067             __IOM uint32_t RSPQFF  : 1; /*!< [4..4] Normal Response Queue Full Flag                                    */
10068             __IOM uint32_t TABTF   : 1; /*!< [5..5] Normal Transfer Abort Flag                                         */
10069             uint32_t               : 3;
10070             __IOM uint32_t TEF     : 1; /*!< [9..9] Normal Transfer Error Flag                                         */
10071             uint32_t               : 10;
10072             __IOM uint32_t RSQFF   : 1; /*!< [20..20] Normal Receive Status Queue Full Flag                            */
10073             uint32_t               : 11;
10074         } NTST_b;
10075     };
10076 
10077     union
10078     {
10079         __IOM uint32_t NTSTE;           /*!< (@ 0x000001E4) Normal Transfer Status Enable Register                     */
10080 
10081         struct
10082         {
10083             __IOM uint32_t TDBEE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Enable 0                         */
10084             __IOM uint32_t RDBFE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Enable 0                           */
10085             __IOM uint32_t IBIQEFE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Enable                                 */
10086             __IOM uint32_t CMDQEE  : 1; /*!< [3..3] Normal Command Queue Empty Enable                                  */
10087             __IOM uint32_t RSPQFE  : 1; /*!< [4..4] Normal Response Queue Full Enable                                  */
10088             __IOM uint32_t TABTE   : 1; /*!< [5..5] Normal Transfer Abort Enable                                       */
10089             uint32_t               : 3;
10090             __IOM uint32_t TEE     : 1; /*!< [9..9] Normal Transfer Error Enable                                       */
10091             uint32_t               : 10;
10092             __IOM uint32_t RSQFE   : 1; /*!< [20..20] Normal Receive Status Queue Full Enable                          */
10093             uint32_t               : 11;
10094         } NTSTE_b;
10095     };
10096 
10097     union
10098     {
10099         __IOM uint32_t NTIE;             /*!< (@ 0x000001E8) Normal Transfer Interrupt Enable Register                  */
10100 
10101         struct
10102         {
10103             __IOM uint32_t TDBEIE0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Interrupt Enable 0               */
10104             __IOM uint32_t RDBFIE0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Interrupt Enable 0                 */
10105             __IOM uint32_t IBIQEFIE : 1; /*!< [2..2] Normal IBI Queue Empty/Full Interrupt Enable                       */
10106             __IOM uint32_t CMDQEIE  : 1; /*!< [3..3] Normal Command Queue Empty Interrupt Enable                        */
10107             __IOM uint32_t RSPQFIE  : 1; /*!< [4..4] Normal Response Queue Full Interrupt Enable                        */
10108             __IOM uint32_t TABTIE   : 1; /*!< [5..5] Normal Transfer Abort Interrupt Enable                             */
10109             uint32_t                : 3;
10110             __IOM uint32_t TEIE     : 1; /*!< [9..9] Normal Transfer Error Interrupt Enable                             */
10111             uint32_t                : 10;
10112             __IOM uint32_t RSQFIE   : 1; /*!< [20..20] Normal Receive Status Queue Full Interrupt Enable                */
10113             uint32_t                : 11;
10114         } NTIE_b;
10115     };
10116 
10117     union
10118     {
10119         __IOM uint32_t NTSTFC;          /*!< (@ 0x000001EC) Normal Transfer Status Force Register                      */
10120 
10121         struct
10122         {
10123             __OM uint32_t TDBEFC0  : 1; /*!< [0..0] Normal Transmit Data Buffer Empty Force 0                          */
10124             __OM uint32_t RDBFFC0  : 1; /*!< [1..1] Normal Receive Data Buffer Full Force 0                            */
10125             __OM uint32_t IBIQEFFC : 1; /*!< [2..2] Normal IBI Queue Empty/Full Force                                  */
10126             __OM uint32_t CMDQEFC  : 1; /*!< [3..3] Normal Command Queue Empty Force                                   */
10127             __OM uint32_t RSPQFFC  : 1; /*!< [4..4] Normal Response Queue Full Force                                   */
10128             __OM uint32_t TABTFC   : 1; /*!< [5..5] Normal Transfer Abort Force                                        */
10129             uint32_t               : 3;
10130             __OM uint32_t TEFC     : 1; /*!< [9..9] Normal Transfer Error Force                                        */
10131             uint32_t               : 10;
10132             __OM uint32_t RSQFFC   : 1; /*!< [20..20] Normal Receive Status Queue Full Force                           */
10133             uint32_t               : 11;
10134         } NTSTFC_b;
10135     };
10136     __IM uint32_t RESERVED17[8];
10137 
10138     union
10139     {
10140         __IM uint32_t BCST;            /*!< (@ 0x00000210) Bus Condition Status Register                              */
10141 
10142         struct
10143         {
10144             __IM uint32_t BFREF : 1;   /*!< [0..0] Bus Free Detection Flag                                            */
10145             __IM uint32_t BAVLF : 1;   /*!< [1..1] Bus Available Detection Flag                                       */
10146             __IM uint32_t BIDLF : 1;   /*!< [2..2] Bus Idle Detection Flag                                            */
10147             uint32_t            : 29;
10148         } BCST_b;
10149     };
10150 
10151     union
10152     {
10153         __IOM uint32_t SVST;           /*!< (@ 0x00000214) Slave Status Register                                      */
10154 
10155         struct
10156         {
10157             __IOM uint32_t GCAF  : 1;  /*!< [0..0] General Call Address Detection Flag                                */
10158             uint32_t             : 4;
10159             __IOM uint32_t HSMCF : 1;  /*!< [5..5] Hs-mode Master Code Detection Flag                                 */
10160             __IOM uint32_t DVIDF : 1;  /*!< [6..6] Device-ID Address Detection Flag                                   */
10161             uint32_t             : 8;
10162             __IOM uint32_t HOAF  : 1;  /*!< [15..15] Host Address Detection Flag                                      */
10163             __IOM uint32_t SVAFn : 1;  /*!< [16..16] Slave Address Detection Flag n (n = 0)                           */
10164             uint32_t             : 15;
10165         } SVST_b;
10166     };
10167 
10168     union
10169     {
10170         __IOM uint32_t WUST;            /*!< (@ 0x00000218) Wake Up Unit Control Register                              */
10171 
10172         struct
10173         {
10174             __IOM uint32_t WUASYNF : 1; /*!< [0..0] Wake-up function asynchronous operation status flag.               */
10175             uint32_t               : 31;
10176         } WUST_b;
10177     };
10178     __IM uint32_t RESERVED18[2];
10179 
10180     union
10181     {
10182         __IOM uint32_t DATBAS0;         /*!< (@ 0x00000224) Device Address Table Basic Register 0                      */
10183 
10184         struct
10185         {
10186             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10187             uint32_t               : 5;
10188             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10189             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10190             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10191             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10192             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10193             uint32_t               : 5;
10194             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10195             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10196         } DATBAS0_b;
10197     };
10198     __IM uint32_t RESERVED19;
10199 
10200     union
10201     {
10202         __IOM uint32_t DATBAS1;         /*!< (@ 0x0000022C) Device Address Table Basic Register 1                      */
10203 
10204         struct
10205         {
10206             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10207             uint32_t               : 5;
10208             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10209             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10210             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10211             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10212             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10213             uint32_t               : 5;
10214             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10215             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10216         } DATBAS1_b;
10217     };
10218     __IM uint32_t RESERVED20;
10219 
10220     union
10221     {
10222         __IOM uint32_t DATBAS2;         /*!< (@ 0x00000234) Device Address Table Basic Register 2                      */
10223 
10224         struct
10225         {
10226             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10227             uint32_t               : 5;
10228             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10229             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10230             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10231             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10232             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10233             uint32_t               : 5;
10234             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10235             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10236         } DATBAS2_b;
10237     };
10238     __IM uint32_t RESERVED21;
10239 
10240     union
10241     {
10242         __IOM uint32_t DATBAS3;         /*!< (@ 0x0000023C) Device Address Table Basic Register 3                      */
10243 
10244         struct
10245         {
10246             __IOM uint32_t DVSTAD  : 7; /*!< [6..0] Device Static Address                                              */
10247             uint32_t               : 5;
10248             __IOM uint32_t DVIBIPL : 1; /*!< [12..12] Device IBI Payload                                               */
10249             __IOM uint32_t DVSIRRJ : 1; /*!< [13..13] Device In-Band Slave Interrupt Request Reject                    */
10250             __IOM uint32_t DVMRRJ  : 1; /*!< [14..14] Device In-Band Master Request Reject                             */
10251             __IOM uint32_t DVIBITS : 1; /*!< [15..15] Device IBI Time-stamp                                            */
10252             __IOM uint32_t DVDYAD  : 8; /*!< [23..16] Device I3C Dynamic Address                                       */
10253             uint32_t               : 5;
10254             __IOM uint32_t DVNACK  : 2; /*!< [30..29] Device NACK Retry Count                                          */
10255             __IOM uint32_t DVTYP   : 1; /*!< [31..31] Device Type                                                      */
10256         } DATBAS3_b;
10257     };
10258     __IM uint32_t RESERVED22[24];
10259 
10260     union
10261     {
10262         __IOM uint32_t EXDATBAS;       /*!< (@ 0x000002A0) Extended Device Address Table Basic Register               */
10263 
10264         struct
10265         {
10266             __IOM uint32_t EDSTAD : 7; /*!< [6..0] Extended Device Static Address                                     */
10267             uint32_t              : 9;
10268             __IOM uint32_t EDDYAD : 8; /*!< [23..16] Extended Device I3C Dynamic Address                              */
10269             uint32_t              : 5;
10270             __IOM uint32_t EDNACK : 2; /*!< [30..29] Extended Device NACK Retry Count                                 */
10271             __IOM uint32_t EDTYP  : 1; /*!< [31..31] Extended Device Type                                             */
10272         } EXDATBAS_b;
10273     };
10274     __IM uint32_t RESERVED23[3];
10275 
10276     union
10277     {
10278         __IOM uint32_t SDATBAS0;         /*!< (@ 0x000002B0) Slave Device Address Table Basic Register 0                */
10279 
10280         struct
10281         {
10282             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10283             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10284             uint32_t               : 1;
10285             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10286             uint32_t               : 3;
10287             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10288             uint32_t               : 9;
10289         } SDATBAS0_b;
10290     };
10291 
10292     union
10293     {
10294         __IOM uint32_t SDATBAS1;         /*!< (@ 0x000002B4) Slave Device Address Table Basic Register 1                */
10295 
10296         struct
10297         {
10298             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10299             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10300             uint32_t               : 1;
10301             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10302             uint32_t               : 3;
10303             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10304             uint32_t               : 9;
10305         } SDATBAS1_b;
10306     };
10307 
10308     union
10309     {
10310         __IOM uint32_t SDATBAS2;         /*!< (@ 0x000002B8) Slave Device Address Table Basic Register 2                */
10311 
10312         struct
10313         {
10314             __IOM uint32_t SDSTAD  : 10; /*!< [9..0] Slave Device Static Address                                        */
10315             __IOM uint32_t SDADLS  : 1;  /*!< [10..10] Slave Device Address Length Selection                            */
10316             uint32_t               : 1;
10317             __IOM uint32_t SDIBIPL : 1;  /*!< [12..12] Slave Device IBI Payload                                         */
10318             uint32_t               : 3;
10319             __IOM uint32_t SDDYAD  : 7;  /*!< [22..16] Slave Device I3C Dynamic Address                                 */
10320             uint32_t               : 9;
10321         } SDATBAS2_b;
10322     };
10323     __IM uint32_t RESERVED24[5];
10324 
10325     union
10326     {
10327         __IOM uint32_t MSDCT0;         /*!< (@ 0x000002D0) Master Device Characteristic Table Register 0              */
10328 
10329         struct
10330         {
10331             uint32_t              : 8;
10332             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10333             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10334             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10335             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10336             uint32_t              : 2;
10337             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10338             uint32_t              : 16;
10339         } MSDCT0_b;
10340     };
10341 
10342     union
10343     {
10344         __IOM uint32_t MSDCT1;         /*!< (@ 0x000002D4) Master Device Characteristic Table Register 1              */
10345 
10346         struct
10347         {
10348             uint32_t              : 8;
10349             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10350             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10351             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10352             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10353             uint32_t              : 2;
10354             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10355             uint32_t              : 16;
10356         } MSDCT1_b;
10357     };
10358 
10359     union
10360     {
10361         __IOM uint32_t MSDCT2;         /*!< (@ 0x000002D8) Master Device Characteristic Table Register 2              */
10362 
10363         struct
10364         {
10365             uint32_t              : 8;
10366             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10367             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10368             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10369             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10370             uint32_t              : 2;
10371             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10372             uint32_t              : 16;
10373         } MSDCT2_b;
10374     };
10375 
10376     union
10377     {
10378         __IOM uint32_t MSDCT3;         /*!< (@ 0x000002DC) Master Device Characteristic Table Register 3              */
10379 
10380         struct
10381         {
10382             uint32_t              : 8;
10383             __IOM uint32_t RBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10384             __IOM uint32_t RBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10385             __IOM uint32_t RBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10386             __IOM uint32_t RBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10387             uint32_t              : 2;
10388             __IOM uint32_t RBCR76 : 2; /*!< [15..14] Device Role                                                      */
10389             uint32_t              : 16;
10390         } MSDCT3_b;
10391     };
10392     __IM uint32_t RESERVED25[16];
10393 
10394     union
10395     {
10396         __IOM uint32_t SVDCT;          /*!< (@ 0x00000320) Slave Device Characteristic Table Register                 */
10397 
10398         struct
10399         {
10400             __IOM uint32_t TDCR   : 8; /*!< [7..0] Transfar Device Characteristic Register                            */
10401             __IOM uint32_t TBCR0  : 1; /*!< [8..8] Max Data Speed Limitation                                          */
10402             __IOM uint32_t TBCR1  : 1; /*!< [9..9] IBI Request Capable                                                */
10403             __IOM uint32_t TBCR2  : 1; /*!< [10..10] IBI Payload                                                      */
10404             __IOM uint32_t TBCR3  : 1; /*!< [11..11] Offline Capable                                                  */
10405             uint32_t              : 2;
10406             __IOM uint32_t TBCR76 : 2; /*!< [15..14] Device Role                                                      */
10407             uint32_t              : 16;
10408         } SVDCT_b;
10409     };
10410     __IOM uint32_t SDCTPIDL;           /*!< (@ 0x00000324) Slave Device Characteristic Table Provisional
10411                                         *                  ID Low Register                                            */
10412     __IOM uint32_t SDCTPIDH;           /*!< (@ 0x00000328) Slave Device Characteristic Table Provisional
10413                                         *                  ID High Register                                           */
10414     __IM uint32_t RESERVED26;
10415 
10416     union
10417     {
10418         __IM uint32_t SVDVAD0;         /*!< (@ 0x00000330) Slave Device Address Register 0                            */
10419 
10420         struct
10421         {
10422             uint32_t             : 16;
10423             __IM uint32_t SVAD   : 10; /*!< [25..16] Slave Address                                                    */
10424             uint32_t             : 1;
10425             __IM uint32_t SADLG  : 1;  /*!< [27..27] Slave Address Length                                             */
10426             uint32_t             : 2;
10427             __IM uint32_t SSTADV : 1;  /*!< [30..30] Slave Static Address Valid                                       */
10428             __IM uint32_t SDYADV : 1;  /*!< [31..31] Slave Dynamic Address Valid                                      */
10429         } SVDVAD0_b;
10430     };
10431     __IM uint32_t RESERVED27[7];
10432 
10433     union
10434     {
10435         __IOM uint32_t CSECMD;         /*!< (@ 0x00000350) CCC Slave Events Command Register                          */
10436 
10437         struct
10438         {
10439             __IOM uint32_t SVIRQE : 1; /*!< [0..0] Slave Interrupt Requests Enable                                    */
10440             __IOM uint32_t MSRQE  : 1; /*!< [1..1] Mastership Requests Enable                                         */
10441             uint32_t              : 1;
10442             __IOM uint32_t HJEVE  : 1; /*!< [3..3] Hot-Join Event Enable                                              */
10443             uint32_t              : 28;
10444         } CSECMD_b;
10445     };
10446 
10447     union
10448     {
10449         __IOM uint32_t CEACTST;        /*!< (@ 0x00000354) CCC Enter Activity State Register                          */
10450 
10451         struct
10452         {
10453             __IOM uint32_t ACTST : 4;  /*!< [3..0] Activity State                                                     */
10454             uint32_t             : 28;
10455         } CEACTST_b;
10456     };
10457 
10458     union
10459     {
10460         __IOM uint32_t CMWLG;          /*!< (@ 0x00000358) CCC Max Write Length Register                              */
10461 
10462         struct
10463         {
10464             __IOM uint32_t MWLG : 16;  /*!< [15..0] Max Write Length                                                  */
10465             uint32_t            : 16;
10466         } CMWLG_b;
10467     };
10468 
10469     union
10470     {
10471         __IOM uint32_t CMRLG;           /*!< (@ 0x0000035C) CCC Max Read Length Register                               */
10472 
10473         struct
10474         {
10475             __IOM uint32_t MRLG   : 16; /*!< [15..0] Max Read Length                                                   */
10476             __IOM uint32_t IBIPSZ : 8;  /*!< [23..16] IBI Payload Size                                                 */
10477             uint32_t              : 8;
10478         } CMRLG_b;
10479     };
10480 
10481     union
10482     {
10483         __IM uint32_t CETSTMD;         /*!< (@ 0x00000360) CCC Enter Test Mode Register                               */
10484 
10485         struct
10486         {
10487             __IM uint32_t TSTMD : 8;   /*!< [7..0] Test Mode                                                          */
10488             uint32_t            : 24;
10489         } CETSTMD_b;
10490     };
10491 
10492     union
10493     {
10494         __IOM uint32_t CGDVST;         /*!< (@ 0x00000364) CCC Get Device Status Register                             */
10495 
10496         struct
10497         {
10498             __IOM uint32_t PNDINT : 4; /*!< [3..0] Pending Interrupt                                                  */
10499             uint32_t              : 1;
10500             __IOM uint32_t PRTE   : 1; /*!< [5..5] Protocol Error                                                     */
10501             __IOM uint32_t ACTMD  : 2; /*!< [7..6] Slave Device's current Activity Mode                               */
10502             __IOM uint32_t VDRSV  : 8; /*!< [15..8] Vendor Reserved                                                   */
10503             uint32_t              : 16;
10504         } CGDVST_b;
10505     };
10506 
10507     union
10508     {
10509         __IOM uint32_t CMDSPW;         /*!< (@ 0x00000368) CCC Max Data Speed W (Write) Register                      */
10510 
10511         struct
10512         {
10513             __IOM uint32_t MSWDR : 3;  /*!< [2..0] Maximum Sustained Write Data Rate                                  */
10514             uint32_t             : 29;
10515         } CMDSPW_b;
10516     };
10517 
10518     union
10519     {
10520         __IOM uint32_t CMDSPR;         /*!< (@ 0x0000036C) CCC Max Data Speed R (Read) Register                       */
10521 
10522         struct
10523         {
10524             __IOM uint32_t MSRDR  : 3; /*!< [2..0] Maximum Sustained Read Data Rate                                   */
10525             __IOM uint32_t CDTTIM : 3; /*!< [5..3] Clock to Data Turnaround Time (TSCO)                               */
10526             uint32_t              : 26;
10527         } CMDSPR_b;
10528     };
10529 
10530     union
10531     {
10532         __IOM uint32_t CMDSPT;          /*!< (@ 0x00000370) CCC Max Data Speed T (Turnaround) Register                 */
10533 
10534         struct
10535         {
10536             __IOM uint32_t MRTTIM : 24; /*!< [23..0] Maximum Read Turnaround Time                                      */
10537             uint32_t              : 7;
10538             __IOM uint32_t MRTE   : 1;  /*!< [31..31] Maximum Read Turnaround Time Enable                              */
10539         } CMDSPT_b;
10540     };
10541 
10542     union
10543     {
10544         __IOM uint32_t CETSM;          /*!< (@ 0x00000374) CCC Exchange Timing Support Information M (Mode)
10545                                         *                  Register                                                   */
10546 
10547         struct
10548         {
10549             uint32_t            : 8;
10550             __IOM uint32_t FREQ : 8;   /*!< [15..8] Frequency Byte                                                    */
10551             __IOM uint32_t INAC : 8;   /*!< [23..16] Inaccuracy Byte                                                  */
10552             uint32_t            : 8;
10553         } CETSM_b;
10554     };
10555     __IM uint32_t RESERVED28[2];
10556 
10557     union
10558     {
10559         __IOM uint32_t BITCNT;         /*!< (@ 0x00000380) Bit Count Register                                         */
10560 
10561         struct
10562         {
10563             __IOM uint32_t BCNT  : 5;  /*!< [4..0] Bit Counter                                                        */
10564             uint32_t             : 2;
10565             __OM uint32_t BCNTWP : 1;  /*!< [7..7] BCNT Write Protect                                                 */
10566             uint32_t             : 24;
10567         } BITCNT_b;
10568     };
10569     __IM uint32_t RESERVED29[4];
10570 
10571     union
10572     {
10573         __IM uint32_t NQSTLV;          /*!< (@ 0x00000394) Normal Queue Status Level Register                         */
10574 
10575         struct
10576         {
10577             __IM uint32_t CMDQFLV : 8; /*!< [7..0] Normal Command Queue Free Level                                    */
10578             __IM uint32_t RSPQLV  : 8; /*!< [15..8] Normal Response Queue Level                                       */
10579             __IM uint32_t IBIQLV  : 8; /*!< [23..16] Normal IBI Queue Level                                           */
10580             __IM uint32_t IBISCNT : 5; /*!< [28..24] Normal IBI Status Count                                          */
10581             uint32_t              : 3;
10582         } NQSTLV_b;
10583     };
10584 
10585     union
10586     {
10587         __IM uint32_t NDBSTLV0;        /*!< (@ 0x00000398) Normal Data Buffer Status Level Register                   */
10588 
10589         struct
10590         {
10591             __IM uint32_t TDBFLV : 8;  /*!< [7..0] Normal Transmit Data Buffer Free Level                             */
10592             __IM uint32_t RDBLV  : 8;  /*!< [15..8] Normal Receive Data Buffer Level                                  */
10593             uint32_t             : 16;
10594         } NDBSTLV0_b;
10595     };
10596     __IM uint32_t RESERVED30[9];
10597 
10598     union
10599     {
10600         __IM uint32_t NRSQSTLV;        /*!< (@ 0x000003C0) Normal Receive Status Queue Status Level Register          */
10601 
10602         struct
10603         {
10604             __IM uint32_t RSQLV : 8;   /*!< [7..0] Normal Receive Status Queue Level                                  */
10605             uint32_t            : 24;
10606         } NRSQSTLV_b;
10607     };
10608     __IM uint32_t RESERVED31[2];
10609 
10610     union
10611     {
10612         __IM uint32_t PRSTDBG;         /*!< (@ 0x000003CC) Present State Debug Register                               */
10613 
10614         struct
10615         {
10616             __IM uint32_t SCILV : 1;   /*!< [0..0] SCL Line Signal Level                                              */
10617             __IM uint32_t SDILV : 1;   /*!< [1..1] SDA Line Signal Level                                              */
10618             __IM uint32_t SCOLV : 1;   /*!< [2..2] SCL Output Level                                                   */
10619             __IM uint32_t SDOLV : 1;   /*!< [3..3] SDA Output Level                                                   */
10620             uint32_t            : 28;
10621         } PRSTDBG_b;
10622     };
10623 
10624     union
10625     {
10626         __IM uint32_t MSERRCNT;        /*!< (@ 0x000003D0) Master Error Counters Register                             */
10627 
10628         struct
10629         {
10630             __IM uint32_t M2ECNT : 8;  /*!< [7..0] M2 Error Counter                                                   */
10631             uint32_t             : 24;
10632         } MSERRCNT_b;
10633     };
10634 } R_I3C0_Type;                         /*!< Size = 980 (0x3d4)                                                        */
10635 
10636 /* =========================================================================================================================== */
10637 /* ================                                        R_MPU_MMPU                                         ================ */
10638 /* =========================================================================================================================== */
10639 
10640 /**
10641  * @brief Bus Master MPU (R_MPU_MMPU)
10642  */
10643 
10644 typedef struct                         /*!< (@ 0x40000000) R_MPU_MMPU Structure                                       */
10645 {
10646     union
10647     {
10648         __IOM uint16_t OAD;            /*!< (@ 0x00000000) MMPU Operation After Detection Register                    */
10649 
10650         struct
10651         {
10652             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
10653             uint16_t           : 7;
10654             __OM uint16_t KEY  : 8;    /*!< [15..8] Write Keyword The data written to these bits are not
10655                                         *   stored.                                                                   */
10656         } OAD_b;
10657     };
10658     __IM uint16_t RESERVED;
10659 
10660     union
10661     {
10662         __IOM uint16_t OADPT;           /*!< (@ 0x00000004) MMPU Operation After Detection Protect Register            */
10663 
10664         struct
10665         {
10666             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
10667             uint16_t               : 7;
10668             __OM uint16_t KEY      : 8; /*!< [15..8] Write Keyword The data written to these bits are not
10669                                          *   stored.                                                                   */
10670         } OADPT_b;
10671     };
10672     __IM uint16_t               RESERVED1;
10673     __IM uint32_t               RESERVED2[62];
10674     __IOM R_MPU_MMPU_GROUP_Type DMAC0;    /*!< (@ 0x00000100) DMAC0 MMPU Registers                                       */
10675     __IOM R_MPU_MMPU_GROUP_Type DMAC1;    /*!< (@ 0x00000300) DMAC1 MMPU Registers                                       */
10676     __IOM R_MPU_MMPU_GROUP_Type EDMAC;    /*!< (@ 0x00000500) EDMAC MMPU Registers                                       */
10677     __IOM R_MPU_MMPU_GROUP_Type GLCDC;    /*!< (@ 0x00000700) GLCDC MMPU Registers                                       */
10678     __IOM R_MPU_MMPU_GROUP_Type DRW;      /*!< (@ 0x00000900) DRW MMPU Registers                                         */
10679     __IOM R_MPU_MMPU_GROUP_Type MIPI_DSI; /*!< (@ 0x00000B00) MIPI_DSI MMPU Registers                                    */
10680     __IOM R_MPU_MMPU_GROUP_Type CEU;      /*!< (@ 0x00000D00) CEU MMPU Registers                                         */
10681     __IOM R_MPU_MMPU_GROUP_Type MIPI_CSI; /*!< (@ 0x00000F00) MIPI_CSI MMPU Registers                                    */
10682     __IOM R_MPU_MMPU_GROUP_Type NPU;      /*!< (@ 0x00001100) NPU MMPU Registers                                         */
10683 } R_MPU_MMPU_Type;                        /*!< Size = 4864 (0x1300)                                                      */
10684 
10685 /* =========================================================================================================================== */
10686 /* ================                                        R_MPU_SPMON                                        ================ */
10687 /* =========================================================================================================================== */
10688 
10689 /**
10690  * @brief CPU Stack Pointer Monitor (R_MPU_SPMON)
10691  */
10692 
10693 typedef struct                         /*!< (@ 0x40000D00) R_MPU_SPMON Structure                                      */
10694 {
10695     __IOM R_MPU_SPMON_SP_Type SP[2];   /*!< (@ 0x00000000) Stack Pointer Monitor                                      */
10696 } R_MPU_SPMON_Type;                    /*!< Size = 32 (0x20)                                                          */
10697 
10698 /* =========================================================================================================================== */
10699 /* ================                                          R_MSTP                                           ================ */
10700 /* =========================================================================================================================== */
10701 
10702 /**
10703  * @brief System-Module Stop (R_MSTP)
10704  */
10705 
10706 typedef struct                          /*!< (@ 0x40084000) R_MSTP Structure                                           */
10707 {
10708     union
10709     {
10710         __IOM uint32_t MSTPCRA;         /*!< (@ 0x00000000) Module Stop Control Register A                             */
10711 
10712         struct
10713         {
10714             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10715             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10716             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10717             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10718             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10719             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10720             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10721             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10722             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10723             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10724             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10725                                          *   usage.                                                                    */
10726             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10727                                          *   usage.                                                                    */
10728             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10729                                          *   usage.                                                                    */
10730             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10731                                          *   usage.                                                                    */
10732             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10733                                          *   usage.                                                                    */
10734             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10735                                          *   usage.                                                                    */
10736             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10737                                          *   usage.                                                                    */
10738             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10739                                          *   usage.                                                                    */
10740             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10741                                          *   usage.                                                                    */
10742             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10743                                          *   usage.                                                                    */
10744             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10745                                          *   usage.                                                                    */
10746             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10747                                          *   usage.                                                                    */
10748             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10749                                          *   usage.                                                                    */
10750             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10751                                          *   usage.                                                                    */
10752             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10753                                          *   usage.                                                                    */
10754             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10755                                          *   usage.                                                                    */
10756             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10757                                          *   usage.                                                                    */
10758             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10759                                          *   usage.                                                                    */
10760             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10761                                          *   usage.                                                                    */
10762             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10763                                          *   usage.                                                                    */
10764             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10765                                          *   usage.                                                                    */
10766             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10767                                          *   usage.                                                                    */
10768         } MSTPCRA_b;
10769     };
10770 
10771     union
10772     {
10773         __IOM uint32_t MSTPCRB;         /*!< (@ 0x00000004) Module Stop Control Register B                             */
10774 
10775         struct
10776         {
10777             __IOM uint32_t MSTPB0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10778             __IOM uint32_t MSTPB1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10779             __IOM uint32_t MSTPB2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10780             __IOM uint32_t MSTPB3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10781             __IOM uint32_t MSTPB4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10782             __IOM uint32_t MSTPB5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10783             __IOM uint32_t MSTPB6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10784             __IOM uint32_t MSTPB7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10785             __IOM uint32_t MSTPB8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10786             __IOM uint32_t MSTPB9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10787             __IOM uint32_t MSTPB10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10788                                          *   usage.                                                                    */
10789             __IOM uint32_t MSTPB11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10790                                          *   usage.                                                                    */
10791             __IOM uint32_t MSTPB12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10792                                          *   usage.                                                                    */
10793             __IOM uint32_t MSTPB13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10794                                          *   usage.                                                                    */
10795             __IOM uint32_t MSTPB14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10796                                          *   usage.                                                                    */
10797             __IOM uint32_t MSTPB15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10798                                          *   usage.                                                                    */
10799             __IOM uint32_t MSTPB16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10800                                          *   usage.                                                                    */
10801             __IOM uint32_t MSTPB17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10802                                          *   usage.                                                                    */
10803             __IOM uint32_t MSTPB18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10804                                          *   usage.                                                                    */
10805             __IOM uint32_t MSTPB19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10806                                          *   usage.                                                                    */
10807             __IOM uint32_t MSTPB20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10808                                          *   usage.                                                                    */
10809             __IOM uint32_t MSTPB21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10810                                          *   usage.                                                                    */
10811             __IOM uint32_t MSTPB22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10812                                          *   usage.                                                                    */
10813             __IOM uint32_t MSTPB23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10814                                          *   usage.                                                                    */
10815             __IOM uint32_t MSTPB24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10816                                          *   usage.                                                                    */
10817             __IOM uint32_t MSTPB25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10818                                          *   usage.                                                                    */
10819             __IOM uint32_t MSTPB26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10820                                          *   usage.                                                                    */
10821             __IOM uint32_t MSTPB27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10822                                          *   usage.                                                                    */
10823             __IOM uint32_t MSTPB28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10824                                          *   usage.                                                                    */
10825             __IOM uint32_t MSTPB29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10826                                          *   usage.                                                                    */
10827             __IOM uint32_t MSTPB30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10828                                          *   usage.                                                                    */
10829             __IOM uint32_t MSTPB31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10830                                          *   usage.                                                                    */
10831         } MSTPCRB_b;
10832     };
10833 
10834     union
10835     {
10836         __IOM uint32_t MSTPCRC;         /*!< (@ 0x00000008) Module Stop Control Register C                             */
10837 
10838         struct
10839         {
10840             __IOM uint32_t MSTPC0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10841             __IOM uint32_t MSTPC1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10842             __IOM uint32_t MSTPC2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10843             __IOM uint32_t MSTPC3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10844             __IOM uint32_t MSTPC4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10845             __IOM uint32_t MSTPC5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10846             __IOM uint32_t MSTPC6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10847             __IOM uint32_t MSTPC7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10848             __IOM uint32_t MSTPC8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10849             __IOM uint32_t MSTPC9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10850             __IOM uint32_t MSTPC10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10851                                          *   usage.                                                                    */
10852             __IOM uint32_t MSTPC11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10853                                          *   usage.                                                                    */
10854             __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10855                                          *   usage.                                                                    */
10856             __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10857                                          *   usage.                                                                    */
10858             __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10859                                          *   usage.                                                                    */
10860             __IOM uint32_t MSTPC15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10861                                          *   usage.                                                                    */
10862             __IOM uint32_t MSTPC16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10863                                          *   usage.                                                                    */
10864             __IOM uint32_t MSTPC17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10865                                          *   usage.                                                                    */
10866             __IOM uint32_t MSTPC18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10867                                          *   usage.                                                                    */
10868             __IOM uint32_t MSTPC19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10869                                          *   usage.                                                                    */
10870             __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10871                                          *   usage.                                                                    */
10872             __IOM uint32_t MSTPC21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10873                                          *   usage.                                                                    */
10874             __IOM uint32_t MSTPC22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10875                                          *   usage.                                                                    */
10876             __IOM uint32_t MSTPC23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10877                                          *   usage.                                                                    */
10878             __IOM uint32_t MSTPC24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10879                                          *   usage.                                                                    */
10880             __IOM uint32_t MSTPC25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10881                                          *   usage.                                                                    */
10882             __IOM uint32_t MSTPC26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10883                                          *   usage.                                                                    */
10884             __IOM uint32_t MSTPC27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10885                                          *   usage.                                                                    */
10886             __IOM uint32_t MSTPC28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10887                                          *   usage.                                                                    */
10888             __IOM uint32_t MSTPC29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10889                                          *   usage.                                                                    */
10890             __IOM uint32_t MSTPC30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10891                                          *   usage.                                                                    */
10892             __IOM uint32_t MSTPC31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10893                                          *   usage.                                                                    */
10894         } MSTPCRC_b;
10895     };
10896 
10897     union
10898     {
10899         __IOM uint32_t MSTPCRD;         /*!< (@ 0x0000000C) Module Stop Control Register D                             */
10900 
10901         struct
10902         {
10903             __IOM uint32_t MSTPD0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10904             __IOM uint32_t MSTPD1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10905             __IOM uint32_t MSTPD2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10906             __IOM uint32_t MSTPD3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10907             __IOM uint32_t MSTPD4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10908             __IOM uint32_t MSTPD5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10909             __IOM uint32_t MSTPD6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10910             __IOM uint32_t MSTPD7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10911             __IOM uint32_t MSTPD8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10912             __IOM uint32_t MSTPD9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10913             __IOM uint32_t MSTPD10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10914                                          *   usage.                                                                    */
10915             __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10916                                          *   usage.                                                                    */
10917             __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10918                                          *   usage.                                                                    */
10919             __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10920                                          *   usage.                                                                    */
10921             __IOM uint32_t MSTPD14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10922                                          *   usage.                                                                    */
10923             __IOM uint32_t MSTPD15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10924                                          *   usage.                                                                    */
10925             __IOM uint32_t MSTPD16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10926                                          *   usage.                                                                    */
10927             __IOM uint32_t MSTPD17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10928                                          *   usage.                                                                    */
10929             __IOM uint32_t MSTPD18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10930                                          *   usage.                                                                    */
10931             __IOM uint32_t MSTPD19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10932                                          *   usage.                                                                    */
10933             __IOM uint32_t MSTPD20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10934                                          *   usage.                                                                    */
10935             __IOM uint32_t MSTPD21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
10936                                          *   usage.                                                                    */
10937             __IOM uint32_t MSTPD22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
10938                                          *   usage.                                                                    */
10939             __IOM uint32_t MSTPD23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
10940                                          *   usage.                                                                    */
10941             __IOM uint32_t MSTPD24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
10942                                          *   usage.                                                                    */
10943             __IOM uint32_t MSTPD25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
10944                                          *   usage.                                                                    */
10945             __IOM uint32_t MSTPD26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
10946                                          *   usage.                                                                    */
10947             __IOM uint32_t MSTPD27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
10948                                          *   usage.                                                                    */
10949             __IOM uint32_t MSTPD28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
10950                                          *   usage.                                                                    */
10951             __IOM uint32_t MSTPD29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
10952                                          *   usage.                                                                    */
10953             __IOM uint32_t MSTPD30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
10954                                          *   usage.                                                                    */
10955             __IOM uint32_t MSTPD31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
10956                                          *   usage.                                                                    */
10957         } MSTPCRD_b;
10958     };
10959 
10960     union
10961     {
10962         union
10963         {
10964             __IOM uint32_t MSTPCRE;         /*!< (@ 0x00000010) Module Stop Control Register E                             */
10965 
10966             struct
10967             {
10968                 __IOM uint32_t MSTPE0  : 1; /*!< [0..0] Module stop bit 0. See device hardware manual for usage.           */
10969                 __IOM uint32_t MSTPE1  : 1; /*!< [1..1] Module stop bit 1. See device hardware manual for usage.           */
10970                 __IOM uint32_t MSTPE2  : 1; /*!< [2..2] Module stop bit 2. See device hardware manual for usage.           */
10971                 __IOM uint32_t MSTPE3  : 1; /*!< [3..3] Module stop bit 3. See device hardware manual for usage.           */
10972                 __IOM uint32_t MSTPE4  : 1; /*!< [4..4] Module stop bit 4. See device hardware manual for usage.           */
10973                 __IOM uint32_t MSTPE5  : 1; /*!< [5..5] Module stop bit 5. See device hardware manual for usage.           */
10974                 __IOM uint32_t MSTPE6  : 1; /*!< [6..6] Module stop bit 6. See device hardware manual for usage.           */
10975                 __IOM uint32_t MSTPE7  : 1; /*!< [7..7] Module stop bit 7. See device hardware manual for usage.           */
10976                 __IOM uint32_t MSTPE8  : 1; /*!< [8..8] Module stop bit 8. See device hardware manual for usage.           */
10977                 __IOM uint32_t MSTPE9  : 1; /*!< [9..9] Module stop bit 9. See device hardware manual for usage.           */
10978                 __IOM uint32_t MSTPE10 : 1; /*!< [10..10] Module stop bit 10. See device hardware manual for
10979                                              *   usage.                                                                    */
10980                 __IOM uint32_t MSTPE11 : 1; /*!< [11..11] Module stop bit 11. See device hardware manual for
10981                                              *   usage.                                                                    */
10982                 __IOM uint32_t MSTPE12 : 1; /*!< [12..12] Module stop bit 12. See device hardware manual for
10983                                              *   usage.                                                                    */
10984                 __IOM uint32_t MSTPE13 : 1; /*!< [13..13] Module stop bit 13. See device hardware manual for
10985                                              *   usage.                                                                    */
10986                 __IOM uint32_t MSTPE14 : 1; /*!< [14..14] Module stop bit 14. See device hardware manual for
10987                                              *   usage.                                                                    */
10988                 __IOM uint32_t MSTPE15 : 1; /*!< [15..15] Module stop bit 15. See device hardware manual for
10989                                              *   usage.                                                                    */
10990                 __IOM uint32_t MSTPE16 : 1; /*!< [16..16] Module stop bit 16. See device hardware manual for
10991                                              *   usage.                                                                    */
10992                 __IOM uint32_t MSTPE17 : 1; /*!< [17..17] Module stop bit 17. See device hardware manual for
10993                                              *   usage.                                                                    */
10994                 __IOM uint32_t MSTPE18 : 1; /*!< [18..18] Module stop bit 18. See device hardware manual for
10995                                              *   usage.                                                                    */
10996                 __IOM uint32_t MSTPE19 : 1; /*!< [19..19] Module stop bit 19. See device hardware manual for
10997                                              *   usage.                                                                    */
10998                 __IOM uint32_t MSTPE20 : 1; /*!< [20..20] Module stop bit 20. See device hardware manual for
10999                                              *   usage.                                                                    */
11000                 __IOM uint32_t MSTPE21 : 1; /*!< [21..21] Module stop bit 21. See device hardware manual for
11001                                              *   usage.                                                                    */
11002                 __IOM uint32_t MSTPE22 : 1; /*!< [22..22] Module stop bit 22. See device hardware manual for
11003                                              *   usage.                                                                    */
11004                 __IOM uint32_t MSTPE23 : 1; /*!< [23..23] Module stop bit 23. See device hardware manual for
11005                                              *   usage.                                                                    */
11006                 __IOM uint32_t MSTPE24 : 1; /*!< [24..24] Module stop bit 24. See device hardware manual for
11007                                              *   usage.                                                                    */
11008                 __IOM uint32_t MSTPE25 : 1; /*!< [25..25] Module stop bit 25. See device hardware manual for
11009                                              *   usage.                                                                    */
11010                 __IOM uint32_t MSTPE26 : 1; /*!< [26..26] Module stop bit 26. See device hardware manual for
11011                                              *   usage.                                                                    */
11012                 __IOM uint32_t MSTPE27 : 1; /*!< [27..27] Module stop bit 27. See device hardware manual for
11013                                              *   usage.                                                                    */
11014                 __IOM uint32_t MSTPE28 : 1; /*!< [28..28] Module stop bit 28. See device hardware manual for
11015                                              *   usage.                                                                    */
11016                 __IOM uint32_t MSTPE29 : 1; /*!< [29..29] Module stop bit 29. See device hardware manual for
11017                                              *   usage.                                                                    */
11018                 __IOM uint32_t MSTPE30 : 1; /*!< [30..30] Module stop bit 30. See device hardware manual for
11019                                              *   usage.                                                                    */
11020                 __IOM uint32_t MSTPE31 : 1; /*!< [31..31] Module stop bit 31. See device hardware manual for
11021                                              *   usage.                                                                    */
11022             } MSTPCRE_b;
11023         };
11024 
11025         union
11026         {
11027             __IOM uint16_t LSMRWDIS;         /*!< (@ 0x00000010) Low Speed Module R/W Disable Control Register              */
11028 
11029             struct
11030             {
11031                 __IOM uint16_t RTCRWDIS : 1; /*!< [0..0] RTC Register R/W Enable Control                                    */
11032                 __IOM uint16_t WDTDIS   : 1; /*!< [1..1] WDT Operate Clock Control                                          */
11033                 __IOM uint16_t IWDTIDS  : 1; /*!< [2..2] IWDT Register Clock Control                                        */
11034                 uint16_t                : 4;
11035                 __IOM uint16_t WREN     : 1; /*!< [7..7] Write Enable for bits [2:0]                                        */
11036                 __OM uint16_t  PRKEY    : 8; /*!< [15..8] LSMRWDIS Key Code                                                 */
11037             } LSMRWDIS_b;
11038         };
11039     };
11040 } R_MSTP_Type;                               /*!< Size = 20 (0x14)                                                          */
11041 
11042 /* =========================================================================================================================== */
11043 /* ================                                          R_PORT0                                          ================ */
11044 /* =========================================================================================================================== */
11045 
11046 /**
11047  * @brief I/O Ports (R_PORT0)
11048  */
11049 
11050 typedef struct                         /*!< (@ 0x40080000) R_PORT0 Structure                                          */
11051 {
11052     union
11053     {
11054         union
11055         {
11056             __IOM uint32_t PCNTR1;        /*!< (@ 0x00000000) Port Control Register 1                                    */
11057 
11058             struct
11059             {
11060                 __IOM uint32_t PDR  : 16; /*!< [15..0] Pmn Direction                                                     */
11061                 __IOM uint32_t PODR : 16; /*!< [31..16] Pmn Output Data                                                  */
11062             } PCNTR1_b;
11063         };
11064 
11065         struct
11066         {
11067             union
11068             {
11069                 __IOM uint16_t PODR;           /*!< (@ 0x00000000) Output data register                                       */
11070 
11071                 struct
11072                 {
11073                     __IOM uint16_t PODR0  : 1; /*!< [0..0] Pmn Output Data                                                    */
11074                     __IOM uint16_t PODR1  : 1; /*!< [1..1] Pmn Output Data                                                    */
11075                     __IOM uint16_t PODR2  : 1; /*!< [2..2] Pmn Output Data                                                    */
11076                     __IOM uint16_t PODR3  : 1; /*!< [3..3] Pmn Output Data                                                    */
11077                     __IOM uint16_t PODR4  : 1; /*!< [4..4] Pmn Output Data                                                    */
11078                     __IOM uint16_t PODR5  : 1; /*!< [5..5] Pmn Output Data                                                    */
11079                     __IOM uint16_t PODR6  : 1; /*!< [6..6] Pmn Output Data                                                    */
11080                     __IOM uint16_t PODR7  : 1; /*!< [7..7] Pmn Output Data                                                    */
11081                     __IOM uint16_t PODR8  : 1; /*!< [8..8] Pmn Output Data                                                    */
11082                     __IOM uint16_t PODR9  : 1; /*!< [9..9] Pmn Output Data                                                    */
11083                     __IOM uint16_t PODR10 : 1; /*!< [10..10] Pmn Output Data                                                  */
11084                     __IOM uint16_t PODR11 : 1; /*!< [11..11] Pmn Output Data                                                  */
11085                     __IOM uint16_t PODR12 : 1; /*!< [12..12] Pmn Output Data                                                  */
11086                     __IOM uint16_t PODR13 : 1; /*!< [13..13] Pmn Output Data                                                  */
11087                     __IOM uint16_t PODR14 : 1; /*!< [14..14] Pmn Output Data                                                  */
11088                     __IOM uint16_t PODR15 : 1; /*!< [15..15] Pmn Output Data                                                  */
11089                 } PODR_b;
11090             };
11091 
11092             union
11093             {
11094                 __IOM uint16_t PDR;           /*!< (@ 0x00000002) Data direction register                                    */
11095 
11096                 struct
11097                 {
11098                     __IOM uint16_t PDR0  : 1; /*!< [0..0] Pmn Direction                                                      */
11099                     __IOM uint16_t PDR1  : 1; /*!< [1..1] Pmn Direction                                                      */
11100                     __IOM uint16_t PDR2  : 1; /*!< [2..2] Pmn Direction                                                      */
11101                     __IOM uint16_t PDR3  : 1; /*!< [3..3] Pmn Direction                                                      */
11102                     __IOM uint16_t PDR4  : 1; /*!< [4..4] Pmn Direction                                                      */
11103                     __IOM uint16_t PDR5  : 1; /*!< [5..5] Pmn Direction                                                      */
11104                     __IOM uint16_t PDR6  : 1; /*!< [6..6] Pmn Direction                                                      */
11105                     __IOM uint16_t PDR7  : 1; /*!< [7..7] Pmn Direction                                                      */
11106                     __IOM uint16_t PDR8  : 1; /*!< [8..8] Pmn Direction                                                      */
11107                     __IOM uint16_t PDR9  : 1; /*!< [9..9] Pmn Direction                                                      */
11108                     __IOM uint16_t PDR10 : 1; /*!< [10..10] Pmn Direction                                                    */
11109                     __IOM uint16_t PDR11 : 1; /*!< [11..11] Pmn Direction                                                    */
11110                     __IOM uint16_t PDR12 : 1; /*!< [12..12] Pmn Direction                                                    */
11111                     __IOM uint16_t PDR13 : 1; /*!< [13..13] Pmn Direction                                                    */
11112                     __IOM uint16_t PDR14 : 1; /*!< [14..14] Pmn Direction                                                    */
11113                     __IOM uint16_t PDR15 : 1; /*!< [15..15] Pmn Direction                                                    */
11114                 } PDR_b;
11115             };
11116         };
11117     };
11118 
11119     union
11120     {
11121         union
11122         {
11123             __IM uint32_t PCNTR2;        /*!< (@ 0x00000004) Port Control Register 2                                    */
11124 
11125             struct
11126             {
11127                 __IM uint32_t PIDR : 16; /*!< [15..0] Pmn Input Data                                                    */
11128                 __IM uint32_t EIDR : 16; /*!< [31..16] Pmn Event Input Data                                             */
11129             } PCNTR2_b;
11130         };
11131 
11132         struct
11133         {
11134             union
11135             {
11136                 __IM uint16_t EIDR;           /*!< (@ 0x00000004) Event input data register                                  */
11137 
11138                 struct
11139                 {
11140                     __IM uint16_t EIDR0  : 1; /*!< [0..0] Pmn Event Input Data                                               */
11141                     __IM uint16_t EIDR1  : 1; /*!< [1..1] Pmn Event Input Data                                               */
11142                     __IM uint16_t EIDR2  : 1; /*!< [2..2] Pmn Event Input Data                                               */
11143                     __IM uint16_t EIDR3  : 1; /*!< [3..3] Pmn Event Input Data                                               */
11144                     __IM uint16_t EIDR4  : 1; /*!< [4..4] Pmn Event Input Data                                               */
11145                     __IM uint16_t EIDR5  : 1; /*!< [5..5] Pmn Event Input Data                                               */
11146                     __IM uint16_t EIDR6  : 1; /*!< [6..6] Pmn Event Input Data                                               */
11147                     __IM uint16_t EIDR7  : 1; /*!< [7..7] Pmn Event Input Data                                               */
11148                     __IM uint16_t EIDR8  : 1; /*!< [8..8] Pmn Event Input Data                                               */
11149                     __IM uint16_t EIDR9  : 1; /*!< [9..9] Pmn Event Input Data                                               */
11150                     __IM uint16_t EIDR10 : 1; /*!< [10..10] Pmn Event Input Data                                             */
11151                     __IM uint16_t EIDR11 : 1; /*!< [11..11] Pmn Event Input Data                                             */
11152                     __IM uint16_t EIDR12 : 1; /*!< [12..12] Pmn Event Input Data                                             */
11153                     __IM uint16_t EIDR13 : 1; /*!< [13..13] Pmn Event Input Data                                             */
11154                     __IM uint16_t EIDR14 : 1; /*!< [14..14] Pmn Event Input Data                                             */
11155                     __IM uint16_t EIDR15 : 1; /*!< [15..15] Pmn Event Input Data                                             */
11156                 } EIDR_b;
11157             };
11158 
11159             union
11160             {
11161                 __IM uint16_t PIDR;           /*!< (@ 0x00000006) Input data register                                        */
11162 
11163                 struct
11164                 {
11165                     __IM uint16_t PIDR0  : 1; /*!< [0..0] Pmn Input Data                                                     */
11166                     __IM uint16_t PIDR1  : 1; /*!< [1..1] Pmn Input Data                                                     */
11167                     __IM uint16_t PIDR2  : 1; /*!< [2..2] Pmn Input Data                                                     */
11168                     __IM uint16_t PIDR3  : 1; /*!< [3..3] Pmn Input Data                                                     */
11169                     __IM uint16_t PIDR4  : 1; /*!< [4..4] Pmn Input Data                                                     */
11170                     __IM uint16_t PIDR5  : 1; /*!< [5..5] Pmn Input Data                                                     */
11171                     __IM uint16_t PIDR6  : 1; /*!< [6..6] Pmn Input Data                                                     */
11172                     __IM uint16_t PIDR7  : 1; /*!< [7..7] Pmn Input Data                                                     */
11173                     __IM uint16_t PIDR8  : 1; /*!< [8..8] Pmn Input Data                                                     */
11174                     __IM uint16_t PIDR9  : 1; /*!< [9..9] Pmn Input Data                                                     */
11175                     __IM uint16_t PIDR10 : 1; /*!< [10..10] Pmn Input Data                                                   */
11176                     __IM uint16_t PIDR11 : 1; /*!< [11..11] Pmn Input Data                                                   */
11177                     __IM uint16_t PIDR12 : 1; /*!< [12..12] Pmn Input Data                                                   */
11178                     __IM uint16_t PIDR13 : 1; /*!< [13..13] Pmn Input Data                                                   */
11179                     __IM uint16_t PIDR14 : 1; /*!< [14..14] Pmn Input Data                                                   */
11180                     __IM uint16_t PIDR15 : 1; /*!< [15..15] Pmn Input Data                                                   */
11181                 } PIDR_b;
11182             };
11183         };
11184     };
11185 
11186     union
11187     {
11188         union
11189         {
11190             __OM uint32_t PCNTR3;        /*!< (@ 0x00000008) Port Control Register 3                                    */
11191 
11192             struct
11193             {
11194                 __OM uint32_t POSR : 16; /*!< [15..0] Pmn Output Set                                                    */
11195                 __OM uint32_t PORR : 16; /*!< [31..16] Pmn Output Reset                                                 */
11196             } PCNTR3_b;
11197         };
11198 
11199         struct
11200         {
11201             union
11202             {
11203                 __OM uint16_t PORR;           /*!< (@ 0x00000008) Output set register                                        */
11204 
11205                 struct
11206                 {
11207                     __OM uint16_t PORR0  : 1; /*!< [0..0] Pmn Output Reset                                                   */
11208                     __OM uint16_t PORR1  : 1; /*!< [1..1] Pmn Output Reset                                                   */
11209                     __OM uint16_t PORR2  : 1; /*!< [2..2] Pmn Output Reset                                                   */
11210                     __OM uint16_t PORR3  : 1; /*!< [3..3] Pmn Output Reset                                                   */
11211                     __OM uint16_t PORR4  : 1; /*!< [4..4] Pmn Output Reset                                                   */
11212                     __OM uint16_t PORR5  : 1; /*!< [5..5] Pmn Output Reset                                                   */
11213                     __OM uint16_t PORR6  : 1; /*!< [6..6] Pmn Output Reset                                                   */
11214                     __OM uint16_t PORR7  : 1; /*!< [7..7] Pmn Output Reset                                                   */
11215                     __OM uint16_t PORR8  : 1; /*!< [8..8] Pmn Output Reset                                                   */
11216                     __OM uint16_t PORR9  : 1; /*!< [9..9] Pmn Output Reset                                                   */
11217                     __OM uint16_t PORR10 : 1; /*!< [10..10] Pmn Output Reset                                                 */
11218                     __OM uint16_t PORR11 : 1; /*!< [11..11] Pmn Output Reset                                                 */
11219                     __OM uint16_t PORR12 : 1; /*!< [12..12] Pmn Output Reset                                                 */
11220                     __OM uint16_t PORR13 : 1; /*!< [13..13] Pmn Output Reset                                                 */
11221                     __OM uint16_t PORR14 : 1; /*!< [14..14] Pmn Output Reset                                                 */
11222                     __OM uint16_t PORR15 : 1; /*!< [15..15] Pmn Output Reset                                                 */
11223                 } PORR_b;
11224             };
11225 
11226             union
11227             {
11228                 __OM uint16_t POSR;           /*!< (@ 0x0000000A) Output reset register                                      */
11229 
11230                 struct
11231                 {
11232                     __OM uint16_t POSR0  : 1; /*!< [0..0] Pmn Output Set                                                     */
11233                     __OM uint16_t POSR1  : 1; /*!< [1..1] Pmn Output Set                                                     */
11234                     __OM uint16_t POSR2  : 1; /*!< [2..2] Pmn Output Set                                                     */
11235                     __OM uint16_t POSR3  : 1; /*!< [3..3] Pmn Output Set                                                     */
11236                     __OM uint16_t POSR4  : 1; /*!< [4..4] Pmn Output Set                                                     */
11237                     __OM uint16_t POSR5  : 1; /*!< [5..5] Pmn Output Set                                                     */
11238                     __OM uint16_t POSR6  : 1; /*!< [6..6] Pmn Output Set                                                     */
11239                     __OM uint16_t POSR7  : 1; /*!< [7..7] Pmn Output Set                                                     */
11240                     __OM uint16_t POSR8  : 1; /*!< [8..8] Pmn Output Set                                                     */
11241                     __OM uint16_t POSR9  : 1; /*!< [9..9] Pmn Output Set                                                     */
11242                     __OM uint16_t POSR10 : 1; /*!< [10..10] Pmn Output Set                                                   */
11243                     __OM uint16_t POSR11 : 1; /*!< [11..11] Pmn Output Set                                                   */
11244                     __OM uint16_t POSR12 : 1; /*!< [12..12] Pmn Output Set                                                   */
11245                     __OM uint16_t POSR13 : 1; /*!< [13..13] Pmn Output Set                                                   */
11246                     __OM uint16_t POSR14 : 1; /*!< [14..14] Pmn Output Set                                                   */
11247                     __OM uint16_t POSR15 : 1; /*!< [15..15] Pmn Output Set                                                   */
11248                 } POSR_b;
11249             };
11250         };
11251     };
11252 
11253     union
11254     {
11255         union
11256         {
11257             __IOM uint32_t PCNTR4;        /*!< (@ 0x0000000C) Port Control Register 4                                    */
11258 
11259             struct
11260             {
11261                 __IOM uint32_t EOSR : 16; /*!< [15..0] Pmn Event Output Set                                              */
11262                 __IOM uint32_t EORR : 16; /*!< [31..16] Pmn Event Output Reset                                           */
11263             } PCNTR4_b;
11264         };
11265 
11266         struct
11267         {
11268             union
11269             {
11270                 __IOM uint16_t EORR;           /*!< (@ 0x0000000C) Event output set register                                  */
11271 
11272                 struct
11273                 {
11274                     __IOM uint16_t EORR0  : 1; /*!< [0..0] Pmn Event Output Reset                                             */
11275                     __IOM uint16_t EORR1  : 1; /*!< [1..1] Pmn Event Output Reset                                             */
11276                     __IOM uint16_t EORR2  : 1; /*!< [2..2] Pmn Event Output Reset                                             */
11277                     __IOM uint16_t EORR3  : 1; /*!< [3..3] Pmn Event Output Reset                                             */
11278                     __IOM uint16_t EORR4  : 1; /*!< [4..4] Pmn Event Output Reset                                             */
11279                     __IOM uint16_t EORR5  : 1; /*!< [5..5] Pmn Event Output Reset                                             */
11280                     __IOM uint16_t EORR6  : 1; /*!< [6..6] Pmn Event Output Reset                                             */
11281                     __IOM uint16_t EORR7  : 1; /*!< [7..7] Pmn Event Output Reset                                             */
11282                     __IOM uint16_t EORR8  : 1; /*!< [8..8] Pmn Event Output Reset                                             */
11283                     __IOM uint16_t EORR9  : 1; /*!< [9..9] Pmn Event Output Reset                                             */
11284                     __IOM uint16_t EORR10 : 1; /*!< [10..10] Pmn Event Output Reset                                           */
11285                     __IOM uint16_t EORR11 : 1; /*!< [11..11] Pmn Event Output Reset                                           */
11286                     __IOM uint16_t EORR12 : 1; /*!< [12..12] Pmn Event Output Reset                                           */
11287                     __IOM uint16_t EORR13 : 1; /*!< [13..13] Pmn Event Output Reset                                           */
11288                     __IOM uint16_t EORR14 : 1; /*!< [14..14] Pmn Event Output Reset                                           */
11289                     __IOM uint16_t EORR15 : 1; /*!< [15..15] Pmn Event Output Reset                                           */
11290                 } EORR_b;
11291             };
11292 
11293             union
11294             {
11295                 __IOM uint16_t EOSR;           /*!< (@ 0x0000000E) Event output reset register                                */
11296 
11297                 struct
11298                 {
11299                     __IOM uint16_t EOSR0  : 1; /*!< [0..0] Pmn Event Output Set                                               */
11300                     __IOM uint16_t EOSR1  : 1; /*!< [1..1] Pmn Event Output Set                                               */
11301                     __IOM uint16_t EOSR2  : 1; /*!< [2..2] Pmn Event Output Set                                               */
11302                     __IOM uint16_t EOSR3  : 1; /*!< [3..3] Pmn Event Output Set                                               */
11303                     __IOM uint16_t EOSR4  : 1; /*!< [4..4] Pmn Event Output Set                                               */
11304                     __IOM uint16_t EOSR5  : 1; /*!< [5..5] Pmn Event Output Set                                               */
11305                     __IOM uint16_t EOSR6  : 1; /*!< [6..6] Pmn Event Output Set                                               */
11306                     __IOM uint16_t EOSR7  : 1; /*!< [7..7] Pmn Event Output Set                                               */
11307                     __IOM uint16_t EOSR8  : 1; /*!< [8..8] Pmn Event Output Set                                               */
11308                     __IOM uint16_t EOSR9  : 1; /*!< [9..9] Pmn Event Output Set                                               */
11309                     __IOM uint16_t EOSR10 : 1; /*!< [10..10] Pmn Event Output Set                                             */
11310                     __IOM uint16_t EOSR11 : 1; /*!< [11..11] Pmn Event Output Set                                             */
11311                     __IOM uint16_t EOSR12 : 1; /*!< [12..12] Pmn Event Output Set                                             */
11312                     __IOM uint16_t EOSR13 : 1; /*!< [13..13] Pmn Event Output Set                                             */
11313                     __IOM uint16_t EOSR14 : 1; /*!< [14..14] Pmn Event Output Set                                             */
11314                     __IOM uint16_t EOSR15 : 1; /*!< [15..15] Pmn Event Output Set                                             */
11315                 } EOSR_b;
11316             };
11317         };
11318     };
11319 } R_PORT0_Type;                        /*!< Size = 16 (0x10)                                                          */
11320 
11321 /* =========================================================================================================================== */
11322 /* ================                                           R_PFS                                           ================ */
11323 /* =========================================================================================================================== */
11324 
11325 /**
11326  * @brief I/O Ports-PFS (R_PFS)
11327  */
11328 
11329 typedef struct                           /*!< (@ 0x40080800) R_PFS Structure                                            */
11330 {
11331     union
11332     {
11333         __IOM R_PFS_PORT_Type  PORT[15]; /*!< (@ 0x00000000) Port [0..14]                                               */
11334         __IOM R_PFS_VLSEL_Type VLSEL;    /*!< (@ 0x00000000) VLSEL                                                      */
11335     };
11336 } R_PFS_Type;                            /*!< Size = 960 (0x3c0)                                                        */
11337 
11338 /* =========================================================================================================================== */
11339 /* ================                                          R_PMISC                                          ================ */
11340 /* =========================================================================================================================== */
11341 
11342 /**
11343  * @brief I/O Ports-MISC (R_PMISC)
11344  */
11345 
11346 typedef struct                         /*!< (@ 0x40080D00) R_PMISC Structure                                          */
11347 {
11348     union
11349     {
11350         __IOM uint8_t PFENET;          /*!< (@ 0x00000000) Ethernet Control Register                                  */
11351 
11352         struct
11353         {
11354             uint8_t                : 4;
11355             __IOM uint8_t PHYMODE0 : 1; /*!< [4..4] Ethernet Mode Setting ch0                                          */
11356             __IOM uint8_t PHYMODE1 : 1; /*!< [5..5] Ethernet Mode Setting ch1                                          */
11357             uint8_t                : 2;
11358         } PFENET_b;
11359     };
11360     __IM uint8_t RESERVED[2];
11361 
11362     union
11363     {
11364         __IOM uint8_t PWPR;            /*!< (@ 0x00000003) Write-Protect Register                                     */
11365 
11366         struct
11367         {
11368             uint8_t             : 6;
11369             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
11370             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
11371         } PWPR_b;
11372     };
11373     __IM uint8_t RESERVED1;
11374 
11375     union
11376     {
11377         __IOM uint8_t PWPRS;           /*!< (@ 0x00000005) Write-Protect Register for Secure                          */
11378 
11379         struct
11380         {
11381             uint8_t             : 6;
11382             __IOM uint8_t PFSWE : 1;   /*!< [6..6] PmnPFS Register Write                                              */
11383             __IOM uint8_t B0WI  : 1;   /*!< [7..7] PFSWE Bit Write Disable                                            */
11384         } PWPRS_b;
11385     };
11386     __IM uint16_t RESERVED2[4];
11387     __IM uint8_t  RESERVED3;
11388 
11389     union
11390     {
11391         __IOM uint8_t PRWCNTR;          /*!< (@ 0x0000000F) Port Read Wait Control Register                            */
11392 
11393         struct
11394         {
11395             __IOM uint8_t WAIT : 2;     /*!< [1..0] Wait Cycle Control                                                 */
11396             uint8_t            : 6;
11397         } PRWCNTR_b;
11398     };
11399     __IOM R_PMISC_PMSAR_Type PMSAR[12]; /*!< (@ 0x00000010) Port Security Attribution Register                         */
11400 } R_PMISC_Type;                         /*!< Size = 40 (0x28)                                                          */
11401 
11402 /* =========================================================================================================================== */
11403 /* ================                                          R_QSPI                                           ================ */
11404 /* =========================================================================================================================== */
11405 
11406 /**
11407  * @brief Quad Serial Peripheral Interface (R_QSPI)
11408  */
11409 
11410 typedef struct                         /*!< (@ 0x64000000) R_QSPI Structure                                           */
11411 {
11412     union
11413     {
11414         __IOM uint32_t SFMSMD;         /*!< (@ 0x00000000) Transfer Mode Control Register                             */
11415 
11416         struct
11417         {
11418             __IOM uint32_t SFMRM  : 3; /*!< [2..0] Serial interface read mode selection                               */
11419             uint32_t              : 1;
11420             __IOM uint32_t SFMSE  : 2; /*!< [5..4] Selection of the prefetch function                                 */
11421             __IOM uint32_t SFMPFE : 1; /*!< [6..6] Selection of the prefetch function                                 */
11422             __IOM uint32_t SFMPAE : 1; /*!< [7..7] Selection of the function for stopping prefetch at locations
11423                                         *   other than on byte boundaries                                             */
11424             __IOM uint32_t SFMMD3 : 1; /*!< [8..8] SPI mode selection. An initial value is determined by
11425                                         *   input to CFGMD3.                                                          */
11426             __IOM uint32_t SFMOEX : 1; /*!< [9..9] Extension of the I/O buffer output enable signal for
11427                                         *   the serial interface                                                      */
11428             __IOM uint32_t SFMOHW : 1; /*!< [10..10] Hold time adjustment for serial transmission                     */
11429             __IOM uint32_t SFMOSW : 1; /*!< [11..11] Setup time adjustment for serial transmission                    */
11430             uint32_t              : 3;
11431             __IOM uint32_t SFMCCE : 1; /*!< [15..15] Read instruction code selection.                                 */
11432             uint32_t              : 16;
11433         } SFMSMD_b;
11434     };
11435 
11436     union
11437     {
11438         __IOM uint32_t SFMSSC;         /*!< (@ 0x00000004) Chip Selection Control Register                            */
11439 
11440         struct
11441         {
11442             __IOM uint32_t SFMSW  : 4; /*!< [3..0] Selection of a minimum high-level width of the QSSL signal         */
11443             __IOM uint32_t SFMSHD : 1; /*!< [4..4] QSSL signal release timing selection                               */
11444             __IOM uint32_t SFMSLD : 1; /*!< [5..5] QSSL signal output timing selection                                */
11445             uint32_t              : 26;
11446         } SFMSSC_b;
11447     };
11448 
11449     union
11450     {
11451         __IOM uint32_t SFMSKC;         /*!< (@ 0x00000008) Clock Control Register                                     */
11452 
11453         struct
11454         {
11455             __IOM uint32_t SFMDV : 5;  /*!< [4..0] Serial interface reference cycle selection (* Pay attention
11456                                         *   to the irregularity.)NOTE: When PCLKA multiplied by an
11457                                         *   odd number is selected, the high-level width of the SCK
11458                                         *   signal is longer than the low-level width by 1 x PCLKA
11459                                         *   before duty ratio correction.                                             */
11460             __IOM uint32_t SFMDTY : 1; /*!< [5..5] Selection of a duty ratio correction function for the
11461                                         *   SCK signal                                                                */
11462             uint32_t : 26;
11463         } SFMSKC_b;
11464     };
11465 
11466     union
11467     {
11468         __IM uint32_t SFMSST;          /*!< (@ 0x0000000C) Status Register                                            */
11469 
11470         struct
11471         {
11472             __IM uint32_t PFCNT : 5;   /*!< [4..0] Number of bytes of prefetched dataRange: 00000 - 10010
11473                                         *   (No combination other than the above is available.)                       */
11474             uint32_t            : 1;
11475             __IM uint32_t PFFUL : 1;   /*!< [6..6] Prefetch buffer state                                              */
11476             __IM uint32_t PFOFF : 1;   /*!< [7..7] Prefetch function operation state                                  */
11477             uint32_t            : 24;
11478         } SFMSST_b;
11479     };
11480 
11481     union
11482     {
11483         __IOM uint32_t SFMCOM;         /*!< (@ 0x00000010) Communication Port Register                                */
11484 
11485         struct
11486         {
11487             __IOM uint32_t SFMD : 8;   /*!< [7..0] Port for direct communication with the SPI bus.Input/output
11488                                         *   to and from this port is converted to a SPIbus cycle. This
11489                                         *   port is accessible in the direct communication mode (DCOM=1)
11490                                         *   only.Access to this port is ignored in the ROM access mode.               */
11491             uint32_t : 24;
11492         } SFMCOM_b;
11493     };
11494 
11495     union
11496     {
11497         __IOM uint32_t SFMCMD;         /*!< (@ 0x00000014) Communication Mode Control Register                        */
11498 
11499         struct
11500         {
11501             __IOM uint32_t DCOM : 1;   /*!< [0..0] Selection of a mode of communication with the SPI bus              */
11502             uint32_t            : 31;
11503         } SFMCMD_b;
11504     };
11505 
11506     union
11507     {
11508         __IOM uint32_t SFMCST;         /*!< (@ 0x00000018) Communication Status Register                              */
11509 
11510         struct
11511         {
11512             __IM uint32_t COMBSY : 1;  /*!< [0..0] SPI bus cycle completion state in direct communication             */
11513             uint32_t             : 6;
11514             __IM uint32_t EROMR  : 1;  /*!< [7..7] Status of ROM access detection in the direct communication
11515                                         *   modeNOTE: Writing of 0 only is possible. Writing of 1 is
11516                                         *   ignored.                                                                  */
11517             uint32_t : 24;
11518         } SFMCST_b;
11519     };
11520     __IM uint32_t RESERVED;
11521 
11522     union
11523     {
11524         __IOM uint32_t SFMSIC;         /*!< (@ 0x00000020) Instruction Code Register                                  */
11525 
11526         struct
11527         {
11528             __IOM uint32_t SFMCIC : 8; /*!< [7..0] Serial ROM instruction code to substitute                          */
11529             uint32_t              : 24;
11530         } SFMSIC_b;
11531     };
11532 
11533     union
11534     {
11535         __IOM uint32_t SFMSAC;         /*!< (@ 0x00000024) Address Mode Control Register                              */
11536 
11537         struct
11538         {
11539             __IOM uint32_t SFMAS  : 2; /*!< [1..0] Selection the number of address bits of the serial interface       */
11540             uint32_t              : 2;
11541             __IOM uint32_t SFM4BC : 1; /*!< [4..4] Selection of a default instruction code, when Serial
11542                                         *   Interface address width is selected 4 bytes.                              */
11543             uint32_t : 27;
11544         } SFMSAC_b;
11545     };
11546 
11547     union
11548     {
11549         __IOM uint32_t SFMSDC;         /*!< (@ 0x00000028) Dummy Cycle Control Register                               */
11550 
11551         struct
11552         {
11553             __IOM uint32_t SFMDN : 4;  /*!< [3..0] Selection of the number of dummy cycles of Fast Read
11554                                         *   instructions                                                              */
11555             uint32_t              : 2;
11556             __IM uint32_t  SFMXST : 1; /*!< [6..6] XIP mode status                                                    */
11557             __IOM uint32_t SFMXEN : 1; /*!< [7..7] XIP mode permission                                                */
11558             __IOM uint32_t SFMXD  : 8; /*!< [15..8] Mode data for serial ROM. (Control XIP mode)                      */
11559             uint32_t              : 16;
11560         } SFMSDC_b;
11561     };
11562     __IM uint32_t RESERVED1;
11563 
11564     union
11565     {
11566         __IOM uint32_t SFMSPC;         /*!< (@ 0x00000030) SPI Protocol Control Register                              */
11567 
11568         struct
11569         {
11570             __IOM uint32_t SFMSPI : 2; /*!< [1..0] Selection of SPI protocolNOTE: Serial ROM's SPI protocol
11571                                         *   is required to be set by software separately.                             */
11572             uint32_t              : 2;
11573             __IOM uint32_t SFMSDE : 1; /*!< [4..4] Selection of the minimum time of input output switch,
11574                                         *   when Dual SPI protocol or Quad SPI protocol is selected.                  */
11575             uint32_t : 27;
11576         } SFMSPC_b;
11577     };
11578 
11579     union
11580     {
11581         __IOM uint32_t SFMPMD;         /*!< (@ 0x00000034) Port Control Register                                      */
11582 
11583         struct
11584         {
11585             uint32_t              : 2;
11586             __IOM uint32_t SFMWPL : 1; /*!< [2..2] Specify level of WP pin                                            */
11587             uint32_t              : 29;
11588         } SFMPMD_b;
11589     };
11590     __IM uint32_t RESERVED2[499];
11591 
11592     union
11593     {
11594         __IOM uint32_t SFMCNT1;        /*!< (@ 0x00000804) External QSPI Address Register 1                           */
11595 
11596         struct
11597         {
11598             uint32_t                : 26;
11599             __IOM uint32_t QSPI_EXT : 6; /*!< [31..26] BANK Switching AddressWhen accessing from 0x6000_0000
11600                                           *   to 0x63FF_FFFF, Addres bus is Set QSPI_EXT[5:0] to high-order
11601                                           *   6bits of SHADDR[31:0]NOTE: Setting 6'h3F is prihibited.                   */
11602         } SFMCNT1_b;
11603     };
11604 } R_QSPI_Type;                           /*!< Size = 2056 (0x808)                                                       */
11605 
11606 /* =========================================================================================================================== */
11607 /* ================                                           R_RTC                                           ================ */
11608 /* =========================================================================================================================== */
11609 
11610 /**
11611  * @brief Realtime Clock (R_RTC)
11612  */
11613 
11614 typedef struct                         /*!< (@ 0x40083000) R_RTC Structure                                            */
11615 {
11616     union
11617     {
11618         __IM uint8_t R64CNT;           /*!< (@ 0x00000000) 64-Hz Counter                                              */
11619 
11620         struct
11621         {
11622             __IM uint8_t F64HZ : 1;    /*!< [0..0] 64Hz                                                               */
11623             __IM uint8_t F32HZ : 1;    /*!< [1..1] 32Hz                                                               */
11624             __IM uint8_t F16HZ : 1;    /*!< [2..2] 16Hz                                                               */
11625             __IM uint8_t F8HZ  : 1;    /*!< [3..3] 8Hz                                                                */
11626             __IM uint8_t F4HZ  : 1;    /*!< [4..4] 4Hz                                                                */
11627             __IM uint8_t F2HZ  : 1;    /*!< [5..5] 2Hz                                                                */
11628             __IM uint8_t F1HZ  : 1;    /*!< [6..6] 1Hz                                                                */
11629             uint8_t            : 1;
11630         } R64CNT_b;
11631     };
11632     __IM uint8_t RESERVED;
11633 
11634     union
11635     {
11636         union
11637         {
11638             __IOM uint8_t BCNT0;         /*!< (@ 0x00000002) Binary Counter 0                                           */
11639 
11640             struct
11641             {
11642                 __IOM uint8_t BCNT0 : 8; /*!< [7..0] The BCNT0 counter is a readable/writable 32-bit binary
11643                                           *   counter b7 to b0.                                                         */
11644             } BCNT0_b;
11645         };
11646 
11647         union
11648         {
11649             __IOM uint8_t RSECCNT;       /*!< (@ 0x00000002) Second Counter                                             */
11650 
11651             struct
11652             {
11653                 __IOM uint8_t SEC1 : 4;  /*!< [3..0] 1-Second Count Counts from 0 to 9 every second. When
11654                                           *   a carry is generated, 1 is added to the tens place.                       */
11655                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Second Count Counts from 0 to 5 for 60-second counting.         */
11656                 uint8_t             : 1;
11657             } RSECCNT_b;
11658         };
11659     };
11660     __IM uint8_t RESERVED1;
11661 
11662     union
11663     {
11664         union
11665         {
11666             __IOM uint8_t BCNT1;         /*!< (@ 0x00000004) Binary Counter 1                                           */
11667 
11668             struct
11669             {
11670                 __IOM uint8_t BCNT1 : 8; /*!< [7..0] The BCNT1 counter is a readable/writable 32-bit binary
11671                                           *   counter b15 to b8.                                                        */
11672             } BCNT1_b;
11673         };
11674 
11675         union
11676         {
11677             __IOM uint8_t RMINCNT;       /*!< (@ 0x00000004) Minute Counter                                             */
11678 
11679             struct
11680             {
11681                 __IOM uint8_t MIN1 : 4;  /*!< [3..0] 1-Minute Count Counts from 0 to 9 every minute. When
11682                                           *   a carry is generated, 1 is added to the tens place.                       */
11683                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Counts from 0 to 5 for 60-minute counting.         */
11684                 uint8_t             : 1;
11685             } RMINCNT_b;
11686         };
11687     };
11688     __IM uint8_t RESERVED2;
11689 
11690     union
11691     {
11692         union
11693         {
11694             __IOM uint8_t BCNT2;         /*!< (@ 0x00000006) Binary Counter 2                                           */
11695 
11696             struct
11697             {
11698                 __IOM uint8_t BCNT2 : 8; /*!< [7..0] The BCNT2 counter is a readable/writable 32-bit binary
11699                                           *   counter b23 to b16.                                                       */
11700             } BCNT2_b;
11701         };
11702 
11703         union
11704         {
11705             __IOM uint8_t RHRCNT;       /*!< (@ 0x00000006) Hour Counter                                               */
11706 
11707             struct
11708             {
11709                 __IOM uint8_t HR1 : 4;  /*!< [3..0] 1-Hour Count Counts from 0 to 9 once per hour. When a
11710                                          *   carry is generated, 1 is added to the tens place.                         */
11711                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Counts from 0 to 2 once per carry from
11712                                          *   the ones place.                                                           */
11713                 __IOM uint8_t PM : 1;   /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
11714                 uint8_t          : 1;
11715             } RHRCNT_b;
11716         };
11717     };
11718     __IM uint8_t RESERVED3;
11719 
11720     union
11721     {
11722         union
11723         {
11724             __IOM uint8_t BCNT3;         /*!< (@ 0x00000008) Binary Counter 3                                           */
11725 
11726             struct
11727             {
11728                 __IOM uint8_t BCNT3 : 8; /*!< [7..0] The BCNT3 counter is a readable/writable 32-bit binary
11729                                           *   counter b31 to b24.                                                       */
11730             } BCNT3_b;
11731         };
11732 
11733         union
11734         {
11735             __IOM uint8_t RWKCNT;       /*!< (@ 0x00000008) Day-of-Week Counter                                        */
11736 
11737             struct
11738             {
11739                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
11740                 uint8_t            : 5;
11741             } RWKCNT_b;
11742         };
11743     };
11744     __IM uint8_t RESERVED4;
11745 
11746     union
11747     {
11748         __IOM uint8_t RDAYCNT;         /*!< (@ 0x0000000A) Day Counter                                                */
11749 
11750         struct
11751         {
11752             __IOM uint8_t DATE1 : 4;   /*!< [3..0] 1-Day Count Counts from 0 to 9 once per day. When a carry
11753                                         *   is generated, 1 is added to the tens place.                               */
11754             __IOM uint8_t DATE10 : 2;  /*!< [5..4] 10-Day Count Counts from 0 to 3 once per carry from the
11755                                         *   ones place.                                                               */
11756             uint8_t : 2;
11757         } RDAYCNT_b;
11758     };
11759     __IM uint8_t RESERVED5;
11760 
11761     union
11762     {
11763         __IOM uint8_t RMONCNT;         /*!< (@ 0x0000000C) Month Counter                                              */
11764 
11765         struct
11766         {
11767             __IOM uint8_t MON1 : 4;    /*!< [3..0] 1-Month Count Counts from 0 to 9 once per month. When
11768                                         *   a carry is generated, 1 is added to the tens place.                       */
11769             __IOM uint8_t MON10 : 1;   /*!< [4..4] 10-Month Count Counts from 0 to 1 once per carry from
11770                                         *   the ones place.                                                           */
11771             uint8_t : 3;
11772         } RMONCNT_b;
11773     };
11774     __IM uint8_t RESERVED6;
11775 
11776     union
11777     {
11778         __IOM uint16_t RYRCNT;         /*!< (@ 0x0000000E) Year Counter                                               */
11779 
11780         struct
11781         {
11782             __IOM uint16_t YR1 : 4;    /*!< [3..0] 1-Year Count Counts from 0 to 9 once per year. When a
11783                                         *   carry is generated, 1 is added to the tens place.                         */
11784             __IOM uint16_t YR10 : 4;   /*!< [7..4] 10-Year Count Counts from 0 to 9 once per carry from
11785                                         *   ones place. When a carry is generated in the tens place,
11786                                         *   1 is added to the hundreds place.                                         */
11787             uint16_t : 8;
11788         } RYRCNT_b;
11789     };
11790 
11791     union
11792     {
11793         union
11794         {
11795             __IOM uint8_t BCNT0AR;         /*!< (@ 0x00000010) Binary Counter 0 Alarm Register                            */
11796 
11797             struct
11798             {
11799                 __IOM uint8_t BCNT0AR : 8; /*!< [7..0] he BCNT0AR counter is a readable/writable alarm register
11800                                             *   corresponding to 32-bit binary counter b7 to b0.                          */
11801             } BCNT0AR_b;
11802         };
11803 
11804         union
11805         {
11806             __IOM uint8_t RSECAR;        /*!< (@ 0x00000010) Second Alarm Register                                      */
11807 
11808             struct
11809             {
11810                 __OM uint8_t  SEC1  : 4; /*!< [3..0] 1-Second Value for the ones place of seconds                       */
11811                 __IOM uint8_t SEC10 : 3; /*!< [6..4] 10-Seconds Value for the tens place of seconds                     */
11812                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
11813             } RSECAR_b;
11814         };
11815     };
11816     __IM uint8_t RESERVED7;
11817 
11818     union
11819     {
11820         union
11821         {
11822             __IOM uint8_t BCNT1AR;         /*!< (@ 0x00000012) Binary Counter 1 Alarm Register                            */
11823 
11824             struct
11825             {
11826                 __IOM uint8_t BCNT1AR : 8; /*!< [7..0] he BCNT1AR counter is a readable/writable alarm register
11827                                             *   corresponding to 32-bit binary counter b15 to b8.                         */
11828             } BCNT1AR_b;
11829         };
11830 
11831         union
11832         {
11833             __IOM uint8_t RMINAR;        /*!< (@ 0x00000012) Minute Alarm Register                                      */
11834 
11835             struct
11836             {
11837                 __IOM uint8_t MIN1  : 4; /*!< [3..0] 1-Minute Count Value for the ones place of minutes                 */
11838                 __IOM uint8_t MIN10 : 3; /*!< [6..4] 10-Minute Count Value for the tens place of minutes                */
11839                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
11840             } RMINAR_b;
11841         };
11842     };
11843     __IM uint8_t RESERVED8;
11844 
11845     union
11846     {
11847         union
11848         {
11849             __IOM uint8_t BCNT2AR;         /*!< (@ 0x00000014) Binary Counter 2 Alarm Register                            */
11850 
11851             struct
11852             {
11853                 __IOM uint8_t BCNT2AR : 8; /*!< [7..0] The BCNT2AR counter is a readable/writable 32-bit binary
11854                                             *   counter b23 to b16.                                                       */
11855             } BCNT2AR_b;
11856         };
11857 
11858         union
11859         {
11860             __IOM uint8_t RHRAR;        /*!< (@ 0x00000014) Hour Alarm Register                                        */
11861 
11862             struct
11863             {
11864                 __IOM uint8_t HR1  : 4; /*!< [3..0] 1-Hour Count Value for the ones place of hours                     */
11865                 __IOM uint8_t HR10 : 2; /*!< [5..4] 10-Hour Count Value for the tens place of hours                    */
11866                 __IOM uint8_t PM   : 1; /*!< [6..6] Time Counter Setting for a.m./p.m.                                 */
11867                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
11868             } RHRAR_b;
11869         };
11870     };
11871     __IM uint8_t RESERVED9;
11872 
11873     union
11874     {
11875         union
11876         {
11877             __IOM uint8_t BCNT3AR;         /*!< (@ 0x00000016) Binary Counter 3 Alarm Register                            */
11878 
11879             struct
11880             {
11881                 __IOM uint8_t BCNT3AR : 8; /*!< [7..0] The BCNT3AR counter is a readable/writable 32-bit binary
11882                                             *   counter b31 to b24.                                                       */
11883             } BCNT3AR_b;
11884         };
11885 
11886         union
11887         {
11888             __IOM uint8_t RWKAR;        /*!< (@ 0x00000016) Day-of-Week Alarm Register                                 */
11889 
11890             struct
11891             {
11892                 __IOM uint8_t DAYW : 3; /*!< [2..0] Day-of-Week Counting                                               */
11893                 uint8_t            : 4;
11894                 __IOM uint8_t ENB  : 1; /*!< [7..7] Compare enable                                                     */
11895             } RWKAR_b;
11896         };
11897     };
11898     __IM uint8_t RESERVED10;
11899 
11900     union
11901     {
11902         union
11903         {
11904             __IOM uint8_t BCNT0AER;    /*!< (@ 0x00000018) Binary Counter 0 Alarm Enable Register                     */
11905 
11906             struct
11907             {
11908                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT0AER register is a readable/writable register
11909                                         *   for setting the alarm enable corresponding to 32-bit binary
11910                                         *   counter b7 to b0.                                                         */
11911             } BCNT0AER_b;
11912         };
11913 
11914         union
11915         {
11916             __IOM uint8_t RDAYAR;         /*!< (@ 0x00000018) Date Alarm Register                                        */
11917 
11918             struct
11919             {
11920                 __IOM uint8_t DATE1  : 4; /*!< [3..0] 1 Day Value for the ones place of days                             */
11921                 __IOM uint8_t DATE10 : 2; /*!< [5..4] 10 Days Value for the tens place of days                           */
11922                 uint8_t              : 1;
11923                 __IOM uint8_t ENB    : 1; /*!< [7..7] Compare enable                                                     */
11924             } RDAYAR_b;
11925         };
11926     };
11927     __IM uint8_t RESERVED11;
11928 
11929     union
11930     {
11931         union
11932         {
11933             __IOM uint8_t BCNT1AER;    /*!< (@ 0x0000001A) Binary Counter 1 Alarm Enable Register                     */
11934 
11935             struct
11936             {
11937                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT1AER register is a readable/writable register
11938                                         *   for setting the alarm enable corresponding to 32-bit binary
11939                                         *   counter b15 to b8.                                                        */
11940             } BCNT1AER_b;
11941         };
11942 
11943         union
11944         {
11945             __IOM uint8_t RMONAR;        /*!< (@ 0x0000001A) Month Alarm Register                                       */
11946 
11947             struct
11948             {
11949                 __IOM uint8_t MON1  : 4; /*!< [3..0] 1 Month Value for the ones place of months                         */
11950                 __IOM uint8_t MON10 : 1; /*!< [4..4] 10 Months Value for the tens place of months                       */
11951                 uint8_t             : 2;
11952                 __IOM uint8_t ENB   : 1; /*!< [7..7] Compare enable                                                     */
11953             } RMONAR_b;
11954         };
11955     };
11956     __IM uint8_t RESERVED12;
11957 
11958     union
11959     {
11960         union
11961         {
11962             __IOM uint16_t BCNT2AER;    /*!< (@ 0x0000001C) Binary Counter 2 Alarm Enable Register                     */
11963 
11964             struct
11965             {
11966                 __IOM uint16_t ENB : 8; /*!< [7..0] The BCNT2AER register is a readable/writable register
11967                                          *   for setting the alarm enable corresponding to 32-bit binary
11968                                          *   counter b23 to b16.                                                       */
11969                 uint16_t : 8;
11970             } BCNT2AER_b;
11971         };
11972 
11973         union
11974         {
11975             __IOM uint16_t RYRAR;        /*!< (@ 0x0000001C) Year Alarm Register                                        */
11976 
11977             struct
11978             {
11979                 __IOM uint16_t YR1  : 4; /*!< [3..0] 1 Year Value for the ones place of years                           */
11980                 __IOM uint16_t YR10 : 4; /*!< [7..4] 10 Years Value for the tens place of years                         */
11981                 uint16_t            : 8;
11982             } RYRAR_b;
11983         };
11984     };
11985 
11986     union
11987     {
11988         union
11989         {
11990             __IOM uint8_t BCNT3AER;    /*!< (@ 0x0000001E) Binary Counter 3 Alarm Enable Register                     */
11991 
11992             struct
11993             {
11994                 __IOM uint8_t ENB : 8; /*!< [7..0] The BCNT3AER register is a readable/writable register
11995                                         *   for setting the alarm enable corresponding to 32-bit binary
11996                                         *   counter b31 to b24.                                                       */
11997             } BCNT3AER_b;
11998         };
11999 
12000         union
12001         {
12002             __IOM uint8_t RYRAREN;     /*!< (@ 0x0000001E) Year Alarm Enable Register                                 */
12003 
12004             struct
12005             {
12006                 uint8_t           : 7;
12007                 __IOM uint8_t ENB : 1; /*!< [7..7] Compare enable                                                     */
12008             } RYRAREN_b;
12009         };
12010     };
12011     __IM uint8_t  RESERVED13;
12012     __IM uint16_t RESERVED14;
12013 
12014     union
12015     {
12016         __IOM uint8_t RCR1;            /*!< (@ 0x00000022) RTC Control Register 1                                     */
12017 
12018         struct
12019         {
12020             __IOM uint8_t AIE   : 1;   /*!< [0..0] Alarm Interrupt Enable                                             */
12021             __IOM uint8_t CIE   : 1;   /*!< [1..1] Carry Interrupt Enable                                             */
12022             __IOM uint8_t PIE   : 1;   /*!< [2..2] Periodic Interrupt Enable                                          */
12023             __IOM uint8_t RTCOS : 1;   /*!< [3..3] RTCOUT Output Select                                               */
12024             __IOM uint8_t PES   : 4;   /*!< [7..4] Periodic Interrupt Select                                          */
12025         } RCR1_b;
12026     };
12027     __IM uint8_t RESERVED15;
12028 
12029     union
12030     {
12031         __IOM uint8_t RCR2;            /*!< (@ 0x00000024) RTC Control Register 2                                     */
12032 
12033         struct
12034         {
12035             __IOM uint8_t START : 1;   /*!< [0..0] Start                                                              */
12036             __IOM uint8_t RESET : 1;   /*!< [1..1] RTC Software Reset                                                 */
12037             __IOM uint8_t ADJ30 : 1;   /*!< [2..2] 30-Second Adjustment                                               */
12038             __IOM uint8_t RTCOE : 1;   /*!< [3..3] RTCOUT Output Enable                                               */
12039             __IOM uint8_t AADJE : 1;   /*!< [4..4] Automatic Adjustment Enable (When the LOCO clock is selected,
12040                                         *   the setting of this bit is disabled.)                                     */
12041             __IOM uint8_t AADJP : 1;   /*!< [5..5] Automatic Adjustment Period Select (When the LOCO clock
12042                                         *   is selected, the setting of this bit is disabled.)                        */
12043             __IOM uint8_t HR24  : 1;   /*!< [6..6] Hours Mode                                                         */
12044             __IOM uint8_t CNTMD : 1;   /*!< [7..7] Count Mode Select                                                  */
12045         } RCR2_b;
12046     };
12047     __IM uint8_t  RESERVED16;
12048     __IM uint16_t RESERVED17;
12049 
12050     union
12051     {
12052         __IOM uint8_t RCR4;            /*!< (@ 0x00000028) RTC Control Register 4                                     */
12053 
12054         struct
12055         {
12056             __IOM uint8_t RCKSEL : 1;  /*!< [0..0] Count Source Select                                                */
12057             uint8_t              : 6;
12058             __IOM uint8_t ROPSEL : 1;  /*!< [7..7] RTC Operation Mode Select                                          */
12059         } RCR4_b;
12060     };
12061     __IM uint8_t RESERVED18;
12062 
12063     union
12064     {
12065         __IOM uint16_t RFRH;           /*!< (@ 0x0000002A) Frequency Register H                                       */
12066 
12067         struct
12068         {
12069             __IOM uint16_t RFC16 : 1;  /*!< [0..0] Frequency Comparison Value (b16) To generate the operating
12070                                         *   clock from the LOCOclock, this bit sets the comparison
12071                                         *   value of the 128-Hz clock cycle.                                          */
12072             uint16_t : 15;
12073         } RFRH_b;
12074     };
12075 
12076     union
12077     {
12078         __IOM uint16_t RFRL;           /*!< (@ 0x0000002C) Frequency Register L                                       */
12079 
12080         struct
12081         {
12082             __IOM uint16_t RFC : 16;   /*!< [15..0] Frequency Comparison Value(b15-b0) To generate the operating
12083                                         *   clock from the main clock, this bit sets the comparison
12084                                         *   value of the 128-Hz clock cycle.                                          */
12085         } RFRL_b;
12086     };
12087 
12088     union
12089     {
12090         __IOM uint8_t RADJ;            /*!< (@ 0x0000002E) Time Error Adjustment Register                             */
12091 
12092         struct
12093         {
12094             __IOM uint8_t ADJ : 6;     /*!< [5..0] Adjustment Value These bits specify the adjustment value
12095                                         *   from the prescaler.                                                       */
12096             __IOM uint8_t PMADJ : 2;   /*!< [7..6] Plus-Minus                                                         */
12097         } RADJ_b;
12098     };
12099     __IM uint8_t           RESERVED19;
12100     __IM uint16_t          RESERVED20[8];
12101     __IOM R_RTC_RTCCR_Type RTCCR[3];   /*!< (@ 0x00000040) Time Capture Control Register                              */
12102     __IM uint16_t          RESERVED21[5];
12103     __IOM R_RTC_CP_Type    CP[3];      /*!< (@ 0x00000050) Capture registers                                          */
12104 } R_RTC_Type;                          /*!< Size = 128 (0x80)                                                         */
12105 
12106 /* =========================================================================================================================== */
12107 /* ================                                          R_SCI0                                           ================ */
12108 /* =========================================================================================================================== */
12109 
12110 /**
12111  * @brief Serial Communications Interface (R_SCI0)
12112  */
12113 
12114 typedef struct                         /*!< (@ 0x40118000) R_SCI0 Structure                                           */
12115 {
12116     union
12117     {
12118         union
12119         {
12120             __IOM uint8_t SMR;          /*!< (@ 0x00000000) Serial Mode Register (SCMR.SMIF = 0)                       */
12121 
12122             struct
12123             {
12124                 __IOM uint8_t CKS  : 2; /*!< [1..0] Clock Select                                                       */
12125                 __IOM uint8_t MP   : 1; /*!< [2..2] Multi-Processor Mode(Valid only in asynchronous mode)              */
12126                 __IOM uint8_t STOP : 1; /*!< [3..3] Stop Bit Length(Valid only in asynchronous mode)                   */
12127                 __IOM uint8_t PM   : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
12128                 __IOM uint8_t PE   : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
12129                 __IOM uint8_t CHR  : 1; /*!< [6..6] Character Length(Valid only in asynchronous mode)                  */
12130                 __IOM uint8_t CM   : 1; /*!< [7..7] Communication Mode                                                 */
12131             } SMR_b;
12132         };
12133 
12134         union
12135         {
12136             __IOM uint8_t SMR_SMCI;    /*!< (@ 0x00000000) Serial mode register (SCMR.SMIF = 1)                       */
12137 
12138             struct
12139             {
12140                 __IOM uint8_t CKS : 2; /*!< [1..0] Clock Select                                                       */
12141                 __IOM uint8_t BCP : 2; /*!< [3..2] Base Clock Pulse(Valid only in asynchronous mode)                  */
12142                 __IOM uint8_t PM  : 1; /*!< [4..4] Parity Mode (Valid only when the PE bit is 1)                      */
12143                 __IOM uint8_t PE  : 1; /*!< [5..5] Parity Enable(Valid only in asynchronous mode)                     */
12144                 __IOM uint8_t BLK : 1; /*!< [6..6] Block Transfer Mode                                                */
12145                 __IOM uint8_t GM  : 1; /*!< [7..7] GSM Mode                                                           */
12146             } SMR_SMCI_b;
12147         };
12148     };
12149 
12150     union
12151     {
12152         __IOM uint8_t BRR;             /*!< (@ 0x00000001) Bit Rate Register                                          */
12153 
12154         struct
12155         {
12156             __IOM uint8_t BRR : 8;     /*!< [7..0] BRR is an 8-bit register that adjusts the bit rate.                */
12157         } BRR_b;
12158     };
12159 
12160     union
12161     {
12162         union
12163         {
12164             __IOM uint8_t SCR;          /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF = 0)                    */
12165 
12166             struct
12167             {
12168                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
12169                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
12170                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable(Valid in asynchronous
12171                                          *   mode when SMR.MP = 1)                                                     */
12172                 __IOM uint8_t RE  : 1;  /*!< [4..4] Receive Enable                                                     */
12173                 __IOM uint8_t TE  : 1;  /*!< [5..5] Transmit Enable                                                    */
12174                 __IOM uint8_t RIE : 1;  /*!< [6..6] Receive Interrupt Enable                                           */
12175                 __IOM uint8_t TIE : 1;  /*!< [7..7] Transmit Interrupt Enable                                          */
12176             } SCR_b;
12177         };
12178 
12179         union
12180         {
12181             __IOM uint8_t SCR_SMCI;     /*!< (@ 0x00000002) Serial Control Register (SCMR.SMIF =1)                     */
12182 
12183             struct
12184             {
12185                 __IOM uint8_t CKE  : 2; /*!< [1..0] Clock Enable                                                       */
12186                 __IOM uint8_t TEIE : 1; /*!< [2..2] Transmit End Interrupt Enable                                      */
12187                 __IOM uint8_t MPIE : 1; /*!< [3..3] Multi-Processor Interrupt Enable                                   */
12188                 __IOM uint8_t RE   : 1; /*!< [4..4] Receive Enable                                                     */
12189                 __IOM uint8_t TE   : 1; /*!< [5..5] Transmit Enable                                                    */
12190                 __IOM uint8_t RIE  : 1; /*!< [6..6] Receive Interrupt Enable                                           */
12191                 __IOM uint8_t TIE  : 1; /*!< [7..7] Transmit Interrupt Enable                                          */
12192             } SCR_SMCI_b;
12193         };
12194     };
12195 
12196     union
12197     {
12198         __IOM uint8_t TDR;             /*!< (@ 0x00000003) Transmit Data Register                                     */
12199 
12200         struct
12201         {
12202             __IOM uint8_t TDR : 8;     /*!< [7..0] TDR is an 8-bit register that stores transmit data.                */
12203         } TDR_b;
12204     };
12205 
12206     union
12207     {
12208         union
12209         {
12210             __IOM uint8_t SSR;          /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)         */
12211 
12212             struct
12213             {
12214                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit Transfer                                       */
12215                 __IM uint8_t  MPB  : 1; /*!< [1..1] Multi-Processor                                                    */
12216                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
12217                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
12218                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
12219                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
12220                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
12221                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
12222             } SSR_b;
12223         };
12224 
12225         union
12226         {
12227             __IOM uint8_t SSR_FIFO;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)         */
12228 
12229             struct
12230             {
12231                 __IOM uint8_t DR : 1;   /*!< [0..0] Receive Data Ready flag(Valid only in asynchronous mode(including
12232                                          *   multi-processor) and FIFO selected)                                       */
12233                 uint8_t            : 1;
12234                 __IOM uint8_t TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
12235                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
12236                 __IOM uint8_t FER  : 1; /*!< [4..4] Framing Error Flag                                                 */
12237                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
12238                 __IOM uint8_t RDF  : 1; /*!< [6..6] Receive FIFO data full flag                                        */
12239                 __IOM uint8_t TDFE : 1; /*!< [7..7] Transmit FIFO data empty flag                                      */
12240             } SSR_FIFO_b;
12241         };
12242 
12243         union
12244         {
12245             __IOM uint8_t SSR_SMCI;     /*!< (@ 0x00000004) Serial Status Register(SCMR.SMIF = 1)                      */
12246 
12247             struct
12248             {
12249                 __IOM uint8_t MPBT : 1; /*!< [0..0] Multi-Processor Bit TransferThis bit should be 0 in smart
12250                                          *   card interface mode.                                                      */
12251                 __IM uint8_t MPB : 1;   /*!< [1..1] Multi-ProcessorThis bit should be 0 in smart card interface
12252                                          *   mode.                                                                     */
12253                 __IM uint8_t  TEND : 1; /*!< [2..2] Transmit End Flag                                                  */
12254                 __IOM uint8_t PER  : 1; /*!< [3..3] Parity Error Flag                                                  */
12255                 __IOM uint8_t ERS  : 1; /*!< [4..4] Error Signal Status Flag                                           */
12256                 __IOM uint8_t ORER : 1; /*!< [5..5] Overrun Error Flag                                                 */
12257                 __IOM uint8_t RDRF : 1; /*!< [6..6] Receive Data Full Flag                                             */
12258                 __IOM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag                                           */
12259             } SSR_SMCI_b;
12260         };
12261     };
12262 
12263     union
12264     {
12265         __IM uint8_t RDR;              /*!< (@ 0x00000005) Receive Data Register                                      */
12266 
12267         struct
12268         {
12269             __IM uint8_t RDR : 8;      /*!< [7..0] RDR is an 8-bit register that stores receive data.                 */
12270         } RDR_b;
12271     };
12272 
12273     union
12274     {
12275         __IOM uint8_t SCMR;            /*!< (@ 0x00000006) Smart Card Mode Register                                   */
12276 
12277         struct
12278         {
12279             __IOM uint8_t SMIF : 1;    /*!< [0..0] Smart Card Interface Mode Select                                   */
12280             uint8_t            : 1;
12281             __IOM uint8_t SINV : 1;    /*!< [2..2] Transmitted/Received Data InvertSet this bit to 0 if
12282                                         *   operation is to be in simple I2C mode.                                    */
12283             __IOM uint8_t SDIR : 1;    /*!< [3..3] Transmitted/Received Data Transfer DirectionNOTE: The
12284                                         *   setting is invalid and a fixed data length of 8 bits is
12285                                         *   used in modes other than asynchronous mode.Set this bit
12286                                         *   to 1 if operation is to be in simple I2C mode.                            */
12287             __IOM uint8_t CHR1 : 1;    /*!< [4..4] Character Length 1(Only valid in asynchronous mode)                */
12288             uint8_t            : 2;
12289             __IOM uint8_t BCP2 : 1;    /*!< [7..7] Base Clock Pulse 2Selects the number of base clock cycles
12290                                         *   in combination with the SMR.BCP[1:0] bits                                 */
12291         } SCMR_b;
12292     };
12293 
12294     union
12295     {
12296         __IOM uint8_t SEMR;            /*!< (@ 0x00000007) Serial Extended Mode Register                              */
12297 
12298         struct
12299         {
12300             __IOM uint8_t ACS0 : 1;    /*!< [0..0] Asynchronous Mode Clock Source Select (Valid only in
12301                                         *   asynchronous mode).                                                       */
12302             __IOM uint8_t PADIS : 1;   /*!< [1..1] Preamble function Disable (Valid only in asynchronous
12303                                         *   mode).                                                                    */
12304             __IOM uint8_t BRME  : 1;   /*!< [2..2] Bit Rate Modulation Enable                                         */
12305             __IOM uint8_t ABCSE : 1;   /*!< [3..3] Asynchronous Mode Extended Base Clock Select 1(Valid
12306                                         *   only in asynchronous mode and SCR.CKE[1]=0)                               */
12307             __IOM uint8_t ABCS : 1;    /*!< [4..4] Asynchronous Mode Base Clock Select(Valid only in asynchronous
12308                                         *   mode)                                                                     */
12309             __IOM uint8_t NFEN : 1;    /*!< [5..5] Digital Noise Filter Function Enable(The NFEN bit should
12310                                         *   be 0 without simple I2C mode and asynchronous mode.)In
12311                                         *   asynchronous mode, for RXDn input only. In simple I2C mode,
12312                                         *   for RXDn/TxDn input.                                                      */
12313             __IOM uint8_t BGDM : 1;    /*!< [6..6] Baud Rate Generator Double-Speed Mode Select(Only valid
12314                                         *   the CKE[1] bit in SCR is 0 in asynchronous mode).                         */
12315             __IOM uint8_t RXDESEL : 1; /*!< [7..7] Asynchronous Start Bit Edge Detection Select(Valid only
12316                                         *   in asynchronous mode)                                                     */
12317         } SEMR_b;
12318     };
12319 
12320     union
12321     {
12322         __IOM uint8_t SNFR;            /*!< (@ 0x00000008) Noise Filter Setting Register                              */
12323 
12324         struct
12325         {
12326             __IOM uint8_t NFCS : 3;    /*!< [2..0] Noise Filter Clock Select                                          */
12327             uint8_t            : 5;
12328         } SNFR_b;
12329     };
12330 
12331     union
12332     {
12333         __IOM uint8_t SIMR1;           /*!< (@ 0x00000009) I2C Mode Register 1                                        */
12334 
12335         struct
12336         {
12337             __IOM uint8_t IICM  : 1;   /*!< [0..0] Simple I2C Mode Select                                             */
12338             uint8_t             : 2;
12339             __IOM uint8_t IICDL : 5;   /*!< [7..3] SDA Delay Output SelectCycles below are of the clock
12340                                         *   signal from the on-chip baud rate generator.                              */
12341         } SIMR1_b;
12342     };
12343 
12344     union
12345     {
12346         __IOM uint8_t SIMR2;           /*!< (@ 0x0000000A) I2C Mode Register 2                                        */
12347 
12348         struct
12349         {
12350             __IOM uint8_t IICINTM : 1; /*!< [0..0] I2C Interrupt Mode Select                                          */
12351             __IOM uint8_t IICCSC  : 1; /*!< [1..1] Clock Synchronization                                              */
12352             uint8_t               : 3;
12353             __IOM uint8_t IICACKT : 1; /*!< [5..5] ACK Transmission Data                                              */
12354             uint8_t               : 2;
12355         } SIMR2_b;
12356     };
12357 
12358     union
12359     {
12360         __IOM uint8_t SIMR3;              /*!< (@ 0x0000000B) I2C Mode Register 3                                        */
12361 
12362         struct
12363         {
12364             __IOM uint8_t IICSTAREQ  : 1; /*!< [0..0] Start Condition Generation                                         */
12365             __IOM uint8_t IICRSTAREQ : 1; /*!< [1..1] Restart Condition Generation                                       */
12366             __IOM uint8_t IICSTPREQ  : 1; /*!< [2..2] Stop Condition Generation                                          */
12367             __IOM uint8_t IICSTIF    : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
12368                                            *   Flag(When 0 is written to IICSTIF, it is cleared to 0.)                   */
12369             __IOM uint8_t IICSDAS : 2;    /*!< [5..4] SDA Output Select                                                  */
12370             __IOM uint8_t IICSCLS : 2;    /*!< [7..6] SCL Output Select                                                  */
12371         } SIMR3_b;
12372     };
12373 
12374     union
12375     {
12376         __IM uint8_t SISR;             /*!< (@ 0x0000000C) I2C Status Register                                        */
12377 
12378         struct
12379         {
12380             __IM uint8_t IICACKR : 1;  /*!< [0..0] ACK Reception Data Flag                                            */
12381             uint8_t              : 7;
12382         } SISR_b;
12383     };
12384 
12385     union
12386     {
12387         __IOM uint8_t SPMR;            /*!< (@ 0x0000000D) SPI Mode Register                                          */
12388 
12389         struct
12390         {
12391             __IOM uint8_t SSE    : 1;  /*!< [0..0] SSn Pin Function Enable                                            */
12392             __IOM uint8_t CTSE   : 1;  /*!< [1..1] CTS Enable                                                         */
12393             __IOM uint8_t MSS    : 1;  /*!< [2..2] Master Slave Select                                                */
12394             __IOM uint8_t CSTPEN : 1;  /*!< [3..3] CTS external pin Enable                                            */
12395             __IOM uint8_t MFF    : 1;  /*!< [4..4] Mode Fault Flag                                                    */
12396             uint8_t              : 1;
12397             __IOM uint8_t CKPOL  : 1;  /*!< [6..6] Clock Polarity Select                                              */
12398             __IOM uint8_t CKPH   : 1;  /*!< [7..7] Clock Phase Select                                                 */
12399         } SPMR_b;
12400     };
12401 
12402     union
12403     {
12404         union
12405         {
12406             __IOM uint16_t TDRHL;         /*!< (@ 0x0000000E) Transmit 9-bit Data Register                               */
12407 
12408             struct
12409             {
12410                 __OM uint16_t TDRHL : 16; /*!< [15..0] TDRHL is a 16-bit register that stores transmit data.             */
12411             } TDRHL_b;
12412         };
12413 
12414         union
12415         {
12416             __OM uint16_t FTDRHL;       /*!< (@ 0x0000000E) Transmit FIFO Data Register HL                             */
12417 
12418             struct
12419             {
12420                 __OM uint16_t TDAT : 9; /*!< [8..0] Serial transmit data (Valid only in asynchronous mode(including
12421                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
12422                 __OM uint16_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag(Valid only in asynchronous
12423                                          *   mode and SMR.MP=1 and FIFO selected)                                      */
12424                 uint16_t : 6;
12425             } FTDRHL_b;
12426         };
12427 
12428         struct
12429         {
12430             union
12431             {
12432                 __OM uint8_t FTDRH;         /*!< (@ 0x0000000E) Transmit FIFO Data Register H                              */
12433 
12434                 struct
12435                 {
12436                     __OM uint8_t TDATH : 1; /*!< [0..0] Serial transmit data (b8) (Valid only in asynchronous
12437                                              *   mode(including multi-processor) or clock synchronous mode,
12438                                              *   and FIFO selected)                                                        */
12439                     __OM uint8_t MPBT : 1;  /*!< [1..1] Multi-processor transfer bit flag(Valid only in asynchronous
12440                                              *   mode and SMR.MP=1 and FIFO selected)                                      */
12441                     uint8_t : 6;
12442                 } FTDRH_b;
12443             };
12444 
12445             union
12446             {
12447                 __OM uint8_t FTDRL;         /*!< (@ 0x0000000F) Transmit FIFO Data Register L                              */
12448 
12449                 struct
12450                 {
12451                     __OM uint8_t TDATL : 8; /*!< [7..0] Serial transmit data(b7-b0) (Valid only in asynchronous
12452                                              *   mode(including multi-processor) or clock synchronous mode,
12453                                              *   and FIFO selected)                                                        */
12454                 } FTDRL_b;
12455             };
12456         };
12457     };
12458 
12459     union
12460     {
12461         union
12462         {
12463             __IM uint16_t RDRHL;          /*!< (@ 0x00000010) Receive 9-bit Data Register                                */
12464 
12465             struct
12466             {
12467                 __IM uint16_t RDRHL : 16; /*!< [15..0] RDRHL is an 16-bit register that stores receive data.             */
12468             } RDRHL_b;
12469         };
12470 
12471         union
12472         {
12473             __IM uint16_t FRDRHL;       /*!< (@ 0x00000010) Receive FIFO Data Register HL                              */
12474 
12475             struct
12476             {
12477                 __IM uint16_t RDAT : 9; /*!< [8..0] Serial receive data(Valid only in asynchronous mode(including
12478                                          *   multi-processor) or clock synchronous mode, and FIFO selected)            */
12479                 __IM uint16_t MPB : 1;  /*!< [9..9] Multi-processor bit flag(Valid only in asynchronous mode
12480                                          *   with SMR.MP=1 and FIFO selected) It can read multi-processor
12481                                          *   bit corresponded to serial receive data(RDATA[8:0])                       */
12482                 __IM uint16_t DR   : 1; /*!< [10..10] Receive data ready flag(It is same as SSR.DR)                    */
12483                 __IM uint16_t PER  : 1; /*!< [11..11] Parity error flag                                                */
12484                 __IM uint16_t FER  : 1; /*!< [12..12] Framing error flag                                               */
12485                 __IM uint16_t ORER : 1; /*!< [13..13] Overrun error flag(It is same as SSR.ORER)                       */
12486                 __IM uint16_t RDF  : 1; /*!< [14..14] Receive FIFO data full flag(It is same as SSR.RDF)               */
12487                 uint16_t           : 1;
12488             } FRDRHL_b;
12489         };
12490 
12491         struct
12492         {
12493             union
12494             {
12495                 __IM uint8_t FRDRH;         /*!< (@ 0x00000010) Receive FIFO Data Register H                               */
12496 
12497                 struct
12498                 {
12499                     __IM uint8_t RDATH : 1; /*!< [0..0] Serial receive data(b8)(Valid only in asynchronous mode(including
12500                                              *   multi-processor) or clock synchronous mode, and FIFO selected)            */
12501                     __IM uint8_t MPB : 1;   /*!< [1..1] Multi-processor bit flag(Valid only in asynchronous mode
12502                                              *   with SMR.MP=1 and FIFO selected) It can read multi-processor
12503                                              *   bit corresponded to serial receive data(RDATA[8:0])                       */
12504                     __IM uint8_t DR   : 1;  /*!< [2..2] Receive data ready flag(It is same as SSR.DR)                      */
12505                     __IM uint8_t PER  : 1;  /*!< [3..3] Parity error flag                                                  */
12506                     __IM uint8_t FER  : 1;  /*!< [4..4] Framing error flag                                                 */
12507                     __IM uint8_t ORER : 1;  /*!< [5..5] Overrun error flag(It is same as SSR.ORER)                         */
12508                     __IM uint8_t RDF  : 1;  /*!< [6..6] Receive FIFO data full flag(It is same as SSR.RDF)                 */
12509                     uint8_t           : 1;
12510                 } FRDRH_b;
12511             };
12512 
12513             union
12514             {
12515                 __IM uint8_t FRDRL;         /*!< (@ 0x00000011) Receive FIFO Data Register L                               */
12516 
12517                 struct
12518                 {
12519                     __IM uint8_t RDATL : 8; /*!< [7..0] Serial receive data(Valid only in asynchronous mode(including
12520                                              *   multi-processor) or clock synchronous mode, and FIFO selected)NOTE:
12521                                              *   When reading both of FRDRH register and FRDRL register,
12522                                              *   please read by an order of the FRDRH register and the FRDRL
12523                                              *   register.                                                                 */
12524                 } FRDRL_b;
12525             };
12526         };
12527     };
12528 
12529     union
12530     {
12531         __IOM uint8_t MDDR;            /*!< (@ 0x00000012) Modulation Duty Register                                   */
12532 
12533         struct
12534         {
12535             __IOM uint8_t MDDR : 8;    /*!< [7..0] MDDR corrects the bit rate adjusted by the BRR register.           */
12536         } MDDR_b;
12537     };
12538 
12539     union
12540     {
12541         __IOM uint8_t DCCR;            /*!< (@ 0x00000013) Data Compare Match Control Register                        */
12542 
12543         struct
12544         {
12545             __IOM uint8_t DCMF  : 1;   /*!< [0..0] Data Compare Match Flag                                            */
12546             uint8_t             : 2;
12547             __IOM uint8_t DPER  : 1;   /*!< [3..3] Data Compare Match Parity Error Flag                               */
12548             __IOM uint8_t DFER  : 1;   /*!< [4..4] Data Compare Match Framing Error Flag                              */
12549             uint8_t             : 1;
12550             __IOM uint8_t IDSEL : 1;   /*!< [6..6] ID frame select(Valid only in asynchronous mode(including
12551                                         *   multi-processor)                                                          */
12552             __IOM uint8_t DCME : 1;    /*!< [7..7] Data Compare Match Enable(Valid only in asynchronous
12553                                         *   mode(including multi-processor)                                           */
12554         } DCCR_b;
12555     };
12556 
12557     union
12558     {
12559         __IOM uint16_t FCR;            /*!< (@ 0x00000014) FIFO Control Register                                      */
12560 
12561         struct
12562         {
12563             __IOM uint16_t FM : 1;     /*!< [0..0] FIFO Mode Select(Valid only in asynchronous mode(including
12564                                         *   multi-processor) or clock synchronous mode)                               */
12565             __IOM uint16_t RFRST : 1;  /*!< [1..1] Receive FIFO Data Register Reset(Valid only in FCR.FM=1)           */
12566             __IOM uint16_t TFRST : 1;  /*!< [2..2] Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)          */
12567             __IOM uint16_t DRES  : 1;  /*!< [3..3] Receive data ready error select bit(When detecting a
12568                                         *   reception data ready, the interrupt request is selected.)                 */
12569             __IOM uint16_t TTRG : 4;   /*!< [7..4] Transmit FIFO data trigger number(Valid only in asynchronous
12570                                         *   mode(including multi-processor) or clock synchronous mode)                */
12571             __IOM uint16_t RTRG : 4;   /*!< [11..8] Receive FIFO data trigger number(Valid only in asynchronous
12572                                         *   mode(including multi-processor) or clock synchronous mode)                */
12573             __IOM uint16_t RSTRG : 4;  /*!< [15..12] RTS Output Active Trigger Number Select(Valid only
12574                                         *   in asynchronous mode(including multi-processor) or clock
12575                                         *   synchronous mode)                                                         */
12576         } FCR_b;
12577     };
12578 
12579     union
12580     {
12581         __IM uint16_t FDR;             /*!< (@ 0x00000016) FIFO Data Count Register                                   */
12582 
12583         struct
12584         {
12585             __IM uint16_t R : 5;       /*!< [4..0] Receive FIFO Data CountIndicate the quantity of receive
12586                                         *   data stored in FRDRH and FRDRL(Valid only in asynchronous
12587                                         *   mode(including multi-processor) or clock synchronous mode,
12588                                         *   while FCR.FM=1)                                                           */
12589             uint16_t        : 3;
12590             __IM uint16_t T : 5;       /*!< [12..8] Transmit FIFO Data CountIndicate the quantity of non-transmit
12591                                         *   data stored in FTDRH and FTDRL(Valid only in asynchronous
12592                                         *   mode(including multi-processor) or clock synchronous mode,
12593                                         *   while FCR.FM=1)                                                           */
12594             uint16_t : 3;
12595         } FDR_b;
12596     };
12597 
12598     union
12599     {
12600         __IM uint16_t LSR;             /*!< (@ 0x00000018) Line Status Register                                       */
12601 
12602         struct
12603         {
12604             __IM uint16_t ORER : 1;    /*!< [0..0] Overrun Error Flag (Valid only in asynchronous mode(including
12605                                         *   multi-processor) or clock synchronous mode, and FIFO selected)            */
12606             uint16_t           : 1;
12607             __IM uint16_t FNUM : 5;    /*!< [6..2] Framing Error CountIndicates the quantity of data with
12608                                         *   a framing error among the receive data stored in the receive
12609                                         *   FIFO data register (FRDRH and FRDRL).                                     */
12610             uint16_t           : 1;
12611             __IM uint16_t PNUM : 5;    /*!< [12..8] Parity Error CountIndicates the quantity of data with
12612                                         *   a parity error among the receive data stored in the receive
12613                                         *   FIFO data register (FRDRH and FRDRL).                                     */
12614             uint16_t : 3;
12615         } LSR_b;
12616     };
12617 
12618     union
12619     {
12620         __IOM uint16_t CDR;            /*!< (@ 0x0000001A) Compare Match Data Register                                */
12621 
12622         struct
12623         {
12624             __IOM uint16_t CMPD : 9;   /*!< [8..0] Compare Match DataCompare data pattern for address match
12625                                         *   wake-up function                                                          */
12626             uint16_t : 7;
12627         } CDR_b;
12628     };
12629 
12630     union
12631     {
12632         __IOM uint8_t SPTR;            /*!< (@ 0x0000001C) Serial Port Register                                       */
12633 
12634         struct
12635         {
12636             __IM uint8_t RXDMON : 1;   /*!< [0..0] Serial input data monitor bit(The state of the RXD terminal
12637                                         *   is shown.)                                                                */
12638             __IOM uint8_t SPB2DT : 1;  /*!< [1..1] Serial port break data select bit(The output level of
12639                                         *   TxD terminal is selected when SCR.TE = 0.)                                */
12640             __IOM uint8_t SPB2IO : 1;  /*!< [2..2] Serial port break I/O bit(It's selected whether the value
12641                                         *   of SPB2DT is output to TxD terminal.)                                     */
12642             uint8_t            : 1;
12643             __IOM uint8_t RINV : 1;    /*!< [4..4] RXD invert bit                                                     */
12644             __IOM uint8_t TINV : 1;    /*!< [5..5] TXD invert bit                                                     */
12645             __IOM uint8_t ASEN : 1;    /*!< [6..6] Adjust receive sampling timing enable                              */
12646             __IOM uint8_t ATEN : 1;    /*!< [7..7] Adjust transmit timing enable                                      */
12647         } SPTR_b;
12648     };
12649 
12650     union
12651     {
12652         __IOM uint8_t ACTR;            /*!< (@ 0x0000001D) Adjustment Communication Timing Register                   */
12653 
12654         struct
12655         {
12656             __IOM uint8_t AST : 3;     /*!< [2..0] Adjustment value for receive Sampling Timing                       */
12657             __IOM uint8_t AJD : 1;     /*!< [3..3] Adjustment Direction for receive sampling timing                   */
12658             __IOM uint8_t ATT : 3;     /*!< [6..4] Adjustment value for Transmit timing                               */
12659             __IOM uint8_t AET : 1;     /*!< [7..7] Adjustment edge for transmit timing                                */
12660         } ACTR_b;
12661     };
12662     __IM uint16_t RESERVED;
12663 
12664     union
12665     {
12666         __IOM uint8_t ESMER;           /*!< (@ 0x00000020) Extended Serial Module Enable Register                     */
12667 
12668         struct
12669         {
12670             __IOM uint8_t ESME : 1;    /*!< [0..0] Extended Serial Mode Enable                                        */
12671             uint8_t            : 7;
12672         } ESMER_b;
12673     };
12674 
12675     union
12676     {
12677         __IOM uint8_t CR0;             /*!< (@ 0x00000021) Control Register 0                                         */
12678 
12679         struct
12680         {
12681             uint8_t             : 1;
12682             __IM uint8_t  SFSF  : 1;   /*!< [1..1] Start Frame Status Flag                                            */
12683             __IM uint8_t  RXDSF : 1;   /*!< [2..2] RXDXn Input Status Flag                                            */
12684             __IOM uint8_t BRME  : 1;   /*!< [3..3] Bit Rate Measurement Enable                                        */
12685             uint8_t             : 4;
12686         } CR0_b;
12687     };
12688 
12689     union
12690     {
12691         __IOM uint8_t CR1;             /*!< (@ 0x00000022) Control Register 1                                         */
12692 
12693         struct
12694         {
12695             __IOM uint8_t BFE   : 1;   /*!< [0..0] Break Field Enable                                                 */
12696             __IOM uint8_t CF0RE : 1;   /*!< [1..1] Control Field 0 Reception Enable                                   */
12697             __IOM uint8_t CF1DS : 2;   /*!< [3..2] Control Field 1 Data Register Select                               */
12698             __IOM uint8_t PIBE  : 1;   /*!< [4..4] Priority Interrupt Bit Enable                                      */
12699             __IOM uint8_t PIBS  : 3;   /*!< [7..5] Priority Interrupt Bit Select                                      */
12700         } CR1_b;
12701     };
12702 
12703     union
12704     {
12705         __IOM uint8_t CR2;             /*!< (@ 0x00000023) Control Register 2                                         */
12706 
12707         struct
12708         {
12709             __IOM uint8_t DFCS : 3;    /*!< [2..0] RXDXn Signal Digital Filter Clock Select                           */
12710             uint8_t            : 1;
12711             __IOM uint8_t BCCS : 2;    /*!< [5..4] Bus Collision Detection Clock Select                               */
12712             __IOM uint8_t RTS  : 2;    /*!< [7..6] RXDXn Reception Sampling Timing Select                             */
12713         } CR2_b;
12714     };
12715 
12716     union
12717     {
12718         __IOM uint8_t CR3;             /*!< (@ 0x00000024) Control Register 3                                         */
12719 
12720         struct
12721         {
12722             __IOM uint8_t SDST : 1;    /*!< [0..0] Start Frame Detection Start                                        */
12723             uint8_t            : 7;
12724         } CR3_b;
12725     };
12726 
12727     union
12728     {
12729         __IOM uint8_t PCR;             /*!< (@ 0x00000025) Port Control Register                                      */
12730 
12731         struct
12732         {
12733             __IOM uint8_t TXDXPS : 1;  /*!< [0..0] TXDXn Signal Polarity Select                                       */
12734             __IOM uint8_t RXDXPS : 1;  /*!< [1..1] RXDXn Signal Polarity Select                                       */
12735             uint8_t              : 2;
12736             __IOM uint8_t SHARPS : 1;  /*!< [4..4] TXDXn/RXDXn Pin Multiplexing Select                                */
12737             uint8_t              : 3;
12738         } PCR_b;
12739     };
12740 
12741     union
12742     {
12743         __IOM uint8_t ICR;             /*!< (@ 0x00000026) Interrupt Control Register                                 */
12744 
12745         struct
12746         {
12747             __IOM uint8_t BFDIE  : 1;  /*!< [0..0] Break Field Low Width Detected Interrupt Enable                    */
12748             __IOM uint8_t CF0MIE : 1;  /*!< [1..1] Control Field 0 Match Detected Interrupt Enable                    */
12749             __IOM uint8_t CF1MIE : 1;  /*!< [2..2] Control Field 1 Match Detected Interrupt Enable                    */
12750             __IOM uint8_t PIBDIE : 1;  /*!< [3..3] Priority Interrupt Bit Detected Interrupt Enable                   */
12751             __IOM uint8_t BCDIE  : 1;  /*!< [4..4] Bus Collision Detected Interrupt Enable                            */
12752             __IOM uint8_t AEDIE  : 1;  /*!< [5..5] Valid Edge Detected Interrupt Enable                               */
12753             uint8_t              : 2;
12754         } ICR_b;
12755     };
12756 
12757     union
12758     {
12759         __IM uint8_t STR;              /*!< (@ 0x00000027) Status Register                                            */
12760 
12761         struct
12762         {
12763             __IM uint8_t BFDF  : 1;    /*!< [0..0] Break Field Low Width Detection Flag                               */
12764             __IM uint8_t CF0MF : 1;    /*!< [1..1] Control Field 0 Match Flag                                         */
12765             __IM uint8_t CF1MF : 1;    /*!< [2..2] Control Field 1 Match Flag                                         */
12766             __IM uint8_t PIBDF : 1;    /*!< [3..3] Priority Interrupt Bit Detection Flag                              */
12767             __IM uint8_t BCDF  : 1;    /*!< [4..4] Bus Collision Detected Flag                                        */
12768             __IM uint8_t AEDF  : 1;    /*!< [5..5] Valid Edge Detection Flag                                          */
12769             uint8_t            : 2;
12770         } STR_b;
12771     };
12772 
12773     union
12774     {
12775         __IOM uint8_t STCR;            /*!< (@ 0x00000028) Status Clear Register                                      */
12776 
12777         struct
12778         {
12779             __IOM uint8_t BFDCL  : 1;  /*!< [0..0] BFDF Clear                                                         */
12780             __IOM uint8_t CF0MCL : 1;  /*!< [1..1] CF0MF Clear                                                        */
12781             __IOM uint8_t CF1MCL : 1;  /*!< [2..2] CF1MF Clear                                                        */
12782             __IOM uint8_t PIBDCL : 1;  /*!< [3..3] PIBDF Clear                                                        */
12783             __IOM uint8_t BCDCL  : 1;  /*!< [4..4] BCDF Clear                                                         */
12784             __IOM uint8_t AEDCL  : 1;  /*!< [5..5] AEDF Clear                                                         */
12785             uint8_t              : 2;
12786         } STCR_b;
12787     };
12788     __IOM uint8_t CF0DR;               /*!< (@ 0x00000029) Control Field 0 Data Register                              */
12789 
12790     union
12791     {
12792         __IOM uint8_t CF0CR;           /*!< (@ 0x0000002A) Control Field 0 Compare Enable Register                    */
12793 
12794         struct
12795         {
12796             __IOM uint8_t CF0CE0 : 1;  /*!< [0..0] Control Field 0 Bit 0 Compare Enable                               */
12797             __IOM uint8_t CF0CE1 : 1;  /*!< [1..1] Control Field 1 Bit 0 Compare Enable                               */
12798             __IOM uint8_t CF0CE2 : 1;  /*!< [2..2] Control Field 2 Bit 0 Compare Enable                               */
12799             __IOM uint8_t CF0CE3 : 1;  /*!< [3..3] Control Field 3 Bit 0 Compare Enable                               */
12800             __IOM uint8_t CF0CE4 : 1;  /*!< [4..4] Control Field 4 Bit 0 Compare Enable                               */
12801             __IOM uint8_t CF0CE5 : 1;  /*!< [5..5] Control Field 5 Bit 0 Compare Enable                               */
12802             __IOM uint8_t CF0CE6 : 1;  /*!< [6..6] Control Field 6 Bit 0 Compare Enable                               */
12803             __IOM uint8_t CF0CE7 : 1;  /*!< [7..7] Control Field 7 Bit 0 Compare Enable                               */
12804         } CF0CR_b;
12805     };
12806     __IOM uint8_t CF0RR;               /*!< (@ 0x0000002B) Control Field 0 Receive Data Register                      */
12807     __IOM uint8_t PCF1DR;              /*!< (@ 0x0000002C) Primary Control Field 1 Data Register                      */
12808     __IOM uint8_t SCF1DR;              /*!< (@ 0x0000002D) Secondary Control Field 1 Data Register                    */
12809 
12810     union
12811     {
12812         __IOM uint8_t CF1CR;           /*!< (@ 0x0000002E) Control Field 1 Compare Enable Register                    */
12813 
12814         struct
12815         {
12816             __IOM uint8_t CF1CE0 : 1;  /*!< [0..0] Control Field 1 Bit 0 Compare Enable                               */
12817             __IOM uint8_t CF1CE1 : 1;  /*!< [1..1] Control Field 1 Bit 1 Compare Enable                               */
12818             __IOM uint8_t CF1CE2 : 1;  /*!< [2..2] Control Field 1 Bit 2 Compare Enable                               */
12819             __IOM uint8_t CF1CE3 : 1;  /*!< [3..3] Control Field 1 Bit 3 Compare Enable                               */
12820             __IOM uint8_t CF1CE4 : 1;  /*!< [4..4] Control Field 1 Bit 4 Compare Enable                               */
12821             __IOM uint8_t CF1CE5 : 1;  /*!< [5..5] Control Field 1 Bit 5 Compare Enable                               */
12822             __IOM uint8_t CF1CE6 : 1;  /*!< [6..6] Control Field 1 Bit 6 Compare Enable                               */
12823             __IOM uint8_t CF1CE7 : 1;  /*!< [7..7] Control Field 1 Bit 7 Compare Enable                               */
12824         } CF1CR_b;
12825     };
12826     __IOM uint8_t CF1RR;               /*!< (@ 0x0000002F) Control Field 1 Receive Data Register                      */
12827 
12828     union
12829     {
12830         __IOM uint8_t TCR;             /*!< (@ 0x00000030) Timer Control Register                                     */
12831 
12832         struct
12833         {
12834             __IOM uint8_t TCST : 1;    /*!< [0..0] Timer Count Start                                                  */
12835             uint8_t            : 7;
12836         } TCR_b;
12837     };
12838 
12839     union
12840     {
12841         __IOM uint8_t TMR;             /*!< (@ 0x00000031) Timer Mode Register                                        */
12842 
12843         struct
12844         {
12845             __IOM uint8_t TOMS : 2;    /*!< [1..0] Timer Operating Mode Select                                        */
12846             uint8_t            : 1;
12847             __IOM uint8_t TWRC : 1;    /*!< [3..3] Counter Write Control                                              */
12848             __IOM uint8_t TCSS : 3;    /*!< [6..4] Timer Count Clock Source Select                                    */
12849             uint8_t            : 1;
12850         } TMR_b;
12851     };
12852     __IOM uint8_t TPRE;                /*!< (@ 0x00000032) Timer Prescaler Register                                   */
12853     __IOM uint8_t TCNT;                /*!< (@ 0x00000033) Timer Count Register                                       */
12854 } R_SCI0_Type;                         /*!< Size = 52 (0x34)                                                          */
12855 
12856 /* =========================================================================================================================== */
12857 /* ================                                          R_SDHI0                                          ================ */
12858 /* =========================================================================================================================== */
12859 
12860 /**
12861  * @brief SD/MMC Host Interface (R_SDHI0)
12862  */
12863 
12864 typedef struct                          /*!< (@ 0x40092000) R_SDHI0 Structure                                          */
12865 {
12866     union
12867     {
12868         __IOM uint32_t SD_CMD;          /*!< (@ 0x00000000) Command Type Register                                      */
12869 
12870         struct
12871         {
12872             __IOM uint32_t CMDIDX : 6;  /*!< [5..0] Command IndexThese bits specify Command Format[45:40]
12873                                          *   (command index).[Examples]CMD6: SD_CMD[7:0] = 8'b00_000110CMD18:
12874                                          *   SD_CMD[7:0] = 8'b00_010010ACMD13: SD_CMD[7:0] = 8'b01_001101              */
12875             __IOM uint32_t ACMD  : 2;   /*!< [7..6] Command Type Select                                                */
12876             __IOM uint32_t RSPTP : 3;   /*!< [10..8] Mode/Response TypeNOTE: As some commands cannot be used
12877                                          *   in normal mode, see section 1.4.10, Example of SD_CMD Register
12878                                          *   Setting to select mode/response type.                                     */
12879             __IOM uint32_t CMDTP : 1;   /*!< [11..11] Data Mode (Command Type)                                         */
12880             __IOM uint32_t CMDRW : 1;   /*!< [12..12] Write/Read Mode (enabled when the command with data
12881                                          *   is handled)                                                               */
12882             __IOM uint32_t TRSTP : 1;   /*!< [13..13] Single/Multiple Block Transfer (enabled when the command
12883                                          *   with data is handled)                                                     */
12884             __IOM uint32_t CMD12AT : 2; /*!< [15..14] Multiple Block Transfer Mode (enabled at multiple block
12885                                          *   transfer)                                                                 */
12886             uint32_t : 16;
12887         } SD_CMD_b;
12888     };
12889     __IM uint32_t RESERVED;
12890 
12891     union
12892     {
12893         __IOM uint32_t SD_ARG;          /*!< (@ 0x00000008) SD Command Argument Register                               */
12894 
12895         struct
12896         {
12897             __IOM uint32_t SD_ARG : 32; /*!< [31..0] Argument RegisterSet command format[39:8] (argument)              */
12898         } SD_ARG_b;
12899     };
12900 
12901     union
12902     {
12903         __IOM uint32_t SD_ARG1;          /*!< (@ 0x0000000C) SD Command Argument Register 1                             */
12904 
12905         struct
12906         {
12907             __IOM uint32_t SD_ARG1 : 16; /*!< [15..0] Argument Register 1Set command format[39:24] (argument)           */
12908             uint32_t               : 16;
12909         } SD_ARG1_b;
12910     };
12911 
12912     union
12913     {
12914         __IOM uint32_t SD_STOP;        /*!< (@ 0x00000010) Data Stop Register                                         */
12915 
12916         struct
12917         {
12918             __IOM uint32_t STP : 1;    /*!< [0..0] Stop- When STP is set to 1 during multiple block transfer,
12919                                         *   CMD12 is issued to halt the transfer through the SD host
12920                                         *   interface.However, if a command sequence is halted because
12921                                         *   of a communications error or timeout, CMD12 is not issued.
12922                                         *   Although continued buffer access is possible even after
12923                                         *   STP has been set to 1, the buffer access error bit (ERR5
12924                                         *   or ERR4) in SD_INFO2 will be set accordingly.- When STP
12925                                         *   has been set to 1 during transfer for single block write,
12926                                         *   the access end flag is set when SD_BUF becomes emp                        */
12927             uint32_t           : 7;
12928             __IOM uint32_t SEC : 1;    /*!< [8..8] Block Count EnableSet SEC to 1 at multiple block transfer.When
12929                                         *   SD_CMD is set as follows to start the command sequence
12930                                         *   while SEC is set to 1, CMD12 is automatically issued to
12931                                         *   stop multi-block transfer with the number of blocks which
12932                                         *   is set to SD_SECCNT.1. CMD18 or CMD25 in normal mode (SD_CMD[10:8]
12933                                         *   = 000)2. SD_CMD[15:13] = 001 in extended mode (CMD12 is
12934                                         *   automatically issued, multiple block transfer)When the
12935                                         *   command sequence is halted because of a communications
12936                                         *   error or timeout, CMD12 is not automatically i                            */
12937             uint32_t : 23;
12938         } SD_STOP_b;
12939     };
12940 
12941     union
12942     {
12943         __IOM uint32_t SD_SECCNT;          /*!< (@ 0x00000014) Block Count Register                                       */
12944 
12945         struct
12946         {
12947             __IOM uint32_t SD_SECCNT : 32; /*!< [31..0] Number of Transfer BlocksNOTE: Do not change the value
12948                                             *   of this bit when the CBSY bit in SD_INFO2 is set to 1.                    */
12949         } SD_SECCNT_b;
12950     };
12951 
12952     union
12953     {
12954         __IM uint32_t SD_RSP10;          /*!< (@ 0x00000018) SD Card Response Register 10                               */
12955 
12956         struct
12957         {
12958             __IM uint32_t SD_RSP10 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
12959         } SD_RSP10_b;
12960     };
12961 
12962     union
12963     {
12964         __IM uint32_t SD_RSP1;          /*!< (@ 0x0000001C) SD Card Response Register 1                                */
12965 
12966         struct
12967         {
12968             __IM uint32_t SD_RSP1 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
12969             uint32_t              : 16;
12970         } SD_RSP1_b;
12971     };
12972 
12973     union
12974     {
12975         __IM uint32_t SD_RSP32;          /*!< (@ 0x00000020) SD Card Response Register 32                               */
12976 
12977         struct
12978         {
12979             __IM uint32_t SD_RSP32 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
12980         } SD_RSP32_b;
12981     };
12982 
12983     union
12984     {
12985         __IM uint32_t SD_RSP3;          /*!< (@ 0x00000024) SD Card Response Register 3                                */
12986 
12987         struct
12988         {
12989             __IM uint32_t SD_RSP3 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
12990             uint32_t              : 16;
12991         } SD_RSP3_b;
12992     };
12993 
12994     union
12995     {
12996         __IM uint32_t SD_RSP54;          /*!< (@ 0x00000028) SD Card Response Register 54                               */
12997 
12998         struct
12999         {
13000             __IM uint32_t SD_RSP54 : 32; /*!< [31..0] Store the response from the SD card/MMC                           */
13001         } SD_RSP54_b;
13002     };
13003 
13004     union
13005     {
13006         __IM uint32_t SD_RSP5;          /*!< (@ 0x0000002C) SD Card Response Register 5                                */
13007 
13008         struct
13009         {
13010             __IM uint32_t SD_RSP5 : 16; /*!< [15..0] Store the response from the SD card/MMC                           */
13011             uint32_t              : 16;
13012         } SD_RSP5_b;
13013     };
13014 
13015     union
13016     {
13017         __IM uint32_t SD_RSP76;          /*!< (@ 0x00000030) SD Card Response Register 76                               */
13018 
13019         struct
13020         {
13021             __IM uint32_t SD_RSP76 : 24; /*!< [23..0] Store the response from the SD card/MMC                           */
13022             uint32_t               : 8;
13023         } SD_RSP76_b;
13024     };
13025 
13026     union
13027     {
13028         __IM uint32_t SD_RSP7;         /*!< (@ 0x00000034) SD Card Response Register 7                                */
13029 
13030         struct
13031         {
13032             __IM uint32_t SD_RSP7 : 8; /*!< [7..0] Store the response from the SD card/MMC                            */
13033             uint32_t              : 24;
13034         } SD_RSP7_b;
13035     };
13036 
13037     union
13038     {
13039         __IOM uint32_t SD_INFO1;        /*!< (@ 0x00000038) SD Card Interrupt Flag Register 1                          */
13040 
13041         struct
13042         {
13043             __IOM uint32_t RSPEND  : 1; /*!< [0..0] Response End Detection                                             */
13044             uint32_t               : 1;
13045             __IOM uint32_t ACEND   : 1; /*!< [2..2] Access End                                                         */
13046             __IOM uint32_t SDCDRM  : 1; /*!< [3..3] SDnCD Card Removal                                                 */
13047             __IOM uint32_t SDCDIN  : 1; /*!< [4..4] SDnCD Card Insertion                                               */
13048             __IM uint32_t  SDCDMON : 1; /*!< [5..5] Indicates the SDnCD state                                          */
13049             uint32_t               : 1;
13050             __IM uint32_t  SDWPMON : 1; /*!< [7..7] Indicates the SDnWP state                                          */
13051             __IOM uint32_t SDD3RM  : 1; /*!< [8..8] SDnDAT3 Card Removal                                               */
13052             __IOM uint32_t SDD3IN  : 1; /*!< [9..9] SDnDAT3 Card Insertion                                             */
13053             __IM uint32_t  SDD3MON : 1; /*!< [10..10] Inticates the SDnDAT3 State                                      */
13054             uint32_t               : 21;
13055         } SD_INFO1_b;
13056     };
13057 
13058     union
13059     {
13060         __IOM uint32_t SD_INFO2;             /*!< (@ 0x0000003C) SD Card Interrupt Flag Register 2                          */
13061 
13062         struct
13063         {
13064             __IOM uint32_t CMDE    : 1;      /*!< [0..0] Command Error                                                      */
13065             __IOM uint32_t CRCE    : 1;      /*!< [1..1] CRC Error                                                          */
13066             __IOM uint32_t ENDE    : 1;      /*!< [2..2] END Error                                                          */
13067             __IOM uint32_t DTO     : 1;      /*!< [3..3] Data Timeout                                                       */
13068             __IOM uint32_t ILW     : 1;      /*!< [4..4] SD_BUF Illegal Write Access                                        */
13069             __IOM uint32_t ILR     : 1;      /*!< [5..5] SD_BUF Illegal Read Access                                         */
13070             __IOM uint32_t RSPTO   : 1;      /*!< [6..6] Response Timeout                                                   */
13071             __IM uint32_t  SDD0MON : 1;      /*!< [7..7] SDDAT0Indicates the SDDAT0 state of the port specified
13072                                               *   by SD_PORTSEL.                                                            */
13073             __IOM uint32_t BRE          : 1; /*!< [8..8] SD_BUF Read Enable                                                 */
13074             __IOM uint32_t BWE          : 1; /*!< [9..9] SD_BUF Write Enable                                                */
13075             uint32_t                    : 3;
13076             __IM uint32_t SD_CLK_CTRLEN : 1; /*!< [13..13] When a command sequence is started by writing to SD_CMD,
13077                                               *   the CBSY bit is set to 1 and, at the same time, the SCLKDIVEN
13078                                               *   bit is set to 0. The SCLKDIVEN bit is set to 1 after 8
13079                                               *   cycles of SDCLK have elapsed after setting of the CBSY
13080                                               *   bit to 0 due to completion of the command sequence.                       */
13081             __IM uint32_t  CBSY : 1;         /*!< [14..14] Command Type Register Busy                                       */
13082             __IOM uint32_t ILA  : 1;         /*!< [15..15] Illegal Access Error                                             */
13083             uint32_t            : 16;
13084         } SD_INFO2_b;
13085     };
13086 
13087     union
13088     {
13089         __IOM uint32_t SD_INFO1_MASK;   /*!< (@ 0x00000040) SD_INFO1 Interrupt Mask Register                           */
13090 
13091         struct
13092         {
13093             __IOM uint32_t RSPENDM : 1; /*!< [0..0] Response End Interrupt Request Mask                                */
13094             uint32_t               : 1;
13095             __IOM uint32_t ACENDM  : 1; /*!< [2..2] Access End Interrupt Request Mask                                  */
13096             __IOM uint32_t SDCDRMM : 1; /*!< [3..3] SDnCD card Removal Interrupt Request Mask                          */
13097             __IOM uint32_t SDCDINM : 1; /*!< [4..4] SDnCD card Insertion Interrupt Request Mask                        */
13098             uint32_t               : 3;
13099             __IOM uint32_t SDD3RMM : 1; /*!< [8..8] SDnDAT3 Card Removal Interrupt Request Mask                        */
13100             __IOM uint32_t SDD3INM : 1; /*!< [9..9] SDnDAT3 Card Insertion Interrupt Request Mask                      */
13101             uint32_t               : 22;
13102         } SD_INFO1_MASK_b;
13103     };
13104 
13105     union
13106     {
13107         __IOM uint32_t SD_INFO2_MASK;  /*!< (@ 0x00000044) SD_INFO2 Interrupt Mask Register                           */
13108 
13109         struct
13110         {
13111             __IOM uint32_t CMDEM  : 1; /*!< [0..0] Command Error Interrupt Request Mask                               */
13112             __IOM uint32_t CRCEM  : 1; /*!< [1..1] CRC Error Interrupt Request Mask                                   */
13113             __IOM uint32_t ENDEM  : 1; /*!< [2..2] End Bit Error Interrupt Request Mask                               */
13114             __IOM uint32_t DTOM   : 1; /*!< [3..3] Data Timeout Interrupt Request Mask                                */
13115             __IOM uint32_t ILWM   : 1; /*!< [4..4] SD_BUF Register Illegal Write Interrupt Request Mask               */
13116             __IOM uint32_t ILRM   : 1; /*!< [5..5] SD_BUF Register Illegal Read Interrupt Request Mask                */
13117             __IOM uint32_t RSPTOM : 1; /*!< [6..6] Response Timeout Interrupt Request Mask                            */
13118             uint32_t              : 1;
13119             __IOM uint32_t BREM   : 1; /*!< [8..8] BRE Interrupt Request Mask                                         */
13120             __IOM uint32_t BWEM   : 1; /*!< [9..9] BWE Interrupt Request Mask                                         */
13121             uint32_t              : 5;
13122             __IOM uint32_t ILAM   : 1; /*!< [15..15] Illegal Access Error Interrupt Request Mask                      */
13123             uint32_t              : 16;
13124         } SD_INFO2_MASK_b;
13125     };
13126 
13127     union
13128     {
13129         __IOM uint32_t SD_CLK_CTRL;       /*!< (@ 0x00000048) SD Clock Control Register                                  */
13130 
13131         struct
13132         {
13133             __IOM uint32_t CLKSEL    : 8; /*!< [7..0] SDHI Clock Frequency Select                                        */
13134             __IOM uint32_t CLKEN     : 1; /*!< [8..8] SD/MMC Clock Output Control Enable                                 */
13135             __IOM uint32_t CLKCTRLEN : 1; /*!< [9..9] SD/MMC Clock Output Automatic Control Enable                       */
13136             uint32_t                 : 22;
13137         } SD_CLK_CTRL_b;
13138     };
13139 
13140     union
13141     {
13142         __IOM uint32_t SD_SIZE;        /*!< (@ 0x0000004C) Transfer Data Length Register                              */
13143 
13144         struct
13145         {
13146             __IOM uint32_t LEN : 10;   /*!< [9..0] Transfer Data SizeThese bits specify a size between 1
13147                                         *   and 512 bytes for the transfer of single blocks.In cases
13148                                         *   of multiple block transfer with automatic issuing of CMD12
13149                                         *   (CMD18 and CMD25), the only specifiable transfer data size
13150                                         *   is 512 bytes. Furthermore, in cases of multiple block transfer
13151                                         *   without automatic issuing of CMD12, as well as 512 bytes,
13152                                         *   32, 64, 128, and 256 bytes are specifiable. However, in
13153                                         *   the reading of 32, 64, 128, and 256 bytes for the transfer
13154                                         *   of multiple blocks, this is restricted to mult                            */
13155             uint32_t : 22;
13156         } SD_SIZE_b;
13157     };
13158 
13159     union
13160     {
13161         __IOM uint32_t SD_OPTION;        /*!< (@ 0x00000050) SD Card Access Control Option Register                     */
13162 
13163         struct
13164         {
13165             __IOM uint32_t CTOP     : 4; /*!< [3..0] Card Detect Time Counter                                           */
13166             __IOM uint32_t TOP      : 4; /*!< [7..4] Timeout Counter                                                    */
13167             __IOM uint32_t TOUTMASK : 1; /*!< [8..8] Timeout MASKWhen timeout occurs in case of inactivating
13168                                           *   timeout, software reset should be executed to terminate
13169                                           *   command sequence.                                                         */
13170             uint32_t              : 4;
13171             __IOM uint32_t WIDTH8 : 1;   /*!< [13..13] Bus Widthsee b15, WIDTH bit                                      */
13172             uint32_t              : 1;
13173             __IOM uint32_t WIDTH  : 1;   /*!< [15..15] Bus WidthNOTE: The initial value is applied at a reset
13174                                           *   and when the SOFT_RST.SDRST flag is 0.                                    */
13175             uint32_t : 16;
13176         } SD_OPTION_b;
13177     };
13178     __IM uint32_t RESERVED1;
13179 
13180     union
13181     {
13182         __IM uint32_t SD_ERR_STS1;      /*!< (@ 0x00000058) SD Error Status Register 1                                 */
13183 
13184         struct
13185         {
13186             __IM uint32_t CMDE0 : 1;    /*!< [0..0] Command Error 0NOTE: other than a response to a command
13187                                          *   issued within a command sequence                                          */
13188             __IM uint32_t CMDE1 : 1;    /*!< [1..1] Command Error 1NOTE: In cases where CMD12 is issued by
13189                                          *   setting a command index in SD_CMD, this is Indicated in
13190                                          *   CMDE0.                                                                    */
13191             __IM uint32_t RSPLENE0 : 1; /*!< [2..2] Response Length Error 0NOTE: other than a response to
13192                                          *   a command issued within a command sequence                                */
13193             __IM uint32_t RSPLENE1 : 1; /*!< [3..3] Response Length Error 1NOTE: In cases where CMD12 is
13194                                          *   issued by setting a command index in SD_CMD, this is indicated
13195                                          *   in RSPLENE0.                                                              */
13196             __IM uint32_t RDLENE   : 1; /*!< [4..4] Read Data Length Error                                             */
13197             __IM uint32_t CRCLENE  : 1; /*!< [5..5] CRC Status Token Length Error                                      */
13198             uint32_t               : 2;
13199             __IM uint32_t RSPCRCE0 : 1; /*!< [8..8] Response CRC Error 0NOTE: other than a response to a
13200                                          *   command issued within a command sequence                                  */
13201             __IM uint32_t RSPCRCE1 : 1; /*!< [9..9] Response CRC Error 1NOTE: In cases where CMD12 is issued
13202                                          *   by setting a command index in SD_CMD, this is indicated
13203                                          *   in RSPCRCE0.                                                              */
13204             __IM uint32_t RDCRCE : 1;   /*!< [10..10] Read Data CRC Error                                              */
13205             __IM uint32_t CRCTKE : 1;   /*!< [11..11] CRC Status Token Error                                           */
13206             __IM uint32_t CRCTK  : 3;   /*!< [14..12] CRC Status TokenStore the CRC status token value (normal
13207                                          *   value is 010b)                                                            */
13208             uint32_t : 17;
13209         } SD_ERR_STS1_b;
13210     };
13211 
13212     union
13213     {
13214         __IM uint32_t SD_ERR_STS2;      /*!< (@ 0x0000005C) SD Error Status Register 2                                 */
13215 
13216         struct
13217         {
13218             __IM uint32_t RSPTO0   : 1; /*!< [0..0] Response Timeout 0                                                 */
13219             __IM uint32_t RSPTO1   : 1; /*!< [1..1] Response Timeout 1                                                 */
13220             __IM uint32_t BSYTO0   : 1; /*!< [2..2] Busy Timeout 0                                                     */
13221             __IM uint32_t BSYTO1   : 1; /*!< [3..3] Busy Timeout 1                                                     */
13222             __IM uint32_t RDTO     : 1; /*!< [4..4] Read Data Timeout                                                  */
13223             __IM uint32_t CRCTO    : 1; /*!< [5..5] CRC Status Token Timeout                                           */
13224             __IM uint32_t CRCBSYTO : 1; /*!< [6..6] CRC Status Token Busy Timeout                                      */
13225             uint32_t               : 25;
13226         } SD_ERR_STS2_b;
13227     };
13228 
13229     union
13230     {
13231         __IOM uint32_t SD_BUF0;         /*!< (@ 0x00000060) SD Buffer Register                                         */
13232 
13233         struct
13234         {
13235             __IOM uint32_t SD_BUF : 32; /*!< [31..0] SD Buffer RegisterWhen writing to the SD card, the write
13236                                          *   data is written to this register. When reading from the
13237                                          *   SD card, the read data is read from this register. This
13238                                          *   register is internally connected to two 512-byte buffers.If
13239                                          *   both buffers are not empty when executing multiple block
13240                                          *   read, SD/MMC clock is stopped to suspend receiving data.
13241                                          *   When one of buffers is empty, SD/MMC clock is supplied
13242                                          *   to resume receiving data.                                                 */
13243         } SD_BUF0_b;
13244     };
13245     __IM uint32_t RESERVED2;
13246 
13247     union
13248     {
13249         __IOM uint32_t SDIO_MODE;      /*!< (@ 0x00000068) SDIO Mode Control Register                                 */
13250 
13251         struct
13252         {
13253             __IOM uint32_t INTEN  : 1; /*!< [0..0] SDIO Mode                                                          */
13254             uint32_t              : 1;
13255             __IOM uint32_t RWREQ  : 1; /*!< [2..2] Read Wait Request                                                  */
13256             uint32_t              : 5;
13257             __IOM uint32_t IOABT  : 1; /*!< [8..8] SDIO AbortNOTE: See manual                                         */
13258             __IOM uint32_t C52PUB : 1; /*!< [9..9] SDIO None AbortNOTE: See manual                                    */
13259             uint32_t              : 22;
13260         } SDIO_MODE_b;
13261     };
13262 
13263     union
13264     {
13265         __IOM uint32_t SDIO_INFO1;      /*!< (@ 0x0000006C) SDIO Interrupt Flag Register 1                             */
13266 
13267         struct
13268         {
13269             __IOM uint32_t IOIRQ   : 1; /*!< [0..0] SDIO Interrupt Status                                              */
13270             uint32_t               : 13;
13271             __IOM uint32_t EXPUB52 : 1; /*!< [14..14] EXPUB52 Status FlagNOTE: See manual                              */
13272             __IOM uint32_t EXWT    : 1; /*!< [15..15] EXWT Status FlagNOTE: See manual                                 */
13273             uint32_t               : 16;
13274         } SDIO_INFO1_b;
13275     };
13276 
13277     union
13278     {
13279         __IOM uint32_t SDIO_INFO1_MASK;  /*!< (@ 0x00000070) SDIO_INFO1 Interrupt Mask Register                         */
13280 
13281         struct
13282         {
13283             __IOM uint32_t IOIRQM   : 1; /*!< [0..0] IOIRQ Interrupt Mask Control                                       */
13284             uint32_t                : 13;
13285             __IOM uint32_t EXPUB52M : 1; /*!< [14..14] EXPUB52 Interrupt Request Mask Control                           */
13286             __IOM uint32_t EXWTM    : 1; /*!< [15..15] EXWT Interrupt Request Mask Control                              */
13287             uint32_t                : 16;
13288         } SDIO_INFO1_MASK_b;
13289     };
13290     __IM uint32_t RESERVED3[79];
13291 
13292     union
13293     {
13294         __IOM uint32_t SD_DMAEN;       /*!< (@ 0x000001B0) DMA Mode Enable Register                                   */
13295 
13296         struct
13297         {
13298             uint32_t             : 1;
13299             __IOM uint32_t DMAEN : 1;  /*!< [1..1] SD_BUF Read/Write DMA Transfer                                     */
13300             uint32_t             : 30;
13301         } SD_DMAEN_b;
13302     };
13303     __IM uint32_t RESERVED4[3];
13304 
13305     union
13306     {
13307         __IOM uint32_t SOFT_RST;       /*!< (@ 0x000001C0) Software Reset Register                                    */
13308 
13309         struct
13310         {
13311             __IOM uint32_t SDRST : 1;  /*!< [0..0] Software Reset of SD I/F Unit                                      */
13312             uint32_t             : 31;
13313         } SOFT_RST_b;
13314     };
13315     __IM uint32_t RESERVED5[2];
13316 
13317     union
13318     {
13319         __IOM uint32_t SDIF_MODE;      /*!< (@ 0x000001CC) SD Interface Mode Setting Register                         */
13320 
13321         struct
13322         {
13323             uint32_t               : 8;
13324             __IOM uint32_t NOCHKCR : 1; /*!< [8..8] CRC Check Mask (for MMC test commands)                             */
13325             uint32_t               : 23;
13326         } SDIF_MODE_b;
13327     };
13328     __IM uint32_t RESERVED6[4];
13329 
13330     union
13331     {
13332         __IOM uint32_t EXT_SWAP;       /*!< (@ 0x000001E0) Swap Control Register                                      */
13333 
13334         struct
13335         {
13336             uint32_t             : 6;
13337             __IOM uint32_t BWSWP : 1;  /*!< [6..6] SD_BUF0 Swap Write                                                 */
13338             __IOM uint32_t BRSWP : 1;  /*!< [7..7] SD_BUF0 Swap Read                                                  */
13339             uint32_t             : 24;
13340         } EXT_SWAP_b;
13341     };
13342 } R_SDHI0_Type;                        /*!< Size = 484 (0x1e4)                                                        */
13343 
13344 /* =========================================================================================================================== */
13345 /* ================                                          R_SPI0                                           ================ */
13346 /* =========================================================================================================================== */
13347 
13348 /**
13349  * @brief Serial Peripheral Interface (R_SPI0)
13350  */
13351 
13352 typedef struct                         /*!< (@ 0x4011A000) R_SPI0 Structure                                           */
13353 {
13354     union
13355     {
13356         __IOM uint8_t SPCR;            /*!< (@ 0x00000000) SPI Control Register                                       */
13357 
13358         struct
13359         {
13360             __IOM uint8_t SPMS   : 1;  /*!< [0..0] SPI Mode Select                                                    */
13361             __IOM uint8_t TXMD   : 1;  /*!< [1..1] Communications Operating Mode Select                               */
13362             __IOM uint8_t MODFEN : 1;  /*!< [2..2] Mode Fault Error Detection Enable                                  */
13363             __IOM uint8_t MSTR   : 1;  /*!< [3..3] SPI Master/Slave Mode Select                                       */
13364             __IOM uint8_t SPEIE  : 1;  /*!< [4..4] SPI Error Interrupt Enable                                         */
13365             __IOM uint8_t SPTIE  : 1;  /*!< [5..5] Transmit Buffer Empty Interrupt Enable                             */
13366             __IOM uint8_t SPE    : 1;  /*!< [6..6] SPI Function Enable                                                */
13367             __IOM uint8_t SPRIE  : 1;  /*!< [7..7] SPI Receive Buffer Full Interrupt Enable                           */
13368         } SPCR_b;
13369     };
13370 
13371     union
13372     {
13373         __IOM uint8_t SSLP;            /*!< (@ 0x00000001) SPI Slave Select Polarity Register                         */
13374 
13375         struct
13376         {
13377             __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
13378             __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
13379             __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
13380             __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
13381             __IOM uint8_t SSL4P : 1;   /*!< [4..4] SSL4 Signal Polarity Setting                                       */
13382             __IOM uint8_t SSL5P : 1;   /*!< [5..5] SSL5 Signal Polarity Setting                                       */
13383             __IOM uint8_t SSL6P : 1;   /*!< [6..6] SSL6 Signal Polarity Setting                                       */
13384             __IOM uint8_t SSL7P : 1;   /*!< [7..7] SSL7 Signal Polarity Setting                                       */
13385         } SSLP_b;
13386     };
13387 
13388     union
13389     {
13390         __IOM uint8_t SPPCR;           /*!< (@ 0x00000002) SPI Pin Control Register                                   */
13391 
13392         struct
13393         {
13394             __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
13395             __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
13396             uint8_t             : 2;
13397             __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
13398             __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
13399             uint8_t             : 2;
13400         } SPPCR_b;
13401     };
13402 
13403     union
13404     {
13405         __IOM uint8_t SPSR;            /*!< (@ 0x00000003) SPI Status Register                                        */
13406 
13407         struct
13408         {
13409             __IOM uint8_t OVRF  : 1;   /*!< [0..0] Overrun Error Flag                                                 */
13410             __IM uint8_t  IDLNF : 1;   /*!< [1..1] SPI Idle Flag                                                      */
13411             __IOM uint8_t MODF  : 1;   /*!< [2..2] Mode Fault Error Flag                                              */
13412             __IOM uint8_t PERF  : 1;   /*!< [3..3] Parity Error Flag                                                  */
13413             __IOM uint8_t UDRF  : 1;   /*!< [4..4] Underrun Error Flag(When MODF is 0, This bit is invalid.)          */
13414             __IOM uint8_t SPTEF : 1;   /*!< [5..5] SPI Transmit Buffer Empty Flag                                     */
13415             __IOM uint8_t CENDF : 1;   /*!< [6..6] Communication End Flag                                             */
13416             __IOM uint8_t SPRF  : 1;   /*!< [7..7] SPI Receive Buffer Full Flag                                       */
13417         } SPSR_b;
13418     };
13419 
13420     union
13421     {
13422         __IOM uint32_t SPDR;           /*!< (@ 0x00000004) SPI Data Register                                          */
13423         __IOM uint16_t SPDR_HA;        /*!< (@ 0x00000004) SPI Data Register ( halfword access )                      */
13424         __IOM uint8_t  SPDR_BY;        /*!< (@ 0x00000004) SPI Data Register ( byte access )                          */
13425     };
13426 
13427     union
13428     {
13429         __IOM uint8_t SPSCR;           /*!< (@ 0x00000008) SPI Sequence Control Register                              */
13430 
13431         struct
13432         {
13433             __IOM uint8_t SPSLN : 3;   /*!< [2..0] RSPI Sequence Length SpecificationThe order in which
13434                                         *   the SPCMD0 to SPCMD07 registers are to be referenced is
13435                                         *   changed in accordance with the sequence length that is
13436                                         *   set in these bits. The relationship among the setting of
13437                                         *   these bits, sequence length, and SPCMD0 to SPCMD7 registers
13438                                         *   referenced by the RSPI is shown above. However, the RSPI
13439                                         *   in slave mode always references SPCMD0.                                   */
13440             uint8_t : 5;
13441         } SPSCR_b;
13442     };
13443 
13444     union
13445     {
13446         __IM uint8_t SPSSR;            /*!< (@ 0x00000009) SPI Sequence Status Register                               */
13447 
13448         struct
13449         {
13450             __IM uint8_t SPCP  : 3;    /*!< [2..0] RSPI Command Pointer                                               */
13451             uint8_t            : 1;
13452             __IM uint8_t SPECM : 3;    /*!< [6..4] RSPI Error Command                                                 */
13453             uint8_t            : 1;
13454         } SPSSR_b;
13455     };
13456 
13457     union
13458     {
13459         __IOM uint8_t SPBR;            /*!< (@ 0x0000000A) SPI Bit Rate Register                                      */
13460 
13461         struct
13462         {
13463             __IOM uint8_t SPR : 8;     /*!< [7..0] SPBR sets the bit rate in master mode.                             */
13464         } SPBR_b;
13465     };
13466 
13467     union
13468     {
13469         __IOM uint8_t SPDCR;           /*!< (@ 0x0000000B) SPI Data Control Register                                  */
13470 
13471         struct
13472         {
13473             __IOM uint8_t SPFC   : 2;  /*!< [1..0] Number of Frames Specification                                     */
13474             __IOM uint8_t SLSEL  : 2;  /*!< [3..2] SSL Pin Output Select                                              */
13475             __IOM uint8_t SPRDTD : 1;  /*!< [4..4] SPI Receive/Transmit Data Selection                                */
13476             __IOM uint8_t SPLW   : 1;  /*!< [5..5] SPI Word Access/Halfword Access Specification                      */
13477             __IOM uint8_t SPBYT  : 1;  /*!< [6..6] SPI Byte Access Specification                                      */
13478             uint8_t              : 1;
13479         } SPDCR_b;
13480     };
13481 
13482     union
13483     {
13484         __IOM uint8_t SPCKD;           /*!< (@ 0x0000000C) SPI Clock Delay Register                                   */
13485 
13486         struct
13487         {
13488             __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
13489             uint8_t             : 5;
13490         } SPCKD_b;
13491     };
13492 
13493     union
13494     {
13495         __IOM uint8_t SSLND;           /*!< (@ 0x0000000D) SPI Slave Select Negation Delay Register                   */
13496 
13497         struct
13498         {
13499             __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Setting                                         */
13500             uint8_t             : 5;
13501         } SSLND_b;
13502     };
13503 
13504     union
13505     {
13506         __IOM uint8_t SPND;            /*!< (@ 0x0000000E) SPI Next-Access Delay Register                             */
13507 
13508         struct
13509         {
13510             __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Setting                                      */
13511             uint8_t             : 5;
13512         } SPND_b;
13513     };
13514 
13515     union
13516     {
13517         __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
13518 
13519         struct
13520         {
13521             __IOM uint8_t SPPE   : 1;  /*!< [0..0] Parity Enable                                                      */
13522             __IOM uint8_t SPOE   : 1;  /*!< [1..1] Parity Mode                                                        */
13523             __IOM uint8_t SPIIE  : 1;  /*!< [2..2] SPI Idle Interrupt Enable                                          */
13524             __IOM uint8_t PTE    : 1;  /*!< [3..3] Parity Self-Testing                                                */
13525             __IOM uint8_t SCKASE : 1;  /*!< [4..4] RSPCK Auto-Stop Function Enable                                    */
13526             __IOM uint8_t SPTDDL : 3;  /*!< [7..5] RSPI Transmit Data Delay                                           */
13527         } SPCR2_b;
13528     };
13529 
13530     union
13531     {
13532         __IOM uint16_t SPCMD[8];       /*!< (@ 0x00000010) SPI Command Register [0..7]                                */
13533 
13534         struct
13535         {
13536             __IOM uint16_t CPHA   : 1; /*!< [0..0] RSPCK Phase Setting                                                */
13537             __IOM uint16_t CPOL   : 1; /*!< [1..1] RSPCK Polarity Setting                                             */
13538             __IOM uint16_t BRDV   : 2; /*!< [3..2] Bit Rate Division Setting                                          */
13539             __IOM uint16_t SSLA   : 3; /*!< [6..4] SSL Signal Assertion Setting                                       */
13540             __IOM uint16_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Keeping                                           */
13541             __IOM uint16_t SPB    : 4; /*!< [11..8] SPI Data Length Setting                                           */
13542             __IOM uint16_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
13543             __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
13544             __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
13545             __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
13546         } SPCMD_b[8];
13547     };
13548 
13549     union
13550     {
13551         __IOM uint8_t SPDCR2;          /*!< (@ 0x00000020) SPI Data Control Register 2                                */
13552 
13553         struct
13554         {
13555             __IOM uint8_t BYSW : 1;    /*!< [0..0] Byte Swap Operating Mode Select                                    */
13556             __IOM uint8_t SINV : 1;    /*!< [1..1] Serial data invert bit                                             */
13557             uint8_t            : 6;
13558         } SPDCR2_b;
13559     };
13560 
13561     union
13562     {
13563         __IOM uint8_t SPCR3;           /*!< (@ 0x00000021) RSPI Control Register 3                                    */
13564 
13565         struct
13566         {
13567             __IOM uint8_t ETXMD  : 1;  /*!< [0..0] Extended Communication Mode Select                                 */
13568             __IOM uint8_t BFDS   : 1;  /*!< [1..1] Between Burst Transfer Frames Delay Select                         */
13569             uint8_t              : 2;
13570             __IOM uint8_t CENDIE : 1;  /*!< [4..4] RSPI Communication End Interrupt Enable                            */
13571             uint8_t              : 3;
13572         } SPCR3_b;
13573     };
13574     __IM uint16_t RESERVED;
13575     __IM uint32_t RESERVED1[6];
13576     __IM uint16_t RESERVED2;
13577 
13578     union
13579     {
13580         __IOM uint16_t SPPR;           /*!< (@ 0x0000003E) RSPI Parameter Read Register                               */
13581 
13582         struct
13583         {
13584             uint16_t              : 4;
13585             __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check                                                 */
13586             uint16_t              : 3;
13587             __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check                                               */
13588             uint16_t              : 1;
13589             __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check                                             */
13590         } SPPR_b;
13591     };
13592 } R_SPI0_Type;                         /*!< Size = 64 (0x40)                                                          */
13593 
13594 /* =========================================================================================================================== */
13595 /* ================                                          R_SRAM                                           ================ */
13596 /* =========================================================================================================================== */
13597 
13598 /**
13599  * @brief SRAM (R_SRAM)
13600  */
13601 
13602 typedef struct                         /*!< (@ 0x40002000) R_SRAM Structure                                           */
13603 {
13604     union
13605     {
13606         __IOM uint8_t PARIOAD;         /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register       */
13607 
13608         struct
13609         {
13610             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
13611             uint8_t           : 7;
13612         } PARIOAD_b;
13613     };
13614     __IM uint8_t RESERVED[3];
13615 
13616     union
13617     {
13618         __IOM uint8_t SRAMPRCR;         /*!< (@ 0x00000004) SRAM Protection Register                                   */
13619 
13620         struct
13621         {
13622             __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control                                             */
13623             __OM uint8_t  KW       : 7; /*!< [7..1] Write Key Code                                                     */
13624         } SRAMPRCR_b;
13625     };
13626     __IM uint8_t  RESERVED1[3];
13627     __IOM uint8_t SRAMWTSC;             /*!< (@ 0x00000008) RAM Wait State Control Register                            */
13628     __IM uint8_t  RESERVED2[3];
13629 
13630     union
13631     {
13632         __IOM uint8_t SRAMPRCR2;         /*!< (@ 0x0000000C) SRAM Protection Register 2                                 */
13633 
13634         struct
13635         {
13636             __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
13637             __OM uint8_t  KW        : 7; /*!< [7..1] Write Key Code                                                     */
13638         } SRAMPRCR2_b;
13639     };
13640     __IM uint8_t RESERVED3[179];
13641 
13642     union
13643     {
13644         __IOM uint8_t ECCMODE;         /*!< (@ 0x000000C0) ECC Operating Mode Control Register                        */
13645 
13646         struct
13647         {
13648             __IOM uint8_t ECCMOD : 2;  /*!< [1..0] ECC Operating Mode Select                                          */
13649             uint8_t              : 6;
13650         } ECCMODE_b;
13651     };
13652 
13653     union
13654     {
13655         __IOM uint8_t ECC2STS;         /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register                            */
13656 
13657         struct
13658         {
13659             __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status                                             */
13660             uint8_t               : 7;
13661         } ECC2STS_b;
13662     };
13663 
13664     union
13665     {
13666         __IOM uint8_t ECC1STSEN;       /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register         */
13667 
13668         struct
13669         {
13670             __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable                          */
13671             uint8_t               : 7;
13672         } ECC1STSEN_b;
13673     };
13674 
13675     union
13676     {
13677         __IOM uint8_t ECC1STS;         /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register                            */
13678 
13679         struct
13680         {
13681             __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status                                             */
13682             uint8_t               : 7;
13683         } ECC1STS_b;
13684     };
13685 
13686     union
13687     {
13688         __IOM uint8_t ECCPRCR;         /*!< (@ 0x000000C4) ECC Protection Register                                    */
13689 
13690         struct
13691         {
13692             __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control                                             */
13693             __OM uint8_t  KW      : 7; /*!< [7..1] Write Key Code                                                     */
13694         } ECCPRCR_b;
13695     };
13696     __IM uint8_t RESERVED4[11];
13697 
13698     union
13699     {
13700         __IOM uint8_t ECCPRCR2;         /*!< (@ 0x000000D0) ECC Protection Register 2                                  */
13701 
13702         struct
13703         {
13704             __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control                                             */
13705             __OM uint8_t  KW2      : 7; /*!< [7..1] Write Key Code                                                     */
13706         } ECCPRCR2_b;
13707     };
13708     __IM uint8_t RESERVED5[3];
13709 
13710     union
13711     {
13712         __IOM uint8_t ECCETST;         /*!< (@ 0x000000D4) ECC Test Control Register                                  */
13713 
13714         struct
13715         {
13716             __IOM uint8_t TSTBYP : 1;  /*!< [0..0] ECC Bypass Select                                                  */
13717             uint8_t              : 7;
13718         } ECCETST_b;
13719     };
13720     __IM uint8_t RESERVED6[3];
13721 
13722     union
13723     {
13724         __IOM uint8_t ECCOAD;          /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register          */
13725 
13726         struct
13727         {
13728             __IOM uint8_t OAD : 1;     /*!< [0..0] Operation after Detection                                          */
13729             uint8_t           : 7;
13730         } ECCOAD_b;
13731     };
13732 } R_SRAM_Type;                         /*!< Size = 217 (0xd9)                                                         */
13733 
13734 /* =========================================================================================================================== */
13735 /* ================                                          R_SSI0                                           ================ */
13736 /* =========================================================================================================================== */
13737 
13738 /**
13739  * @brief Serial Sound Interface Enhanced (SSIE) (R_SSI0)
13740  */
13741 
13742 typedef struct                         /*!< (@ 0x4009D000) R_SSI0 Structure                                           */
13743 {
13744     union
13745     {
13746         __IOM uint32_t SSICR;          /*!< (@ 0x00000000) Control Register                                           */
13747 
13748         struct
13749         {
13750             __IOM uint32_t REN  : 1;   /*!< [0..0] Receive Enable                                                     */
13751             __IOM uint32_t TEN  : 1;   /*!< [1..1] Transmit Enable                                                    */
13752             uint32_t            : 1;
13753             __IOM uint32_t MUEN : 1;   /*!< [3..3] Mute EnableNOTE: When this module is muted, the value
13754                                         *   of outputting serial data is rewritten to 0 but data transmission
13755                                         *   is not stopped. Write dummy data to the SSIFTDR not to
13756                                         *   generate a transmit underflow because the number of data
13757                                         *   in the transmit FIFO is decreasing.                                       */
13758             __IOM uint32_t CKDV  : 4;  /*!< [7..4] Serial Oversampling Clock Division Ratio                           */
13759             __IOM uint32_t DEL   : 1;  /*!< [8..8] Serial Data Delay                                                  */
13760             __IOM uint32_t PDTA  : 1;  /*!< [9..9] Parallel Data Alignment                                            */
13761             __IOM uint32_t SDTA  : 1;  /*!< [10..10] Serial Data Alignment                                            */
13762             __IOM uint32_t SPDP  : 1;  /*!< [11..11] Serial Padding Polarity                                          */
13763             __IOM uint32_t LRCKP : 1;  /*!< [12..12] Serial WS Polarity                                               */
13764             __IOM uint32_t BCKP  : 1;  /*!< [13..13] Serial Bit Clock Polarity                                        */
13765             __IOM uint32_t MST   : 1;  /*!< [14..14] Serial WS Direction NOTE: Only the following settings
13766                                         *   are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
13767                                         *   are prohibited.                                                           */
13768             uint32_t           : 1;
13769             __IOM uint32_t SWL : 3;    /*!< [18..16] System Word LengthSet the system word length to the
13770                                         *   bit clock frequency/2 fs.                                                 */
13771             __IOM uint32_t DWL   : 3;  /*!< [21..19] Data Word Length                                                 */
13772             __IOM uint32_t FRM   : 2;  /*!< [23..22] Channels                                                         */
13773             uint32_t             : 1;
13774             __IOM uint32_t IIEN  : 1;  /*!< [25..25] Idle Mode Interrupt Enable                                       */
13775             __IOM uint32_t ROIEN : 1;  /*!< [26..26] Receive Overflow Interrupt Enable                                */
13776             __IOM uint32_t RUIEN : 1;  /*!< [27..27] Receive Underflow Interrupt Enable                               */
13777             __IOM uint32_t TOIEN : 1;  /*!< [28..28] Transmit Overflow Interrupt Enable                               */
13778             __IOM uint32_t TUIEN : 1;  /*!< [29..29] Transmit Underflow Interrupt Enable                              */
13779             __IOM uint32_t CKS   : 1;  /*!< [30..30] Oversampling Clock Select                                        */
13780             uint32_t             : 1;
13781         } SSICR_b;
13782     };
13783 
13784     union
13785     {
13786         __IOM uint32_t SSISR;          /*!< (@ 0x00000004) Status Register                                            */
13787 
13788         struct
13789         {
13790             __IM uint32_t IDST   : 1;  /*!< [0..0] Idle Mode Status Flag                                              */
13791             __IM uint32_t RSWNO  : 1;  /*!< [1..1] Receive Serial Word Number                                         */
13792             __IM uint32_t RCHNO  : 2;  /*!< [3..2] Receive Channel Number.These bits are read as 00b.                 */
13793             __IM uint32_t TSWNO  : 1;  /*!< [4..4] Transmit Serial Word Number                                        */
13794             __IM uint32_t TCHNO  : 2;  /*!< [6..5] Transmit Channel Number                                            */
13795             uint32_t             : 18;
13796             __IM uint32_t  IIRQ  : 1;  /*!< [25..25] Idle Mode Interrupt Status Flag                                  */
13797             __IOM uint32_t ROIRQ : 1;  /*!< [26..26] Receive Overflow Error Interrupt Status Flag NOTE:
13798                                         *   Writable only to clear the flag. Confirm the value is 1
13799                                         *   and then write 0.                                                         */
13800             __IOM uint32_t RUIRQ : 1;  /*!< [27..27] Receive Underflow Error Interrupt Status Flag NOTE:
13801                                         *   Writable only to clear the flag. Confirm the value is 1
13802                                         *   and then write 0.                                                         */
13803             __IOM uint32_t TOIRQ : 1;  /*!< [28..28] Transmit Overflow Error Interrupt Status Flag NOTE:
13804                                         *   Writable only to clear the flag. Confirm the value is 1
13805                                         *   and then write 0.                                                         */
13806             __IOM uint32_t TUIRQ : 1;  /*!< [29..29] Transmit Underflow Error Interrupt Status Flag NOTE:
13807                                         *   Writable only to clear the flag. Confirm the value is 1
13808                                         *   and then write 0.                                                         */
13809             uint32_t : 2;
13810         } SSISR_b;
13811     };
13812     __IM uint32_t RESERVED[2];
13813 
13814     union
13815     {
13816         __IOM uint32_t SSIFCR;         /*!< (@ 0x00000010) FIFO Control Register                                      */
13817 
13818         struct
13819         {
13820             __IOM uint32_t RFRST : 1;  /*!< [0..0] Receive FIFO Data Register Reset                                   */
13821             __IOM uint32_t TFRST : 1;  /*!< [1..1] Transmit FIFO Data Register Reset                                  */
13822             __IOM uint32_t RIE   : 1;  /*!< [2..2] Receive Interrupt Enable NOTE: RXI can be cleared by
13823                                         *   clearing either the RDF flag (see the description of the
13824                                         *   RDF bit for details) or RIE bit.                                          */
13825             __IOM uint32_t TIE : 1;    /*!< [3..3] Transmit Interrupt Enable NOTE: TXI can be cleared by
13826                                         *   clearing either the TDE flag (see the description of the
13827                                         *   TDE bit for details) or TIE bit.                                          */
13828             __IOM uint32_t RTRG : 2;   /*!< [5..4] Receive Data Trigger Number                                        */
13829             __IOM uint32_t TTRG : 2;   /*!< [7..6] Transmit Data Trigger Number NOTE: The values in parenthesis
13830                                         *   are the number of empty stages in SSIFTDR at which the
13831                                         *   TDE flag is set.                                                          */
13832             uint32_t              : 3;
13833             __IOM uint32_t BSW    : 1; /*!< [11..11] Byte Swap Enable                                                 */
13834             uint32_t              : 4;
13835             __IOM uint32_t SSIRST : 1; /*!< [16..16] SSI soft ware reset                                              */
13836             uint32_t              : 14;
13837             __IOM uint32_t AUCKE  : 1; /*!< [31..31] Oversampling Clock Enable                                        */
13838         } SSIFCR_b;
13839     };
13840 
13841     union
13842     {
13843         __IOM uint32_t SSIFSR;         /*!< (@ 0x00000014) FIFO Status Register                                       */
13844 
13845         struct
13846         {
13847             __IOM uint32_t RDF : 1;    /*!< [0..0] Receive Data Full Flag NOTE: Since the SSIFRDR register
13848                                         *   is a 32-byte FIFO register, the maximum number of data
13849                                         *   bytes that can be read from it while the RDF flag is 1
13850                                         *   is indicated in the RDC[3:0] flags. If reading data from
13851                                         *   the SSIFRDR register is continued after all the data is
13852                                         *   read, undefined values will be read.                                      */
13853             uint32_t          : 7;
13854             __IM uint32_t RDC : 6;     /*!< [13..8] Receive Data Indicate Flag(Indicates the number of data
13855                                         *   units stored in SSIFRDR)                                                  */
13856             uint32_t           : 2;
13857             __IOM uint32_t TDE : 1;    /*!< [16..16] Transmit Data Empty Flag NOTE: Since the SSIFTDR register
13858                                         *   is a 32-byte FIFO register, the maximum number of bytes
13859                                         *   that can be written to it while the TDE flag is 1 is 8
13860                                         *   - TDC[3:0]. If writing data to the SSIFTDR register is
13861                                         *   continued after all the data is written, writing will be
13862                                         *   invalid and an overflow occurs.                                           */
13863             uint32_t          : 7;
13864             __IM uint32_t TDC : 6;     /*!< [29..24] Transmit Data Indicate Flag(Indicates the number of
13865                                         *   data units stored in SSIFTDR)                                             */
13866             uint32_t : 2;
13867         } SSIFSR_b;
13868     };
13869 
13870     union
13871     {
13872         union
13873         {
13874             __OM uint32_t SSIFTDR;          /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
13875 
13876             struct
13877             {
13878                 __OM uint32_t SSIFTDR : 32; /*!< [31..0] SSIFTDR is a write-only FIFO register consisting of
13879                                              *   eight stages of 32-bit registers for storing data to be
13880                                              *   serially transmitted. NOTE: that when the SSIFTDR register
13881                                              *   is full of data (32 bytes), the next data cannot be written
13882                                              *   to it. If writing is attempted, it will be ignored and
13883                                              *   an overflow occurs.                                                       */
13884             } SSIFTDR_b;
13885         };
13886         __OM uint16_t SSIFTDR16;            /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
13887         __OM uint8_t  SSIFTDR8;             /*!< (@ 0x00000018) Transmit FIFO Data Register                                */
13888     };
13889 
13890     union
13891     {
13892         union
13893         {
13894             __IM uint32_t SSIFRDR;          /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
13895 
13896             struct
13897             {
13898                 __IM uint32_t SSIFRDR : 32; /*!< [31..0] SSIFRDR is a read-only FIFO register consisting of eight
13899                                              *   stages of 32-bit registers for storing serially received
13900                                              *   data.                                                                     */
13901             } SSIFRDR_b;
13902         };
13903         __IM uint16_t SSIFRDR16;            /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
13904         __IM uint8_t  SSIFRDR8;             /*!< (@ 0x0000001C) Receive FIFO Data Register                                 */
13905     };
13906 
13907     union
13908     {
13909         __IOM uint32_t SSIOFR;          /*!< (@ 0x00000020) Audio Format Register                                      */
13910 
13911         struct
13912         {
13913             __IOM uint32_t OMOD    : 2; /*!< [1..0] Audio Format Select                                                */
13914             uint32_t               : 6;
13915             __IOM uint32_t LRCONT  : 1; /*!< [8..8] Whether to Enable LRCK/FS Continuation                             */
13916             __IOM uint32_t BCKASTP : 1; /*!< [9..9] Whether to Enable Stopping BCK Output When SSIE is in
13917                                          *   Idle Status                                                               */
13918             uint32_t : 22;
13919         } SSIOFR_b;
13920     };
13921 
13922     union
13923     {
13924         __IOM uint32_t SSISCR;         /*!< (@ 0x00000024) Status Control Register                                    */
13925 
13926         struct
13927         {
13928             __IOM uint32_t RDFS : 5;   /*!< [4..0] RDF Setting Condition Select                                       */
13929             uint32_t            : 3;
13930             __IOM uint32_t TDES : 5;   /*!< [12..8] TDE Setting Condition Select                                      */
13931             uint32_t            : 19;
13932         } SSISCR_b;
13933     };
13934 } R_SSI0_Type;                         /*!< Size = 40 (0x28)                                                          */
13935 
13936 /* =========================================================================================================================== */
13937 /* ================                                         R_SYSTEM                                          ================ */
13938 /* =========================================================================================================================== */
13939 
13940 /**
13941  * @brief System Pins (R_SYSTEM)
13942  */
13943 
13944 typedef struct                         /*!< (@ 0x4001E000) R_SYSTEM Structure                                         */
13945 {
13946     __IM uint32_t RESERVED[3];
13947 
13948     union
13949     {
13950         __IOM uint16_t SBYCR;          /*!< (@ 0x0000000C) Standby Control Register                                   */
13951 
13952         struct
13953         {
13954             uint16_t            : 14;
13955             __IOM uint16_t OPE  : 1;   /*!< [14..14] Output Port Enable                                               */
13956             __IOM uint16_t SSBY : 1;   /*!< [15..15] Software Standby                                                 */
13957         } SBYCR_b;
13958     };
13959     __IM uint16_t RESERVED1;
13960     __IM uint32_t RESERVED2[3];
13961 
13962     union
13963     {
13964         __IOM uint32_t MSTPCRA;         /*!< (@ 0x0000001C) Module Stop Control Register A                             */
13965 
13966         struct
13967         {
13968             __IOM uint32_t MSTPA0  : 1; /*!< [0..0] Module Stop bit 0. See device hardware manual for usage.           */
13969             __IOM uint32_t MSTPA1  : 1; /*!< [1..1] Module Stop bit 1. See device hardware manual for usage.           */
13970             __IOM uint32_t MSTPA2  : 1; /*!< [2..2] Module Stop bit 2. See device hardware manual for usage.           */
13971             __IOM uint32_t MSTPA3  : 1; /*!< [3..3] Module Stop bit 3. See device hardware manual for usage.           */
13972             __IOM uint32_t MSTPA4  : 1; /*!< [4..4] Module Stop bit 4. See device hardware manual for usage.           */
13973             __IOM uint32_t MSTPA5  : 1; /*!< [5..5] Module Stop bit 5. See device hardware manual for usage.           */
13974             __IOM uint32_t MSTPA6  : 1; /*!< [6..6] Module Stop bit 6. See device hardware manual for usage.           */
13975             __IOM uint32_t MSTPA7  : 1; /*!< [7..7] Module Stop bit 7. See device hardware manual for usage.           */
13976             __IOM uint32_t MSTPA8  : 1; /*!< [8..8] Module Stop bit 8. See device hardware manual for usage.           */
13977             __IOM uint32_t MSTPA9  : 1; /*!< [9..9] Module Stop bit 9. See device hardware manual for usage.           */
13978             __IOM uint32_t MSTPA10 : 1; /*!< [10..10] Module Stop bit 10. See device hardware manual for
13979                                          *   usage.                                                                    */
13980             __IOM uint32_t MSTPA11 : 1; /*!< [11..11] Module Stop bit 11. See device hardware manual for
13981                                          *   usage.                                                                    */
13982             __IOM uint32_t MSTPA12 : 1; /*!< [12..12] Module Stop bit 12. See device hardware manual for
13983                                          *   usage.                                                                    */
13984             __IOM uint32_t MSTPA13 : 1; /*!< [13..13] Module Stop bit 13. See device hardware manual for
13985                                          *   usage.                                                                    */
13986             __IOM uint32_t MSTPA14 : 1; /*!< [14..14] Module Stop bit 14. See device hardware manual for
13987                                          *   usage.                                                                    */
13988             __IOM uint32_t MSTPA15 : 1; /*!< [15..15] Module Stop bit 15. See device hardware manual for
13989                                          *   usage.                                                                    */
13990             __IOM uint32_t MSTPA16 : 1; /*!< [16..16] Module Stop bit 16. See device hardware manual for
13991                                          *   usage.                                                                    */
13992             __IOM uint32_t MSTPA17 : 1; /*!< [17..17] Module Stop bit 17. See device hardware manual for
13993                                          *   usage.                                                                    */
13994             __IOM uint32_t MSTPA18 : 1; /*!< [18..18] Module Stop bit 18. See device hardware manual for
13995                                          *   usage.                                                                    */
13996             __IOM uint32_t MSTPA19 : 1; /*!< [19..19] Module Stop bit 19. See device hardware manual for
13997                                          *   usage.                                                                    */
13998             __IOM uint32_t MSTPA20 : 1; /*!< [20..20] Module Stop bit 20. See device hardware manual for
13999                                          *   usage.                                                                    */
14000             __IOM uint32_t MSTPA21 : 1; /*!< [21..21] Module Stop bit 21. See device hardware manual for
14001                                          *   usage.                                                                    */
14002             __IOM uint32_t MSTPA22 : 1; /*!< [22..22] Module Stop bit 22. See device hardware manual for
14003                                          *   usage.                                                                    */
14004             __IOM uint32_t MSTPA23 : 1; /*!< [23..23] Module Stop bit 23. See device hardware manual for
14005                                          *   usage.                                                                    */
14006             __IOM uint32_t MSTPA24 : 1; /*!< [24..24] Module Stop bit 24. See device hardware manual for
14007                                          *   usage.                                                                    */
14008             __IOM uint32_t MSTPA25 : 1; /*!< [25..25] Module Stop bit 25. See device hardware manual for
14009                                          *   usage.                                                                    */
14010             __IOM uint32_t MSTPA26 : 1; /*!< [26..26] Module Stop bit 26. See device hardware manual for
14011                                          *   usage.                                                                    */
14012             __IOM uint32_t MSTPA27 : 1; /*!< [27..27] Module Stop bit 27. See device hardware manual for
14013                                          *   usage.                                                                    */
14014             __IOM uint32_t MSTPA28 : 1; /*!< [28..28] Module Stop bit 28. See device hardware manual for
14015                                          *   usage.                                                                    */
14016             __IOM uint32_t MSTPA29 : 1; /*!< [29..29] Module Stop bit 29. See device hardware manual for
14017                                          *   usage.                                                                    */
14018             __IOM uint32_t MSTPA30 : 1; /*!< [30..30] Module Stop bit 30. See device hardware manual for
14019                                          *   usage.                                                                    */
14020             __IOM uint32_t MSTPA31 : 1; /*!< [31..31] Module Stop bit 31. See device hardware manual for
14021                                          *   usage.                                                                    */
14022         } MSTPCRA_b;
14023     };
14024 
14025     union
14026     {
14027         __IOM uint32_t SCKDIVCR;       /*!< (@ 0x00000020) System Clock Division Control Register                     */
14028 
14029         struct
14030         {
14031             __IOM uint32_t PCKD : 3;   /*!< [2..0] Peripheral Module Clock D (PCLKD) Select                           */
14032             uint32_t            : 1;
14033             __IOM uint32_t PCKC : 3;   /*!< [6..4] Peripheral Module Clock C (PCLKC) Select                           */
14034             uint32_t            : 1;
14035             __IOM uint32_t PCKB : 3;   /*!< [10..8] Peripheral Module Clock B (PCLKB) Select                          */
14036             uint32_t            : 1;
14037             __IOM uint32_t PCKA : 3;   /*!< [14..12] Peripheral Module Clock A (PCLKA) Select                         */
14038             uint32_t            : 1;
14039             __IOM uint32_t BCK  : 3;   /*!< [18..16] External Bus Clock (BCLK) Select                                 */
14040             uint32_t            : 5;
14041             __IOM uint32_t ICK  : 3;   /*!< [26..24] System Clock (ICLK) Select                                       */
14042             uint32_t            : 1;
14043             __IOM uint32_t FCK  : 3;   /*!< [30..28] Flash IF Clock (FCLK) Select                                     */
14044             uint32_t            : 1;
14045         } SCKDIVCR_b;
14046     };
14047 
14048     union
14049     {
14050         __IOM uint8_t SCKDIVCR2;       /*!< (@ 0x00000024) System Clock Division Control Register 2                   */
14051 
14052         struct
14053         {
14054             uint8_t           : 4;
14055             __IOM uint8_t UCK : 3;     /*!< [6..4] USB Clock (UCLK) Select                                            */
14056             uint8_t           : 1;
14057         } SCKDIVCR2_b;
14058     };
14059     __IM uint8_t RESERVED3;
14060 
14061     union
14062     {
14063         __IOM uint8_t SCKSCR;          /*!< (@ 0x00000026) System Clock Source Control Register                       */
14064 
14065         struct
14066         {
14067             __IOM uint8_t CKSEL : 3;   /*!< [2..0] Clock Source Select                                                */
14068             uint8_t             : 5;
14069         } SCKSCR_b;
14070     };
14071     __IM uint8_t RESERVED4;
14072 
14073     union
14074     {
14075         __IOM uint16_t PLLCCR;           /*!< (@ 0x00000028) PLL Clock Control Register                                 */
14076 
14077         struct
14078         {
14079             __IOM uint16_t PLIDIV   : 2; /*!< [1..0] PLL Input Frequency Division Ratio Select                          */
14080             uint16_t                : 2;
14081             __IOM uint16_t PLSRCSEL : 1; /*!< [4..4] PLL Clock Source Select                                            */
14082             uint16_t                : 3;
14083             __IOM uint16_t PLLMUL   : 6; /*!< [13..8] PLL Frequency Multiplication Factor Select [PLL Frequency
14084                                           *   Multiplication Factor] = (PLLUMUL+1) / 2 Range: 0x23 -
14085                                           *   0x3B for example 010011: x10.0 010100: x10.5 010101: x11.0
14086                                           *   : 011100: x14.5 011101: x15.0 011110: x15.5 : 111010: x29.5
14087                                           *   111011: x30.0                                                             */
14088             uint16_t : 2;
14089         } PLLCCR_b;
14090     };
14091 
14092     union
14093     {
14094         __IOM uint8_t PLLCR;           /*!< (@ 0x0000002A) PLL Control Register                                       */
14095 
14096         struct
14097         {
14098             __IOM uint8_t PLLSTP : 1;  /*!< [0..0] PLL Stop Control                                                   */
14099             uint8_t              : 7;
14100         } PLLCR_b;
14101     };
14102 
14103     union
14104     {
14105         __IOM uint8_t PLLCCR2;         /*!< (@ 0x0000002B) PLL Clock Control Register2                                */
14106 
14107         struct
14108         {
14109             __IOM uint8_t PLLMUL : 5;  /*!< [4..0] PLL Frequency Multiplication Factor Select                         */
14110             uint8_t              : 1;
14111             __IOM uint8_t PLODIV : 2;  /*!< [7..6] PLL Output Frequency Division Ratio Select                         */
14112         } PLLCCR2_b;
14113     };
14114     __IM uint32_t RESERVED5;
14115 
14116     union
14117     {
14118         __IOM uint8_t BCKCR;           /*!< (@ 0x00000030) External Bus Clock Control Register                        */
14119 
14120         struct
14121         {
14122             __IOM uint8_t BCLKDIV : 1; /*!< [0..0] BCLK Pin Output Select                                             */
14123             uint8_t               : 7;
14124         } BCKCR_b;
14125     };
14126 
14127     union
14128     {
14129         __IOM uint8_t MEMWAIT;         /*!< (@ 0x00000031) Memory Wait Cycle Control Register                         */
14130 
14131         struct
14132         {
14133             __IOM uint8_t MEMWAIT : 1; /*!< [0..0] Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT
14134                                         *   is prohibited when SCKDIVCR.ICK selects division by 1 and
14135                                         *   SCKSCR.CKSEL[2:0] bits select thesystem clock source that
14136                                         *   is faster than 32 MHz (ICLK > 32 MHz).                                    */
14137             uint8_t : 7;
14138         } MEMWAIT_b;
14139     };
14140 
14141     union
14142     {
14143         __IOM uint8_t MOSCCR;          /*!< (@ 0x00000032) Main Clock Oscillator Control Register                     */
14144 
14145         struct
14146         {
14147             __IOM uint8_t MOSTP : 1;   /*!< [0..0] Main Clock Oscillator Stop                                         */
14148             uint8_t             : 7;
14149         } MOSCCR_b;
14150     };
14151     __IM uint8_t  RESERVED6;
14152     __IM uint16_t RESERVED7;
14153 
14154     union
14155     {
14156         __IOM uint8_t HOCOCR;          /*!< (@ 0x00000036) High-Speed On-Chip Oscillator Control Register             */
14157 
14158         struct
14159         {
14160             __IOM uint8_t HCSTP : 1;   /*!< [0..0] HOCO Stop                                                          */
14161             uint8_t             : 7;
14162         } HOCOCR_b;
14163     };
14164 
14165     union
14166     {
14167         __IOM uint8_t HOCOCR2;         /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
14168                                         *                  2                                                          */
14169 
14170         struct
14171         {
14172             __IOM uint8_t HCFRQ0 : 2;  /*!< [1..0] HOCO Frequency Setting 0                                           */
14173             uint8_t              : 1;
14174             __IOM uint8_t HCFRQ1 : 3;  /*!< [5..3] HOCO Frequency Setting 1                                           */
14175             uint8_t              : 2;
14176         } HOCOCR2_b;
14177     };
14178 
14179     union
14180     {
14181         __IOM uint8_t MOCOCR;          /*!< (@ 0x00000038) Middle-Speed On-Chip Oscillator Control Register           */
14182 
14183         struct
14184         {
14185             __IOM uint8_t MCSTP : 1;   /*!< [0..0] MOCO Stop                                                          */
14186             uint8_t             : 7;
14187         } MOCOCR_b;
14188     };
14189 
14190     union
14191     {
14192         __IOM uint8_t FLLCR1;          /*!< (@ 0x00000039) FLL Control Register 1                                     */
14193 
14194         struct
14195         {
14196             __IOM uint8_t FLLEN : 1;   /*!< [0..0] FLL Enable                                                         */
14197             uint8_t             : 7;
14198         } FLLCR1_b;
14199     };
14200 
14201     union
14202     {
14203         __IOM uint16_t FLLCR2;           /*!< (@ 0x0000003A) FLL Control Register 2                                     */
14204 
14205         struct
14206         {
14207             __IOM uint16_t FLLCNTL : 11; /*!< [10..0] FLL Multiplication ControlMultiplication ratio of the
14208                                           *   FLL reference clock select                                                */
14209             uint16_t : 5;
14210         } FLLCR2_b;
14211     };
14212 
14213     union
14214     {
14215         __IM uint8_t OSCSF;            /*!< (@ 0x0000003C) Oscillation Stabilization Flag Register                    */
14216 
14217         struct
14218         {
14219             __IM uint8_t HOCOSF : 1;   /*!< [0..0] HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF
14220                                         *   bit value after a reset is 1 when the OFS1.HOCOEN bit is
14221                                         *   0. It is 0 when the OFS1.HOCOEN bit is 1.                                 */
14222             uint8_t             : 2;
14223             __IM uint8_t MOSCSF : 1;   /*!< [3..3] Main Clock Oscillation Stabilization Flag                          */
14224             uint8_t             : 1;
14225             __IM uint8_t PLLSF  : 1;   /*!< [5..5] PLL Clock Oscillation Stabilization Flag                           */
14226             __IM uint8_t PLL2SF : 1;   /*!< [6..6] PLL2 Clock Oscillation Stabilization Flag                          */
14227             uint8_t             : 1;
14228         } OSCSF_b;
14229     };
14230     __IM uint8_t RESERVED8;
14231 
14232     union
14233     {
14234         __IOM uint8_t CKOCR;           /*!< (@ 0x0000003E) Clock Out Control Register                                 */
14235 
14236         struct
14237         {
14238             __IOM uint8_t CKOSEL : 3;  /*!< [2..0] Clock out source select                                            */
14239             uint8_t              : 1;
14240             __IOM uint8_t CKODIV : 3;  /*!< [6..4] Clock out input frequency Division Select                          */
14241             __IOM uint8_t CKOEN  : 1;  /*!< [7..7] Clock out enable                                                   */
14242         } CKOCR_b;
14243     };
14244 
14245     union
14246     {
14247         __IOM uint8_t TRCKCR;          /*!< (@ 0x0000003F) Trace Clock Control Register                               */
14248 
14249         struct
14250         {
14251             __IOM uint8_t TRCK   : 4;  /*!< [3..0] Trace Clock operating frequency select                             */
14252             uint8_t              : 3;
14253             __IOM uint8_t TRCKEN : 1;  /*!< [7..7] Trace Clock operating Enable                                       */
14254         } TRCKCR_b;
14255     };
14256 
14257     union
14258     {
14259         __IOM uint8_t OSTDCR;          /*!< (@ 0x00000040) Oscillation Stop Detection Control Register                */
14260 
14261         struct
14262         {
14263             __IOM uint8_t OSTDIE : 1;  /*!< [0..0] Oscillation Stop Detection Interrupt Enable                        */
14264             uint8_t              : 6;
14265             __IOM uint8_t OSTDE  : 1;  /*!< [7..7] Oscillation Stop Detection Function Enable                         */
14266         } OSTDCR_b;
14267     };
14268 
14269     union
14270     {
14271         __IOM uint8_t OSTDSR;          /*!< (@ 0x00000041) Oscillation Stop Detection Status Register                 */
14272 
14273         struct
14274         {
14275             __IOM uint8_t OSTDF : 1;   /*!< [0..0] Oscillation Stop Detection Flag                                    */
14276             uint8_t             : 7;
14277         } OSTDSR_b;
14278     };
14279     __IM uint16_t RESERVED9;
14280     __IM uint32_t RESERVED10;
14281 
14282     union
14283     {
14284         __IOM uint16_t PLL2CCR;           /*!< (@ 0x00000048) PLL2 Clock Control Register                                */
14285 
14286         struct
14287         {
14288             __IOM uint16_t PL2IDIV   : 2; /*!< [1..0] PLL2 Input Frequency Division Ratio Select                         */
14289             uint16_t                 : 2;
14290             __IOM uint16_t PL2SRCSEL : 1; /*!< [4..4] PLL2 Clock Source Select                                           */
14291             uint16_t                 : 3;
14292             __IOM uint16_t PLL2MUL   : 6; /*!< [13..8] PLL2 Frequency Multiplication Factor Select                       */
14293             uint16_t                 : 2;
14294         } PLL2CCR_b;
14295     };
14296 
14297     union
14298     {
14299         __IOM uint8_t PLL2CR;          /*!< (@ 0x0000004A) PLL2 Control Register                                      */
14300 
14301         struct
14302         {
14303             __IOM uint8_t PLL2STP : 1; /*!< [0..0] PLL2 Stop Control                                                  */
14304             uint8_t               : 7;
14305         } PLL2CR_b;
14306     };
14307     __IM uint8_t RESERVED11;
14308 
14309     union
14310     {
14311         __IOM uint8_t LPOPT;             /*!< (@ 0x0000004C) Lower Power Operation Control Register                     */
14312 
14313         struct
14314         {
14315             __IOM uint8_t MPUDIS : 1;    /*!< [0..0] MPU Clock Disable Control. Stop the MPU operate clock
14316                                           *   (valid only when LPOPTEN = 1)                                             */
14317             __IOM uint8_t DCLKDIS   : 2; /*!< [2..1] Debug Clock Disable Control                                        */
14318             __IOM uint8_t BPFCLKDIS : 1; /*!< [3..3] BPF Clock Disable Control. Stop the Flash register R/W
14319                                           *   clock (valid only when LPOPT.LPOPTEN = 1)                                 */
14320             uint8_t               : 3;
14321             __IOM uint8_t LPOPTEN : 1;   /*!< [7..7] Lower Power Operation Enable                                       */
14322         } LPOPT_b;
14323     };
14324     __IM uint8_t  RESERVED12;
14325     __IM uint16_t RESERVED13;
14326 
14327     union
14328     {
14329         __IOM uint8_t SLCDSCKCR;         /*!< (@ 0x00000050) Segment LCD Source Clock Control Register                  */
14330 
14331         struct
14332         {
14333             __IOM uint8_t LCDSCKSEL : 3; /*!< [2..0] LCD Source Clock (LCDSRCCLK) Select                                */
14334             uint8_t                 : 4;
14335             __IOM uint8_t LCDSCKEN  : 1; /*!< [7..7] LCD Source Clock Out Enable                                        */
14336         } SLCDSCKCR_b;
14337     };
14338     __IM uint8_t RESERVED14;
14339 
14340     union
14341     {
14342         __IOM uint8_t EBCKOCR;         /*!< (@ 0x00000052) External Bus Clock Output Control Register                 */
14343 
14344         struct
14345         {
14346             __IOM uint8_t EBCKOEN : 1; /*!< [0..0] BCLK Pin Output Control                                            */
14347             uint8_t               : 7;
14348         } EBCKOCR_b;
14349     };
14350 
14351     union
14352     {
14353         __IOM uint8_t SDCKOCR;         /*!< (@ 0x00000053) SDRAM Clock Output Control Register                        */
14354 
14355         struct
14356         {
14357             __IOM uint8_t SDCKOEN : 1; /*!< [0..0] SDCLK Pin Output Control                                           */
14358             uint8_t               : 7;
14359         } SDCKOCR_b;
14360     };
14361     __IM uint32_t RESERVED15[3];
14362     __IM uint8_t  RESERVED16;
14363 
14364     union
14365     {
14366         __IOM uint8_t MOCOUTCR;         /*!< (@ 0x00000061) MOCO User Trimming Control Register                        */
14367 
14368         struct
14369         {
14370             __IOM uint8_t MOCOUTRM : 8; /*!< [7..0] MOCO User Trimming 1000_0000 : -128 1000_0001 : -127
14371                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
14372                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
14373                                          +126 0111_1111 : +127These bits are added to original MOCO
14374                                          *   trimming bits                                                             */
14375         } MOCOUTCR_b;
14376     };
14377 
14378     union
14379     {
14380         __IOM uint8_t HOCOUTCR;         /*!< (@ 0x00000062) HOCO User Trimming Control Register                        */
14381 
14382         struct
14383         {
14384             __IOM uint8_t HOCOUTRM : 8; /*!< [7..0] HOCO User Trimming 1000_0000 : -128 1000_0001 : -127
14385                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
14386                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
14387                                          +126 0111_1111 : +127These bits are added to original HOCO
14388                                          *   trimming bits                                                             */
14389         } HOCOUTCR_b;
14390     };
14391     __IM uint8_t  RESERVED17;
14392     __IM uint32_t RESERVED18[2];
14393 
14394     union
14395     {
14396         __IOM uint8_t USBCKDIVCR;       /*!< (@ 0x0000006C) USB Clock Division Control Register                        */
14397 
14398         struct
14399         {
14400             __IOM uint8_t USBCKDIV : 3; /*!< [2..0] USB Clock (USBCLK) Division Select                                 */
14401             uint8_t                : 5;
14402         } USBCKDIVCR_b;
14403     };
14404 
14405     union
14406     {
14407         union
14408         {
14409             __IOM uint8_t OCTACKDIVCR;       /*!< (@ 0x0000006D) Octal-SPI Clock Division Control Register                  */
14410 
14411             struct
14412             {
14413                 __IOM uint8_t OCTACKDIV : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Division Select                          */
14414                 uint8_t                 : 5;
14415             } OCTACKDIVCR_b;
14416         };
14417 
14418         union
14419         {
14420             __IOM uint8_t SCISPICKDIVCR;       /*!< (@ 0x0000006D) SCI SPI Clock Division Control Register                    */
14421 
14422             struct
14423             {
14424                 __IOM uint8_t SCISPICKDIV : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Division Select                          */
14425                 uint8_t                   : 5;
14426             } SCISPICKDIVCR_b;
14427         };
14428     };
14429 
14430     union
14431     {
14432         __IOM uint8_t CANFDCKDIVCR;       /*!< (@ 0x0000006E) CANFD Clock Division Control Register                      */
14433 
14434         struct
14435         {
14436             __IOM uint8_t CANFDCKDIV : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Division Select                             */
14437             uint8_t                  : 5;
14438         } CANFDCKDIVCR_b;
14439     };
14440 
14441     union
14442     {
14443         union
14444         {
14445             __IOM uint8_t GPTCKDIVCR;       /*!< (@ 0x0000006F) GPT Clock Division Control Register                        */
14446 
14447             struct
14448             {
14449                 __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select                                 */
14450                 uint8_t                : 5;
14451             } GPTCKDIVCR_b;
14452         };
14453 
14454         union
14455         {
14456             __IOM uint8_t USB60CKDIVCR;       /*!< (@ 0x0000006F) USB60 Clock Division Control Register                      */
14457 
14458             struct
14459             {
14460                 __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select                               */
14461                 uint8_t                  : 5;
14462             } USB60CKDIVCR_b;
14463         };
14464     };
14465 
14466     union
14467     {
14468         union
14469         {
14470             __IOM uint8_t CECCKDIVCR;       /*!< (@ 0x00000070) CEC Clock Division Control Register                        */
14471 
14472             struct
14473             {
14474                 __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select                                 */
14475                 uint8_t                : 5;
14476             } CECCKDIVCR_b;
14477         };
14478 
14479         union
14480         {
14481             __IOM uint8_t IICCKDIVCR;       /*!< (@ 0x00000070) IIC Clock Division Control Register                        */
14482 
14483             struct
14484             {
14485                 __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select                                 */
14486                 uint8_t                : 5;
14487             } IICCKDIVCR_b;
14488         };
14489     };
14490 
14491     union
14492     {
14493         __IOM uint8_t I3CCKDIVCR;       /*!< (@ 0x00000071) I3C clock Division control register                        */
14494 
14495         struct
14496         {
14497             __IOM uint8_t I3CCKDIV : 3; /*!< [2..0] I3C clock (I3CCLK) Division Select                                 */
14498             uint8_t                : 5;
14499         } I3CCKDIVCR_b;
14500     };
14501     __IM uint16_t RESERVED19;
14502 
14503     union
14504     {
14505         __IOM uint8_t USBCKCR;           /*!< (@ 0x00000074) USB Clock Control Register                                 */
14506 
14507         struct
14508         {
14509             __IOM uint8_t USBCKSEL  : 3; /*!< [2..0] USB Clock (USBCLK) Source Select                                   */
14510             uint8_t                 : 3;
14511             __IOM uint8_t USBCKSREQ : 1; /*!< [6..6] USB Clock (USBCLK) Switching Request                               */
14512             __IM uint8_t  USBCKSRDY : 1; /*!< [7..7] USB Clock (USBCLK) Switching Ready state flag                      */
14513         } USBCKCR_b;
14514     };
14515 
14516     union
14517     {
14518         union
14519         {
14520             __IOM uint8_t OCTACKCR;           /*!< (@ 0x00000075) Octal-SPI Clock Control Register                           */
14521 
14522             struct
14523             {
14524                 __IOM uint8_t OCTACKSEL  : 3; /*!< [2..0] Octal-SPI Clock (OCTACLK) Source Select                            */
14525                 uint8_t                  : 3;
14526                 __IOM uint8_t OCTACKSREQ : 1; /*!< [6..6] Octal-SPI Clock (OCTACLK) Switching Request                        */
14527                 __IM uint8_t  OCTACKSRDY : 1; /*!< [7..7] Octal-SPI Clock (OCTACLK) Switching Ready state flag               */
14528             } OCTACKCR_b;
14529         };
14530 
14531         union
14532         {
14533             __IOM uint8_t SCISPICKCR;           /*!< (@ 0x00000075) SCI SPI Clock Control Register                             */
14534 
14535             struct
14536             {
14537                 __IOM uint8_t SCISPICKSEL  : 3; /*!< [2..0] SCI SPI Clock (SCISPICLK) Source Select                            */
14538                 uint8_t                    : 3;
14539                 __IOM uint8_t SCISPICKSREQ : 1; /*!< [6..6] SCI SPI Clock (SCISPICLK) Switching Request                        */
14540                 __IM uint8_t  SCISPICKSRDY : 1; /*!< [7..7] SCI SPI Clock (SCISPICLK) Switching Ready state flag               */
14541             } SCISPICKCR_b;
14542         };
14543     };
14544 
14545     union
14546     {
14547         __IOM uint8_t CANFDCKCR;           /*!< (@ 0x00000076) CANFD Clock Control Register                               */
14548 
14549         struct
14550         {
14551             __IOM uint8_t CANFDCKSEL  : 3; /*!< [2..0] CANFD Clock (CANFDCLK) Source Select                               */
14552             uint8_t                   : 3;
14553             __IOM uint8_t CANFDCKSREQ : 1; /*!< [6..6] CANFD Clock (CANFDCLK) Switching Request                           */
14554             __IM uint8_t  CANFDCKSRDY : 1; /*!< [7..7] CANFD Clock (CANFDCLK) Switching Ready state flag                  */
14555         } CANFDCKCR_b;
14556     };
14557 
14558     union
14559     {
14560         union
14561         {
14562             __IOM uint8_t GPTCKCR;           /*!< (@ 0x00000077) GPT Clock Control Register                                 */
14563 
14564             struct
14565             {
14566                 __IOM uint8_t GPTCKSEL  : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select                                   */
14567                 uint8_t                 : 3;
14568                 __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request                               */
14569                 __IM uint8_t  GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag                      */
14570             } GPTCKCR_b;
14571         };
14572 
14573         union
14574         {
14575             __IOM uint8_t USB60CKCR;           /*!< (@ 0x00000077) USB60 clock control register                               */
14576 
14577             struct
14578             {
14579                 __IOM uint8_t USB60CKSEL  : 4; /*!< [3..0] USB clock (USB60CLK) Source Select                                 */
14580                 uint8_t                   : 2;
14581                 __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request                             */
14582                 __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag                    */
14583             } USB60CKCR_b;
14584         };
14585     };
14586 
14587     union
14588     {
14589         union
14590         {
14591             __IOM uint8_t CECCKCR;           /*!< (@ 0x00000078) CEC Clock Control Register                                 */
14592 
14593             struct
14594             {
14595                 __IOM uint8_t CECCKSEL  : 3; /*!< [2..0] CEC clock (CECCLK) Source Select                                   */
14596                 uint8_t                 : 3;
14597                 __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request                               */
14598                 __IM uint8_t  CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag                      */
14599             } CECCKCR_b;
14600         };
14601 
14602         union
14603         {
14604             __IOM uint8_t IICCKCR;           /*!< (@ 0x00000078) IIC Clock Control Register                                 */
14605 
14606             struct
14607             {
14608                 __IOM uint8_t IICCKSEL  : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select                                   */
14609                 uint8_t                 : 3;
14610                 __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request                               */
14611                 __IM uint8_t  IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag                      */
14612             } IICCKCR_b;
14613         };
14614     };
14615 
14616     union
14617     {
14618         __IOM uint8_t I3CCKCR;           /*!< (@ 0x00000079) I3C Clock Control Register                                 */
14619 
14620         struct
14621         {
14622             __IOM uint8_t I3CCKSEL  : 3; /*!< [2..0] I3C clock (I3CCLK) source select                                   */
14623             uint8_t                 : 3;
14624             __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request                               */
14625             __IM uint8_t  I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag                      */
14626         } I3CCKCR_b;
14627     };
14628     __IM uint16_t RESERVED20;
14629     __IM uint32_t RESERVED21[3];
14630 
14631     union
14632     {
14633         __IOM uint32_t SNZREQCR1;         /*!< (@ 0x00000088) Snooze Request Control Register 1                          */
14634 
14635         struct
14636         {
14637             __IOM uint32_t SNZREQEN0 : 1; /*!< [0..0] Enable AGT3 underflow snooze request                               */
14638             __IOM uint32_t SNZREQEN1 : 1; /*!< [1..1] Enable AGT3 underflow snooze request                               */
14639             __IOM uint32_t SNZREQEN2 : 1; /*!< [2..2] Enable AGT3 underflow snooze request                               */
14640             uint32_t                 : 29;
14641         } SNZREQCR1_b;
14642     };
14643     __IM uint32_t RESERVED22;
14644     __IM uint16_t RESERVED23;
14645 
14646     union
14647     {
14648         __IOM uint8_t SNZCR;            /*!< (@ 0x00000092) Snooze Control Register                                    */
14649 
14650         struct
14651         {
14652             __IOM uint8_t RXDREQEN : 1; /*!< [0..0] RXD0 Snooze Request Enable NOTE: Do not set to 1 other
14653                                          *   than in asynchronous mode.                                                */
14654             __IOM uint8_t SNZDTCEN : 1; /*!< [1..1] DTC Enable in Snooze Mode                                          */
14655             uint8_t                : 5;
14656             __IOM uint8_t SNZE     : 1; /*!< [7..7] Snooze Mode Enable                                                 */
14657         } SNZCR_b;
14658     };
14659     __IM uint8_t RESERVED24;
14660 
14661     union
14662     {
14663         __IOM uint8_t SNZEDCR;           /*!< (@ 0x00000094) Snooze End Control Register                                */
14664 
14665         struct
14666         {
14667             __IOM uint8_t AGT1UNFED : 1; /*!< [0..0] AGT1 underflow Snooze End Enable                                   */
14668             __IOM uint8_t DTCZRED   : 1; /*!< [1..1] Last DTC transmission completion Snooze End Enable                 */
14669             __IOM uint8_t DTCNZRED  : 1; /*!< [2..2] Not Last DTC transmission completion Snooze End Enable             */
14670             __IOM uint8_t AD0MATED  : 1; /*!< [3..3] AD compare match 0 Snooze End Enable                               */
14671             __IOM uint8_t AD0UMTED  : 1; /*!< [4..4] AD compare mismatch 0 Snooze End Enable                            */
14672             __IOM uint8_t AD1MATED  : 1; /*!< [5..5] AD compare match 1 Snooze End Enable                               */
14673             __IOM uint8_t AD1UMTED  : 1; /*!< [6..6] AD compare mismatch 1 Snooze End Enable                            */
14674             __IOM uint8_t SCI0UMTED : 1; /*!< [7..7] SCI0 address unmatch Snooze End EnableNote: Do not set
14675                                           *   to 1 other than in asynchronous mode.                                     */
14676         } SNZEDCR_b;
14677     };
14678 
14679     union
14680     {
14681         __IOM uint8_t SNZEDCR1;          /*!< (@ 0x00000095) Snooze End Control Register 1                              */
14682 
14683         struct
14684         {
14685             __IOM uint8_t AGT3UNFED : 1; /*!< [0..0] AGT3 underflow Snooze End Enable                                   */
14686             uint8_t                 : 7;
14687         } SNZEDCR1_b;
14688     };
14689     __IM uint16_t RESERVED25;
14690 
14691     union
14692     {
14693         __IOM uint32_t SNZREQCR;           /*!< (@ 0x00000098) Snooze Request Control Register                            */
14694 
14695         struct
14696         {
14697             __IOM uint32_t SNZREQEN0  : 1; /*!< [0..0] Snooze Request Enable 0Enable IRQ 0 pin snooze request             */
14698             __IOM uint32_t SNZREQEN1  : 1; /*!< [1..1] Snooze Request Enable 0Enable IRQ 1 pin snooze request             */
14699             __IOM uint32_t SNZREQEN2  : 1; /*!< [2..2] Snooze Request Enable 0Enable IRQ 2 pin snooze request             */
14700             __IOM uint32_t SNZREQEN3  : 1; /*!< [3..3] Snooze Request Enable 0Enable IRQ 3 pin snooze request             */
14701             __IOM uint32_t SNZREQEN4  : 1; /*!< [4..4] Snooze Request Enable 0Enable IRQ 4 pin snooze request             */
14702             __IOM uint32_t SNZREQEN5  : 1; /*!< [5..5] Snooze Request Enable 0Enable IRQ 5 pin snooze request             */
14703             __IOM uint32_t SNZREQEN6  : 1; /*!< [6..6] Snooze Request Enable 0Enable IRQ 6 pin snooze request             */
14704             __IOM uint32_t SNZREQEN7  : 1; /*!< [7..7] Snooze Request Enable 0Enable IRQ 7 pin snooze request             */
14705             __IOM uint32_t SNZREQEN8  : 1; /*!< [8..8] Snooze Request Enable 0Enable IRQ 8 pin snooze request             */
14706             __IOM uint32_t SNZREQEN9  : 1; /*!< [9..9] Snooze Request Enable 0Enable IRQ 9 pin snooze request             */
14707             __IOM uint32_t SNZREQEN10 : 1; /*!< [10..10] Snooze Request Enable 0Enable IRQ 10 pin snooze request          */
14708             __IOM uint32_t SNZREQEN11 : 1; /*!< [11..11] Snooze Request Enable 0Enable IRQ 11 pin snooze request          */
14709             __IOM uint32_t SNZREQEN12 : 1; /*!< [12..12] Snooze Request Enable 0Enable IRQ 12 pin snooze request          */
14710             __IOM uint32_t SNZREQEN13 : 1; /*!< [13..13] Snooze Request Enable 0Enable IRQ 13 pin snooze request          */
14711             __IOM uint32_t SNZREQEN14 : 1; /*!< [14..14] Snooze Request Enable 0Enable IRQ 14 pin snooze request          */
14712             __IOM uint32_t SNZREQEN15 : 1; /*!< [15..15] Snooze Request Enable 0Enable IRQ 15 pin snooze request          */
14713             uint32_t                  : 1;
14714             __IOM uint32_t SNZREQEN17 : 1; /*!< [17..17] Snooze Request Enable 17Enable KR snooze request                 */
14715             uint32_t                  : 4;
14716             __IOM uint32_t SNZREQEN22 : 1; /*!< [22..22] Snooze Request Enable 22Enable Comparator-HS0 snooze
14717                                             *   request                                                                   */
14718             __IOM uint32_t SNZREQEN23 : 1; /*!< [23..23] Snooze Request Enable 23Enable Comparator-LP0 snooze
14719                                             *   request                                                                   */
14720             __IOM uint32_t SNZREQEN24 : 1; /*!< [24..24] Snooze Request Enable 24Enable RTC alarm snooze request          */
14721             __IOM uint32_t SNZREQEN25 : 1; /*!< [25..25] Snooze Request Enable 25Enable RTC period snooze request         */
14722             uint32_t                  : 2;
14723             __IOM uint32_t SNZREQEN28 : 1; /*!< [28..28] Snooze Request Enable 28Enable AGT1 underflow snooze
14724                                             *   request                                                                   */
14725             __IOM uint32_t SNZREQEN29 : 1; /*!< [29..29] Snooze Request Enable 29Enable AGT1 compare match A
14726                                             *   snooze request                                                            */
14727             __IOM uint32_t SNZREQEN30 : 1; /*!< [30..30] Snooze Request Enable 30Enable AGT1 compare match B
14728                                             *   snooze request                                                            */
14729             uint32_t : 1;
14730         } SNZREQCR_b;
14731     };
14732     __IM uint16_t RESERVED26;
14733 
14734     union
14735     {
14736         __IOM uint8_t FLSTOP;          /*!< (@ 0x0000009E) Flash Operation Control Register                           */
14737 
14738         struct
14739         {
14740             __IOM uint8_t FLSTOP : 1;  /*!< [0..0] Selecting ON/OFF of the Flash Memory Operation                     */
14741             uint8_t              : 3;
14742             __IOM uint8_t FLSTPF : 1;  /*!< [4..4] Flash Memory Operation Status Flag                                 */
14743             uint8_t              : 3;
14744         } FLSTOP_b;
14745     };
14746 
14747     union
14748     {
14749         __IOM uint8_t PSMCR;           /*!< (@ 0x0000009F) Power Save Memory Control Register                         */
14750 
14751         struct
14752         {
14753             __IOM uint8_t PSMC : 2;    /*!< [1..0] Power save memory control.                                         */
14754             uint8_t            : 6;
14755         } PSMCR_b;
14756     };
14757 
14758     union
14759     {
14760         __IOM uint8_t OPCCR;           /*!< (@ 0x000000A0) Operating Power Control Register                           */
14761 
14762         struct
14763         {
14764             __IOM uint8_t OPCM   : 2;  /*!< [1..0] Operating Power Control Mode Select                                */
14765             uint8_t              : 2;
14766             __IM uint8_t OPCMTSF : 1;  /*!< [4..4] Operating Power Control Mode Transition Status Flag                */
14767             uint8_t              : 3;
14768         } OPCCR_b;
14769     };
14770     __IM uint8_t RESERVED27;
14771 
14772     union
14773     {
14774         __IOM uint8_t MOSCWTCR;        /*!< (@ 0x000000A2) Main Clock Oscillator Wait Control Register                */
14775 
14776         struct
14777         {
14778             __IOM uint8_t MSTS : 4;    /*!< [3..0] Main clock oscillator wait time setting                            */
14779             uint8_t            : 4;
14780         } MOSCWTCR_b;
14781     };
14782     __IM uint8_t RESERVED28[2];
14783 
14784     union
14785     {
14786         __IOM uint8_t HOCOWTCR;        /*!< (@ 0x000000A5) High-speed on-chip oscillator wait control register        */
14787 
14788         struct
14789         {
14790             __IOM uint8_t HSTS : 3;    /*!< [2..0] HOCO wait time settingWaiting time (sec) = setting of
14791                                         *   the HSTS[2:0] bits/fLOCO(Trimmed) + 3/fLOC(Untrimmed)                     */
14792             uint8_t : 5;
14793         } HOCOWTCR_b;
14794     };
14795     __IM uint16_t RESERVED29[2];
14796 
14797     union
14798     {
14799         __IOM uint8_t SOPCCR;          /*!< (@ 0x000000AA) Sub Operating Power Control Register                       */
14800 
14801         struct
14802         {
14803             __IOM uint8_t SOPCM   : 1; /*!< [0..0] Sub Operating Power Control Mode Select                            */
14804             uint8_t               : 3;
14805             __IM uint8_t SOPCMTSF : 1; /*!< [4..4] Sub Operating Power Control Mode Transition Status Flag            */
14806             uint8_t               : 3;
14807         } SOPCCR_b;
14808     };
14809     __IM uint8_t  RESERVED30;
14810     __IM uint32_t RESERVED31[5];
14811 
14812     union
14813     {
14814         __IOM uint16_t RSTSR1;         /*!< (@ 0x000000C0) Reset Status Register 1                                    */
14815 
14816         struct
14817         {
14818             __IOM uint16_t IWDTRF : 1; /*!< [0..0] Independent Watchdog Timer Reset Detect FlagNOTE: Writable
14819                                         *   only to clear the flag. Confirm the value is 1 and then
14820                                         *   write 0.                                                                  */
14821             __IOM uint16_t WDTRF : 1;  /*!< [1..1] Watchdog Timer Reset Detect FlagNOTE: Writable only to
14822                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
14823             __IOM uint16_t SWRF : 1;   /*!< [2..2] Software Reset Detect FlagNOTE: Writable only to clear
14824                                         *   the flag. Confirm the value is 1 and then write 0.                        */
14825             uint16_t             : 5;
14826             __IOM uint16_t RPERF : 1;  /*!< [8..8] RAM Parity Error Reset Detect FlagNOTE: Writable only
14827                                         *   to clear the flag. Confirm the value is 1 and then write
14828                                         *   0.                                                                        */
14829             __IOM uint16_t REERF : 1;  /*!< [9..9] RAM ECC Error Reset Detect FlagNOTE: Writable only to
14830                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
14831             __IOM uint16_t BUSSRF : 1; /*!< [10..10] Bus Slave MPU Reset Detect FlagNOTE: Writable only
14832                                         *   to clear the flag. Confirm the value is 1 and then write
14833                                         *   0.                                                                        */
14834             __IOM uint16_t BUSMRF : 1; /*!< [11..11] Bus Master MPU Reset Detect FlagNOTE: Writable only
14835                                         *   to clear the flag. Confirm the value is 1 and then write
14836                                         *   0.                                                                        */
14837             __IOM uint16_t SPERF : 1;  /*!< [12..12] SP Error Reset Detect FlagNOTE: Writable only to clear
14838                                         *   the flag. Confirm the value is 1 and then write 0.                        */
14839             __IOM uint16_t TZERF : 1;  /*!< [13..13] Trust Zone Error Reset Detect Flag                               */
14840             uint16_t             : 1;
14841             __IOM uint16_t CPERF : 1;  /*!< [15..15] Cache Parity Error Reset Detect Flag                             */
14842         } RSTSR1_b;
14843     };
14844     __IM uint16_t RESERVED32;
14845     __IM uint32_t RESERVED33[3];
14846 
14847     union
14848     {
14849         __IOM uint8_t USBCKCR_ALT;       /*!< (@ 0x000000D0) USB Clock Control Register                                 */
14850 
14851         struct
14852         {
14853             __IOM uint8_t USBCLKSEL : 1; /*!< [0..0] The USBCLKSEL bit selects the source of the USB clock
14854                                           *   (UCLK).                                                                   */
14855             uint8_t : 7;
14856         } USBCKCR_ALT_b;
14857     };
14858 
14859     union
14860     {
14861         __IOM uint8_t SDADCCKCR;          /*!< (@ 0x000000D1) 24-bit Sigma-Delta A/D Converter Clock Control
14862                                            *                  Register                                                   */
14863 
14864         struct
14865         {
14866             __IOM uint8_t SDADCCKSEL : 1; /*!< [0..0] 24-bit Sigma-Delta A/D Converter Clock Select                      */
14867             uint8_t                  : 6;
14868             __IOM uint8_t SDADCCKEN  : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable                      */
14869         } SDADCCKCR_b;
14870     };
14871     __IM uint16_t RESERVED34;
14872     __IM uint32_t RESERVED35[3];
14873 
14874     union
14875     {
14876         __IOM uint8_t LVD1CR1;         /*!< (@ 0x000000E0) Voltage Monitor 1 Circuit Control Register 1               */
14877 
14878         struct
14879         {
14880             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
14881             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
14882             uint8_t              : 5;
14883         } LVD1CR1_b;
14884     };
14885 
14886     union
14887     {
14888         __IOM uint8_t LVD1SR;          /*!< (@ 0x000000E1) Voltage Monitor 1 Circuit Status Register                  */
14889 
14890         struct
14891         {
14892             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
14893                                         *   0 can be written to this bit. After writing 0 to this bit,
14894                                         *   it takes 2 system clock cycles for the bit to be read as
14895                                         *   0.                                                                        */
14896             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
14897             uint8_t          : 6;
14898         } LVD1SR_b;
14899     };
14900 
14901     union
14902     {
14903         __IOM uint8_t LVD2CR1;         /*!< (@ 0x000000E2) Voltage Monitor 2 Circuit Control Register 1               */
14904 
14905         struct
14906         {
14907             __IOM uint8_t IDTSEL : 2;  /*!< [1..0] Voltage Monitor Interrupt Generation Condition Select              */
14908             __IOM uint8_t IRQSEL : 1;  /*!< [2..2] Voltage Monitor Interrupt Type Select                              */
14909             uint8_t              : 5;
14910         } LVD2CR1_b;
14911     };
14912 
14913     union
14914     {
14915         __IOM uint8_t LVD2SR;          /*!< (@ 0x000000E3) Voltage Monitor 2 Circuit Status Register                  */
14916 
14917         struct
14918         {
14919             __IOM uint8_t DET : 1;     /*!< [0..0] Voltage Monitor Voltage Change Detection Flag NOTE: Only
14920                                         *   0 can be written to this bit. After writing 0 to this bit,
14921                                         *   it takes 2 system clock cycles for the bit to be read as
14922                                         *   0.                                                                        */
14923             __IM uint8_t MON : 1;      /*!< [1..1] Voltage Monitor 1 Signal Monitor Flag                              */
14924             uint8_t          : 6;
14925         } LVD2SR_b;
14926     };
14927     __IM uint32_t RESERVED36[183];
14928 
14929     union
14930     {
14931         __IOM uint32_t CGFSAR;           /*!< (@ 0x000003C0) Clock Generation Function Security Attribute
14932                                           *                  Register                                                   */
14933 
14934         struct
14935         {
14936             __IOM uint32_t NONSEC00 : 1; /*!< [0..0] Non Secure Attribute bit 00                                        */
14937             uint32_t                : 1;
14938             __IOM uint32_t NONSEC02 : 1; /*!< [2..2] Non Secure Attribute bit 02                                        */
14939             __IOM uint32_t NONSEC03 : 1; /*!< [3..3] Non Secure Attribute bit 03                                        */
14940             __IOM uint32_t NONSEC04 : 1; /*!< [4..4] Non Secure Attribute bit 04                                        */
14941             __IOM uint32_t NONSEC05 : 1; /*!< [5..5] Non Secure Attribute bit 05                                        */
14942             __IOM uint32_t NONSEC06 : 1; /*!< [6..6] Non Secure Attribute bit 06                                        */
14943             __IOM uint32_t NONSEC07 : 1; /*!< [7..7] Non Secure Attribute bit 07                                        */
14944             __IOM uint32_t NONSEC08 : 1; /*!< [8..8] Non Secure Attribute bit 08                                        */
14945             __IOM uint32_t NONSEC09 : 1; /*!< [9..9] Non Secure Attribute bit 09                                        */
14946             uint32_t                : 1;
14947             __IOM uint32_t NONSEC11 : 1; /*!< [11..11] Non Secure Attribute bit 11                                      */
14948             __IOM uint32_t NONSEC12 : 1; /*!< [12..12] Non Secure Attribute bit 12                                      */
14949             uint32_t                : 3;
14950             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
14951             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
14952             uint32_t                : 14;
14953         } CGFSAR_b;
14954     };
14955     __IM uint32_t RESERVED37;
14956 
14957     union
14958     {
14959         __IOM uint32_t LPMSAR;          /*!< (@ 0x000003C8) Low Power Mode Security Attribution Register               */
14960 
14961         struct
14962         {
14963             __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
14964             uint32_t               : 1;
14965             __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
14966             uint32_t               : 1;
14967             __IOM uint32_t NONSEC4 : 1; /*!< [4..4] Non Secure Attribute bit 4                                         */
14968             uint32_t               : 3;
14969             __IOM uint32_t NONSEC8 : 1; /*!< [8..8] Non Secure Attribute bit 8                                         */
14970             __IOM uint32_t NONSEC9 : 1; /*!< [9..9] Non Secure Attribute bit 9                                         */
14971             uint32_t               : 22;
14972         } LPMSAR_b;
14973     };
14974 
14975     union
14976     {
14977         union
14978         {
14979             __IOM uint32_t LVDSAR;          /*!< (@ 0x000003CC) Low Voltage Detection Security Attribution Register        */
14980 
14981             struct
14982             {
14983                 __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
14984                 __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
14985                 uint32_t               : 30;
14986             } LVDSAR_b;
14987         };
14988 
14989         union
14990         {
14991             __IOM uint32_t RSTSAR;          /*!< (@ 0x000003CC) Reset Security Attribution Register                        */
14992 
14993             struct
14994             {
14995                 __IOM uint32_t NONSEC0 : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
14996                 __IOM uint32_t NONSEC1 : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
14997                 __IOM uint32_t NONSEC2 : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
14998                 uint32_t               : 29;
14999             } RSTSAR_b;
15000         };
15001     };
15002 
15003     union
15004     {
15005         __IOM uint32_t BBFSAR;           /*!< (@ 0x000003D0) Battery Backup Function Security Attribute Register        */
15006 
15007         struct
15008         {
15009             __IOM uint32_t NONSEC0  : 1; /*!< [0..0] Non Secure Attribute bit 0                                         */
15010             __IOM uint32_t NONSEC1  : 1; /*!< [1..1] Non Secure Attribute bit 1                                         */
15011             __IOM uint32_t NONSEC2  : 1; /*!< [2..2] Non Secure Attribute bit 2                                         */
15012             uint32_t                : 13;
15013             __IOM uint32_t NONSEC16 : 1; /*!< [16..16] Non Secure Attribute bit 16                                      */
15014             __IOM uint32_t NONSEC17 : 1; /*!< [17..17] Non Secure Attribute bit 17                                      */
15015             __IOM uint32_t NONSEC18 : 1; /*!< [18..18] Non Secure Attribute bit 18                                      */
15016             __IOM uint32_t NONSEC19 : 1; /*!< [19..19] Non Secure Attribute bit 19                                      */
15017             __IOM uint32_t NONSEC20 : 1; /*!< [20..20] Non Secure Attribute bit 20                                      */
15018             __IOM uint32_t NONSEC21 : 1; /*!< [21..21] Non Secure Attribute bit 21                                      */
15019             __IOM uint32_t NONSEC22 : 1; /*!< [22..22] Non Secure Attribute bit 22                                      */
15020             __IOM uint32_t NONSEC23 : 1; /*!< [23..23] Non Secure Attribute bit 23                                      */
15021             uint32_t                : 8;
15022         } BBFSAR_b;
15023     };
15024     __IM uint32_t RESERVED38[3];
15025 
15026     union
15027     {
15028         __IOM uint32_t DPFSAR;          /*!< (@ 0x000003E0) Deep Standby Interrupt Factor Security Attribution
15029                                          *                  Register                                                   */
15030 
15031         struct
15032         {
15033             __IOM uint32_t DPFSA0 : 1;  /*!< [0..0] Deep Standby Interrupt Factor Security Attribute bit
15034                                          *   0                                                                         */
15035             __IOM uint32_t DPFSA1 : 1;  /*!< [1..1] Deep Standby Interrupt Factor Security Attribute bit
15036                                          *   1                                                                         */
15037             __IOM uint32_t DPFSA2 : 1;  /*!< [2..2] Deep Standby Interrupt Factor Security Attribute bit
15038                                          *   2                                                                         */
15039             __IOM uint32_t DPFSA3 : 1;  /*!< [3..3] Deep Standby Interrupt Factor Security Attribute bit
15040                                          *   3                                                                         */
15041             __IOM uint32_t DPFSA4 : 1;  /*!< [4..4] Deep Standby Interrupt Factor Security Attribute bit
15042                                          *   4                                                                         */
15043             __IOM uint32_t DPFSA5 : 1;  /*!< [5..5] Deep Standby Interrupt Factor Security Attribute bit
15044                                          *   5                                                                         */
15045             __IOM uint32_t DPFSA6 : 1;  /*!< [6..6] Deep Standby Interrupt Factor Security Attribute bit
15046                                          *   6                                                                         */
15047             __IOM uint32_t DPFSA7 : 1;  /*!< [7..7] Deep Standby Interrupt Factor Security Attribute bit
15048                                          *   7                                                                         */
15049             __IOM uint32_t DPFSA8 : 1;  /*!< [8..8] Deep Standby Interrupt Factor Security Attribute bit
15050                                          *   8                                                                         */
15051             __IOM uint32_t DPFSA9 : 1;  /*!< [9..9] Deep Standby Interrupt Factor Security Attribute bit
15052                                          *   9                                                                         */
15053             __IOM uint32_t DPFSA10 : 1; /*!< [10..10] Deep Standby Interrupt Factor Security Attribute bit
15054                                          *   10                                                                        */
15055             __IOM uint32_t DPFSA11 : 1; /*!< [11..11] Deep Standby Interrupt Factor Security Attribute bit
15056                                          *   11                                                                        */
15057             __IOM uint32_t DPFSA12 : 1; /*!< [12..12] Deep Standby Interrupt Factor Security Attribute bit
15058                                          *   12                                                                        */
15059             __IOM uint32_t DPFSA13 : 1; /*!< [13..13] Deep Standby Interrupt Factor Security Attribute bit
15060                                          *   13                                                                        */
15061             __IOM uint32_t DPFSA14 : 1; /*!< [14..14] Deep Standby Interrupt Factor Security Attribute bit
15062                                          *   14                                                                        */
15063             __IOM uint32_t DPFSA15 : 1; /*!< [15..15] Deep Standby Interrupt Factor Security Attribute bit
15064                                          *   15                                                                        */
15065             __IOM uint32_t DPFSA16 : 1; /*!< [16..16] Deep Standby Interrupt Factor Security Attribute bit
15066                                          *   16                                                                        */
15067             __IOM uint32_t DPFSA17 : 1; /*!< [17..17] Deep Standby Interrupt Factor Security Attribute bit
15068                                          *   17                                                                        */
15069             __IOM uint32_t DPFSA18 : 1; /*!< [18..18] Deep Standby Interrupt Factor Security Attribute bit
15070                                          *   18                                                                        */
15071             __IOM uint32_t DPFSA19 : 1; /*!< [19..19] Deep Standby Interrupt Factor Security Attribute bit
15072                                          *   19                                                                        */
15073             __IOM uint32_t DPFSA20 : 1; /*!< [20..20] Deep Standby Interrupt Factor Security Attribute bit
15074                                          *   20                                                                        */
15075             uint32_t               : 3;
15076             __IOM uint32_t DPFSA24 : 1; /*!< [24..24] Deep Standby Interrupt Factor Security Attribute bit
15077                                          *   24                                                                        */
15078             uint32_t               : 1;
15079             __IOM uint32_t DPFSA26 : 1; /*!< [26..26] Deep Standby Interrupt Factor Security Attribute bit
15080                                          *   26                                                                        */
15081             __IOM uint32_t DPFSA27 : 1; /*!< [27..27] Deep Standby Interrupt Factor Security Attribute bit
15082                                          *   27                                                                        */
15083             uint32_t : 4;
15084         } DPFSAR_b;
15085     };
15086     __IM uint32_t RESERVED39[6];
15087     __IM uint16_t RESERVED40;
15088 
15089     union
15090     {
15091         __IOM uint16_t PRCR;           /*!< (@ 0x000003FE) Protect Register                                           */
15092 
15093         struct
15094         {
15095             __IOM uint16_t PRC0 : 1;   /*!< [0..0] Enables writing to the registers related to the clock
15096                                         *   generation circuit.                                                       */
15097             __IOM uint16_t PRC1 : 1;   /*!< [1..1] Enables writing to the registers related to the operating
15098                                         *   modes, the low power consumption modes and the battery
15099                                         *   backup function.                                                          */
15100             uint16_t            : 1;
15101             __IOM uint16_t PRC3 : 1;   /*!< [3..3] Enables writing to the registers related to the LVD.               */
15102             __IOM uint16_t PRC4 : 1;   /*!< [4..4] PRC4                                                               */
15103             uint16_t            : 3;
15104             __OM uint16_t PRKEY : 8;   /*!< [15..8] PRKEY Key Code                                                    */
15105         } PRCR_b;
15106     };
15107 
15108     union
15109     {
15110         __IOM uint8_t DPSBYCR;         /*!< (@ 0x00000400) Deep Standby Control Register                              */
15111 
15112         struct
15113         {
15114             __IOM uint8_t DEEPCUT : 2; /*!< [1..0] Power-Supply Control                                               */
15115             uint8_t               : 4;
15116             __IOM uint8_t IOKEEP  : 1; /*!< [6..6] I/O Port Retention                                                 */
15117             __IOM uint8_t DPSBY   : 1; /*!< [7..7] Deep Software Standby                                              */
15118         } DPSBYCR_b;
15119     };
15120 
15121     union
15122     {
15123         __IOM uint8_t DPSWCR;          /*!< (@ 0x00000401) Deep Standby Wait Control Register                         */
15124 
15125         struct
15126         {
15127             __IOM uint8_t WTSTS : 6;   /*!< [5..0] Deep Software Wait Standby Time Setting Bit                        */
15128             uint8_t             : 2;
15129         } DPSWCR_b;
15130     };
15131 
15132     union
15133     {
15134         __IOM uint8_t DPSIER0;         /*!< (@ 0x00000402) Deep Standby Interrupt Enable Register 0                   */
15135 
15136         struct
15137         {
15138             __IOM uint8_t DIRQ0E : 1;  /*!< [0..0] IRQ-DS Pin Enable                                                  */
15139             __IOM uint8_t DIRQ1E : 1;  /*!< [1..1] IRQ-DS Pin Enable                                                  */
15140             __IOM uint8_t DIRQ2E : 1;  /*!< [2..2] IRQ-DS Pin Enable                                                  */
15141             __IOM uint8_t DIRQ3E : 1;  /*!< [3..3] IRQ-DS Pin Enable                                                  */
15142             __IOM uint8_t DIRQ4E : 1;  /*!< [4..4] IRQ-DS Pin Enable                                                  */
15143             __IOM uint8_t DIRQ5E : 1;  /*!< [5..5] IRQ-DS Pin Enable                                                  */
15144             __IOM uint8_t DIRQ6E : 1;  /*!< [6..6] IRQ-DS Pin Enable                                                  */
15145             __IOM uint8_t DIRQ7E : 1;  /*!< [7..7] IRQ-DS Pin Enable                                                  */
15146         } DPSIER0_b;
15147     };
15148 
15149     union
15150     {
15151         __IOM uint8_t DPSIER1;         /*!< (@ 0x00000403) Deep Standby Interrupt Enable Register 1                   */
15152 
15153         struct
15154         {
15155             __IOM uint8_t DIRQ8E  : 1; /*!< [0..0] IRQ-DS Pin Enable                                                  */
15156             __IOM uint8_t DIRQ9E  : 1; /*!< [1..1] IRQ-DS Pin Enable                                                  */
15157             __IOM uint8_t DIRQ10E : 1; /*!< [2..2] IRQ-DS Pin Enable                                                  */
15158             __IOM uint8_t DIRQ11E : 1; /*!< [3..3] IRQ-DS Pin Enable                                                  */
15159             __IOM uint8_t DIRQ12E : 1; /*!< [4..4] IRQ-DS Pin Enable                                                  */
15160             __IOM uint8_t DIRQ13E : 1; /*!< [5..5] IRQ-DS Pin Enable                                                  */
15161             __IOM uint8_t DIRQ14E : 1; /*!< [6..6] IRQ-DS Pin Enable                                                  */
15162             __IOM uint8_t DIRQ15E : 1; /*!< [7..7] IRQ-DS Pin Enable                                                  */
15163         } DPSIER1_b;
15164     };
15165 
15166     union
15167     {
15168         __IOM uint8_t DPSIER2;          /*!< (@ 0x00000404) Deep Standby Interrupt Enable Register 2                   */
15169 
15170         struct
15171         {
15172             __IOM uint8_t DLVD1IE  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Signal Enable                             */
15173             __IOM uint8_t DLVD2IE  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Signal Enable                             */
15174             __IOM uint8_t DTRTCIIE : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Signal Enable           */
15175             __IOM uint8_t DRTCAIE  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Signal Enable              */
15176             __IOM uint8_t DNMIE    : 1; /*!< [4..4] NMI Pin Enable                                                     */
15177             uint8_t                : 3;
15178         } DPSIER2_b;
15179     };
15180 
15181     union
15182     {
15183         __IOM uint8_t DPSIER3;          /*!< (@ 0x00000405) Deep Standby Interrupt Enable Register 3                   */
15184 
15185         struct
15186         {
15187             __IOM uint8_t DUSBFSIE : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Signal Enable             */
15188             __IOM uint8_t DUSBHSIE : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Signal Enable             */
15189             __IOM uint8_t DAGT1IE  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Signal Enable                   */
15190             __IOM uint8_t DAGT3IE  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Signal Enable                   */
15191             uint8_t                : 4;
15192         } DPSIER3_b;
15193     };
15194 
15195     union
15196     {
15197         __IOM uint8_t DPSIFR0;         /*!< (@ 0x00000406) Deep Standby Interrupt Flag Register 0                     */
15198 
15199         struct
15200         {
15201             __IOM uint8_t DIRQ0F : 1;  /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
15202             __IOM uint8_t DIRQ1F : 1;  /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
15203             __IOM uint8_t DIRQ2F : 1;  /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
15204             __IOM uint8_t DIRQ3F : 1;  /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
15205             __IOM uint8_t DIRQ4F : 1;  /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
15206             __IOM uint8_t DIRQ5F : 1;  /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
15207             __IOM uint8_t DIRQ6F : 1;  /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
15208             __IOM uint8_t DIRQ7F : 1;  /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
15209         } DPSIFR0_b;
15210     };
15211 
15212     union
15213     {
15214         __IOM uint8_t DPSIFR1;         /*!< (@ 0x00000407) Deep Standby Interrupt Flag Register 1                     */
15215 
15216         struct
15217         {
15218             __IOM uint8_t DIRQ8F  : 1; /*!< [0..0] IRQ-DS Pin Deep Standby Cancel Flag                                */
15219             __IOM uint8_t DIRQ9F  : 1; /*!< [1..1] IRQ-DS Pin Deep Standby Cancel Flag                                */
15220             __IOM uint8_t DIRQ10F : 1; /*!< [2..2] IRQ-DS Pin Deep Standby Cancel Flag                                */
15221             __IOM uint8_t DIRQ11F : 1; /*!< [3..3] IRQ-DS Pin Deep Standby Cancel Flag                                */
15222             __IOM uint8_t DIRQ12F : 1; /*!< [4..4] IRQ-DS Pin Deep Standby Cancel Flag                                */
15223             __IOM uint8_t DIRQ13F : 1; /*!< [5..5] IRQ-DS Pin Deep Standby Cancel Flag                                */
15224             __IOM uint8_t DIRQ14F : 1; /*!< [6..6] IRQ-DS Pin Deep Standby Cancel Flag                                */
15225             __IOM uint8_t DIRQ15F : 1; /*!< [7..7] IRQ-DS Pin Deep Standby Cancel Flag                                */
15226         } DPSIFR1_b;
15227     };
15228 
15229     union
15230     {
15231         __IOM uint8_t DPSIFR2;          /*!< (@ 0x00000408) Deep Standby Interrupt Flag Register 2                     */
15232 
15233         struct
15234         {
15235             __IOM uint8_t DLVD1IF  : 1; /*!< [0..0] LVD1 Deep Standby Cancel Flag                                      */
15236             __IOM uint8_t DLVD2IF  : 1; /*!< [1..1] LVD2 Deep Standby Cancel Flag                                      */
15237             __IOM uint8_t DTRTCIIF : 1; /*!< [2..2] RTC Interval interrupt Deep Standby Cancel Flag                    */
15238             __IOM uint8_t DRTCAIF  : 1; /*!< [3..3] RTC Alarm interrupt Deep Standby Cancel Flag                       */
15239             __IOM uint8_t DNMIF    : 1; /*!< [4..4] NMI Pin Deep Standby Cancel Flag                                   */
15240             uint8_t                : 3;
15241         } DPSIFR2_b;
15242     };
15243 
15244     union
15245     {
15246         __IOM uint8_t DPSIFR3;          /*!< (@ 0x00000409) Deep Standby Interrupt Flag Register 3                     */
15247 
15248         struct
15249         {
15250             __IOM uint8_t DUSBFSIF : 1; /*!< [0..0] USBFS Suspend/Resume Deep Standby Cancel Flag                      */
15251             __IOM uint8_t DUSBHSIF : 1; /*!< [1..1] USBHS Suspend/Resume Deep Standby Cancel Flag                      */
15252             __IOM uint8_t DAGT1IF  : 1; /*!< [2..2] AGT1 Underflow Deep Standby Cancel Flag                            */
15253             __IOM uint8_t DAGT3IF  : 1; /*!< [3..3] AGT3 Underflow Deep Standby Cancel Flag                            */
15254             uint8_t                : 4;
15255         } DPSIFR3_b;
15256     };
15257 
15258     union
15259     {
15260         __IOM uint8_t DPSIEGR0;        /*!< (@ 0x0000040A) Deep Standby Interrupt Edge Register 0                     */
15261 
15262         struct
15263         {
15264             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
15265             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
15266             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
15267             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
15268             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
15269             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
15270             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
15271             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
15272         } DPSIEGR0_b;
15273     };
15274 
15275     union
15276     {
15277         __IOM uint8_t DPSIEGR1;        /*!< (@ 0x0000040B) Deep Standby Interrupt Edge Register 1                     */
15278 
15279         struct
15280         {
15281             __IOM uint8_t DIRQ0EG : 1; /*!< [0..0] IRQ-DS Pin Edge Select                                             */
15282             __IOM uint8_t DIRQ1EG : 1; /*!< [1..1] IRQ-DS Pin Edge Select                                             */
15283             __IOM uint8_t DIRQ2EG : 1; /*!< [2..2] IRQ-DS Pin Edge Select                                             */
15284             __IOM uint8_t DIRQ3EG : 1; /*!< [3..3] IRQ-DS Pin Edge Select                                             */
15285             __IOM uint8_t DIRQ4EG : 1; /*!< [4..4] IRQ-DS Pin Edge Select                                             */
15286             __IOM uint8_t DIRQ5EG : 1; /*!< [5..5] IRQ-DS Pin Edge Select                                             */
15287             __IOM uint8_t DIRQ6EG : 1; /*!< [6..6] IRQ-DS Pin Edge Select                                             */
15288             __IOM uint8_t DIRQ7EG : 1; /*!< [7..7] IRQ-DS Pin Edge Select                                             */
15289         } DPSIEGR1_b;
15290     };
15291 
15292     union
15293     {
15294         __IOM uint8_t DPSIEGR2;         /*!< (@ 0x0000040C) Deep Standby Interrupt Edge Register 2                     */
15295 
15296         struct
15297         {
15298             __IOM uint8_t DLVD1IEG : 1; /*!< [0..0] LVD1 Edge Select                                                   */
15299             __IOM uint8_t DLVD2IEG : 1; /*!< [1..1] LVD2 Edge Select                                                   */
15300             uint8_t                : 2;
15301             __IOM uint8_t DNMIEG   : 1; /*!< [4..4] NMI Pin Edge Select                                                */
15302             uint8_t                : 3;
15303         } DPSIEGR2_b;
15304     };
15305     __IM uint8_t RESERVED41;
15306 
15307     union
15308     {
15309         __IOM uint8_t SYOCDCR;         /*!< (@ 0x0000040E) System Control OCD Control Register                        */
15310 
15311         struct
15312         {
15313             __IOM uint8_t DOCDF : 1;   /*!< [0..0] Deep Standby OCD flag                                              */
15314             uint8_t             : 6;
15315             __IOM uint8_t DBGEN : 1;   /*!< [7..7] Debugger Enable bit                                                */
15316         } SYOCDCR_b;
15317     };
15318 
15319     union
15320     {
15321         __IOM uint8_t STCONR;          /*!< (@ 0x0000040F) Standby Condition Register                                 */
15322 
15323         struct
15324         {
15325             __IOM uint8_t STCON : 2;   /*!< [1..0] SSTBY condition bit                                                */
15326             uint8_t             : 6;
15327         } STCONR_b;
15328     };
15329 
15330     union
15331     {
15332         __IOM uint8_t RSTSR0;          /*!< (@ 0x00000410) Reset Status Register 0                                    */
15333 
15334         struct
15335         {
15336             __IOM uint8_t PORF : 1;    /*!< [0..0] Power-On Reset Detect FlagNOTE: Writable only to clear
15337                                         *   the flag. Confirm the value is 1 and then write 0.                        */
15338             __IOM uint8_t LVD0RF : 1;  /*!< [1..1] Voltage Monitor 0 Reset Detect FlagNOTE: Writable only
15339                                         *   to clear the flag. Confirm the value is 1 and then write
15340                                         *   0.                                                                        */
15341             __IOM uint8_t LVD1RF : 1;  /*!< [2..2] Voltage Monitor 1 Reset Detect FlagNOTE: Writable only
15342                                         *   to clear the flag. Confirm the value is 1 and then write
15343                                         *   0.                                                                        */
15344             __IOM uint8_t LVD2RF : 1;  /*!< [3..3] Voltage Monitor 2 Reset Detect FlagNOTE: Writable only
15345                                         *   to clear the flag. Confirm the value is 1 and then write
15346                                         *   0.                                                                        */
15347             uint8_t               : 3;
15348             __IOM uint8_t DPSRSTF : 1; /*!< [7..7] Deep Software Standby Reset FlagNOTE: Writable only to
15349                                         *   clear the flag. Confirm the value is 1 and then write 0.                  */
15350         } RSTSR0_b;
15351     };
15352 
15353     union
15354     {
15355         __IOM uint8_t RSTSR2;          /*!< (@ 0x00000411) Reset Status Register 2                                    */
15356 
15357         struct
15358         {
15359             __IOM uint8_t CWSF : 1;    /*!< [0..0] Cold/Warm Start Determination Flag                                 */
15360             uint8_t            : 7;
15361         } RSTSR2_b;
15362     };
15363     __IM uint8_t RESERVED42;
15364 
15365     union
15366     {
15367         __IOM uint8_t MOMCR;           /*!< (@ 0x00000413) Main Clock Oscillator Mode Oscillation Control
15368                                         *                  Register                                                   */
15369 
15370         struct
15371         {
15372             uint8_t                 : 3;
15373             __IOM uint8_t MODRV1    : 1; /*!< [3..3] Main Clock Oscillator Drive Capability 1 Switching                 */
15374             __IOM uint8_t MODRV0    : 2; /*!< [5..4] Main Clock Oscillator Drive Capability 0 Switching                 */
15375             __IOM uint8_t MOSEL     : 1; /*!< [6..6] Main Clock Oscillator Switching                                    */
15376             __IOM uint8_t AUTODRVEN : 1; /*!< [7..7] Main Clock Oscillator Drive Capability Auto Switching
15377                                           *   Enable                                                                    */
15378         } MOMCR_b;
15379     };
15380     __IM uint16_t RESERVED43;
15381 
15382     union
15383     {
15384         __IOM uint8_t FWEPROR;         /*!< (@ 0x00000416) Flash P/E Protect Register                                 */
15385 
15386         struct
15387         {
15388             __IOM uint8_t FLWE : 2;    /*!< [1..0] Flash Programming and Erasure                                      */
15389             uint8_t            : 6;
15390         } FWEPROR_b;
15391     };
15392 
15393     union
15394     {
15395         union
15396         {
15397             __IOM uint8_t LVCMPCR;     /*!< (@ 0x00000417) Voltage Monitor Circuit Control Register                   */
15398 
15399             struct
15400             {
15401                 uint8_t             : 5;
15402                 __IOM uint8_t LVD1E : 1; /*!< [5..5] Voltage Detection 1 Enable                                         */
15403                 __IOM uint8_t LVD2E : 1; /*!< [6..6] Voltage Detection 2 Enable                                         */
15404                 uint8_t             : 1;
15405             } LVCMPCR_b;
15406         };
15407 
15408         union
15409         {
15410             __IOM uint8_t LVD1CMPCR;       /*!< (@ 0x00000417) Voltage Monitoring 1 Comparator Control Register           */
15411 
15412             struct
15413             {
15414                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
15415                                             *   drop in voltage)                                                          */
15416                 uint8_t             : 2;
15417                 __IOM uint8_t LVD1E : 1;   /*!< [7..7] Voltage Detection 1 Enable                                         */
15418             } LVD1CMPCR_b;
15419         };
15420     };
15421 
15422     union
15423     {
15424         union
15425         {
15426             __IOM uint8_t LVDLVLR;         /*!< (@ 0x00000418) Voltage Detection Level Select Register                    */
15427 
15428             struct
15429             {
15430                 __IOM uint8_t LVD1LVL : 5; /*!< [4..0] Voltage Detection 1 Level Select (Standard voltage during
15431                                             *   fall in voltage)                                                          */
15432                 __IOM uint8_t LVD2LVL : 3; /*!< [7..5] Voltage Detection 2 Level Select (Standard voltage during
15433                                             *   fall in voltage)                                                          */
15434             } LVDLVLR_b;
15435         };
15436 
15437         union
15438         {
15439             __IOM uint8_t LVD2CMPCR;       /*!< (@ 0x00000418) Voltage Monitoring 2 Comparator Control Register           */
15440 
15441             struct
15442             {
15443                 __IOM uint8_t LVD2LVL : 3; /*!< [2..0] Voltage Detection 2 Level Select (Standard voltage during
15444                                             *   drop in voltage)                                                          */
15445                 uint8_t             : 4;
15446                 __IOM uint8_t LVD2E : 1;   /*!< [7..7] Voltage Detection 2 Enable                                         */
15447             } LVD2CMPCR_b;
15448         };
15449     };
15450     __IM uint8_t RESERVED44;
15451 
15452     union
15453     {
15454         __IOM uint8_t LVD1CR0;         /*!< (@ 0x0000041A) Voltage Monitor 1 Circuit Control Register 0               */
15455 
15456         struct
15457         {
15458             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
15459             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
15460             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
15461             uint8_t             : 1;
15462             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
15463             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
15464             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
15465         } LVD1CR0_b;
15466     };
15467 
15468     union
15469     {
15470         __IOM uint8_t LVD2CR0;         /*!< (@ 0x0000041B) Voltage Monitor 2 Circuit Control Register 0               */
15471 
15472         struct
15473         {
15474             __IOM uint8_t RIE   : 1;   /*!< [0..0] Voltage Monitor Interrupt/Reset Enable                             */
15475             __IOM uint8_t DFDIS : 1;   /*!< [1..1] Voltage Monitor Digital Filter Disable Mode Select                 */
15476             __IOM uint8_t CMPE  : 1;   /*!< [2..2] Voltage Monitor Circuit Comparison Result Output Enable            */
15477             uint8_t             : 1;
15478             __IOM uint8_t FSAMP : 2;   /*!< [5..4] Sampling Clock Select                                              */
15479             __IOM uint8_t RI    : 1;   /*!< [6..6] Voltage Monitor Circuit Mode Select                                */
15480             __IOM uint8_t RN    : 1;   /*!< [7..7] Voltage Monitor Reset Negate Select                                */
15481         } LVD2CR0_b;
15482     };
15483     __IM uint8_t RESERVED45;
15484 
15485     union
15486     {
15487         __IOM uint8_t VBATTMNSELR;        /*!< (@ 0x0000041D) Battery Backup Voltage Monitor Function Select
15488                                            *                  Register                                                   */
15489 
15490         struct
15491         {
15492             __IOM uint8_t VBATTMNSEL : 1; /*!< [0..0] VBATT Low Voltage Detect Function Select Bit                       */
15493             uint8_t                  : 7;
15494         } VBATTMNSELR_b;
15495     };
15496 
15497     union
15498     {
15499         __IM uint8_t VBATTMONR;        /*!< (@ 0x0000041E) Battery Backup Voltage Monitor Register                    */
15500 
15501         struct
15502         {
15503             __IM uint8_t VBATTMON : 1; /*!< [0..0] VBATT Voltage Monitor Bit                                          */
15504             uint8_t               : 7;
15505         } VBATTMONR_b;
15506     };
15507 
15508     union
15509     {
15510         __IOM uint8_t VBTCR1;           /*!< (@ 0x0000041F) VBATT Control Register1                                    */
15511 
15512         struct
15513         {
15514             __IOM uint8_t BPWSWSTP : 1; /*!< [0..0] Battery Power supply Switch Stop                                   */
15515             uint8_t                : 7;
15516         } VBTCR1_b;
15517     };
15518     __IM uint32_t RESERVED46[8];
15519 
15520     union
15521     {
15522         union
15523         {
15524             __IOM uint8_t DCDCCTL;         /*!< (@ 0x00000440) DCDC/LDO Control Register                                  */
15525 
15526             struct
15527             {
15528                 __IOM uint8_t DCDCON  : 1; /*!< [0..0] LDO/DCDC on/off Control bit                                        */
15529                 __IOM uint8_t OCPEN   : 1; /*!< [1..1] DCDC OCP Function Enable bit                                       */
15530                 uint8_t               : 2;
15531                 __IOM uint8_t STOPZA  : 1; /*!< [4..4] DCDC IO Buffer Power Control bit                                   */
15532                 __IOM uint8_t LCBOOST : 1; /*!< [5..5] LDO LCBOOST Mode Control bit                                       */
15533                 __IOM uint8_t FST     : 1; /*!< [6..6] DCDC Fast Startup                                                  */
15534                 __IOM uint8_t PD      : 1; /*!< [7..7] DCDC VREF Generate Disable bit                                     */
15535             } DCDCCTL_b;
15536         };
15537 
15538         union
15539         {
15540             __IOM uint8_t LDOSCR;          /*!< (@ 0x00000440) LDO Stop Control Register                                  */
15541 
15542             struct
15543             {
15544                 __IOM uint8_t LDOSTP0 : 1; /*!< [0..0] LDO0 Stop                                                          */
15545                 __IOM uint8_t LDOSTP1 : 1; /*!< [1..1] LDO1 Stop                                                          */
15546                 uint8_t               : 6;
15547             } LDOSCR_b;
15548         };
15549     };
15550 
15551     union
15552     {
15553         __IOM uint8_t VCCSEL;          /*!< (@ 0x00000441) Voltage Level Selection Control Register                   */
15554 
15555         struct
15556         {
15557             __IOM uint8_t VCCSEL : 2;  /*!< [1..0] DCDC Working Voltage Level Selection                               */
15558             uint8_t              : 6;
15559         } VCCSEL_b;
15560     };
15561     __IM uint16_t RESERVED47;
15562 
15563     union
15564     {
15565         __IOM uint8_t PL2LDOSCR;         /*!< (@ 0x00000444) PLL2-LDO Stop Control Register                             */
15566 
15567         struct
15568         {
15569             __IOM uint8_t PL2LDOSTP : 1; /*!< [0..0] LDO0 Stop                                                          */
15570             uint8_t                 : 7;
15571         } PL2LDOSCR_b;
15572     };
15573     __IM uint8_t  RESERVED48;
15574     __IM uint16_t RESERVED49;
15575     __IM uint32_t RESERVED50[14];
15576 
15577     union
15578     {
15579         __IOM uint8_t SOSCCR;          /*!< (@ 0x00000480) Sub-Clock Oscillator Control Register                      */
15580 
15581         struct
15582         {
15583             __IOM uint8_t SOSTP : 1;   /*!< [0..0] Sub-Clock Oscillator Stop                                          */
15584             uint8_t             : 7;
15585         } SOSCCR_b;
15586     };
15587 
15588     union
15589     {
15590         __IOM uint8_t SOMCR;           /*!< (@ 0x00000481) Sub Clock Oscillator Mode Control Register                 */
15591 
15592         struct
15593         {
15594             __IOM uint8_t SODRV : 2;   /*!< [1..0] Sub-Clock Oscillator Drive Capability Switching                    */
15595             uint8_t             : 6;
15596         } SOMCR_b;
15597     };
15598 
15599     union
15600     {
15601         __IOM uint8_t SOMRG;           /*!< (@ 0x00000482) Sub Clock Oscillator Margin Check Register                 */
15602 
15603         struct
15604         {
15605             __IOM uint8_t SOSCMRG : 2; /*!< [1..0] Sub Clock Oscillator Margin check Switching                        */
15606             uint8_t               : 6;
15607         } SOMRG_b;
15608     };
15609     __IM uint8_t  RESERVED51;
15610     __IM uint32_t RESERVED52[3];
15611 
15612     union
15613     {
15614         __IOM uint8_t LOCOCR;          /*!< (@ 0x00000490) Low-Speed On-Chip Oscillator Control Register              */
15615 
15616         struct
15617         {
15618             __IOM uint8_t LCSTP : 1;   /*!< [0..0] LOCO Stop                                                          */
15619             uint8_t             : 7;
15620         } LOCOCR_b;
15621     };
15622     __IM uint8_t RESERVED53;
15623 
15624     union
15625     {
15626         __IOM uint8_t LOCOUTCR;         /*!< (@ 0x00000492) LOCO User Trimming Control Register                        */
15627 
15628         struct
15629         {
15630             __IOM uint8_t LOCOUTRM : 8; /*!< [7..0] LOCO User Trimming 1000_0000 : -128 1000_0001 : -127
15631                                          *   1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center
15632                                          *   Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 :
15633                                          +126 0111_1111 : +127These bits are added to original LOCO
15634                                          *   trimming bits                                                             */
15635         } LOCOUTCR_b;
15636     };
15637     __IM uint8_t  RESERVED54;
15638     __IM uint32_t RESERVED55[7];
15639 
15640     union
15641     {
15642         __IOM uint8_t VBTCR2;          /*!< (@ 0x000004B0) VBATT Control Register2                                    */
15643 
15644         struct
15645         {
15646             uint8_t                 : 4;
15647             __IOM uint8_t VBTLVDEN  : 1; /*!< [4..4] VBATT Pin Low Voltage Detect Enable Bit                            */
15648             uint8_t                 : 1;
15649             __IOM uint8_t VBTLVDLVL : 2; /*!< [7..6] VBATT Pin Voltage Low Voltage Detect Level Select Bit              */
15650         } VBTCR2_b;
15651     };
15652 
15653     union
15654     {
15655         __IOM uint8_t VBTSR;           /*!< (@ 0x000004B1) VBATT Status Register                                      */
15656 
15657         struct
15658         {
15659             __IOM uint8_t VBTRDF  : 1; /*!< [0..0] VBAT_R Reset Detect Flag                                           */
15660             __IOM uint8_t VBTBLDF : 1; /*!< [1..1] VBATT Battery Low voltage Detect Flag                              */
15661             uint8_t               : 2;
15662             __IM uint8_t VBTRVLD  : 1; /*!< [4..4] VBATT_R Valid                                                      */
15663             uint8_t               : 3;
15664         } VBTSR_b;
15665     };
15666 
15667     union
15668     {
15669         __IOM uint8_t VBTCMPCR;        /*!< (@ 0x000004B2) VBATT Comparator Control Register                          */
15670 
15671         struct
15672         {
15673             __IOM uint8_t VBTCMPE : 1; /*!< [0..0] VBATT pin low voltage detect circuit output enable                 */
15674             uint8_t               : 7;
15675         } VBTCMPCR_b;
15676     };
15677     __IM uint8_t RESERVED56;
15678 
15679     union
15680     {
15681         __IOM uint8_t VBTLVDICR;          /*!< (@ 0x000004B4) VBATT Pin Low Voltage Detect Interrupt Control
15682                                            *                  Register                                                   */
15683 
15684         struct
15685         {
15686             __IOM uint8_t VBTLVDIE   : 1; /*!< [0..0] VBATT Pin Low Voltage Detect Interrupt Enable bit                  */
15687             __IOM uint8_t VBTLVDISEL : 1; /*!< [1..1] Pin Low Voltage Detect Interrupt Select bit                        */
15688             uint8_t                  : 6;
15689         } VBTLVDICR_b;
15690     };
15691     __IM uint8_t RESERVED57;
15692 
15693     union
15694     {
15695         __IOM uint8_t VBTWCTLR;        /*!< (@ 0x000004B6) VBATT Wakeup function Control Register                     */
15696 
15697         struct
15698         {
15699             __IOM uint8_t VWEN : 1;    /*!< [0..0] VBATT wakeup enable                                                */
15700             uint8_t            : 7;
15701         } VBTWCTLR_b;
15702     };
15703     __IM uint8_t RESERVED58;
15704 
15705     union
15706     {
15707         __IOM uint8_t VBTWCH0OTSR;     /*!< (@ 0x000004B8) VBATT Wakeup I/O 0 Output Trigger Select Register          */
15708 
15709         struct
15710         {
15711             uint8_t                  : 1;
15712             __IOM uint8_t CH0VCH1TE  : 1; /*!< [1..1] VBATWIO0 Output VBATWIO1 Trigger Enable                            */
15713             __IOM uint8_t CH0VCH2TE  : 1; /*!< [2..2] VBATWIO0 Output VBATWIO2 Trigger Enable                            */
15714             __IOM uint8_t CH0VRTCTE  : 1; /*!< [3..3] VBATWIO0 Output RTC Periodic Signal Enable                         */
15715             __IOM uint8_t CH0VRTCATE : 1; /*!< [4..4] VBATWIO0 Output RTC Alarm Signal Enable                            */
15716             __IOM uint8_t CH0VAGTUTE : 1; /*!< [5..5] CH0 Output AGT(ch1) underflow Signal Enable                        */
15717             uint8_t                  : 2;
15718         } VBTWCH0OTSR_b;
15719     };
15720 
15721     union
15722     {
15723         __IOM uint8_t VBTWCH1OTSR;        /*!< (@ 0x000004B9) VBATT Wakeup I/O 1 Output Trigger Select Register          */
15724 
15725         struct
15726         {
15727             __IOM uint8_t CH1VCH0TE  : 1; /*!< [0..0] VBATWIO1 Output VBATWIO0 Trigger Enable                            */
15728             uint8_t                  : 1;
15729             __IOM uint8_t CH1VCH2TE  : 1; /*!< [2..2] VBATWIO1 Output VBATWIO2 Trigger Enable                            */
15730             __IOM uint8_t CH1VRTCTE  : 1; /*!< [3..3] VBATWIO1 Output RTC Periodic Signal Enable                         */
15731             __IOM uint8_t CH1VRTCATE : 1; /*!< [4..4] VBATWIO1 Output RTC Alarm Signal Enable                            */
15732             __IOM uint8_t CH1VAGTUTE : 1; /*!< [5..5] CH1 Output AGT(ch1) underflow Signal Enable                        */
15733             uint8_t                  : 2;
15734         } VBTWCH1OTSR_b;
15735     };
15736 
15737     union
15738     {
15739         __IOM uint8_t VBTWCH2OTSR;        /*!< (@ 0x000004BA) VBATT Wakeup I/O 2 Output Trigger Select Register          */
15740 
15741         struct
15742         {
15743             __IOM uint8_t CH2VCH0TE  : 1; /*!< [0..0] VBATWIO2 Output VBATWIO0 Trigger Enable                            */
15744             __IOM uint8_t CH2VCH1TE  : 1; /*!< [1..1] VBATWIO2 Output VBATWIO1 Trigger Enable                            */
15745             uint8_t                  : 1;
15746             __IOM uint8_t CH2VRTCTE  : 1; /*!< [3..3] VBATWIO2 Output RTC Periodic Signal Enable                         */
15747             __IOM uint8_t CH2VRTCATE : 1; /*!< [4..4] VBATWIO2 Output RTC Alarm Signal Enable                            */
15748             __IOM uint8_t CH2VAGTUTE : 1; /*!< [5..5] CH2 Output AGT(CH2) underflow Signal Enable                        */
15749             uint8_t                  : 2;
15750         } VBTWCH2OTSR_b;
15751     };
15752 
15753     union
15754     {
15755         __IOM uint8_t VBTICTLR;         /*!< (@ 0x000004BB) VBATT Input Control Register                               */
15756 
15757         struct
15758         {
15759             __IOM uint8_t VCH0INEN : 1; /*!< [0..0] RTCIC0 Input Enable                                                */
15760             __IOM uint8_t VCH1INEN : 1; /*!< [1..1] RTCIC1 Input Enable                                                */
15761             __IOM uint8_t VCH2INEN : 1; /*!< [2..2] RTCIC2 Input Enable                                                */
15762             uint8_t                : 5;
15763         } VBTICTLR_b;
15764     };
15765 
15766     union
15767     {
15768         __IOM uint8_t VBTOCTLR;          /*!< (@ 0x000004BC) VBATT Output Control Register                              */
15769 
15770         struct
15771         {
15772             __IOM uint8_t VCH0OEN   : 1; /*!< [0..0] VBATT Wakeup I/O 0 Output Enable                                   */
15773             __IOM uint8_t VCH1OEN   : 1; /*!< [1..1] VBATT Wakeup I/O 1 Output Enable                                   */
15774             __IOM uint8_t VCH2OEN   : 1; /*!< [2..2] VBATT Wakeup I/O 2 Output Enable                                   */
15775             __IOM uint8_t VOUT0LSEL : 1; /*!< [3..3] VBATT Wakeup I/O 0 Output Level Selection                          */
15776             __IOM uint8_t VCOU1LSEL : 1; /*!< [4..4] VBATT Wakeup I/O 1 Output Level Selection                          */
15777             __IOM uint8_t VOUT2LSEL : 1; /*!< [5..5] VBATT Wakeup I/O 2 Output Level Selection                          */
15778             uint8_t                 : 2;
15779         } VBTOCTLR_b;
15780     };
15781 
15782     union
15783     {
15784         __IOM uint8_t VBTWTER;         /*!< (@ 0x000004BD) VBATT Wakeup Trigger source Enable Register                */
15785 
15786         struct
15787         {
15788             __IOM uint8_t VCH0E  : 1;  /*!< [0..0] VBATWIO0 Pin Enable                                                */
15789             __IOM uint8_t VCH1E  : 1;  /*!< [1..1] VBATWIO1 Pin Enable                                                */
15790             __IOM uint8_t VCH2E  : 1;  /*!< [2..2] VBATWIO2 Pin Enable                                                */
15791             __IOM uint8_t VRTCIE : 1;  /*!< [3..3] RTC Periodic Signal Enable                                         */
15792             __IOM uint8_t VRTCAE : 1;  /*!< [4..4] RTC Alarm Signal Enable                                            */
15793             __IOM uint8_t VAGTUE : 1;  /*!< [5..5] AGT(ch1) underflow Signal Enable                                   */
15794             uint8_t              : 2;
15795         } VBTWTER_b;
15796     };
15797 
15798     union
15799     {
15800         __IOM uint8_t VBTWEGR;         /*!< (@ 0x000004BE) VBATT Wakeup Trigger source Edge Register                  */
15801 
15802         struct
15803         {
15804             __IOM uint8_t VCH0EG : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Source Edge Select                         */
15805             __IOM uint8_t VCH1EG : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Source Edge Select                         */
15806             __IOM uint8_t VCH2EG : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Source Edge Select                         */
15807             uint8_t              : 5;
15808         } VBTWEGR_b;
15809     };
15810 
15811     union
15812     {
15813         __IOM uint8_t VBTWFR;          /*!< (@ 0x000004BF) VBATT Wakeup trigger source Flag Register                  */
15814 
15815         struct
15816         {
15817             __IOM uint8_t VCH0F  : 1;  /*!< [0..0] VBATWIO0 Wakeup Trigger Flag                                       */
15818             __IOM uint8_t VCH1F  : 1;  /*!< [1..1] VBATWIO1 Wakeup Trigger Flag                                       */
15819             __IOM uint8_t VCH2F  : 1;  /*!< [2..2] VBATWIO2 Wakeup Trigger Flag                                       */
15820             __IOM uint8_t VRTCIF : 1;  /*!< [3..3] VBATT RTC-Interval Wakeup Trigger Flag                             */
15821             __IOM uint8_t VRTCAF : 1;  /*!< [4..4] VBATT RTC-Alarm Wakeup Trigger Flag                                */
15822             __IOM uint8_t VAGTUF : 1;  /*!< [5..5] AGT(ch1) underflow VBATT Wakeup Trigger Flag                       */
15823             uint8_t              : 2;
15824         } VBTWFR_b;
15825     };
15826 
15827     union
15828     {
15829         __IOM uint8_t VBTBER;          /*!< (@ 0x000004C0) VBATT Backup Enable Register                               */
15830 
15831         struct
15832         {
15833             uint8_t            : 3;
15834             __IOM uint8_t VBAE : 1;    /*!< [3..3] VBATT backup register access enable bit                            */
15835             uint8_t            : 4;
15836         } VBTBER_b;
15837     };
15838     __IM uint8_t  RESERVED59;
15839     __IM uint16_t RESERVED60;
15840     __IM uint32_t RESERVED61[15];
15841 
15842     union
15843     {
15844         __IOM uint8_t VBTBKR[512];     /*!< (@ 0x00000500) VBATT Backup Register [0..511]                             */
15845 
15846         struct
15847         {
15848             __IOM uint8_t VBTBKR : 8;  /*!< [7..0] VBTBKR is a 512-byte readable/writable register to store
15849                                         *   data powered by VBATT.The value of this register is retained
15850                                         *   even when VCC is not powered but VBATT is powered.VBTBKR
15851                                         *   is initialized by VBATT selected voltage power-on-reset.                  */
15852         } VBTBKR_b[512];
15853     };
15854 } R_SYSTEM_Type;                       /*!< Size = 1792 (0x700)                                                       */
15855 
15856 /* =========================================================================================================================== */
15857 /* ================                                         R_TSN_CAL                                         ================ */
15858 /* =========================================================================================================================== */
15859 
15860 /**
15861  * @brief Temperature Sensor (R_TSN_CAL)
15862  */
15863 
15864 typedef struct                         /*!< (@ 0x407FB17C) R_TSN_CAL Structure                                        */
15865 {
15866     union
15867     {
15868         __IM uint32_t TSCDR;           /*!< (@ 0x00000000) Temperature Sensor 32 bit Calibration Data Register        */
15869 
15870         struct
15871         {
15872             __IM uint32_t TSCDR : 32;  /*!< [31..0] The 32 bit TSCDR register stores temperature sensor
15873                                         *   calibration converted value.                                              */
15874         } TSCDR_b;
15875     };
15876 } R_TSN_CAL_Type;                      /*!< Size = 4 (0x4)                                                            */
15877 
15878 /* =========================================================================================================================== */
15879 /* ================                                        R_TSN_CTRL                                         ================ */
15880 /* =========================================================================================================================== */
15881 
15882 /**
15883  * @brief Temperature Sensor (R_TSN_CTRL)
15884  */
15885 
15886 typedef struct                         /*!< (@ 0x400F3000) R_TSN_CTRL Structure                                       */
15887 {
15888     union
15889     {
15890         __IOM uint8_t TSCR;            /*!< (@ 0x00000000) Temperature Sensor Control Register                        */
15891 
15892         struct
15893         {
15894             uint8_t            : 4;
15895             __IOM uint8_t TSOE : 1;    /*!< [4..4] Temperature Sensor Enable                                          */
15896             uint8_t            : 2;
15897             __IOM uint8_t TSEN : 1;    /*!< [7..7] Temperature Sensor Output Enable                                   */
15898         } TSCR_b;
15899     };
15900 } R_TSN_CTRL_Type;                     /*!< Size = 1 (0x1)                                                            */
15901 
15902 /* =========================================================================================================================== */
15903 /* ================                                         R_USB_FS0                                         ================ */
15904 /* =========================================================================================================================== */
15905 
15906 /**
15907  * @brief USB 2.0 Module (R_USB_FS0)
15908  */
15909 
15910 typedef struct                         /*!< (@ 0x40090000) R_USB_FS0 Structure                                        */
15911 {
15912     union
15913     {
15914         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
15915 
15916         struct
15917         {
15918             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
15919             uint16_t             : 2;
15920             __IOM uint16_t DMRPU : 1;  /*!< [3..3] D- Line Resistor Control                                           */
15921             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
15922             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
15923             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
15924             uint16_t             : 1;
15925             __IOM uint16_t CNEN  : 1;  /*!< [8..8] CNEN Single End Receiver Enable                                    */
15926             uint16_t             : 1;
15927             __IOM uint16_t SCKE  : 1;  /*!< [10..10] USB Clock Enable                                                 */
15928             uint16_t             : 5;
15929         } SYSCFG_b;
15930     };
15931 
15932     union
15933     {
15934         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
15935 
15936         struct
15937         {
15938             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
15939                                         *   access cycles)                                                            */
15940             uint16_t : 12;
15941         } BUSWAIT_b;
15942     };
15943 
15944     union
15945     {
15946         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register 0                     */
15947 
15948         struct
15949         {
15950             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
15951             __IM uint16_t IDMON : 1;   /*!< [2..2] External ID0 Input Pin Monitor                                     */
15952             uint16_t            : 2;
15953             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
15954                                         *   Selected.                                                                 */
15955             __IM uint16_t HTACT  : 1;  /*!< [6..6] USB Host Sequencer Status Monitor                                  */
15956             uint16_t             : 7;
15957             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe
15958                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
15959                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
15960                                         *   pin.                                                                      */
15961         } SYSSTS0_b;
15962     };
15963 
15964     union
15965     {
15966         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
15967 
15968         struct
15969         {
15970             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
15971             uint16_t              : 15;
15972         } PLLSTA_b;
15973     };
15974 
15975     union
15976     {
15977         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
15978 
15979         struct
15980         {
15981             __IM uint16_t RHST     : 3; /*!< [2..0] USB Bus Reset Status                                               */
15982             uint16_t               : 1;
15983             __IOM uint16_t UACT    : 1; /*!< [4..4] USB Bus Enable                                                     */
15984             __IOM uint16_t RESUME  : 1; /*!< [5..5] Resume Output                                                      */
15985             __IOM uint16_t USBRST  : 1; /*!< [6..6] USB Bus Reset Output                                               */
15986             __IOM uint16_t RWUPE   : 1; /*!< [7..7] Wakeup Detection Enable                                            */
15987             __IOM uint16_t WKUP    : 1; /*!< [8..8] Wakeup Output                                                      */
15988             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USB_VBUSEN Output Pin Control                                      */
15989             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USB_EXICEN Output Pin Control                                    */
15990             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control This bit is
15991                                          *   used when switching from device B to device A while in
15992                                          *   OTG mode. If the HNPBTOA bit is 1, the internal function
15993                                          *   control keeps the suspended state until the HNP processing
15994                                          *   ends even though SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is
15995                                          *   set.                                                                      */
15996             uint16_t : 4;
15997         } DVSTCTR0_b;
15998     };
15999     __IM uint16_t RESERVED;
16000 
16001     union
16002     {
16003         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
16004 
16005         struct
16006         {
16007             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
16008             uint16_t            : 12;
16009         } TESTMODE_b;
16010     };
16011     __IM uint16_t RESERVED1;
16012     __IM uint32_t RESERVED2;
16013 
16014     union
16015     {
16016         __IOM uint32_t CFIFO;          /*!< (@ 0x00000014) CFIFO Port Register                                        */
16017 
16018         struct
16019         {
16020             union
16021             {
16022                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
16023                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
16024             };
16025 
16026             union
16027             {
16028                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
16029 
16030                 struct
16031                 {
16032                     __IM uint8_t  RESERVED3;
16033                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
16034                 };
16035             };
16036         };
16037     };
16038 
16039     union
16040     {
16041         __IOM uint32_t D0FIFO;         /*!< (@ 0x00000018) D0FIFO Port Register                                       */
16042 
16043         struct
16044         {
16045             union
16046             {
16047                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
16048                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
16049             };
16050 
16051             union
16052             {
16053                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
16054 
16055                 struct
16056                 {
16057                     __IM uint8_t  RESERVED4;
16058                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
16059                 };
16060             };
16061         };
16062     };
16063 
16064     union
16065     {
16066         __IOM uint32_t D1FIFO;         /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
16067 
16068         struct
16069         {
16070             union
16071             {
16072                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
16073                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
16074             };
16075 
16076             union
16077             {
16078                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
16079 
16080                 struct
16081                 {
16082                     __IM uint8_t  RESERVED5;
16083                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
16084                 };
16085             };
16086         };
16087     };
16088 
16089     union
16090     {
16091         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
16092 
16093         struct
16094         {
16095             __IOM uint16_t CURPIPE : 4; /*!< [3..0] CFIFO Port Access Pipe Specification                               */
16096             uint16_t               : 1;
16097             __IOM uint16_t ISEL    : 1; /*!< [5..5] CFIFO Port Access Direction When DCP is Selected                   */
16098             uint16_t               : 2;
16099             __IOM uint16_t BIGEND  : 1; /*!< [8..8] CFIFO Port Endian Control                                          */
16100             uint16_t               : 1;
16101             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
16102             uint16_t               : 2;
16103             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
16104             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
16105         } CFIFOSEL_b;
16106     };
16107 
16108     union
16109     {
16110         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
16111 
16112         struct
16113         {
16114             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
16115                                         *   data.                                                                     */
16116             uint16_t            : 1;
16117             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
16118             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
16119             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
16120         } CFIFOCTR_b;
16121     };
16122     __IM uint32_t RESERVED6;
16123 
16124     union
16125     {
16126         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
16127 
16128         struct
16129         {
16130             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
16131             uint16_t               : 4;
16132             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
16133             uint16_t               : 1;
16134             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
16135             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
16136             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
16137                                          *   Pipe Data is Read                                                         */
16138             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer RewindNote: Only 0 can be read.                   */
16139             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
16140         } D0FIFOSEL_b;
16141     };
16142 
16143     union
16144     {
16145         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
16146 
16147         struct
16148         {
16149             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
16150                                         *   data.                                                                     */
16151             uint16_t            : 1;
16152             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
16153             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
16154             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
16155         } D0FIFOCTR_b;
16156     };
16157 
16158     union
16159     {
16160         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
16161 
16162         struct
16163         {
16164             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
16165             uint16_t               : 4;
16166             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
16167             uint16_t               : 1;
16168             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
16169             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA/DTC Transfer Request Enable                                  */
16170             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
16171                                          *   Pipe Data is Read                                                         */
16172             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
16173             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
16174         } D1FIFOSEL_b;
16175     };
16176 
16177     union
16178     {
16179         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
16180 
16181         struct
16182         {
16183             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data LengthIndicates the length of the receive
16184                                         *   data.                                                                     */
16185             uint16_t            : 1;
16186             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
16187             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer ClearNote: Only 0 can be read.                        */
16188             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
16189         } D1FIFOCTR_b;
16190     };
16191 
16192     union
16193     {
16194         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
16195 
16196         struct
16197         {
16198             uint16_t             : 8;
16199             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
16200             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
16201             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
16202             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
16203             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
16204             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
16205             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
16206             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
16207         } INTENB0_b;
16208     };
16209 
16210     union
16211     {
16212         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
16213 
16214         struct
16215         {
16216             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
16217             uint16_t                  : 3;
16218             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
16219             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
16220             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
16221             uint16_t                  : 4;
16222             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
16223             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
16224             uint16_t                  : 1;
16225             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
16226             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Enable                        */
16227         } INTENB1_b;
16228     };
16229     __IM uint16_t RESERVED7;
16230 
16231     union
16232     {
16233         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
16234 
16235         struct
16236         {
16237             __IOM uint16_t PIPE0BRDYE : 1; /*!< [0..0] BRDY Interrupt Enable for PIPE                                     */
16238             __IOM uint16_t PIPE1BRDYE : 1; /*!< [1..1] BRDY Interrupt Enable for PIPE                                     */
16239             __IOM uint16_t PIPE2BRDYE : 1; /*!< [2..2] BRDY Interrupt Enable for PIPE                                     */
16240             __IOM uint16_t PIPE3BRDYE : 1; /*!< [3..3] BRDY Interrupt Enable for PIPE                                     */
16241             __IOM uint16_t PIPE4BRDYE : 1; /*!< [4..4] BRDY Interrupt Enable for PIPE                                     */
16242             __IOM uint16_t PIPE5BRDYE : 1; /*!< [5..5] BRDY Interrupt Enable for PIPE                                     */
16243             __IOM uint16_t PIPE6BRDYE : 1; /*!< [6..6] BRDY Interrupt Enable for PIPE                                     */
16244             __IOM uint16_t PIPE7BRDYE : 1; /*!< [7..7] BRDY Interrupt Enable for PIPE                                     */
16245             __IOM uint16_t PIPE8BRDYE : 1; /*!< [8..8] BRDY Interrupt Enable for PIPE                                     */
16246             __IOM uint16_t PIPE9BRDYE : 1; /*!< [9..9] BRDY Interrupt Enable for PIPE                                     */
16247             uint16_t                  : 6;
16248         } BRDYENB_b;
16249     };
16250 
16251     union
16252     {
16253         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
16254 
16255         struct
16256         {
16257             __IOM uint16_t PIPE0NRDYE : 1; /*!< [0..0] NRDY Interrupt Enable for PIPE                                     */
16258             __IOM uint16_t PIPE1NRDYE : 1; /*!< [1..1] NRDY Interrupt Enable for PIPE                                     */
16259             __IOM uint16_t PIPE2NRDYE : 1; /*!< [2..2] NRDY Interrupt Enable for PIPE                                     */
16260             __IOM uint16_t PIPE3NRDYE : 1; /*!< [3..3] NRDY Interrupt Enable for PIPE                                     */
16261             __IOM uint16_t PIPE4NRDYE : 1; /*!< [4..4] NRDY Interrupt Enable for PIPE                                     */
16262             __IOM uint16_t PIPE5NRDYE : 1; /*!< [5..5] NRDY Interrupt Enable for PIPE                                     */
16263             __IOM uint16_t PIPE6NRDYE : 1; /*!< [6..6] NRDY Interrupt Enable for PIPE                                     */
16264             __IOM uint16_t PIPE7NRDYE : 1; /*!< [7..7] NRDY Interrupt Enable for PIPE                                     */
16265             __IOM uint16_t PIPE8NRDYE : 1; /*!< [8..8] NRDY Interrupt Enable for PIPE                                     */
16266             __IOM uint16_t PIPE9NRDYE : 1; /*!< [9..9] NRDY Interrupt Enable for PIPE                                     */
16267             uint16_t                  : 6;
16268         } NRDYENB_b;
16269     };
16270 
16271     union
16272     {
16273         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
16274 
16275         struct
16276         {
16277             __IOM uint16_t PIPE0BEMPE : 1; /*!< [0..0] BEMP Interrupt Enable for PIPE                                     */
16278             __IOM uint16_t PIPE1BEMPE : 1; /*!< [1..1] BEMP Interrupt Enable for PIPE                                     */
16279             __IOM uint16_t PIPE2BEMPE : 1; /*!< [2..2] BEMP Interrupt Enable for PIPE                                     */
16280             __IOM uint16_t PIPE3BEMPE : 1; /*!< [3..3] BEMP Interrupt Enable for PIPE                                     */
16281             __IOM uint16_t PIPE4BEMPE : 1; /*!< [4..4] BEMP Interrupt Enable for PIPE                                     */
16282             __IOM uint16_t PIPE5BEMPE : 1; /*!< [5..5] BEMP Interrupt Enable for PIPE                                     */
16283             __IOM uint16_t PIPE6BEMPE : 1; /*!< [6..6] BEMP Interrupt Enable for PIPE                                     */
16284             __IOM uint16_t PIPE7BEMPE : 1; /*!< [7..7] BEMP Interrupt Enable for PIPE                                     */
16285             __IOM uint16_t PIPE8BEMPE : 1; /*!< [8..8] BEMP Interrupt Enable for PIPE                                     */
16286             __IOM uint16_t PIPE9BEMPE : 1; /*!< [9..9] BEMP Interrupt Enable for PIPE                                     */
16287             uint16_t                  : 6;
16288         } BEMPENB_b;
16289     };
16290 
16291     union
16292     {
16293         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Output Configuration Register                          */
16294 
16295         struct
16296         {
16297             uint16_t                : 4;
16298             __IM uint16_t  EDGESTS  : 1; /*!< [4..4] Edge Interrupt Output Status Monitor                               */
16299             __IOM uint16_t INTL     : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
16300             __IOM uint16_t BRDYM    : 1; /*!< [6..6] BRDY Interrupt Status Clear Timing                                 */
16301             uint16_t                : 1;
16302             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select                                    */
16303             uint16_t                : 7;
16304         } SOFCFG_b;
16305     };
16306 
16307     union
16308     {
16309         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
16310 
16311         struct
16312         {
16313             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
16314             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
16315             uint16_t                : 1;
16316             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
16317             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
16318             uint16_t                : 2;
16319             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
16320             uint16_t                : 1;
16321             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
16322             uint16_t                : 3;
16323             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
16324         } PHYSET_b;
16325     };
16326 
16327     union
16328     {
16329         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
16330 
16331         struct
16332         {
16333             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
16334             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
16335             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
16336             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
16337             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
16338             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
16339             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
16340             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
16341             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
16342             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
16343             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
16344             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
16345         } INTSTS0_b;
16346     };
16347 
16348     union
16349     {
16350         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
16351 
16352         struct
16353         {
16354             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET0 Detection Interrupt Status                                  */
16355             uint16_t                 : 3;
16356             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
16357             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
16358             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
16359             uint16_t                 : 1;
16360             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
16361             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
16362             uint16_t                 : 1;
16363             __IOM uint16_t ATTCH     : 1; /*!< [11..11] ATTCH Interrupt Status                                           */
16364             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
16365             uint16_t                 : 1;
16366             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
16367             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Input Change Interrupt Status                        */
16368         } INTSTS1_b;
16369     };
16370     __IM uint16_t RESERVED8;
16371 
16372     union
16373     {
16374         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
16375 
16376         struct
16377         {
16378             __IOM uint16_t PIPE0BRDY : 1; /*!< [0..0] BRDY Interrupt Status for PIPE                                     */
16379             __IOM uint16_t PIPE1BRDY : 1; /*!< [1..1] BRDY Interrupt Status for PIPE                                     */
16380             __IOM uint16_t PIPE2BRDY : 1; /*!< [2..2] BRDY Interrupt Status for PIPE                                     */
16381             __IOM uint16_t PIPE3BRDY : 1; /*!< [3..3] BRDY Interrupt Status for PIPE                                     */
16382             __IOM uint16_t PIPE4BRDY : 1; /*!< [4..4] BRDY Interrupt Status for PIPE                                     */
16383             __IOM uint16_t PIPE5BRDY : 1; /*!< [5..5] BRDY Interrupt Status for PIPE                                     */
16384             __IOM uint16_t PIPE6BRDY : 1; /*!< [6..6] BRDY Interrupt Status for PIPE                                     */
16385             __IOM uint16_t PIPE7BRDY : 1; /*!< [7..7] BRDY Interrupt Status for PIPE                                     */
16386             __IOM uint16_t PIPE8BRDY : 1; /*!< [8..8] BRDY Interrupt Status for PIPE                                     */
16387             __IOM uint16_t PIPE9BRDY : 1; /*!< [9..9] BRDY Interrupt Status for PIPE                                     */
16388             uint16_t                 : 6;
16389         } BRDYSTS_b;
16390     };
16391 
16392     union
16393     {
16394         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
16395 
16396         struct
16397         {
16398             __IOM uint16_t PIPE0NRDY : 1; /*!< [0..0] NRDY Interrupt Status for PIPE                                     */
16399             __IOM uint16_t PIPE1NRDY : 1; /*!< [1..1] NRDY Interrupt Status for PIPE                                     */
16400             __IOM uint16_t PIPE2NRDY : 1; /*!< [2..2] NRDY Interrupt Status for PIPE                                     */
16401             __IOM uint16_t PIPE3NRDY : 1; /*!< [3..3] NRDY Interrupt Status for PIPE                                     */
16402             __IOM uint16_t PIPE4NRDY : 1; /*!< [4..4] NRDY Interrupt Status for PIPE                                     */
16403             __IOM uint16_t PIPE5NRDY : 1; /*!< [5..5] NRDY Interrupt Status for PIPE                                     */
16404             __IOM uint16_t PIPE6NRDY : 1; /*!< [6..6] NRDY Interrupt Status for PIPE                                     */
16405             __IOM uint16_t PIPE7NRDY : 1; /*!< [7..7] NRDY Interrupt Status for PIPE                                     */
16406             __IOM uint16_t PIPE8NRDY : 1; /*!< [8..8] NRDY Interrupt Status for PIPE                                     */
16407             __IOM uint16_t PIPE9NRDY : 1; /*!< [9..9] NRDY Interrupt Status for PIPE                                     */
16408             uint16_t                 : 6;
16409         } NRDYSTS_b;
16410     };
16411 
16412     union
16413     {
16414         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
16415 
16416         struct
16417         {
16418             __IOM uint16_t PIPE0BEMP : 1; /*!< [0..0] BEMP Interrupt Status for PIPE                                     */
16419             __IOM uint16_t PIPE1BEMP : 1; /*!< [1..1] BEMP Interrupt Status for PIPE                                     */
16420             __IOM uint16_t PIPE2BEMP : 1; /*!< [2..2] BEMP Interrupt Status for PIPE                                     */
16421             __IOM uint16_t PIPE3BEMP : 1; /*!< [3..3] BEMP Interrupt Status for PIPE                                     */
16422             __IOM uint16_t PIPE4BEMP : 1; /*!< [4..4] BEMP Interrupt Status for PIPE                                     */
16423             __IOM uint16_t PIPE5BEMP : 1; /*!< [5..5] BEMP Interrupt Status for PIPE                                     */
16424             __IOM uint16_t PIPE6BEMP : 1; /*!< [6..6] BEMP Interrupt Status for PIPE                                     */
16425             __IOM uint16_t PIPE7BEMP : 1; /*!< [7..7] BEMP Interrupt Status for PIPE                                     */
16426             __IOM uint16_t PIPE8BEMP : 1; /*!< [8..8] BEMP Interrupt Status for PIPE                                     */
16427             __IOM uint16_t PIPE9BEMP : 1; /*!< [9..9] BEMP Interrupt Status for PIPE                                     */
16428             uint16_t                 : 6;
16429         } BEMPSTS_b;
16430     };
16431 
16432     union
16433     {
16434         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
16435 
16436         struct
16437         {
16438             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame NumberLatest frame number                                   */
16439             uint16_t            : 3;
16440             __IOM uint16_t CRCE : 1;   /*!< [14..14] Receive Data Error                                               */
16441             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
16442         } FRMNUM_b;
16443     };
16444 
16445     union
16446     {
16447         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
16448 
16449         struct
16450         {
16451             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
16452             uint16_t             : 12;
16453             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
16454         } UFRMNUM_b;
16455     };
16456 
16457     union
16458     {
16459         __IOM uint16_t USBADDR;           /*!< (@ 0x00000050) USB Address Register                                       */
16460 
16461         struct
16462         {
16463             __IM uint16_t USBADDR : 7;    /*!< [6..0] USB Address In device controller mode, these flags indicate
16464                                            *   the USB address assigned by the host when the USBHS processed
16465                                            *   the SET_ADDRESS request successfully.                                     */
16466             uint16_t                 : 1;
16467             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
16468             uint16_t                 : 5;
16469         } USBADDR_b;
16470     };
16471     __IM uint16_t RESERVED9;
16472 
16473     union
16474     {
16475         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
16476 
16477         struct
16478         {
16479             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request TypeThese bits store the USB request bmRequestType
16480                                                *   value.                                                                    */
16481             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] RequestThese bits store the USB request bRequest value.           */
16482         } USBREQ_b;
16483     };
16484 
16485     union
16486     {
16487         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
16488 
16489         struct
16490         {
16491             __IOM uint16_t WVALUE : 16; /*!< [15..0] ValueThese bits store the USB request Value value.                */
16492         } USBVAL_b;
16493     };
16494 
16495     union
16496     {
16497         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
16498 
16499         struct
16500         {
16501             __IOM uint16_t WINDEX : 16; /*!< [15..0] IndexThese bits store the USB request wIndex value.               */
16502         } USBINDX_b;
16503     };
16504 
16505     union
16506     {
16507         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
16508 
16509         struct
16510         {
16511             __IOM uint16_t WLENGTH : 16; /*!< [15..0] LengthThese bits store the USB request wLength value.             */
16512         } USBLENG_b;
16513     };
16514 
16515     union
16516     {
16517         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
16518 
16519         struct
16520         {
16521             uint16_t              : 4;
16522             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
16523             uint16_t              : 2;
16524             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
16525             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
16526             uint16_t              : 7;
16527         } DCPCFG_b;
16528     };
16529 
16530     union
16531     {
16532         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
16533 
16534         struct
16535         {
16536             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits set the maximum amount
16537                                         *   of data (maximum packet size) in payloads for the DCP.                    */
16538             uint16_t              : 5;
16539             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
16540         } DCPMAXP_b;
16541     };
16542 
16543     union
16544     {
16545         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
16546 
16547         struct
16548         {
16549             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
16550             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
16551             uint16_t                : 2;
16552             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
16553             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
16554             __IOM uint16_t SQSET    : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
16555             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
16556             uint16_t                : 2;
16557             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
16558             uint16_t                : 2;
16559             __IOM uint16_t SUREQ    : 1; /*!< [14..14] Setup Token Transmission                                         */
16560             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
16561         } DCPCTR_b;
16562     };
16563     __IM uint16_t RESERVED10;
16564 
16565     union
16566     {
16567         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
16568 
16569         struct
16570         {
16571             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
16572             uint16_t               : 12;
16573         } PIPESEL_b;
16574     };
16575     __IM uint16_t RESERVED11;
16576 
16577     union
16578     {
16579         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
16580 
16581         struct
16582         {
16583             __IOM uint16_t EPNUM : 4;  /*!< [3..0] Endpoint NumberThese bits specify the endpoint number
16584                                         *   for the selected pipe.Setting 0000b means unused pipe.                    */
16585             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
16586             uint16_t              : 2;
16587             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
16588             uint16_t              : 1;
16589             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
16590             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
16591             uint16_t              : 3;
16592             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
16593         } PIPECFG_b;
16594     };
16595     __IM uint16_t RESERVED12;
16596 
16597     union
16598     {
16599         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
16600 
16601         struct
16602         {
16603             __IOM uint16_t MXPS : 9;   /*!< [8..0] Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to
16604                                         *   256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes
16605                                         *   (010h), 32 bytes (020h), 64 bytes (040h) (Bits [8:7] and
16606                                         *   [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to
16607                                         *   64 bytes (040h) (Bits [8:7] are not provided.)                            */
16608             uint16_t              : 3;
16609             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device Select                                                    */
16610         } PIPEMAXP_b;
16611     };
16612 
16613     union
16614     {
16615         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
16616 
16617         struct
16618         {
16619             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalSpecifies the interval
16620                                         *   error detection timing for the selected pipe in terms of
16621                                         *   frames, which is expressed as nth power of 2.                             */
16622             uint16_t            : 9;
16623             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
16624             uint16_t            : 3;
16625         } PIPEPERI_b;
16626     };
16627 
16628     union
16629     {
16630         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) Pipe [0..8] Control Register                               */
16631 
16632         struct
16633         {
16634             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
16635             uint16_t              : 3;
16636             __IM uint16_t  PBUSY  : 1; /*!< [5..5] Pipe Busy                                                          */
16637             __IM uint16_t  SQMON  : 1; /*!< [6..6] Sequence Toggle Bit Confirmation                                   */
16638             __IOM uint16_t SQSET  : 1; /*!< [7..7] Sequence Toggle Bit Set                                            */
16639             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Sequence Toggle Bit Clear                                          */
16640             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
16641             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
16642             uint16_t              : 1;
16643             __IM uint16_t CSSTS   : 1; /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
16644                                         *   Split Transaction of the relevant pipe                                    */
16645             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
16646                                         *   the CSSTS bit of the relevant pipe                                        */
16647             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer Monitor                                          */
16648             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
16649         } PIPE_CTR_b[9];
16650     };
16651     __IM uint16_t                RESERVED13;
16652     __IM uint32_t                RESERVED14[3];
16653     __IOM R_USB_FS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
16654     __IM uint32_t                RESERVED15[3];
16655 
16656     union
16657     {
16658         __IOM uint16_t USBBCCTRL0;         /*!< (@ 0x000000B0) BC Control Register 0                                      */
16659 
16660         struct
16661         {
16662             __IOM uint16_t RPDME0     : 1; /*!< [0..0] D- Pin Pull-Down Control                                           */
16663             __IOM uint16_t IDPSRCE0   : 1; /*!< [1..1] D+ Pin IDPSRC Output Control                                       */
16664             __IOM uint16_t IDMSINKE0  : 1; /*!< [2..2] D- Pin 0.6 V Input Detection (Comparator and Sink) Control         */
16665             __IOM uint16_t VDPSRCE0   : 1; /*!< [3..3] D+ Pin VDPSRC (0.6 V) Output Control                               */
16666             __IOM uint16_t IDPSINKE0  : 1; /*!< [4..4] D+ Pin 0.6 V Input Detection (Comparator and Sink) Control         */
16667             __IOM uint16_t VDMSRCE0   : 1; /*!< [5..5] D- Pin VDMSRC (0.6 V) Output Control                               */
16668             uint16_t                  : 1;
16669             __IOM uint16_t BATCHGE0   : 1; /*!< [7..7] BC (Battery Charger) Function Ch0 General Enable Control           */
16670             __IM uint16_t  CHGDETSTS0 : 1; /*!< [8..8] D- Pin 0.6 V Input Detection Status                                */
16671             __IM uint16_t  PDDETSTS0  : 1; /*!< [9..9] D+ Pin 0.6 V Input Detection Status                                */
16672             uint16_t                  : 6;
16673         } USBBCCTRL0_b;
16674     };
16675     __IM uint16_t RESERVED16;
16676     __IM uint32_t RESERVED17[4];
16677 
16678     union
16679     {
16680         __IOM uint16_t UCKSEL;          /*!< (@ 0x000000C4) USB Clock Selection Register                               */
16681 
16682         struct
16683         {
16684             __IOM uint16_t UCKSELC : 1; /*!< [0..0] USB Clock Selection                                                */
16685             uint16_t               : 15;
16686         } UCKSEL_b;
16687     };
16688     __IM uint16_t RESERVED18;
16689     __IM uint32_t RESERVED19;
16690 
16691     union
16692     {
16693         __IOM uint16_t USBMC;           /*!< (@ 0x000000CC) USB Module Control Register                                */
16694 
16695         struct
16696         {
16697             __IOM uint16_t VDDUSBE : 1; /*!< [0..0] USB Reference Power Supply Circuit On/Off Control                  */
16698             uint16_t               : 6;
16699             __IOM uint16_t VDCEN   : 1; /*!< [7..7] USB Regulator On/Off Control                                       */
16700             uint16_t               : 8;
16701         } USBMC_b;
16702     };
16703     __IM uint16_t RESERVED20;
16704 
16705     union
16706     {
16707         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
16708 
16709         struct
16710         {
16711             uint16_t               : 6;
16712             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
16713             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
16714             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
16715             uint16_t               : 1;
16716         } DEVADD_b[10];
16717     };
16718     __IM uint32_t RESERVED21[3];
16719 
16720     union
16721     {
16722         __IOM uint32_t PHYSLEW;         /*!< (@ 0x000000F0) PHY Cross Point Adjustment Register                        */
16723 
16724         struct
16725         {
16726             __IOM uint32_t SLEWR00 : 1; /*!< [0..0] Receiver Cross Point Adjustment 00                                 */
16727             __IOM uint32_t SLEWR01 : 1; /*!< [1..1] Receiver Cross Point Adjustment 01                                 */
16728             __IOM uint32_t SLEWF00 : 1; /*!< [2..2] Receiver Cross Point Adjustment 00                                 */
16729             __IOM uint32_t SLEWF01 : 1; /*!< [3..3] Receiver Cross Point Adjustment 01                                 */
16730             uint32_t               : 28;
16731         } PHYSLEW_b;
16732     };
16733     __IM uint32_t RESERVED22[3];
16734 
16735     union
16736     {
16737         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
16738 
16739         struct
16740         {
16741             uint16_t             : 7;
16742             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
16743             uint16_t             : 8;
16744         } LPCTRL_b;
16745     };
16746 
16747     union
16748     {
16749         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
16750 
16751         struct
16752         {
16753             uint16_t                : 14;
16754             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
16755             uint16_t                : 1;
16756         } LPSTS_b;
16757     };
16758     __IM uint32_t RESERVED23[15];
16759 
16760     union
16761     {
16762         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
16763 
16764         struct
16765         {
16766             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
16767             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
16768             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
16769             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
16770             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
16771             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
16772             uint16_t                : 2;
16773             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
16774             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
16775             uint16_t                : 6;
16776         } BCCTRL_b;
16777     };
16778     __IM uint16_t RESERVED24;
16779 
16780     union
16781     {
16782         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
16783 
16784         struct
16785         {
16786             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
16787             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
16788             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
16789                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
16790             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
16791                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
16792             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
16793                                           *   value used for L1NEGOMD.The format is the same as the HIRD
16794                                           *   field in HL1CTRL.                                                         */
16795             uint16_t               : 2;
16796             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
16797             uint16_t               : 1;
16798         } PL1CTRL1_b;
16799     };
16800 
16801     union
16802     {
16803         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
16804 
16805         struct
16806         {
16807             uint16_t               : 8;
16808             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
16809             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
16810             uint16_t               : 3;
16811         } PL1CTRL2_b;
16812     };
16813 
16814     union
16815     {
16816         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
16817 
16818         struct
16819         {
16820             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
16821             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
16822             uint16_t                : 13;
16823         } HL1CTRL1_b;
16824     };
16825 
16826     union
16827     {
16828         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
16829 
16830         struct
16831         {
16832             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
16833                                         *   be set in the ADDR field of LPM token.                                    */
16834             uint16_t             : 4;
16835             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
16836             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
16837                                         *   value to be set in the RWE field of LPM token.                            */
16838             uint16_t            : 2;
16839             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
16840                                         *   period at the time of L1 Resume.                                          */
16841         } HL1CTRL2_b;
16842     };
16843     __IM uint32_t RESERVED25[5];
16844 
16845     union
16846     {
16847         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
16848                                         *                  Register                                                   */
16849 
16850         struct
16851         {
16852             uint32_t              : 20;
16853             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
16854                                          *   HS side of USB port.                                                      */
16855             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
16856                                          *   HS side of USB port.                                                      */
16857             uint32_t               : 1;
16858             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
16859                                          *   of USB port.                                                              */
16860             uint32_t : 8;
16861         } DPUSR0R_b;
16862     };
16863 
16864     union
16865     {
16866         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
16867 
16868         struct
16869         {
16870             uint32_t                : 4;
16871             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
16872             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
16873             uint32_t                : 1;
16874             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
16875             uint32_t                : 12;
16876             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
16877             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
16878             uint32_t                : 1;
16879             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
16880             uint32_t                : 8;
16881         } DPUSR1R_b;
16882     };
16883 
16884     union
16885     {
16886         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
16887 
16888         struct
16889         {
16890             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
16891             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
16892             uint16_t            : 2;
16893             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
16894                                         *   port.                                                                     */
16895             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
16896                                         *   port.                                                                     */
16897             uint16_t              : 2;
16898             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
16899             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
16900             uint16_t              : 6;
16901         } DPUSR2R_b;
16902     };
16903 
16904     union
16905     {
16906         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
16907 
16908         struct
16909         {
16910             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
16911             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
16912             uint16_t                : 14;
16913         } DPUSRCR_b;
16914     };
16915     __IM uint32_t RESERVED26[165];
16916 
16917     union
16918     {
16919         __IOM uint32_t DPUSR0R_FS;      /*!< (@ 0x00000400) Deep Software Standby USB Transceiver Control/Pin
16920                                          *                  Monitor Register                                           */
16921 
16922         struct
16923         {
16924             __IOM uint32_t SRPC0   : 1; /*!< [0..0] USB Single End Receiver Control                                    */
16925             __IOM uint32_t RPUE0   : 1; /*!< [1..1] DP Pull-Up Resistor Control                                        */
16926             uint32_t               : 1;
16927             __IOM uint32_t DRPD0   : 1; /*!< [3..3] D+/D- Pull-Down Resistor Control                                   */
16928             __IOM uint32_t FIXPHY0 : 1; /*!< [4..4] USB Transceiver Output Fix                                         */
16929             uint32_t               : 11;
16930             __IM uint32_t DP0      : 1; /*!< [16..16] USB0 D+ InputIndicates the D+ input signal of the USB.           */
16931             __IM uint32_t DM0      : 1; /*!< [17..17] USB D-InputIndicates the D- input signal of the USB.             */
16932             uint32_t               : 2;
16933             __IM uint32_t DOVCA0   : 1; /*!< [20..20] USB OVRCURA InputIndicates the OVRCURA input signal
16934                                          *   of the USB.                                                               */
16935             __IM uint32_t DOVCB0 : 1;   /*!< [21..21] USB OVRCURB InputIndicates the OVRCURB input signal
16936                                          *   of the USB.                                                               */
16937             uint32_t              : 1;
16938             __IM uint32_t DVBSTS0 : 1;  /*!< [23..23] USB VBUS InputIndicates the VBUS input signal of the
16939                                          *   USB.                                                                      */
16940             uint32_t : 8;
16941         } DPUSR0R_FS_b;
16942     };
16943 
16944     union
16945     {
16946         __IOM uint32_t DPUSR1R_FS;        /*!< (@ 0x00000404) Deep Software Standby USB Suspend/Resume Interrupt
16947                                            *                  Register                                                   */
16948 
16949         struct
16950         {
16951             __IOM uint32_t DPINTE0   : 1; /*!< [0..0] USB DP Interrupt Enable/Clear                                      */
16952             __IOM uint32_t DMINTE0   : 1; /*!< [1..1] USB DM Interrupt Enable/Clear                                      */
16953             uint32_t                 : 2;
16954             __IOM uint32_t DOVRCRAE0 : 1; /*!< [4..4] USB OVRCURA Interrupt Enable/Clear                                 */
16955             __IOM uint32_t DOVRCRBE0 : 1; /*!< [5..5] USB OVRCURB Interrupt Enable/Clear                                 */
16956             uint32_t                 : 1;
16957             __IOM uint32_t DVBSE0    : 1; /*!< [7..7] USB VBUS Interrupt Enable/Clear                                    */
16958             uint32_t                 : 8;
16959             __IM uint32_t DPINT0     : 1; /*!< [16..16] USB DP Interrupt Source Recovery                                 */
16960             __IM uint32_t DMINT0     : 1; /*!< [17..17] USB DM Interrupt Source Recovery                                 */
16961             uint32_t                 : 2;
16962             __IM uint32_t DOVRCRA0   : 1; /*!< [20..20] USB OVRCURA Interrupt Source Recovery                            */
16963             __IM uint32_t DOVRCRB0   : 1; /*!< [21..21] USB OVRCURB Interrupt Source Recovery                            */
16964             uint32_t                 : 1;
16965             __IM uint32_t DVBINT0    : 1; /*!< [23..23] USB VBUS Interrupt Source Recovery                               */
16966             uint32_t                 : 8;
16967         } DPUSR1R_FS_b;
16968     };
16969 } R_USB_FS0_Type;                         /*!< Size = 1032 (0x408)                                                       */
16970 
16971 /* =========================================================================================================================== */
16972 /* ================                                           R_WDT                                           ================ */
16973 /* =========================================================================================================================== */
16974 
16975 /**
16976  * @brief Watchdog Timer (R_WDT)
16977  */
16978 
16979 typedef struct                         /*!< (@ 0x40083400) R_WDT Structure                                            */
16980 {
16981     union
16982     {
16983         __IOM uint8_t WDTRR;           /*!< (@ 0x00000000) WDT Refresh Register                                       */
16984 
16985         struct
16986         {
16987             __IOM uint8_t WDTRR : 8;   /*!< [7..0] WDTRR is an 8-bit register that refreshes the down-counter
16988                                         *   of the WDT.                                                               */
16989         } WDTRR_b;
16990     };
16991     __IM uint8_t RESERVED;
16992 
16993     union
16994     {
16995         __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
16996 
16997         struct
16998         {
16999             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
17000             uint16_t            : 2;
17001             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
17002             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
17003             uint16_t            : 2;
17004             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
17005             uint16_t            : 2;
17006         } WDTCR_b;
17007     };
17008 
17009     union
17010     {
17011         __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
17012 
17013         struct
17014         {
17015             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
17016             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
17017             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
17018         } WDTSR_b;
17019     };
17020 
17021     union
17022     {
17023         __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
17024 
17025         struct
17026         {
17027             uint8_t               : 7;
17028             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
17029         } WDTRCR_b;
17030     };
17031     __IM uint8_t RESERVED1;
17032 
17033     union
17034     {
17035         __IOM uint8_t WDTCSTPR;        /*!< (@ 0x00000008) WDT Count Stop Control Register                            */
17036 
17037         struct
17038         {
17039             uint8_t              : 7;
17040             __IOM uint8_t SLCSTP : 1;  /*!< [7..7] Sleep-Mode Count Stop Control                                      */
17041         } WDTCSTPR_b;
17042     };
17043     __IM uint8_t  RESERVED2;
17044     __IM uint16_t RESERVED3;
17045 } R_WDT_Type;                          /*!< Size = 12 (0xc)                                                           */
17046 
17047 /* =========================================================================================================================== */
17048 /* ================                                           R_TZF                                           ================ */
17049 /* =========================================================================================================================== */
17050 
17051 /**
17052  * @brief TrustZone Filter (R_TZF)
17053  */
17054 
17055 typedef struct                         /*!< (@ 0x40000E00) R_TZF Structure                                            */
17056 {
17057     union
17058     {
17059         __IOM uint16_t TZFOAD;         /*!< (@ 0x00000000) TrustZone Filter Operation After Detection Register        */
17060 
17061         struct
17062         {
17063             __IOM uint16_t OAD : 1;    /*!< [0..0] Operation after detection                                          */
17064             uint16_t           : 7;
17065             __OM uint16_t KEY  : 8;    /*!< [15..8] KeyCode                                                           */
17066         } TZFOAD_b;
17067     };
17068     __IM uint16_t RESERVED;
17069 
17070     union
17071     {
17072         __IOM uint16_t TZFPT;           /*!< (@ 0x00000004) TrustZone Filter Protect Register                          */
17073 
17074         struct
17075         {
17076             __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register                                             */
17077             uint16_t               : 7;
17078             __OM uint16_t KEY      : 8; /*!< [15..8] KeyCode                                                           */
17079         } TZFPT_b;
17080     };
17081     __IM uint16_t RESERVED1;
17082     __IM uint32_t RESERVED2[94];
17083 
17084     union
17085     {
17086         __IOM uint32_t TZFSAR;         /*!< (@ 0x00000180) TrustZone Filter Security Attribution Register             */
17087 
17088         struct
17089         {
17090             __IOM uint32_t TZFSA0 : 1; /*!< [0..0] Security attributes of registers for TrustZone Filter              */
17091             uint32_t              : 31;
17092         } TZFSAR_b;
17093     };
17094 } R_TZF_Type;                          /*!< Size = 388 (0x184)                                                        */
17095 
17096 /* =========================================================================================================================== */
17097 /* ================                                          R_CACHE                                          ================ */
17098 /* =========================================================================================================================== */
17099 
17100 /**
17101  * @brief R_CACHE (R_CACHE)
17102  */
17103 
17104 typedef struct                         /*!< (@ 0x40007000) R_CACHE Structure                                          */
17105 {
17106     union
17107     {
17108         __IOM uint32_t CCACTL;         /*!< (@ 0x00000000) C-Cache Control Register                                   */
17109 
17110         struct
17111         {
17112             __IOM uint32_t ENC : 1;    /*!< [0..0] C-Cache Enable                                                     */
17113             uint32_t           : 31;
17114         } CCACTL_b;
17115     };
17116 
17117     union
17118     {
17119         __IOM uint32_t CCAFCT;         /*!< (@ 0x00000004) C-Cache Flush Control Register                             */
17120 
17121         struct
17122         {
17123             __IOM uint32_t FC : 1;     /*!< [0..0] C-Cache Flush                                                      */
17124             uint32_t          : 31;
17125         } CCAFCT_b;
17126     };
17127 
17128     union
17129     {
17130         __IOM uint32_t CCALCF;         /*!< (@ 0x00000008) C-Cache Line Configuration Register                        */
17131 
17132         struct
17133         {
17134             __IOM uint32_t CC : 2;     /*!< [1..0] C-Cache Line Size                                                  */
17135             uint32_t          : 30;
17136         } CCALCF_b;
17137     };
17138     __IM uint32_t RESERVED[13];
17139 
17140     union
17141     {
17142         __IOM uint32_t SCACTL;         /*!< (@ 0x00000040) S-Cache Control Register                                   */
17143 
17144         struct
17145         {
17146             __IOM uint32_t ENS : 1;    /*!< [0..0] S-Cache Enable                                                     */
17147             uint32_t           : 31;
17148         } SCACTL_b;
17149     };
17150 
17151     union
17152     {
17153         __IOM uint32_t SCAFCT;         /*!< (@ 0x00000044) S-Cache Flush Control Register                             */
17154 
17155         struct
17156         {
17157             __IOM uint32_t FS : 1;     /*!< [0..0] S-Cache Flush                                                      */
17158             uint32_t          : 31;
17159         } SCAFCT_b;
17160     };
17161 
17162     union
17163     {
17164         __IOM uint32_t SCALCF;         /*!< (@ 0x00000048) S-Cache Line Configuration Register                        */
17165 
17166         struct
17167         {
17168             __IOM uint32_t CS : 2;     /*!< [1..0] S-Cache Line Size                                                  */
17169             uint32_t          : 30;
17170         } SCALCF_b;
17171     };
17172     __IM uint32_t RESERVED1[109];
17173 
17174     union
17175     {
17176         __IOM uint32_t CAPOAD;         /*!< (@ 0x00000200) Cache Parity Error Operation After Detection
17177                                         *                  Register                                                   */
17178 
17179         struct
17180         {
17181             __IOM uint32_t OAD : 1;    /*!< [0..0] Operation after Detection                                          */
17182             uint32_t           : 31;
17183         } CAPOAD_b;
17184     };
17185 
17186     union
17187     {
17188         __IOM uint32_t CAPRCR;         /*!< (@ 0x00000204) Cache Protection Register                                  */
17189 
17190         struct
17191         {
17192             __IOM uint32_t PRCR : 1;   /*!< [0..0] Register Write Control                                             */
17193             __IOM uint32_t KW   : 7;   /*!< [7..1] Write key code                                                     */
17194             uint32_t            : 24;
17195         } CAPRCR_b;
17196     };
17197 } R_CACHE_Type;                        /*!< Size = 520 (0x208)                                                        */
17198 
17199 /* =========================================================================================================================== */
17200 /* ================                                          R_CPSCU                                          ================ */
17201 /* =========================================================================================================================== */
17202 
17203 /**
17204  * @brief CPU System Security Control Unit (R_CPSCU)
17205  */
17206 
17207 typedef struct                           /*!< (@ 0x40008000) R_CPSCU Structure                                          */
17208 {
17209     union
17210     {
17211         __IOM uint32_t CSAR;             /*!< (@ 0x00000000) Cache Security Attribution Register                        */
17212 
17213         struct
17214         {
17215             __IOM uint32_t CACHESA  : 1; /*!< [0..0] Security Attributes of Registers for Cache Control                 */
17216             __IOM uint32_t CACHELSA : 1; /*!< [1..1] Security Attributes of Registers for Cache Line Configuration      */
17217             __IOM uint32_t CACHEESA : 1; /*!< [2..2] Security Attributes of Registers for Cache Error                   */
17218             uint32_t                : 29;
17219         } CSAR_b;
17220     };
17221     __IM uint32_t RESERVED[3];
17222 
17223     union
17224     {
17225         __IOM uint32_t SRAMSAR;         /*!< (@ 0x00000010) SRAM Security Attribution Register                         */
17226 
17227         struct
17228         {
17229             __IOM uint32_t SRAMSA0 : 1; /*!< [0..0] Security attributes of registers for SRAM Protection               */
17230             __IOM uint32_t SRAMSA1 : 1; /*!< [1..1] Security attributes of registers for SRAM Protection
17231                                          *   2                                                                         */
17232             __IOM uint32_t SRAMSA2 : 1; /*!< [2..2] Security attributes of registers for ECC Relation                  */
17233             uint32_t               : 29;
17234         } SRAMSAR_b;
17235     };
17236 
17237     union
17238     {
17239         __IOM uint32_t STBRAMSAR;       /*!< (@ 0x00000014) Standby RAM memory Security Attribution Register           */
17240 
17241         struct
17242         {
17243             __IOM uint32_t NSBSTBR : 4; /*!< [3..0] Security attributes of each region for Standby RAM                 */
17244             uint32_t               : 28;
17245         } STBRAMSAR_b;
17246     };
17247     __IM uint32_t RESERVED1[6];
17248 
17249     union
17250     {
17251         __IOM uint32_t DTCSAR;          /*!< (@ 0x00000030) DTC Controller Security Attribution Register               */
17252 
17253         struct
17254         {
17255             __IOM uint32_t DTCSTSA : 1; /*!< [0..0] DTC Security Attribution                                           */
17256             uint32_t               : 31;
17257         } DTCSAR_b;
17258     };
17259 
17260     union
17261     {
17262         __IOM uint32_t DMACSAR;         /*!< (@ 0x00000034) DMAC Controller Security Attribution Register              */
17263 
17264         struct
17265         {
17266             __IOM uint32_t DMASTSA : 1; /*!< [0..0] DMAST Security Attribution                                         */
17267             uint32_t               : 31;
17268         } DMACSAR_b;
17269     };
17270     __IM uint32_t RESERVED2[2];
17271 
17272     union
17273     {
17274         __IOM uint32_t ICUSARA;           /*!< (@ 0x00000040) ICU Security Attribution Register A                        */
17275 
17276         struct
17277         {
17278             __IOM uint32_t SAIRQCRn : 16; /*!< [15..0] Security Attributes of registers for the IRQCRn registers         */
17279             uint32_t                : 16;
17280         } ICUSARA_b;
17281     };
17282 
17283     union
17284     {
17285         __IOM uint32_t ICUSARB;        /*!< (@ 0x00000044) ICU Security Attribution Register B                        */
17286 
17287         struct
17288         {
17289             __IOM uint32_t SANMI : 1;  /*!< [0..0] Security Attributes of nonmaskable interrupt                       */
17290             uint32_t             : 31;
17291         } ICUSARB_b;
17292     };
17293 
17294     union
17295     {
17296         __IOM uint32_t ICUSARC;         /*!< (@ 0x00000048) ICU Security Attribution Register C                        */
17297 
17298         struct
17299         {
17300             __IOM uint32_t SADMACn : 8; /*!< [7..0] Security Attributes of registers for DMAC channel                  */
17301             uint32_t               : 24;
17302         } ICUSARC_b;
17303     };
17304 
17305     union
17306     {
17307         __IOM uint32_t ICUSARD;          /*!< (@ 0x0000004C) ICU Security Attribution Register D                        */
17308 
17309         struct
17310         {
17311             __IOM uint32_t SASELSR0 : 1; /*!< [0..0] Security Attributes of registers for SELSR0                        */
17312             uint32_t                : 31;
17313         } ICUSARD_b;
17314     };
17315 
17316     union
17317     {
17318         __IOM uint32_t ICUSARE;        /*!< (@ 0x00000050) ICU Security Attribution Register E                        */
17319 
17320         struct
17321         {
17322             uint32_t                   : 16;
17323             __IOM uint32_t SAIWDTWUP   : 1; /*!< [16..16] Security Attributes of registers for WUPEN0.b 16                 */
17324             uint32_t                   : 1;
17325             __IOM uint32_t SALVD1WUP   : 1; /*!< [18..18] Security Attributes of registers for WUPEN0.b 18                 */
17326             __IOM uint32_t SALVD2WUP   : 1; /*!< [19..19] Security Attributes of registers for WUPEN0.b 19                 */
17327             __IOM uint32_t SAVBATTWUP  : 1; /*!< [20..20] Security Attributes of registers for WUPEN0.b 20                 */
17328             uint32_t                   : 3;
17329             __IOM uint32_t SARTCALMWUP : 1; /*!< [24..24] Security Attributes of registers for WUPEN0.b 24                 */
17330             __IOM uint32_t SARTCPRDWUP : 1; /*!< [25..25] Security Attributes of registers for WUPEN0.b 25                 */
17331             uint32_t                   : 1;
17332             __IOM uint32_t SAUSBFS0WUP : 1; /*!< [27..27] Security Attributes of registers for WUPEN0.b 27                 */
17333             __IOM uint32_t SAAGT1UDWUP : 1; /*!< [28..28] Security Attributes of registers for WUPEN0.b 28                 */
17334             __IOM uint32_t SAAGT1CAWUP : 1; /*!< [29..29] Security Attributes of registers for WUPEN0.b 29                 */
17335             __IOM uint32_t SAAGT1CBWUP : 1; /*!< [30..30] Security Attributes of registers for WUPEN0.b 30                 */
17336             __IOM uint32_t SAIIC0WUP   : 1; /*!< [31..31] Security Attributes of registers for WUPEN0.b 31                 */
17337         } ICUSARE_b;
17338     };
17339 
17340     union
17341     {
17342         __IOM uint32_t ICUSARF;              /*!< (@ 0x00000054) ICU Security Attribution Register F                        */
17343 
17344         struct
17345         {
17346             __IOM uint32_t SAAGT3UDWUP  : 1; /*!< [0..0] Security Attributes of registers for WUPEN1.b 0                    */
17347             __IOM uint32_t SAAGT3CAWUP  : 1; /*!< [1..1] Security Attributes of registers for WUPEN1.b 1                    */
17348             __IOM uint32_t SAAGT3CBWUP  : 1; /*!< [2..2] Security Attributes of registers for WUPEN1.b 2                    */
17349             __IOM uint32_t SACOMPHS0WUP : 1; /*!< [3..3] Security attributes of registers for WUPEN1.b 3                    */
17350             uint32_t                    : 4;
17351             __IOM uint32_t SAULP0UWUP   : 1; /*!< [8..8] Security attributes of registers for WUPEN1.b 8                    */
17352             __IOM uint32_t SAULP0AWUP   : 1; /*!< [9..9] Security attributes of registers for WUPEN1.b 9                    */
17353             __IOM uint32_t SAULP0BWUP   : 1; /*!< [10..10] Security Attributes of registers for WUPEN1.b 10                 */
17354             __IOM uint32_t SAI3CWUP     : 1; /*!< [11..11] Security Attributes of registers for WUPEN1.b 11                 */
17355             __IOM uint32_t SAULP1UWUP   : 1; /*!< [12..12] Security Attributes of registers for WUPEN1.b 12                 */
17356             __IOM uint32_t SAULP1AWUP   : 1; /*!< [13..13] Security Attributes of registers for WUPEN1.b 13                 */
17357             __IOM uint32_t SAULP1BWUP   : 1; /*!< [14..14] Security Attributes of registers for WUPEN1.b 14                 */
17358             uint32_t                    : 17;
17359         } ICUSARF_b;
17360     };
17361     __IM uint32_t RESERVED3[6];
17362 
17363     union
17364     {
17365         __IOM uint32_t ICUSARG;           /*!< (@ 0x00000070) ICU Security Attribution Register G                        */
17366 
17367         struct
17368         {
17369             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR31 to IELSR0            */
17370         } ICUSARG_b;
17371     };
17372 
17373     union
17374     {
17375         __IOM uint32_t ICUSARH;           /*!< (@ 0x00000074) ICU Security Attribution Register H                        */
17376 
17377         struct
17378         {
17379             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR63 to IELSR32           */
17380         } ICUSARH_b;
17381     };
17382 
17383     union
17384     {
17385         __IOM uint32_t ICUSARI;           /*!< (@ 0x00000078) ICU Security Attribution Register I                        */
17386 
17387         struct
17388         {
17389             __IOM uint32_t SAIELSRn : 32; /*!< [31..0] Security Attributes of registers for IELSR95 to IELSR64           */
17390         } ICUSARI_b;
17391     };
17392     __IM uint32_t RESERVED4[33];
17393 
17394     union
17395     {
17396         __IOM uint32_t BUSSARA;        /*!< (@ 0x00000100) Bus Security Attribution Register A                        */
17397 
17398         struct
17399         {
17400             __IOM uint32_t BUSSA0 : 1; /*!< [0..0] BUS Security Attribution A0                                        */
17401             uint32_t              : 31;
17402         } BUSSARA_b;
17403     };
17404 
17405     union
17406     {
17407         __IOM uint32_t BUSSARB;        /*!< (@ 0x00000104) Bus Security Attribution Register B                        */
17408 
17409         struct
17410         {
17411             __IOM uint32_t BUSSB0 : 1; /*!< [0..0] BUS Security Attribution B0                                        */
17412             uint32_t              : 31;
17413         } BUSSARB_b;
17414     };
17415     __IM uint32_t RESERVED5[10];
17416 
17417     union
17418     {
17419         __IOM uint32_t MMPUSARA;         /*!< (@ 0x00000130) Master Memory Protection Unit Security Attribution
17420                                           *                  Register A                                                 */
17421 
17422         struct
17423         {
17424             __IOM uint32_t MMPUAnSA : 8; /*!< [7..0] MMPUAn Security Attribution (n = 0 to 7)                           */
17425             uint32_t                : 24;
17426         } MMPUSARA_b;
17427     };
17428 
17429     union
17430     {
17431         __IOM uint32_t MMPUSARB;         /*!< (@ 0x00000134) Master Memory Protection Unit Security Attribution
17432                                           *                  Register B                                                 */
17433 
17434         struct
17435         {
17436             __IOM uint32_t MMPUB0SA : 1; /*!< [0..0] MMPUB0 Security Attribution                                        */
17437             uint32_t                : 31;
17438         } MMPUSARB_b;
17439     };
17440     __IM uint32_t RESERVED6[26];
17441 
17442     union
17443     {
17444         __IOM uint32_t DMACCHSAR;          /*!< (@ 0x000001A0) DMA channel Security Attribution Register                  */
17445 
17446         struct
17447         {
17448             __IOM uint32_t DMACCHSARn : 8; /*!< [7..0] Security attributes of output and registers for DMAC
17449                                             *   channel                                                                   */
17450             uint32_t : 24;
17451         } DMACCHSAR_b;
17452     };
17453     __IM uint32_t RESERVED7[3];
17454 
17455     union
17456     {
17457         __IOM uint32_t CPUDSAR;         /*!< (@ 0x000001B0) CPU Debug Security Attribution Register                    */
17458 
17459         struct
17460         {
17461             __IOM uint32_t CPUDSA0 : 1; /*!< [0..0] CPU Debug Security Attribution 0                                   */
17462             uint32_t               : 31;
17463         } CPUDSAR_b;
17464     };
17465     __IM uint32_t RESERVED8[147];
17466 
17467     union
17468     {
17469         __IOM uint32_t SRAMSABAR0;     /*!< (@ 0x00000400) SRAM Security Attribute Boundary Address Register
17470                                         *                  0                                                          */
17471 
17472         struct
17473         {
17474             uint32_t                 : 13;
17475             __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
17476                                            *   address of non-secure region).                                            */
17477             uint32_t : 11;
17478         } SRAMSABAR0_b;
17479     };
17480 
17481     union
17482     {
17483         __IOM uint32_t SRAMSABAR1;     /*!< (@ 0x00000404) SRAM Security Attribute Boundary Address Register
17484                                         *                  1                                                          */
17485 
17486         struct
17487         {
17488             uint32_t                 : 13;
17489             __IOM uint32_t SRAMSABAR : 8; /*!< [20..13] Boundary address between secure and non-secure (Start
17490                                            *   address of non-secure region).                                            */
17491             uint32_t : 11;
17492         } SRAMSABAR1_b;
17493     };
17494     __IM uint32_t RESERVED9[126];
17495 
17496     union
17497     {
17498         __IOM uint32_t TEVTRCR;        /*!< (@ 0x00000600) Trusted Event Route Control Register                       */
17499 
17500         struct
17501         {
17502             __IOM uint32_t TEVTE : 1;  /*!< [0..0] Trusted Event Route Control Register for IELSRn, DELSRn
17503                                         *   and ELCSRn                                                                */
17504             uint32_t : 31;
17505         } TEVTRCR_b;
17506     };
17507 } R_CPSCU_Type;                        /*!< Size = 1540 (0x604)                                                       */
17508 
17509 /* =========================================================================================================================== */
17510 /* ================                                           R_CEC                                           ================ */
17511 /* =========================================================================================================================== */
17512 
17513 /**
17514  * @brief Consumer Electronics Control (R_CEC)
17515  */
17516 
17517 typedef struct                         /*!< (@ 0x400AC000) R_CEC Structure                                            */
17518 {
17519     union
17520     {
17521         __IOM uint16_t CADR;           /*!< (@ 0x00000000) CEC Local Address Setting Register                         */
17522 
17523         struct
17524         {
17525             __IOM uint16_t ADR00 : 1;  /*!< [0..0] Local Address at Address 0 (TV)                                    */
17526             __IOM uint16_t ADR01 : 1;  /*!< [1..1] Local Address Setting at Address 1 (recording device
17527                                         *   1)                                                                        */
17528             __IOM uint16_t ADR02 : 1;  /*!< [2..2] Local Address Setting at Address 2 (recording device
17529                                         *   2)                                                                        */
17530             __IOM uint16_t ADR03 : 1;  /*!< [3..3] Local Address Setting at Address 3 (tuner 1)                       */
17531             __IOM uint16_t ADR04 : 1;  /*!< [4..4] Local Address Setting at Address 4 (playback device 1)             */
17532             __IOM uint16_t ADR05 : 1;  /*!< [5..5] Local Address Setting at Address 5 (audio system)                  */
17533             __IOM uint16_t ADR06 : 1;  /*!< [6..6] Local Address Setting at Address 6 (tuner 2)                       */
17534             __IOM uint16_t ADR07 : 1;  /*!< [7..7] Local Address Setting at Address 7 (tuner 3)                       */
17535             __IOM uint16_t ADR08 : 1;  /*!< [8..8] Local Address Setting at Address 8 (playback device 2)             */
17536             __IOM uint16_t ADR09 : 1;  /*!< [9..9] Local Address Setting at Address 9 (recording device
17537                                         *   3)                                                                        */
17538             __IOM uint16_t ADR10 : 1;  /*!< [10..10] Local Address Setting at Address 10 (tuner 4)                    */
17539             __IOM uint16_t ADR11 : 1;  /*!< [11..11] Local Address Setting at Address 11 (playback device
17540                                         *   3)                                                                        */
17541             __IOM uint16_t ADR12 : 1;  /*!< [12..12] Local Address Setting at Address 12 (reserved)                   */
17542             __IOM uint16_t ADR13 : 1;  /*!< [13..13] Local Address Setting at Address 13 (reserved)                   */
17543             __IOM uint16_t ADR14 : 1;  /*!< [14..14] Local Address Setting at Address 14 (specific use)               */
17544             uint16_t             : 1;
17545         } CADR_b;
17546     };
17547 
17548     union
17549     {
17550         __IOM uint8_t CECCTL1;         /*!< (@ 0x00000002) CEC Control Register 1                                     */
17551 
17552         struct
17553         {
17554             __IOM uint8_t SFT   : 2;   /*!< [1..0] Signal-Free Time Data Bit Width Select                             */
17555             __IOM uint8_t CESEL : 2;   /*!< [3..2] Communication Complete Interrupt (INTCE) Generation Timing
17556                                         *   Select                                                                    */
17557             __IOM uint8_t STERRD : 1;  /*!< [4..4] Start Bit Error Detection Select                                   */
17558             __IOM uint8_t BLERRD : 1;  /*!< [5..5] Bus Lock Detection Select                                          */
17559             __IOM uint8_t CINTMK : 1;  /*!< [6..6] CEC Data Interrupt (INTDA) Generation Select                       */
17560             __IOM uint8_t CDFC   : 1;  /*!< [7..7] Digital Filter Select                                              */
17561         } CECCTL1_b;
17562     };
17563     __IM uint8_t RESERVED;
17564 
17565     union
17566     {
17567         __IOM uint16_t STATB;          /*!< (@ 0x00000004) CEC Transmission Start Bit Width Setting Register          */
17568 
17569         struct
17570         {
17571             __IOM uint16_t STATB : 9;  /*!< [8..0] CEC Transmission Start Bit Width Setting                           */
17572             uint16_t             : 7;
17573         } STATB_b;
17574     };
17575 
17576     union
17577     {
17578         __IOM uint16_t STATL;          /*!< (@ 0x00000006) CEC Transmission Start Bit Low Width Setting
17579                                         *                  Register                                                   */
17580 
17581         struct
17582         {
17583             __IOM uint16_t STATL : 9;  /*!< [8..0] CEC Transmission Start Bit Low Width Setting                       */
17584             uint16_t             : 7;
17585         } STATL_b;
17586     };
17587 
17588     union
17589     {
17590         __IOM uint16_t LGC0L;          /*!< (@ 0x00000008) CEC Transmission Logical 0 Low Width Setting
17591                                         *                  Register                                                   */
17592 
17593         struct
17594         {
17595             __IOM uint16_t LGC0L : 9;  /*!< [8..0] CEC Transmission Logical 0 Low Width Setting                       */
17596             uint16_t             : 7;
17597         } LGC0L_b;
17598     };
17599 
17600     union
17601     {
17602         __IOM uint16_t LGC1L;          /*!< (@ 0x0000000A) CEC Transmission Logical 1 Low Width Setting
17603                                         *                  Register                                                   */
17604 
17605         struct
17606         {
17607             __IOM uint16_t LGC1L : 9;  /*!< [8..0] CEC Transmission Logical 1 Low Width Setting                       */
17608             uint16_t             : 7;
17609         } LGC1L_b;
17610     };
17611 
17612     union
17613     {
17614         __IOM uint16_t DATB;           /*!< (@ 0x0000000C) CEC Transmission Data Bit Width Setting Register           */
17615 
17616         struct
17617         {
17618             __IOM uint16_t DATB : 9;   /*!< [8..0] CEC Transmission Data Bit Width Setting                            */
17619             uint16_t            : 7;
17620         } DATB_b;
17621     };
17622 
17623     union
17624     {
17625         __IOM uint16_t NOMT;           /*!< (@ 0x0000000E) CEC Reception Data Sampling Time Setting Register          */
17626 
17627         struct
17628         {
17629             __IOM uint16_t NOMT : 9;   /*!< [8..0] CEC Reception Data Sampling Time Setting,                          */
17630             uint16_t            : 7;
17631         } NOMT_b;
17632     };
17633 
17634     union
17635     {
17636         __IOM uint16_t STATLL;         /*!< (@ 0x00000010) CEC Reception Start Bit Minimum Low Width Setting
17637                                         *                  Register                                                   */
17638 
17639         struct
17640         {
17641             __IOM uint16_t STATLL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Low Width Setting                  */
17642             uint16_t              : 7;
17643         } STATLL_b;
17644     };
17645 
17646     union
17647     {
17648         __IOM uint16_t STATLH;         /*!< (@ 0x00000012) CEC Reception Start Bit Maximum Low Width Setting
17649                                         *                  Register                                                   */
17650 
17651         struct
17652         {
17653             __IOM uint16_t STATLH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting                  */
17654             uint16_t              : 7;
17655         } STATLH_b;
17656     };
17657 
17658     union
17659     {
17660         __IOM uint16_t STATBL;         /*!< (@ 0x00000014) CEC Reception Start Bit Minimum Bit Width Setting
17661                                         *                  Register                                                   */
17662 
17663         struct
17664         {
17665             __IOM uint16_t STATBL : 9; /*!< [8..0] CEC Reception Start Bit Minimum Bit Width Setting                  */
17666             uint16_t              : 7;
17667         } STATBL_b;
17668     };
17669 
17670     union
17671     {
17672         __IOM uint16_t STATBH;         /*!< (@ 0x00000016) CEC Reception Start Bit Maximum Bit Width Setting
17673                                         *                  Register                                                   */
17674 
17675         struct
17676         {
17677             __IOM uint16_t STATBH : 9; /*!< [8..0] CEC Reception Start Bit Maximum Bit Width Setting                  */
17678             uint16_t              : 7;
17679         } STATBH_b;
17680     };
17681 
17682     union
17683     {
17684         __IOM uint16_t LGC0LL;         /*!< (@ 0x00000018) CEC Reception Logical 0 Minimum Low Width Setting
17685                                         *                  Register                                                   */
17686 
17687         struct
17688         {
17689             __IOM uint16_t LGC0LL : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting                  */
17690             uint16_t              : 7;
17691         } LGC0LL_b;
17692     };
17693 
17694     union
17695     {
17696         __IOM uint16_t LGC0LH;         /*!< (@ 0x0000001A) CEC Reception Logical 0 Maximum Low Width Setting
17697                                         *                  Register                                                   */
17698 
17699         struct
17700         {
17701             __IOM uint16_t LGC0LH : 9; /*!< [8..0] CEC Reception Logical 0 Minimum Low Width Setting                  */
17702             uint16_t              : 7;
17703         } LGC0LH_b;
17704     };
17705 
17706     union
17707     {
17708         __IOM uint16_t LGC1LL;         /*!< (@ 0x0000001C) CEC Reception Logical 1 Minimum Low Width Setting
17709                                         *                  Register                                                   */
17710 
17711         struct
17712         {
17713             __IOM uint16_t LGC1LL : 9; /*!< [8..0] CEC Reception Logical 1 Minimum Low Width Setting                  */
17714             uint16_t              : 7;
17715         } LGC1LL_b;
17716     };
17717 
17718     union
17719     {
17720         __IOM uint16_t LGC1LH;         /*!< (@ 0x0000001E) CEC Reception Logical 1 Maximum Low Width Setting
17721                                         *                  Register                                                   */
17722 
17723         struct
17724         {
17725             __IOM uint16_t LGC1LH : 9; /*!< [8..0] CEC Reception Logical 1 Maximum Low Width Setting                  */
17726             uint16_t              : 7;
17727         } LGC1LH_b;
17728     };
17729 
17730     union
17731     {
17732         __IOM uint16_t DATBL;          /*!< (@ 0x00000020) CEC Reception Data Bit Minimum Bit Width Setting
17733                                         *                  Register                                                   */
17734 
17735         struct
17736         {
17737             __IOM uint16_t DATBL : 9;  /*!< [8..0] CEC Reception Data Bit Minimum Bit Width Setting                   */
17738             uint16_t             : 7;
17739         } DATBL_b;
17740     };
17741 
17742     union
17743     {
17744         __IOM uint16_t DATBH;          /*!< (@ 0x00000022) CEC Reception Data Bit Maximum Bit Width Setting
17745                                         *                  Register                                                   */
17746 
17747         struct
17748         {
17749             __IOM uint16_t DATBH : 9;  /*!< [8..0] CEC Reception Data Bit Maximum Bit Width Setting                   */
17750             uint16_t             : 7;
17751         } DATBH_b;
17752     };
17753 
17754     union
17755     {
17756         __IOM uint16_t NOMP;           /*!< (@ 0x00000024) CEC Data Bit Reference Width Setting Register              */
17757 
17758         struct
17759         {
17760             __IOM uint16_t NOMP : 9;   /*!< [8..0] CEC Data Bit Reference Width Setting                               */
17761             uint16_t            : 7;
17762         } NOMP_b;
17763     };
17764     __IM uint16_t RESERVED1;
17765 
17766     union
17767     {
17768         __IOM uint8_t CECEXMD;         /*!< (@ 0x00000028) CEC Extension Mode Register                                */
17769 
17770         struct
17771         {
17772             uint8_t                  : 4;
17773             __IOM uint8_t LERPLEN    : 1; /*!< [4..4] Pulse Output Function Enable by Long Bit Width Error               */
17774             __IOM uint8_t RERCVEN    : 1; /*!< [5..5] Start Detection Reception Restart Enable                           */
17775             uint8_t                  : 1;
17776             __IOM uint8_t RCVINTDSEL : 1; /*!< [7..7] INTDA Reception Interrupt Timing Change                            */
17777         } CECEXMD_b;
17778     };
17779     __IM uint8_t RESERVED2;
17780 
17781     union
17782     {
17783         __IOM uint8_t CECEXMON;        /*!< (@ 0x0000002A) CEC Extension Monitor Register                             */
17784 
17785         struct
17786         {
17787             __IM uint8_t CECLNMON : 1; /*!< [0..0] CEC Line Monitor                                                   */
17788             __IM uint8_t ACKF     : 1; /*!< [1..1] ACK Flag                                                           */
17789             uint8_t               : 6;
17790         } CECEXMON_b;
17791     };
17792     __IM uint8_t  RESERVED3;
17793     __IM uint16_t RESERVED4[10];
17794     __IOM uint8_t CTXD;                /*!< (@ 0x00000040) CEC Transmission Buffer Register                           */
17795     __IOM uint8_t CRXD;                /*!< (@ 0x00000041) CEC Reception Buffer Register                              */
17796 
17797     union
17798     {
17799         __IOM uint8_t CECES;           /*!< (@ 0x00000042) CEC Communication Error Status Register                    */
17800 
17801         struct
17802         {
17803             __IM uint8_t OERR   : 1;   /*!< [0..0] Overrun Error Detection Flag                                       */
17804             __IM uint8_t UERR   : 1;   /*!< [1..1] Underrun Error Detection Flag                                      */
17805             __IM uint8_t ACKERR : 1;   /*!< [2..2] ACK Error Detection Flag                                           */
17806             __IM uint8_t TERR   : 1;   /*!< [3..3] Timing Error Detection Flag                                        */
17807             __IM uint8_t TXERR  : 1;   /*!< [4..4] Transmission Error Detection Flag                                  */
17808             __IM uint8_t AERR   : 1;   /*!< [5..5] Arbitration Loss Detection Flag                                    */
17809             __IM uint8_t BLERR  : 1;   /*!< [6..6] Bus Lock Error Detection Flag                                      */
17810             uint8_t             : 1;
17811         } CECES_b;
17812     };
17813 
17814     union
17815     {
17816         __IOM uint8_t CECS;            /*!< (@ 0x00000043) CEC Communication Status Register                          */
17817 
17818         struct
17819         {
17820             __IM uint8_t ADRF  : 1;    /*!< [0..0] Address Match Detection Flag                                       */
17821             __IM uint8_t BUSST : 1;    /*!< [1..1] Bus Busy Detection Flag                                            */
17822             __IM uint8_t TXST  : 1;    /*!< [2..2] Transmission Status Flag                                           */
17823             __IM uint8_t EOMF  : 1;    /*!< [3..3] EOM Flag                                                           */
17824             __IM uint8_t ITCEF : 1;    /*!< [4..4] INTCE Generation Source Flag                                       */
17825             uint8_t            : 2;
17826             __IM uint8_t SFTST : 1;    /*!< [7..7] Signal-Free Time Rewrite Disable Report Flag                       */
17827         } CECS_b;
17828     };
17829 
17830     union
17831     {
17832         __IOM uint8_t CECFC;           /*!< (@ 0x00000044) CEC Communication Error Flag Clear Trigger Register        */
17833 
17834         struct
17835         {
17836             __OM uint8_t OCTRG   : 1;  /*!< [0..0] Overrun Error Detection Flag Clear Trigger                         */
17837             __OM uint8_t UCTRG   : 1;  /*!< [1..1] Underrun Error Detection Flag Clear Trigger                        */
17838             __OM uint8_t ACKCTRG : 1;  /*!< [2..2] ACK Error Detection Flag Clear Trigger                             */
17839             __OM uint8_t TCTRG   : 1;  /*!< [3..3] Timing Error Detection Flag Clear Trigger                          */
17840             __OM uint8_t TXCTRG  : 1;  /*!< [4..4] Transmission Error Detection Flag Clear Trigger                    */
17841             __OM uint8_t ACTRG   : 1;  /*!< [5..5] Arbitration Loss Detection Flag Clear Trigger                      */
17842             __OM uint8_t BLCTRG  : 1;  /*!< [6..6] Bus Lock Error Detection Flag Clear Trigger                        */
17843             uint8_t              : 1;
17844         } CECFC_b;
17845     };
17846 
17847     union
17848     {
17849         __IOM uint8_t CECCTL0;         /*!< (@ 0x00000045) CEC Control Register 0                                     */
17850 
17851         struct
17852         {
17853             __IOM uint8_t EOM     : 1; /*!< [0..0] EOM Setting                                                        */
17854             __IOM uint8_t CECRXEN : 1; /*!< [1..1] Reception Enable Control                                           */
17855             __OM uint8_t  TXTRG   : 1; /*!< [2..2] Transmission Start Trigger                                         */
17856             __IOM uint8_t CCL     : 3; /*!< [5..3] CEC Clock (CECCLK) Select                                          */
17857             __IOM uint8_t ACKTEN  : 1; /*!< [6..6] ACK Bit Timing Error (Bit Width) Check Enable                      */
17858             __IOM uint8_t CECE    : 1; /*!< [7..7] CEC Operation Enable Flag                                          */
17859         } CECCTL0_b;
17860     };
17861 } R_CEC_Type;                          /*!< Size = 70 (0x46)                                                          */
17862 
17863 /* =========================================================================================================================== */
17864 /* ================                                          R_OSPI                                           ================ */
17865 /* =========================================================================================================================== */
17866 
17867 /**
17868  * @brief Octa Serial Peripheral Interface (R_OSPI)
17869  */
17870 
17871 typedef struct                         /*!< (@ 0x400A6000) R_OSPI Structure                                           */
17872 {
17873     union
17874     {
17875         __IOM uint32_t DCR;            /*!< (@ 0x00000000) Device Command Register                                    */
17876 
17877         struct
17878         {
17879             __IOM uint32_t DVCMD0 : 8; /*!< [7..0] Device Command data                                                */
17880             __IOM uint32_t DVCMD1 : 8; /*!< [15..8] Device Command data                                               */
17881             uint32_t              : 16;
17882         } DCR_b;
17883     };
17884 
17885     union
17886     {
17887         __IOM uint32_t DAR;            /*!< (@ 0x00000004) Device Address Register                                    */
17888 
17889         struct
17890         {
17891             __IOM uint32_t DVAD0 : 8;  /*!< [7..0] Device Address data 0                                              */
17892             __IOM uint32_t DVAD1 : 8;  /*!< [15..8] Device Address data 1                                             */
17893             __IOM uint32_t DVAD2 : 8;  /*!< [23..16] Device Address data 2                                            */
17894             __IOM uint32_t DVAD3 : 8;  /*!< [31..24] Device Address data 3                                            */
17895         } DAR_b;
17896     };
17897 
17898     union
17899     {
17900         __IOM uint32_t DCSR;           /*!< (@ 0x00000008) Device Command Setting Register                            */
17901 
17902         struct
17903         {
17904             __IOM uint32_t DALEN  : 8; /*!< [7..0] Transfer data length setting                                       */
17905             __IOM uint32_t DMLEN  : 8; /*!< [15..8] Dummy cycle setting                                               */
17906             uint32_t              : 3;
17907             __IOM uint32_t ACDV   : 1; /*!< [19..19] Access Device setting                                            */
17908             __IOM uint32_t CMDLEN : 3; /*!< [22..20] Transfer command length setting                                  */
17909             __IOM uint32_t DAOR   : 1; /*!< [23..23] Data order setting                                               */
17910             __IOM uint32_t ADLEN  : 3; /*!< [26..24] Transfer address length setting                                  */
17911             __IOM uint32_t DOPI   : 1; /*!< [27..27] DOPI single byte setting                                         */
17912             __IOM uint32_t ACDA   : 1; /*!< [28..28] Data Access Control                                              */
17913             __IOM uint32_t PREN   : 1; /*!< [29..29] Preamble bit enable for OctaRAM                                  */
17914             uint32_t              : 2;
17915         } DCSR_b;
17916     };
17917 
17918     union
17919     {
17920         __IOM uint32_t DSR[2];         /*!< (@ 0x0000000C) Device Size Register 0                                     */
17921 
17922         struct
17923         {
17924             __IOM uint32_t DVSZ  : 30; /*!< [29..0] Device size setting                                               */
17925             __IOM uint32_t DVTYP : 2;  /*!< [31..30] Device type setting                                              */
17926         } DSR_b[2];
17927     };
17928 
17929     union
17930     {
17931         __IOM uint32_t MDTR;             /*!< (@ 0x00000014) Memory Delay Trim Register                                 */
17932 
17933         struct
17934         {
17935             __IOM uint32_t DV0DEL   : 8; /*!< [7..0] Device 0 delay setting                                             */
17936             __IOM uint32_t DQSERAM  : 4; /*!< [11..8] OM_DQS enable counter                                             */
17937             __IOM uint32_t DQSESOPI : 4; /*!< [15..12] OM_DQS enable counter                                            */
17938             __IOM uint32_t DV1DEL   : 8; /*!< [23..16] Device 1 delay setting                                           */
17939             __IOM uint32_t DQSEDOPI : 4; /*!< [27..24] OM_DQS enable counter                                            */
17940             uint32_t                : 4;
17941         } MDTR_b;
17942     };
17943 
17944     union
17945     {
17946         __IOM uint32_t ACTR;           /*!< (@ 0x00000018) Auto-Calibration Timer Register                            */
17947 
17948         struct
17949         {
17950             __IOM uint32_t CTP : 32;   /*!< [31..0] Automatic calibration cycle time setting                          */
17951         } ACTR_b;
17952     };
17953 
17954     union
17955     {
17956         __IOM uint32_t ACAR[2];        /*!< (@ 0x0000001C) Auto-Calibration Address Register                          */
17957 
17958         struct
17959         {
17960             __IOM uint32_t CAD : 32;   /*!< [31..0] Automatic calibration address                                     */
17961         } ACAR_b[2];
17962     };
17963     __IM uint32_t RESERVED[4];
17964 
17965     union
17966     {
17967         __IOM uint32_t DRCSTR;           /*!< (@ 0x00000034) Device Memory Map Read Chip Select Timing Setting
17968                                           *                  Register                                                   */
17969 
17970         struct
17971         {
17972             __IOM uint32_t CTRW0 : 7;    /*!< [6..0] Device 0 single continuous read waiting cycle setting
17973                                           *   in PCLKH units                                                            */
17974             __IOM uint32_t CTR0     : 1; /*!< [7..7] Device 0 single continuous read mode setting                       */
17975             __IOM uint32_t DVRDCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting                       */
17976             __IOM uint32_t DVRDHI0  : 3; /*!< [13..11] Device 0 select signal pull-up timing setting                    */
17977             __IOM uint32_t DVRDLO0  : 2; /*!< [15..14] Device 0 select signal pull-down timing setting                  */
17978             __IOM uint32_t CTRW1    : 7; /*!< [22..16] Device 1 single continuous read waiting cycle setting
17979                                           *   in PCLKH units                                                            */
17980             __IOM uint32_t CTR1     : 1; /*!< [23..23] Device 1 single continuous read mode setting                     */
17981             __IOM uint32_t DVRDCMD1 : 3; /*!< [26..24] Device 1 Command execution interval                              */
17982             __IOM uint32_t DVRDHI1  : 3; /*!< [29..27] Device 1 select signal High timing setting                       */
17983             __IOM uint32_t DVRDLO1  : 2; /*!< [31..30] Device 1 select signal pull-down timing setting                  */
17984         } DRCSTR_b;
17985     };
17986 
17987     union
17988     {
17989         __IOM uint32_t DWCSTR;          /*!< (@ 0x00000038) Device Memory Map Write Chip Select Timing Setting
17990                                          *                  Register                                                   */
17991 
17992         struct
17993         {
17994             __IOM uint32_t CTWW0 : 7;   /*!< [6..0] Device 0 single continuous write waiting cycle setting
17995                                          *   in PCLKH units                                                            */
17996             __IOM uint32_t CTW0    : 1; /*!< [7..7] Device 0 single continuous write mode setting                      */
17997             __IOM uint32_t DVWCMD0 : 3; /*!< [10..8] Device 0 Command execution interval setting                       */
17998             __IOM uint32_t DVWHI0  : 3; /*!< [13..11] Device 0 select signal pull-up timing setting                    */
17999             __IOM uint32_t DVWLO0  : 2; /*!< [15..14] Device 0 select signal pull-down timing setting                  */
18000             __IOM uint32_t CTWW1   : 7; /*!< [22..16] Device 1 single continuous write waiting cycle setting
18001                                          *   in PCLKH units                                                            */
18002             __IOM uint32_t CTW1    : 1; /*!< [23..23] Device 1 single continuous write mode setting                    */
18003             __IOM uint32_t DVWCMD1 : 3; /*!< [26..24] Device 1 Command execution interval setting                      */
18004             __IOM uint32_t DVWHI1  : 3; /*!< [29..27] Device 1 select signal pull-up timing setting                    */
18005             __IOM uint32_t DVWLO1  : 2; /*!< [31..30] Device 1 select signal pull-down timing setting                  */
18006         } DWCSTR_b;
18007     };
18008 
18009     union
18010     {
18011         __IOM uint32_t DCSTR;          /*!< (@ 0x0000003C) Device Chip Select Timing Setting Register                 */
18012 
18013         struct
18014         {
18015             uint32_t                : 8;
18016             __IOM uint32_t DVSELCMD : 3; /*!< [10..8] Device Command execution interval setting                         */
18017             __IOM uint32_t DVSELHI  : 3; /*!< [13..11] Device select signal pull-up timing setting                      */
18018             __IOM uint32_t DVSELLO  : 2; /*!< [15..14] Device select signal pull-down timing setting                    */
18019             uint32_t                : 16;
18020         } DCSTR_b;
18021     };
18022 
18023     union
18024     {
18025         __IOM uint32_t CDSR;            /*!< (@ 0x00000040) Controller and Device Setting Register                     */
18026 
18027         struct
18028         {
18029             __IOM uint32_t DV0TTYP : 2; /*!< [1..0] Device0_transfer_type setting                                      */
18030             __IOM uint32_t DV1TTYP : 2; /*!< [3..2] Device1_transfer_type setting                                      */
18031             __IOM uint32_t DV0PC   : 1; /*!< [4..4] Device0_memory precycle setting                                    */
18032             __IOM uint32_t DV1PC   : 1; /*!< [5..5] Device1_memory precycle setting                                    */
18033             uint32_t               : 4;
18034             __IOM uint32_t ACMEME0 : 1; /*!< [10..10] Automatic calibration memory enable setting for device
18035                                          *   0                                                                         */
18036             __IOM uint32_t ACMEME1 : 1; /*!< [11..11] Automatic calibration memory enable setting for device
18037                                          *   1                                                                         */
18038             __IOM uint32_t ACMODE : 2;  /*!< [13..12] Automatic calibration mode                                       */
18039             uint32_t              : 17;
18040             __IOM uint32_t DLFT   : 1;  /*!< [31..31] Deadlock Free Timer Enable                                       */
18041         } CDSR_b;
18042     };
18043 
18044     union
18045     {
18046         __IOM uint32_t MDLR;           /*!< (@ 0x00000044) Memory Map Dummy Length Register                           */
18047 
18048         struct
18049         {
18050             __IOM uint32_t DV0RDL : 8; /*!< [7..0] Device 0 Read dummy length setting                                 */
18051             __IOM uint32_t DV0WDL : 8; /*!< [15..8] Device 0 Write dummy length setting                               */
18052             __IOM uint32_t DV1RDL : 8; /*!< [23..16] Device 1 Read dummy length setting                               */
18053             __IOM uint32_t DV1WDL : 8; /*!< [31..24] Device 1 Write dummy length setting                              */
18054         } MDLR_b;
18055     };
18056 
18057     union
18058     {
18059         __IOM uint32_t MRWCR[2];        /*!< (@ 0x00000048) Memory Map Read/Write Command Register                     */
18060 
18061         struct
18062         {
18063             __IOM uint32_t DMRCMD0 : 8; /*!< [7..0] Memory map read command 0 setting                                  */
18064             __IOM uint32_t DMRCMD1 : 8; /*!< [15..8] Memory map read command 1 setting                                 */
18065             __IOM uint32_t DMWCMD0 : 8; /*!< [23..16] Memory map write command 0 setting                               */
18066             __IOM uint32_t DMWCMD1 : 8; /*!< [31..24] Memory map write command 1 setting                               */
18067         } MRWCR_b[2];
18068     };
18069 
18070     union
18071     {
18072         __IOM uint32_t MRWCSR;         /*!< (@ 0x00000050) Memory Map Read/Write Setting Register                     */
18073 
18074         struct
18075         {
18076             __IOM uint32_t MRAL0 : 3;  /*!< [2..0] Device 0 read address length setting                               */
18077             __IOM uint32_t MRCL0 : 3;  /*!< [5..3] Device 0 read command length setting                               */
18078             __IOM uint32_t MRO0  : 1;  /*!< [6..6] Device 0 read order setting                                        */
18079             __IOM uint32_t PREN0 : 1;  /*!< [7..7] Preamble bit enable for mem0 memory-map read                       */
18080             __IOM uint32_t MWAL0 : 3;  /*!< [10..8] Device 0 write address length setting                             */
18081             __IOM uint32_t MWCL0 : 3;  /*!< [13..11] Device 0 write command length setting                            */
18082             __IOM uint32_t MWO0  : 1;  /*!< [14..14] Device 0 write order setting                                     */
18083             uint32_t             : 1;
18084             __IOM uint32_t MRAL1 : 3;  /*!< [18..16] Device 1 read address length setting                             */
18085             __IOM uint32_t MRCL1 : 3;  /*!< [21..19] Device 1 read command length setting                             */
18086             __IOM uint32_t MRO1  : 1;  /*!< [22..22] Device 1 read order setting                                      */
18087             __IOM uint32_t PREN1 : 1;  /*!< [23..23] Preamble bit enable for mem1 memory-map read                     */
18088             __IOM uint32_t MWAL1 : 3;  /*!< [26..24] Device 1 write address length setting                            */
18089             __IOM uint32_t MWCL1 : 3;  /*!< [29..27] Device 1 write command length setting                            */
18090             __IOM uint32_t MWO1  : 1;  /*!< [30..30] Device 1 write order setting                                     */
18091             uint32_t             : 1;
18092         } MRWCSR_b;
18093     };
18094 
18095     union
18096     {
18097         __IM uint32_t ESR;             /*!< (@ 0x00000054) Error Status Register                                      */
18098 
18099         struct
18100         {
18101             __IM uint32_t MRESR : 8;   /*!< [7..0] Memory map read error status                                       */
18102             __IM uint32_t MWESR : 8;   /*!< [15..8] Memory map write error status                                     */
18103             uint32_t            : 16;
18104         } ESR_b;
18105     };
18106 
18107     union
18108     {
18109         __OM uint32_t CWNDR;           /*!< (@ 0x00000058) Configure Write without Data Register                      */
18110 
18111         struct
18112         {
18113             __OM uint32_t WND : 32;    /*!< [31..0] The write value should be 0.                                      */
18114         } CWNDR_b;
18115     };
18116 
18117     union
18118     {
18119         __OM uint32_t CWDR;            /*!< (@ 0x0000005C) Configure Write Data Register                              */
18120 
18121         struct
18122         {
18123             __OM uint32_t WD0 : 8;     /*!< [7..0] Write data 0                                                       */
18124             __OM uint32_t WD1 : 8;     /*!< [15..8] Write data 1                                                      */
18125             __OM uint32_t WD2 : 8;     /*!< [23..16] Write data 2                                                     */
18126             __OM uint32_t WD3 : 8;     /*!< [31..24] Write data 3                                                     */
18127         } CWDR_b;
18128     };
18129 
18130     union
18131     {
18132         __IM uint32_t CRR;             /*!< (@ 0x00000060) Configure Read Register                                    */
18133 
18134         struct
18135         {
18136             __IM uint32_t RD0 : 8;     /*!< [7..0] Read data 0                                                        */
18137             __IM uint32_t RD1 : 8;     /*!< [15..8] Read data 1                                                       */
18138             __IM uint32_t RD2 : 8;     /*!< [23..16] Read data 2                                                      */
18139             __IM uint32_t RD3 : 8;     /*!< [31..24] Read data 3                                                      */
18140         } CRR_b;
18141     };
18142 
18143     union
18144     {
18145         __IOM uint32_t ACSR;           /*!< (@ 0x00000064) Auto-Calibration Status Register                           */
18146 
18147         struct
18148         {
18149             __IOM uint32_t ACSR0 : 3;  /*!< [2..0] Auto-calibration status of device 0                                */
18150             __IOM uint32_t ACSR1 : 3;  /*!< [5..3] Auto-calibration status of device 1                                */
18151             uint32_t             : 26;
18152         } ACSR_b;
18153     };
18154     __IM uint32_t RESERVED1[5];
18155 
18156     union
18157     {
18158         __IOM uint32_t DCSMXR;         /*!< (@ 0x0000007C) Device Chip Select Maximum Period Register                 */
18159 
18160         struct
18161         {
18162             __IOM uint32_t CTWMX0 : 9; /*!< [8..0] Indicates the maximum period that OM_CS0 and OM_CS1 are
18163                                         *   Low in single continuous write of OctaRAM.                                */
18164             uint32_t              : 7;
18165             __IOM uint32_t CTWMX1 : 9; /*!< [24..16] Indicates the maximum period that OM_CS0 and OM_CS1
18166                                         *   are Low in single continuous read of OctaRAM.                             */
18167             uint32_t : 7;
18168         } DCSMXR_b;
18169     };
18170 
18171     union
18172     {
18173         __IOM uint32_t DWSCTSR;        /*!< (@ 0x00000080) Device Memory Map Write single continuous translating
18174                                         *                  size Register                                              */
18175 
18176         struct
18177         {
18178             __IOM uint32_t CTSN0 : 11; /*!< [10..0] Indicates the number of bytes to translate in single
18179                                         *   continuous write of device 0.                                             */
18180             uint32_t             : 5;
18181             __IOM uint32_t CTSN1 : 11; /*!< [26..16] Indicates the number of bytes to translate in single
18182                                         *   continuous write of device 1.                                             */
18183             uint32_t : 5;
18184         } DWSCTSR_b;
18185     };
18186 } R_OSPI_Type;                         /*!< Size = 132 (0x84)                                                         */
18187 
18188 /* =========================================================================================================================== */
18189 /* ================                                         R_USB_HS0                                         ================ */
18190 /* =========================================================================================================================== */
18191 
18192 /**
18193  * @brief USB 2.0 High-Speed Module (R_USB_HS0)
18194  */
18195 
18196 typedef struct                         /*!< (@ 0x40111000) R_USB_HS0 Structure                                        */
18197 {
18198     union
18199     {
18200         __IOM uint16_t SYSCFG;         /*!< (@ 0x00000000) System Configuration Control Register                      */
18201 
18202         struct
18203         {
18204             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Operation Enable                                               */
18205             uint16_t             : 3;
18206             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
18207             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                        */
18208             __IOM uint16_t DCFM  : 1;  /*!< [6..6] Controller Function Select                                         */
18209             __IOM uint16_t HSE   : 1;  /*!< [7..7] High-Speed Operation Enable                                        */
18210             __IOM uint16_t CNEN  : 1;  /*!< [8..8] Single End Receiver Enable                                         */
18211             uint16_t             : 7;
18212         } SYSCFG_b;
18213     };
18214 
18215     union
18216     {
18217         __IOM uint16_t BUSWAIT;        /*!< (@ 0x00000002) CPU Bus Wait Register                                      */
18218 
18219         struct
18220         {
18221             __IOM uint16_t BWAIT : 4;  /*!< [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2
18222                                         *   access cycles)                                                            */
18223             uint16_t : 12;
18224         } BUSWAIT_b;
18225     };
18226 
18227     union
18228     {
18229         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register                       */
18230 
18231         struct
18232         {
18233             __IM uint16_t LNST  : 2;   /*!< [1..0] USB Data Line Status Monitor                                       */
18234             __IM uint16_t IDMON : 1;   /*!< [2..2] ID0 Pin Monitor                                                    */
18235             uint16_t            : 2;
18236             __IM uint16_t SOFEA : 1;   /*!< [5..5] SOF Active Monitor While Host Controller Function is
18237                                         *   Selected.                                                                 */
18238             __IM uint16_t HTACT  : 1;  /*!< [6..6] Host Sequencer Status Monitor                                      */
18239             uint16_t             : 7;
18240             __IM uint16_t OVCMON : 2;  /*!< [15..14] External USB1_OVRCURA/USB1_OVRCURB Input Pin MonitorThe
18241                                         *   OCVMON[1] bit indicates the status of the USBHS_OVRCURA
18242                                         *   pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB
18243                                         *   pin.                                                                      */
18244         } SYSSTS0_b;
18245     };
18246 
18247     union
18248     {
18249         __IM uint16_t PLLSTA;          /*!< (@ 0x00000006) PLL Status Register                                        */
18250 
18251         struct
18252         {
18253             __IM uint16_t PLLLOCK : 1; /*!< [0..0] PLL Lock Flag                                                      */
18254             uint16_t              : 15;
18255         } PLLSTA_b;
18256     };
18257 
18258     union
18259     {
18260         __IOM uint16_t DVSTCTR0;        /*!< (@ 0x00000008) Device State Control Register 0                            */
18261 
18262         struct
18263         {
18264             __IM uint16_t RHST    : 3;  /*!< [2..0] USB Bus Reset Status                                               */
18265             uint16_t              : 1;
18266             __IOM uint16_t UACT   : 1;  /*!< [4..4] USB Bus Operation Enable for the Host Controller Operation         */
18267             __IOM uint16_t RESUME : 1;  /*!< [5..5] Resume Signal Output for the Host Controller Operation             */
18268             __IOM uint16_t USBRST : 1;  /*!< [6..6] USB Bus Reset Output for the Host Controller Operation             */
18269             __IOM uint16_t RWUPE  : 1;  /*!< [7..7] Remote Wakeup Detection Enable for the Host Controller
18270                                          *   Operation                                                                 */
18271             __IOM uint16_t WKUP    : 1; /*!< [8..8] Remote Wakeup Output for the Device Controller Operation           */
18272             __IOM uint16_t VBUSEN  : 1; /*!< [9..9] USBHS_VBUSEN Output Pin Control                                    */
18273             __IOM uint16_t EXICEN  : 1; /*!< [10..10] USBHS_EXICEN Output Pin Control                                  */
18274             __IOM uint16_t HNPBTOA : 1; /*!< [11..11] Host Negotiation Protocol (HNP) Control Use this bit
18275                                          *   when switching from device B to device A in OTGmode. If
18276                                          *   the HNPBTOA bit is 1, the internal function controlremains
18277                                          *   in the Suspend state until the HNP processing endseven
18278                                          *   if SYSCFG.DPRPU = 0 or SYSCFG.DCFM = 1 is set.                            */
18279             uint16_t : 4;
18280         } DVSTCTR0_b;
18281     };
18282     __IM uint16_t RESERVED;
18283 
18284     union
18285     {
18286         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
18287 
18288         struct
18289         {
18290             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
18291             uint16_t            : 12;
18292         } TESTMODE_b;
18293     };
18294     __IM uint16_t RESERVED1;
18295     __IM uint32_t RESERVED2;
18296 
18297     union
18298     {
18299         union
18300         {
18301             __IOM uint32_t CFIFO;             /*!< (@ 0x00000014) CFIFO Port Register                                        */
18302 
18303             struct
18304             {
18305                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port.Read receive data from the FIFO buffer or
18306                                                *   write transmit data to the FIFO buffer by accessing these
18307                                                *   bits.                                                                     */
18308             } CFIFO_b;
18309         };
18310 
18311         struct
18312         {
18313             union
18314             {
18315                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) CFIFO Port Register L                                      */
18316                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) CFIFO Port Register LL                                     */
18317             };
18318 
18319             union
18320             {
18321                 __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) CFIFO Port Register H                                      */
18322 
18323                 struct
18324                 {
18325                     __IM uint8_t  RESERVED3;
18326                     __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) CFIFO Port Register HH                                     */
18327                 };
18328             };
18329         };
18330     };
18331 
18332     union
18333     {
18334         union
18335         {
18336             __IOM uint32_t D0FIFO;            /*!< (@ 0x00000018) D0FIFO Port Register                                       */
18337 
18338             struct
18339             {
18340                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port Read receive data from the FIFO buffer or
18341                                                *   write transmit data to the FIFO buffer by accessing these
18342                                                *   bits.                                                                     */
18343             } D0FIFO_b;
18344         };
18345 
18346         struct
18347         {
18348             union
18349             {
18350                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) D0FIFO Port Register L                                     */
18351                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) D0FIFO Port Register LL                                    */
18352             };
18353 
18354             union
18355             {
18356                 __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) D0FIFO Port Register H                                     */
18357 
18358                 struct
18359                 {
18360                     __IM uint8_t  RESERVED4;
18361                     __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) D0FIFO Port Register HH                                    */
18362                 };
18363             };
18364         };
18365     };
18366 
18367     union
18368     {
18369         union
18370         {
18371             __IOM uint32_t D1FIFO;            /*!< (@ 0x0000001C) D1FIFO Port Register                                       */
18372 
18373             struct
18374             {
18375                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO PortRead receive data from the FIFO buffer or write
18376                                                *   transmit data to the FIFO buffer by accessing these bits.                 */
18377             } D1FIFO_b;
18378         };
18379 
18380         struct
18381         {
18382             union
18383             {
18384                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) D1FIFO Port Register L                                     */
18385                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) D1FIFO Port Register LL                                    */
18386             };
18387 
18388             union
18389             {
18390                 __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) D1FIFO Port Register H                                     */
18391 
18392                 struct
18393                 {
18394                     __IM uint8_t  RESERVED5;
18395                     __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) D1FIFO Port Register HH                                    */
18396                 };
18397             };
18398         };
18399     };
18400 
18401     union
18402     {
18403         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
18404 
18405         struct
18406         {
18407             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
18408             uint16_t               : 1;
18409             __IOM uint16_t ISEL    : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected                    */
18410             uint16_t               : 2;
18411             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
18412             uint16_t               : 1;
18413             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
18414             uint16_t               : 2;
18415             __OM uint16_t  REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
18416             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
18417         } CFIFOSEL_b;
18418     };
18419 
18420     union
18421     {
18422         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) CFIFO Port Control Register                                */
18423 
18424         struct
18425         {
18426             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
18427                                         *   data.                                                                     */
18428             uint16_t           : 1;
18429             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
18430                                         *   be accessed.                                                              */
18431             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
18432             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
18433         } CFIFOCTR_b;
18434     };
18435     __IM uint32_t RESERVED6;
18436 
18437     union
18438     {
18439         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
18440 
18441         struct
18442         {
18443             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
18444             uint16_t               : 4;
18445             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
18446             uint16_t               : 1;
18447             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
18448             __IOM uint16_t DREQE   : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable                                 */
18449             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
18450                                          *   Pipe Data is Read                                                         */
18451             __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
18452             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
18453         } D0FIFOSEL_b;
18454     };
18455 
18456     union
18457     {
18458         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) D0FIFO Port Control Register                               */
18459 
18460         struct
18461         {
18462             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
18463                                         *   data.                                                                     */
18464             uint16_t           : 1;
18465             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
18466                                         *   be accessed.                                                              */
18467             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
18468             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
18469         } D0FIFOCTR_b;
18470     };
18471 
18472     union
18473     {
18474         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
18475 
18476         struct
18477         {
18478             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
18479             uint16_t               : 4;
18480             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
18481             uint16_t               : 1;
18482             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
18483             __IOM uint16_t DREQE   : 1; /*!< [12..12] UCL_Dx_DREQ Signal Output Enable                                 */
18484             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode Accessed after Specified
18485                                          *   Pipe Data is Read                                                         */
18486             __OM uint16_t  REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
18487             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
18488         } D1FIFOSEL_b;
18489     };
18490 
18491     union
18492     {
18493         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) D1FIFO Port Control Register                               */
18494 
18495         struct
18496         {
18497             __IM uint16_t DTLN : 12;   /*!< [11..0] Receive Data Length.Indicates the length of the receive
18498                                         *   data.                                                                     */
18499             uint16_t           : 1;
18500             __IM uint16_t FRDY : 1;    /*!< [13..13] FIFO Port ReadyIndicates whether the FIFO port can
18501                                         *   be accessed.                                                              */
18502             __OM uint16_t  BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
18503             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
18504         } D1FIFOCTR_b;
18505     };
18506 
18507     union
18508     {
18509         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
18510 
18511         struct
18512         {
18513             uint16_t             : 8;
18514             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
18515             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
18516             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
18517             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
18518             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
18519             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
18520             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
18521             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
18522         } INTENB0_b;
18523     };
18524 
18525     union
18526     {
18527         __IOM uint16_t INTENB1;            /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
18528 
18529         struct
18530         {
18531             __IOM uint16_t PDDETINTE0 : 1; /*!< [0..0] PDDETINT0 Detection Interrupt Enable                               */
18532             uint16_t                  : 3;
18533             __IOM uint16_t SACKE      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Enable                 */
18534             __IOM uint16_t SIGNE      : 1; /*!< [5..5] Setup Transaction Error Interrupt Enable                           */
18535             __IOM uint16_t EOFERRE    : 1; /*!< [6..6] EOF Error Detection Interrupt Enable                               */
18536             uint16_t                  : 1;
18537             __IOM uint16_t LPMENDE    : 1; /*!< [8..8] LPM Transaction End Interrupt Enable                               */
18538             __IOM uint16_t L1RSMENDE  : 1; /*!< [9..9] L1 Resume End Interrupt Enable                                     */
18539             uint16_t                  : 1;
18540             __IOM uint16_t ATTCHE     : 1; /*!< [11..11] Connection Detection Interrupt Enable                            */
18541             __IOM uint16_t DTCHE      : 1; /*!< [12..12] Disconnection Detection Interrupt Enable                         */
18542             uint16_t                  : 1;
18543             __IOM uint16_t BCHGE      : 1; /*!< [14..14] USB Bus Change Interrupt Enable                                  */
18544             __IOM uint16_t OVRCRE     : 1; /*!< [15..15] OVRCRE Interrupt Enable                                          */
18545         } INTENB1_b;
18546     };
18547     __IM uint16_t RESERVED7;
18548 
18549     union
18550     {
18551         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
18552 
18553         struct
18554         {
18555             __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe                                */
18556             uint16_t                 : 6;
18557         } BRDYENB_b;
18558     };
18559 
18560     union
18561     {
18562         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
18563 
18564         struct
18565         {
18566             __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe                                */
18567             uint16_t                 : 6;
18568         } NRDYENB_b;
18569     };
18570 
18571     union
18572     {
18573         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
18574 
18575         struct
18576         {
18577             __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe                                */
18578             uint16_t                 : 6;
18579         } BEMPENB_b;
18580     };
18581 
18582     union
18583     {
18584         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Pin Configuration Register                             */
18585 
18586         struct
18587         {
18588             uint16_t               : 4;
18589             __IM uint16_t  EDGESTS : 1;  /*!< [4..4] Interrupt Edge Processing Status Monitor                           */
18590             __IOM uint16_t INTL    : 1;  /*!< [5..5] Interrupt Output Sense Select                                      */
18591             __IOM uint16_t BRDYM   : 1;  /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing.This bit can be
18592                                           *   set only in the initial setting (before communications).The
18593                                           *   setting cannot be changed once communication starts.                      */
18594             uint16_t                : 1;
18595             __IOM uint16_t TRNENSEL : 1; /*!< [8..8] Transaction-Enabled Time Select.The transfer efficiency
18596                                           *   can be improved by setting this bit to 1 if no low-speed
18597                                           *   device is connected directly or via FS-HUB to the USB port.               */
18598             uint16_t : 7;
18599         } SOFCFG_b;
18600     };
18601 
18602     union
18603     {
18604         __IOM uint16_t PHYSET;           /*!< (@ 0x0000003E) PHY Setting Register                                       */
18605 
18606         struct
18607         {
18608             __IOM uint16_t DIRPD    : 1; /*!< [0..0] Power-Down Control                                                 */
18609             __IOM uint16_t PLLRESET : 1; /*!< [1..1] PLL Reset Control                                                  */
18610             uint16_t                : 1;
18611             __IOM uint16_t CDPEN    : 1; /*!< [3..3] Charging Downstream Port Enable                                    */
18612             __IOM uint16_t CLKSEL   : 2; /*!< [5..4] Input System Clock Frequency                                       */
18613             uint16_t                : 2;
18614             __IOM uint16_t REPSEL   : 2; /*!< [9..8] Terminating Resistance Adjustment Cycle                            */
18615             uint16_t                : 1;
18616             __IOM uint16_t REPSTART : 1; /*!< [11..11] Forcibly Start Terminating Resistance Adjustment                 */
18617             uint16_t                : 3;
18618             __IOM uint16_t HSEB     : 1; /*!< [15..15] CL-Only Mode                                                     */
18619         } PHYSET_b;
18620     };
18621 
18622     union
18623     {
18624         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
18625 
18626         struct
18627         {
18628             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
18629             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
18630             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
18631             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
18632             __IM uint16_t  BRDY  : 1;  /*!< [8..8] Buffer Ready Interrupt Status                                      */
18633             __IM uint16_t  NRDY  : 1;  /*!< [9..9] Buffer Not Ready Interrupt Status                                  */
18634             __IM uint16_t  BEMP  : 1;  /*!< [10..10] Buffer Empty Interrupt Status                                    */
18635             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
18636             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
18637             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Refresh Interrupt Status                            */
18638             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
18639             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Interrupt Status                                            */
18640         } INTSTS0_b;
18641     };
18642 
18643     union
18644     {
18645         __IOM uint16_t INTSTS1;           /*!< (@ 0x00000042) Interrupt Status Register 1                                */
18646 
18647         struct
18648         {
18649             __IOM uint16_t PDDETINT0 : 1; /*!< [0..0] PDDET Detection Interrupt Status                                   */
18650             uint16_t                 : 3;
18651             __IOM uint16_t SACK      : 1; /*!< [4..4] Setup Transaction Normal Response Interrupt Status                 */
18652             __IOM uint16_t SIGN      : 1; /*!< [5..5] Setup Transaction Error Interrupt Status                           */
18653             __IOM uint16_t EOFERR    : 1; /*!< [6..6] EOF Error Detection Interrupt Status                               */
18654             uint16_t                 : 1;
18655             __IOM uint16_t LPMEND    : 1; /*!< [8..8] LPM Transaction End Interrupt Status                               */
18656             __IOM uint16_t L1RSMEND  : 1; /*!< [9..9] L1 Resume End Interrupt Status                                     */
18657             uint16_t                 : 1;
18658             __IOM uint16_t ATTCH     : 1; /*!< [11..11] USB Connection Detection Interrupt Status                        */
18659             __IOM uint16_t DTCH      : 1; /*!< [12..12] USB Disconnection Detection Interrupt Status                     */
18660             uint16_t                 : 1;
18661             __IOM uint16_t BCHG      : 1; /*!< [14..14] USB Bus Change Interrupt Status                                  */
18662             __IOM uint16_t OVRCR     : 1; /*!< [15..15] Overcurrent Interrupt Status                                     */
18663         } INTSTS1_b;
18664     };
18665     __IM uint16_t RESERVED8;
18666 
18667     union
18668     {
18669         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
18670 
18671         struct
18672         {
18673             __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe                                */
18674             uint16_t                : 6;
18675         } BRDYSTS_b;
18676     };
18677 
18678     union
18679     {
18680         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
18681 
18682         struct
18683         {
18684             __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe                                */
18685             uint16_t                : 6;
18686         } NRDYSTS_b;
18687     };
18688 
18689     union
18690     {
18691         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
18692 
18693         struct
18694         {
18695             __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe                                */
18696             uint16_t                : 6;
18697         } BEMPSTS_b;
18698     };
18699 
18700     union
18701     {
18702         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
18703 
18704         struct
18705         {
18706             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame Number.Indicate the latest frame number.                    */
18707             uint16_t            : 3;
18708             __IOM uint16_t CRCE : 1;   /*!< [14..14] CRC Error Detection Status                                       */
18709             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
18710         } FRMNUM_b;
18711     };
18712 
18713     union
18714     {
18715         __IOM uint16_t UFRMNUM;        /*!< (@ 0x0000004E) uFrame Number Register                                     */
18716 
18717         struct
18718         {
18719             __IM uint16_t UFRNM  : 3;  /*!< [2..0] MicroframeIndicate the microframe number.                          */
18720             uint16_t             : 12;
18721             __IOM uint16_t DVCHG : 1;  /*!< [15..15] Device State Change                                              */
18722         } UFRMNUM_b;
18723     };
18724 
18725     union
18726     {
18727         __IOM uint16_t USBADDR;        /*!< (@ 0x00000050) USB Address Register                                       */
18728 
18729         struct
18730         {
18731             uint16_t                 : 8;
18732             __IOM uint16_t STSRECOV0 : 3; /*!< [10..8] Status Recovery                                                   */
18733             uint16_t                 : 5;
18734         } USBADDR_b;
18735     };
18736     __IM uint16_t RESERVED9;
18737 
18738     union
18739     {
18740         __IOM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
18741 
18742         struct
18743         {
18744             __IOM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] USB request bmRequestType value Finction controller selected
18745                                                *   : read-only Host controller selected : read-write                         */
18746             __IOM uint16_t BREQUEST : 8;      /*!< [15..8] USB request bRequest value Finction controller selected
18747                                                *   : read-only Host controller selected : read-write                         */
18748         } USBREQ_b;
18749     };
18750 
18751     union
18752     {
18753         __IOM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
18754 
18755         struct
18756         {
18757             __IOM uint16_t WVALUE : 16; /*!< [15..0] Value of USB request wValue Finction controller selected
18758                                          *   : read-only Host controller selected : read-write                         */
18759         } USBVAL_b;
18760     };
18761 
18762     union
18763     {
18764         __IOM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
18765 
18766         struct
18767         {
18768             __IOM uint16_t WINDEX : 16; /*!< [15..0] Value of USB request wIndex Finction controller selected
18769                                          *   : read-only Host controller selected : read-write                         */
18770         } USBINDX_b;
18771     };
18772 
18773     union
18774     {
18775         __IOM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
18776 
18777         struct
18778         {
18779             __IOM uint16_t WLENGTH : 16; /*!< [15..0] Value of USB request wLength Finction controller selected
18780                                           *   : read-only Host controller selected : read-write                         */
18781         } USBLENG_b;
18782     };
18783 
18784     union
18785     {
18786         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
18787 
18788         struct
18789         {
18790             uint16_t              : 4;
18791             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
18792             uint16_t              : 2;
18793             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Blocking on End of Transfer                                   */
18794             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
18795             uint16_t              : 7;
18796         } DCPCFG_b;
18797     };
18798 
18799     union
18800     {
18801         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
18802 
18803         struct
18804         {
18805             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet SizeThese bits specify the maximum data
18806                                         *   payload (maximum packet size) for the DCP.                                */
18807             uint16_t              : 5;
18808             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
18809                                         *   destination function device for control transfer when the
18810                                         *   host controller function is selected.                                     */
18811         } DCPMAXP_b;
18812     };
18813 
18814     union
18815     {
18816         __IOM uint16_t DCPCTR;           /*!< (@ 0x00000060) DCP Control Register                                       */
18817 
18818         struct
18819         {
18820             __IOM uint16_t PID      : 2; /*!< [1..0] Response PID                                                       */
18821             __IOM uint16_t CCPL     : 1; /*!< [2..2] Control Transfer End Enable                                        */
18822             uint16_t                : 1;
18823             __IOM uint16_t PINGE    : 1; /*!< [4..4] PING Token Issue Enable                                            */
18824             __IM uint16_t  PBUSY    : 1; /*!< [5..5] Pipe Busy                                                          */
18825             __IM uint16_t  SQMON    : 1; /*!< [6..6] Sequence Toggle Bit Monitor                                        */
18826             __IOM uint16_t SQSET    : 1; /*!< [7..7] Toggle Bit Set                                                     */
18827             __IOM uint16_t SQCLR    : 1; /*!< [8..8] Toggle Bit Clear                                                   */
18828             uint16_t                : 2;
18829             __IOM uint16_t SUREQCLR : 1; /*!< [11..11] SUREQ Bit Clear                                                  */
18830             __IM uint16_t  CSSTS    : 1; /*!< [12..12] Split Transaction COMPLETE SPLIT(CSPLIT) Status                  */
18831             __IOM uint16_t CSCLR    : 1; /*!< [13..13] Split Transaction CSPLIT Status Clear                            */
18832             __IOM uint16_t SUREQ    : 1; /*!< [14..14] SETUP Token Transmission                                         */
18833             __IM uint16_t  BSTS     : 1; /*!< [15..15] Buffer Status                                                    */
18834         } DCPCTR_b;
18835     };
18836     __IM uint16_t  RESERVED10;
18837     __IOM uint16_t PIPESEL;              /*!< (@ 0x00000064) Pipe Window Select Register                                */
18838     __IM uint16_t  RESERVED11;
18839 
18840     union
18841     {
18842         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
18843 
18844         struct
18845         {
18846             __IOM uint16_t EPNUM  : 4; /*!< [3..0] Endpoint Number                                                    */
18847             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
18848             uint16_t              : 2;
18849             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disabled at End of Transfer                                   */
18850             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
18851             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
18852             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
18853             uint16_t              : 3;
18854             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
18855         } PIPECFG_b;
18856     };
18857 
18858     union
18859     {
18860         __IOM uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Register                                       */
18861 
18862         struct
18863         {
18864             __IOM uint16_t BUFNMB : 8;  /*!< [7..0] Buffer NumberThese bits specify the FIFO buffer number
18865                                          *   of the selected pipe (04h to 87h).                                        */
18866             uint16_t               : 2;
18867             __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer Size 00h: 64 bytes 01h: 128 bytes : 1Fh: 2 Kbytes         */
18868             uint16_t               : 1;
18869         } PIPEBUF_b;
18870     };
18871 
18872     union
18873     {
18874         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
18875 
18876         struct
18877         {
18878             __IOM uint16_t MXPS : 11;  /*!< [10..0] Maximum Packet SizeThese bits specify the maximum data
18879                                         *   payload (maximum packet size) for the selected pipe.A size
18880                                         *   of 1h to 40h bytes can be set for PIPE6 to PIPE9.                         */
18881             uint16_t              : 1;
18882             __IOM uint16_t DEVSEL : 4; /*!< [15..12] Device SelectThese bits specify the address of the
18883                                         *   peripheral device when the host controller function is
18884                                         *   selected.                                                                 */
18885         } PIPEMAXP_b;
18886     };
18887 
18888     union
18889     {
18890         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Cycle Control Register                                */
18891 
18892         struct
18893         {
18894             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection IntervalThese bits specify the
18895                                         *   transfer interval timing for the selected pipe as n-th
18896                                         *   power of 2 of the frame timing.                                           */
18897             uint16_t            : 9;
18898             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
18899             uint16_t            : 3;
18900         } PIPEPERI_b;
18901     };
18902 
18903     union
18904     {
18905         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) PIPE Control Register                                      */
18906 
18907         struct
18908         {
18909             __IOM uint16_t PID : 2;    /*!< [1..0] Response PIDThese bits specify the response type for
18910                                         *   the next transaction of the relevant pipe.                                */
18911             uint16_t            : 3;
18912             __IM uint16_t PBUSY : 1;   /*!< [5..5] Pipe BusyThis bit indicates whether the relevant pipe
18913                                         *   is being used for the USB bus                                             */
18914             __IM uint16_t SQMON : 1;   /*!< [6..6] Toggle Bit ConfirmationThis bit indicates the expected
18915                                         *   value of the sequence toggle bit for the next transaction
18916                                         *   of the relevant pipe                                                      */
18917             __IOM uint16_t SQSET : 1;  /*!< [7..7] Toggle Bit SetThis bit is set to 1 when the expected
18918                                         *   value of the sequence toggle bit for the next transaction
18919                                         *   of the relevant pipe is set for DATA1                                     */
18920             __IOM uint16_t SQCLR : 1;  /*!< [8..8] Toggle Bit ClearThis bit is set to 1 when the expected
18921                                         *   value of the sequence toggle bit for the next transaction
18922                                         *   of the relevant pipe is cleared to DATA0                                  */
18923             __IOM uint16_t ACLRM : 1;  /*!< [9..9] Auto Buffer Clear ModeThis bit enables or disables auto
18924                                         *   buffer clear mode for the relevant pipe                                   */
18925             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response ModeThis bit enables or disables auto
18926                                         *   response mode for the relevant pipe.                                      */
18927             uint16_t            : 1;
18928             __IM uint16_t CSSTS : 1;   /*!< [12..12] CSSTS StatusThis bit indicates the CSPLIT status of
18929                                         *   Split Transaction of the relevant pipe                                    */
18930             __IOM uint16_t CSCLR : 1;  /*!< [13..13] CSPLIT Status ClearSet this bit to 1 when clearing
18931                                         *   the CSSTS bit of the relevant pipe                                        */
18932             __IM uint16_t INBUFM : 1;  /*!< [14..14] Transmit Buffer MonitorThis bit indicates the FIFO
18933                                         *   buffer status for the relevant pipe in the transmitting
18934                                         *   direction.                                                                */
18935             __IM uint16_t BSTS : 1;    /*!< [15..15] Buffer StatusThis bit indicates the FIFO buffer status
18936                                         *   for the relevant pipe.                                                    */
18937         } PIPE_CTR_b[9];
18938     };
18939     __IM uint16_t                RESERVED12;
18940     __IM uint32_t                RESERVED13[3];
18941     __IOM R_USB_HS0_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) Pipe Transaction Counter Registers                         */
18942     __IM uint32_t                RESERVED14[11];
18943 
18944     union
18945     {
18946         __IOM uint16_t DEVADD[10];     /*!< (@ 0x000000D0) Device Address Configuration Register                      */
18947 
18948         struct
18949         {
18950             uint16_t               : 6;
18951             __IOM uint16_t USBSPD  : 2; /*!< [7..6] Transfer Speed of Communication Target Device                      */
18952             __IOM uint16_t HUBPORT : 3; /*!< [10..8] Communication Target Connecting Hub Port                          */
18953             __IOM uint16_t UPPHUB  : 4; /*!< [14..11] Communication Target Connecting Hub Register                     */
18954             uint16_t               : 1;
18955         } DEVADD_b[10];
18956     };
18957     __IM uint32_t RESERVED15[7];
18958 
18959     union
18960     {
18961         __IOM uint16_t LPCTRL;         /*!< (@ 0x00000100) Low Power Control Register                                 */
18962 
18963         struct
18964         {
18965             uint16_t             : 7;
18966             __IOM uint16_t HWUPM : 1;  /*!< [7..7] Resume Return Mode Setting                                         */
18967             uint16_t             : 8;
18968         } LPCTRL_b;
18969     };
18970 
18971     union
18972     {
18973         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
18974 
18975         struct
18976         {
18977             uint16_t                : 14;
18978             __IOM uint16_t SUSPENDM : 1; /*!< [14..14] UTMI SuspendM Control                                            */
18979             uint16_t                : 1;
18980         } LPSTS_b;
18981     };
18982     __IM uint32_t RESERVED16[15];
18983 
18984     union
18985     {
18986         __IOM uint16_t BCCTRL;           /*!< (@ 0x00000140) Battery Charging Control Register                          */
18987 
18988         struct
18989         {
18990             __IOM uint16_t IDPSRCE  : 1; /*!< [0..0] IDPSRC Control                                                     */
18991             __IOM uint16_t IDMSINKE : 1; /*!< [1..1] IDMSINK Control                                                    */
18992             __IOM uint16_t VDPSRCE  : 1; /*!< [2..2] VDPSRC Control                                                     */
18993             __IOM uint16_t IDPSINKE : 1; /*!< [3..3] IDPSINK Control                                                    */
18994             __IOM uint16_t VDMSRCE  : 1; /*!< [4..4] VDMSRC Control                                                     */
18995             __IOM uint16_t DCPMODE  : 1; /*!< [5..5] DCP Mode Control                                                   */
18996             uint16_t                : 2;
18997             __IM uint16_t CHGDETSTS : 1; /*!< [8..8] CHGDET Status                                                      */
18998             __IM uint16_t PDDETSTS  : 1; /*!< [9..9] PDDET Status                                                       */
18999             uint16_t                : 6;
19000         } BCCTRL_b;
19001     };
19002     __IM uint16_t RESERVED17;
19003 
19004     union
19005     {
19006         __IOM uint16_t PL1CTRL1;         /*!< (@ 0x00000144) Function L1 Control Register 1                             */
19007 
19008         struct
19009         {
19010             __IOM uint16_t L1RESPEN : 1; /*!< [0..0] L1 Response Enable                                                 */
19011             __IOM uint16_t L1RESPMD : 2; /*!< [2..1] L1 Response Mode                                                   */
19012             __IOM uint16_t L1NEGOMD : 1; /*!< [3..3] L1 Response Negotiation Control.NOTE: This bit is valid
19013                                           *   only when the L1RESPMD[1:0] value is 2'b11.                               */
19014             __IM uint16_t DVSQ : 4;      /*!< [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0.Indicates
19015                                           *   the L1 state together with the device state bits DVSQ[2:0].               */
19016             __IOM uint16_t HIRDTHR : 4;  /*!< [11..8] L1 Response Negotiation Threshold ValueHIRD threshold
19017                                           *   value used for L1NEGOMD.The format is the same as the HIRD
19018                                           *   field in HL1CTRL.                                                         */
19019             uint16_t               : 2;
19020             __IOM uint16_t L1EXTMD : 1;  /*!< [14..14] PHY Control Mode at L1 Return                                    */
19021             uint16_t               : 1;
19022         } PL1CTRL1_b;
19023     };
19024 
19025     union
19026     {
19027         __IOM uint16_t PL1CTRL2;       /*!< (@ 0x00000146) Function L1 Control Register 2                             */
19028 
19029         struct
19030         {
19031             uint16_t               : 8;
19032             __IOM uint16_t HIRDMON : 4; /*!< [11..8] HIRD Value Monitor                                                */
19033             __IOM uint16_t RWEMON  : 1; /*!< [12..12] RWE Value Monitor                                                */
19034             uint16_t               : 3;
19035         } PL1CTRL2_b;
19036     };
19037 
19038     union
19039     {
19040         __IOM uint16_t HL1CTRL1;         /*!< (@ 0x00000148) Host L1 Control Register 1                                 */
19041 
19042         struct
19043         {
19044             __IOM uint16_t L1REQ    : 1; /*!< [0..0] L1 Transition Request                                              */
19045             __IM uint16_t  L1STATUS : 2; /*!< [2..1] L1 Request Completion Status                                       */
19046             uint16_t                : 13;
19047         } HL1CTRL1_b;
19048     };
19049 
19050     union
19051     {
19052         __IOM uint16_t HL1CTRL2;       /*!< (@ 0x0000014A) Host L1 Control Register 2                                 */
19053 
19054         struct
19055         {
19056             __IOM uint16_t L1ADDR : 4; /*!< [3..0] LPM Token DeviceAddressThese bits specify the value to
19057                                         *   be set in the ADDR field of LPM token.                                    */
19058             uint16_t             : 4;
19059             __IOM uint16_t HIRD  : 4;  /*!< [11..8] LPM Token HIRD                                                    */
19060             __IOM uint16_t L1RWE : 1;  /*!< [12..12] LPM Token L1 RemoteWake EnableThese bits specify the
19061                                         *   value to be set in the RWE field of LPM token.                            */
19062             uint16_t            : 2;
19063             __IOM uint16_t BESL : 1;   /*!< [15..15] BESL & Alternate HIRDThis bit selects the K-State drive
19064                                         *   period at the time of L1 Resume.                                          */
19065         } HL1CTRL2_b;
19066     };
19067     __IM uint32_t RESERVED18;
19068 
19069     union
19070     {
19071         __IOM uint16_t PHYTRIM1;          /*!< (@ 0x00000150) PHY Timing Register 1                                      */
19072 
19073         struct
19074         {
19075             __IOM uint16_t DRISE     : 2; /*!< [1..0] FS/LS Rising-Edge Output Waveform Adjustment Function              */
19076             __IOM uint16_t DFALL     : 2; /*!< [3..2] FS/LS Falling-Edge Output Waveform Adjustment Function             */
19077             uint16_t                 : 3;
19078             __IOM uint16_t PCOMPENB  : 1; /*!< [7..7] PVDD Start-up Detection                                            */
19079             __IOM uint16_t HSIUP     : 4; /*!< [11..8] HS Output Level Setting                                           */
19080             __IOM uint16_t IMPOFFSET : 3; /*!< [14..12] terminating resistance offset value setting.Offset
19081                                            *   value for adjusting the terminating resistance.                           */
19082             uint16_t : 1;
19083         } PHYTRIM1_b;
19084     };
19085 
19086     union
19087     {
19088         __IOM uint16_t PHYTRIM2;         /*!< (@ 0x00000152) PHY Timing Register 2                                      */
19089 
19090         struct
19091         {
19092             __IOM uint16_t SQU      : 4; /*!< [3..0] Squelch Detection Level                                            */
19093             uint16_t                : 3;
19094             __IOM uint16_t HSRXENMO : 1; /*!< [7..7] HS Receive Enable Control Mode                                     */
19095             __IOM uint16_t PDR      : 2; /*!< [9..8] HS Output Adjustment Function                                      */
19096             uint16_t                : 2;
19097             __IOM uint16_t DIS      : 3; /*!< [14..12] Disconnect Detection Level                                       */
19098             uint16_t                : 1;
19099         } PHYTRIM2_b;
19100     };
19101     __IM uint32_t RESERVED19[3];
19102 
19103     union
19104     {
19105         __IM uint32_t DPUSR0R;         /*!< (@ 0x00000160) Deep Standby USB Transceiver Control/Pin Monitor
19106                                         *                  Register                                                   */
19107 
19108         struct
19109         {
19110             uint32_t              : 20;
19111             __IM uint32_t DOVCAHM : 1;  /*!< [20..20] OVRCURA InputIndicates OVRCURA input signal on the
19112                                          *   HS side of USB port.                                                      */
19113             __IM uint32_t DOVCBHM : 1;  /*!< [21..21] OVRCURB InputIndicates OVRCURB input signal on the
19114                                          *   HS side of USB port.                                                      */
19115             uint32_t               : 1;
19116             __IM uint32_t DVBSTSHM : 1; /*!< [23..23] VBUS InputIndicates VBUS input signal on the HS side
19117                                          *   of USB port.                                                              */
19118             uint32_t : 8;
19119         } DPUSR0R_b;
19120     };
19121 
19122     union
19123     {
19124         __IOM uint32_t DPUSR1R;        /*!< (@ 0x00000164) Deep Standby USB Suspend/Resume Interrupt Register         */
19125 
19126         struct
19127         {
19128             uint32_t                : 4;
19129             __IOM uint32_t DOVCAHE  : 1; /*!< [4..4] OVRCURA Interrupt Enable Clear                                     */
19130             __IOM uint32_t DOVCBHE  : 1; /*!< [5..5] OVRCURB Interrupt Enable Clear                                     */
19131             uint32_t                : 1;
19132             __IOM uint32_t DVBSTSHE : 1; /*!< [7..7] VBUS Interrupt Enable/Clear                                        */
19133             uint32_t                : 12;
19134             __IM uint32_t DOVCAH    : 1; /*!< [20..20] Indication of Return from OVRCURA Interrupt Source               */
19135             __IM uint32_t DOVCBH    : 1; /*!< [21..21] Indication of Return from OVRCURB Interrupt Source               */
19136             uint32_t                : 1;
19137             __IM uint32_t DVBSTSH   : 1; /*!< [23..23] Indication of Return from VBUS Interrupt Source                  */
19138             uint32_t                : 8;
19139         } DPUSR1R_b;
19140     };
19141 
19142     union
19143     {
19144         __IOM uint16_t DPUSR2R;        /*!< (@ 0x00000168) Deep Standby USB Suspend/Resume Interrupt Register         */
19145 
19146         struct
19147         {
19148             __IM uint16_t DPINT : 1;   /*!< [0..0] Indication of Return from DP Interrupt Source                      */
19149             __IM uint16_t DMINT : 1;   /*!< [1..1] Indication of Return from DM Interrupt Source                      */
19150             uint16_t            : 2;
19151             __IM uint16_t DPVAL : 1;   /*!< [4..4] DP InputIndicates DP input signal on the HS side of USB
19152                                         *   port.                                                                     */
19153             __IM uint16_t DMVAL : 1;   /*!< [5..5] DM InputIndicates DM input signal on the HS side of USB
19154                                         *   port.                                                                     */
19155             uint16_t              : 2;
19156             __IOM uint16_t DPINTE : 1; /*!< [8..8] DP Interrupt Enable Clear                                          */
19157             __IOM uint16_t DMINTE : 1; /*!< [9..9] DM Interrupt Enable Clear                                          */
19158             uint16_t              : 6;
19159         } DPUSR2R_b;
19160     };
19161 
19162     union
19163     {
19164         __IOM uint16_t DPUSRCR;          /*!< (@ 0x0000016A) Deep Standby USB Suspend/Resume Command Register           */
19165 
19166         struct
19167         {
19168             __IOM uint16_t FIXPHY   : 1; /*!< [0..0] USB Transceiver Control Fix                                        */
19169             __IOM uint16_t FIXPHYPD : 1; /*!< [1..1] USB Transceiver Control Fix for PLL                                */
19170             uint16_t                : 14;
19171         } DPUSRCR_b;
19172     };
19173 } R_USB_HS0_Type;                        /*!< Size = 364 (0x16c)                                                        */
19174 
19175 /* =========================================================================================================================== */
19176 /* ================                                          R_AGTX0                                          ================ */
19177 /* =========================================================================================================================== */
19178 
19179 /**
19180  * @brief Asynchronous General Purpose Timer (R_AGTX0)
19181  */
19182 
19183 typedef struct                          /*!< (@ 0x400E8000) R_AGTX0 Structure                                          */
19184 {
19185     union
19186     {
19187         __IOM R_AGTX0_AGT32_Type AGT32; /*!< (@ 0x00000000) AGTW (32-bit) peripheral registers                         */
19188         __IOM R_AGTX0_AGT16_Type AGT16; /*!< (@ 0x00000000) AGT (16-bit) peripheral registers                          */
19189     };
19190 } R_AGTX0_Type;                         /*!< Size = 20 (0x14)                                                          */
19191 
19192 /* =========================================================================================================================== */
19193 /* ================                                          R_FLAD                                           ================ */
19194 /* =========================================================================================================================== */
19195 
19196 /**
19197  * @brief Data Flash (R_FLAD)
19198  */
19199 
19200 typedef struct                         /*!< (@ 0x407FC000) R_FLAD Structure                                           */
19201 {
19202     __IM uint8_t RESERVED[64];
19203 
19204     union
19205     {
19206         __IOM uint8_t FCKMHZ;          /*!< (@ 0x00000040) Data Flash Access Frequency Register                       */
19207 
19208         struct
19209         {
19210             __IOM uint8_t FCKMHZ : 8;  /*!< [7..0] Data Flash Access Frequency Register                               */
19211         } FCKMHZ_b;
19212     };
19213 } R_FLAD_Type;                         /*!< Size = 65 (0x41)                                                          */
19214 
19215 /** @} */ /* End of group Device_Peripheral_peripherals */
19216 
19217 /* =========================================================================================================================== */
19218 /* ================                          Device Specific Peripheral Address Map                           ================ */
19219 /* =========================================================================================================================== */
19220 
19221 /** @addtogroup Device_Peripheral_peripheralAddr
19222  * @{
19223  */
19224 
19225  #define R_ADC0_BASE            0x40170000UL
19226  #define R_ADC1_BASE            0x40170200UL
19227  #define R_PSCU_BASE            0x400E0000UL
19228  #define R_BUS_BASE             0x40003000UL
19229  #define R_CAC_BASE             0x40083600UL
19230  #define R_CANFD_BASE           0x400B0000UL
19231  #define R_CRC_BASE             0x40108000UL
19232  #define R_CTSU_BASE            0x400D0000UL
19233  #define R_DAC_BASE             0x40171000UL
19234  #define R_DEBUG_BASE           0x4001B000UL
19235  #define R_DMA_BASE             0x40005200UL
19236  #define R_DMAC0_BASE           0x40005000UL
19237  #define R_DMAC1_BASE           0x40005040UL
19238  #define R_DMAC2_BASE           0x40005080UL
19239  #define R_DMAC3_BASE           0x400050C0UL
19240  #define R_DMAC4_BASE           0x40005100UL
19241  #define R_DMAC5_BASE           0x40005140UL
19242  #define R_DMAC6_BASE           0x40005180UL
19243  #define R_DMAC7_BASE           0x400051C0UL
19244  #define R_DOC_BASE             0x40109000UL
19245  #define R_DTC_BASE             0x40005400UL
19246  #define R_ELC_BASE             0x40082000UL
19247  #define R_ETHERC0_BASE         0x40114100UL
19248  #define R_ETHERC_EDMAC_BASE    0x40114000UL
19249  #define R_FACI_HP_CMD_BASE     0x407E0000UL
19250  #define R_FACI_HP_BASE         0x407FE000UL
19251  #define R_FCACHE_BASE          0x4001C000UL
19252  #define R_GPT0_BASE            0x40169000UL
19253  #define R_GPT1_BASE            0x40169100UL
19254  #define R_GPT2_BASE            0x40169200UL
19255  #define R_GPT3_BASE            0x40169300UL
19256  #define R_GPT4_BASE            0x40169400UL
19257  #define R_GPT5_BASE            0x40169500UL
19258  #define R_GPT6_BASE            0x40169600UL
19259  #define R_GPT7_BASE            0x40169700UL
19260  #define R_GPT8_BASE            0x40169800UL
19261  #define R_GPT9_BASE            0x40169900UL
19262  #define R_GPT10_BASE           0x40169A00UL
19263  #define R_GPT11_BASE           0x40169B00UL
19264  #define R_GPT12_BASE           0x40169C00UL
19265  #define R_GPT13_BASE           0x40169D00UL
19266  #define R_GPT_OPS_BASE         0x40169A00UL
19267  #define R_GPT_POEG0_BASE       0x4008A000UL
19268  #define R_GPT_POEG1_BASE       0x4008A100UL
19269  #define R_GPT_POEG2_BASE       0x4008A200UL
19270  #define R_GPT_POEG3_BASE       0x4008A300UL
19271  #define R_ICU_BASE             0x40006000UL
19272  #define R_IIC0_BASE            0x4009F000UL
19273  #define R_IIC1_BASE            0x4009F100UL
19274  #define R_IIC2_BASE            0x4009F200UL
19275  #define R_IWDT_BASE            0x40083200UL
19276  #define R_I3C0_BASE            0x4011F000UL
19277  #define R_I3C1_BASE            0x4011F400UL
19278  #define R_MPU_MMPU_BASE        0x40000000UL
19279  #define R_MPU_SPMON_BASE       0x40000D00UL
19280  #define R_MSTP_BASE            0x40084000UL
19281  #define R_PORT0_BASE           0x40080000UL
19282  #define R_PORT1_BASE           0x40080020UL
19283  #define R_PORT2_BASE           0x40080040UL
19284  #define R_PORT3_BASE           0x40080060UL
19285  #define R_PORT4_BASE           0x40080080UL
19286  #define R_PORT5_BASE           0x400800A0UL
19287  #define R_PORT6_BASE           0x400800C0UL
19288  #define R_PORT7_BASE           0x400800E0UL
19289  #define R_PORT8_BASE           0x40080100UL
19290  #define R_PORT9_BASE           0x40080120UL
19291  #define R_PORT10_BASE          0x40080140UL
19292  #define R_PORT11_BASE          0x40080160UL
19293  #define R_PORT12_BASE          0x40080180UL
19294  #define R_PORT13_BASE          0x400801A0UL
19295  #define R_PORT14_BASE          0x400801C0UL
19296  #define R_PFS_BASE             0x40080800UL
19297  #define R_PMISC_BASE           0x40080D00UL
19298  #define R_QSPI_BASE            0x64000000UL
19299  #define R_RTC_BASE             0x40083000UL
19300  #define R_SCI0_BASE            0x40118000UL
19301  #define R_SCI1_BASE            0x40118100UL
19302  #define R_SCI2_BASE            0x40118200UL
19303  #define R_SCI3_BASE            0x40118300UL
19304  #define R_SCI4_BASE            0x40118400UL
19305  #define R_SCI5_BASE            0x40118500UL
19306  #define R_SCI6_BASE            0x40118600UL
19307  #define R_SCI7_BASE            0x40118700UL
19308  #define R_SCI8_BASE            0x40118800UL
19309  #define R_SCI9_BASE            0x40118900UL
19310  #define R_SDHI0_BASE           0x40092000UL
19311  #define R_SDHI1_BASE           0x40092400UL
19312  #define R_SPI0_BASE            0x4011A000UL
19313  #define R_SPI1_BASE            0x4011A100UL
19314  #define R_SRAM_BASE            0x40002000UL
19315  #define R_SSI0_BASE            0x4009D000UL
19316  #define R_SSI1_BASE            0x4009D100UL
19317  #define R_SYSTEM_BASE          0x4001E000UL
19318  #define R_TSN_CAL_BASE         0x407FB17CUL
19319  #define R_TSN_CTRL_BASE        0x400F3000UL
19320  #define R_USB_FS0_BASE         0x40090000UL
19321  #define R_WDT_BASE             0x40083400UL
19322  #define R_TZF_BASE             0x40000E00UL
19323  #define R_CACHE_BASE           0x40007000UL
19324  #define R_CPSCU_BASE           0x40008000UL
19325  #define R_CEC_BASE             0x400AC000UL
19326  #define R_OSPI_BASE            0x400A6000UL
19327  #define R_USB_HS0_BASE         0x40111000UL
19328  #define R_AGTX0_BASE           0x400E8000UL
19329  #define R_AGTX1_BASE           0x400E8100UL
19330  #define R_AGTX2_BASE           0x400E8200UL
19331  #define R_AGTX3_BASE           0x400E8300UL
19332  #define R_AGTX4_BASE           0x400E8400UL
19333  #define R_AGTX5_BASE           0x400E8500UL
19334  #define R_AGTX6_BASE           0x400E8600UL
19335  #define R_AGTX7_BASE           0x400E8700UL
19336  #define R_AGTX8_BASE           0x400E8800UL
19337  #define R_AGTX9_BASE           0x400E8900UL
19338  #define R_FLAD_BASE            0x407FC000UL
19339 
19340 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
19341 
19342 /* =========================================================================================================================== */
19343 /* ================                                  Peripheral declaration                                   ================ */
19344 /* =========================================================================================================================== */
19345 
19346 /** @addtogroup Device_Peripheral_declaration
19347  * @{
19348  */
19349 
19350  #define R_ADC0            ((R_ADC0_Type *) R_ADC0_BASE)
19351  #define R_ADC1            ((R_ADC0_Type *) R_ADC1_BASE)
19352  #define R_PSCU            ((R_PSCU_Type *) R_PSCU_BASE)
19353  #define R_BUS             ((R_BUS_Type *) R_BUS_BASE)
19354  #define R_CAC             ((R_CAC_Type *) R_CAC_BASE)
19355  #define R_CANFD           ((R_CANFD_Type *) R_CANFD_BASE)
19356  #define R_CRC             ((R_CRC_Type *) R_CRC_BASE)
19357  #define R_CTSU            ((R_CTSU_Type *) R_CTSU_BASE)
19358  #define R_DAC             ((R_DAC_Type *) R_DAC_BASE)
19359  #define R_DEBUG           ((R_DEBUG_Type *) R_DEBUG_BASE)
19360  #define R_DMA             ((R_DMA_Type *) R_DMA_BASE)
19361  #define R_DMAC0           ((R_DMAC0_Type *) R_DMAC0_BASE)
19362  #define R_DMAC1           ((R_DMAC0_Type *) R_DMAC1_BASE)
19363  #define R_DMAC2           ((R_DMAC0_Type *) R_DMAC2_BASE)
19364  #define R_DMAC3           ((R_DMAC0_Type *) R_DMAC3_BASE)
19365  #define R_DMAC4           ((R_DMAC0_Type *) R_DMAC4_BASE)
19366  #define R_DMAC5           ((R_DMAC0_Type *) R_DMAC5_BASE)
19367  #define R_DMAC6           ((R_DMAC0_Type *) R_DMAC6_BASE)
19368  #define R_DMAC7           ((R_DMAC0_Type *) R_DMAC7_BASE)
19369  #define R_DOC             ((R_DOC_Type *) R_DOC_BASE)
19370  #define R_DTC             ((R_DTC_Type *) R_DTC_BASE)
19371  #define R_ELC             ((R_ELC_Type *) R_ELC_BASE)
19372  #define R_ETHERC0         ((R_ETHERC0_Type *) R_ETHERC0_BASE)
19373  #define R_ETHERC_EDMAC    ((R_ETHERC_EDMAC_Type *) R_ETHERC_EDMAC_BASE)
19374  #define R_FACI_HP_CMD     ((R_FACI_HP_CMD_Type *) R_FACI_HP_CMD_BASE)
19375  #define R_FACI_HP         ((R_FACI_HP_Type *) R_FACI_HP_BASE)
19376  #define R_FCACHE          ((R_FCACHE_Type *) R_FCACHE_BASE)
19377  #define R_GPT0            ((R_GPT0_Type *) R_GPT0_BASE)
19378  #define R_GPT1            ((R_GPT0_Type *) R_GPT1_BASE)
19379  #define R_GPT2            ((R_GPT0_Type *) R_GPT2_BASE)
19380  #define R_GPT3            ((R_GPT0_Type *) R_GPT3_BASE)
19381  #define R_GPT4            ((R_GPT0_Type *) R_GPT4_BASE)
19382  #define R_GPT5            ((R_GPT0_Type *) R_GPT5_BASE)
19383  #define R_GPT6            ((R_GPT0_Type *) R_GPT6_BASE)
19384  #define R_GPT7            ((R_GPT0_Type *) R_GPT7_BASE)
19385  #define R_GPT8            ((R_GPT0_Type *) R_GPT8_BASE)
19386  #define R_GPT9            ((R_GPT0_Type *) R_GPT9_BASE)
19387  #define R_GPT10           ((R_GPT0_Type *) R_GPT10_BASE)
19388  #define R_GPT11           ((R_GPT0_Type *) R_GPT11_BASE)
19389  #define R_GPT12           ((R_GPT0_Type *) R_GPT12_BASE)
19390  #define R_GPT13           ((R_GPT0_Type *) R_GPT13_BASE)
19391  #define R_GPT_OPS         ((R_GPT_OPS_Type *) R_GPT_OPS_BASE)
19392  #define R_GPT_POEG0       ((R_GPT_POEG0_Type *) R_GPT_POEG0_BASE)
19393  #define R_GPT_POEG1       ((R_GPT_POEG0_Type *) R_GPT_POEG1_BASE)
19394  #define R_GPT_POEG2       ((R_GPT_POEG0_Type *) R_GPT_POEG2_BASE)
19395  #define R_GPT_POEG3       ((R_GPT_POEG0_Type *) R_GPT_POEG3_BASE)
19396  #define R_ICU             ((R_ICU_Type *) R_ICU_BASE)
19397  #define R_IIC0            ((R_IIC0_Type *) R_IIC0_BASE)
19398  #define R_IIC1            ((R_IIC0_Type *) R_IIC1_BASE)
19399  #define R_IIC2            ((R_IIC0_Type *) R_IIC2_BASE)
19400  #define R_IWDT            ((R_IWDT_Type *) R_IWDT_BASE)
19401  #define R_I3C0            ((R_I3C0_Type *) R_I3C0_BASE)
19402  #define R_I3C1            ((R_I3C0_Type *) R_I3C1_BASE)
19403  #define R_MPU_MMPU        ((R_MPU_MMPU_Type *) R_MPU_MMPU_BASE)
19404  #define R_MPU_SPMON       ((R_MPU_SPMON_Type *) R_MPU_SPMON_BASE)
19405  #define R_MSTP            ((R_MSTP_Type *) R_MSTP_BASE)
19406  #define R_PORT0           ((R_PORT0_Type *) R_PORT0_BASE)
19407  #define R_PORT1           ((R_PORT0_Type *) R_PORT1_BASE)
19408  #define R_PORT2           ((R_PORT0_Type *) R_PORT2_BASE)
19409  #define R_PORT3           ((R_PORT0_Type *) R_PORT3_BASE)
19410  #define R_PORT4           ((R_PORT0_Type *) R_PORT4_BASE)
19411  #define R_PORT5           ((R_PORT0_Type *) R_PORT5_BASE)
19412  #define R_PORT6           ((R_PORT0_Type *) R_PORT6_BASE)
19413  #define R_PORT7           ((R_PORT0_Type *) R_PORT7_BASE)
19414  #define R_PORT8           ((R_PORT0_Type *) R_PORT8_BASE)
19415  #define R_PORT9           ((R_PORT0_Type *) R_PORT9_BASE)
19416  #define R_PORT10          ((R_PORT0_Type *) R_PORT10_BASE)
19417  #define R_PORT11          ((R_PORT0_Type *) R_PORT11_BASE)
19418  #define R_PORT12          ((R_PORT0_Type *) R_PORT12_BASE)
19419  #define R_PORT13          ((R_PORT0_Type *) R_PORT13_BASE)
19420  #define R_PORT14          ((R_PORT0_Type *) R_PORT14_BASE)
19421  #define R_PFS             ((R_PFS_Type *) R_PFS_BASE)
19422  #define R_PMISC           ((R_PMISC_Type *) R_PMISC_BASE)
19423  #define R_QSPI            ((R_QSPI_Type *) R_QSPI_BASE)
19424  #define R_RTC             ((R_RTC_Type *) R_RTC_BASE)
19425  #define R_SCI0            ((R_SCI0_Type *) R_SCI0_BASE)
19426  #define R_SCI1            ((R_SCI0_Type *) R_SCI1_BASE)
19427  #define R_SCI2            ((R_SCI0_Type *) R_SCI2_BASE)
19428  #define R_SCI3            ((R_SCI0_Type *) R_SCI3_BASE)
19429  #define R_SCI4            ((R_SCI0_Type *) R_SCI4_BASE)
19430  #define R_SCI5            ((R_SCI0_Type *) R_SCI5_BASE)
19431  #define R_SCI6            ((R_SCI0_Type *) R_SCI6_BASE)
19432  #define R_SCI7            ((R_SCI0_Type *) R_SCI7_BASE)
19433  #define R_SCI8            ((R_SCI0_Type *) R_SCI8_BASE)
19434  #define R_SCI9            ((R_SCI0_Type *) R_SCI9_BASE)
19435  #define R_SDHI0           ((R_SDHI0_Type *) R_SDHI0_BASE)
19436  #define R_SDHI1           ((R_SDHI0_Type *) R_SDHI1_BASE)
19437  #define R_SPI0            ((R_SPI0_Type *) R_SPI0_BASE)
19438  #define R_SPI1            ((R_SPI0_Type *) R_SPI1_BASE)
19439  #define R_SRAM            ((R_SRAM_Type *) R_SRAM_BASE)
19440  #define R_SSI0            ((R_SSI0_Type *) R_SSI0_BASE)
19441  #define R_SSI1            ((R_SSI0_Type *) R_SSI1_BASE)
19442  #define R_SYSTEM          ((R_SYSTEM_Type *) R_SYSTEM_BASE)
19443  #define R_TSN_CAL         ((R_TSN_CAL_Type *) R_TSN_CAL_BASE)
19444  #define R_TSN_CTRL        ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE)
19445  #define R_USB_FS0         ((R_USB_FS0_Type *) R_USB_FS0_BASE)
19446  #define R_WDT             ((R_WDT_Type *) R_WDT_BASE)
19447  #define R_TZF             ((R_TZF_Type *) R_TZF_BASE)
19448  #define R_CACHE           ((R_CACHE_Type *) R_CACHE_BASE)
19449  #define R_CPSCU           ((R_CPSCU_Type *) R_CPSCU_BASE)
19450  #define R_CEC             ((R_CEC_Type *) R_CEC_BASE)
19451  #define R_OSPI            ((R_OSPI_Type *) R_OSPI_BASE)
19452  #define R_USB_HS0         ((R_USB_HS0_Type *) R_USB_HS0_BASE)
19453  #define R_AGT0            ((R_AGTX0_Type *) R_AGTX0_BASE)
19454  #define R_AGT1            ((R_AGTX0_Type *) R_AGTX1_BASE)
19455  #define R_AGT2            ((R_AGTX0_Type *) R_AGTX2_BASE)
19456  #define R_AGT3            ((R_AGTX0_Type *) R_AGTX3_BASE)
19457  #define R_AGT4            ((R_AGTX0_Type *) R_AGTX4_BASE)
19458  #define R_AGT5            ((R_AGTX0_Type *) R_AGTX5_BASE)
19459  #define R_AGT6            ((R_AGTX0_Type *) R_AGTX6_BASE)
19460  #define R_AGT7            ((R_AGTX0_Type *) R_AGTX7_BASE)
19461  #define R_AGT8            ((R_AGTX0_Type *) R_AGTX8_BASE)
19462  #define R_AGT9            ((R_AGTX0_Type *) R_AGTX9_BASE)
19463  #define R_FLAD            ((R_FLAD_Type *) R_FLAD_BASE)
19464 
19465 /** @} */ /* End of group Device_Peripheral_declaration */
19466 
19467 /* =========================================  End of section using anonymous unions  ========================================= */
19468  #if defined(__CC_ARM)
19469   #pragma pop
19470  #elif defined(__ICCARM__)
19471 
19472 /* leave anonymous unions enabled */
19473  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
19474   #pragma clang diagnostic pop
19475  #elif defined(__GNUC__)
19476 
19477 /* anonymous unions are enabled by default */
19478  #elif defined(__TMS470__)
19479 
19480 /* anonymous unions are enabled by default */
19481  #elif defined(__TASKING__)
19482   #pragma warning restore
19483  #elif defined(__CSMC__)
19484 
19485 /* anonymous unions are enabled by default */
19486  #endif
19487 
19488 /* =========================================================================================================================== */
19489 /* ================                                 Pos/Mask Cluster Section                                  ================ */
19490 /* =========================================================================================================================== */
19491 
19492 /** @addtogroup PosMask_clusters
19493  * @{
19494  */
19495 
19496 /* =========================================================================================================================== */
19497 /* ================                                            CSa                                            ================ */
19498 /* =========================================================================================================================== */
19499 
19500 /* ==========================================================  MOD  ========================================================== */
19501  #define R_BUS_CSa_MOD_PRMOD_Pos        (15UL)         /*!< PRMOD (Bit 15)                                        */
19502  #define R_BUS_CSa_MOD_PRMOD_Msk        (0x8000UL)     /*!< PRMOD (Bitfield-Mask: 0x01)                           */
19503  #define R_BUS_CSa_MOD_PWENB_Pos        (9UL)          /*!< PWENB (Bit 9)                                         */
19504  #define R_BUS_CSa_MOD_PWENB_Msk        (0x200UL)      /*!< PWENB (Bitfield-Mask: 0x01)                           */
19505  #define R_BUS_CSa_MOD_PRENB_Pos        (8UL)          /*!< PRENB (Bit 8)                                         */
19506  #define R_BUS_CSa_MOD_PRENB_Msk        (0x100UL)      /*!< PRENB (Bitfield-Mask: 0x01)                           */
19507  #define R_BUS_CSa_MOD_EWENB_Pos        (3UL)          /*!< EWENB (Bit 3)                                         */
19508  #define R_BUS_CSa_MOD_EWENB_Msk        (0x8UL)        /*!< EWENB (Bitfield-Mask: 0x01)                           */
19509  #define R_BUS_CSa_MOD_WRMOD_Pos        (0UL)          /*!< WRMOD (Bit 0)                                         */
19510  #define R_BUS_CSa_MOD_WRMOD_Msk        (0x1UL)        /*!< WRMOD (Bitfield-Mask: 0x01)                           */
19511 /* =========================================================  WCR1  ========================================================== */
19512  #define R_BUS_CSa_WCR1_CSRWAIT_Pos     (24UL)         /*!< CSRWAIT (Bit 24)                                      */
19513  #define R_BUS_CSa_WCR1_CSRWAIT_Msk     (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f)                         */
19514  #define R_BUS_CSa_WCR1_CSWWAIT_Pos     (16UL)         /*!< CSWWAIT (Bit 16)                                      */
19515  #define R_BUS_CSa_WCR1_CSWWAIT_Msk     (0x1f0000UL)   /*!< CSWWAIT (Bitfield-Mask: 0x1f)                         */
19516  #define R_BUS_CSa_WCR1_CSPRWAIT_Pos    (8UL)          /*!< CSPRWAIT (Bit 8)                                      */
19517  #define R_BUS_CSa_WCR1_CSPRWAIT_Msk    (0x700UL)      /*!< CSPRWAIT (Bitfield-Mask: 0x07)                        */
19518  #define R_BUS_CSa_WCR1_CSPWWAIT_Pos    (0UL)          /*!< CSPWWAIT (Bit 0)                                      */
19519  #define R_BUS_CSa_WCR1_CSPWWAIT_Msk    (0x7UL)        /*!< CSPWWAIT (Bitfield-Mask: 0x07)                        */
19520 /* =========================================================  WCR2  ========================================================== */
19521  #define R_BUS_CSa_WCR2_CSON_Pos        (28UL)         /*!< CSON (Bit 28)                                         */
19522  #define R_BUS_CSa_WCR2_CSON_Msk        (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07)                            */
19523  #define R_BUS_CSa_WCR2_WDON_Pos        (24UL)         /*!< WDON (Bit 24)                                         */
19524  #define R_BUS_CSa_WCR2_WDON_Msk        (0x7000000UL)  /*!< WDON (Bitfield-Mask: 0x07)                            */
19525  #define R_BUS_CSa_WCR2_WRON_Pos        (20UL)         /*!< WRON (Bit 20)                                         */
19526  #define R_BUS_CSa_WCR2_WRON_Msk        (0x700000UL)   /*!< WRON (Bitfield-Mask: 0x07)                            */
19527  #define R_BUS_CSa_WCR2_RDON_Pos        (16UL)         /*!< RDON (Bit 16)                                         */
19528  #define R_BUS_CSa_WCR2_RDON_Msk        (0x70000UL)    /*!< RDON (Bitfield-Mask: 0x07)                            */
19529  #define R_BUS_CSa_WCR2_AWAIT_Pos       (12UL)         /*!< AWAIT (Bit 12)                                        */
19530  #define R_BUS_CSa_WCR2_AWAIT_Msk       (0x3000UL)     /*!< AWAIT (Bitfield-Mask: 0x03)                           */
19531  #define R_BUS_CSa_WCR2_WDOFF_Pos       (8UL)          /*!< WDOFF (Bit 8)                                         */
19532  #define R_BUS_CSa_WCR2_WDOFF_Msk       (0x700UL)      /*!< WDOFF (Bitfield-Mask: 0x07)                           */
19533  #define R_BUS_CSa_WCR2_CSWOFF_Pos      (4UL)          /*!< CSWOFF (Bit 4)                                        */
19534  #define R_BUS_CSa_WCR2_CSWOFF_Msk      (0x70UL)       /*!< CSWOFF (Bitfield-Mask: 0x07)                          */
19535  #define R_BUS_CSa_WCR2_CSROFF_Pos      (0UL)          /*!< CSROFF (Bit 0)                                        */
19536  #define R_BUS_CSa_WCR2_CSROFF_Msk      (0x7UL)        /*!< CSROFF (Bitfield-Mask: 0x07)                          */
19537 
19538 /* =========================================================================================================================== */
19539 /* ================                                            CSb                                            ================ */
19540 /* =========================================================================================================================== */
19541 
19542 /* ==========================================================  CR  =========================================================== */
19543  #define R_BUS_CSb_CR_MPXEN_Pos    (12UL)     /*!< MPXEN (Bit 12)                                        */
19544  #define R_BUS_CSb_CR_MPXEN_Msk    (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01)                           */
19545  #define R_BUS_CSb_CR_EMODE_Pos    (8UL)      /*!< EMODE (Bit 8)                                         */
19546  #define R_BUS_CSb_CR_EMODE_Msk    (0x100UL)  /*!< EMODE (Bitfield-Mask: 0x01)                           */
19547  #define R_BUS_CSb_CR_BSIZE_Pos    (4UL)      /*!< BSIZE (Bit 4)                                         */
19548  #define R_BUS_CSb_CR_BSIZE_Msk    (0x30UL)   /*!< BSIZE (Bitfield-Mask: 0x03)                           */
19549  #define R_BUS_CSb_CR_EXENB_Pos    (0UL)      /*!< EXENB (Bit 0)                                         */
19550  #define R_BUS_CSb_CR_EXENB_Msk    (0x1UL)    /*!< EXENB (Bitfield-Mask: 0x01)                           */
19551 /* ==========================================================  REC  ========================================================== */
19552  #define R_BUS_CSb_REC_WRCV_Pos    (8UL)      /*!< WRCV (Bit 8)                                          */
19553  #define R_BUS_CSb_REC_WRCV_Msk    (0xf00UL)  /*!< WRCV (Bitfield-Mask: 0x0f)                            */
19554  #define R_BUS_CSb_REC_RRCV_Pos    (0UL)      /*!< RRCV (Bit 0)                                          */
19555  #define R_BUS_CSb_REC_RRCV_Msk    (0xfUL)    /*!< RRCV (Bitfield-Mask: 0x0f)                            */
19556 
19557 /* =========================================================================================================================== */
19558 /* ================                                           SDRAM                                           ================ */
19559 /* =========================================================================================================================== */
19560 
19561 /* =========================================================  SDCCR  ========================================================= */
19562  #define R_BUS_SDRAM_SDCCR_BSIZE_Pos     (4UL)       /*!< BSIZE (Bit 4)                                         */
19563  #define R_BUS_SDRAM_SDCCR_BSIZE_Msk     (0x30UL)    /*!< BSIZE (Bitfield-Mask: 0x03)                           */
19564  #define R_BUS_SDRAM_SDCCR_EXENB_Pos     (0UL)       /*!< EXENB (Bit 0)                                         */
19565  #define R_BUS_SDRAM_SDCCR_EXENB_Msk     (0x1UL)     /*!< EXENB (Bitfield-Mask: 0x01)                           */
19566 /* ========================================================  SDCMOD  ========================================================= */
19567  #define R_BUS_SDRAM_SDCMOD_EMODE_Pos    (0UL)       /*!< EMODE (Bit 0)                                         */
19568  #define R_BUS_SDRAM_SDCMOD_EMODE_Msk    (0x1UL)     /*!< EMODE (Bitfield-Mask: 0x01)                           */
19569 /* ========================================================  SDAMOD  ========================================================= */
19570  #define R_BUS_SDRAM_SDAMOD_BE_Pos       (0UL)       /*!< BE (Bit 0)                                            */
19571  #define R_BUS_SDRAM_SDAMOD_BE_Msk       (0x1UL)     /*!< BE (Bitfield-Mask: 0x01)                              */
19572 /* ========================================================  SDSELF  ========================================================= */
19573  #define R_BUS_SDRAM_SDSELF_SFEN_Pos     (0UL)       /*!< SFEN (Bit 0)                                          */
19574  #define R_BUS_SDRAM_SDSELF_SFEN_Msk     (0x1UL)     /*!< SFEN (Bitfield-Mask: 0x01)                            */
19575 /* ========================================================  SDRFCR  ========================================================= */
19576  #define R_BUS_SDRAM_SDRFCR_REFW_Pos     (12UL)      /*!< REFW (Bit 12)                                         */
19577  #define R_BUS_SDRAM_SDRFCR_REFW_Msk     (0xf000UL)  /*!< REFW (Bitfield-Mask: 0x0f)                            */
19578  #define R_BUS_SDRAM_SDRFCR_RFC_Pos      (0UL)       /*!< RFC (Bit 0)                                           */
19579  #define R_BUS_SDRAM_SDRFCR_RFC_Msk      (0xfffUL)   /*!< RFC (Bitfield-Mask: 0xfff)                            */
19580 /* ========================================================  SDRFEN  ========================================================= */
19581  #define R_BUS_SDRAM_SDRFEN_RFEN_Pos     (0UL)       /*!< RFEN (Bit 0)                                          */
19582  #define R_BUS_SDRAM_SDRFEN_RFEN_Msk     (0x1UL)     /*!< RFEN (Bitfield-Mask: 0x01)                            */
19583 /* =========================================================  SDICR  ========================================================= */
19584  #define R_BUS_SDRAM_SDICR_INIRQ_Pos     (0UL)       /*!< INIRQ (Bit 0)                                         */
19585  #define R_BUS_SDRAM_SDICR_INIRQ_Msk     (0x1UL)     /*!< INIRQ (Bitfield-Mask: 0x01)                           */
19586 /* =========================================================  SDIR  ========================================================== */
19587  #define R_BUS_SDRAM_SDIR_PRC_Pos        (8UL)       /*!< PRC (Bit 8)                                           */
19588  #define R_BUS_SDRAM_SDIR_PRC_Msk        (0x700UL)   /*!< PRC (Bitfield-Mask: 0x07)                             */
19589  #define R_BUS_SDRAM_SDIR_ARFC_Pos       (4UL)       /*!< ARFC (Bit 4)                                          */
19590  #define R_BUS_SDRAM_SDIR_ARFC_Msk       (0xf0UL)    /*!< ARFC (Bitfield-Mask: 0x0f)                            */
19591  #define R_BUS_SDRAM_SDIR_ARFI_Pos       (0UL)       /*!< ARFI (Bit 0)                                          */
19592  #define R_BUS_SDRAM_SDIR_ARFI_Msk       (0xfUL)     /*!< ARFI (Bitfield-Mask: 0x0f)                            */
19593 /* =========================================================  SDADR  ========================================================= */
19594  #define R_BUS_SDRAM_SDADR_MXC_Pos       (0UL)       /*!< MXC (Bit 0)                                           */
19595  #define R_BUS_SDRAM_SDADR_MXC_Msk       (0x3UL)     /*!< MXC (Bitfield-Mask: 0x03)                             */
19596 /* =========================================================  SDTR  ========================================================== */
19597  #define R_BUS_SDRAM_SDTR_RAS_Pos        (16UL)      /*!< RAS (Bit 16)                                          */
19598  #define R_BUS_SDRAM_SDTR_RAS_Msk        (0x70000UL) /*!< RAS (Bitfield-Mask: 0x07)                             */
19599  #define R_BUS_SDRAM_SDTR_RCD_Pos        (12UL)      /*!< RCD (Bit 12)                                          */
19600  #define R_BUS_SDRAM_SDTR_RCD_Msk        (0x3000UL)  /*!< RCD (Bitfield-Mask: 0x03)                             */
19601  #define R_BUS_SDRAM_SDTR_RP_Pos         (9UL)       /*!< RP (Bit 9)                                            */
19602  #define R_BUS_SDRAM_SDTR_RP_Msk         (0xe00UL)   /*!< RP (Bitfield-Mask: 0x07)                              */
19603  #define R_BUS_SDRAM_SDTR_WR_Pos         (8UL)       /*!< WR (Bit 8)                                            */
19604  #define R_BUS_SDRAM_SDTR_WR_Msk         (0x100UL)   /*!< WR (Bitfield-Mask: 0x01)                              */
19605  #define R_BUS_SDRAM_SDTR_CL_Pos         (0UL)       /*!< CL (Bit 0)                                            */
19606  #define R_BUS_SDRAM_SDTR_CL_Msk         (0x7UL)     /*!< CL (Bitfield-Mask: 0x07)                              */
19607 /* =========================================================  SDMOD  ========================================================= */
19608  #define R_BUS_SDRAM_SDMOD_MR_Pos        (0UL)       /*!< MR (Bit 0)                                            */
19609  #define R_BUS_SDRAM_SDMOD_MR_Msk        (0x7fffUL)  /*!< MR (Bitfield-Mask: 0x7fff)                            */
19610 /* =========================================================  SDSR  ========================================================== */
19611  #define R_BUS_SDRAM_SDSR_SRFST_Pos      (4UL)       /*!< SRFST (Bit 4)                                         */
19612  #define R_BUS_SDRAM_SDSR_SRFST_Msk      (0x10UL)    /*!< SRFST (Bitfield-Mask: 0x01)                           */
19613  #define R_BUS_SDRAM_SDSR_INIST_Pos      (3UL)       /*!< INIST (Bit 3)                                         */
19614  #define R_BUS_SDRAM_SDSR_INIST_Msk      (0x8UL)     /*!< INIST (Bitfield-Mask: 0x01)                           */
19615  #define R_BUS_SDRAM_SDSR_MRSST_Pos      (0UL)       /*!< MRSST (Bit 0)                                         */
19616  #define R_BUS_SDRAM_SDSR_MRSST_Msk      (0x1UL)     /*!< MRSST (Bitfield-Mask: 0x01)                           */
19617 
19618 /* =========================================================================================================================== */
19619 /* ================                                          BUSERRa                                          ================ */
19620 /* =========================================================================================================================== */
19621 
19622 /* ==========================================================  ADD  ========================================================== */
19623  #define R_BUS_BUSERRa_ADD_BERAD_Pos       (0UL)          /*!< BERAD (Bit 0)                                         */
19624  #define R_BUS_BUSERRa_ADD_BERAD_Msk       (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff)                     */
19625 /* =========================================================  STAT  ========================================================== */
19626  #define R_BUS_BUSERRa_STAT_ERRSTAT_Pos    (7UL)          /*!< ERRSTAT (Bit 7)                                       */
19627  #define R_BUS_BUSERRa_STAT_ERRSTAT_Msk    (0x80UL)       /*!< ERRSTAT (Bitfield-Mask: 0x01)                         */
19628  #define R_BUS_BUSERRa_STAT_ACCSTAT_Pos    (0UL)          /*!< ACCSTAT (Bit 0)                                       */
19629  #define R_BUS_BUSERRa_STAT_ACCSTAT_Msk    (0x1UL)        /*!< ACCSTAT (Bitfield-Mask: 0x01)                         */
19630 /* ==========================================================  RW  =========================================================== */
19631  #define R_BUS_BUSERRa_RW_RWSTAT_Pos       (0UL)          /*!< RWSTAT (Bit 0)                                        */
19632  #define R_BUS_BUSERRa_RW_RWSTAT_Msk       (0x1UL)        /*!< RWSTAT (Bitfield-Mask: 0x01)                          */
19633 
19634 /* =========================================================================================================================== */
19635 /* ================                                          BTZFERR                                          ================ */
19636 /* =========================================================================================================================== */
19637 
19638 /* ==========================================================  ADD  ========================================================== */
19639  #define R_BUS_BTZFERR_ADD_BTZFERAD_Pos    (0UL)          /*!< BTZFERAD (Bit 0)                                      */
19640  #define R_BUS_BTZFERR_ADD_BTZFERAD_Msk    (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff)                  */
19641 /* ==========================================================  RW  =========================================================== */
19642  #define R_BUS_BTZFERR_RW_TRWSTAT_Pos      (0UL)          /*!< TRWSTAT (Bit 0)                                       */
19643  #define R_BUS_BTZFERR_RW_TRWSTAT_Msk      (0x1UL)        /*!< TRWSTAT (Bitfield-Mask: 0x01)                         */
19644 
19645 /* =========================================================================================================================== */
19646 /* ================                                          BUSERRb                                          ================ */
19647 /* =========================================================================================================================== */
19648 
19649 /* =========================================================  STAT  ========================================================== */
19650  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Pos    (5UL)    /*!< MSERRSTAT (Bit 5)                                     */
19651  #define R_BUS_BUSERRb_STAT_MSERRSTAT_Msk    (0x20UL) /*!< MSERRSTAT (Bitfield-Mask: 0x01)                       */
19652  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Pos    (4UL)    /*!< ILERRSTAT (Bit 4)                                     */
19653  #define R_BUS_BUSERRb_STAT_ILERRSTAT_Msk    (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01)                       */
19654  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Pos    (3UL)    /*!< MMERRSTAT (Bit 3)                                     */
19655  #define R_BUS_BUSERRb_STAT_MMERRSTAT_Msk    (0x8UL)  /*!< MMERRSTAT (Bitfield-Mask: 0x01)                       */
19656  #define R_BUS_BUSERRb_STAT_STERRSTAT_Pos    (1UL)    /*!< STERRSTAT (Bit 1)                                     */
19657  #define R_BUS_BUSERRb_STAT_STERRSTAT_Msk    (0x2UL)  /*!< STERRSTAT (Bitfield-Mask: 0x01)                       */
19658  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Pos    (0UL)    /*!< SLERRSTAT (Bit 0)                                     */
19659  #define R_BUS_BUSERRb_STAT_SLERRSTAT_Msk    (0x1UL)  /*!< SLERRSTAT (Bitfield-Mask: 0x01)                       */
19660 /* ==========================================================  CLR  ========================================================== */
19661  #define R_BUS_BUSERRb_CLR_MSERRCLR_Pos      (5UL)    /*!< MSERRCLR (Bit 5)                                      */
19662  #define R_BUS_BUSERRb_CLR_MSERRCLR_Msk      (0x20UL) /*!< MSERRCLR (Bitfield-Mask: 0x01)                        */
19663  #define R_BUS_BUSERRb_CLR_ILERRCLR_Pos      (4UL)    /*!< ILERRCLR (Bit 4)                                      */
19664  #define R_BUS_BUSERRb_CLR_ILERRCLR_Msk      (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01)                        */
19665  #define R_BUS_BUSERRb_CLR_MMERRCLR_Pos      (3UL)    /*!< MMERRCLR (Bit 3)                                      */
19666  #define R_BUS_BUSERRb_CLR_MMERRCLR_Msk      (0x8UL)  /*!< MMERRCLR (Bitfield-Mask: 0x01)                        */
19667  #define R_BUS_BUSERRb_CLR_STERRCLR_Pos      (1UL)    /*!< STERRCLR (Bit 1)                                      */
19668  #define R_BUS_BUSERRb_CLR_STERRCLR_Msk      (0x2UL)  /*!< STERRCLR (Bitfield-Mask: 0x01)                        */
19669  #define R_BUS_BUSERRb_CLR_SLERRCLR_Pos      (0UL)    /*!< SLERRCLR (Bit 0)                                      */
19670  #define R_BUS_BUSERRb_CLR_SLERRCLR_Msk      (0x1UL)  /*!< SLERRCLR (Bitfield-Mask: 0x01)                        */
19671 
19672 /* =========================================================================================================================== */
19673 /* ================                                        DMACDTCERR                                         ================ */
19674 /* =========================================================================================================================== */
19675 
19676 /* =========================================================  STAT  ========================================================== */
19677  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Pos    (0UL)   /*!< MTERRSTAT (Bit 0)                                     */
19678  #define R_BUS_DMACDTCERR_STAT_MTERRSTAT_Msk    (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01)                       */
19679 /* ==========================================================  CLR  ========================================================== */
19680  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Pos      (0UL)   /*!< MTERRCLR (Bit 0)                                      */
19681  #define R_BUS_DMACDTCERR_CLR_MTERRCLR_Msk      (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01)                        */
19682 
19683 /* =========================================================================================================================== */
19684 /* ================                                         BUSSABT0                                          ================ */
19685 /* =========================================================================================================================== */
19686 
19687 /* =========================================================  FLBI  ========================================================== */
19688  #define R_BUS_BUSSABT0_FLBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19689  #define R_BUS_BUSSABT0_FLBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19690 /* ========================================================  MRE0BI  ========================================================= */
19691  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
19692  #define R_BUS_BUSSABT0_MRE0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19693 /* =========================================================  S0BI  ========================================================== */
19694  #define R_BUS_BUSSABT0_S0BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19695  #define R_BUS_BUSSABT0_S0BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19696 /* =========================================================  S1BI  ========================================================== */
19697  #define R_BUS_BUSSABT0_S1BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19698  #define R_BUS_BUSSABT0_S1BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19699 /* =========================================================  S2BI  ========================================================== */
19700  #define R_BUS_BUSSABT0_S2BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19701  #define R_BUS_BUSSABT0_S2BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19702 /* =========================================================  S3BI  ========================================================== */
19703  #define R_BUS_BUSSABT0_S3BI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19704  #define R_BUS_BUSSABT0_S3BI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19705 /* ========================================================  STBYSBI  ======================================================== */
19706  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
19707  #define R_BUS_BUSSABT0_STBYSBI_ARBS_Msk      (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19708 /* =========================================================  ECBI  ========================================================== */
19709  #define R_BUS_BUSSABT0_ECBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19710  #define R_BUS_BUSSABT0_ECBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19711 /* =========================================================  EOBI  ========================================================== */
19712  #define R_BUS_BUSSABT0_EOBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19713  #define R_BUS_BUSSABT0_EOBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19714 /* ========================================================  SPI0BI  ========================================================= */
19715  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
19716  #define R_BUS_BUSSABT0_SPI0BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19717 /* ========================================================  SPI1BI  ========================================================= */
19718  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Pos       (0UL)   /*!< ARBS (Bit 0)                                          */
19719  #define R_BUS_BUSSABT0_SPI1BI_ARBS_Msk       (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19720 /* =========================================================  PBBI  ========================================================== */
19721  #define R_BUS_BUSSABT0_PBBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19722  #define R_BUS_BUSSABT0_PBBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19723 /* =========================================================  PABI  ========================================================== */
19724  #define R_BUS_BUSSABT0_PABI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19725  #define R_BUS_BUSSABT0_PABI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19726 /* =========================================================  PIBI  ========================================================== */
19727  #define R_BUS_BUSSABT0_PIBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19728  #define R_BUS_BUSSABT0_PIBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19729 /* =========================================================  PSBI  ========================================================== */
19730  #define R_BUS_BUSSABT0_PSBI_ARBS_Pos         (0UL)   /*!< ARBS (Bit 0)                                          */
19731  #define R_BUS_BUSSABT0_PSBI_ARBS_Msk         (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19732 /* =======================================================  CPU0SAHBI  ======================================================= */
19733  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
19734  #define R_BUS_BUSSABT0_CPU0SAHBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19735 /* =======================================================  CPU1TCMBI  ======================================================= */
19736  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
19737  #define R_BUS_BUSSABT0_CPU1TCMBI_ARBS_Msk    (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01)                            */
19738 
19739 /* =========================================================================================================================== */
19740 /* ================                                         BUSSABT1                                          ================ */
19741 /* =========================================================================================================================== */
19742 
19743 /* =========================================================  FHBI  ========================================================== */
19744  #define R_BUS_BUSSABT1_FHBI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
19745  #define R_BUS_BUSSABT1_FHBI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
19746 /* ========================================================  MRC0BI  ========================================================= */
19747  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Pos    (0UL)   /*!< ARBS (Bit 0)                                          */
19748  #define R_BUS_BUSSABT1_MRC0BI_ARBS_Msk    (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
19749 /* =========================================================  S0BI  ========================================================== */
19750  #define R_BUS_BUSSABT1_S0BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
19751  #define R_BUS_BUSSABT1_S0BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
19752 /* =========================================================  S1BI  ========================================================== */
19753  #define R_BUS_BUSSABT1_S1BI_ARBS_Pos      (0UL)   /*!< ARBS (Bit 0)                                          */
19754  #define R_BUS_BUSSABT1_S1BI_ARBS_Msk      (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03)                            */
19755 
19756 /* =========================================================================================================================== */
19757 /* ================                                          BMSAERR                                          ================ */
19758 /* =========================================================================================================================== */
19759 
19760 /* ==========================================================  ADD  ========================================================== */
19761  #define R_BUS_BMSAERR_ADD_MSERAD_Pos      (0UL)          /*!< MSERAD (Bit 0)                                        */
19762  #define R_BUS_BMSAERR_ADD_MSERAD_Msk      (0xffffffffUL) /*!< MSERAD (Bitfield-Mask: 0xffffffff)                    */
19763 /* ==========================================================  RW  =========================================================== */
19764  #define R_BUS_BMSAERR_RW_MSARWSTAT_Pos    (0UL)          /*!< MSARWSTAT (Bit 0)                                     */
19765  #define R_BUS_BMSAERR_RW_MSARWSTAT_Msk    (0x1UL)        /*!< MSARWSTAT (Bitfield-Mask: 0x01)                       */
19766 
19767 /* =========================================================================================================================== */
19768 /* ================                                            OAD                                            ================ */
19769 /* =========================================================================================================================== */
19770 
19771 /* ========================================================  BUSOAD  ========================================================= */
19772  #define R_BUS_OAD_BUSOAD_BWERROAD_Pos     (2UL)      /*!< BWERROAD (Bit 2)                                      */
19773  #define R_BUS_OAD_BUSOAD_BWERROAD_Msk     (0x4UL)    /*!< BWERROAD (Bitfield-Mask: 0x01)                        */
19774  #define R_BUS_OAD_BUSOAD_SLERROAD_Pos     (1UL)      /*!< SLERROAD (Bit 1)                                      */
19775  #define R_BUS_OAD_BUSOAD_SLERROAD_Msk     (0x2UL)    /*!< SLERROAD (Bitfield-Mask: 0x01)                        */
19776  #define R_BUS_OAD_BUSOAD_ILERROAD_Pos     (0UL)      /*!< ILERROAD (Bit 0)                                      */
19777  #define R_BUS_OAD_BUSOAD_ILERROAD_Msk     (0x1UL)    /*!< ILERROAD (Bitfield-Mask: 0x01)                        */
19778 /* =======================================================  BUSOADPT  ======================================================== */
19779  #define R_BUS_OAD_BUSOADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
19780  #define R_BUS_OAD_BUSOADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
19781  #define R_BUS_OAD_BUSOADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
19782  #define R_BUS_OAD_BUSOADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
19783 /* ========================================================  MSAOAD  ========================================================= */
19784  #define R_BUS_OAD_MSAOAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
19785  #define R_BUS_OAD_MSAOAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
19786  #define R_BUS_OAD_MSAOAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
19787  #define R_BUS_OAD_MSAOAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
19788 /* =========================================================  MSAPT  ========================================================= */
19789  #define R_BUS_OAD_MSAPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
19790  #define R_BUS_OAD_MSAPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
19791  #define R_BUS_OAD_MSAPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
19792  #define R_BUS_OAD_MSAPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
19793 
19794 /* =========================================================================================================================== */
19795 /* ================                                          MBWERR                                           ================ */
19796 /* =========================================================================================================================== */
19797 
19798 /* =========================================================  STAT  ========================================================== */
19799  #define R_BUS_MBWERR_STAT_BWERR_Pos    (0UL)   /*!< BWERR (Bit 0)                                         */
19800  #define R_BUS_MBWERR_STAT_BWERR_Msk    (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
19801 /* ==========================================================  CLR  ========================================================== */
19802  #define R_BUS_MBWERR_CLR_BWERR_Pos     (0UL)   /*!< BWERR (Bit 0)                                         */
19803  #define R_BUS_MBWERR_CLR_BWERR_Msk     (0x1UL) /*!< BWERR (Bitfield-Mask: 0x01)                           */
19804 
19805 /* =========================================================================================================================== */
19806 /* ================                                           BUSM                                            ================ */
19807 /* =========================================================================================================================== */
19808 
19809 /* ==========================================================  CNT  ========================================================== */
19810  #define R_BUS_BUSM_CNT_IERES_Pos    (15UL)     /*!< IERES (Bit 15)                                        */
19811  #define R_BUS_BUSM_CNT_IERES_Msk    (0x8000UL) /*!< IERES (Bitfield-Mask: 0x01)                           */
19812 
19813 /* =========================================================================================================================== */
19814 /* ================                                           BUSS                                            ================ */
19815 /* =========================================================================================================================== */
19816 
19817 /* ==========================================================  CNT  ========================================================== */
19818  #define R_BUS_BUSS_CNT_ARBMET_Pos    (4UL)    /*!< ARBMET (Bit 4)                                        */
19819  #define R_BUS_BUSS_CNT_ARBMET_Msk    (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03)                          */
19820  #define R_BUS_BUSS_CNT_ARBS_Pos      (0UL)    /*!< ARBS (Bit 0)                                          */
19821  #define R_BUS_BUSS_CNT_ARBS_Msk      (0x3UL)  /*!< ARBS (Bitfield-Mask: 0x03)                            */
19822 
19823 /* =========================================================================================================================== */
19824 /* ================                                           CFDC                                            ================ */
19825 /* =========================================================================================================================== */
19826 
19827 /* =========================================================  NCFG  ========================================================== */
19828  #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
19829  #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
19830  #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
19831  #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
19832  #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
19833  #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
19834  #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
19835  #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
19836 /* ==========================================================  CTR  ========================================================== */
19837  #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
19838  #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
19839  #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
19840  #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
19841  #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
19842  #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
19843  #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
19844  #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
19845  #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
19846  #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
19847  #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
19848  #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
19849  #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
19850  #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
19851  #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
19852  #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
19853  #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
19854  #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
19855  #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
19856  #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
19857  #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
19858  #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
19859  #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
19860  #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
19861  #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
19862  #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
19863  #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
19864  #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
19865  #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
19866  #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
19867  #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
19868  #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
19869  #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
19870  #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
19871  #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
19872  #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
19873  #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
19874  #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
19875  #define R_CANFD_CFDC_CTR_TRWE_Pos       (27UL)         /*!< TRWE (Bit 27)                                         */
19876  #define R_CANFD_CFDC_CTR_TRWE_Msk       (0x8000000UL)  /*!< TRWE (Bitfield-Mask: 0x01)                            */
19877  #define R_CANFD_CFDC_CTR_TRH_Pos        (28UL)         /*!< TRH (Bit 28)                                          */
19878  #define R_CANFD_CFDC_CTR_TRH_Msk        (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01)                             */
19879  #define R_CANFD_CFDC_CTR_TRR_Pos        (29UL)         /*!< TRR (Bit 29)                                          */
19880  #define R_CANFD_CFDC_CTR_TRR_Msk        (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01)                             */
19881  #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
19882  #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
19883  #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
19884  #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
19885 /* ==========================================================  STS  ========================================================== */
19886  #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
19887  #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
19888  #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
19889  #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
19890  #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
19891  #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
19892  #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
19893  #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
19894  #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
19895  #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
19896  #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
19897  #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
19898  #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
19899  #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
19900  #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
19901  #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
19902  #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
19903  #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
19904  #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
19905  #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
19906  #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
19907  #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
19908 /* =========================================================  ERFL  ========================================================== */
19909  #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
19910  #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
19911  #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
19912  #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
19913  #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
19914  #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
19915  #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
19916  #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
19917  #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
19918  #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
19919  #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
19920  #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
19921  #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
19922  #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
19923  #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
19924  #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
19925  #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
19926  #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
19927  #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
19928  #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
19929  #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
19930  #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
19931  #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
19932  #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
19933  #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
19934  #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
19935  #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
19936  #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
19937  #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
19938  #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
19939  #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
19940  #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
19941 
19942 /* =========================================================================================================================== */
19943 /* ================                                           CFDC2                                           ================ */
19944 /* =========================================================================================================================== */
19945 
19946 /* =========================================================  DCFG  ========================================================== */
19947  #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
19948  #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
19949  #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
19950  #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
19951  #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
19952  #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
19953  #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
19954  #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
19955 /* =========================================================  FDCFG  ========================================================= */
19956  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
19957  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
19958  #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
19959  #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
19960  #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
19961  #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
19962  #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
19963  #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
19964  #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
19965  #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
19966  #define R_CANFD_CFDC2_FDCFG_GWEN_Pos      (24UL)         /*!< GWEN (Bit 24)                                         */
19967  #define R_CANFD_CFDC2_FDCFG_GWEN_Msk      (0x1000000UL)  /*!< GWEN (Bitfield-Mask: 0x01)                            */
19968  #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos     (25UL)         /*!< GWFDF (Bit 25)                                        */
19969  #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk     (0x2000000UL)  /*!< GWFDF (Bitfield-Mask: 0x01)                           */
19970  #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos     (26UL)         /*!< GWBRS (Bit 26)                                        */
19971  #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk     (0x4000000UL)  /*!< GWBRS (Bitfield-Mask: 0x01)                           */
19972  #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
19973  #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
19974  #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
19975  #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
19976  #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
19977  #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
19978  #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos     (31UL)         /*!< CFDTE (Bit 31)                                        */
19979  #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk     (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01)                           */
19980 /* =========================================================  FDCTR  ========================================================= */
19981  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
19982  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
19983  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
19984  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
19985 /* =========================================================  FDSTS  ========================================================= */
19986  #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
19987  #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
19988  #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
19989  #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
19990  #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
19991  #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
19992  #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
19993  #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
19994  #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
19995  #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
19996  #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
19997  #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
19998 /* =========================================================  FDCRC  ========================================================= */
19999  #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
20000  #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
20001  #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (24UL)         /*!< SCNT (Bit 24)                                         */
20002  #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0xf000000UL)  /*!< SCNT (Bitfield-Mask: 0x0f)                            */
20003 /* =========================================================  BLCT  ========================================================== */
20004  #define R_CANFD_CFDC2_BLCT_BLCE_Pos       (0UL)          /*!< BLCE (Bit 0)                                          */
20005  #define R_CANFD_CFDC2_BLCT_BLCE_Msk       (0x1UL)        /*!< BLCE (Bitfield-Mask: 0x01)                            */
20006  #define R_CANFD_CFDC2_BLCT_BLCLD_Pos      (8UL)          /*!< BLCLD (Bit 8)                                         */
20007  #define R_CANFD_CFDC2_BLCT_BLCLD_Msk      (0x100UL)      /*!< BLCLD (Bitfield-Mask: 0x01)                           */
20008 /* =========================================================  BLSTS  ========================================================= */
20009  #define R_CANFD_CFDC2_BLSTS_BLC_Pos       (3UL)          /*!< BLC (Bit 3)                                           */
20010  #define R_CANFD_CFDC2_BLSTS_BLC_Msk       (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff)                       */
20011 
20012 /* =========================================================================================================================== */
20013 /* ================                                          CFDGAFL                                          ================ */
20014 /* =========================================================================================================================== */
20015 
20016 /* ==========================================================  ID  =========================================================== */
20017  #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
20018  #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
20019  #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
20020  #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
20021  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
20022  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
20023  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
20024  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
20025 /* ===========================================================  M  =========================================================== */
20026  #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
20027  #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
20028  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
20029  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
20030  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
20031  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
20032  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
20033  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
20034 /* ==========================================================  P0  =========================================================== */
20035  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
20036  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
20037  #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos    (4UL)          /*!< GAFLSRD0 (Bit 4)                                      */
20038  #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk    (0x10UL)       /*!< GAFLSRD0 (Bitfield-Mask: 0x01)                        */
20039  #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos    (5UL)          /*!< GAFLSRD1 (Bit 5)                                      */
20040  #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk    (0x20UL)       /*!< GAFLSRD1 (Bitfield-Mask: 0x01)                        */
20041  #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos    (6UL)          /*!< GAFLSRD2 (Bit 6)                                      */
20042  #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk    (0x40UL)       /*!< GAFLSRD2 (Bitfield-Mask: 0x01)                        */
20043  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
20044  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
20045  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
20046  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
20047  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
20048  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
20049  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
20050  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
20051 /* ==========================================================  P1  =========================================================== */
20052  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
20053  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x3fffUL)     /*!< GAFLFDP (Bitfield-Mask: 0x3fff)                       */
20054 
20055 /* =========================================================================================================================== */
20056 /* ================                                          CFDTHL                                           ================ */
20057 /* =========================================================================================================================== */
20058 
20059 /* =========================================================  ACC0  ========================================================== */
20060  #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
20061  #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
20062  #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
20063  #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
20064  #define R_CANFD_CFDTHL_ACC0_TGW_Pos     (15UL)         /*!< TGW (Bit 15)                                          */
20065  #define R_CANFD_CFDTHL_ACC0_TGW_Msk     (0x8000UL)     /*!< TGW (Bitfield-Mask: 0x01)                             */
20066  #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
20067  #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
20068 /* =========================================================  ACC1  ========================================================== */
20069  #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
20070  #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
20071  #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
20072  #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
20073 
20074 /* =========================================================================================================================== */
20075 /* ================                                           CFDRM                                           ================ */
20076 /* =========================================================================================================================== */
20077 
20078 /* ==========================================================  ID  =========================================================== */
20079  #define R_CANFD_CFDRM_ID_RMID_Pos        (0UL)          /*!< RMID (Bit 0)                                          */
20080  #define R_CANFD_CFDRM_ID_RMID_Msk        (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
20081  #define R_CANFD_CFDRM_ID_RMRTR_Pos       (30UL)         /*!< RMRTR (Bit 30)                                        */
20082  #define R_CANFD_CFDRM_ID_RMRTR_Msk       (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
20083  #define R_CANFD_CFDRM_ID_RMIDE_Pos       (31UL)         /*!< RMIDE (Bit 31)                                        */
20084  #define R_CANFD_CFDRM_ID_RMIDE_Msk       (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
20085 /* ==========================================================  PTR  ========================================================== */
20086  #define R_CANFD_CFDRM_PTR_RMTS_Pos       (0UL)          /*!< RMTS (Bit 0)                                          */
20087  #define R_CANFD_CFDRM_PTR_RMTS_Msk       (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
20088  #define R_CANFD_CFDRM_PTR_RMDLC_Pos      (28UL)         /*!< RMDLC (Bit 28)                                        */
20089  #define R_CANFD_CFDRM_PTR_RMDLC_Msk      (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
20090 /* =========================================================  FDSTS  ========================================================= */
20091  #define R_CANFD_CFDRM_FDSTS_RMESI_Pos    (0UL)          /*!< RMESI (Bit 0)                                         */
20092  #define R_CANFD_CFDRM_FDSTS_RMESI_Msk    (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
20093  #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos    (1UL)          /*!< RMBRS (Bit 1)                                         */
20094  #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk    (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
20095  #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos    (2UL)          /*!< RMFDF (Bit 2)                                         */
20096  #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk    (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
20097  #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos    (8UL)          /*!< RMIFL (Bit 8)                                         */
20098  #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk    (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
20099  #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos    (16UL)         /*!< RMPTR (Bit 16)                                        */
20100  #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk    (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
20101 /* ==========================================================  DF  =========================================================== */
20102  #define R_CANFD_CFDRM_DF_RMDB_Pos        (0UL)          /*!< RMDB (Bit 0)                                          */
20103  #define R_CANFD_CFDRM_DF_RMDB_Msk        (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
20104 
20105 /* =========================================================================================================================== */
20106 /* ================                                           CFDRF                                           ================ */
20107 /* =========================================================================================================================== */
20108 
20109 /* ==========================================================  ID  =========================================================== */
20110  #define R_CANFD_CFDRF_ID_RFID_Pos        (0UL)          /*!< RFID (Bit 0)                                          */
20111  #define R_CANFD_CFDRF_ID_RFID_Msk        (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
20112  #define R_CANFD_CFDRF_ID_RFRTR_Pos       (30UL)         /*!< RFRTR (Bit 30)                                        */
20113  #define R_CANFD_CFDRF_ID_RFRTR_Msk       (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
20114  #define R_CANFD_CFDRF_ID_RFIDE_Pos       (31UL)         /*!< RFIDE (Bit 31)                                        */
20115  #define R_CANFD_CFDRF_ID_RFIDE_Msk       (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
20116 /* ==========================================================  PTR  ========================================================== */
20117  #define R_CANFD_CFDRF_PTR_RFTS_Pos       (0UL)          /*!< RFTS (Bit 0)                                          */
20118  #define R_CANFD_CFDRF_PTR_RFTS_Msk       (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
20119  #define R_CANFD_CFDRF_PTR_RFDLC_Pos      (28UL)         /*!< RFDLC (Bit 28)                                        */
20120  #define R_CANFD_CFDRF_PTR_RFDLC_Msk      (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
20121 /* =========================================================  FDSTS  ========================================================= */
20122  #define R_CANFD_CFDRF_FDSTS_RFESI_Pos    (0UL)          /*!< RFESI (Bit 0)                                         */
20123  #define R_CANFD_CFDRF_FDSTS_RFESI_Msk    (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
20124  #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos    (1UL)          /*!< RFBRS (Bit 1)                                         */
20125  #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk    (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
20126  #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos    (2UL)          /*!< RFFDF (Bit 2)                                         */
20127  #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk    (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
20128  #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos    (8UL)          /*!< RFIFL (Bit 8)                                         */
20129  #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk    (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
20130  #define R_CANFD_CFDRF_FDSTS_RFPTR_Pos    (16UL)         /*!< RFPTR (Bit 16)                                        */
20131  #define R_CANFD_CFDRF_FDSTS_RFPTR_Msk    (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff)                         */
20132 /* ==========================================================  DF  =========================================================== */
20133  #define R_CANFD_CFDRF_DF_RFDB_Pos        (0UL)          /*!< RFDB (Bit 0)                                          */
20134  #define R_CANFD_CFDRF_DF_RFDB_Msk        (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
20135 
20136 /* =========================================================================================================================== */
20137 /* ================                                           CFDCF                                           ================ */
20138 /* =========================================================================================================================== */
20139 
20140 /* ==========================================================  ID  =========================================================== */
20141  #define R_CANFD_CFDCF_ID_CFID_Pos        (0UL)          /*!< CFID (Bit 0)                                          */
20142  #define R_CANFD_CFDCF_ID_CFID_Msk        (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
20143  #define R_CANFD_CFDCF_ID_CFRTR_Pos       (30UL)         /*!< CFRTR (Bit 30)                                        */
20144  #define R_CANFD_CFDCF_ID_CFRTR_Msk       (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
20145  #define R_CANFD_CFDCF_ID_CFIDE_Pos       (31UL)         /*!< CFIDE (Bit 31)                                        */
20146  #define R_CANFD_CFDCF_ID_CFIDE_Msk       (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
20147 /* ==========================================================  PTR  ========================================================== */
20148  #define R_CANFD_CFDCF_PTR_CFTS_Pos       (0UL)          /*!< CFTS (Bit 0)                                          */
20149  #define R_CANFD_CFDCF_PTR_CFTS_Msk       (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
20150  #define R_CANFD_CFDCF_PTR_CFDLC_Pos      (28UL)         /*!< CFDLC (Bit 28)                                        */
20151  #define R_CANFD_CFDCF_PTR_CFDLC_Msk      (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
20152 /* =========================================================  FDSTS  ========================================================= */
20153  #define R_CANFD_CFDCF_FDSTS_CFESI_Pos    (0UL)          /*!< CFESI (Bit 0)                                         */
20154  #define R_CANFD_CFDCF_FDSTS_CFESI_Msk    (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
20155  #define R_CANFD_CFDCF_FDSTS_CFBRS_Pos    (1UL)          /*!< CFBRS (Bit 1)                                         */
20156  #define R_CANFD_CFDCF_FDSTS_CFBRS_Msk    (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
20157  #define R_CANFD_CFDCF_FDSTS_CFFDF_Pos    (2UL)          /*!< CFFDF (Bit 2)                                         */
20158  #define R_CANFD_CFDCF_FDSTS_CFFDF_Msk    (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
20159  #define R_CANFD_CFDCF_FDSTS_CFIFL_Pos    (8UL)          /*!< CFIFL (Bit 8)                                         */
20160  #define R_CANFD_CFDCF_FDSTS_CFIFL_Msk    (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
20161  #define R_CANFD_CFDCF_FDSTS_CFPTR_Pos    (16UL)         /*!< CFPTR (Bit 16)                                        */
20162  #define R_CANFD_CFDCF_FDSTS_CFPTR_Msk    (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
20163 /* ==========================================================  DF  =========================================================== */
20164  #define R_CANFD_CFDCF_DF_CFDB_Pos        (0UL)          /*!< CFDB (Bit 0)                                          */
20165  #define R_CANFD_CFDCF_DF_CFDB_Msk        (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
20166 
20167 /* =========================================================================================================================== */
20168 /* ================                                           CFDTM                                           ================ */
20169 /* =========================================================================================================================== */
20170 
20171 /* ==========================================================  ID  =========================================================== */
20172  #define R_CANFD_CFDTM_ID_TMID_Pos        (0UL)          /*!< TMID (Bit 0)                                          */
20173  #define R_CANFD_CFDTM_ID_TMID_Msk        (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
20174  #define R_CANFD_CFDTM_ID_TMRTR_Pos       (30UL)         /*!< TMRTR (Bit 30)                                        */
20175  #define R_CANFD_CFDTM_ID_TMRTR_Msk       (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
20176  #define R_CANFD_CFDTM_ID_TMIDE_Pos       (31UL)         /*!< TMIDE (Bit 31)                                        */
20177  #define R_CANFD_CFDTM_ID_TMIDE_Msk       (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
20178 /* ==========================================================  PTR  ========================================================== */
20179  #define R_CANFD_CFDTM_PTR_TMTS_Pos       (0UL)          /*!< TMTS (Bit 0)                                          */
20180  #define R_CANFD_CFDTM_PTR_TMTS_Msk       (0xffffUL)     /*!< TMTS (Bitfield-Mask: 0xffff)                          */
20181  #define R_CANFD_CFDTM_PTR_TMDLC_Pos      (28UL)         /*!< TMDLC (Bit 28)                                        */
20182  #define R_CANFD_CFDTM_PTR_TMDLC_Msk      (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
20183 /* =========================================================  FDCTR  ========================================================= */
20184  #define R_CANFD_CFDTM_FDCTR_TMESI_Pos    (0UL)          /*!< TMESI (Bit 0)                                         */
20185  #define R_CANFD_CFDTM_FDCTR_TMESI_Msk    (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
20186  #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos    (1UL)          /*!< TMBRS (Bit 1)                                         */
20187  #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk    (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
20188  #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos    (2UL)          /*!< TMFDF (Bit 2)                                         */
20189  #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk    (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
20190  #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos    (8UL)          /*!< TMIFL (Bit 8)                                         */
20191  #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk    (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
20192  #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos    (16UL)         /*!< TMPTR (Bit 16)                                        */
20193  #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk    (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
20194 /* ==========================================================  DF  =========================================================== */
20195  #define R_CANFD_CFDTM_DF_TMDB_Pos        (0UL)          /*!< TMDB (Bit 0)                                          */
20196  #define R_CANFD_CFDTM_DF_TMDB_Msk        (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
20197 
20198 /* =========================================================================================================================== */
20199 /* ================                                          ELSEGR                                           ================ */
20200 /* =========================================================================================================================== */
20201 
20202 /* ==========================================================  BY  =========================================================== */
20203  #define R_ELC_ELSEGR_BY_WI_Pos     (7UL)    /*!< WI (Bit 7)                                            */
20204  #define R_ELC_ELSEGR_BY_WI_Msk     (0x80UL) /*!< WI (Bitfield-Mask: 0x01)                              */
20205  #define R_ELC_ELSEGR_BY_WE_Pos     (6UL)    /*!< WE (Bit 6)                                            */
20206  #define R_ELC_ELSEGR_BY_WE_Msk     (0x40UL) /*!< WE (Bitfield-Mask: 0x01)                              */
20207  #define R_ELC_ELSEGR_BY_SEG_Pos    (0UL)    /*!< SEG (Bit 0)                                           */
20208  #define R_ELC_ELSEGR_BY_SEG_Msk    (0x1UL)  /*!< SEG (Bitfield-Mask: 0x01)                             */
20209 
20210 /* =========================================================================================================================== */
20211 /* ================                                           ELSR                                            ================ */
20212 /* =========================================================================================================================== */
20213 
20214 /* ==========================================================  HA  =========================================================== */
20215  #define R_ELC_ELSR_HA_ELS_Pos    (0UL)     /*!< ELS (Bit 0)                                           */
20216  #define R_ELC_ELSR_HA_ELS_Msk    (0x1ffUL) /*!< ELS (Bitfield-Mask: 0x1ff)                            */
20217 
20218 /* =========================================================================================================================== */
20219 /* ================                                            SAR                                            ================ */
20220 /* =========================================================================================================================== */
20221 
20222 /* ===========================================================  L  =========================================================== */
20223  #define R_IIC0_SAR_L_SVA_Pos     (0UL)    /*!< SVA (Bit 0)                                           */
20224  #define R_IIC0_SAR_L_SVA_Msk     (0xffUL) /*!< SVA (Bitfield-Mask: 0xff)                             */
20225 /* ===========================================================  U  =========================================================== */
20226  #define R_IIC0_SAR_U_SVA9_Pos    (2UL)    /*!< SVA9 (Bit 2)                                          */
20227  #define R_IIC0_SAR_U_SVA9_Msk    (0x4UL)  /*!< SVA9 (Bitfield-Mask: 0x01)                            */
20228  #define R_IIC0_SAR_U_SVA8_Pos    (1UL)    /*!< SVA8 (Bit 1)                                          */
20229  #define R_IIC0_SAR_U_SVA8_Msk    (0x2UL)  /*!< SVA8 (Bitfield-Mask: 0x01)                            */
20230  #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
20231  #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
20232 
20233 /* =========================================================================================================================== */
20234 /* ================                                          REGION                                           ================ */
20235 /* =========================================================================================================================== */
20236 
20237 /* ==========================================================  AC  =========================================================== */
20238  #define R_MPU_MMPU_GROUP_REGION_AC_PP_Pos        (3UL)          /*!< PP (Bit 3)                                            */
20239  #define R_MPU_MMPU_GROUP_REGION_AC_PP_Msk        (0x8UL)        /*!< PP (Bitfield-Mask: 0x01)                              */
20240  #define R_MPU_MMPU_GROUP_REGION_AC_WP_Pos        (2UL)          /*!< WP (Bit 2)                                            */
20241  #define R_MPU_MMPU_GROUP_REGION_AC_WP_Msk        (0x4UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
20242  #define R_MPU_MMPU_GROUP_REGION_AC_RP_Pos        (1UL)          /*!< RP (Bit 1)                                            */
20243  #define R_MPU_MMPU_GROUP_REGION_AC_RP_Msk        (0x2UL)        /*!< RP (Bitfield-Mask: 0x01)                              */
20244  #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Pos    (0UL)          /*!< ENABLE (Bit 0)                                        */
20245  #define R_MPU_MMPU_GROUP_REGION_AC_ENABLE_Msk    (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
20246 /* ===========================================================  S  =========================================================== */
20247  #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Pos      (0UL)          /*!< MMPUS (Bit 0)                                         */
20248  #define R_MPU_MMPU_GROUP_REGION_S_MMPUS_Msk      (0xffffffffUL) /*!< MMPUS (Bitfield-Mask: 0xffffffff)                     */
20249 /* ===========================================================  E  =========================================================== */
20250  #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Pos      (0UL)          /*!< MMPUE (Bit 0)                                         */
20251  #define R_MPU_MMPU_GROUP_REGION_E_MMPUE_Msk      (0xffffffffUL) /*!< MMPUE (Bitfield-Mask: 0xffffffff)                     */
20252 
20253 /* =========================================================================================================================== */
20254 /* ================                                           GROUP                                           ================ */
20255 /* =========================================================================================================================== */
20256 
20257 /* ==========================================================  EN  =========================================================== */
20258  #define R_MPU_MMPU_GROUP_EN_KEY_Pos             (8UL)      /*!< KEY (Bit 8)                                           */
20259  #define R_MPU_MMPU_GROUP_EN_KEY_Msk             (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20260  #define R_MPU_MMPU_GROUP_EN_ENABLE_Pos          (0UL)      /*!< ENABLE (Bit 0)                                        */
20261  #define R_MPU_MMPU_GROUP_EN_ENABLE_Msk          (0x1UL)    /*!< ENABLE (Bitfield-Mask: 0x01)                          */
20262 /* =========================================================  ENPT  ========================================================== */
20263  #define R_MPU_MMPU_GROUP_ENPT_KEY_Pos           (8UL)      /*!< KEY (Bit 8)                                           */
20264  #define R_MPU_MMPU_GROUP_ENPT_KEY_Msk           (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20265  #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Pos       (0UL)      /*!< PROTECT (Bit 0)                                       */
20266  #define R_MPU_MMPU_GROUP_ENPT_PROTECT_Msk       (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20267 /* ==========================================================  RPT  ========================================================== */
20268  #define R_MPU_MMPU_GROUP_RPT_KEY_Pos            (8UL)      /*!< KEY (Bit 8)                                           */
20269  #define R_MPU_MMPU_GROUP_RPT_KEY_Msk            (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20270  #define R_MPU_MMPU_GROUP_RPT_PROTECT_Pos        (0UL)      /*!< PROTECT (Bit 0)                                       */
20271  #define R_MPU_MMPU_GROUP_RPT_PROTECT_Msk        (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20272 /* ========================================================  RPT_SEC  ======================================================== */
20273  #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
20274  #define R_MPU_MMPU_GROUP_RPT_SEC_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
20275  #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
20276  #define R_MPU_MMPU_GROUP_RPT_SEC_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20277 
20278 /* =========================================================================================================================== */
20279 /* ================                                            SP                                             ================ */
20280 /* =========================================================================================================================== */
20281 
20282 /* ==========================================================  OAD  ========================================================== */
20283  #define R_MPU_SPMON_SP_OAD_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
20284  #define R_MPU_SPMON_SP_OAD_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20285  #define R_MPU_SPMON_SP_OAD_OAD_Pos        (0UL)          /*!< OAD (Bit 0)                                           */
20286  #define R_MPU_SPMON_SP_OAD_OAD_Msk        (0x1UL)        /*!< OAD (Bitfield-Mask: 0x01)                             */
20287 /* ==========================================================  CTL  ========================================================== */
20288  #define R_MPU_SPMON_SP_CTL_ERROR_Pos      (8UL)          /*!< ERROR (Bit 8)                                         */
20289  #define R_MPU_SPMON_SP_CTL_ERROR_Msk      (0x100UL)      /*!< ERROR (Bitfield-Mask: 0x01)                           */
20290  #define R_MPU_SPMON_SP_CTL_ENABLE_Pos     (0UL)          /*!< ENABLE (Bit 0)                                        */
20291  #define R_MPU_SPMON_SP_CTL_ENABLE_Msk     (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
20292 /* ==========================================================  PT  =========================================================== */
20293  #define R_MPU_SPMON_SP_PT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
20294  #define R_MPU_SPMON_SP_PT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
20295  #define R_MPU_SPMON_SP_PT_PROTECT_Pos     (0UL)          /*!< PROTECT (Bit 0)                                       */
20296  #define R_MPU_SPMON_SP_PT_PROTECT_Msk     (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
20297 /* ==========================================================  SA  =========================================================== */
20298  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Pos    (0UL)          /*!< MSPMPUSA (Bit 0)                                      */
20299  #define R_MPU_SPMON_SP_SA_MSPMPUSA_Msk    (0xffffffffUL) /*!< MSPMPUSA (Bitfield-Mask: 0xffffffff)                  */
20300 /* ==========================================================  EA  =========================================================== */
20301  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Pos    (0UL)          /*!< MSPMPUEA (Bit 0)                                      */
20302  #define R_MPU_SPMON_SP_EA_MSPMPUEA_Msk    (0xffffffffUL) /*!< MSPMPUEA (Bitfield-Mask: 0xffffffff)                  */
20303 
20304 /* =========================================================================================================================== */
20305 /* ================                                            PIN                                            ================ */
20306 /* =========================================================================================================================== */
20307 
20308 /* =======================================================  PmnPFS_BY  ======================================================= */
20309  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
20310  #define R_PFS_PORT_PIN_PmnPFS_BY_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
20311  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
20312  #define R_PFS_PORT_PIN_PmnPFS_BY_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
20313  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
20314  #define R_PFS_PORT_PIN_PmnPFS_BY_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
20315  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
20316  #define R_PFS_PORT_PIN_PmnPFS_BY_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
20317  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
20318  #define R_PFS_PORT_PIN_PmnPFS_BY_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
20319  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
20320  #define R_PFS_PORT_PIN_PmnPFS_BY_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
20321 /* =======================================================  PmnPFS_HA  ======================================================= */
20322  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Pos    (6UL)          /*!< NCODR (Bit 6)                                         */
20323  #define R_PFS_PORT_PIN_PmnPFS_HA_NCODR_Msk    (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
20324  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Pos      (5UL)          /*!< PIM (Bit 5)                                           */
20325  #define R_PFS_PORT_PIN_PmnPFS_HA_PIM_Msk      (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
20326  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Pos      (4UL)          /*!< PCR (Bit 4)                                           */
20327  #define R_PFS_PORT_PIN_PmnPFS_HA_PCR_Msk      (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
20328  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Pos      (2UL)          /*!< PDR (Bit 2)                                           */
20329  #define R_PFS_PORT_PIN_PmnPFS_HA_PDR_Msk      (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
20330  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Pos     (1UL)          /*!< PIDR (Bit 1)                                          */
20331  #define R_PFS_PORT_PIN_PmnPFS_HA_PIDR_Msk     (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
20332  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Pos     (0UL)          /*!< PODR (Bit 0)                                          */
20333  #define R_PFS_PORT_PIN_PmnPFS_HA_PODR_Msk     (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
20334  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Pos     (15UL)         /*!< ASEL (Bit 15)                                         */
20335  #define R_PFS_PORT_PIN_PmnPFS_HA_ASEL_Msk     (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
20336  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Pos     (14UL)         /*!< ISEL (Bit 14)                                         */
20337  #define R_PFS_PORT_PIN_PmnPFS_HA_ISEL_Msk     (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
20338  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Pos     (12UL)         /*!< EOFR (Bit 12)                                         */
20339  #define R_PFS_PORT_PIN_PmnPFS_HA_EOFR_Msk     (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
20340  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Pos     (10UL)         /*!< DSCR (Bit 10)                                         */
20341  #define R_PFS_PORT_PIN_PmnPFS_HA_DSCR_Msk     (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
20342 /* ========================================================  PmnPFS  ========================================================= */
20343  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Pos       (6UL)          /*!< NCODR (Bit 6)                                         */
20344  #define R_PFS_PORT_PIN_PmnPFS_NCODR_Msk       (0x40UL)       /*!< NCODR (Bitfield-Mask: 0x01)                           */
20345  #define R_PFS_PORT_PIN_PmnPFS_PIM_Pos         (5UL)          /*!< PIM (Bit 5)                                           */
20346  #define R_PFS_PORT_PIN_PmnPFS_PIM_Msk         (0x20UL)       /*!< PIM (Bitfield-Mask: 0x01)                             */
20347  #define R_PFS_PORT_PIN_PmnPFS_PCR_Pos         (4UL)          /*!< PCR (Bit 4)                                           */
20348  #define R_PFS_PORT_PIN_PmnPFS_PCR_Msk         (0x10UL)       /*!< PCR (Bitfield-Mask: 0x01)                             */
20349  #define R_PFS_PORT_PIN_PmnPFS_PDR_Pos         (2UL)          /*!< PDR (Bit 2)                                           */
20350  #define R_PFS_PORT_PIN_PmnPFS_PDR_Msk         (0x4UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
20351  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Pos        (1UL)          /*!< PIDR (Bit 1)                                          */
20352  #define R_PFS_PORT_PIN_PmnPFS_PIDR_Msk        (0x2UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
20353  #define R_PFS_PORT_PIN_PmnPFS_PODR_Pos        (0UL)          /*!< PODR (Bit 0)                                          */
20354  #define R_PFS_PORT_PIN_PmnPFS_PODR_Msk        (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
20355  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Pos        (15UL)         /*!< ASEL (Bit 15)                                         */
20356  #define R_PFS_PORT_PIN_PmnPFS_ASEL_Msk        (0x8000UL)     /*!< ASEL (Bitfield-Mask: 0x01)                            */
20357  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Pos        (14UL)         /*!< ISEL (Bit 14)                                         */
20358  #define R_PFS_PORT_PIN_PmnPFS_ISEL_Msk        (0x4000UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
20359  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Pos        (12UL)         /*!< EOFR (Bit 12)                                         */
20360  #define R_PFS_PORT_PIN_PmnPFS_EOFR_Msk        (0x3000UL)     /*!< EOFR (Bitfield-Mask: 0x03)                            */
20361  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Pos        (10UL)         /*!< DSCR (Bit 10)                                         */
20362  #define R_PFS_PORT_PIN_PmnPFS_DSCR_Msk        (0xc00UL)      /*!< DSCR (Bitfield-Mask: 0x03)                            */
20363  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Pos        (24UL)         /*!< PSEL (Bit 24)                                         */
20364  #define R_PFS_PORT_PIN_PmnPFS_PSEL_Msk        (0x1f000000UL) /*!< PSEL (Bitfield-Mask: 0x1f)                            */
20365  #define R_PFS_PORT_PIN_PmnPFS_PMR_Pos         (16UL)         /*!< PMR (Bit 16)                                          */
20366  #define R_PFS_PORT_PIN_PmnPFS_PMR_Msk         (0x10000UL)    /*!< PMR (Bitfield-Mask: 0x01)                             */
20367 
20368 /* =========================================================================================================================== */
20369 /* ================                                           PORT                                            ================ */
20370 /* =========================================================================================================================== */
20371 
20372 /* =========================================================================================================================== */
20373 /* ================                                           VLSEL                                           ================ */
20374 /* =========================================================================================================================== */
20375 
20376 /* ========================================================  VL1SEL  ========================================================= */
20377  #define R_PFS_VLSEL_VL1SEL_SELVL_Pos    (0UL)   /*!< SELVL (Bit 0)                                         */
20378  #define R_PFS_VLSEL_VL1SEL_SELVL_Msk    (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01)                           */
20379 
20380 /* =========================================================================================================================== */
20381 /* ================                                           PMSAR                                           ================ */
20382 /* =========================================================================================================================== */
20383 
20384 /* =========================================================  PMSAR  ========================================================= */
20385 
20386 /* =========================================================================================================================== */
20387 /* ================                                           RTCCR                                           ================ */
20388 /* =========================================================================================================================== */
20389 
20390 /* =========================================================  RTCCR  ========================================================= */
20391  #define R_RTC_RTCCR_RTCCR_TCEN_Pos    (7UL)    /*!< TCEN (Bit 7)                                          */
20392  #define R_RTC_RTCCR_RTCCR_TCEN_Msk    (0x80UL) /*!< TCEN (Bitfield-Mask: 0x01)                            */
20393  #define R_RTC_RTCCR_RTCCR_TCNF_Pos    (4UL)    /*!< TCNF (Bit 4)                                          */
20394  #define R_RTC_RTCCR_RTCCR_TCNF_Msk    (0x30UL) /*!< TCNF (Bitfield-Mask: 0x03)                            */
20395  #define R_RTC_RTCCR_RTCCR_TCST_Pos    (2UL)    /*!< TCST (Bit 2)                                          */
20396  #define R_RTC_RTCCR_RTCCR_TCST_Msk    (0x4UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
20397  #define R_RTC_RTCCR_RTCCR_TCCT_Pos    (0UL)    /*!< TCCT (Bit 0)                                          */
20398  #define R_RTC_RTCCR_RTCCR_TCCT_Msk    (0x3UL)  /*!< TCCT (Bitfield-Mask: 0x03)                            */
20399 
20400 /* =========================================================================================================================== */
20401 /* ================                                            CP                                             ================ */
20402 /* =========================================================================================================================== */
20403 
20404 /* =========================================================  RSEC  ========================================================== */
20405  #define R_RTC_CP_RSEC_SEC10_Pos       (4UL)    /*!< SEC10 (Bit 4)                                         */
20406  #define R_RTC_CP_RSEC_SEC10_Msk       (0x70UL) /*!< SEC10 (Bitfield-Mask: 0x07)                           */
20407  #define R_RTC_CP_RSEC_SEC1_Pos        (0UL)    /*!< SEC1 (Bit 0)                                          */
20408  #define R_RTC_CP_RSEC_SEC1_Msk        (0xfUL)  /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
20409 /* =========================================================  BCNT0  ========================================================= */
20410  #define R_RTC_CP_BCNT0_BCNT0CP_Pos    (0UL)    /*!< BCNT0CP (Bit 0)                                       */
20411  #define R_RTC_CP_BCNT0_BCNT0CP_Msk    (0xffUL) /*!< BCNT0CP (Bitfield-Mask: 0xff)                         */
20412 /* =========================================================  RMIN  ========================================================== */
20413  #define R_RTC_CP_RMIN_MIN10_Pos       (4UL)    /*!< MIN10 (Bit 4)                                         */
20414  #define R_RTC_CP_RMIN_MIN10_Msk       (0x70UL) /*!< MIN10 (Bitfield-Mask: 0x07)                           */
20415  #define R_RTC_CP_RMIN_MIN1_Pos        (0UL)    /*!< MIN1 (Bit 0)                                          */
20416  #define R_RTC_CP_RMIN_MIN1_Msk        (0xfUL)  /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
20417 /* =========================================================  BCNT1  ========================================================= */
20418  #define R_RTC_CP_BCNT1_BCNT1CP_Pos    (0UL)    /*!< BCNT1CP (Bit 0)                                       */
20419  #define R_RTC_CP_BCNT1_BCNT1CP_Msk    (0xffUL) /*!< BCNT1CP (Bitfield-Mask: 0xff)                         */
20420 /* ==========================================================  RHR  ========================================================== */
20421  #define R_RTC_CP_RHR_PM_Pos           (6UL)    /*!< PM (Bit 6)                                            */
20422  #define R_RTC_CP_RHR_PM_Msk           (0x40UL) /*!< PM (Bitfield-Mask: 0x01)                              */
20423  #define R_RTC_CP_RHR_HR10_Pos         (4UL)    /*!< HR10 (Bit 4)                                          */
20424  #define R_RTC_CP_RHR_HR10_Msk         (0x30UL) /*!< HR10 (Bitfield-Mask: 0x03)                            */
20425  #define R_RTC_CP_RHR_HR1_Pos          (0UL)    /*!< HR1 (Bit 0)                                           */
20426  #define R_RTC_CP_RHR_HR1_Msk          (0xfUL)  /*!< HR1 (Bitfield-Mask: 0x0f)                             */
20427 /* =========================================================  BCNT2  ========================================================= */
20428  #define R_RTC_CP_BCNT2_BCNT2CP_Pos    (0UL)    /*!< BCNT2CP (Bit 0)                                       */
20429  #define R_RTC_CP_BCNT2_BCNT2CP_Msk    (0xffUL) /*!< BCNT2CP (Bitfield-Mask: 0xff)                         */
20430 /* =========================================================  RDAY  ========================================================== */
20431  #define R_RTC_CP_RDAY_DATE10_Pos      (4UL)    /*!< DATE10 (Bit 4)                                        */
20432  #define R_RTC_CP_RDAY_DATE10_Msk      (0x30UL) /*!< DATE10 (Bitfield-Mask: 0x03)                          */
20433  #define R_RTC_CP_RDAY_DATE1_Pos       (0UL)    /*!< DATE1 (Bit 0)                                         */
20434  #define R_RTC_CP_RDAY_DATE1_Msk       (0xfUL)  /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
20435 /* =========================================================  BCNT3  ========================================================= */
20436  #define R_RTC_CP_BCNT3_BCNT3CP_Pos    (0UL)    /*!< BCNT3CP (Bit 0)                                       */
20437  #define R_RTC_CP_BCNT3_BCNT3CP_Msk    (0xffUL) /*!< BCNT3CP (Bitfield-Mask: 0xff)                         */
20438 /* =========================================================  RMON  ========================================================== */
20439  #define R_RTC_CP_RMON_MON10_Pos       (4UL)    /*!< MON10 (Bit 4)                                         */
20440  #define R_RTC_CP_RMON_MON10_Msk       (0x10UL) /*!< MON10 (Bitfield-Mask: 0x01)                           */
20441  #define R_RTC_CP_RMON_MON1_Pos        (0UL)    /*!< MON1 (Bit 0)                                          */
20442  #define R_RTC_CP_RMON_MON1_Msk        (0xfUL)  /*!< MON1 (Bitfield-Mask: 0x0f)                            */
20443 
20444 /* =========================================================================================================================== */
20445 /* ================                                          PIPE_TR                                          ================ */
20446 /* =========================================================================================================================== */
20447 
20448 /* ===========================================================  E  =========================================================== */
20449  #define R_USB_FS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
20450  #define R_USB_FS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
20451  #define R_USB_FS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
20452  #define R_USB_FS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
20453 /* ===========================================================  N  =========================================================== */
20454  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
20455  #define R_USB_FS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
20456 
20457 /* =========================================================================================================================== */
20458 /* ================                                          PIPE_TR                                          ================ */
20459 /* =========================================================================================================================== */
20460 
20461 /* ===========================================================  E  =========================================================== */
20462  #define R_USB_HS0_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
20463  #define R_USB_HS0_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
20464  #define R_USB_HS0_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
20465  #define R_USB_HS0_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
20466 /* ===========================================================  N  =========================================================== */
20467  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
20468  #define R_USB_HS0_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
20469 
20470 /* =========================================================================================================================== */
20471 /* ================                                           CTRL                                            ================ */
20472 /* =========================================================================================================================== */
20473 
20474 /* =========================================================  AGTCR  ========================================================= */
20475  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Pos          (7UL)    /*!< TCMBF (Bit 7)                                         */
20476  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMBF_Msk          (0x80UL) /*!< TCMBF (Bitfield-Mask: 0x01)                           */
20477  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Pos          (6UL)    /*!< TCMAF (Bit 6)                                         */
20478  #define R_AGTX0_AGT16_CTRL_AGTCR_TCMAF_Msk          (0x40UL) /*!< TCMAF (Bitfield-Mask: 0x01)                           */
20479  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos          (5UL)    /*!< TUNDF (Bit 5)                                         */
20480  #define R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Msk          (0x20UL) /*!< TUNDF (Bitfield-Mask: 0x01)                           */
20481  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos          (4UL)    /*!< TEDGF (Bit 4)                                         */
20482  #define R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Msk          (0x10UL) /*!< TEDGF (Bitfield-Mask: 0x01)                           */
20483  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Pos          (2UL)    /*!< TSTOP (Bit 2)                                         */
20484  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTOP_Msk          (0x4UL)  /*!< TSTOP (Bitfield-Mask: 0x01)                           */
20485  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos          (1UL)    /*!< TCSTF (Bit 1)                                         */
20486  #define R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Msk          (0x2UL)  /*!< TCSTF (Bitfield-Mask: 0x01)                           */
20487  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Pos         (0UL)    /*!< TSTART (Bit 0)                                        */
20488  #define R_AGTX0_AGT16_CTRL_AGTCR_TSTART_Msk         (0x1UL)  /*!< TSTART (Bitfield-Mask: 0x01)                          */
20489 /* ========================================================  AGTMR1  ========================================================= */
20490  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos           (4UL)    /*!< TCK (Bit 4)                                           */
20491  #define R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Msk           (0x70UL) /*!< TCK (Bitfield-Mask: 0x07)                             */
20492  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Pos        (3UL)    /*!< TEDGPL (Bit 3)                                        */
20493  #define R_AGTX0_AGT16_CTRL_AGTMR1_TEDGPL_Msk        (0x8UL)  /*!< TEDGPL (Bitfield-Mask: 0x01)                          */
20494  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Pos          (0UL)    /*!< TMOD (Bit 0)                                          */
20495  #define R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk          (0x7UL)  /*!< TMOD (Bitfield-Mask: 0x07)                            */
20496 /* ========================================================  AGTMR2  ========================================================= */
20497  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Pos           (7UL)    /*!< LPM (Bit 7)                                           */
20498  #define R_AGTX0_AGT16_CTRL_AGTMR2_LPM_Msk           (0x80UL) /*!< LPM (Bitfield-Mask: 0x01)                             */
20499  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Pos           (0UL)    /*!< CKS (Bit 0)                                           */
20500  #define R_AGTX0_AGT16_CTRL_AGTMR2_CKS_Msk           (0x7UL)  /*!< CKS (Bitfield-Mask: 0x07)                             */
20501 /* =====================================================  AGTIOSEL_ALT  ====================================================== */
20502  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Pos    (4UL)    /*!< TIES (Bit 4)                                          */
20503  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_TIES_Msk    (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
20504  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Pos     (0UL)    /*!< SEL (Bit 0)                                           */
20505  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_ALT_SEL_Msk     (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
20506 /* ========================================================  AGTIOC  ========================================================= */
20507  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Pos         (6UL)    /*!< TIOGT (Bit 6)                                         */
20508  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIOGT_Msk         (0xc0UL) /*!< TIOGT (Bitfield-Mask: 0x03)                           */
20509  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Pos          (4UL)    /*!< TIPF (Bit 4)                                          */
20510  #define R_AGTX0_AGT16_CTRL_AGTIOC_TIPF_Msk          (0x30UL) /*!< TIPF (Bitfield-Mask: 0x03)                            */
20511  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Pos           (2UL)    /*!< TOE (Bit 2)                                           */
20512  #define R_AGTX0_AGT16_CTRL_AGTIOC_TOE_Msk           (0x4UL)  /*!< TOE (Bitfield-Mask: 0x01)                             */
20513  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Pos       (0UL)    /*!< TEDGSEL (Bit 0)                                       */
20514  #define R_AGTX0_AGT16_CTRL_AGTIOC_TEDGSEL_Msk       (0x1UL)  /*!< TEDGSEL (Bitfield-Mask: 0x01)                         */
20515 /* ========================================================  AGTISR  ========================================================= */
20516  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Pos          (2UL)    /*!< EEPS (Bit 2)                                          */
20517  #define R_AGTX0_AGT16_CTRL_AGTISR_EEPS_Msk          (0x4UL)  /*!< EEPS (Bitfield-Mask: 0x01)                            */
20518 /* ========================================================  AGTCMSR  ======================================================== */
20519  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Pos       (6UL)    /*!< TOPOLB (Bit 6)                                        */
20520  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLB_Msk       (0x40UL) /*!< TOPOLB (Bitfield-Mask: 0x01)                          */
20521  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Pos         (5UL)    /*!< TOEB (Bit 5)                                          */
20522  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEB_Msk         (0x20UL) /*!< TOEB (Bitfield-Mask: 0x01)                            */
20523  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Pos        (4UL)    /*!< TCMEB (Bit 4)                                         */
20524  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEB_Msk        (0x10UL) /*!< TCMEB (Bitfield-Mask: 0x01)                           */
20525  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Pos       (2UL)    /*!< TOPOLA (Bit 2)                                        */
20526  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOPOLA_Msk       (0x4UL)  /*!< TOPOLA (Bitfield-Mask: 0x01)                          */
20527  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Pos         (1UL)    /*!< TOEA (Bit 1)                                          */
20528  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TOEA_Msk         (0x2UL)  /*!< TOEA (Bitfield-Mask: 0x01)                            */
20529  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos        (0UL)    /*!< TCMEA (Bit 0)                                         */
20530  #define R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Msk        (0x1UL)  /*!< TCMEA (Bitfield-Mask: 0x01)                           */
20531 /* =======================================================  AGTIOSEL  ======================================================== */
20532  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Pos        (4UL)    /*!< TIES (Bit 4)                                          */
20533  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_TIES_Msk        (0x10UL) /*!< TIES (Bitfield-Mask: 0x01)                            */
20534  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Pos         (0UL)    /*!< SEL (Bit 0)                                           */
20535  #define R_AGTX0_AGT16_CTRL_AGTIOSEL_SEL_Msk         (0x3UL)  /*!< SEL (Bitfield-Mask: 0x03)                             */
20536 
20537 /* =========================================================================================================================== */
20538 /* ================                                           AGT16                                           ================ */
20539 /* =========================================================================================================================== */
20540 
20541 /* ==========================================================  AGT  ========================================================== */
20542  #define R_AGTX0_AGT16_AGT_AGT_Pos          (0UL)      /*!< AGT (Bit 0)                                           */
20543  #define R_AGTX0_AGT16_AGT_AGT_Msk          (0xffffUL) /*!< AGT (Bitfield-Mask: 0xffff)                           */
20544 /* ========================================================  AGTCMA  ========================================================= */
20545  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Pos    (0UL)      /*!< AGTCMA (Bit 0)                                        */
20546  #define R_AGTX0_AGT16_AGTCMA_AGTCMA_Msk    (0xffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffff)                        */
20547 /* ========================================================  AGTCMB  ========================================================= */
20548  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Pos    (0UL)      /*!< AGTCMB (Bit 0)                                        */
20549  #define R_AGTX0_AGT16_AGTCMB_AGTCMB_Msk    (0xffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffff)                        */
20550 
20551 /* =========================================================================================================================== */
20552 /* ================                                           AGT32                                           ================ */
20553 /* =========================================================================================================================== */
20554 
20555 /* ==========================================================  AGT  ========================================================== */
20556  #define R_AGTX0_AGT32_AGT_AGT_Pos          (0UL)          /*!< AGT (Bit 0)                                           */
20557  #define R_AGTX0_AGT32_AGT_AGT_Msk          (0xffffffffUL) /*!< AGT (Bitfield-Mask: 0xffffffff)                       */
20558 /* ========================================================  AGTCMA  ========================================================= */
20559  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Pos    (0UL)          /*!< AGTCMA (Bit 0)                                        */
20560  #define R_AGTX0_AGT32_AGTCMA_AGTCMA_Msk    (0xffffffffUL) /*!< AGTCMA (Bitfield-Mask: 0xffffffff)                    */
20561 /* ========================================================  AGTCMB  ========================================================= */
20562  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Pos    (0UL)          /*!< AGTCMB (Bit 0)                                        */
20563  #define R_AGTX0_AGT32_AGTCMB_AGTCMB_Msk    (0xffffffffUL) /*!< AGTCMB (Bitfield-Mask: 0xffffffff)                    */
20564 
20565 /** @} */ /* End of group PosMask_clusters */
20566 
20567 /* =========================================================================================================================== */
20568 /* ================                                Pos/Mask Peripheral Section                                ================ */
20569 /* =========================================================================================================================== */
20570 
20571 /** @addtogroup PosMask_peripherals
20572  * @{
20573  */
20574 
20575 /* =========================================================================================================================== */
20576 /* ================                                          R_ADC0                                           ================ */
20577 /* =========================================================================================================================== */
20578 
20579 /* =========================================================  ADCSR  ========================================================= */
20580  #define R_ADC0_ADCSR_ADST_Pos              (15UL)      /*!< ADST (Bit 15)                                         */
20581  #define R_ADC0_ADCSR_ADST_Msk              (0x8000UL)  /*!< ADST (Bitfield-Mask: 0x01)                            */
20582  #define R_ADC0_ADCSR_ADCS_Pos              (13UL)      /*!< ADCS (Bit 13)                                         */
20583  #define R_ADC0_ADCSR_ADCS_Msk              (0x6000UL)  /*!< ADCS (Bitfield-Mask: 0x03)                            */
20584  #define R_ADC0_ADCSR_ADHSC_Pos             (10UL)      /*!< ADHSC (Bit 10)                                        */
20585  #define R_ADC0_ADCSR_ADHSC_Msk             (0x400UL)   /*!< ADHSC (Bitfield-Mask: 0x01)                           */
20586  #define R_ADC0_ADCSR_TRGE_Pos              (9UL)       /*!< TRGE (Bit 9)                                          */
20587  #define R_ADC0_ADCSR_TRGE_Msk              (0x200UL)   /*!< TRGE (Bitfield-Mask: 0x01)                            */
20588  #define R_ADC0_ADCSR_EXTRG_Pos             (8UL)       /*!< EXTRG (Bit 8)                                         */
20589  #define R_ADC0_ADCSR_EXTRG_Msk             (0x100UL)   /*!< EXTRG (Bitfield-Mask: 0x01)                           */
20590  #define R_ADC0_ADCSR_DBLE_Pos              (7UL)       /*!< DBLE (Bit 7)                                          */
20591  #define R_ADC0_ADCSR_DBLE_Msk              (0x80UL)    /*!< DBLE (Bitfield-Mask: 0x01)                            */
20592  #define R_ADC0_ADCSR_GBADIE_Pos            (6UL)       /*!< GBADIE (Bit 6)                                        */
20593  #define R_ADC0_ADCSR_GBADIE_Msk            (0x40UL)    /*!< GBADIE (Bitfield-Mask: 0x01)                          */
20594  #define R_ADC0_ADCSR_DBLANS_Pos            (0UL)       /*!< DBLANS (Bit 0)                                        */
20595  #define R_ADC0_ADCSR_DBLANS_Msk            (0x1fUL)    /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
20596  #define R_ADC0_ADCSR_ADIE_Pos              (12UL)      /*!< ADIE (Bit 12)                                         */
20597  #define R_ADC0_ADCSR_ADIE_Msk              (0x1000UL)  /*!< ADIE (Bitfield-Mask: 0x01)                            */
20598 /* ========================================================  ADANSA  ========================================================= */
20599  #define R_ADC0_ADANSA_ANSA_Pos             (0UL)       /*!< ANSA (Bit 0)                                          */
20600  #define R_ADC0_ADANSA_ANSA_Msk             (0x1UL)     /*!< ANSA (Bitfield-Mask: 0x01)                            */
20601 /* =========================================================  ADADS  ========================================================= */
20602  #define R_ADC0_ADADS_ADS_Pos               (0UL)       /*!< ADS (Bit 0)                                           */
20603  #define R_ADC0_ADADS_ADS_Msk               (0x1UL)     /*!< ADS (Bitfield-Mask: 0x01)                             */
20604 /* =========================================================  ADADC  ========================================================= */
20605  #define R_ADC0_ADADC_ADC_Pos               (0UL)       /*!< ADC (Bit 0)                                           */
20606  #define R_ADC0_ADADC_ADC_Msk               (0x7UL)     /*!< ADC (Bitfield-Mask: 0x07)                             */
20607  #define R_ADC0_ADADC_AVEE_Pos              (7UL)       /*!< AVEE (Bit 7)                                          */
20608  #define R_ADC0_ADADC_AVEE_Msk              (0x80UL)    /*!< AVEE (Bitfield-Mask: 0x01)                            */
20609 /* =========================================================  ADCER  ========================================================= */
20610  #define R_ADC0_ADCER_ADRFMT_Pos            (15UL)      /*!< ADRFMT (Bit 15)                                       */
20611  #define R_ADC0_ADCER_ADRFMT_Msk            (0x8000UL)  /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
20612  #define R_ADC0_ADCER_ADINV_Pos             (14UL)      /*!< ADINV (Bit 14)                                        */
20613  #define R_ADC0_ADCER_ADINV_Msk             (0x4000UL)  /*!< ADINV (Bitfield-Mask: 0x01)                           */
20614  #define R_ADC0_ADCER_DIAGM_Pos             (11UL)      /*!< DIAGM (Bit 11)                                        */
20615  #define R_ADC0_ADCER_DIAGM_Msk             (0x800UL)   /*!< DIAGM (Bitfield-Mask: 0x01)                           */
20616  #define R_ADC0_ADCER_DIAGLD_Pos            (10UL)      /*!< DIAGLD (Bit 10)                                       */
20617  #define R_ADC0_ADCER_DIAGLD_Msk            (0x400UL)   /*!< DIAGLD (Bitfield-Mask: 0x01)                          */
20618  #define R_ADC0_ADCER_DIAGVAL_Pos           (8UL)       /*!< DIAGVAL (Bit 8)                                       */
20619  #define R_ADC0_ADCER_DIAGVAL_Msk           (0x300UL)   /*!< DIAGVAL (Bitfield-Mask: 0x03)                         */
20620  #define R_ADC0_ADCER_ACE_Pos               (5UL)       /*!< ACE (Bit 5)                                           */
20621  #define R_ADC0_ADCER_ACE_Msk               (0x20UL)    /*!< ACE (Bitfield-Mask: 0x01)                             */
20622  #define R_ADC0_ADCER_ADPRC_Pos             (1UL)       /*!< ADPRC (Bit 1)                                         */
20623  #define R_ADC0_ADCER_ADPRC_Msk             (0x6UL)     /*!< ADPRC (Bitfield-Mask: 0x03)                           */
20624  #define R_ADC0_ADCER_DCE_Pos               (4UL)       /*!< DCE (Bit 4)                                           */
20625  #define R_ADC0_ADCER_DCE_Msk               (0x10UL)    /*!< DCE (Bitfield-Mask: 0x01)                             */
20626 /* ========================================================  ADSTRGR  ======================================================== */
20627  #define R_ADC0_ADSTRGR_TRSA_Pos            (8UL)       /*!< TRSA (Bit 8)                                          */
20628  #define R_ADC0_ADSTRGR_TRSA_Msk            (0x3f00UL)  /*!< TRSA (Bitfield-Mask: 0x3f)                            */
20629  #define R_ADC0_ADSTRGR_TRSB_Pos            (0UL)       /*!< TRSB (Bit 0)                                          */
20630  #define R_ADC0_ADSTRGR_TRSB_Msk            (0x3fUL)    /*!< TRSB (Bitfield-Mask: 0x3f)                            */
20631 /* ========================================================  ADEXICR  ======================================================== */
20632  #define R_ADC0_ADEXICR_OCSB_Pos            (11UL)      /*!< OCSB (Bit 11)                                         */
20633  #define R_ADC0_ADEXICR_OCSB_Msk            (0x800UL)   /*!< OCSB (Bitfield-Mask: 0x01)                            */
20634  #define R_ADC0_ADEXICR_TSSB_Pos            (10UL)      /*!< TSSB (Bit 10)                                         */
20635  #define R_ADC0_ADEXICR_TSSB_Msk            (0x400UL)   /*!< TSSB (Bitfield-Mask: 0x01)                            */
20636  #define R_ADC0_ADEXICR_OCSA_Pos            (9UL)       /*!< OCSA (Bit 9)                                          */
20637  #define R_ADC0_ADEXICR_OCSA_Msk            (0x200UL)   /*!< OCSA (Bitfield-Mask: 0x01)                            */
20638  #define R_ADC0_ADEXICR_TSSA_Pos            (8UL)       /*!< TSSA (Bit 8)                                          */
20639  #define R_ADC0_ADEXICR_TSSA_Msk            (0x100UL)   /*!< TSSA (Bitfield-Mask: 0x01)                            */
20640  #define R_ADC0_ADEXICR_OCSAD_Pos           (1UL)       /*!< OCSAD (Bit 1)                                         */
20641  #define R_ADC0_ADEXICR_OCSAD_Msk           (0x2UL)     /*!< OCSAD (Bitfield-Mask: 0x01)                           */
20642  #define R_ADC0_ADEXICR_TSSAD_Pos           (0UL)       /*!< TSSAD (Bit 0)                                         */
20643  #define R_ADC0_ADEXICR_TSSAD_Msk           (0x1UL)     /*!< TSSAD (Bitfield-Mask: 0x01)                           */
20644  #define R_ADC0_ADEXICR_EXSEL_Pos           (14UL)      /*!< EXSEL (Bit 14)                                        */
20645  #define R_ADC0_ADEXICR_EXSEL_Msk           (0x4000UL)  /*!< EXSEL (Bitfield-Mask: 0x01)                           */
20646  #define R_ADC0_ADEXICR_EXOEN_Pos           (15UL)      /*!< EXOEN (Bit 15)                                        */
20647  #define R_ADC0_ADEXICR_EXOEN_Msk           (0x8000UL)  /*!< EXOEN (Bitfield-Mask: 0x01)                           */
20648 /* ========================================================  ADANSB  ========================================================= */
20649  #define R_ADC0_ADANSB_ANSB_Pos             (0UL)       /*!< ANSB (Bit 0)                                          */
20650  #define R_ADC0_ADANSB_ANSB_Msk             (0x1UL)     /*!< ANSB (Bitfield-Mask: 0x01)                            */
20651 /* ========================================================  ADDBLDR  ======================================================== */
20652  #define R_ADC0_ADDBLDR_ADDBLDR_Pos         (0UL)       /*!< ADDBLDR (Bit 0)                                       */
20653  #define R_ADC0_ADDBLDR_ADDBLDR_Msk         (0xffffUL)  /*!< ADDBLDR (Bitfield-Mask: 0xffff)                       */
20654 /* ========================================================  ADTSDR  ========================================================= */
20655  #define R_ADC0_ADTSDR_ADTSDR_Pos           (0UL)       /*!< ADTSDR (Bit 0)                                        */
20656  #define R_ADC0_ADTSDR_ADTSDR_Msk           (0xffffUL)  /*!< ADTSDR (Bitfield-Mask: 0xffff)                        */
20657 /* ========================================================  ADOCDR  ========================================================= */
20658  #define R_ADC0_ADOCDR_ADOCDR_Pos           (0UL)       /*!< ADOCDR (Bit 0)                                        */
20659  #define R_ADC0_ADOCDR_ADOCDR_Msk           (0xffffUL)  /*!< ADOCDR (Bitfield-Mask: 0xffff)                        */
20660 /* ======================================================  ADRD_RIGHT  ======================================================= */
20661  #define R_ADC0_ADRD_RIGHT_DIAGST_Pos       (14UL)      /*!< DIAGST (Bit 14)                                       */
20662  #define R_ADC0_ADRD_RIGHT_DIAGST_Msk       (0xc000UL)  /*!< DIAGST (Bitfield-Mask: 0x03)                          */
20663  #define R_ADC0_ADRD_RIGHT_AD_Pos           (0UL)       /*!< AD (Bit 0)                                            */
20664  #define R_ADC0_ADRD_RIGHT_AD_Msk           (0x3fffUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
20665 /* =======================================================  ADRD_LEFT  ======================================================= */
20666  #define R_ADC0_ADRD_LEFT_AD_Pos            (2UL)       /*!< AD (Bit 2)                                            */
20667  #define R_ADC0_ADRD_LEFT_AD_Msk            (0xfffcUL)  /*!< AD (Bitfield-Mask: 0x3fff)                            */
20668  #define R_ADC0_ADRD_LEFT_DIAGST_Pos        (0UL)       /*!< DIAGST (Bit 0)                                        */
20669  #define R_ADC0_ADRD_LEFT_DIAGST_Msk        (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
20670 /* =========================================================  ADDR  ========================================================== */
20671  #define R_ADC0_ADDR_ADDR_Pos               (0UL)       /*!< ADDR (Bit 0)                                          */
20672  #define R_ADC0_ADDR_ADDR_Msk               (0xffffUL)  /*!< ADDR (Bitfield-Mask: 0xffff)                          */
20673 /* ========================================================  ADSHCR  ========================================================= */
20674  #define R_ADC0_ADSHCR_SHANS2_Pos           (10UL)      /*!< SHANS2 (Bit 10)                                       */
20675  #define R_ADC0_ADSHCR_SHANS2_Msk           (0x400UL)   /*!< SHANS2 (Bitfield-Mask: 0x01)                          */
20676  #define R_ADC0_ADSHCR_SHANS1_Pos           (9UL)       /*!< SHANS1 (Bit 9)                                        */
20677  #define R_ADC0_ADSHCR_SHANS1_Msk           (0x200UL)   /*!< SHANS1 (Bitfield-Mask: 0x01)                          */
20678  #define R_ADC0_ADSHCR_SHANS0_Pos           (8UL)       /*!< SHANS0 (Bit 8)                                        */
20679  #define R_ADC0_ADSHCR_SHANS0_Msk           (0x100UL)   /*!< SHANS0 (Bitfield-Mask: 0x01)                          */
20680  #define R_ADC0_ADSHCR_SSTSH_Pos            (0UL)       /*!< SSTSH (Bit 0)                                         */
20681  #define R_ADC0_ADSHCR_SSTSH_Msk            (0xffUL)    /*!< SSTSH (Bitfield-Mask: 0xff)                           */
20682 /* ========================================================  ADDISCR  ======================================================== */
20683  #define R_ADC0_ADDISCR_CHARGE_Pos          (4UL)       /*!< CHARGE (Bit 4)                                        */
20684  #define R_ADC0_ADDISCR_CHARGE_Msk          (0x10UL)    /*!< CHARGE (Bitfield-Mask: 0x01)                          */
20685  #define R_ADC0_ADDISCR_ADNDIS_Pos          (0UL)       /*!< ADNDIS (Bit 0)                                        */
20686  #define R_ADC0_ADDISCR_ADNDIS_Msk          (0xfUL)     /*!< ADNDIS (Bitfield-Mask: 0x0f)                          */
20687 /* ========================================================  ADSHMSR  ======================================================== */
20688  #define R_ADC0_ADSHMSR_SHMD_Pos            (0UL)       /*!< SHMD (Bit 0)                                          */
20689  #define R_ADC0_ADSHMSR_SHMD_Msk            (0x1UL)     /*!< SHMD (Bitfield-Mask: 0x01)                            */
20690 /* ========================================================  ADACSR  ========================================================= */
20691  #define R_ADC0_ADACSR_ADSAC_Pos            (1UL)       /*!< ADSAC (Bit 1)                                         */
20692  #define R_ADC0_ADACSR_ADSAC_Msk            (0x2UL)     /*!< ADSAC (Bitfield-Mask: 0x01)                           */
20693 /* ========================================================  ADGSPCR  ======================================================== */
20694  #define R_ADC0_ADGSPCR_GBRP_Pos            (15UL)      /*!< GBRP (Bit 15)                                         */
20695  #define R_ADC0_ADGSPCR_GBRP_Msk            (0x8000UL)  /*!< GBRP (Bitfield-Mask: 0x01)                            */
20696  #define R_ADC0_ADGSPCR_GBRSCN_Pos          (1UL)       /*!< GBRSCN (Bit 1)                                        */
20697  #define R_ADC0_ADGSPCR_GBRSCN_Msk          (0x2UL)     /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
20698  #define R_ADC0_ADGSPCR_PGS_Pos             (0UL)       /*!< PGS (Bit 0)                                           */
20699  #define R_ADC0_ADGSPCR_PGS_Msk             (0x1UL)     /*!< PGS (Bitfield-Mask: 0x01)                             */
20700  #define R_ADC0_ADGSPCR_GBEXTRG_Pos         (8UL)       /*!< GBEXTRG (Bit 8)                                       */
20701  #define R_ADC0_ADGSPCR_GBEXTRG_Msk         (0x100UL)   /*!< GBEXTRG (Bitfield-Mask: 0x01)                         */
20702 /* =========================================================  ADICR  ========================================================= */
20703  #define R_ADC0_ADICR_ADIC_Pos              (0UL)       /*!< ADIC (Bit 0)                                          */
20704  #define R_ADC0_ADICR_ADIC_Msk              (0x3UL)     /*!< ADIC (Bitfield-Mask: 0x03)                            */
20705 /* =======================================================  ADDBLDRA  ======================================================== */
20706  #define R_ADC0_ADDBLDRA_ADDBLDRA_Pos       (0UL)       /*!< ADDBLDRA (Bit 0)                                      */
20707  #define R_ADC0_ADDBLDRA_ADDBLDRA_Msk       (0xffffUL)  /*!< ADDBLDRA (Bitfield-Mask: 0xffff)                      */
20708 /* =======================================================  ADDBLDRB  ======================================================== */
20709  #define R_ADC0_ADDBLDRB_ADDBLDRB_Pos       (0UL)       /*!< ADDBLDRB (Bit 0)                                      */
20710  #define R_ADC0_ADDBLDRB_ADDBLDRB_Msk       (0xffffUL)  /*!< ADDBLDRB (Bitfield-Mask: 0xffff)                      */
20711 /* ======================================================  ADHVREFCNT  ======================================================= */
20712  #define R_ADC0_ADHVREFCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
20713  #define R_ADC0_ADHVREFCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
20714  #define R_ADC0_ADHVREFCNT_LVSEL_Pos        (4UL)       /*!< LVSEL (Bit 4)                                         */
20715  #define R_ADC0_ADHVREFCNT_LVSEL_Msk        (0x10UL)    /*!< LVSEL (Bitfield-Mask: 0x01)                           */
20716  #define R_ADC0_ADHVREFCNT_HVSEL_Pos        (0UL)       /*!< HVSEL (Bit 0)                                         */
20717  #define R_ADC0_ADHVREFCNT_HVSEL_Msk        (0x3UL)     /*!< HVSEL (Bitfield-Mask: 0x03)                           */
20718 /* =======================================================  ADWINMON  ======================================================== */
20719  #define R_ADC0_ADWINMON_MONCMPB_Pos        (5UL)       /*!< MONCMPB (Bit 5)                                       */
20720  #define R_ADC0_ADWINMON_MONCMPB_Msk        (0x20UL)    /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
20721  #define R_ADC0_ADWINMON_MONCMPA_Pos        (4UL)       /*!< MONCMPA (Bit 4)                                       */
20722  #define R_ADC0_ADWINMON_MONCMPA_Msk        (0x10UL)    /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
20723  #define R_ADC0_ADWINMON_MONCOMB_Pos        (0UL)       /*!< MONCOMB (Bit 0)                                       */
20724  #define R_ADC0_ADWINMON_MONCOMB_Msk        (0x1UL)     /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
20725 /* ========================================================  ADCMPCR  ======================================================== */
20726  #define R_ADC0_ADCMPCR_CMPAIE_Pos          (15UL)      /*!< CMPAIE (Bit 15)                                       */
20727  #define R_ADC0_ADCMPCR_CMPAIE_Msk          (0x8000UL)  /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
20728  #define R_ADC0_ADCMPCR_WCMPE_Pos           (14UL)      /*!< WCMPE (Bit 14)                                        */
20729  #define R_ADC0_ADCMPCR_WCMPE_Msk           (0x4000UL)  /*!< WCMPE (Bitfield-Mask: 0x01)                           */
20730  #define R_ADC0_ADCMPCR_CMPBIE_Pos          (13UL)      /*!< CMPBIE (Bit 13)                                       */
20731  #define R_ADC0_ADCMPCR_CMPBIE_Msk          (0x2000UL)  /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
20732  #define R_ADC0_ADCMPCR_CMPAE_Pos           (11UL)      /*!< CMPAE (Bit 11)                                        */
20733  #define R_ADC0_ADCMPCR_CMPAE_Msk           (0x800UL)   /*!< CMPAE (Bitfield-Mask: 0x01)                           */
20734  #define R_ADC0_ADCMPCR_CMPBE_Pos           (9UL)       /*!< CMPBE (Bit 9)                                         */
20735  #define R_ADC0_ADCMPCR_CMPBE_Msk           (0x200UL)   /*!< CMPBE (Bitfield-Mask: 0x01)                           */
20736  #define R_ADC0_ADCMPCR_CMPAB_Pos           (0UL)       /*!< CMPAB (Bit 0)                                         */
20737  #define R_ADC0_ADCMPCR_CMPAB_Msk           (0x3UL)     /*!< CMPAB (Bitfield-Mask: 0x03)                           */
20738 /* ======================================================  ADCMPANSER  ======================================================= */
20739  #define R_ADC0_ADCMPANSER_CMPOCA_Pos       (1UL)       /*!< CMPOCA (Bit 1)                                        */
20740  #define R_ADC0_ADCMPANSER_CMPOCA_Msk       (0x2UL)     /*!< CMPOCA (Bitfield-Mask: 0x01)                          */
20741  #define R_ADC0_ADCMPANSER_CMPTSA_Pos       (0UL)       /*!< CMPTSA (Bit 0)                                        */
20742  #define R_ADC0_ADCMPANSER_CMPTSA_Msk       (0x1UL)     /*!< CMPTSA (Bitfield-Mask: 0x01)                          */
20743 /* =======================================================  ADCMPLER  ======================================================== */
20744  #define R_ADC0_ADCMPLER_CMPLOCA_Pos        (1UL)       /*!< CMPLOCA (Bit 1)                                       */
20745  #define R_ADC0_ADCMPLER_CMPLOCA_Msk        (0x2UL)     /*!< CMPLOCA (Bitfield-Mask: 0x01)                         */
20746  #define R_ADC0_ADCMPLER_CMPLTSA_Pos        (0UL)       /*!< CMPLTSA (Bit 0)                                       */
20747  #define R_ADC0_ADCMPLER_CMPLTSA_Msk        (0x1UL)     /*!< CMPLTSA (Bitfield-Mask: 0x01)                         */
20748 /* =======================================================  ADCMPANSR  ======================================================= */
20749  #define R_ADC0_ADCMPANSR_CMPCHA_Pos        (0UL)       /*!< CMPCHA (Bit 0)                                        */
20750  #define R_ADC0_ADCMPANSR_CMPCHA_Msk        (0x1UL)     /*!< CMPCHA (Bitfield-Mask: 0x01)                          */
20751 /* ========================================================  ADCMPLR  ======================================================== */
20752  #define R_ADC0_ADCMPLR_CMPLCHA_Pos         (0UL)       /*!< CMPLCHA (Bit 0)                                       */
20753  #define R_ADC0_ADCMPLR_CMPLCHA_Msk         (0x1UL)     /*!< CMPLCHA (Bitfield-Mask: 0x01)                         */
20754 /* =======================================================  ADCMPDR0  ======================================================== */
20755  #define R_ADC0_ADCMPDR0_ADCMPDR0_Pos       (0UL)       /*!< ADCMPDR0 (Bit 0)                                      */
20756  #define R_ADC0_ADCMPDR0_ADCMPDR0_Msk       (0xffffUL)  /*!< ADCMPDR0 (Bitfield-Mask: 0xffff)                      */
20757 /* =======================================================  ADCMPDR1  ======================================================== */
20758  #define R_ADC0_ADCMPDR1_ADCMPDR1_Pos       (0UL)       /*!< ADCMPDR1 (Bit 0)                                      */
20759  #define R_ADC0_ADCMPDR1_ADCMPDR1_Msk       (0xffffUL)  /*!< ADCMPDR1 (Bitfield-Mask: 0xffff)                      */
20760 /* ========================================================  ADCMPSR  ======================================================== */
20761  #define R_ADC0_ADCMPSR_CMPSTCHA_Pos        (0UL)       /*!< CMPSTCHA (Bit 0)                                      */
20762  #define R_ADC0_ADCMPSR_CMPSTCHA_Msk        (0x1UL)     /*!< CMPSTCHA (Bitfield-Mask: 0x01)                        */
20763 /* =======================================================  ADCMPSER  ======================================================== */
20764  #define R_ADC0_ADCMPSER_CMPSTOCA_Pos       (1UL)       /*!< CMPSTOCA (Bit 1)                                      */
20765  #define R_ADC0_ADCMPSER_CMPSTOCA_Msk       (0x2UL)     /*!< CMPSTOCA (Bitfield-Mask: 0x01)                        */
20766  #define R_ADC0_ADCMPSER_CMPSTTSA_Pos       (0UL)       /*!< CMPSTTSA (Bit 0)                                      */
20767  #define R_ADC0_ADCMPSER_CMPSTTSA_Msk       (0x1UL)     /*!< CMPSTTSA (Bitfield-Mask: 0x01)                        */
20768 /* =======================================================  ADCMPBNSR  ======================================================= */
20769  #define R_ADC0_ADCMPBNSR_CMPLB_Pos         (7UL)       /*!< CMPLB (Bit 7)                                         */
20770  #define R_ADC0_ADCMPBNSR_CMPLB_Msk         (0x80UL)    /*!< CMPLB (Bitfield-Mask: 0x01)                           */
20771  #define R_ADC0_ADCMPBNSR_CMPCHB_Pos        (0UL)       /*!< CMPCHB (Bit 0)                                        */
20772  #define R_ADC0_ADCMPBNSR_CMPCHB_Msk        (0x3fUL)    /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
20773 /* =======================================================  ADWINLLB  ======================================================== */
20774  #define R_ADC0_ADWINLLB_ADWINLLB_Pos       (0UL)       /*!< ADWINLLB (Bit 0)                                      */
20775  #define R_ADC0_ADWINLLB_ADWINLLB_Msk       (0xffffUL)  /*!< ADWINLLB (Bitfield-Mask: 0xffff)                      */
20776 /* =======================================================  ADWINULB  ======================================================== */
20777  #define R_ADC0_ADWINULB_ADWINULB_Pos       (0UL)       /*!< ADWINULB (Bit 0)                                      */
20778  #define R_ADC0_ADWINULB_ADWINULB_Msk       (0xffffUL)  /*!< ADWINULB (Bitfield-Mask: 0xffff)                      */
20779 /* =======================================================  ADCMPBSR  ======================================================== */
20780  #define R_ADC0_ADCMPBSR_CMPSTB_Pos         (0UL)       /*!< CMPSTB (Bit 0)                                        */
20781  #define R_ADC0_ADCMPBSR_CMPSTB_Msk         (0x1UL)     /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
20782 /* ========================================================  ADSSTRL  ======================================================== */
20783  #define R_ADC0_ADSSTRL_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
20784  #define R_ADC0_ADSSTRL_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
20785 /* ========================================================  ADSSTRT  ======================================================== */
20786  #define R_ADC0_ADSSTRT_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
20787  #define R_ADC0_ADSSTRT_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
20788 /* ========================================================  ADSSTRO  ======================================================== */
20789  #define R_ADC0_ADSSTRO_SST_Pos             (0UL)       /*!< SST (Bit 0)                                           */
20790  #define R_ADC0_ADSSTRO_SST_Msk             (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
20791 /* ========================================================  ADSSTR  ========================================================= */
20792  #define R_ADC0_ADSSTR_SST_Pos              (0UL)       /*!< SST (Bit 0)                                           */
20793  #define R_ADC0_ADSSTR_SST_Msk              (0xffUL)    /*!< SST (Bitfield-Mask: 0xff)                             */
20794 /* ========================================================  ADPGACR  ======================================================== */
20795  #define R_ADC0_ADPGACR_P002GEN_Pos         (11UL)      /*!< P002GEN (Bit 11)                                      */
20796  #define R_ADC0_ADPGACR_P002GEN_Msk         (0x800UL)   /*!< P002GEN (Bitfield-Mask: 0x01)                         */
20797  #define R_ADC0_ADPGACR_P002ENAMP_Pos       (10UL)      /*!< P002ENAMP (Bit 10)                                    */
20798  #define R_ADC0_ADPGACR_P002ENAMP_Msk       (0x400UL)   /*!< P002ENAMP (Bitfield-Mask: 0x01)                       */
20799  #define R_ADC0_ADPGACR_P002SEL1_Pos        (9UL)       /*!< P002SEL1 (Bit 9)                                      */
20800  #define R_ADC0_ADPGACR_P002SEL1_Msk        (0x200UL)   /*!< P002SEL1 (Bitfield-Mask: 0x01)                        */
20801  #define R_ADC0_ADPGACR_P002SEL0_Pos        (8UL)       /*!< P002SEL0 (Bit 8)                                      */
20802  #define R_ADC0_ADPGACR_P002SEL0_Msk        (0x100UL)   /*!< P002SEL0 (Bitfield-Mask: 0x01)                        */
20803  #define R_ADC0_ADPGACR_P001GEN_Pos         (7UL)       /*!< P001GEN (Bit 7)                                       */
20804  #define R_ADC0_ADPGACR_P001GEN_Msk         (0x80UL)    /*!< P001GEN (Bitfield-Mask: 0x01)                         */
20805  #define R_ADC0_ADPGACR_P001ENAMP_Pos       (6UL)       /*!< P001ENAMP (Bit 6)                                     */
20806  #define R_ADC0_ADPGACR_P001ENAMP_Msk       (0x40UL)    /*!< P001ENAMP (Bitfield-Mask: 0x01)                       */
20807  #define R_ADC0_ADPGACR_P001SEL1_Pos        (5UL)       /*!< P001SEL1 (Bit 5)                                      */
20808  #define R_ADC0_ADPGACR_P001SEL1_Msk        (0x20UL)    /*!< P001SEL1 (Bitfield-Mask: 0x01)                        */
20809  #define R_ADC0_ADPGACR_P001SEL0_Pos        (4UL)       /*!< P001SEL0 (Bit 4)                                      */
20810  #define R_ADC0_ADPGACR_P001SEL0_Msk        (0x10UL)    /*!< P001SEL0 (Bitfield-Mask: 0x01)                        */
20811  #define R_ADC0_ADPGACR_P000GEN_Pos         (3UL)       /*!< P000GEN (Bit 3)                                       */
20812  #define R_ADC0_ADPGACR_P000GEN_Msk         (0x8UL)     /*!< P000GEN (Bitfield-Mask: 0x01)                         */
20813  #define R_ADC0_ADPGACR_P000ENAMP_Pos       (2UL)       /*!< P000ENAMP (Bit 2)                                     */
20814  #define R_ADC0_ADPGACR_P000ENAMP_Msk       (0x4UL)     /*!< P000ENAMP (Bitfield-Mask: 0x01)                       */
20815  #define R_ADC0_ADPGACR_P000SEL1_Pos        (1UL)       /*!< P000SEL1 (Bit 1)                                      */
20816  #define R_ADC0_ADPGACR_P000SEL1_Msk        (0x2UL)     /*!< P000SEL1 (Bitfield-Mask: 0x01)                        */
20817  #define R_ADC0_ADPGACR_P000SEL0_Pos        (0UL)       /*!< P000SEL0 (Bit 0)                                      */
20818  #define R_ADC0_ADPGACR_P000SEL0_Msk        (0x1UL)     /*!< P000SEL0 (Bitfield-Mask: 0x01)                        */
20819  #define R_ADC0_ADPGACR_P003SEL0_Pos        (12UL)      /*!< P003SEL0 (Bit 12)                                     */
20820  #define R_ADC0_ADPGACR_P003SEL0_Msk        (0x1000UL)  /*!< P003SEL0 (Bitfield-Mask: 0x01)                        */
20821  #define R_ADC0_ADPGACR_P003SEL1_Pos        (13UL)      /*!< P003SEL1 (Bit 13)                                     */
20822  #define R_ADC0_ADPGACR_P003SEL1_Msk        (0x2000UL)  /*!< P003SEL1 (Bitfield-Mask: 0x01)                        */
20823  #define R_ADC0_ADPGACR_P003ENAMP_Pos       (14UL)      /*!< P003ENAMP (Bit 14)                                    */
20824  #define R_ADC0_ADPGACR_P003ENAMP_Msk       (0x4000UL)  /*!< P003ENAMP (Bitfield-Mask: 0x01)                       */
20825  #define R_ADC0_ADPGACR_P003GEN_Pos         (15UL)      /*!< P003GEN (Bit 15)                                      */
20826  #define R_ADC0_ADPGACR_P003GEN_Msk         (0x8000UL)  /*!< P003GEN (Bitfield-Mask: 0x01)                         */
20827 /* =========================================================  ADRD  ========================================================== */
20828  #define R_ADC0_ADRD_AD_Pos                 (0UL)       /*!< AD (Bit 0)                                            */
20829  #define R_ADC0_ADRD_AD_Msk                 (0xffffUL)  /*!< AD (Bitfield-Mask: 0xffff)                            */
20830 /* =========================================================  ADRST  ========================================================= */
20831  #define R_ADC0_ADRST_DIAGST_Pos            (0UL)       /*!< DIAGST (Bit 0)                                        */
20832  #define R_ADC0_ADRST_DIAGST_Msk            (0x3UL)     /*!< DIAGST (Bitfield-Mask: 0x03)                          */
20833 /* ======================================================  VREFAMPCNT  ======================================================= */
20834  #define R_ADC0_VREFAMPCNT_VREFADCG_Pos     (1UL)       /*!< VREFADCG (Bit 1)                                      */
20835  #define R_ADC0_VREFAMPCNT_VREFADCG_Msk     (0x6UL)     /*!< VREFADCG (Bitfield-Mask: 0x03)                        */
20836  #define R_ADC0_VREFAMPCNT_VREFADCEN_Pos    (3UL)       /*!< VREFADCEN (Bit 3)                                     */
20837  #define R_ADC0_VREFAMPCNT_VREFADCEN_Msk    (0x8UL)     /*!< VREFADCEN (Bitfield-Mask: 0x01)                       */
20838  #define R_ADC0_VREFAMPCNT_ADSLP_Pos        (7UL)       /*!< ADSLP (Bit 7)                                         */
20839  #define R_ADC0_VREFAMPCNT_ADSLP_Msk        (0x80UL)    /*!< ADSLP (Bitfield-Mask: 0x01)                           */
20840  #define R_ADC0_VREFAMPCNT_OLDETEN_Pos      (0UL)       /*!< OLDETEN (Bit 0)                                       */
20841  #define R_ADC0_VREFAMPCNT_OLDETEN_Msk      (0x1UL)     /*!< OLDETEN (Bitfield-Mask: 0x01)                         */
20842  #define R_ADC0_VREFAMPCNT_BGREN_Pos        (4UL)       /*!< BGREN (Bit 4)                                         */
20843  #define R_ADC0_VREFAMPCNT_BGREN_Msk        (0x10UL)    /*!< BGREN (Bitfield-Mask: 0x01)                           */
20844 /* =======================================================  ADCALEXE  ======================================================== */
20845  #define R_ADC0_ADCALEXE_CALEXE_Pos         (7UL)       /*!< CALEXE (Bit 7)                                        */
20846  #define R_ADC0_ADCALEXE_CALEXE_Msk         (0x80UL)    /*!< CALEXE (Bitfield-Mask: 0x01)                          */
20847  #define R_ADC0_ADCALEXE_CALMON_Pos         (6UL)       /*!< CALMON (Bit 6)                                        */
20848  #define R_ADC0_ADCALEXE_CALMON_Msk         (0x40UL)    /*!< CALMON (Bitfield-Mask: 0x01)                          */
20849 /* ========================================================  ADANIM  ========================================================= */
20850  #define R_ADC0_ADANIM_ANIM_Pos             (0UL)       /*!< ANIM (Bit 0)                                          */
20851  #define R_ADC0_ADANIM_ANIM_Msk             (0x1UL)     /*!< ANIM (Bitfield-Mask: 0x01)                            */
20852 /* =======================================================  ADPGAGS0  ======================================================== */
20853  #define R_ADC0_ADPGAGS0_P002GAIN_Pos       (8UL)       /*!< P002GAIN (Bit 8)                                      */
20854  #define R_ADC0_ADPGAGS0_P002GAIN_Msk       (0xf00UL)   /*!< P002GAIN (Bitfield-Mask: 0x0f)                        */
20855  #define R_ADC0_ADPGAGS0_P001GAIN_Pos       (4UL)       /*!< P001GAIN (Bit 4)                                      */
20856  #define R_ADC0_ADPGAGS0_P001GAIN_Msk       (0xf0UL)    /*!< P001GAIN (Bitfield-Mask: 0x0f)                        */
20857  #define R_ADC0_ADPGAGS0_P000GAIN_Pos       (0UL)       /*!< P000GAIN (Bit 0)                                      */
20858  #define R_ADC0_ADPGAGS0_P000GAIN_Msk       (0xfUL)     /*!< P000GAIN (Bitfield-Mask: 0x0f)                        */
20859  #define R_ADC0_ADPGAGS0_P003GAIN_Pos       (12UL)      /*!< P003GAIN (Bit 12)                                     */
20860  #define R_ADC0_ADPGAGS0_P003GAIN_Msk       (0xf000UL)  /*!< P003GAIN (Bitfield-Mask: 0x0f)                        */
20861 /* =======================================================  ADPGADCR0  ======================================================= */
20862  #define R_ADC0_ADPGADCR0_P003DG_Pos        (12UL)      /*!< P003DG (Bit 12)                                       */
20863  #define R_ADC0_ADPGADCR0_P003DG_Msk        (0x3000UL)  /*!< P003DG (Bitfield-Mask: 0x03)                          */
20864  #define R_ADC0_ADPGADCR0_P002DEN_Pos       (11UL)      /*!< P002DEN (Bit 11)                                      */
20865  #define R_ADC0_ADPGADCR0_P002DEN_Msk       (0x800UL)   /*!< P002DEN (Bitfield-Mask: 0x01)                         */
20866  #define R_ADC0_ADPGADCR0_P002DG_Pos        (8UL)       /*!< P002DG (Bit 8)                                        */
20867  #define R_ADC0_ADPGADCR0_P002DG_Msk        (0x300UL)   /*!< P002DG (Bitfield-Mask: 0x03)                          */
20868  #define R_ADC0_ADPGADCR0_P001DEN_Pos       (7UL)       /*!< P001DEN (Bit 7)                                       */
20869  #define R_ADC0_ADPGADCR0_P001DEN_Msk       (0x80UL)    /*!< P001DEN (Bitfield-Mask: 0x01)                         */
20870  #define R_ADC0_ADPGADCR0_P001DG_Pos        (4UL)       /*!< P001DG (Bit 4)                                        */
20871  #define R_ADC0_ADPGADCR0_P001DG_Msk        (0x30UL)    /*!< P001DG (Bitfield-Mask: 0x03)                          */
20872  #define R_ADC0_ADPGADCR0_P000DEN_Pos       (3UL)       /*!< P000DEN (Bit 3)                                       */
20873  #define R_ADC0_ADPGADCR0_P000DEN_Msk       (0x8UL)     /*!< P000DEN (Bitfield-Mask: 0x01)                         */
20874  #define R_ADC0_ADPGADCR0_P000DG_Pos        (0UL)       /*!< P000DG (Bit 0)                                        */
20875  #define R_ADC0_ADPGADCR0_P000DG_Msk        (0x3UL)     /*!< P000DG (Bitfield-Mask: 0x03)                          */
20876  #define R_ADC0_ADPGADCR0_P003DEN_Pos       (15UL)      /*!< P003DEN (Bit 15)                                      */
20877  #define R_ADC0_ADPGADCR0_P003DEN_Msk       (0x8000UL)  /*!< P003DEN (Bitfield-Mask: 0x01)                         */
20878 /* =========================================================  ADREF  ========================================================= */
20879  #define R_ADC0_ADREF_ADF_Pos               (0UL)       /*!< ADF (Bit 0)                                           */
20880  #define R_ADC0_ADREF_ADF_Msk               (0x1UL)     /*!< ADF (Bitfield-Mask: 0x01)                             */
20881  #define R_ADC0_ADREF_ADSCACT_Pos           (7UL)       /*!< ADSCACT (Bit 7)                                       */
20882  #define R_ADC0_ADREF_ADSCACT_Msk           (0x80UL)    /*!< ADSCACT (Bitfield-Mask: 0x01)                         */
20883 /* ========================================================  ADEXREF  ======================================================== */
20884  #define R_ADC0_ADEXREF_GBADF_Pos           (0UL)       /*!< GBADF (Bit 0)                                         */
20885  #define R_ADC0_ADEXREF_GBADF_Msk           (0x1UL)     /*!< GBADF (Bitfield-Mask: 0x01)                           */
20886 /* =======================================================  ADAMPOFF  ======================================================== */
20887  #define R_ADC0_ADAMPOFF_OPOFF_Pos          (0UL)       /*!< OPOFF (Bit 0)                                         */
20888  #define R_ADC0_ADAMPOFF_OPOFF_Msk          (0xffUL)    /*!< OPOFF (Bitfield-Mask: 0xff)                           */
20889 /* ========================================================  ADTSTPR  ======================================================== */
20890  #define R_ADC0_ADTSTPR_PRO_Pos             (0UL)       /*!< PRO (Bit 0)                                           */
20891  #define R_ADC0_ADTSTPR_PRO_Msk             (0x1UL)     /*!< PRO (Bitfield-Mask: 0x01)                             */
20892  #define R_ADC0_ADTSTPR_B0WI_Pos            (1UL)       /*!< B0WI (Bit 1)                                          */
20893  #define R_ADC0_ADTSTPR_B0WI_Msk            (0x2UL)     /*!< B0WI (Bitfield-Mask: 0x01)                            */
20894 /* =======================================================  ADDDACER  ======================================================== */
20895  #define R_ADC0_ADDDACER_WRION_Pos          (0UL)       /*!< WRION (Bit 0)                                         */
20896  #define R_ADC0_ADDDACER_WRION_Msk          (0x1fUL)    /*!< WRION (Bitfield-Mask: 0x1f)                           */
20897  #define R_ADC0_ADDDACER_WRIOFF_Pos         (8UL)       /*!< WRIOFF (Bit 8)                                        */
20898  #define R_ADC0_ADDDACER_WRIOFF_Msk         (0x1f00UL)  /*!< WRIOFF (Bitfield-Mask: 0x1f)                          */
20899  #define R_ADC0_ADDDACER_ADHS_Pos           (15UL)      /*!< ADHS (Bit 15)                                         */
20900  #define R_ADC0_ADDDACER_ADHS_Msk           (0x8000UL)  /*!< ADHS (Bitfield-Mask: 0x01)                            */
20901 /* =======================================================  ADEXTSTR  ======================================================== */
20902  #define R_ADC0_ADEXTSTR_SHTEST_Pos         (0UL)       /*!< SHTEST (Bit 0)                                        */
20903  #define R_ADC0_ADEXTSTR_SHTEST_Msk         (0x7UL)     /*!< SHTEST (Bitfield-Mask: 0x07)                          */
20904  #define R_ADC0_ADEXTSTR_SWTST_Pos          (4UL)       /*!< SWTST (Bit 4)                                         */
20905  #define R_ADC0_ADEXTSTR_SWTST_Msk          (0x30UL)    /*!< SWTST (Bitfield-Mask: 0x03)                           */
20906  #define R_ADC0_ADEXTSTR_SHTRM_Pos          (8UL)       /*!< SHTRM (Bit 8)                                         */
20907  #define R_ADC0_ADEXTSTR_SHTRM_Msk          (0x300UL)   /*!< SHTRM (Bitfield-Mask: 0x03)                           */
20908  #define R_ADC0_ADEXTSTR_ADTRM3_Pos         (11UL)      /*!< ADTRM3 (Bit 11)                                       */
20909  #define R_ADC0_ADEXTSTR_ADTRM3_Msk         (0x800UL)   /*!< ADTRM3 (Bitfield-Mask: 0x01)                          */
20910  #define R_ADC0_ADEXTSTR_ADTRM2_Pos         (12UL)      /*!< ADTRM2 (Bit 12)                                       */
20911  #define R_ADC0_ADEXTSTR_ADTRM2_Msk         (0x3000UL)  /*!< ADTRM2 (Bitfield-Mask: 0x03)                          */
20912  #define R_ADC0_ADEXTSTR_ADTRM1_Pos         (14UL)      /*!< ADTRM1 (Bit 14)                                       */
20913  #define R_ADC0_ADEXTSTR_ADTRM1_Msk         (0xc000UL)  /*!< ADTRM1 (Bitfield-Mask: 0x03)                          */
20914 /* ========================================================  ADTSTRA  ======================================================== */
20915  #define R_ADC0_ADTSTRA_ATBUSSEL_Pos        (0UL)       /*!< ATBUSSEL (Bit 0)                                      */
20916  #define R_ADC0_ADTSTRA_ATBUSSEL_Msk        (0x1UL)     /*!< ATBUSSEL (Bitfield-Mask: 0x01)                        */
20917  #define R_ADC0_ADTSTRA_TSTSWREF_Pos        (1UL)       /*!< TSTSWREF (Bit 1)                                      */
20918  #define R_ADC0_ADTSTRA_TSTSWREF_Msk        (0xeUL)     /*!< TSTSWREF (Bitfield-Mask: 0x07)                        */
20919  #define R_ADC0_ADTSTRA_OCSW_Pos            (5UL)       /*!< OCSW (Bit 5)                                          */
20920  #define R_ADC0_ADTSTRA_OCSW_Msk            (0x20UL)    /*!< OCSW (Bitfield-Mask: 0x01)                            */
20921  #define R_ADC0_ADTSTRA_TSSW_Pos            (6UL)       /*!< TSSW (Bit 6)                                          */
20922  #define R_ADC0_ADTSTRA_TSSW_Msk            (0x40UL)    /*!< TSSW (Bitfield-Mask: 0x01)                            */
20923  #define R_ADC0_ADTSTRA_ADTEST_AD_Pos       (8UL)       /*!< ADTEST_AD (Bit 8)                                     */
20924  #define R_ADC0_ADTSTRA_ADTEST_AD_Msk       (0xf00UL)   /*!< ADTEST_AD (Bitfield-Mask: 0x0f)                       */
20925  #define R_ADC0_ADTSTRA_ADTEST_IO_Pos       (12UL)      /*!< ADTEST_IO (Bit 12)                                    */
20926  #define R_ADC0_ADTSTRA_ADTEST_IO_Msk       (0xf000UL)  /*!< ADTEST_IO (Bitfield-Mask: 0x0f)                       */
20927 /* ========================================================  ADTSTRB  ======================================================== */
20928  #define R_ADC0_ADTSTRB_ADVAL_Pos           (0UL)       /*!< ADVAL (Bit 0)                                         */
20929  #define R_ADC0_ADTSTRB_ADVAL_Msk           (0x7fffUL)  /*!< ADVAL (Bitfield-Mask: 0x7fff)                         */
20930 /* ========================================================  ADTSTRC  ======================================================== */
20931  #define R_ADC0_ADTSTRC_ADMD_Pos            (0UL)       /*!< ADMD (Bit 0)                                          */
20932  #define R_ADC0_ADTSTRC_ADMD_Msk            (0xffUL)    /*!< ADMD (Bitfield-Mask: 0xff)                            */
20933  #define R_ADC0_ADTSTRC_SYNCERR_Pos         (12UL)      /*!< SYNCERR (Bit 12)                                      */
20934  #define R_ADC0_ADTSTRC_SYNCERR_Msk         (0x1000UL)  /*!< SYNCERR (Bitfield-Mask: 0x01)                         */
20935 /* ========================================================  ADTSTRD  ======================================================== */
20936  #define R_ADC0_ADTSTRD_ADVAL16_Pos         (0UL)       /*!< ADVAL16 (Bit 0)                                       */
20937  #define R_ADC0_ADTSTRD_ADVAL16_Msk         (0x1UL)     /*!< ADVAL16 (Bitfield-Mask: 0x01)                         */
20938 /* =======================================================  ADSWTSTR0  ======================================================= */
20939  #define R_ADC0_ADSWTSTR0_CHSW00_Pos        (0UL)       /*!< CHSW00 (Bit 0)                                        */
20940  #define R_ADC0_ADSWTSTR0_CHSW00_Msk        (0x1UL)     /*!< CHSW00 (Bitfield-Mask: 0x01)                          */
20941  #define R_ADC0_ADSWTSTR0_CHSW01_Pos        (1UL)       /*!< CHSW01 (Bit 1)                                        */
20942  #define R_ADC0_ADSWTSTR0_CHSW01_Msk        (0x2UL)     /*!< CHSW01 (Bitfield-Mask: 0x01)                          */
20943  #define R_ADC0_ADSWTSTR0_CHSW02_Pos        (2UL)       /*!< CHSW02 (Bit 2)                                        */
20944  #define R_ADC0_ADSWTSTR0_CHSW02_Msk        (0x4UL)     /*!< CHSW02 (Bitfield-Mask: 0x01)                          */
20945  #define R_ADC0_ADSWTSTR0_CHSW03_Pos        (3UL)       /*!< CHSW03 (Bit 3)                                        */
20946  #define R_ADC0_ADSWTSTR0_CHSW03_Msk        (0x8UL)     /*!< CHSW03 (Bitfield-Mask: 0x01)                          */
20947  #define R_ADC0_ADSWTSTR0_CHSW04_Pos        (4UL)       /*!< CHSW04 (Bit 4)                                        */
20948  #define R_ADC0_ADSWTSTR0_CHSW04_Msk        (0x10UL)    /*!< CHSW04 (Bitfield-Mask: 0x01)                          */
20949  #define R_ADC0_ADSWTSTR0_CHSW05_Pos        (5UL)       /*!< CHSW05 (Bit 5)                                        */
20950  #define R_ADC0_ADSWTSTR0_CHSW05_Msk        (0x20UL)    /*!< CHSW05 (Bitfield-Mask: 0x01)                          */
20951 /* =======================================================  ADSWTSTR1  ======================================================= */
20952  #define R_ADC0_ADSWTSTR1_CHSW16_Pos        (0UL)       /*!< CHSW16 (Bit 0)                                        */
20953  #define R_ADC0_ADSWTSTR1_CHSW16_Msk        (0x1UL)     /*!< CHSW16 (Bitfield-Mask: 0x01)                          */
20954  #define R_ADC0_ADSWTSTR1_CHSW17_Pos        (1UL)       /*!< CHSW17 (Bit 1)                                        */
20955  #define R_ADC0_ADSWTSTR1_CHSW17_Msk        (0x2UL)     /*!< CHSW17 (Bitfield-Mask: 0x01)                          */
20956  #define R_ADC0_ADSWTSTR1_CHSW18_Pos        (2UL)       /*!< CHSW18 (Bit 2)                                        */
20957  #define R_ADC0_ADSWTSTR1_CHSW18_Msk        (0x4UL)     /*!< CHSW18 (Bitfield-Mask: 0x01)                          */
20958  #define R_ADC0_ADSWTSTR1_CHSW19_Pos        (3UL)       /*!< CHSW19 (Bit 3)                                        */
20959  #define R_ADC0_ADSWTSTR1_CHSW19_Msk        (0x8UL)     /*!< CHSW19 (Bitfield-Mask: 0x01)                          */
20960  #define R_ADC0_ADSWTSTR1_CHSW20_Pos        (4UL)       /*!< CHSW20 (Bit 4)                                        */
20961  #define R_ADC0_ADSWTSTR1_CHSW20_Msk        (0x10UL)    /*!< CHSW20 (Bitfield-Mask: 0x01)                          */
20962  #define R_ADC0_ADSWTSTR1_CHSW21_Pos        (5UL)       /*!< CHSW21 (Bit 5)                                        */
20963  #define R_ADC0_ADSWTSTR1_CHSW21_Msk        (0x20UL)    /*!< CHSW21 (Bitfield-Mask: 0x01)                          */
20964 /* =======================================================  ADSWTSTR2  ======================================================= */
20965  #define R_ADC0_ADSWTSTR2_EX0SW_Pos         (0UL)       /*!< EX0SW (Bit 0)                                         */
20966  #define R_ADC0_ADSWTSTR2_EX0SW_Msk         (0x1UL)     /*!< EX0SW (Bitfield-Mask: 0x01)                           */
20967  #define R_ADC0_ADSWTSTR2_EX1SW_Pos         (1UL)       /*!< EX1SW (Bit 1)                                         */
20968  #define R_ADC0_ADSWTSTR2_EX1SW_Msk         (0x2UL)     /*!< EX1SW (Bitfield-Mask: 0x01)                           */
20969  #define R_ADC0_ADSWTSTR2_SHBYPS0_Pos       (4UL)       /*!< SHBYPS0 (Bit 4)                                       */
20970  #define R_ADC0_ADSWTSTR2_SHBYPS0_Msk       (0x10UL)    /*!< SHBYPS0 (Bitfield-Mask: 0x01)                         */
20971  #define R_ADC0_ADSWTSTR2_SHBYPS1_Pos       (5UL)       /*!< SHBYPS1 (Bit 5)                                       */
20972  #define R_ADC0_ADSWTSTR2_SHBYPS1_Msk       (0x20UL)    /*!< SHBYPS1 (Bitfield-Mask: 0x01)                         */
20973  #define R_ADC0_ADSWTSTR2_SHBYPS2_Pos       (6UL)       /*!< SHBYPS2 (Bit 6)                                       */
20974  #define R_ADC0_ADSWTSTR2_SHBYPS2_Msk       (0x40UL)    /*!< SHBYPS2 (Bitfield-Mask: 0x01)                         */
20975  #define R_ADC0_ADSWTSTR2_GRP0SW_Pos        (8UL)       /*!< GRP0SW (Bit 8)                                        */
20976  #define R_ADC0_ADSWTSTR2_GRP0SW_Msk        (0x100UL)   /*!< GRP0SW (Bitfield-Mask: 0x01)                          */
20977  #define R_ADC0_ADSWTSTR2_GRP1SW_Pos        (9UL)       /*!< GRP1SW (Bit 9)                                        */
20978  #define R_ADC0_ADSWTSTR2_GRP1SW_Msk        (0x200UL)   /*!< GRP1SW (Bitfield-Mask: 0x01)                          */
20979  #define R_ADC0_ADSWTSTR2_GRP2SW_Pos        (10UL)      /*!< GRP2SW (Bit 10)                                       */
20980  #define R_ADC0_ADSWTSTR2_GRP2SW_Msk        (0x400UL)   /*!< GRP2SW (Bitfield-Mask: 0x01)                          */
20981  #define R_ADC0_ADSWTSTR2_GRP3SW_Pos        (11UL)      /*!< GRP3SW (Bit 11)                                       */
20982  #define R_ADC0_ADSWTSTR2_GRP3SW_Msk        (0x800UL)   /*!< GRP3SW (Bitfield-Mask: 0x01)                          */
20983  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Pos      (12UL)      /*!< GRPEX1SW (Bit 12)                                     */
20984  #define R_ADC0_ADSWTSTR2_GRPEX1SW_Msk      (0x1000UL)  /*!< GRPEX1SW (Bitfield-Mask: 0x01)                        */
20985 /* ========================================================  ADSWCR  ========================================================= */
20986  #define R_ADC0_ADSWCR_ADSWREF_Pos          (0UL)       /*!< ADSWREF (Bit 0)                                       */
20987  #define R_ADC0_ADSWCR_ADSWREF_Msk          (0x7UL)     /*!< ADSWREF (Bitfield-Mask: 0x07)                         */
20988  #define R_ADC0_ADSWCR_SHSWREF_Pos          (4UL)       /*!< SHSWREF (Bit 4)                                       */
20989  #define R_ADC0_ADSWCR_SHSWREF_Msk          (0x70UL)    /*!< SHSWREF (Bitfield-Mask: 0x07)                         */
20990 /* ========================================================  ADGSCS  ========================================================= */
20991  #define R_ADC0_ADGSCS_CHSELGB_Pos          (0UL)       /*!< CHSELGB (Bit 0)                                       */
20992  #define R_ADC0_ADGSCS_CHSELGB_Msk          (0xffUL)    /*!< CHSELGB (Bitfield-Mask: 0xff)                         */
20993  #define R_ADC0_ADGSCS_CHSELGA_Pos          (8UL)       /*!< CHSELGA (Bit 8)                                       */
20994  #define R_ADC0_ADGSCS_CHSELGA_Msk          (0xff00UL)  /*!< CHSELGA (Bitfield-Mask: 0xff)                         */
20995 /* =========================================================  ADSER  ========================================================= */
20996  #define R_ADC0_ADSER_SMPEX_Pos             (7UL)       /*!< SMPEX (Bit 7)                                         */
20997  #define R_ADC0_ADSER_SMPEX_Msk             (0x80UL)    /*!< SMPEX (Bitfield-Mask: 0x01)                           */
20998 /* ========================================================  ADBUF0  ========================================================= */
20999  #define R_ADC0_ADBUF0_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21000  #define R_ADC0_ADBUF0_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21001 /* ========================================================  ADBUF1  ========================================================= */
21002  #define R_ADC0_ADBUF1_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21003  #define R_ADC0_ADBUF1_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21004 /* ========================================================  ADBUF2  ========================================================= */
21005  #define R_ADC0_ADBUF2_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21006  #define R_ADC0_ADBUF2_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21007 /* ========================================================  ADBUF3  ========================================================= */
21008  #define R_ADC0_ADBUF3_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21009  #define R_ADC0_ADBUF3_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21010 /* ========================================================  ADBUF4  ========================================================= */
21011  #define R_ADC0_ADBUF4_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21012  #define R_ADC0_ADBUF4_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21013 /* ========================================================  ADBUF5  ========================================================= */
21014  #define R_ADC0_ADBUF5_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21015  #define R_ADC0_ADBUF5_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21016 /* ========================================================  ADBUF6  ========================================================= */
21017  #define R_ADC0_ADBUF6_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21018  #define R_ADC0_ADBUF6_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21019 /* ========================================================  ADBUF7  ========================================================= */
21020  #define R_ADC0_ADBUF7_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21021  #define R_ADC0_ADBUF7_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21022 /* ========================================================  ADBUF8  ========================================================= */
21023  #define R_ADC0_ADBUF8_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21024  #define R_ADC0_ADBUF8_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21025 /* ========================================================  ADBUF9  ========================================================= */
21026  #define R_ADC0_ADBUF9_ADBUF_Pos            (0UL)       /*!< ADBUF (Bit 0)                                         */
21027  #define R_ADC0_ADBUF9_ADBUF_Msk            (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21028 /* ========================================================  ADBUF10  ======================================================== */
21029  #define R_ADC0_ADBUF10_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21030  #define R_ADC0_ADBUF10_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21031 /* ========================================================  ADBUF11  ======================================================== */
21032  #define R_ADC0_ADBUF11_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21033  #define R_ADC0_ADBUF11_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21034 /* ========================================================  ADBUF12  ======================================================== */
21035  #define R_ADC0_ADBUF12_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21036  #define R_ADC0_ADBUF12_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21037 /* ========================================================  ADBUF13  ======================================================== */
21038  #define R_ADC0_ADBUF13_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21039  #define R_ADC0_ADBUF13_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21040 /* ========================================================  ADBUF14  ======================================================== */
21041  #define R_ADC0_ADBUF14_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21042  #define R_ADC0_ADBUF14_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21043 /* ========================================================  ADBUF15  ======================================================== */
21044  #define R_ADC0_ADBUF15_ADBUF_Pos           (0UL)       /*!< ADBUF (Bit 0)                                         */
21045  #define R_ADC0_ADBUF15_ADBUF_Msk           (0xffffUL)  /*!< ADBUF (Bitfield-Mask: 0xffff)                         */
21046 /* ========================================================  ADBUFEN  ======================================================== */
21047  #define R_ADC0_ADBUFEN_BUFEN_Pos           (0UL)       /*!< BUFEN (Bit 0)                                         */
21048  #define R_ADC0_ADBUFEN_BUFEN_Msk           (0x1UL)     /*!< BUFEN (Bitfield-Mask: 0x01)                           */
21049 /* =======================================================  ADBUFPTR  ======================================================== */
21050  #define R_ADC0_ADBUFPTR_BUFPTR_Pos         (0UL)       /*!< BUFPTR (Bit 0)                                        */
21051  #define R_ADC0_ADBUFPTR_BUFPTR_Msk         (0xfUL)     /*!< BUFPTR (Bitfield-Mask: 0x0f)                          */
21052  #define R_ADC0_ADBUFPTR_PTROVF_Pos         (4UL)       /*!< PTROVF (Bit 4)                                        */
21053  #define R_ADC0_ADBUFPTR_PTROVF_Msk         (0x10UL)    /*!< PTROVF (Bitfield-Mask: 0x01)                          */
21054 /* =======================================================  ADPGADBS0  ======================================================= */
21055  #define R_ADC0_ADPGADBS0_P0BIAS_Pos        (0UL)       /*!< P0BIAS (Bit 0)                                        */
21056  #define R_ADC0_ADPGADBS0_P0BIAS_Msk        (0x1UL)     /*!< P0BIAS (Bitfield-Mask: 0x01)                          */
21057 /* =======================================================  ADPGADBS1  ======================================================= */
21058  #define R_ADC0_ADPGADBS1_P3BIAS_Pos        (0UL)       /*!< P3BIAS (Bit 0)                                        */
21059  #define R_ADC0_ADPGADBS1_P3BIAS_Msk        (0x1UL)     /*!< P3BIAS (Bitfield-Mask: 0x01)                          */
21060 /* =======================================================  ADREFMON  ======================================================== */
21061  #define R_ADC0_ADREFMON_PGAMON_Pos         (0UL)       /*!< PGAMON (Bit 0)                                        */
21062  #define R_ADC0_ADREFMON_PGAMON_Msk         (0x7UL)     /*!< PGAMON (Bitfield-Mask: 0x07)                          */
21063  #define R_ADC0_ADREFMON_MONSEL_Pos         (16UL)      /*!< MONSEL (Bit 16)                                       */
21064  #define R_ADC0_ADREFMON_MONSEL_Msk         (0xf0000UL) /*!< MONSEL (Bitfield-Mask: 0x0f)                          */
21065 
21066 /* =========================================================================================================================== */
21067 /* ================                                          R_PSCU                                           ================ */
21068 /* =========================================================================================================================== */
21069 
21070 /* =========================================================  PSARB  ========================================================= */
21071  #define R_PSCU_PSARB_PSARB1_Pos     (1UL)          /*!< PSARB1 (Bit 1)                                        */
21072  #define R_PSCU_PSARB_PSARB1_Msk     (0x2UL)        /*!< PSARB1 (Bitfield-Mask: 0x01)                          */
21073  #define R_PSCU_PSARB_PSARB2_Pos     (2UL)          /*!< PSARB2 (Bit 2)                                        */
21074  #define R_PSCU_PSARB_PSARB2_Msk     (0x4UL)        /*!< PSARB2 (Bitfield-Mask: 0x01)                          */
21075  #define R_PSCU_PSARB_PSARB3_Pos     (3UL)          /*!< PSARB3 (Bit 3)                                        */
21076  #define R_PSCU_PSARB_PSARB3_Msk     (0x8UL)        /*!< PSARB3 (Bitfield-Mask: 0x01)                          */
21077  #define R_PSCU_PSARB_PSARB6_Pos     (6UL)          /*!< PSARB6 (Bit 6)                                        */
21078  #define R_PSCU_PSARB_PSARB6_Msk     (0x40UL)       /*!< PSARB6 (Bitfield-Mask: 0x01)                          */
21079  #define R_PSCU_PSARB_PSARB7_Pos     (7UL)          /*!< PSARB7 (Bit 7)                                        */
21080  #define R_PSCU_PSARB_PSARB7_Msk     (0x80UL)       /*!< PSARB7 (Bitfield-Mask: 0x01)                          */
21081  #define R_PSCU_PSARB_PSARB8_Pos     (8UL)          /*!< PSARB8 (Bit 8)                                        */
21082  #define R_PSCU_PSARB_PSARB8_Msk     (0x100UL)      /*!< PSARB8 (Bitfield-Mask: 0x01)                          */
21083  #define R_PSCU_PSARB_PSARB9_Pos     (9UL)          /*!< PSARB9 (Bit 9)                                        */
21084  #define R_PSCU_PSARB_PSARB9_Msk     (0x200UL)      /*!< PSARB9 (Bitfield-Mask: 0x01)                          */
21085  #define R_PSCU_PSARB_PSARB11_Pos    (11UL)         /*!< PSARB11 (Bit 11)                                      */
21086  #define R_PSCU_PSARB_PSARB11_Msk    (0x800UL)      /*!< PSARB11 (Bitfield-Mask: 0x01)                         */
21087  #define R_PSCU_PSARB_PSARB12_Pos    (12UL)         /*!< PSARB12 (Bit 12)                                      */
21088  #define R_PSCU_PSARB_PSARB12_Msk    (0x1000UL)     /*!< PSARB12 (Bitfield-Mask: 0x01)                         */
21089  #define R_PSCU_PSARB_PSARB15_Pos    (15UL)         /*!< PSARB15 (Bit 15)                                      */
21090  #define R_PSCU_PSARB_PSARB15_Msk    (0x8000UL)     /*!< PSARB15 (Bitfield-Mask: 0x01)                         */
21091  #define R_PSCU_PSARB_PSARB16_Pos    (16UL)         /*!< PSARB16 (Bit 16)                                      */
21092  #define R_PSCU_PSARB_PSARB16_Msk    (0x10000UL)    /*!< PSARB16 (Bitfield-Mask: 0x01)                         */
21093  #define R_PSCU_PSARB_PSARB18_Pos    (18UL)         /*!< PSARB18 (Bit 18)                                      */
21094  #define R_PSCU_PSARB_PSARB18_Msk    (0x40000UL)    /*!< PSARB18 (Bitfield-Mask: 0x01)                         */
21095  #define R_PSCU_PSARB_PSARB19_Pos    (19UL)         /*!< PSARB19 (Bit 19)                                      */
21096  #define R_PSCU_PSARB_PSARB19_Msk    (0x80000UL)    /*!< PSARB19 (Bitfield-Mask: 0x01)                         */
21097  #define R_PSCU_PSARB_PSARB22_Pos    (22UL)         /*!< PSARB22 (Bit 22)                                      */
21098  #define R_PSCU_PSARB_PSARB22_Msk    (0x400000UL)   /*!< PSARB22 (Bitfield-Mask: 0x01)                         */
21099  #define R_PSCU_PSARB_PSARB23_Pos    (23UL)         /*!< PSARB23 (Bit 23)                                      */
21100  #define R_PSCU_PSARB_PSARB23_Msk    (0x800000UL)   /*!< PSARB23 (Bitfield-Mask: 0x01)                         */
21101  #define R_PSCU_PSARB_PSARB24_Pos    (24UL)         /*!< PSARB24 (Bit 24)                                      */
21102  #define R_PSCU_PSARB_PSARB24_Msk    (0x1000000UL)  /*!< PSARB24 (Bitfield-Mask: 0x01)                         */
21103  #define R_PSCU_PSARB_PSARB25_Pos    (25UL)         /*!< PSARB25 (Bit 25)                                      */
21104  #define R_PSCU_PSARB_PSARB25_Msk    (0x2000000UL)  /*!< PSARB25 (Bitfield-Mask: 0x01)                         */
21105  #define R_PSCU_PSARB_PSARB26_Pos    (26UL)         /*!< PSARB26 (Bit 26)                                      */
21106  #define R_PSCU_PSARB_PSARB26_Msk    (0x4000000UL)  /*!< PSARB26 (Bitfield-Mask: 0x01)                         */
21107  #define R_PSCU_PSARB_PSARB27_Pos    (27UL)         /*!< PSARB27 (Bit 27)                                      */
21108  #define R_PSCU_PSARB_PSARB27_Msk    (0x8000000UL)  /*!< PSARB27 (Bitfield-Mask: 0x01)                         */
21109  #define R_PSCU_PSARB_PSARB28_Pos    (28UL)         /*!< PSARB28 (Bit 28)                                      */
21110  #define R_PSCU_PSARB_PSARB28_Msk    (0x10000000UL) /*!< PSARB28 (Bitfield-Mask: 0x01)                         */
21111  #define R_PSCU_PSARB_PSARB29_Pos    (29UL)         /*!< PSARB29 (Bit 29)                                      */
21112  #define R_PSCU_PSARB_PSARB29_Msk    (0x20000000UL) /*!< PSARB29 (Bitfield-Mask: 0x01)                         */
21113  #define R_PSCU_PSARB_PSARB30_Pos    (30UL)         /*!< PSARB30 (Bit 30)                                      */
21114  #define R_PSCU_PSARB_PSARB30_Msk    (0x40000000UL) /*!< PSARB30 (Bitfield-Mask: 0x01)                         */
21115  #define R_PSCU_PSARB_PSARB31_Pos    (31UL)         /*!< PSARB31 (Bit 31)                                      */
21116  #define R_PSCU_PSARB_PSARB31_Msk    (0x80000000UL) /*!< PSARB31 (Bitfield-Mask: 0x01)                         */
21117 /* =========================================================  PSARC  ========================================================= */
21118  #define R_PSCU_PSARC_PSARC0_Pos     (0UL)          /*!< PSARC0 (Bit 0)                                        */
21119  #define R_PSCU_PSARC_PSARC0_Msk     (0x1UL)        /*!< PSARC0 (Bitfield-Mask: 0x01)                          */
21120  #define R_PSCU_PSARC_PSARC1_Pos     (1UL)          /*!< PSARC1 (Bit 1)                                        */
21121  #define R_PSCU_PSARC_PSARC1_Msk     (0x2UL)        /*!< PSARC1 (Bitfield-Mask: 0x01)                          */
21122  #define R_PSCU_PSARC_PSARC3_Pos     (3UL)          /*!< PSARC3 (Bit 3)                                        */
21123  #define R_PSCU_PSARC_PSARC3_Msk     (0x8UL)        /*!< PSARC3 (Bitfield-Mask: 0x01)                          */
21124  #define R_PSCU_PSARC_PSARC8_Pos     (8UL)          /*!< PSARC8 (Bit 8)                                        */
21125  #define R_PSCU_PSARC_PSARC8_Msk     (0x100UL)      /*!< PSARC8 (Bitfield-Mask: 0x01)                          */
21126  #define R_PSCU_PSARC_PSARC12_Pos    (12UL)         /*!< PSARC12 (Bit 12)                                      */
21127  #define R_PSCU_PSARC_PSARC12_Msk    (0x1000UL)     /*!< PSARC12 (Bitfield-Mask: 0x01)                         */
21128  #define R_PSCU_PSARC_PSARC13_Pos    (13UL)         /*!< PSARC13 (Bit 13)                                      */
21129  #define R_PSCU_PSARC_PSARC13_Msk    (0x2000UL)     /*!< PSARC13 (Bitfield-Mask: 0x01)                         */
21130  #define R_PSCU_PSARC_PSARC20_Pos    (20UL)         /*!< PSARC20 (Bit 20)                                      */
21131  #define R_PSCU_PSARC_PSARC20_Msk    (0x100000UL)   /*!< PSARC20 (Bitfield-Mask: 0x01)                         */
21132  #define R_PSCU_PSARC_PSARC27_Pos    (27UL)         /*!< PSARC27 (Bit 27)                                      */
21133  #define R_PSCU_PSARC_PSARC27_Msk    (0x8000000UL)  /*!< PSARC27 (Bitfield-Mask: 0x01)                         */
21134  #define R_PSCU_PSARC_PSARC31_Pos    (31UL)         /*!< PSARC31 (Bit 31)                                      */
21135  #define R_PSCU_PSARC_PSARC31_Msk    (0x80000000UL) /*!< PSARC31 (Bitfield-Mask: 0x01)                         */
21136 /* =========================================================  PSARD  ========================================================= */
21137  #define R_PSCU_PSARD_PSARD0_Pos     (0UL)          /*!< PSARD0 (Bit 0)                                        */
21138  #define R_PSCU_PSARD_PSARD0_Msk     (0x1UL)        /*!< PSARD0 (Bitfield-Mask: 0x01)                          */
21139  #define R_PSCU_PSARD_PSARD1_Pos     (1UL)          /*!< PSARD1 (Bit 1)                                        */
21140  #define R_PSCU_PSARD_PSARD1_Msk     (0x2UL)        /*!< PSARD1 (Bitfield-Mask: 0x01)                          */
21141  #define R_PSCU_PSARD_PSARD2_Pos     (2UL)          /*!< PSARD2 (Bit 2)                                        */
21142  #define R_PSCU_PSARD_PSARD2_Msk     (0x4UL)        /*!< PSARD2 (Bitfield-Mask: 0x01)                          */
21143  #define R_PSCU_PSARD_PSARD3_Pos     (3UL)          /*!< PSARD3 (Bit 3)                                        */
21144  #define R_PSCU_PSARD_PSARD3_Msk     (0x8UL)        /*!< PSARD3 (Bitfield-Mask: 0x01)                          */
21145  #define R_PSCU_PSARD_PSARD11_Pos    (11UL)         /*!< PSARD11 (Bit 11)                                      */
21146  #define R_PSCU_PSARD_PSARD11_Msk    (0x800UL)      /*!< PSARD11 (Bitfield-Mask: 0x01)                         */
21147  #define R_PSCU_PSARD_PSARD12_Pos    (12UL)         /*!< PSARD12 (Bit 12)                                      */
21148  #define R_PSCU_PSARD_PSARD12_Msk    (0x1000UL)     /*!< PSARD12 (Bitfield-Mask: 0x01)                         */
21149  #define R_PSCU_PSARD_PSARD13_Pos    (13UL)         /*!< PSARD13 (Bit 13)                                      */
21150  #define R_PSCU_PSARD_PSARD13_Msk    (0x2000UL)     /*!< PSARD13 (Bitfield-Mask: 0x01)                         */
21151  #define R_PSCU_PSARD_PSARD14_Pos    (14UL)         /*!< PSARD14 (Bit 14)                                      */
21152  #define R_PSCU_PSARD_PSARD14_Msk    (0x4000UL)     /*!< PSARD14 (Bitfield-Mask: 0x01)                         */
21153  #define R_PSCU_PSARD_PSARD15_Pos    (15UL)         /*!< PSARD15 (Bit 15)                                      */
21154  #define R_PSCU_PSARD_PSARD15_Msk    (0x8000UL)     /*!< PSARD15 (Bitfield-Mask: 0x01)                         */
21155  #define R_PSCU_PSARD_PSARD16_Pos    (16UL)         /*!< PSARD16 (Bit 16)                                      */
21156  #define R_PSCU_PSARD_PSARD16_Msk    (0x10000UL)    /*!< PSARD16 (Bitfield-Mask: 0x01)                         */
21157  #define R_PSCU_PSARD_PSARD19_Pos    (19UL)         /*!< PSARD19 (Bit 19)                                      */
21158  #define R_PSCU_PSARD_PSARD19_Msk    (0x80000UL)    /*!< PSARD19 (Bitfield-Mask: 0x01)                         */
21159  #define R_PSCU_PSARD_PSARD20_Pos    (20UL)         /*!< PSARD20 (Bit 20)                                      */
21160  #define R_PSCU_PSARD_PSARD20_Msk    (0x100000UL)   /*!< PSARD20 (Bitfield-Mask: 0x01)                         */
21161  #define R_PSCU_PSARD_PSARD22_Pos    (22UL)         /*!< PSARD22 (Bit 22)                                      */
21162  #define R_PSCU_PSARD_PSARD22_Msk    (0x400000UL)   /*!< PSARD22 (Bitfield-Mask: 0x01)                         */
21163  #define R_PSCU_PSARD_PSARD25_Pos    (25UL)         /*!< PSARD25 (Bit 25)                                      */
21164  #define R_PSCU_PSARD_PSARD25_Msk    (0x2000000UL)  /*!< PSARD25 (Bitfield-Mask: 0x01)                         */
21165  #define R_PSCU_PSARD_PSARD26_Pos    (26UL)         /*!< PSARD26 (Bit 26)                                      */
21166  #define R_PSCU_PSARD_PSARD26_Msk    (0x4000000UL)  /*!< PSARD26 (Bitfield-Mask: 0x01)                         */
21167  #define R_PSCU_PSARD_PSARD27_Pos    (27UL)         /*!< PSARD27 (Bit 27)                                      */
21168  #define R_PSCU_PSARD_PSARD27_Msk    (0x8000000UL)  /*!< PSARD27 (Bitfield-Mask: 0x01)                         */
21169  #define R_PSCU_PSARD_PSARD28_Pos    (28UL)         /*!< PSARD28 (Bit 28)                                      */
21170  #define R_PSCU_PSARD_PSARD28_Msk    (0x10000000UL) /*!< PSARD28 (Bitfield-Mask: 0x01)                         */
21171 /* =========================================================  PSARE  ========================================================= */
21172  #define R_PSCU_PSARE_PSARE0_Pos     (0UL)          /*!< PSARE0 (Bit 0)                                        */
21173  #define R_PSCU_PSARE_PSARE0_Msk     (0x1UL)        /*!< PSARE0 (Bitfield-Mask: 0x01)                          */
21174  #define R_PSCU_PSARE_PSARE1_Pos     (1UL)          /*!< PSARE1 (Bit 1)                                        */
21175  #define R_PSCU_PSARE_PSARE1_Msk     (0x2UL)        /*!< PSARE1 (Bitfield-Mask: 0x01)                          */
21176  #define R_PSCU_PSARE_PSARE2_Pos     (2UL)          /*!< PSARE2 (Bit 2)                                        */
21177  #define R_PSCU_PSARE_PSARE2_Msk     (0x4UL)        /*!< PSARE2 (Bitfield-Mask: 0x01)                          */
21178  #define R_PSCU_PSARE_PSARE14_Pos    (14UL)         /*!< PSARE14 (Bit 14)                                      */
21179  #define R_PSCU_PSARE_PSARE14_Msk    (0x4000UL)     /*!< PSARE14 (Bitfield-Mask: 0x01)                         */
21180  #define R_PSCU_PSARE_PSARE15_Pos    (15UL)         /*!< PSARE15 (Bit 15)                                      */
21181  #define R_PSCU_PSARE_PSARE15_Msk    (0x8000UL)     /*!< PSARE15 (Bitfield-Mask: 0x01)                         */
21182  #define R_PSCU_PSARE_PSARE22_Pos    (22UL)         /*!< PSARE22 (Bit 22)                                      */
21183  #define R_PSCU_PSARE_PSARE22_Msk    (0x400000UL)   /*!< PSARE22 (Bitfield-Mask: 0x01)                         */
21184  #define R_PSCU_PSARE_PSARE23_Pos    (23UL)         /*!< PSARE23 (Bit 23)                                      */
21185  #define R_PSCU_PSARE_PSARE23_Msk    (0x800000UL)   /*!< PSARE23 (Bitfield-Mask: 0x01)                         */
21186  #define R_PSCU_PSARE_PSARE24_Pos    (24UL)         /*!< PSARE24 (Bit 24)                                      */
21187  #define R_PSCU_PSARE_PSARE24_Msk    (0x1000000UL)  /*!< PSARE24 (Bitfield-Mask: 0x01)                         */
21188  #define R_PSCU_PSARE_PSARE25_Pos    (25UL)         /*!< PSARE25 (Bit 25)                                      */
21189  #define R_PSCU_PSARE_PSARE25_Msk    (0x2000000UL)  /*!< PSARE25 (Bitfield-Mask: 0x01)                         */
21190  #define R_PSCU_PSARE_PSARE26_Pos    (26UL)         /*!< PSARE26 (Bit 26)                                      */
21191  #define R_PSCU_PSARE_PSARE26_Msk    (0x4000000UL)  /*!< PSARE26 (Bitfield-Mask: 0x01)                         */
21192  #define R_PSCU_PSARE_PSARE27_Pos    (27UL)         /*!< PSARE27 (Bit 27)                                      */
21193  #define R_PSCU_PSARE_PSARE27_Msk    (0x8000000UL)  /*!< PSARE27 (Bitfield-Mask: 0x01)                         */
21194  #define R_PSCU_PSARE_PSARE28_Pos    (28UL)         /*!< PSARE28 (Bit 28)                                      */
21195  #define R_PSCU_PSARE_PSARE28_Msk    (0x10000000UL) /*!< PSARE28 (Bitfield-Mask: 0x01)                         */
21196  #define R_PSCU_PSARE_PSARE29_Pos    (29UL)         /*!< PSARE29 (Bit 29)                                      */
21197  #define R_PSCU_PSARE_PSARE29_Msk    (0x20000000UL) /*!< PSARE29 (Bitfield-Mask: 0x01)                         */
21198  #define R_PSCU_PSARE_PSARE30_Pos    (30UL)         /*!< PSARE30 (Bit 30)                                      */
21199  #define R_PSCU_PSARE_PSARE30_Msk    (0x40000000UL) /*!< PSARE30 (Bitfield-Mask: 0x01)                         */
21200  #define R_PSCU_PSARE_PSARE31_Pos    (31UL)         /*!< PSARE31 (Bit 31)                                      */
21201  #define R_PSCU_PSARE_PSARE31_Msk    (0x80000000UL) /*!< PSARE31 (Bitfield-Mask: 0x01)                         */
21202 /* =========================================================  MSSAR  ========================================================= */
21203  #define R_PSCU_MSSAR_MSSAR0_Pos     (0UL)          /*!< MSSAR0 (Bit 0)                                        */
21204  #define R_PSCU_MSSAR_MSSAR0_Msk     (0x1UL)        /*!< MSSAR0 (Bitfield-Mask: 0x01)                          */
21205  #define R_PSCU_MSSAR_MSSAR1_Pos     (1UL)          /*!< MSSAR1 (Bit 1)                                        */
21206  #define R_PSCU_MSSAR_MSSAR1_Msk     (0x2UL)        /*!< MSSAR1 (Bitfield-Mask: 0x01)                          */
21207  #define R_PSCU_MSSAR_MSSAR2_Pos     (2UL)          /*!< MSSAR2 (Bit 2)                                        */
21208  #define R_PSCU_MSSAR_MSSAR2_Msk     (0x4UL)        /*!< MSSAR2 (Bitfield-Mask: 0x01)                          */
21209  #define R_PSCU_MSSAR_MSSAR3_Pos     (3UL)          /*!< MSSAR3 (Bit 3)                                        */
21210  #define R_PSCU_MSSAR_MSSAR3_Msk     (0x8UL)        /*!< MSSAR3 (Bitfield-Mask: 0x01)                          */
21211 /* =======================================================  CFSAMONA  ======================================================== */
21212  #define R_PSCU_CFSAMONA_CFS2_Pos    (15UL)         /*!< CFS2 (Bit 15)                                         */
21213  #define R_PSCU_CFSAMONA_CFS2_Msk    (0xff8000UL)   /*!< CFS2 (Bitfield-Mask: 0x1ff)                           */
21214 /* =======================================================  CFSAMONB  ======================================================== */
21215  #define R_PSCU_CFSAMONB_CFS1_Pos    (10UL)         /*!< CFS1 (Bit 10)                                         */
21216  #define R_PSCU_CFSAMONB_CFS1_Msk    (0xfffc00UL)   /*!< CFS1 (Bitfield-Mask: 0x3fff)                          */
21217 /* ========================================================  DFSAMON  ======================================================== */
21218  #define R_PSCU_DFSAMON_DFS_Pos      (10UL)         /*!< DFS (Bit 10)                                          */
21219  #define R_PSCU_DFSAMON_DFS_Msk      (0xfc00UL)     /*!< DFS (Bitfield-Mask: 0x3f)                             */
21220 /* ========================================================  SSAMONA  ======================================================== */
21221  #define R_PSCU_SSAMONA_SS2_Pos      (13UL)         /*!< SS2 (Bit 13)                                          */
21222  #define R_PSCU_SSAMONA_SS2_Msk      (0x1fe000UL)   /*!< SS2 (Bitfield-Mask: 0xff)                             */
21223 /* ========================================================  SSAMONB  ======================================================== */
21224  #define R_PSCU_SSAMONB_SS1_Pos      (10UL)         /*!< SS1 (Bit 10)                                          */
21225  #define R_PSCU_SSAMONB_SS1_Msk      (0x1ffc00UL)   /*!< SS1 (Bitfield-Mask: 0x7ff)                            */
21226 /* ========================================================  DLMMON  ========================================================= */
21227  #define R_PSCU_DLMMON_DLMMON_Pos    (0UL)          /*!< DLMMON (Bit 0)                                        */
21228  #define R_PSCU_DLMMON_DLMMON_Msk    (0xfUL)        /*!< DLMMON (Bitfield-Mask: 0x0f)                          */
21229 
21230 /* =========================================================================================================================== */
21231 /* ================                                           R_BUS                                           ================ */
21232 /* =========================================================================================================================== */
21233 
21234 /* ========================================================  CSRECEN  ======================================================== */
21235  #define R_BUS_CSRECEN_RCVENM_Pos        (8UL)       /*!< RCVENM (Bit 8)                                        */
21236  #define R_BUS_CSRECEN_RCVENM_Msk        (0x100UL)   /*!< RCVENM (Bitfield-Mask: 0x01)                          */
21237  #define R_BUS_CSRECEN_RCVEN_Pos         (0UL)       /*!< RCVEN (Bit 0)                                         */
21238  #define R_BUS_CSRECEN_RCVEN_Msk         (0x1UL)     /*!< RCVEN (Bitfield-Mask: 0x01)                           */
21239 /* ========================================================  BUSMABT  ======================================================== */
21240  #define R_BUS_BUSMABT_ARBS_Pos          (0UL)       /*!< ARBS (Bit 0)                                          */
21241  #define R_BUS_BUSMABT_ARBS_Msk          (0x1UL)     /*!< ARBS (Bitfield-Mask: 0x01)                            */
21242 /* =======================================================  BUSDIVBYP  ======================================================= */
21243  #define R_BUS_BUSDIVBYP_CPU0SBPE_Pos    (16UL)      /*!< CPU0SBPE (Bit 16)                                     */
21244  #define R_BUS_BUSDIVBYP_CPU0SBPE_Msk    (0x10000UL) /*!< CPU0SBPE (Bitfield-Mask: 0x01)                        */
21245  #define R_BUS_BUSDIVBYP_GDSSBPE_Pos     (3UL)       /*!< GDSSBPE (Bit 3)                                       */
21246  #define R_BUS_BUSDIVBYP_GDSSBPE_Msk     (0x8UL)     /*!< GDSSBPE (Bitfield-Mask: 0x01)                         */
21247  #define R_BUS_BUSDIVBYP_EDMABPE_Pos     (0UL)       /*!< EDMABPE (Bit 0)                                       */
21248  #define R_BUS_BUSDIVBYP_EDMABPE_Msk     (0x1UL)     /*!< EDMABPE (Bitfield-Mask: 0x01)                         */
21249 
21250 /* =========================================================================================================================== */
21251 /* ================                                           R_CAC                                           ================ */
21252 /* =========================================================================================================================== */
21253 
21254 /* =========================================================  CACR0  ========================================================= */
21255  #define R_CAC_CACR0_CFME_Pos         (0UL)      /*!< CFME (Bit 0)                                          */
21256  #define R_CAC_CACR0_CFME_Msk         (0x1UL)    /*!< CFME (Bitfield-Mask: 0x01)                            */
21257 /* =========================================================  CACR1  ========================================================= */
21258  #define R_CAC_CACR1_EDGES_Pos        (6UL)      /*!< EDGES (Bit 6)                                         */
21259  #define R_CAC_CACR1_EDGES_Msk        (0xc0UL)   /*!< EDGES (Bitfield-Mask: 0x03)                           */
21260  #define R_CAC_CACR1_TCSS_Pos         (4UL)      /*!< TCSS (Bit 4)                                          */
21261  #define R_CAC_CACR1_TCSS_Msk         (0x30UL)   /*!< TCSS (Bitfield-Mask: 0x03)                            */
21262  #define R_CAC_CACR1_FMCS_Pos         (1UL)      /*!< FMCS (Bit 1)                                          */
21263  #define R_CAC_CACR1_FMCS_Msk         (0xeUL)    /*!< FMCS (Bitfield-Mask: 0x07)                            */
21264  #define R_CAC_CACR1_CACREFE_Pos      (0UL)      /*!< CACREFE (Bit 0)                                       */
21265  #define R_CAC_CACR1_CACREFE_Msk      (0x1UL)    /*!< CACREFE (Bitfield-Mask: 0x01)                         */
21266 /* =========================================================  CACR2  ========================================================= */
21267  #define R_CAC_CACR2_DFS_Pos          (6UL)      /*!< DFS (Bit 6)                                           */
21268  #define R_CAC_CACR2_DFS_Msk          (0xc0UL)   /*!< DFS (Bitfield-Mask: 0x03)                             */
21269  #define R_CAC_CACR2_RCDS_Pos         (4UL)      /*!< RCDS (Bit 4)                                          */
21270  #define R_CAC_CACR2_RCDS_Msk         (0x30UL)   /*!< RCDS (Bitfield-Mask: 0x03)                            */
21271  #define R_CAC_CACR2_RSCS_Pos         (1UL)      /*!< RSCS (Bit 1)                                          */
21272  #define R_CAC_CACR2_RSCS_Msk         (0xeUL)    /*!< RSCS (Bitfield-Mask: 0x07)                            */
21273  #define R_CAC_CACR2_RPS_Pos          (0UL)      /*!< RPS (Bit 0)                                           */
21274  #define R_CAC_CACR2_RPS_Msk          (0x1UL)    /*!< RPS (Bitfield-Mask: 0x01)                             */
21275 /* =========================================================  CAICR  ========================================================= */
21276  #define R_CAC_CAICR_OVFFCL_Pos       (6UL)      /*!< OVFFCL (Bit 6)                                        */
21277  #define R_CAC_CAICR_OVFFCL_Msk       (0x40UL)   /*!< OVFFCL (Bitfield-Mask: 0x01)                          */
21278  #define R_CAC_CAICR_MENDFCL_Pos      (5UL)      /*!< MENDFCL (Bit 5)                                       */
21279  #define R_CAC_CAICR_MENDFCL_Msk      (0x20UL)   /*!< MENDFCL (Bitfield-Mask: 0x01)                         */
21280  #define R_CAC_CAICR_FERRFCL_Pos      (4UL)      /*!< FERRFCL (Bit 4)                                       */
21281  #define R_CAC_CAICR_FERRFCL_Msk      (0x10UL)   /*!< FERRFCL (Bitfield-Mask: 0x01)                         */
21282  #define R_CAC_CAICR_OVFIE_Pos        (2UL)      /*!< OVFIE (Bit 2)                                         */
21283  #define R_CAC_CAICR_OVFIE_Msk        (0x4UL)    /*!< OVFIE (Bitfield-Mask: 0x01)                           */
21284  #define R_CAC_CAICR_MENDIE_Pos       (1UL)      /*!< MENDIE (Bit 1)                                        */
21285  #define R_CAC_CAICR_MENDIE_Msk       (0x2UL)    /*!< MENDIE (Bitfield-Mask: 0x01)                          */
21286  #define R_CAC_CAICR_FERRIE_Pos       (0UL)      /*!< FERRIE (Bit 0)                                        */
21287  #define R_CAC_CAICR_FERRIE_Msk       (0x1UL)    /*!< FERRIE (Bitfield-Mask: 0x01)                          */
21288 /* =========================================================  CASTR  ========================================================= */
21289  #define R_CAC_CASTR_OVFF_Pos         (2UL)      /*!< OVFF (Bit 2)                                          */
21290  #define R_CAC_CASTR_OVFF_Msk         (0x4UL)    /*!< OVFF (Bitfield-Mask: 0x01)                            */
21291  #define R_CAC_CASTR_MENDF_Pos        (1UL)      /*!< MENDF (Bit 1)                                         */
21292  #define R_CAC_CASTR_MENDF_Msk        (0x2UL)    /*!< MENDF (Bitfield-Mask: 0x01)                           */
21293  #define R_CAC_CASTR_FERRF_Pos        (0UL)      /*!< FERRF (Bit 0)                                         */
21294  #define R_CAC_CASTR_FERRF_Msk        (0x1UL)    /*!< FERRF (Bitfield-Mask: 0x01)                           */
21295 /* ========================================================  CAULVR  ========================================================= */
21296  #define R_CAC_CAULVR_CAULVR_Pos      (0UL)      /*!< CAULVR (Bit 0)                                        */
21297  #define R_CAC_CAULVR_CAULVR_Msk      (0xffffUL) /*!< CAULVR (Bitfield-Mask: 0xffff)                        */
21298 /* ========================================================  CALLVR  ========================================================= */
21299  #define R_CAC_CALLVR_CALLVR_Pos      (0UL)      /*!< CALLVR (Bit 0)                                        */
21300  #define R_CAC_CALLVR_CALLVR_Msk      (0xffffUL) /*!< CALLVR (Bitfield-Mask: 0xffff)                        */
21301 /* ========================================================  CACNTBR  ======================================================== */
21302  #define R_CAC_CACNTBR_CACNTBR_Pos    (0UL)      /*!< CACNTBR (Bit 0)                                       */
21303  #define R_CAC_CACNTBR_CACNTBR_Msk    (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff)                       */
21304 
21305 /* =========================================================================================================================== */
21306 /* ================                                          R_CANFD                                          ================ */
21307 /* =========================================================================================================================== */
21308 
21309 /* ========================================================  CFDGCFG  ======================================================== */
21310  #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
21311  #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
21312  #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
21313  #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
21314  #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
21315  #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
21316  #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
21317  #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
21318  #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
21319  #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
21320  #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
21321  #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
21322  #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
21323  #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
21324  #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
21325  #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
21326  #define R_CANFD_CFDGCFG_TSBTCS_Pos              (13UL)         /*!< TSBTCS (Bit 13)                                       */
21327  #define R_CANFD_CFDGCFG_TSBTCS_Msk              (0xe000UL)     /*!< TSBTCS (Bitfield-Mask: 0x07)                          */
21328  #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
21329  #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
21330 /* ========================================================  CFDGCTR  ======================================================== */
21331  #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
21332  #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
21333  #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
21334  #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
21335  #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
21336  #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
21337  #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
21338  #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
21339  #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
21340  #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
21341  #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
21342  #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
21343  #define R_CANFD_CFDGCTR_QMEIE_Pos               (14UL)         /*!< QMEIE (Bit 14)                                        */
21344  #define R_CANFD_CFDGCTR_QMEIE_Msk               (0x4000UL)     /*!< QMEIE (Bitfield-Mask: 0x01)                           */
21345  #define R_CANFD_CFDGCTR_MOWEIE_Pos              (15UL)         /*!< MOWEIE (Bit 15)                                       */
21346  #define R_CANFD_CFDGCTR_MOWEIE_Msk              (0x8000UL)     /*!< MOWEIE (Bitfield-Mask: 0x01)                          */
21347  #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
21348  #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
21349  #define R_CANFD_CFDGCTR_TSWR_Pos                (17UL)         /*!< TSWR (Bit 17)                                         */
21350  #define R_CANFD_CFDGCTR_TSWR_Msk                (0x20000UL)    /*!< TSWR (Bitfield-Mask: 0x01)                            */
21351 /* ========================================================  CFDGSTS  ======================================================== */
21352  #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
21353  #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
21354  #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
21355  #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
21356  #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
21357  #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
21358  #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
21359  #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
21360 /* =======================================================  CFDGERFL  ======================================================== */
21361  #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
21362  #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
21363  #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
21364  #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
21365  #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
21366  #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
21367  #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
21368  #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
21369  #define R_CANFD_CFDGERFL_QOWES_Pos              (4UL)          /*!< QOWES (Bit 4)                                         */
21370  #define R_CANFD_CFDGERFL_QOWES_Msk              (0x10UL)       /*!< QOWES (Bitfield-Mask: 0x01)                           */
21371  #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos          (5UL)          /*!< OTBMLTSTS (Bit 5)                                     */
21372  #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk          (0x20UL)       /*!< OTBMLTSTS (Bitfield-Mask: 0x01)                       */
21373  #define R_CANFD_CFDGERFL_QMES_Pos               (6UL)          /*!< QMES (Bit 6)                                          */
21374  #define R_CANFD_CFDGERFL_QMES_Msk               (0x40UL)       /*!< QMES (Bitfield-Mask: 0x01)                            */
21375  #define R_CANFD_CFDGERFL_RXSFAIL0_Pos           (8UL)          /*!< RXSFAIL0 (Bit 8)                                      */
21376  #define R_CANFD_CFDGERFL_RXSFAIL0_Msk           (0x100UL)      /*!< RXSFAIL0 (Bitfield-Mask: 0x01)                        */
21377  #define R_CANFD_CFDGERFL_RXSFAIL1_Pos           (9UL)          /*!< RXSFAIL1 (Bit 9)                                      */
21378  #define R_CANFD_CFDGERFL_RXSFAIL1_Msk           (0x200UL)      /*!< RXSFAIL1 (Bitfield-Mask: 0x01)                        */
21379  #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
21380  #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
21381  #define R_CANFD_CFDGERFL_EEF1_Pos               (17UL)         /*!< EEF1 (Bit 17)                                         */
21382  #define R_CANFD_CFDGERFL_EEF1_Msk               (0x20000UL)    /*!< EEF1 (Bitfield-Mask: 0x01)                            */
21383 /* ========================================================  CFDGTSC  ======================================================== */
21384  #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
21385  #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
21386 /* ======================================================  CFDGAFLECTR  ====================================================== */
21387  #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
21388  #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
21389  #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
21390  #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
21391 /* ======================================================  CFDGAFLCFG0  ====================================================== */
21392  #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
21393  #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
21394  #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
21395  #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
21396 /* ========================================================  CFDRMNB  ======================================================== */
21397  #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
21398  #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
21399  #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
21400  #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
21401 /* =======================================================  CFDRMND0  ======================================================== */
21402  #define R_CANFD_CFDRMND0_RMNSu_Pos              (0UL)          /*!< RMNSu (Bit 0)                                         */
21403  #define R_CANFD_CFDRMND0_RMNSu_Msk              (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff)                     */
21404 /* ========================================================  CFDRFCC  ======================================================== */
21405  #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
21406  #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
21407  #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
21408  #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
21409  #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
21410  #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
21411  #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
21412  #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
21413  #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
21414  #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
21415  #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
21416  #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
21417  #define R_CANFD_CFDRFCC_RFFIE_Pos               (16UL)         /*!< RFFIE (Bit 16)                                        */
21418  #define R_CANFD_CFDRFCC_RFFIE_Msk               (0x10000UL)    /*!< RFFIE (Bitfield-Mask: 0x01)                           */
21419 /* =======================================================  CFDRFSTS  ======================================================== */
21420  #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
21421  #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
21422  #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
21423  #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
21424  #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
21425  #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
21426  #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
21427  #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
21428  #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
21429  #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
21430  #define R_CANFD_CFDRFSTS_RFFIF_Pos              (16UL)         /*!< RFFIF (Bit 16)                                        */
21431  #define R_CANFD_CFDRFSTS_RFFIF_Msk              (0x10000UL)    /*!< RFFIF (Bitfield-Mask: 0x01)                           */
21432 /* =======================================================  CFDRFPCTR  ======================================================= */
21433  #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
21434  #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
21435 /* ========================================================  CFDCFCC  ======================================================== */
21436  #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
21437  #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
21438  #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
21439  #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
21440  #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
21441  #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
21442  #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
21443  #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
21444  #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
21445  #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
21446  #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
21447  #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
21448  #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
21449  #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
21450  #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
21451  #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
21452  #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
21453  #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
21454  #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
21455  #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
21456  #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
21457  #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
21458  #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
21459  #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
21460 /* =======================================================  CFDCFCCE  ======================================================== */
21461  #define R_CANFD_CFDCFCCE_CFFIE_Pos              (0UL)          /*!< CFFIE (Bit 0)                                         */
21462  #define R_CANFD_CFDCFCCE_CFFIE_Msk              (0x1UL)        /*!< CFFIE (Bitfield-Mask: 0x01)                           */
21463  #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos           (1UL)          /*!< CFOFRXIE (Bit 1)                                      */
21464  #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk           (0x2UL)        /*!< CFOFRXIE (Bitfield-Mask: 0x01)                        */
21465  #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos           (2UL)          /*!< CFOFTXIE (Bit 2)                                      */
21466  #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk           (0x4UL)        /*!< CFOFTXIE (Bitfield-Mask: 0x01)                        */
21467  #define R_CANFD_CFDCFCCE_CFMOWM_Pos             (8UL)          /*!< CFMOWM (Bit 8)                                        */
21468  #define R_CANFD_CFDCFCCE_CFMOWM_Msk             (0x100UL)      /*!< CFMOWM (Bitfield-Mask: 0x01)                          */
21469  #define R_CANFD_CFDCFCCE_CFBME_Pos              (16UL)         /*!< CFBME (Bit 16)                                        */
21470  #define R_CANFD_CFDCFCCE_CFBME_Msk              (0x10000UL)    /*!< CFBME (Bitfield-Mask: 0x01)                           */
21471 /* =======================================================  CFDCFSTS  ======================================================== */
21472  #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
21473  #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
21474  #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
21475  #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
21476  #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
21477  #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
21478  #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
21479  #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
21480  #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
21481  #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
21482  #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
21483  #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
21484  #define R_CANFD_CFDCFSTS_CFFIF_Pos              (16UL)         /*!< CFFIF (Bit 16)                                        */
21485  #define R_CANFD_CFDCFSTS_CFFIF_Msk              (0x10000UL)    /*!< CFFIF (Bitfield-Mask: 0x01)                           */
21486  #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos           (17UL)         /*!< CFOFRXIF (Bit 17)                                     */
21487  #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk           (0x20000UL)    /*!< CFOFRXIF (Bitfield-Mask: 0x01)                        */
21488  #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos           (18UL)         /*!< CFOFTXIF (Bit 18)                                     */
21489  #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk           (0x40000UL)    /*!< CFOFTXIF (Bitfield-Mask: 0x01)                        */
21490  #define R_CANFD_CFDCFSTS_CFMOW_Pos              (24UL)         /*!< CFMOW (Bit 24)                                        */
21491  #define R_CANFD_CFDCFSTS_CFMOW_Msk              (0x1000000UL)  /*!< CFMOW (Bitfield-Mask: 0x01)                           */
21492 /* =======================================================  CFDCFPCTR  ======================================================= */
21493  #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
21494  #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
21495 /* =======================================================  CFDFESTS  ======================================================== */
21496  #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
21497  #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0xffUL)       /*!< RFXEMP (Bitfield-Mask: 0xff)                          */
21498  #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
21499  #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x3f00UL)     /*!< CFXEMP (Bitfield-Mask: 0x3f)                          */
21500 /* =======================================================  CFDFFSTS  ======================================================== */
21501  #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
21502  #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0xffUL)       /*!< RFXFLL (Bitfield-Mask: 0xff)                          */
21503  #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
21504  #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x3f00UL)     /*!< CFXFLL (Bitfield-Mask: 0x3f)                          */
21505 /* =======================================================  CFDFMSTS  ======================================================== */
21506  #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
21507  #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0xffUL)       /*!< RFXMLT (Bitfield-Mask: 0xff)                          */
21508  #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
21509  #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x3f00UL)     /*!< CFXMLT (Bitfield-Mask: 0x3f)                          */
21510 /* =======================================================  CFDRFISTS  ======================================================= */
21511  #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
21512  #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0xffUL)       /*!< RFXIF (Bitfield-Mask: 0xff)                           */
21513  #define R_CANFD_CFDRFISTS_RFXFFLL_Pos           (16UL)         /*!< RFXFFLL (Bit 16)                                      */
21514  #define R_CANFD_CFDRFISTS_RFXFFLL_Msk           (0xff0000UL)   /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
21515 /* ======================================================  CFDCFRISTS  ======================================================= */
21516  #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos          (0UL)          /*!< CFXRXIF (Bit 0)                                       */
21517  #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk          (0x3fUL)       /*!< CFXRXIF (Bitfield-Mask: 0x3f)                         */
21518 /* ======================================================  CFDCFTISTS  ======================================================= */
21519  #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos          (0UL)          /*!< CFXTXIF (Bit 0)                                       */
21520  #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk          (0x3fUL)       /*!< CFXTXIF (Bitfield-Mask: 0x3f)                         */
21521 /* =====================================================  CFDCFOFRISTS  ====================================================== */
21522  #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos      (0UL)          /*!< CFXOFRXIF (Bit 0)                                     */
21523  #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk      (0x3fUL)       /*!< CFXOFRXIF (Bitfield-Mask: 0x3f)                       */
21524 /* =====================================================  CFDCFOFTISTS  ====================================================== */
21525  #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos      (0UL)          /*!< CFXOFTXIF (Bit 0)                                     */
21526  #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk      (0x3fUL)       /*!< CFXOFTXIF (Bitfield-Mask: 0x3f)                       */
21527 /* ======================================================  CFDCFMOWSTS  ====================================================== */
21528  #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos          (0UL)          /*!< CFXMOW (Bit 0)                                        */
21529  #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk          (0x3fUL)       /*!< CFXMOW (Bitfield-Mask: 0x3f)                          */
21530 /* =======================================================  CFDFFFSTS  ======================================================= */
21531  #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos           (0UL)          /*!< RFXFFLL (Bit 0)                                       */
21532  #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk           (0xffUL)       /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
21533  #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos           (8UL)          /*!< CFXFFLL (Bit 8)                                       */
21534  #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk           (0x3f00UL)     /*!< CFXFFLL (Bitfield-Mask: 0x3f)                         */
21535 /* ========================================================  CFDTMC  ========================================================= */
21536  #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
21537  #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
21538  #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
21539  #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
21540  #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
21541  #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
21542 /* =======================================================  CFDTMSTS  ======================================================== */
21543  #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
21544  #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
21545  #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
21546  #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
21547  #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
21548  #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
21549  #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
21550  #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
21551 /* ======================================================  CFDTMTRSTS  ======================================================= */
21552  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos      (0UL)          /*!< CFDTMTRSTSg (Bit 0)                                   */
21553  #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk      (0xffUL)       /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff)                     */
21554 /* ======================================================  CFDTMTARSTS  ====================================================== */
21555  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos    (0UL)          /*!< CFDTMTARSTSg (Bit 0)                                  */
21556  #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk    (0xffUL)       /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff)                    */
21557 /* ======================================================  CFDTMTCSTS  ======================================================= */
21558  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos      (0UL)          /*!< CFDTMTCSTSg (Bit 0)                                   */
21559  #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk      (0xffUL)       /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff)                     */
21560 /* ======================================================  CFDTMTASTS  ======================================================= */
21561  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos      (0UL)          /*!< CFDTMTASTSg (Bit 0)                                   */
21562  #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk      (0xffUL)       /*!< CFDTMTASTSg (Bitfield-Mask: 0xff)                     */
21563 /* =======================================================  CFDTMIEC  ======================================================== */
21564  #define R_CANFD_CFDTMIEC_TMIEg_Pos              (0UL)          /*!< TMIEg (Bit 0)                                         */
21565  #define R_CANFD_CFDTMIEC_TMIEg_Msk              (0xffUL)       /*!< TMIEg (Bitfield-Mask: 0xff)                           */
21566 /* =======================================================  CFDTXQCC0  ======================================================= */
21567  #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
21568  #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
21569  #define R_CANFD_CFDTXQCC0_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
21570  #define R_CANFD_CFDTXQCC0_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
21571  #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
21572  #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
21573  #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
21574  #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
21575  #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
21576  #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
21577  #define R_CANFD_CFDTXQCC0_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
21578  #define R_CANFD_CFDTXQCC0_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
21579  #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
21580  #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
21581  #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
21582  #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
21583 /* ======================================================  CFDTXQSTS0  ======================================================= */
21584  #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
21585  #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
21586  #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
21587  #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
21588  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
21589  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
21590  #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
21591  #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
21592  #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
21593  #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
21594  #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
21595  #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
21596  #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
21597  #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
21598  #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
21599  #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
21600 /* ======================================================  CFDTXQPCTR0  ====================================================== */
21601  #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
21602  #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
21603 /* =======================================================  CFDTXQCC1  ======================================================= */
21604  #define R_CANFD_CFDTXQCC1_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
21605  #define R_CANFD_CFDTXQCC1_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
21606  #define R_CANFD_CFDTXQCC1_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
21607  #define R_CANFD_CFDTXQCC1_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
21608  #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
21609  #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
21610  #define R_CANFD_CFDTXQCC1_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
21611  #define R_CANFD_CFDTXQCC1_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
21612  #define R_CANFD_CFDTXQCC1_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
21613  #define R_CANFD_CFDTXQCC1_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
21614  #define R_CANFD_CFDTXQCC1_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
21615  #define R_CANFD_CFDTXQCC1_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
21616  #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
21617  #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
21618  #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
21619  #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
21620 /* ======================================================  CFDTXQSTS1  ======================================================= */
21621  #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
21622  #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
21623  #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
21624  #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
21625  #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
21626  #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
21627  #define R_CANFD_CFDTXQSTS1_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
21628  #define R_CANFD_CFDTXQSTS1_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
21629  #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
21630  #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
21631  #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
21632  #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
21633  #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
21634  #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
21635  #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
21636  #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
21637 /* ======================================================  CFDTXQPCTR1  ====================================================== */
21638  #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
21639  #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
21640 /* =======================================================  CFDTXQCC2  ======================================================= */
21641  #define R_CANFD_CFDTXQCC2_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
21642  #define R_CANFD_CFDTXQCC2_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
21643  #define R_CANFD_CFDTXQCC2_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
21644  #define R_CANFD_CFDTXQCC2_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
21645  #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
21646  #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
21647  #define R_CANFD_CFDTXQCC2_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
21648  #define R_CANFD_CFDTXQCC2_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
21649  #define R_CANFD_CFDTXQCC2_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
21650  #define R_CANFD_CFDTXQCC2_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
21651  #define R_CANFD_CFDTXQCC2_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
21652  #define R_CANFD_CFDTXQCC2_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
21653  #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
21654  #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
21655  #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
21656  #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
21657 /* ======================================================  CFDTXQSTS2  ======================================================= */
21658  #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
21659  #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
21660  #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
21661  #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
21662  #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
21663  #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
21664  #define R_CANFD_CFDTXQSTS2_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
21665  #define R_CANFD_CFDTXQSTS2_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
21666  #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
21667  #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
21668  #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
21669  #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
21670  #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
21671  #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
21672  #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
21673  #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
21674 /* ======================================================  CFDTXQPCTR2  ====================================================== */
21675  #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
21676  #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
21677 /* =======================================================  CFDTXQCC3  ======================================================= */
21678  #define R_CANFD_CFDTXQCC3_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
21679  #define R_CANFD_CFDTXQCC3_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
21680  #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
21681  #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
21682  #define R_CANFD_CFDTXQCC3_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
21683  #define R_CANFD_CFDTXQCC3_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
21684  #define R_CANFD_CFDTXQCC3_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
21685  #define R_CANFD_CFDTXQCC3_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
21686  #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
21687  #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
21688 /* ======================================================  CFDTXQSTS3  ======================================================= */
21689  #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
21690  #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
21691  #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
21692  #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
21693  #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
21694  #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
21695  #define R_CANFD_CFDTXQSTS3_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
21696  #define R_CANFD_CFDTXQSTS3_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
21697  #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
21698  #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
21699 /* ======================================================  CFDTXQPCTR3  ====================================================== */
21700  #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
21701  #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
21702 /* ======================================================  CFDTXQESTS  ======================================================= */
21703  #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos          (0UL)          /*!< TXQxEMP (Bit 0)                                       */
21704  #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk          (0xffUL)       /*!< TXQxEMP (Bitfield-Mask: 0xff)                         */
21705 /* ======================================================  CFDTXQFISTS  ====================================================== */
21706  #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos        (0UL)          /*!< TXQ0FULL (Bit 0)                                      */
21707  #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk        (0x7UL)        /*!< TXQ0FULL (Bitfield-Mask: 0x07)                        */
21708  #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos        (4UL)          /*!< TXQ1FULL (Bit 4)                                      */
21709  #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk        (0x70UL)       /*!< TXQ1FULL (Bitfield-Mask: 0x07)                        */
21710 /* ======================================================  CFDTXQMSTS  ======================================================= */
21711  #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos           (0UL)          /*!< TXQ0ML (Bit 0)                                        */
21712  #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk           (0x7UL)        /*!< TXQ0ML (Bitfield-Mask: 0x07)                          */
21713  #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos           (4UL)          /*!< TXQ1ML (Bit 4)                                        */
21714  #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk           (0x70UL)       /*!< TXQ1ML (Bitfield-Mask: 0x07)                          */
21715 /* ======================================================  CFDTXQISTS  ======================================================= */
21716  #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos          (0UL)          /*!< TXQ0ISF (Bit 0)                                       */
21717  #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk          (0xfUL)        /*!< TXQ0ISF (Bitfield-Mask: 0x0f)                         */
21718  #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos          (4UL)          /*!< TXQ1ISF (Bit 4)                                       */
21719  #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk          (0xf0UL)       /*!< TXQ1ISF (Bitfield-Mask: 0x0f)                         */
21720 /* =====================================================  CFDTXQOFTISTS  ===================================================== */
21721  #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos    (0UL)          /*!< TXQ0OFTISF (Bit 0)                                    */
21722  #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk    (0xfUL)        /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f)                      */
21723  #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos    (4UL)          /*!< TXQ1OFTISF (Bit 4)                                    */
21724  #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk    (0xf0UL)       /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f)                      */
21725 /* =====================================================  CFDTXQOFRISTS  ===================================================== */
21726  #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos    (0UL)          /*!< TXQ0OFRISF (Bit 0)                                    */
21727  #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk    (0x7UL)        /*!< TXQ0OFRISF (Bitfield-Mask: 0x07)                      */
21728  #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos    (4UL)          /*!< TXQ1OFRISF (Bit 4)                                    */
21729  #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk    (0x70UL)       /*!< TXQ1OFRISF (Bitfield-Mask: 0x07)                      */
21730 /* ======================================================  CFDTXQFSTS  ======================================================= */
21731  #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos          (0UL)          /*!< TXQ0FSF (Bit 0)                                       */
21732  #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk          (0xfUL)        /*!< TXQ0FSF (Bitfield-Mask: 0x0f)                         */
21733  #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos          (4UL)          /*!< TXQ1FSF (Bit 4)                                       */
21734  #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk          (0xf0UL)       /*!< TXQ1FSF (Bitfield-Mask: 0x0f)                         */
21735 /* =======================================================  CFDTHLCC  ======================================================== */
21736  #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
21737  #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
21738  #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
21739  #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
21740  #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
21741  #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
21742  #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
21743  #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
21744  #define R_CANFD_CFDTHLCC_THLDGE_Pos             (11UL)         /*!< THLDGE (Bit 11)                                       */
21745  #define R_CANFD_CFDTHLCC_THLDGE_Msk             (0x800UL)      /*!< THLDGE (Bitfield-Mask: 0x01)                          */
21746 /* =======================================================  CFDTHLSTS  ======================================================= */
21747  #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
21748  #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
21749  #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
21750  #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
21751  #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
21752  #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
21753  #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
21754  #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
21755  #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
21756  #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
21757 /* ======================================================  CFDTHLPCTR  ======================================================= */
21758  #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
21759  #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
21760 /* =====================================================  CFDGTINTSTS0  ====================================================== */
21761  #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
21762  #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
21763  #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
21764  #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
21765  #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
21766  #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
21767  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
21768  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
21769  #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
21770  #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
21771  #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos        (5UL)          /*!< TQOFIF0 (Bit 5)                                       */
21772  #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk        (0x20UL)       /*!< TQOFIF0 (Bitfield-Mask: 0x01)                         */
21773  #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos        (6UL)          /*!< CFOTIF0 (Bit 6)                                       */
21774  #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk        (0x40UL)       /*!< CFOTIF0 (Bitfield-Mask: 0x01)                         */
21775  #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos          (8UL)          /*!< TSIF1 (Bit 8)                                         */
21776  #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk          (0x100UL)      /*!< TSIF1 (Bitfield-Mask: 0x01)                           */
21777  #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos          (9UL)          /*!< TAIF1 (Bit 9)                                         */
21778  #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk          (0x200UL)      /*!< TAIF1 (Bitfield-Mask: 0x01)                           */
21779  #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos          (10UL)         /*!< TQIF1 (Bit 10)                                        */
21780  #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk          (0x400UL)      /*!< TQIF1 (Bitfield-Mask: 0x01)                           */
21781  #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos         (11UL)         /*!< CFTIF1 (Bit 11)                                       */
21782  #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk         (0x800UL)      /*!< CFTIF1 (Bitfield-Mask: 0x01)                          */
21783  #define R_CANFD_CFDGTINTSTS0_THIF1_Pos          (12UL)         /*!< THIF1 (Bit 12)                                        */
21784  #define R_CANFD_CFDGTINTSTS0_THIF1_Msk          (0x1000UL)     /*!< THIF1 (Bitfield-Mask: 0x01)                           */
21785  #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos        (13UL)         /*!< TQOFIF1 (Bit 13)                                      */
21786  #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk        (0x2000UL)     /*!< TQOFIF1 (Bitfield-Mask: 0x01)                         */
21787  #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos        (14UL)         /*!< CFOTIF1 (Bit 14)                                      */
21788  #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk        (0x4000UL)     /*!< CFOTIF1 (Bitfield-Mask: 0x01)                         */
21789 /* ======================================================  CFDGTSTCFG  ======================================================= */
21790  #define R_CANFD_CFDGTSTCFG_ICBCE_Pos            (0UL)          /*!< ICBCE (Bit 0)                                         */
21791  #define R_CANFD_CFDGTSTCFG_ICBCE_Msk            (0x3UL)        /*!< ICBCE (Bitfield-Mask: 0x03)                           */
21792  #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
21793  #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
21794 /* ======================================================  CFDGTSTCTR  ======================================================= */
21795  #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos          (0UL)          /*!< ICBCTME (Bit 0)                                       */
21796  #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk          (0x1UL)        /*!< ICBCTME (Bitfield-Mask: 0x01)                         */
21797  #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
21798  #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
21799 /* =======================================================  CFDGFDCFG  ======================================================= */
21800  #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
21801  #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
21802  #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
21803  #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
21804 /* =======================================================  CFDGLOCKK  ======================================================= */
21805  #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
21806  #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
21807 /* =======================================================  CFDGLOTB  ======================================================== */
21808  #define R_CANFD_CFDGLOTB_OTBFE_Pos              (0UL)          /*!< OTBFE (Bit 0)                                         */
21809  #define R_CANFD_CFDGLOTB_OTBFE_Msk              (0x1UL)        /*!< OTBFE (Bitfield-Mask: 0x01)                           */
21810  #define R_CANFD_CFDGLOTB_OTBEMP_Pos             (8UL)          /*!< OTBEMP (Bit 8)                                        */
21811  #define R_CANFD_CFDGLOTB_OTBEMP_Msk             (0x100UL)      /*!< OTBEMP (Bitfield-Mask: 0x01)                          */
21812  #define R_CANFD_CFDGLOTB_OTBFLL_Pos             (9UL)          /*!< OTBFLL (Bit 9)                                        */
21813  #define R_CANFD_CFDGLOTB_OTBFLL_Msk             (0x200UL)      /*!< OTBFLL (Bitfield-Mask: 0x01)                          */
21814  #define R_CANFD_CFDGLOTB_OTBMLT_Pos             (10UL)         /*!< OTBMLT (Bit 10)                                       */
21815  #define R_CANFD_CFDGLOTB_OTBMLT_Msk             (0x400UL)      /*!< OTBMLT (Bitfield-Mask: 0x01)                          */
21816  #define R_CANFD_CFDGLOTB_OTBMC_Pos              (11UL)         /*!< OTBMC (Bit 11)                                        */
21817  #define R_CANFD_CFDGLOTB_OTBMC_Msk              (0xf800UL)     /*!< OTBMC (Bitfield-Mask: 0x1f)                           */
21818 /* =====================================================  CFDGAFLIGNENT  ===================================================== */
21819  #define R_CANFD_CFDGAFLIGNENT_IRN_Pos           (0UL)          /*!< IRN (Bit 0)                                           */
21820  #define R_CANFD_CFDGAFLIGNENT_IRN_Msk           (0x1ffUL)      /*!< IRN (Bitfield-Mask: 0x1ff)                            */
21821  #define R_CANFD_CFDGAFLIGNENT_ICN_Pos           (16UL)         /*!< ICN (Bit 16)                                          */
21822  #define R_CANFD_CFDGAFLIGNENT_ICN_Msk           (0x70000UL)    /*!< ICN (Bitfield-Mask: 0x07)                             */
21823 /* =====================================================  CFDGAFLIGNCTR  ===================================================== */
21824  #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos          (0UL)          /*!< IREN (Bit 0)                                          */
21825  #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk          (0x1UL)        /*!< IREN (Bitfield-Mask: 0x01)                            */
21826  #define R_CANFD_CFDGAFLIGNCTR_KEY_Pos           (8UL)          /*!< KEY (Bit 8)                                           */
21827  #define R_CANFD_CFDGAFLIGNCTR_KEY_Msk           (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
21828 /* =======================================================  CFDCDTCT  ======================================================== */
21829  #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
21830  #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
21831  #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
21832  #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
21833  #define R_CANFD_CFDCDTCT_RFDMAE2_Pos            (2UL)          /*!< RFDMAE2 (Bit 2)                                       */
21834  #define R_CANFD_CFDCDTCT_RFDMAE2_Msk            (0x4UL)        /*!< RFDMAE2 (Bitfield-Mask: 0x01)                         */
21835  #define R_CANFD_CFDCDTCT_RFDMAE3_Pos            (3UL)          /*!< RFDMAE3 (Bit 3)                                       */
21836  #define R_CANFD_CFDCDTCT_RFDMAE3_Msk            (0x8UL)        /*!< RFDMAE3 (Bitfield-Mask: 0x01)                         */
21837  #define R_CANFD_CFDCDTCT_RFDMAE4_Pos            (4UL)          /*!< RFDMAE4 (Bit 4)                                       */
21838  #define R_CANFD_CFDCDTCT_RFDMAE4_Msk            (0x10UL)       /*!< RFDMAE4 (Bitfield-Mask: 0x01)                         */
21839  #define R_CANFD_CFDCDTCT_RFDMAE5_Pos            (5UL)          /*!< RFDMAE5 (Bit 5)                                       */
21840  #define R_CANFD_CFDCDTCT_RFDMAE5_Msk            (0x20UL)       /*!< RFDMAE5 (Bitfield-Mask: 0x01)                         */
21841  #define R_CANFD_CFDCDTCT_RFDMAE6_Pos            (6UL)          /*!< RFDMAE6 (Bit 6)                                       */
21842  #define R_CANFD_CFDCDTCT_RFDMAE6_Msk            (0x40UL)       /*!< RFDMAE6 (Bitfield-Mask: 0x01)                         */
21843  #define R_CANFD_CFDCDTCT_RFDMAE7_Pos            (7UL)          /*!< RFDMAE7 (Bit 7)                                       */
21844  #define R_CANFD_CFDCDTCT_RFDMAE7_Msk            (0x80UL)       /*!< RFDMAE7 (Bitfield-Mask: 0x01)                         */
21845  #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
21846  #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
21847  #define R_CANFD_CFDCDTCT_CFDMAE1_Pos            (9UL)          /*!< CFDMAE1 (Bit 9)                                       */
21848  #define R_CANFD_CFDCDTCT_CFDMAE1_Msk            (0x200UL)      /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
21849 /* =======================================================  CFDCDTSTS  ======================================================= */
21850  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
21851  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
21852  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
21853  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
21854  #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos         (2UL)          /*!< RFDMASTS2 (Bit 2)                                     */
21855  #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk         (0x4UL)        /*!< RFDMASTS2 (Bitfield-Mask: 0x01)                       */
21856  #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos         (3UL)          /*!< RFDMASTS3 (Bit 3)                                     */
21857  #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk         (0x8UL)        /*!< RFDMASTS3 (Bitfield-Mask: 0x01)                       */
21858  #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos         (4UL)          /*!< RFDMASTS4 (Bit 4)                                     */
21859  #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk         (0x10UL)       /*!< RFDMASTS4 (Bitfield-Mask: 0x01)                       */
21860  #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos         (5UL)          /*!< RFDMASTS5 (Bit 5)                                     */
21861  #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk         (0x20UL)       /*!< RFDMASTS5 (Bitfield-Mask: 0x01)                       */
21862  #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos         (6UL)          /*!< RFDMASTS6 (Bit 6)                                     */
21863  #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk         (0x40UL)       /*!< RFDMASTS6 (Bitfield-Mask: 0x01)                       */
21864  #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos         (7UL)          /*!< RFDMASTS7 (Bit 7)                                     */
21865  #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk         (0x80UL)       /*!< RFDMASTS7 (Bitfield-Mask: 0x01)                       */
21866  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
21867  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
21868  #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos         (9UL)          /*!< CFDMASTS1 (Bit 9)                                     */
21869  #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk         (0x200UL)      /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
21870 /* =======================================================  CFDCDTTCT  ======================================================= */
21871  #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos          (0UL)          /*!< TQ0DMAE0 (Bit 0)                                      */
21872  #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk          (0x1UL)        /*!< TQ0DMAE0 (Bitfield-Mask: 0x01)                        */
21873  #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos          (1UL)          /*!< TQ0DMAE1 (Bit 1)                                      */
21874  #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk          (0x2UL)        /*!< TQ0DMAE1 (Bitfield-Mask: 0x01)                        */
21875  #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos          (8UL)          /*!< TQ3DMAE0 (Bit 8)                                      */
21876  #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk          (0x100UL)      /*!< TQ3DMAE0 (Bitfield-Mask: 0x01)                        */
21877  #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos          (9UL)          /*!< TQ3DMAE1 (Bit 9)                                      */
21878  #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk          (0x200UL)      /*!< TQ3DMAE1 (Bitfield-Mask: 0x01)                        */
21879  #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos           (16UL)         /*!< CFDMAE0 (Bit 16)                                      */
21880  #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk           (0x10000UL)    /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
21881  #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos           (17UL)         /*!< CFDMAE1 (Bit 17)                                      */
21882  #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk           (0x20000UL)    /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
21883 /* ======================================================  CFDCDTTSTS  ======================================================= */
21884  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos       (0UL)          /*!< TQ0DMASTS0 (Bit 0)                                    */
21885  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk       (0x1UL)        /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01)                      */
21886  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos       (1UL)          /*!< TQ0DMASTS1 (Bit 1)                                    */
21887  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk       (0x2UL)        /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01)                      */
21888  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos       (8UL)          /*!< TQ3DMASTS0 (Bit 8)                                    */
21889  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk       (0x100UL)      /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01)                      */
21890  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos       (9UL)          /*!< TQ3DMASTS1 (Bit 9)                                    */
21891  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk       (0x200UL)      /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01)                      */
21892  #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos        (16UL)         /*!< CFDMASTS0 (Bit 16)                                    */
21893  #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk        (0x10000UL)    /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
21894  #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos        (17UL)         /*!< CFDMASTS1 (Bit 17)                                    */
21895  #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk        (0x20000UL)    /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
21896 /* ======================================================  CFDGRINTSTS  ====================================================== */
21897  #define R_CANFD_CFDGRINTSTS_QFIF_Pos            (0UL)          /*!< QFIF (Bit 0)                                          */
21898  #define R_CANFD_CFDGRINTSTS_QFIF_Msk            (0x7UL)        /*!< QFIF (Bitfield-Mask: 0x07)                            */
21899  #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos          (8UL)          /*!< QOFRIF (Bit 8)                                        */
21900  #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk          (0x700UL)      /*!< QOFRIF (Bitfield-Mask: 0x07)                          */
21901  #define R_CANFD_CFDGRINTSTS_CFRIF_Pos           (16UL)         /*!< CFRIF (Bit 16)                                        */
21902  #define R_CANFD_CFDGRINTSTS_CFRIF_Msk           (0x70000UL)    /*!< CFRIF (Bitfield-Mask: 0x07)                           */
21903  #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos          (24UL)         /*!< CFRFIF (Bit 24)                                       */
21904  #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk          (0x7000000UL)  /*!< CFRFIF (Bitfield-Mask: 0x07)                          */
21905  #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos         (28UL)         /*!< CFOFRIF (Bit 28)                                      */
21906  #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk         (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07)                         */
21907 /* =======================================================  CFDGRSTC  ======================================================== */
21908  #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
21909  #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
21910  #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
21911  #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
21912 /* =======================================================  CFDRPGACC  ======================================================= */
21913  #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
21914  #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
21915 
21916 /* =========================================================================================================================== */
21917 /* ================                                           R_CRC                                           ================ */
21918 /* =========================================================================================================================== */
21919 
21920 /* ========================================================  CRCCR0  ========================================================= */
21921  #define R_CRC_CRCCR0_DORCLR_Pos          (7UL)          /*!< DORCLR (Bit 7)                                        */
21922  #define R_CRC_CRCCR0_DORCLR_Msk          (0x80UL)       /*!< DORCLR (Bitfield-Mask: 0x01)                          */
21923  #define R_CRC_CRCCR0_LMS_Pos             (6UL)          /*!< LMS (Bit 6)                                           */
21924  #define R_CRC_CRCCR0_LMS_Msk             (0x40UL)       /*!< LMS (Bitfield-Mask: 0x01)                             */
21925  #define R_CRC_CRCCR0_GPS_Pos             (0UL)          /*!< GPS (Bit 0)                                           */
21926  #define R_CRC_CRCCR0_GPS_Msk             (0x7UL)        /*!< GPS (Bitfield-Mask: 0x07)                             */
21927 /* ========================================================  CRCCR1  ========================================================= */
21928  #define R_CRC_CRCCR1_CRCSEN_Pos          (7UL)          /*!< CRCSEN (Bit 7)                                        */
21929  #define R_CRC_CRCCR1_CRCSEN_Msk          (0x80UL)       /*!< CRCSEN (Bitfield-Mask: 0x01)                          */
21930  #define R_CRC_CRCCR1_CRCSWR_Pos          (6UL)          /*!< CRCSWR (Bit 6)                                        */
21931  #define R_CRC_CRCCR1_CRCSWR_Msk          (0x40UL)       /*!< CRCSWR (Bitfield-Mask: 0x01)                          */
21932 /* ========================================================  CRCDIR  ========================================================= */
21933  #define R_CRC_CRCDIR_CRCDIR_Pos          (0UL)          /*!< CRCDIR (Bit 0)                                        */
21934  #define R_CRC_CRCDIR_CRCDIR_Msk          (0xffffffffUL) /*!< CRCDIR (Bitfield-Mask: 0xffffffff)                    */
21935 /* =======================================================  CRCDIR_BY  ======================================================= */
21936  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Pos    (0UL)          /*!< CRCDIR_BY (Bit 0)                                     */
21937  #define R_CRC_CRCDIR_BY_CRCDIR_BY_Msk    (0xffUL)       /*!< CRCDIR_BY (Bitfield-Mask: 0xff)                       */
21938 /* ========================================================  CRCDOR  ========================================================= */
21939  #define R_CRC_CRCDOR_CRCDOR_Pos          (0UL)          /*!< CRCDOR (Bit 0)                                        */
21940  #define R_CRC_CRCDOR_CRCDOR_Msk          (0xffffffffUL) /*!< CRCDOR (Bitfield-Mask: 0xffffffff)                    */
21941 /* =======================================================  CRCDOR_HA  ======================================================= */
21942  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Pos    (0UL)          /*!< CRCDOR_HA (Bit 0)                                     */
21943  #define R_CRC_CRCDOR_HA_CRCDOR_HA_Msk    (0xffffUL)     /*!< CRCDOR_HA (Bitfield-Mask: 0xffff)                     */
21944 /* =======================================================  CRCDOR_BY  ======================================================= */
21945  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Pos    (0UL)          /*!< CRCDOR_BY (Bit 0)                                     */
21946  #define R_CRC_CRCDOR_BY_CRCDOR_BY_Msk    (0xffUL)       /*!< CRCDOR_BY (Bitfield-Mask: 0xff)                       */
21947 /* ========================================================  CRCSAR  ========================================================= */
21948  #define R_CRC_CRCSAR_CRCSA_Pos           (0UL)          /*!< CRCSA (Bit 0)                                         */
21949  #define R_CRC_CRCSAR_CRCSA_Msk           (0x3fffUL)     /*!< CRCSA (Bitfield-Mask: 0x3fff)                         */
21950 
21951 /* =========================================================================================================================== */
21952 /* ================                                          R_CTSU                                           ================ */
21953 /* =========================================================================================================================== */
21954 
21955 /* ========================================================  CTSUCR0  ======================================================== */
21956  #define R_CTSU_CTSUCR0_CTSUTXVSEL_Pos       (7UL)      /*!< CTSUTXVSEL (Bit 7)                                    */
21957  #define R_CTSU_CTSUCR0_CTSUTXVSEL_Msk       (0x80UL)   /*!< CTSUTXVSEL (Bitfield-Mask: 0x01)                      */
21958  #define R_CTSU_CTSUCR0_CTSUINIT_Pos         (4UL)      /*!< CTSUINIT (Bit 4)                                      */
21959  #define R_CTSU_CTSUCR0_CTSUINIT_Msk         (0x10UL)   /*!< CTSUINIT (Bitfield-Mask: 0x01)                        */
21960  #define R_CTSU_CTSUCR0_CTSUIOC_Pos          (3UL)      /*!< CTSUIOC (Bit 3)                                       */
21961  #define R_CTSU_CTSUCR0_CTSUIOC_Msk          (0x8UL)    /*!< CTSUIOC (Bitfield-Mask: 0x01)                         */
21962  #define R_CTSU_CTSUCR0_CTSUSNZ_Pos          (2UL)      /*!< CTSUSNZ (Bit 2)                                       */
21963  #define R_CTSU_CTSUCR0_CTSUSNZ_Msk          (0x4UL)    /*!< CTSUSNZ (Bitfield-Mask: 0x01)                         */
21964  #define R_CTSU_CTSUCR0_CTSUCAP_Pos          (1UL)      /*!< CTSUCAP (Bit 1)                                       */
21965  #define R_CTSU_CTSUCR0_CTSUCAP_Msk          (0x2UL)    /*!< CTSUCAP (Bitfield-Mask: 0x01)                         */
21966  #define R_CTSU_CTSUCR0_CTSUSTRT_Pos         (0UL)      /*!< CTSUSTRT (Bit 0)                                      */
21967  #define R_CTSU_CTSUCR0_CTSUSTRT_Msk         (0x1UL)    /*!< CTSUSTRT (Bitfield-Mask: 0x01)                        */
21968 /* ========================================================  CTSUCR1  ======================================================== */
21969  #define R_CTSU_CTSUCR1_CTSUMD_Pos           (6UL)      /*!< CTSUMD (Bit 6)                                        */
21970  #define R_CTSU_CTSUCR1_CTSUMD_Msk           (0xc0UL)   /*!< CTSUMD (Bitfield-Mask: 0x03)                          */
21971  #define R_CTSU_CTSUCR1_CTSUCLK_Pos          (4UL)      /*!< CTSUCLK (Bit 4)                                       */
21972  #define R_CTSU_CTSUCR1_CTSUCLK_Msk          (0x30UL)   /*!< CTSUCLK (Bitfield-Mask: 0x03)                         */
21973  #define R_CTSU_CTSUCR1_CTSUATUNE1_Pos       (3UL)      /*!< CTSUATUNE1 (Bit 3)                                    */
21974  #define R_CTSU_CTSUCR1_CTSUATUNE1_Msk       (0x8UL)    /*!< CTSUATUNE1 (Bitfield-Mask: 0x01)                      */
21975  #define R_CTSU_CTSUCR1_CTSUATUNE0_Pos       (2UL)      /*!< CTSUATUNE0 (Bit 2)                                    */
21976  #define R_CTSU_CTSUCR1_CTSUATUNE0_Msk       (0x4UL)    /*!< CTSUATUNE0 (Bitfield-Mask: 0x01)                      */
21977  #define R_CTSU_CTSUCR1_CTSUCSW_Pos          (1UL)      /*!< CTSUCSW (Bit 1)                                       */
21978  #define R_CTSU_CTSUCR1_CTSUCSW_Msk          (0x2UL)    /*!< CTSUCSW (Bitfield-Mask: 0x01)                         */
21979  #define R_CTSU_CTSUCR1_CTSUPON_Pos          (0UL)      /*!< CTSUPON (Bit 0)                                       */
21980  #define R_CTSU_CTSUCR1_CTSUPON_Msk          (0x1UL)    /*!< CTSUPON (Bitfield-Mask: 0x01)                         */
21981 /* =======================================================  CTSUSDPRS  ======================================================= */
21982  #define R_CTSU_CTSUSDPRS_CTSUSOFF_Pos       (6UL)      /*!< CTSUSOFF (Bit 6)                                      */
21983  #define R_CTSU_CTSUSDPRS_CTSUSOFF_Msk       (0x40UL)   /*!< CTSUSOFF (Bitfield-Mask: 0x01)                        */
21984  #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Pos     (4UL)      /*!< CTSUPRMODE (Bit 4)                                    */
21985  #define R_CTSU_CTSUSDPRS_CTSUPRMODE_Msk     (0x30UL)   /*!< CTSUPRMODE (Bitfield-Mask: 0x03)                      */
21986  #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Pos    (0UL)      /*!< CTSUPRRATIO (Bit 0)                                   */
21987  #define R_CTSU_CTSUSDPRS_CTSUPRRATIO_Msk    (0xfUL)    /*!< CTSUPRRATIO (Bitfield-Mask: 0x0f)                     */
21988 /* ========================================================  CTSUSST  ======================================================== */
21989  #define R_CTSU_CTSUSST_CTSUSST_Pos          (0UL)      /*!< CTSUSST (Bit 0)                                       */
21990  #define R_CTSU_CTSUSST_CTSUSST_Msk          (0xffUL)   /*!< CTSUSST (Bitfield-Mask: 0xff)                         */
21991 /* =======================================================  CTSUMCH0  ======================================================== */
21992  #define R_CTSU_CTSUMCH0_CTSUMCH0_Pos        (0UL)      /*!< CTSUMCH0 (Bit 0)                                      */
21993  #define R_CTSU_CTSUMCH0_CTSUMCH0_Msk        (0x3fUL)   /*!< CTSUMCH0 (Bitfield-Mask: 0x3f)                        */
21994 /* =======================================================  CTSUMCH1  ======================================================== */
21995  #define R_CTSU_CTSUMCH1_CTSUMCH1_Pos        (0UL)      /*!< CTSUMCH1 (Bit 0)                                      */
21996  #define R_CTSU_CTSUMCH1_CTSUMCH1_Msk        (0x3fUL)   /*!< CTSUMCH1 (Bitfield-Mask: 0x3f)                        */
21997 /* =======================================================  CTSUCHAC  ======================================================== */
21998  #define R_CTSU_CTSUCHAC_TS_Pos              (0UL)      /*!< TS (Bit 0)                                            */
21999  #define R_CTSU_CTSUCHAC_TS_Msk              (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
22000 /* =======================================================  CTSUCHTRC  ======================================================= */
22001  #define R_CTSU_CTSUCHTRC_TS_Pos             (0UL)      /*!< TS (Bit 0)                                            */
22002  #define R_CTSU_CTSUCHTRC_TS_Msk             (0x1UL)    /*!< TS (Bitfield-Mask: 0x01)                              */
22003 /* =======================================================  CTSUDCLKC  ======================================================= */
22004  #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Pos      (4UL)      /*!< CTSUSSCNT (Bit 4)                                     */
22005  #define R_CTSU_CTSUDCLKC_CTSUSSCNT_Msk      (0x30UL)   /*!< CTSUSSCNT (Bitfield-Mask: 0x03)                       */
22006  #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Pos      (0UL)      /*!< CTSUSSMOD (Bit 0)                                     */
22007  #define R_CTSU_CTSUDCLKC_CTSUSSMOD_Msk      (0x3UL)    /*!< CTSUSSMOD (Bitfield-Mask: 0x03)                       */
22008 /* ========================================================  CTSUST  ========================================================= */
22009  #define R_CTSU_CTSUST_CTSUPS_Pos            (7UL)      /*!< CTSUPS (Bit 7)                                        */
22010  #define R_CTSU_CTSUST_CTSUPS_Msk            (0x80UL)   /*!< CTSUPS (Bitfield-Mask: 0x01)                          */
22011  #define R_CTSU_CTSUST_CTSUROVF_Pos          (6UL)      /*!< CTSUROVF (Bit 6)                                      */
22012  #define R_CTSU_CTSUST_CTSUROVF_Msk          (0x40UL)   /*!< CTSUROVF (Bitfield-Mask: 0x01)                        */
22013  #define R_CTSU_CTSUST_CTSUSOVF_Pos          (5UL)      /*!< CTSUSOVF (Bit 5)                                      */
22014  #define R_CTSU_CTSUST_CTSUSOVF_Msk          (0x20UL)   /*!< CTSUSOVF (Bitfield-Mask: 0x01)                        */
22015  #define R_CTSU_CTSUST_CTSUDTSR_Pos          (4UL)      /*!< CTSUDTSR (Bit 4)                                      */
22016  #define R_CTSU_CTSUST_CTSUDTSR_Msk          (0x10UL)   /*!< CTSUDTSR (Bitfield-Mask: 0x01)                        */
22017  #define R_CTSU_CTSUST_CTSUSTC_Pos           (0UL)      /*!< CTSUSTC (Bit 0)                                       */
22018  #define R_CTSU_CTSUST_CTSUSTC_Msk           (0x7UL)    /*!< CTSUSTC (Bitfield-Mask: 0x07)                         */
22019 /* ========================================================  CTSUSSC  ======================================================== */
22020  #define R_CTSU_CTSUSSC_CTSUSSDIV_Pos        (8UL)      /*!< CTSUSSDIV (Bit 8)                                     */
22021  #define R_CTSU_CTSUSSC_CTSUSSDIV_Msk        (0xf00UL)  /*!< CTSUSSDIV (Bitfield-Mask: 0x0f)                       */
22022 /* ========================================================  CTSUSO0  ======================================================== */
22023  #define R_CTSU_CTSUSO0_CTSUSNUM_Pos         (10UL)     /*!< CTSUSNUM (Bit 10)                                     */
22024  #define R_CTSU_CTSUSO0_CTSUSNUM_Msk         (0xfc00UL) /*!< CTSUSNUM (Bitfield-Mask: 0x3f)                        */
22025  #define R_CTSU_CTSUSO0_CTSUSO_Pos           (0UL)      /*!< CTSUSO (Bit 0)                                        */
22026  #define R_CTSU_CTSUSO0_CTSUSO_Msk           (0x3ffUL)  /*!< CTSUSO (Bitfield-Mask: 0x3ff)                         */
22027 /* ========================================================  CTSUSO1  ======================================================== */
22028  #define R_CTSU_CTSUSO1_CTSUICOG_Pos         (13UL)     /*!< CTSUICOG (Bit 13)                                     */
22029  #define R_CTSU_CTSUSO1_CTSUICOG_Msk         (0x6000UL) /*!< CTSUICOG (Bitfield-Mask: 0x03)                        */
22030  #define R_CTSU_CTSUSO1_CTSUSDPA_Pos         (8UL)      /*!< CTSUSDPA (Bit 8)                                      */
22031  #define R_CTSU_CTSUSO1_CTSUSDPA_Msk         (0x1f00UL) /*!< CTSUSDPA (Bitfield-Mask: 0x1f)                        */
22032  #define R_CTSU_CTSUSO1_CTSURICOA_Pos        (0UL)      /*!< CTSURICOA (Bit 0)                                     */
22033  #define R_CTSU_CTSUSO1_CTSURICOA_Msk        (0xffUL)   /*!< CTSURICOA (Bitfield-Mask: 0xff)                       */
22034 /* ========================================================  CTSUSC  ========================================================= */
22035  #define R_CTSU_CTSUSC_CTSUSC_Pos            (0UL)      /*!< CTSUSC (Bit 0)                                        */
22036  #define R_CTSU_CTSUSC_CTSUSC_Msk            (0xffffUL) /*!< CTSUSC (Bitfield-Mask: 0xffff)                        */
22037 /* ========================================================  CTSURC  ========================================================= */
22038  #define R_CTSU_CTSURC_CTSURC_Pos            (0UL)      /*!< CTSURC (Bit 0)                                        */
22039  #define R_CTSU_CTSURC_CTSURC_Msk            (0xffffUL) /*!< CTSURC (Bitfield-Mask: 0xffff)                        */
22040 /* =======================================================  CTSUERRS  ======================================================== */
22041  #define R_CTSU_CTSUERRS_CTSUICOMP_Pos       (15UL)     /*!< CTSUICOMP (Bit 15)                                    */
22042  #define R_CTSU_CTSUERRS_CTSUICOMP_Msk       (0x8000UL) /*!< CTSUICOMP (Bitfield-Mask: 0x01)                       */
22043  #define R_CTSU_CTSUERRS_CTSUSPMD_Pos        (0UL)      /*!< CTSUSPMD (Bit 0)                                      */
22044  #define R_CTSU_CTSUERRS_CTSUSPMD_Msk        (0x3UL)    /*!< CTSUSPMD (Bitfield-Mask: 0x03)                        */
22045  #define R_CTSU_CTSUERRS_CTSUTSOD_Pos        (2UL)      /*!< CTSUTSOD (Bit 2)                                      */
22046  #define R_CTSU_CTSUERRS_CTSUTSOD_Msk        (0x4UL)    /*!< CTSUTSOD (Bitfield-Mask: 0x01)                        */
22047  #define R_CTSU_CTSUERRS_CTSUDRV_Pos         (3UL)      /*!< CTSUDRV (Bit 3)                                       */
22048  #define R_CTSU_CTSUERRS_CTSUDRV_Msk         (0x8UL)    /*!< CTSUDRV (Bitfield-Mask: 0x01)                         */
22049  #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Pos     (6UL)      /*!< CTSUCLKSEL1 (Bit 6)                                   */
22050  #define R_CTSU_CTSUERRS_CTSUCLKSEL1_Msk     (0x40UL)   /*!< CTSUCLKSEL1 (Bitfield-Mask: 0x01)                     */
22051  #define R_CTSU_CTSUERRS_CTSUTSOC_Pos        (7UL)      /*!< CTSUTSOC (Bit 7)                                      */
22052  #define R_CTSU_CTSUERRS_CTSUTSOC_Msk        (0x80UL)   /*!< CTSUTSOC (Bitfield-Mask: 0x01)                        */
22053 /* =======================================================  CTSUTRMR  ======================================================== */
22054 
22055 /* =========================================================================================================================== */
22056 /* ================                                           R_DAC                                           ================ */
22057 /* =========================================================================================================================== */
22058 
22059 /* =========================================================  DACR  ========================================================== */
22060  #define R_DAC_DACR_DAE_Pos            (5UL)      /*!< DAE (Bit 5)                                           */
22061  #define R_DAC_DACR_DAE_Msk            (0x20UL)   /*!< DAE (Bitfield-Mask: 0x01)                             */
22062  #define R_DAC_DACR_DAOE_Pos           (6UL)      /*!< DAOE (Bit 6)                                          */
22063  #define R_DAC_DACR_DAOE_Msk           (0x40UL)   /*!< DAOE (Bitfield-Mask: 0x01)                            */
22064 /* =========================================================  DADR  ========================================================== */
22065  #define R_DAC_DADR_DADR_Pos           (0UL)      /*!< DADR (Bit 0)                                          */
22066  #define R_DAC_DADR_DADR_Msk           (0xffffUL) /*!< DADR (Bitfield-Mask: 0xffff)                          */
22067 /* =========================================================  DADPR  ========================================================= */
22068  #define R_DAC_DADPR_DPSEL_Pos         (7UL)      /*!< DPSEL (Bit 7)                                         */
22069  #define R_DAC_DADPR_DPSEL_Msk         (0x80UL)   /*!< DPSEL (Bitfield-Mask: 0x01)                           */
22070 /* ========================================================  DAADSCR  ======================================================== */
22071  #define R_DAC_DAADSCR_DAADST_Pos      (7UL)      /*!< DAADST (Bit 7)                                        */
22072  #define R_DAC_DAADSCR_DAADST_Msk      (0x80UL)   /*!< DAADST (Bitfield-Mask: 0x01)                          */
22073 /* =======================================================  DAVREFCR  ======================================================== */
22074  #define R_DAC_DAVREFCR_REF_Pos        (0UL)      /*!< REF (Bit 0)                                           */
22075  #define R_DAC_DAVREFCR_REF_Msk        (0x7UL)    /*!< REF (Bitfield-Mask: 0x07)                             */
22076 /* =========================================================  DAPC  ========================================================== */
22077  #define R_DAC_DAPC_PUMPEN_Pos         (0UL)      /*!< PUMPEN (Bit 0)                                        */
22078  #define R_DAC_DAPC_PUMPEN_Msk         (0x1UL)    /*!< PUMPEN (Bitfield-Mask: 0x01)                          */
22079 /* ========================================================  DAAMPCR  ======================================================== */
22080  #define R_DAC_DAAMPCR_DAAMP_Pos       (6UL)      /*!< DAAMP (Bit 6)                                         */
22081  #define R_DAC_DAAMPCR_DAAMP_Msk       (0x40UL)   /*!< DAAMP (Bitfield-Mask: 0x01)                           */
22082 /* ========================================================  DAASWCR  ======================================================== */
22083  #define R_DAC_DAASWCR_DAASW1_Pos      (7UL)      /*!< DAASW1 (Bit 7)                                        */
22084  #define R_DAC_DAASWCR_DAASW1_Msk      (0x80UL)   /*!< DAASW1 (Bitfield-Mask: 0x01)                          */
22085  #define R_DAC_DAASWCR_DAASW0_Pos      (6UL)      /*!< DAASW0 (Bit 6)                                        */
22086  #define R_DAC_DAASWCR_DAASW0_Msk      (0x40UL)   /*!< DAASW0 (Bitfield-Mask: 0x01)                          */
22087 /* ========================================================  DAADUSR  ======================================================== */
22088  #define R_DAC_DAADUSR_AMADSEL0_Pos    (0UL)      /*!< AMADSEL0 (Bit 0)                                      */
22089  #define R_DAC_DAADUSR_AMADSEL0_Msk    (0x1UL)    /*!< AMADSEL0 (Bitfield-Mask: 0x01)                        */
22090  #define R_DAC_DAADUSR_AMADSEL1_Pos    (1UL)      /*!< AMADSEL1 (Bit 1)                                      */
22091  #define R_DAC_DAADUSR_AMADSEL1_Msk    (0x2UL)    /*!< AMADSEL1 (Bitfield-Mask: 0x01)                        */
22092 
22093 /* =========================================================================================================================== */
22094 /* ================                                          R_DEBUG                                          ================ */
22095 /* =========================================================================================================================== */
22096 
22097 /* ========================================================  DBGSTR  ========================================================= */
22098  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Pos        (28UL)         /*!< CDBGPWRUPREQ (Bit 28)                                 */
22099  #define R_DEBUG_DBGSTR_CDBGPWRUPREQ_Msk        (0x10000000UL) /*!< CDBGPWRUPREQ (Bitfield-Mask: 0x01)                    */
22100  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Pos        (29UL)         /*!< CDBGPWRUPACK (Bit 29)                                 */
22101  #define R_DEBUG_DBGSTR_CDBGPWRUPACK_Msk        (0x20000000UL) /*!< CDBGPWRUPACK (Bitfield-Mask: 0x01)                    */
22102 /* =======================================================  DBGSTOPCR  ======================================================= */
22103  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Pos     (24UL)         /*!< DBGSTOP_RPER (Bit 24)                                 */
22104  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RPER_Msk     (0x1000000UL)  /*!< DBGSTOP_RPER (Bitfield-Mask: 0x01)                    */
22105  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Pos      (14UL)         /*!< DBGSTOP_TIM (Bit 14)                                  */
22106  #define R_DEBUG_DBGSTOPCR_DBGSTOP_TIM_Msk      (0x4000UL)     /*!< DBGSTOP_TIM (Bitfield-Mask: 0x01)                     */
22107  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Pos      (15UL)         /*!< DBGSTOP_SIR (Bit 15)                                  */
22108  #define R_DEBUG_DBGSTOPCR_DBGSTOP_SIR_Msk      (0x8000UL)     /*!< DBGSTOP_SIR (Bitfield-Mask: 0x01)                     */
22109  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Pos      (16UL)         /*!< DBGSTOP_LVD (Bit 16)                                  */
22110  #define R_DEBUG_DBGSTOPCR_DBGSTOP_LVD_Msk      (0x10000UL)    /*!< DBGSTOP_LVD (Bitfield-Mask: 0x01)                     */
22111  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Pos    (25UL)         /*!< DBGSTOP_RECCR (Bit 25)                                */
22112  #define R_DEBUG_DBGSTOPCR_DBGSTOP_RECCR_Msk    (0x2000000UL)  /*!< DBGSTOP_RECCR (Bitfield-Mask: 0x01)                   */
22113  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Pos     (0UL)          /*!< DBGSTOP_IWDT (Bit 0)                                  */
22114  #define R_DEBUG_DBGSTOPCR_DBGSTOP_IWDT_Msk     (0x1UL)        /*!< DBGSTOP_IWDT (Bitfield-Mask: 0x01)                    */
22115  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Pos      (1UL)          /*!< DBGSTOP_WDT (Bit 1)                                   */
22116  #define R_DEBUG_DBGSTOPCR_DBGSTOP_WDT_Msk      (0x2UL)        /*!< DBGSTOP_WDT (Bitfield-Mask: 0x01)                     */
22117  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Pos     (31UL)         /*!< DBGSTOP_CPER (Bit 31)                                 */
22118  #define R_DEBUG_DBGSTOPCR_DBGSTOP_CPER_Msk     (0x80000000UL) /*!< DBGSTOP_CPER (Bitfield-Mask: 0x01)                    */
22119 /* =======================================================  FSBLSTAT  ======================================================== */
22120  #define R_DEBUG_FSBLSTAT_CS_Pos                (0UL)          /*!< CS (Bit 0)                                            */
22121  #define R_DEBUG_FSBLSTAT_CS_Msk                (0x1UL)        /*!< CS (Bitfield-Mask: 0x01)                              */
22122  #define R_DEBUG_FSBLSTAT_RS_Pos                (1UL)          /*!< RS (Bit 1)                                            */
22123  #define R_DEBUG_FSBLSTAT_RS_Msk                (0x2UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
22124  #define R_DEBUG_FSBLSTAT_FSBLCLK_Pos           (8UL)          /*!< FSBLCLK (Bit 8)                                       */
22125  #define R_DEBUG_FSBLSTAT_FSBLCLK_Msk           (0x700UL)      /*!< FSBLCLK (Bitfield-Mask: 0x07)                         */
22126 
22127 /* =========================================================================================================================== */
22128 /* ================                                           R_DMA                                           ================ */
22129 /* =========================================================================================================================== */
22130 
22131 /* =========================================================  DMAST  ========================================================= */
22132  #define R_DMA_DMAST_DMST_Pos         (0UL)       /*!< DMST (Bit 0)                                          */
22133  #define R_DMA_DMAST_DMST_Msk         (0x1UL)     /*!< DMST (Bitfield-Mask: 0x01)                            */
22134 /* ========================================================  DMECHR  ========================================================= */
22135  #define R_DMA_DMECHR_DMECH_Pos       (0UL)       /*!< DMECH (Bit 0)                                         */
22136  #define R_DMA_DMECHR_DMECH_Msk       (0x7UL)     /*!< DMECH (Bitfield-Mask: 0x07)                           */
22137  #define R_DMA_DMECHR_DMECHSAM_Pos    (8UL)       /*!< DMECHSAM (Bit 8)                                      */
22138  #define R_DMA_DMECHR_DMECHSAM_Msk    (0x100UL)   /*!< DMECHSAM (Bitfield-Mask: 0x01)                        */
22139  #define R_DMA_DMECHR_DMESTA_Pos      (16UL)      /*!< DMESTA (Bit 16)                                       */
22140  #define R_DMA_DMECHR_DMESTA_Msk      (0x10000UL) /*!< DMESTA (Bitfield-Mask: 0x01)                          */
22141 /* =========================================================  DELSR  ========================================================= */
22142  #define R_DMA_DELSR_IR_Pos           (16UL)      /*!< IR (Bit 16)                                           */
22143  #define R_DMA_DELSR_IR_Msk           (0x10000UL) /*!< IR (Bitfield-Mask: 0x01)                              */
22144  #define R_DMA_DELSR_DELS_Pos         (0UL)       /*!< DELS (Bit 0)                                          */
22145  #define R_DMA_DELSR_DELS_Msk         (0x1ffUL)   /*!< DELS (Bitfield-Mask: 0x1ff)                           */
22146 
22147 /* =========================================================================================================================== */
22148 /* ================                                          R_DMAC0                                          ================ */
22149 /* =========================================================================================================================== */
22150 
22151 /* =========================================================  DMSAR  ========================================================= */
22152  #define R_DMAC0_DMSAR_DMSAR_Pos     (0UL)          /*!< DMSAR (Bit 0)                                         */
22153  #define R_DMAC0_DMSAR_DMSAR_Msk     (0xffffffffUL) /*!< DMSAR (Bitfield-Mask: 0xffffffff)                     */
22154 /* =========================================================  DMDAR  ========================================================= */
22155  #define R_DMAC0_DMDAR_DMDAR_Pos     (0UL)          /*!< DMDAR (Bit 0)                                         */
22156  #define R_DMAC0_DMDAR_DMDAR_Msk     (0xffffffffUL) /*!< DMDAR (Bitfield-Mask: 0xffffffff)                     */
22157 /* =========================================================  DMCRA  ========================================================= */
22158  #define R_DMAC0_DMCRA_DMCRAH_Pos    (16UL)         /*!< DMCRAH (Bit 16)                                       */
22159  #define R_DMAC0_DMCRA_DMCRAH_Msk    (0x3ff0000UL)  /*!< DMCRAH (Bitfield-Mask: 0x3ff)                         */
22160  #define R_DMAC0_DMCRA_DMCRAL_Pos    (0UL)          /*!< DMCRAL (Bit 0)                                        */
22161  #define R_DMAC0_DMCRA_DMCRAL_Msk    (0xffffUL)     /*!< DMCRAL (Bitfield-Mask: 0xffff)                        */
22162 /* =========================================================  DMCRB  ========================================================= */
22163  #define R_DMAC0_DMCRB_DMCRBL_Pos    (0UL)          /*!< DMCRBL (Bit 0)                                        */
22164  #define R_DMAC0_DMCRB_DMCRBL_Msk    (0xffffUL)     /*!< DMCRBL (Bitfield-Mask: 0xffff)                        */
22165  #define R_DMAC0_DMCRB_DMCRBH_Pos    (16UL)         /*!< DMCRBH (Bit 16)                                       */
22166  #define R_DMAC0_DMCRB_DMCRBH_Msk    (0xffff0000UL) /*!< DMCRBH (Bitfield-Mask: 0xffff)                        */
22167 /* =========================================================  DMTMD  ========================================================= */
22168  #define R_DMAC0_DMTMD_MD_Pos        (14UL)         /*!< MD (Bit 14)                                           */
22169  #define R_DMAC0_DMTMD_MD_Msk        (0xc000UL)     /*!< MD (Bitfield-Mask: 0x03)                              */
22170  #define R_DMAC0_DMTMD_DTS_Pos       (12UL)         /*!< DTS (Bit 12)                                          */
22171  #define R_DMAC0_DMTMD_DTS_Msk       (0x3000UL)     /*!< DTS (Bitfield-Mask: 0x03)                             */
22172  #define R_DMAC0_DMTMD_SZ_Pos        (8UL)          /*!< SZ (Bit 8)                                            */
22173  #define R_DMAC0_DMTMD_SZ_Msk        (0x300UL)      /*!< SZ (Bitfield-Mask: 0x03)                              */
22174  #define R_DMAC0_DMTMD_DCTG_Pos      (0UL)          /*!< DCTG (Bit 0)                                          */
22175  #define R_DMAC0_DMTMD_DCTG_Msk      (0x3UL)        /*!< DCTG (Bitfield-Mask: 0x03)                            */
22176  #define R_DMAC0_DMTMD_TKP_Pos       (10UL)         /*!< TKP (Bit 10)                                          */
22177  #define R_DMAC0_DMTMD_TKP_Msk       (0x400UL)      /*!< TKP (Bitfield-Mask: 0x01)                             */
22178 /* =========================================================  DMINT  ========================================================= */
22179  #define R_DMAC0_DMINT_DTIE_Pos      (4UL)          /*!< DTIE (Bit 4)                                          */
22180  #define R_DMAC0_DMINT_DTIE_Msk      (0x10UL)       /*!< DTIE (Bitfield-Mask: 0x01)                            */
22181  #define R_DMAC0_DMINT_ESIE_Pos      (3UL)          /*!< ESIE (Bit 3)                                          */
22182  #define R_DMAC0_DMINT_ESIE_Msk      (0x8UL)        /*!< ESIE (Bitfield-Mask: 0x01)                            */
22183  #define R_DMAC0_DMINT_RPTIE_Pos     (2UL)          /*!< RPTIE (Bit 2)                                         */
22184  #define R_DMAC0_DMINT_RPTIE_Msk     (0x4UL)        /*!< RPTIE (Bitfield-Mask: 0x01)                           */
22185  #define R_DMAC0_DMINT_SARIE_Pos     (1UL)          /*!< SARIE (Bit 1)                                         */
22186  #define R_DMAC0_DMINT_SARIE_Msk     (0x2UL)        /*!< SARIE (Bitfield-Mask: 0x01)                           */
22187  #define R_DMAC0_DMINT_DARIE_Pos     (0UL)          /*!< DARIE (Bit 0)                                         */
22188  #define R_DMAC0_DMINT_DARIE_Msk     (0x1UL)        /*!< DARIE (Bitfield-Mask: 0x01)                           */
22189 /* =========================================================  DMAMD  ========================================================= */
22190  #define R_DMAC0_DMAMD_SM_Pos        (14UL)         /*!< SM (Bit 14)                                           */
22191  #define R_DMAC0_DMAMD_SM_Msk        (0xc000UL)     /*!< SM (Bitfield-Mask: 0x03)                              */
22192  #define R_DMAC0_DMAMD_SARA_Pos      (8UL)          /*!< SARA (Bit 8)                                          */
22193  #define R_DMAC0_DMAMD_SARA_Msk      (0x1f00UL)     /*!< SARA (Bitfield-Mask: 0x1f)                            */
22194  #define R_DMAC0_DMAMD_DM_Pos        (6UL)          /*!< DM (Bit 6)                                            */
22195  #define R_DMAC0_DMAMD_DM_Msk        (0xc0UL)       /*!< DM (Bitfield-Mask: 0x03)                              */
22196  #define R_DMAC0_DMAMD_DARA_Pos      (0UL)          /*!< DARA (Bit 0)                                          */
22197  #define R_DMAC0_DMAMD_DARA_Msk      (0x1fUL)       /*!< DARA (Bitfield-Mask: 0x1f)                            */
22198  #define R_DMAC0_DMAMD_DADR_Pos      (5UL)          /*!< DADR (Bit 5)                                          */
22199  #define R_DMAC0_DMAMD_DADR_Msk      (0x20UL)       /*!< DADR (Bitfield-Mask: 0x01)                            */
22200  #define R_DMAC0_DMAMD_SADR_Pos      (13UL)         /*!< SADR (Bit 13)                                         */
22201  #define R_DMAC0_DMAMD_SADR_Msk      (0x2000UL)     /*!< SADR (Bitfield-Mask: 0x01)                            */
22202 /* =========================================================  DMOFR  ========================================================= */
22203  #define R_DMAC0_DMOFR_DMOFR_Pos     (0UL)          /*!< DMOFR (Bit 0)                                         */
22204  #define R_DMAC0_DMOFR_DMOFR_Msk     (0xffffffffUL) /*!< DMOFR (Bitfield-Mask: 0xffffffff)                     */
22205 /* =========================================================  DMCNT  ========================================================= */
22206  #define R_DMAC0_DMCNT_DTE_Pos       (0UL)          /*!< DTE (Bit 0)                                           */
22207  #define R_DMAC0_DMCNT_DTE_Msk       (0x1UL)        /*!< DTE (Bitfield-Mask: 0x01)                             */
22208 /* =========================================================  DMREQ  ========================================================= */
22209  #define R_DMAC0_DMREQ_CLRS_Pos      (4UL)          /*!< CLRS (Bit 4)                                          */
22210  #define R_DMAC0_DMREQ_CLRS_Msk      (0x10UL)       /*!< CLRS (Bitfield-Mask: 0x01)                            */
22211  #define R_DMAC0_DMREQ_SWREQ_Pos     (0UL)          /*!< SWREQ (Bit 0)                                         */
22212  #define R_DMAC0_DMREQ_SWREQ_Msk     (0x1UL)        /*!< SWREQ (Bitfield-Mask: 0x01)                           */
22213 /* =========================================================  DMSTS  ========================================================= */
22214  #define R_DMAC0_DMSTS_ACT_Pos       (7UL)          /*!< ACT (Bit 7)                                           */
22215  #define R_DMAC0_DMSTS_ACT_Msk       (0x80UL)       /*!< ACT (Bitfield-Mask: 0x01)                             */
22216  #define R_DMAC0_DMSTS_DTIF_Pos      (4UL)          /*!< DTIF (Bit 4)                                          */
22217  #define R_DMAC0_DMSTS_DTIF_Msk      (0x10UL)       /*!< DTIF (Bitfield-Mask: 0x01)                            */
22218  #define R_DMAC0_DMSTS_ESIF_Pos      (0UL)          /*!< ESIF (Bit 0)                                          */
22219  #define R_DMAC0_DMSTS_ESIF_Msk      (0x1UL)        /*!< ESIF (Bitfield-Mask: 0x01)                            */
22220 /* =========================================================  DMSRR  ========================================================= */
22221 /* =========================================================  DMDRR  ========================================================= */
22222 /* =========================================================  DMSBS  ========================================================= */
22223  #define R_DMAC0_DMSBS_DMSBSL_Pos    (0UL)          /*!< DMSBSL (Bit 0)                                        */
22224  #define R_DMAC0_DMSBS_DMSBSL_Msk    (0xffffUL)     /*!< DMSBSL (Bitfield-Mask: 0xffff)                        */
22225  #define R_DMAC0_DMSBS_DMSBSH_Pos    (16UL)         /*!< DMSBSH (Bit 16)                                       */
22226  #define R_DMAC0_DMSBS_DMSBSH_Msk    (0xffff0000UL) /*!< DMSBSH (Bitfield-Mask: 0xffff)                        */
22227 /* =========================================================  DMDBS  ========================================================= */
22228  #define R_DMAC0_DMDBS_DMDBSL_Pos    (0UL)          /*!< DMDBSL (Bit 0)                                        */
22229  #define R_DMAC0_DMDBS_DMDBSL_Msk    (0xffffUL)     /*!< DMDBSL (Bitfield-Mask: 0xffff)                        */
22230  #define R_DMAC0_DMDBS_DMDBSH_Pos    (16UL)         /*!< DMDBSH (Bit 16)                                       */
22231  #define R_DMAC0_DMDBS_DMDBSH_Msk    (0xffff0000UL) /*!< DMDBSH (Bitfield-Mask: 0xffff)                        */
22232 /* =========================================================  DMBWR  ========================================================= */
22233  #define R_DMAC0_DMBWR_BWE_Pos       (0UL)          /*!< BWE (Bit 0)                                           */
22234  #define R_DMAC0_DMBWR_BWE_Msk       (0x1UL)        /*!< BWE (Bitfield-Mask: 0x01)                             */
22235 
22236 /* =========================================================================================================================== */
22237 /* ================                                           R_DOC                                           ================ */
22238 /* =========================================================================================================================== */
22239 
22240 /* =========================================================  DOCR  ========================================================== */
22241  #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)      /*!< DOPCFCL (Bit 6)                                       */
22242  #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL)   /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
22243  #define R_DOC_DOCR_DOPCF_Pos      (5UL)      /*!< DOPCF (Bit 5)                                         */
22244  #define R_DOC_DOCR_DOPCF_Msk      (0x20UL)   /*!< DOPCF (Bitfield-Mask: 0x01)                           */
22245  #define R_DOC_DOCR_DCSEL_Pos      (2UL)      /*!< DCSEL (Bit 2)                                         */
22246  #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)    /*!< DCSEL (Bitfield-Mask: 0x01)                           */
22247  #define R_DOC_DOCR_OMS_Pos        (0UL)      /*!< OMS (Bit 0)                                           */
22248  #define R_DOC_DOCR_OMS_Msk        (0x3UL)    /*!< OMS (Bitfield-Mask: 0x03)                             */
22249 /* =========================================================  DODIR  ========================================================= */
22250  #define R_DOC_DODIR_DODIR_Pos     (0UL)      /*!< DODIR (Bit 0)                                         */
22251  #define R_DOC_DODIR_DODIR_Msk     (0xffffUL) /*!< DODIR (Bitfield-Mask: 0xffff)                         */
22252 /* =========================================================  DODSR  ========================================================= */
22253  #define R_DOC_DODSR_DODSR_Pos     (0UL)      /*!< DODSR (Bit 0)                                         */
22254  #define R_DOC_DODSR_DODSR_Msk     (0xffffUL) /*!< DODSR (Bitfield-Mask: 0xffff)                         */
22255 
22256 /* =========================================================================================================================== */
22257 /* ================                                           R_DTC                                           ================ */
22258 /* =========================================================================================================================== */
22259 
22260 /* =========================================================  DTCCR  ========================================================= */
22261  #define R_DTC_DTCCR_RRS_Pos         (4UL)          /*!< RRS (Bit 4)                                           */
22262  #define R_DTC_DTCCR_RRS_Msk         (0x10UL)       /*!< RRS (Bitfield-Mask: 0x01)                             */
22263 /* ========================================================  DTCVBR  ========================================================= */
22264  #define R_DTC_DTCVBR_DTCVBR_Pos     (0UL)          /*!< DTCVBR (Bit 0)                                        */
22265  #define R_DTC_DTCVBR_DTCVBR_Msk     (0xffffffffUL) /*!< DTCVBR (Bitfield-Mask: 0xffffffff)                    */
22266 /* =========================================================  DTCST  ========================================================= */
22267  #define R_DTC_DTCST_DTCST_Pos       (0UL)          /*!< DTCST (Bit 0)                                         */
22268  #define R_DTC_DTCST_DTCST_Msk       (0x1UL)        /*!< DTCST (Bitfield-Mask: 0x01)                           */
22269 /* ========================================================  DTCSTS  ========================================================= */
22270  #define R_DTC_DTCSTS_ACT_Pos        (15UL)         /*!< ACT (Bit 15)                                          */
22271  #define R_DTC_DTCSTS_ACT_Msk        (0x8000UL)     /*!< ACT (Bitfield-Mask: 0x01)                             */
22272  #define R_DTC_DTCSTS_VECN_Pos       (0UL)          /*!< VECN (Bit 0)                                          */
22273  #define R_DTC_DTCSTS_VECN_Msk       (0xffUL)       /*!< VECN (Bitfield-Mask: 0xff)                            */
22274 /* =======================================================  DTCCR_SEC  ======================================================= */
22275  #define R_DTC_DTCCR_SEC_RRSS_Pos    (4UL)          /*!< RRSS (Bit 4)                                          */
22276  #define R_DTC_DTCCR_SEC_RRSS_Msk    (0x10UL)       /*!< RRSS (Bitfield-Mask: 0x01)                            */
22277 /* ======================================================  DTCVBR_SEC  ======================================================= */
22278 /* =========================================================  DTEVR  ========================================================= */
22279  #define R_DTC_DTEVR_DTEV_Pos        (0UL)          /*!< DTEV (Bit 0)                                          */
22280  #define R_DTC_DTEVR_DTEV_Msk        (0xffUL)       /*!< DTEV (Bitfield-Mask: 0xff)                            */
22281  #define R_DTC_DTEVR_DTEVSAM_Pos     (8UL)          /*!< DTEVSAM (Bit 8)                                       */
22282  #define R_DTC_DTEVR_DTEVSAM_Msk     (0x100UL)      /*!< DTEVSAM (Bitfield-Mask: 0x01)                         */
22283  #define R_DTC_DTEVR_DTESTA_Pos      (16UL)         /*!< DTESTA (Bit 16)                                       */
22284  #define R_DTC_DTEVR_DTESTA_Msk      (0x10000UL)    /*!< DTESTA (Bitfield-Mask: 0x01)                          */
22285 
22286 /* =========================================================================================================================== */
22287 /* ================                                           R_ELC                                           ================ */
22288 /* =========================================================================================================================== */
22289 
22290 /* =========================================================  ELCR  ========================================================== */
22291  #define R_ELC_ELCR_ELCON_Pos         (7UL)      /*!< ELCON (Bit 7)                                         */
22292  #define R_ELC_ELCR_ELCON_Msk         (0x80UL)   /*!< ELCON (Bitfield-Mask: 0x01)                           */
22293 /* ========================================================  ELCSARA  ======================================================== */
22294  #define R_ELC_ELCSARA_ELCR_Pos       (0UL)      /*!< ELCR (Bit 0)                                          */
22295  #define R_ELC_ELCSARA_ELCR_Msk       (0x1UL)    /*!< ELCR (Bitfield-Mask: 0x01)                            */
22296  #define R_ELC_ELCSARA_ELSEGR0_Pos    (1UL)      /*!< ELSEGR0 (Bit 1)                                       */
22297  #define R_ELC_ELCSARA_ELSEGR0_Msk    (0x2UL)    /*!< ELSEGR0 (Bitfield-Mask: 0x01)                         */
22298  #define R_ELC_ELCSARA_ELSEGR1_Pos    (2UL)      /*!< ELSEGR1 (Bit 2)                                       */
22299  #define R_ELC_ELCSARA_ELSEGR1_Msk    (0x4UL)    /*!< ELSEGR1 (Bitfield-Mask: 0x01)                         */
22300 /* ========================================================  ELCSARB  ======================================================== */
22301  #define R_ELC_ELCSARB_ELSR0_Pos      (0UL)      /*!< ELSR0 (Bit 0)                                         */
22302  #define R_ELC_ELCSARB_ELSR0_Msk      (0x1UL)    /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
22303  #define R_ELC_ELCSARB_ELSR1_Pos      (1UL)      /*!< ELSR1 (Bit 1)                                         */
22304  #define R_ELC_ELCSARB_ELSR1_Msk      (0x2UL)    /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
22305  #define R_ELC_ELCSARB_ELSR2_Pos      (2UL)      /*!< ELSR2 (Bit 2)                                         */
22306  #define R_ELC_ELCSARB_ELSR2_Msk      (0x4UL)    /*!< ELSR2 (Bitfield-Mask: 0x01)                           */
22307  #define R_ELC_ELCSARB_ELSR3_Pos      (3UL)      /*!< ELSR3 (Bit 3)                                         */
22308  #define R_ELC_ELCSARB_ELSR3_Msk      (0x8UL)    /*!< ELSR3 (Bitfield-Mask: 0x01)                           */
22309  #define R_ELC_ELCSARB_ELSR4_Pos      (4UL)      /*!< ELSR4 (Bit 4)                                         */
22310  #define R_ELC_ELCSARB_ELSR4_Msk      (0x10UL)   /*!< ELSR4 (Bitfield-Mask: 0x01)                           */
22311  #define R_ELC_ELCSARB_ELSR5_Pos      (5UL)      /*!< ELSR5 (Bit 5)                                         */
22312  #define R_ELC_ELCSARB_ELSR5_Msk      (0x20UL)   /*!< ELSR5 (Bitfield-Mask: 0x01)                           */
22313  #define R_ELC_ELCSARB_ELSR6_Pos      (6UL)      /*!< ELSR6 (Bit 6)                                         */
22314  #define R_ELC_ELCSARB_ELSR6_Msk      (0x40UL)   /*!< ELSR6 (Bitfield-Mask: 0x01)                           */
22315  #define R_ELC_ELCSARB_ELSR7_Pos      (7UL)      /*!< ELSR7 (Bit 7)                                         */
22316  #define R_ELC_ELCSARB_ELSR7_Msk      (0x80UL)   /*!< ELSR7 (Bitfield-Mask: 0x01)                           */
22317  #define R_ELC_ELCSARB_ELSR8_Pos      (8UL)      /*!< ELSR8 (Bit 8)                                         */
22318  #define R_ELC_ELCSARB_ELSR8_Msk      (0x100UL)  /*!< ELSR8 (Bitfield-Mask: 0x01)                           */
22319  #define R_ELC_ELCSARB_ELSR9_Pos      (9UL)      /*!< ELSR9 (Bit 9)                                         */
22320  #define R_ELC_ELCSARB_ELSR9_Msk      (0x200UL)  /*!< ELSR9 (Bitfield-Mask: 0x01)                           */
22321  #define R_ELC_ELCSARB_ELSR10_Pos     (10UL)     /*!< ELSR10 (Bit 10)                                       */
22322  #define R_ELC_ELCSARB_ELSR10_Msk     (0x400UL)  /*!< ELSR10 (Bitfield-Mask: 0x01)                          */
22323  #define R_ELC_ELCSARB_ELSR11_Pos     (11UL)     /*!< ELSR11 (Bit 11)                                       */
22324  #define R_ELC_ELCSARB_ELSR11_Msk     (0x800UL)  /*!< ELSR11 (Bitfield-Mask: 0x01)                          */
22325  #define R_ELC_ELCSARB_ELSR12_Pos     (12UL)     /*!< ELSR12 (Bit 12)                                       */
22326  #define R_ELC_ELCSARB_ELSR12_Msk     (0x1000UL) /*!< ELSR12 (Bitfield-Mask: 0x01)                          */
22327  #define R_ELC_ELCSARB_ELSR13_Pos     (13UL)     /*!< ELSR13 (Bit 13)                                       */
22328  #define R_ELC_ELCSARB_ELSR13_Msk     (0x2000UL) /*!< ELSR13 (Bitfield-Mask: 0x01)                          */
22329  #define R_ELC_ELCSARB_ELSR14_Pos     (14UL)     /*!< ELSR14 (Bit 14)                                       */
22330  #define R_ELC_ELCSARB_ELSR14_Msk     (0x4000UL) /*!< ELSR14 (Bitfield-Mask: 0x01)                          */
22331  #define R_ELC_ELCSARB_ELSR15_Pos     (15UL)     /*!< ELSR15 (Bit 15)                                       */
22332  #define R_ELC_ELCSARB_ELSR15_Msk     (0x8000UL) /*!< ELSR15 (Bitfield-Mask: 0x01)                          */
22333 /* ========================================================  ELCSARC  ======================================================== */
22334  #define R_ELC_ELCSARC_ELSR16_Pos     (0UL)      /*!< ELSR16 (Bit 0)                                        */
22335  #define R_ELC_ELCSARC_ELSR16_Msk     (0x1UL)    /*!< ELSR16 (Bitfield-Mask: 0x01)                          */
22336  #define R_ELC_ELCSARC_ELSR17_Pos     (1UL)      /*!< ELSR17 (Bit 1)                                        */
22337  #define R_ELC_ELCSARC_ELSR17_Msk     (0x2UL)    /*!< ELSR17 (Bitfield-Mask: 0x01)                          */
22338  #define R_ELC_ELCSARC_ELSR18_Pos     (2UL)      /*!< ELSR18 (Bit 2)                                        */
22339  #define R_ELC_ELCSARC_ELSR18_Msk     (0x4UL)    /*!< ELSR18 (Bitfield-Mask: 0x01)                          */
22340 
22341 /* =========================================================================================================================== */
22342 /* ================                                         R_ETHERC0                                         ================ */
22343 /* =========================================================================================================================== */
22344 
22345 /* =========================================================  ECMR  ========================================================== */
22346  #define R_ETHERC0_ECMR_TPC_Pos          (20UL)         /*!< TPC (Bit 20)                                          */
22347  #define R_ETHERC0_ECMR_TPC_Msk          (0x100000UL)   /*!< TPC (Bitfield-Mask: 0x01)                             */
22348  #define R_ETHERC0_ECMR_ZPF_Pos          (19UL)         /*!< ZPF (Bit 19)                                          */
22349  #define R_ETHERC0_ECMR_ZPF_Msk          (0x80000UL)    /*!< ZPF (Bitfield-Mask: 0x01)                             */
22350  #define R_ETHERC0_ECMR_PFR_Pos          (18UL)         /*!< PFR (Bit 18)                                          */
22351  #define R_ETHERC0_ECMR_PFR_Msk          (0x40000UL)    /*!< PFR (Bitfield-Mask: 0x01)                             */
22352  #define R_ETHERC0_ECMR_RXF_Pos          (17UL)         /*!< RXF (Bit 17)                                          */
22353  #define R_ETHERC0_ECMR_RXF_Msk          (0x20000UL)    /*!< RXF (Bitfield-Mask: 0x01)                             */
22354  #define R_ETHERC0_ECMR_TXF_Pos          (16UL)         /*!< TXF (Bit 16)                                          */
22355  #define R_ETHERC0_ECMR_TXF_Msk          (0x10000UL)    /*!< TXF (Bitfield-Mask: 0x01)                             */
22356  #define R_ETHERC0_ECMR_PRCEF_Pos        (12UL)         /*!< PRCEF (Bit 12)                                        */
22357  #define R_ETHERC0_ECMR_PRCEF_Msk        (0x1000UL)     /*!< PRCEF (Bitfield-Mask: 0x01)                           */
22358  #define R_ETHERC0_ECMR_MPDE_Pos         (9UL)          /*!< MPDE (Bit 9)                                          */
22359  #define R_ETHERC0_ECMR_MPDE_Msk         (0x200UL)      /*!< MPDE (Bitfield-Mask: 0x01)                            */
22360  #define R_ETHERC0_ECMR_RE_Pos           (6UL)          /*!< RE (Bit 6)                                            */
22361  #define R_ETHERC0_ECMR_RE_Msk           (0x40UL)       /*!< RE (Bitfield-Mask: 0x01)                              */
22362  #define R_ETHERC0_ECMR_TE_Pos           (5UL)          /*!< TE (Bit 5)                                            */
22363  #define R_ETHERC0_ECMR_TE_Msk           (0x20UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
22364  #define R_ETHERC0_ECMR_ILB_Pos          (3UL)          /*!< ILB (Bit 3)                                           */
22365  #define R_ETHERC0_ECMR_ILB_Msk          (0x8UL)        /*!< ILB (Bitfield-Mask: 0x01)                             */
22366  #define R_ETHERC0_ECMR_RTM_Pos          (2UL)          /*!< RTM (Bit 2)                                           */
22367  #define R_ETHERC0_ECMR_RTM_Msk          (0x4UL)        /*!< RTM (Bitfield-Mask: 0x01)                             */
22368  #define R_ETHERC0_ECMR_DM_Pos           (1UL)          /*!< DM (Bit 1)                                            */
22369  #define R_ETHERC0_ECMR_DM_Msk           (0x2UL)        /*!< DM (Bitfield-Mask: 0x01)                              */
22370  #define R_ETHERC0_ECMR_PRM_Pos          (0UL)          /*!< PRM (Bit 0)                                           */
22371  #define R_ETHERC0_ECMR_PRM_Msk          (0x1UL)        /*!< PRM (Bitfield-Mask: 0x01)                             */
22372 /* =========================================================  RFLR  ========================================================== */
22373  #define R_ETHERC0_RFLR_RFL_Pos          (0UL)          /*!< RFL (Bit 0)                                           */
22374  #define R_ETHERC0_RFLR_RFL_Msk          (0xfffUL)      /*!< RFL (Bitfield-Mask: 0xfff)                            */
22375 /* =========================================================  ECSR  ========================================================== */
22376  #define R_ETHERC0_ECSR_BFR_Pos          (5UL)          /*!< BFR (Bit 5)                                           */
22377  #define R_ETHERC0_ECSR_BFR_Msk          (0x20UL)       /*!< BFR (Bitfield-Mask: 0x01)                             */
22378  #define R_ETHERC0_ECSR_PSRTO_Pos        (4UL)          /*!< PSRTO (Bit 4)                                         */
22379  #define R_ETHERC0_ECSR_PSRTO_Msk        (0x10UL)       /*!< PSRTO (Bitfield-Mask: 0x01)                           */
22380  #define R_ETHERC0_ECSR_LCHNG_Pos        (2UL)          /*!< LCHNG (Bit 2)                                         */
22381  #define R_ETHERC0_ECSR_LCHNG_Msk        (0x4UL)        /*!< LCHNG (Bitfield-Mask: 0x01)                           */
22382  #define R_ETHERC0_ECSR_MPD_Pos          (1UL)          /*!< MPD (Bit 1)                                           */
22383  #define R_ETHERC0_ECSR_MPD_Msk          (0x2UL)        /*!< MPD (Bitfield-Mask: 0x01)                             */
22384  #define R_ETHERC0_ECSR_ICD_Pos          (0UL)          /*!< ICD (Bit 0)                                           */
22385  #define R_ETHERC0_ECSR_ICD_Msk          (0x1UL)        /*!< ICD (Bitfield-Mask: 0x01)                             */
22386 /* ========================================================  ECSIPR  ========================================================= */
22387  #define R_ETHERC0_ECSIPR_BFSIPR_Pos     (5UL)          /*!< BFSIPR (Bit 5)                                        */
22388  #define R_ETHERC0_ECSIPR_BFSIPR_Msk     (0x20UL)       /*!< BFSIPR (Bitfield-Mask: 0x01)                          */
22389  #define R_ETHERC0_ECSIPR_PSRTOIP_Pos    (4UL)          /*!< PSRTOIP (Bit 4)                                       */
22390  #define R_ETHERC0_ECSIPR_PSRTOIP_Msk    (0x10UL)       /*!< PSRTOIP (Bitfield-Mask: 0x01)                         */
22391  #define R_ETHERC0_ECSIPR_LCHNGIP_Pos    (2UL)          /*!< LCHNGIP (Bit 2)                                       */
22392  #define R_ETHERC0_ECSIPR_LCHNGIP_Msk    (0x4UL)        /*!< LCHNGIP (Bitfield-Mask: 0x01)                         */
22393  #define R_ETHERC0_ECSIPR_MPDIP_Pos      (1UL)          /*!< MPDIP (Bit 1)                                         */
22394  #define R_ETHERC0_ECSIPR_MPDIP_Msk      (0x2UL)        /*!< MPDIP (Bitfield-Mask: 0x01)                           */
22395  #define R_ETHERC0_ECSIPR_ICDIP_Pos      (0UL)          /*!< ICDIP (Bit 0)                                         */
22396  #define R_ETHERC0_ECSIPR_ICDIP_Msk      (0x1UL)        /*!< ICDIP (Bitfield-Mask: 0x01)                           */
22397 /* ==========================================================  PIR  ========================================================== */
22398  #define R_ETHERC0_PIR_MDI_Pos           (3UL)          /*!< MDI (Bit 3)                                           */
22399  #define R_ETHERC0_PIR_MDI_Msk           (0x8UL)        /*!< MDI (Bitfield-Mask: 0x01)                             */
22400  #define R_ETHERC0_PIR_MDO_Pos           (2UL)          /*!< MDO (Bit 2)                                           */
22401  #define R_ETHERC0_PIR_MDO_Msk           (0x4UL)        /*!< MDO (Bitfield-Mask: 0x01)                             */
22402  #define R_ETHERC0_PIR_MMD_Pos           (1UL)          /*!< MMD (Bit 1)                                           */
22403  #define R_ETHERC0_PIR_MMD_Msk           (0x2UL)        /*!< MMD (Bitfield-Mask: 0x01)                             */
22404  #define R_ETHERC0_PIR_MDC_Pos           (0UL)          /*!< MDC (Bit 0)                                           */
22405  #define R_ETHERC0_PIR_MDC_Msk           (0x1UL)        /*!< MDC (Bitfield-Mask: 0x01)                             */
22406 /* ==========================================================  PSR  ========================================================== */
22407  #define R_ETHERC0_PSR_LMON_Pos          (0UL)          /*!< LMON (Bit 0)                                          */
22408  #define R_ETHERC0_PSR_LMON_Msk          (0x1UL)        /*!< LMON (Bitfield-Mask: 0x01)                            */
22409 /* =========================================================  RDMLR  ========================================================= */
22410  #define R_ETHERC0_RDMLR_RMD_Pos         (0UL)          /*!< RMD (Bit 0)                                           */
22411  #define R_ETHERC0_RDMLR_RMD_Msk         (0xfffffUL)    /*!< RMD (Bitfield-Mask: 0xfffff)                          */
22412 /* =========================================================  IPGR  ========================================================== */
22413  #define R_ETHERC0_IPGR_IPG_Pos          (0UL)          /*!< IPG (Bit 0)                                           */
22414  #define R_ETHERC0_IPGR_IPG_Msk          (0x1fUL)       /*!< IPG (Bitfield-Mask: 0x1f)                             */
22415 /* ==========================================================  APR  ========================================================== */
22416  #define R_ETHERC0_APR_AP_Pos            (0UL)          /*!< AP (Bit 0)                                            */
22417  #define R_ETHERC0_APR_AP_Msk            (0xffffUL)     /*!< AP (Bitfield-Mask: 0xffff)                            */
22418 /* ==========================================================  MPR  ========================================================== */
22419  #define R_ETHERC0_MPR_MP_Pos            (0UL)          /*!< MP (Bit 0)                                            */
22420  #define R_ETHERC0_MPR_MP_Msk            (0xffffUL)     /*!< MP (Bitfield-Mask: 0xffff)                            */
22421 /* =========================================================  RFCF  ========================================================== */
22422  #define R_ETHERC0_RFCF_RPAUSE_Pos       (0UL)          /*!< RPAUSE (Bit 0)                                        */
22423  #define R_ETHERC0_RFCF_RPAUSE_Msk       (0xffUL)       /*!< RPAUSE (Bitfield-Mask: 0xff)                          */
22424 /* ========================================================  TPAUSER  ======================================================== */
22425  #define R_ETHERC0_TPAUSER_TPAUSE_Pos    (0UL)          /*!< TPAUSE (Bit 0)                                        */
22426  #define R_ETHERC0_TPAUSER_TPAUSE_Msk    (0xffffUL)     /*!< TPAUSE (Bitfield-Mask: 0xffff)                        */
22427 /* =======================================================  TPAUSECR  ======================================================== */
22428 /* =========================================================  BCFRR  ========================================================= */
22429  #define R_ETHERC0_BCFRR_BCF_Pos         (0UL)          /*!< BCF (Bit 0)                                           */
22430  #define R_ETHERC0_BCFRR_BCF_Msk         (0xffffUL)     /*!< BCF (Bitfield-Mask: 0xffff)                           */
22431 /* =========================================================  MAHR  ========================================================== */
22432  #define R_ETHERC0_MAHR_MAHR_Pos         (0UL)          /*!< MAHR (Bit 0)                                          */
22433  #define R_ETHERC0_MAHR_MAHR_Msk         (0xffffffffUL) /*!< MAHR (Bitfield-Mask: 0xffffffff)                      */
22434 /* =========================================================  MALR  ========================================================== */
22435  #define R_ETHERC0_MALR_MALR_Pos         (0UL)          /*!< MALR (Bit 0)                                          */
22436  #define R_ETHERC0_MALR_MALR_Msk         (0xffffUL)     /*!< MALR (Bitfield-Mask: 0xffff)                          */
22437 /* =========================================================  TROCR  ========================================================= */
22438  #define R_ETHERC0_TROCR_TROCR_Pos       (0UL)          /*!< TROCR (Bit 0)                                         */
22439  #define R_ETHERC0_TROCR_TROCR_Msk       (0xffffffffUL) /*!< TROCR (Bitfield-Mask: 0xffffffff)                     */
22440 /* =========================================================  CDCR  ========================================================== */
22441 /* =========================================================  LCCR  ========================================================== */
22442  #define R_ETHERC0_LCCR_LCCR_Pos         (0UL)          /*!< LCCR (Bit 0)                                          */
22443  #define R_ETHERC0_LCCR_LCCR_Msk         (0xffffffffUL) /*!< LCCR (Bitfield-Mask: 0xffffffff)                      */
22444 /* =========================================================  CNDCR  ========================================================= */
22445  #define R_ETHERC0_CNDCR_CNDCR_Pos       (0UL)          /*!< CNDCR (Bit 0)                                         */
22446  #define R_ETHERC0_CNDCR_CNDCR_Msk       (0xffffffffUL) /*!< CNDCR (Bitfield-Mask: 0xffffffff)                     */
22447 /* =========================================================  CEFCR  ========================================================= */
22448  #define R_ETHERC0_CEFCR_CEFCR_Pos       (0UL)          /*!< CEFCR (Bit 0)                                         */
22449  #define R_ETHERC0_CEFCR_CEFCR_Msk       (0xffffffffUL) /*!< CEFCR (Bitfield-Mask: 0xffffffff)                     */
22450 /* =========================================================  FRECR  ========================================================= */
22451  #define R_ETHERC0_FRECR_FRECR_Pos       (0UL)          /*!< FRECR (Bit 0)                                         */
22452  #define R_ETHERC0_FRECR_FRECR_Msk       (0xffffffffUL) /*!< FRECR (Bitfield-Mask: 0xffffffff)                     */
22453 /* ========================================================  TSFRCR  ========================================================= */
22454  #define R_ETHERC0_TSFRCR_TSFRCR_Pos     (0UL)          /*!< TSFRCR (Bit 0)                                        */
22455  #define R_ETHERC0_TSFRCR_TSFRCR_Msk     (0xffffffffUL) /*!< TSFRCR (Bitfield-Mask: 0xffffffff)                    */
22456 /* ========================================================  TLFRCR  ========================================================= */
22457  #define R_ETHERC0_TLFRCR_TLFRCR_Pos     (0UL)          /*!< TLFRCR (Bit 0)                                        */
22458  #define R_ETHERC0_TLFRCR_TLFRCR_Msk     (0xffffffffUL) /*!< TLFRCR (Bitfield-Mask: 0xffffffff)                    */
22459 /* =========================================================  RFCR  ========================================================== */
22460  #define R_ETHERC0_RFCR_RFCR_Pos         (0UL)          /*!< RFCR (Bit 0)                                          */
22461  #define R_ETHERC0_RFCR_RFCR_Msk         (0xffffffffUL) /*!< RFCR (Bitfield-Mask: 0xffffffff)                      */
22462 /* =========================================================  MAFCR  ========================================================= */
22463  #define R_ETHERC0_MAFCR_MAFCR_Pos       (0UL)          /*!< MAFCR (Bit 0)                                         */
22464  #define R_ETHERC0_MAFCR_MAFCR_Msk       (0xffffffffUL) /*!< MAFCR (Bitfield-Mask: 0xffffffff)                     */
22465 
22466 /* =========================================================================================================================== */
22467 /* ================                                      R_ETHERC_EDMAC                                       ================ */
22468 /* =========================================================================================================================== */
22469 
22470 /* =========================================================  EDMR  ========================================================== */
22471  #define R_ETHERC_EDMAC_EDMR_DE_Pos           (6UL)          /*!< DE (Bit 6)                                            */
22472  #define R_ETHERC_EDMAC_EDMR_DE_Msk           (0x40UL)       /*!< DE (Bitfield-Mask: 0x01)                              */
22473  #define R_ETHERC_EDMAC_EDMR_DL_Pos           (4UL)          /*!< DL (Bit 4)                                            */
22474  #define R_ETHERC_EDMAC_EDMR_DL_Msk           (0x30UL)       /*!< DL (Bitfield-Mask: 0x03)                              */
22475  #define R_ETHERC_EDMAC_EDMR_SWR_Pos          (0UL)          /*!< SWR (Bit 0)                                           */
22476  #define R_ETHERC_EDMAC_EDMR_SWR_Msk          (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
22477 /* =========================================================  EDTRR  ========================================================= */
22478  #define R_ETHERC_EDMAC_EDTRR_TR_Pos          (0UL)          /*!< TR (Bit 0)                                            */
22479  #define R_ETHERC_EDMAC_EDTRR_TR_Msk          (0x1UL)        /*!< TR (Bitfield-Mask: 0x01)                              */
22480 /* =========================================================  EDRRR  ========================================================= */
22481  #define R_ETHERC_EDMAC_EDRRR_RR_Pos          (0UL)          /*!< RR (Bit 0)                                            */
22482  #define R_ETHERC_EDMAC_EDRRR_RR_Msk          (0x1UL)        /*!< RR (Bitfield-Mask: 0x01)                              */
22483 /* =========================================================  TDLAR  ========================================================= */
22484  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Pos       (0UL)          /*!< TDLAR (Bit 0)                                         */
22485  #define R_ETHERC_EDMAC_TDLAR_TDLAR_Msk       (0xffffffffUL) /*!< TDLAR (Bitfield-Mask: 0xffffffff)                     */
22486 /* =========================================================  RDLAR  ========================================================= */
22487  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Pos       (0UL)          /*!< RDLAR (Bit 0)                                         */
22488  #define R_ETHERC_EDMAC_RDLAR_RDLAR_Msk       (0xffffffffUL) /*!< RDLAR (Bitfield-Mask: 0xffffffff)                     */
22489 /* =========================================================  EESR  ========================================================== */
22490  #define R_ETHERC_EDMAC_EESR_TWB_Pos          (30UL)         /*!< TWB (Bit 30)                                          */
22491  #define R_ETHERC_EDMAC_EESR_TWB_Msk          (0x40000000UL) /*!< TWB (Bitfield-Mask: 0x01)                             */
22492  #define R_ETHERC_EDMAC_EESR_TABT_Pos         (26UL)         /*!< TABT (Bit 26)                                         */
22493  #define R_ETHERC_EDMAC_EESR_TABT_Msk         (0x4000000UL)  /*!< TABT (Bitfield-Mask: 0x01)                            */
22494  #define R_ETHERC_EDMAC_EESR_RABT_Pos         (25UL)         /*!< RABT (Bit 25)                                         */
22495  #define R_ETHERC_EDMAC_EESR_RABT_Msk         (0x2000000UL)  /*!< RABT (Bitfield-Mask: 0x01)                            */
22496  #define R_ETHERC_EDMAC_EESR_RFCOF_Pos        (24UL)         /*!< RFCOF (Bit 24)                                        */
22497  #define R_ETHERC_EDMAC_EESR_RFCOF_Msk        (0x1000000UL)  /*!< RFCOF (Bitfield-Mask: 0x01)                           */
22498  #define R_ETHERC_EDMAC_EESR_ADE_Pos          (23UL)         /*!< ADE (Bit 23)                                          */
22499  #define R_ETHERC_EDMAC_EESR_ADE_Msk          (0x800000UL)   /*!< ADE (Bitfield-Mask: 0x01)                             */
22500  #define R_ETHERC_EDMAC_EESR_ECI_Pos          (22UL)         /*!< ECI (Bit 22)                                          */
22501  #define R_ETHERC_EDMAC_EESR_ECI_Msk          (0x400000UL)   /*!< ECI (Bitfield-Mask: 0x01)                             */
22502  #define R_ETHERC_EDMAC_EESR_TC_Pos           (21UL)         /*!< TC (Bit 21)                                           */
22503  #define R_ETHERC_EDMAC_EESR_TC_Msk           (0x200000UL)   /*!< TC (Bitfield-Mask: 0x01)                              */
22504  #define R_ETHERC_EDMAC_EESR_TDE_Pos          (20UL)         /*!< TDE (Bit 20)                                          */
22505  #define R_ETHERC_EDMAC_EESR_TDE_Msk          (0x100000UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
22506  #define R_ETHERC_EDMAC_EESR_TFUF_Pos         (19UL)         /*!< TFUF (Bit 19)                                         */
22507  #define R_ETHERC_EDMAC_EESR_TFUF_Msk         (0x80000UL)    /*!< TFUF (Bitfield-Mask: 0x01)                            */
22508  #define R_ETHERC_EDMAC_EESR_FR_Pos           (18UL)         /*!< FR (Bit 18)                                           */
22509  #define R_ETHERC_EDMAC_EESR_FR_Msk           (0x40000UL)    /*!< FR (Bitfield-Mask: 0x01)                              */
22510  #define R_ETHERC_EDMAC_EESR_RDE_Pos          (17UL)         /*!< RDE (Bit 17)                                          */
22511  #define R_ETHERC_EDMAC_EESR_RDE_Msk          (0x20000UL)    /*!< RDE (Bitfield-Mask: 0x01)                             */
22512  #define R_ETHERC_EDMAC_EESR_RFOF_Pos         (16UL)         /*!< RFOF (Bit 16)                                         */
22513  #define R_ETHERC_EDMAC_EESR_RFOF_Msk         (0x10000UL)    /*!< RFOF (Bitfield-Mask: 0x01)                            */
22514  #define R_ETHERC_EDMAC_EESR_CND_Pos          (11UL)         /*!< CND (Bit 11)                                          */
22515  #define R_ETHERC_EDMAC_EESR_CND_Msk          (0x800UL)      /*!< CND (Bitfield-Mask: 0x01)                             */
22516  #define R_ETHERC_EDMAC_EESR_DLC_Pos          (10UL)         /*!< DLC (Bit 10)                                          */
22517  #define R_ETHERC_EDMAC_EESR_DLC_Msk          (0x400UL)      /*!< DLC (Bitfield-Mask: 0x01)                             */
22518  #define R_ETHERC_EDMAC_EESR_CD_Pos           (9UL)          /*!< CD (Bit 9)                                            */
22519  #define R_ETHERC_EDMAC_EESR_CD_Msk           (0x200UL)      /*!< CD (Bitfield-Mask: 0x01)                              */
22520  #define R_ETHERC_EDMAC_EESR_TRO_Pos          (8UL)          /*!< TRO (Bit 8)                                           */
22521  #define R_ETHERC_EDMAC_EESR_TRO_Msk          (0x100UL)      /*!< TRO (Bitfield-Mask: 0x01)                             */
22522  #define R_ETHERC_EDMAC_EESR_RMAF_Pos         (7UL)          /*!< RMAF (Bit 7)                                          */
22523  #define R_ETHERC_EDMAC_EESR_RMAF_Msk         (0x80UL)       /*!< RMAF (Bitfield-Mask: 0x01)                            */
22524  #define R_ETHERC_EDMAC_EESR_RRF_Pos          (4UL)          /*!< RRF (Bit 4)                                           */
22525  #define R_ETHERC_EDMAC_EESR_RRF_Msk          (0x10UL)       /*!< RRF (Bitfield-Mask: 0x01)                             */
22526  #define R_ETHERC_EDMAC_EESR_RTLF_Pos         (3UL)          /*!< RTLF (Bit 3)                                          */
22527  #define R_ETHERC_EDMAC_EESR_RTLF_Msk         (0x8UL)        /*!< RTLF (Bitfield-Mask: 0x01)                            */
22528  #define R_ETHERC_EDMAC_EESR_RTSF_Pos         (2UL)          /*!< RTSF (Bit 2)                                          */
22529  #define R_ETHERC_EDMAC_EESR_RTSF_Msk         (0x4UL)        /*!< RTSF (Bitfield-Mask: 0x01)                            */
22530  #define R_ETHERC_EDMAC_EESR_PRE_Pos          (1UL)          /*!< PRE (Bit 1)                                           */
22531  #define R_ETHERC_EDMAC_EESR_PRE_Msk          (0x2UL)        /*!< PRE (Bitfield-Mask: 0x01)                             */
22532  #define R_ETHERC_EDMAC_EESR_CERF_Pos         (0UL)          /*!< CERF (Bit 0)                                          */
22533  #define R_ETHERC_EDMAC_EESR_CERF_Msk         (0x1UL)        /*!< CERF (Bitfield-Mask: 0x01)                            */
22534 /* ========================================================  EESIPR  ========================================================= */
22535  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Pos      (30UL)         /*!< TWBIP (Bit 30)                                        */
22536  #define R_ETHERC_EDMAC_EESIPR_TWBIP_Msk      (0x40000000UL) /*!< TWBIP (Bitfield-Mask: 0x01)                           */
22537  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Pos     (26UL)         /*!< TABTIP (Bit 26)                                       */
22538  #define R_ETHERC_EDMAC_EESIPR_TABTIP_Msk     (0x4000000UL)  /*!< TABTIP (Bitfield-Mask: 0x01)                          */
22539  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Pos     (25UL)         /*!< RABTIP (Bit 25)                                       */
22540  #define R_ETHERC_EDMAC_EESIPR_RABTIP_Msk     (0x2000000UL)  /*!< RABTIP (Bitfield-Mask: 0x01)                          */
22541  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Pos    (24UL)         /*!< RFCOFIP (Bit 24)                                      */
22542  #define R_ETHERC_EDMAC_EESIPR_RFCOFIP_Msk    (0x1000000UL)  /*!< RFCOFIP (Bitfield-Mask: 0x01)                         */
22543  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Pos      (23UL)         /*!< ADEIP (Bit 23)                                        */
22544  #define R_ETHERC_EDMAC_EESIPR_ADEIP_Msk      (0x800000UL)   /*!< ADEIP (Bitfield-Mask: 0x01)                           */
22545  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Pos      (22UL)         /*!< ECIIP (Bit 22)                                        */
22546  #define R_ETHERC_EDMAC_EESIPR_ECIIP_Msk      (0x400000UL)   /*!< ECIIP (Bitfield-Mask: 0x01)                           */
22547  #define R_ETHERC_EDMAC_EESIPR_TCIP_Pos       (21UL)         /*!< TCIP (Bit 21)                                         */
22548  #define R_ETHERC_EDMAC_EESIPR_TCIP_Msk       (0x200000UL)   /*!< TCIP (Bitfield-Mask: 0x01)                            */
22549  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Pos      (20UL)         /*!< TDEIP (Bit 20)                                        */
22550  #define R_ETHERC_EDMAC_EESIPR_TDEIP_Msk      (0x100000UL)   /*!< TDEIP (Bitfield-Mask: 0x01)                           */
22551  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Pos     (19UL)         /*!< TFUFIP (Bit 19)                                       */
22552  #define R_ETHERC_EDMAC_EESIPR_TFUFIP_Msk     (0x80000UL)    /*!< TFUFIP (Bitfield-Mask: 0x01)                          */
22553  #define R_ETHERC_EDMAC_EESIPR_FRIP_Pos       (18UL)         /*!< FRIP (Bit 18)                                         */
22554  #define R_ETHERC_EDMAC_EESIPR_FRIP_Msk       (0x40000UL)    /*!< FRIP (Bitfield-Mask: 0x01)                            */
22555  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Pos      (17UL)         /*!< RDEIP (Bit 17)                                        */
22556  #define R_ETHERC_EDMAC_EESIPR_RDEIP_Msk      (0x20000UL)    /*!< RDEIP (Bitfield-Mask: 0x01)                           */
22557  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Pos     (16UL)         /*!< RFOFIP (Bit 16)                                       */
22558  #define R_ETHERC_EDMAC_EESIPR_RFOFIP_Msk     (0x10000UL)    /*!< RFOFIP (Bitfield-Mask: 0x01)                          */
22559  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Pos      (11UL)         /*!< CNDIP (Bit 11)                                        */
22560  #define R_ETHERC_EDMAC_EESIPR_CNDIP_Msk      (0x800UL)      /*!< CNDIP (Bitfield-Mask: 0x01)                           */
22561  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Pos      (10UL)         /*!< DLCIP (Bit 10)                                        */
22562  #define R_ETHERC_EDMAC_EESIPR_DLCIP_Msk      (0x400UL)      /*!< DLCIP (Bitfield-Mask: 0x01)                           */
22563  #define R_ETHERC_EDMAC_EESIPR_CDIP_Pos       (9UL)          /*!< CDIP (Bit 9)                                          */
22564  #define R_ETHERC_EDMAC_EESIPR_CDIP_Msk       (0x200UL)      /*!< CDIP (Bitfield-Mask: 0x01)                            */
22565  #define R_ETHERC_EDMAC_EESIPR_TROIP_Pos      (8UL)          /*!< TROIP (Bit 8)                                         */
22566  #define R_ETHERC_EDMAC_EESIPR_TROIP_Msk      (0x100UL)      /*!< TROIP (Bitfield-Mask: 0x01)                           */
22567  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Pos     (7UL)          /*!< RMAFIP (Bit 7)                                        */
22568  #define R_ETHERC_EDMAC_EESIPR_RMAFIP_Msk     (0x80UL)       /*!< RMAFIP (Bitfield-Mask: 0x01)                          */
22569  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Pos      (4UL)          /*!< RRFIP (Bit 4)                                         */
22570  #define R_ETHERC_EDMAC_EESIPR_RRFIP_Msk      (0x10UL)       /*!< RRFIP (Bitfield-Mask: 0x01)                           */
22571  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Pos     (3UL)          /*!< RTLFIP (Bit 3)                                        */
22572  #define R_ETHERC_EDMAC_EESIPR_RTLFIP_Msk     (0x8UL)        /*!< RTLFIP (Bitfield-Mask: 0x01)                          */
22573  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Pos     (2UL)          /*!< RTSFIP (Bit 2)                                        */
22574  #define R_ETHERC_EDMAC_EESIPR_RTSFIP_Msk     (0x4UL)        /*!< RTSFIP (Bitfield-Mask: 0x01)                          */
22575  #define R_ETHERC_EDMAC_EESIPR_PREIP_Pos      (1UL)          /*!< PREIP (Bit 1)                                         */
22576  #define R_ETHERC_EDMAC_EESIPR_PREIP_Msk      (0x2UL)        /*!< PREIP (Bitfield-Mask: 0x01)                           */
22577  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Pos     (0UL)          /*!< CERFIP (Bit 0)                                        */
22578  #define R_ETHERC_EDMAC_EESIPR_CERFIP_Msk     (0x1UL)        /*!< CERFIP (Bitfield-Mask: 0x01)                          */
22579 /* ========================================================  TRSCER  ========================================================= */
22580  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Pos     (7UL)          /*!< RMAFCE (Bit 7)                                        */
22581  #define R_ETHERC_EDMAC_TRSCER_RMAFCE_Msk     (0x80UL)       /*!< RMAFCE (Bitfield-Mask: 0x01)                          */
22582  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Pos      (4UL)          /*!< RRFCE (Bit 4)                                         */
22583  #define R_ETHERC_EDMAC_TRSCER_RRFCE_Msk      (0x10UL)       /*!< RRFCE (Bitfield-Mask: 0x01)                           */
22584 /* =========================================================  RMFCR  ========================================================= */
22585  #define R_ETHERC_EDMAC_RMFCR_MFC_Pos         (0UL)          /*!< MFC (Bit 0)                                           */
22586  #define R_ETHERC_EDMAC_RMFCR_MFC_Msk         (0xffffUL)     /*!< MFC (Bitfield-Mask: 0xffff)                           */
22587 /* =========================================================  TFTR  ========================================================== */
22588  #define R_ETHERC_EDMAC_TFTR_TFT_Pos          (0UL)          /*!< TFT (Bit 0)                                           */
22589  #define R_ETHERC_EDMAC_TFTR_TFT_Msk          (0x7ffUL)      /*!< TFT (Bitfield-Mask: 0x7ff)                            */
22590 /* ==========================================================  FDR  ========================================================== */
22591  #define R_ETHERC_EDMAC_FDR_TFD_Pos           (8UL)          /*!< TFD (Bit 8)                                           */
22592  #define R_ETHERC_EDMAC_FDR_TFD_Msk           (0x1f00UL)     /*!< TFD (Bitfield-Mask: 0x1f)                             */
22593  #define R_ETHERC_EDMAC_FDR_RFD_Pos           (0UL)          /*!< RFD (Bit 0)                                           */
22594  #define R_ETHERC_EDMAC_FDR_RFD_Msk           (0x1fUL)       /*!< RFD (Bitfield-Mask: 0x1f)                             */
22595 /* =========================================================  RMCR  ========================================================== */
22596  #define R_ETHERC_EDMAC_RMCR_RNR_Pos          (0UL)          /*!< RNR (Bit 0)                                           */
22597  #define R_ETHERC_EDMAC_RMCR_RNR_Msk          (0x1UL)        /*!< RNR (Bitfield-Mask: 0x01)                             */
22598 /* =========================================================  TFUCR  ========================================================= */
22599  #define R_ETHERC_EDMAC_TFUCR_UNDER_Pos       (0UL)          /*!< UNDER (Bit 0)                                         */
22600  #define R_ETHERC_EDMAC_TFUCR_UNDER_Msk       (0xffffUL)     /*!< UNDER (Bitfield-Mask: 0xffff)                         */
22601 /* =========================================================  RFOCR  ========================================================= */
22602  #define R_ETHERC_EDMAC_RFOCR_OVER_Pos        (0UL)          /*!< OVER (Bit 0)                                          */
22603  #define R_ETHERC_EDMAC_RFOCR_OVER_Msk        (0xffffUL)     /*!< OVER (Bitfield-Mask: 0xffff)                          */
22604 /* =========================================================  IOSR  ========================================================== */
22605  #define R_ETHERC_EDMAC_IOSR_ELB_Pos          (0UL)          /*!< ELB (Bit 0)                                           */
22606  #define R_ETHERC_EDMAC_IOSR_ELB_Msk          (0x1UL)        /*!< ELB (Bitfield-Mask: 0x01)                             */
22607 /* =========================================================  FCFTR  ========================================================= */
22608  #define R_ETHERC_EDMAC_FCFTR_RFFO_Pos        (16UL)         /*!< RFFO (Bit 16)                                         */
22609  #define R_ETHERC_EDMAC_FCFTR_RFFO_Msk        (0x70000UL)    /*!< RFFO (Bitfield-Mask: 0x07)                            */
22610  #define R_ETHERC_EDMAC_FCFTR_RFDO_Pos        (0UL)          /*!< RFDO (Bit 0)                                          */
22611  #define R_ETHERC_EDMAC_FCFTR_RFDO_Msk        (0x7UL)        /*!< RFDO (Bitfield-Mask: 0x07)                            */
22612 /* ========================================================  RPADIR  ========================================================= */
22613  #define R_ETHERC_EDMAC_RPADIR_PADS_Pos       (16UL)         /*!< PADS (Bit 16)                                         */
22614  #define R_ETHERC_EDMAC_RPADIR_PADS_Msk       (0x30000UL)    /*!< PADS (Bitfield-Mask: 0x03)                            */
22615  #define R_ETHERC_EDMAC_RPADIR_PADR_Pos       (0UL)          /*!< PADR (Bit 0)                                          */
22616  #define R_ETHERC_EDMAC_RPADIR_PADR_Msk       (0x3fUL)       /*!< PADR (Bitfield-Mask: 0x3f)                            */
22617 /* =========================================================  TRIMD  ========================================================= */
22618  #define R_ETHERC_EDMAC_TRIMD_TIM_Pos         (4UL)          /*!< TIM (Bit 4)                                           */
22619  #define R_ETHERC_EDMAC_TRIMD_TIM_Msk         (0x10UL)       /*!< TIM (Bitfield-Mask: 0x01)                             */
22620  #define R_ETHERC_EDMAC_TRIMD_TIS_Pos         (0UL)          /*!< TIS (Bit 0)                                           */
22621  #define R_ETHERC_EDMAC_TRIMD_TIS_Msk         (0x1UL)        /*!< TIS (Bitfield-Mask: 0x01)                             */
22622 /* =========================================================  RBWAR  ========================================================= */
22623  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Pos       (0UL)          /*!< RBWAR (Bit 0)                                         */
22624  #define R_ETHERC_EDMAC_RBWAR_RBWAR_Msk       (0xffffffffUL) /*!< RBWAR (Bitfield-Mask: 0xffffffff)                     */
22625 /* =========================================================  RDFAR  ========================================================= */
22626  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Pos       (0UL)          /*!< RDFAR (Bit 0)                                         */
22627  #define R_ETHERC_EDMAC_RDFAR_RDFAR_Msk       (0xffffffffUL) /*!< RDFAR (Bitfield-Mask: 0xffffffff)                     */
22628 /* =========================================================  TBRAR  ========================================================= */
22629  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Pos       (0UL)          /*!< TBRAR (Bit 0)                                         */
22630  #define R_ETHERC_EDMAC_TBRAR_TBRAR_Msk       (0xffffffffUL) /*!< TBRAR (Bitfield-Mask: 0xffffffff)                     */
22631 /* =========================================================  TDFAR  ========================================================= */
22632  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Pos       (0UL)          /*!< TDFAR (Bit 0)                                         */
22633  #define R_ETHERC_EDMAC_TDFAR_TDFAR_Msk       (0xffffffffUL) /*!< TDFAR (Bitfield-Mask: 0xffffffff)                     */
22634 
22635 /* =========================================================================================================================== */
22636 /* ================                                       R_FACI_HP_CMD                                       ================ */
22637 /* =========================================================================================================================== */
22638 
22639 /* ======================================================  FACI_CMD16  ======================================================= */
22640 /* =======================================================  FACI_CMD8  ======================================================= */
22641 
22642 /* =========================================================================================================================== */
22643 /* ================                                         R_FACI_HP                                         ================ */
22644 /* =========================================================================================================================== */
22645 
22646 /* ========================================================  FASTAT  ========================================================= */
22647  #define R_FACI_HP_FASTAT_CFAE_Pos         (7UL)          /*!< CFAE (Bit 7)                                          */
22648  #define R_FACI_HP_FASTAT_CFAE_Msk         (0x80UL)       /*!< CFAE (Bitfield-Mask: 0x01)                            */
22649  #define R_FACI_HP_FASTAT_CMDLK_Pos        (4UL)          /*!< CMDLK (Bit 4)                                         */
22650  #define R_FACI_HP_FASTAT_CMDLK_Msk        (0x10UL)       /*!< CMDLK (Bitfield-Mask: 0x01)                           */
22651  #define R_FACI_HP_FASTAT_DFAE_Pos         (3UL)          /*!< DFAE (Bit 3)                                          */
22652  #define R_FACI_HP_FASTAT_DFAE_Msk         (0x8UL)        /*!< DFAE (Bitfield-Mask: 0x01)                            */
22653 /* ========================================================  FAEINT  ========================================================= */
22654  #define R_FACI_HP_FAEINT_CFAEIE_Pos       (7UL)          /*!< CFAEIE (Bit 7)                                        */
22655  #define R_FACI_HP_FAEINT_CFAEIE_Msk       (0x80UL)       /*!< CFAEIE (Bitfield-Mask: 0x01)                          */
22656  #define R_FACI_HP_FAEINT_CMDLKIE_Pos      (4UL)          /*!< CMDLKIE (Bit 4)                                       */
22657  #define R_FACI_HP_FAEINT_CMDLKIE_Msk      (0x10UL)       /*!< CMDLKIE (Bitfield-Mask: 0x01)                         */
22658  #define R_FACI_HP_FAEINT_DFAEIE_Pos       (3UL)          /*!< DFAEIE (Bit 3)                                        */
22659  #define R_FACI_HP_FAEINT_DFAEIE_Msk       (0x8UL)        /*!< DFAEIE (Bitfield-Mask: 0x01)                          */
22660 /* ========================================================  FRDYIE  ========================================================= */
22661  #define R_FACI_HP_FRDYIE_FRDYIE_Pos       (0UL)          /*!< FRDYIE (Bit 0)                                        */
22662  #define R_FACI_HP_FRDYIE_FRDYIE_Msk       (0x1UL)        /*!< FRDYIE (Bitfield-Mask: 0x01)                          */
22663 /* ========================================================  FSADDR  ========================================================= */
22664  #define R_FACI_HP_FSADDR_FSA_Pos          (0UL)          /*!< FSA (Bit 0)                                           */
22665  #define R_FACI_HP_FSADDR_FSA_Msk          (0xffffffffUL) /*!< FSA (Bitfield-Mask: 0xffffffff)                       */
22666 /* ========================================================  FEADDR  ========================================================= */
22667  #define R_FACI_HP_FEADDR_FEA_Pos          (0UL)          /*!< FEA (Bit 0)                                           */
22668  #define R_FACI_HP_FEADDR_FEA_Msk          (0xffffffffUL) /*!< FEA (Bitfield-Mask: 0xffffffff)                       */
22669 /* ========================================================  FMEPROT  ======================================================== */
22670  #define R_FACI_HP_FMEPROT_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
22671  #define R_FACI_HP_FMEPROT_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22672  #define R_FACI_HP_FMEPROT_CEPROT_Pos      (0UL)          /*!< CEPROT (Bit 0)                                        */
22673  #define R_FACI_HP_FMEPROT_CEPROT_Msk      (0x1UL)        /*!< CEPROT (Bitfield-Mask: 0x01)                          */
22674 /* ========================================================  FBPROT0  ======================================================== */
22675  #define R_FACI_HP_FBPROT0_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
22676  #define R_FACI_HP_FBPROT0_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22677  #define R_FACI_HP_FBPROT0_BPCN0_Pos       (0UL)          /*!< BPCN0 (Bit 0)                                         */
22678  #define R_FACI_HP_FBPROT0_BPCN0_Msk       (0x1UL)        /*!< BPCN0 (Bitfield-Mask: 0x01)                           */
22679 /* ========================================================  FBPROT1  ======================================================== */
22680  #define R_FACI_HP_FBPROT1_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
22681  #define R_FACI_HP_FBPROT1_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22682  #define R_FACI_HP_FBPROT1_BPCN1_Pos       (0UL)          /*!< BPCN1 (Bit 0)                                         */
22683  #define R_FACI_HP_FBPROT1_BPCN1_Msk       (0x1UL)        /*!< BPCN1 (Bitfield-Mask: 0x01)                           */
22684 /* ========================================================  FSTATR  ========================================================= */
22685  #define R_FACI_HP_FSTATR_ILGCOMERR_Pos    (23UL)         /*!< ILGCOMERR (Bit 23)                                    */
22686  #define R_FACI_HP_FSTATR_ILGCOMERR_Msk    (0x800000UL)   /*!< ILGCOMERR (Bitfield-Mask: 0x01)                       */
22687  #define R_FACI_HP_FSTATR_FESETERR_Pos     (22UL)         /*!< FESETERR (Bit 22)                                     */
22688  #define R_FACI_HP_FSTATR_FESETERR_Msk     (0x400000UL)   /*!< FESETERR (Bitfield-Mask: 0x01)                        */
22689  #define R_FACI_HP_FSTATR_SECERR_Pos       (21UL)         /*!< SECERR (Bit 21)                                       */
22690  #define R_FACI_HP_FSTATR_SECERR_Msk       (0x200000UL)   /*!< SECERR (Bitfield-Mask: 0x01)                          */
22691  #define R_FACI_HP_FSTATR_OTERR_Pos        (20UL)         /*!< OTERR (Bit 20)                                        */
22692  #define R_FACI_HP_FSTATR_OTERR_Msk        (0x100000UL)   /*!< OTERR (Bitfield-Mask: 0x01)                           */
22693  #define R_FACI_HP_FSTATR_FRDY_Pos         (15UL)         /*!< FRDY (Bit 15)                                         */
22694  #define R_FACI_HP_FSTATR_FRDY_Msk         (0x8000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
22695  #define R_FACI_HP_FSTATR_ILGLERR_Pos      (14UL)         /*!< ILGLERR (Bit 14)                                      */
22696  #define R_FACI_HP_FSTATR_ILGLERR_Msk      (0x4000UL)     /*!< ILGLERR (Bitfield-Mask: 0x01)                         */
22697  #define R_FACI_HP_FSTATR_ERSERR_Pos       (13UL)         /*!< ERSERR (Bit 13)                                       */
22698  #define R_FACI_HP_FSTATR_ERSERR_Msk       (0x2000UL)     /*!< ERSERR (Bitfield-Mask: 0x01)                          */
22699  #define R_FACI_HP_FSTATR_PRGERR_Pos       (12UL)         /*!< PRGERR (Bit 12)                                       */
22700  #define R_FACI_HP_FSTATR_PRGERR_Msk       (0x1000UL)     /*!< PRGERR (Bitfield-Mask: 0x01)                          */
22701  #define R_FACI_HP_FSTATR_SUSRDY_Pos       (11UL)         /*!< SUSRDY (Bit 11)                                       */
22702  #define R_FACI_HP_FSTATR_SUSRDY_Msk       (0x800UL)      /*!< SUSRDY (Bitfield-Mask: 0x01)                          */
22703  #define R_FACI_HP_FSTATR_DBFULL_Pos       (10UL)         /*!< DBFULL (Bit 10)                                       */
22704  #define R_FACI_HP_FSTATR_DBFULL_Msk       (0x400UL)      /*!< DBFULL (Bitfield-Mask: 0x01)                          */
22705  #define R_FACI_HP_FSTATR_ERSSPD_Pos       (9UL)          /*!< ERSSPD (Bit 9)                                        */
22706  #define R_FACI_HP_FSTATR_ERSSPD_Msk       (0x200UL)      /*!< ERSSPD (Bitfield-Mask: 0x01)                          */
22707  #define R_FACI_HP_FSTATR_PRGSPD_Pos       (8UL)          /*!< PRGSPD (Bit 8)                                        */
22708  #define R_FACI_HP_FSTATR_PRGSPD_Msk       (0x100UL)      /*!< PRGSPD (Bitfield-Mask: 0x01)                          */
22709  #define R_FACI_HP_FSTATR_FLWEERR_Pos      (6UL)          /*!< FLWEERR (Bit 6)                                       */
22710  #define R_FACI_HP_FSTATR_FLWEERR_Msk      (0x40UL)       /*!< FLWEERR (Bitfield-Mask: 0x01)                         */
22711 /* ========================================================  FENTRYR  ======================================================== */
22712  #define R_FACI_HP_FENTRYR_KEY_Pos         (8UL)          /*!< KEY (Bit 8)                                           */
22713  #define R_FACI_HP_FENTRYR_KEY_Msk         (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22714  #define R_FACI_HP_FENTRYR_FENTRYD_Pos     (7UL)          /*!< FENTRYD (Bit 7)                                       */
22715  #define R_FACI_HP_FENTRYR_FENTRYD_Msk     (0x80UL)       /*!< FENTRYD (Bitfield-Mask: 0x01)                         */
22716  #define R_FACI_HP_FENTRYR_FENTRYC_Pos     (0UL)          /*!< FENTRYC (Bit 0)                                       */
22717  #define R_FACI_HP_FENTRYR_FENTRYC_Msk     (0x1UL)        /*!< FENTRYC (Bitfield-Mask: 0x01)                         */
22718 /* =======================================================  FSUINITR  ======================================================== */
22719  #define R_FACI_HP_FSUINITR_KEY_Pos        (8UL)          /*!< KEY (Bit 8)                                           */
22720  #define R_FACI_HP_FSUINITR_KEY_Msk        (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22721  #define R_FACI_HP_FSUINITR_SUINIT_Pos     (0UL)          /*!< SUINIT (Bit 0)                                        */
22722  #define R_FACI_HP_FSUINITR_SUINIT_Msk     (0x1UL)        /*!< SUINIT (Bitfield-Mask: 0x01)                          */
22723 /* =========================================================  FCMDR  ========================================================= */
22724  #define R_FACI_HP_FCMDR_CMDR_Pos          (8UL)          /*!< CMDR (Bit 8)                                          */
22725  #define R_FACI_HP_FCMDR_CMDR_Msk          (0xff00UL)     /*!< CMDR (Bitfield-Mask: 0xff)                            */
22726  #define R_FACI_HP_FCMDR_PCMDR_Pos         (0UL)          /*!< PCMDR (Bit 0)                                         */
22727  #define R_FACI_HP_FCMDR_PCMDR_Msk         (0xffUL)       /*!< PCMDR (Bitfield-Mask: 0xff)                           */
22728 /* ========================================================  FBCCNT  ========================================================= */
22729  #define R_FACI_HP_FBCCNT_BCDIR_Pos        (0UL)          /*!< BCDIR (Bit 0)                                         */
22730  #define R_FACI_HP_FBCCNT_BCDIR_Msk        (0x1UL)        /*!< BCDIR (Bitfield-Mask: 0x01)                           */
22731 /* ========================================================  FBCSTAT  ======================================================== */
22732  #define R_FACI_HP_FBCSTAT_BCST_Pos        (0UL)          /*!< BCST (Bit 0)                                          */
22733  #define R_FACI_HP_FBCSTAT_BCST_Msk        (0x1UL)        /*!< BCST (Bitfield-Mask: 0x01)                            */
22734 /* ========================================================  FPSADDR  ======================================================== */
22735  #define R_FACI_HP_FPSADDR_PSADR_Pos       (0UL)          /*!< PSADR (Bit 0)                                         */
22736  #define R_FACI_HP_FPSADDR_PSADR_Msk       (0x7ffffUL)    /*!< PSADR (Bitfield-Mask: 0x7ffff)                        */
22737 /* ========================================================  FAWMON  ========================================================= */
22738  #define R_FACI_HP_FAWMON_BTFLG_Pos        (31UL)         /*!< BTFLG (Bit 31)                                        */
22739  #define R_FACI_HP_FAWMON_BTFLG_Msk        (0x80000000UL) /*!< BTFLG (Bitfield-Mask: 0x01)                           */
22740  #define R_FACI_HP_FAWMON_FAWE_Pos         (16UL)         /*!< FAWE (Bit 16)                                         */
22741  #define R_FACI_HP_FAWMON_FAWE_Msk         (0x7ff0000UL)  /*!< FAWE (Bitfield-Mask: 0x7ff)                           */
22742  #define R_FACI_HP_FAWMON_FSPR_Pos         (15UL)         /*!< FSPR (Bit 15)                                         */
22743  #define R_FACI_HP_FAWMON_FSPR_Msk         (0x8000UL)     /*!< FSPR (Bitfield-Mask: 0x01)                            */
22744  #define R_FACI_HP_FAWMON_FAWS_Pos         (0UL)          /*!< FAWS (Bit 0)                                          */
22745  #define R_FACI_HP_FAWMON_FAWS_Msk         (0x7ffUL)      /*!< FAWS (Bitfield-Mask: 0x7ff)                           */
22746 /* =========================================================  FCPSR  ========================================================= */
22747  #define R_FACI_HP_FCPSR_ESUSPMD_Pos       (0UL)          /*!< ESUSPMD (Bit 0)                                       */
22748  #define R_FACI_HP_FCPSR_ESUSPMD_Msk       (0x1UL)        /*!< ESUSPMD (Bitfield-Mask: 0x01)                         */
22749 /* ========================================================  FPCKAR  ========================================================= */
22750  #define R_FACI_HP_FPCKAR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
22751  #define R_FACI_HP_FPCKAR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22752  #define R_FACI_HP_FPCKAR_PCKA_Pos         (0UL)          /*!< PCKA (Bit 0)                                          */
22753  #define R_FACI_HP_FPCKAR_PCKA_Msk         (0xffUL)       /*!< PCKA (Bitfield-Mask: 0xff)                            */
22754 /* ========================================================  FSUACR  ========================================================= */
22755  #define R_FACI_HP_FSUACR_KEY_Pos          (8UL)          /*!< KEY (Bit 8)                                           */
22756  #define R_FACI_HP_FSUACR_KEY_Msk          (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
22757  #define R_FACI_HP_FSUACR_SAS_Pos          (0UL)          /*!< SAS (Bit 0)                                           */
22758  #define R_FACI_HP_FSUACR_SAS_Msk          (0x3UL)        /*!< SAS (Bitfield-Mask: 0x03)                             */
22759 
22760 /* =========================================================================================================================== */
22761 /* ================                                         R_FCACHE                                          ================ */
22762 /* =========================================================================================================================== */
22763 
22764 /* ========================================================  FCACHEE  ======================================================== */
22765  #define R_FCACHE_FCACHEE_FCACHEEN_Pos     (0UL)     /*!< FCACHEEN (Bit 0)                                      */
22766  #define R_FCACHE_FCACHEE_FCACHEEN_Msk     (0x1UL)   /*!< FCACHEEN (Bitfield-Mask: 0x01)                        */
22767 /* =======================================================  FCACHEIV  ======================================================== */
22768  #define R_FCACHE_FCACHEIV_FCACHEIV_Pos    (0UL)     /*!< FCACHEIV (Bit 0)                                      */
22769  #define R_FCACHE_FCACHEIV_FCACHEIV_Msk    (0x1UL)   /*!< FCACHEIV (Bitfield-Mask: 0x01)                        */
22770 /* =========================================================  FLWT  ========================================================== */
22771  #define R_FCACHE_FLWT_FLWT_Pos            (0UL)     /*!< FLWT (Bit 0)                                          */
22772  #define R_FCACHE_FLWT_FLWT_Msk            (0x7UL)   /*!< FLWT (Bitfield-Mask: 0x07)                            */
22773 /* =========================================================  FSAR  ========================================================== */
22774  #define R_FCACHE_FSAR_FLWTSA_Pos          (0UL)     /*!< FLWTSA (Bit 0)                                        */
22775  #define R_FCACHE_FSAR_FLWTSA_Msk          (0x1UL)   /*!< FLWTSA (Bitfield-Mask: 0x01)                          */
22776  #define R_FCACHE_FSAR_FCKMHZSA_Pos        (8UL)     /*!< FCKMHZSA (Bit 8)                                      */
22777  #define R_FCACHE_FSAR_FCKMHZSA_Msk        (0x100UL) /*!< FCKMHZSA (Bitfield-Mask: 0x01)                        */
22778 
22779 /* =========================================================================================================================== */
22780 /* ================                                          R_GPT0                                           ================ */
22781 /* =========================================================================================================================== */
22782 
22783 /* =========================================================  GTWP  ========================================================== */
22784  #define R_GPT0_GTWP_PRKEY_Pos             (8UL)          /*!< PRKEY (Bit 8)                                         */
22785  #define R_GPT0_GTWP_PRKEY_Msk             (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
22786  #define R_GPT0_GTWP_WP_Pos                (0UL)          /*!< WP (Bit 0)                                            */
22787  #define R_GPT0_GTWP_WP_Msk                (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
22788  #define R_GPT0_GTWP_STRWP_Pos             (1UL)          /*!< STRWP (Bit 1)                                         */
22789  #define R_GPT0_GTWP_STRWP_Msk             (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
22790  #define R_GPT0_GTWP_STPWP_Pos             (2UL)          /*!< STPWP (Bit 2)                                         */
22791  #define R_GPT0_GTWP_STPWP_Msk             (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
22792  #define R_GPT0_GTWP_CLRWP_Pos             (3UL)          /*!< CLRWP (Bit 3)                                         */
22793  #define R_GPT0_GTWP_CLRWP_Msk             (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
22794  #define R_GPT0_GTWP_CMNWP_Pos             (4UL)          /*!< CMNWP (Bit 4)                                         */
22795  #define R_GPT0_GTWP_CMNWP_Msk             (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
22796 /* =========================================================  GTSTR  ========================================================= */
22797  #define R_GPT0_GTSTR_CSTRT_Pos            (0UL)          /*!< CSTRT (Bit 0)                                         */
22798  #define R_GPT0_GTSTR_CSTRT_Msk            (0x1UL)        /*!< CSTRT (Bitfield-Mask: 0x01)                           */
22799 /* =========================================================  GTSTP  ========================================================= */
22800  #define R_GPT0_GTSTP_CSTOP_Pos            (0UL)          /*!< CSTOP (Bit 0)                                         */
22801  #define R_GPT0_GTSTP_CSTOP_Msk            (0x1UL)        /*!< CSTOP (Bitfield-Mask: 0x01)                           */
22802 /* =========================================================  GTCLR  ========================================================= */
22803  #define R_GPT0_GTCLR_CCLR_Pos             (0UL)          /*!< CCLR (Bit 0)                                          */
22804  #define R_GPT0_GTCLR_CCLR_Msk             (0x1UL)        /*!< CCLR (Bitfield-Mask: 0x01)                            */
22805 /* =========================================================  GTSSR  ========================================================= */
22806  #define R_GPT0_GTSSR_CSTRT_Pos            (31UL)         /*!< CSTRT (Bit 31)                                        */
22807  #define R_GPT0_GTSSR_CSTRT_Msk            (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
22808  #define R_GPT0_GTSSR_SSELC_Pos            (16UL)         /*!< SSELC (Bit 16)                                        */
22809  #define R_GPT0_GTSSR_SSELC_Msk            (0x10000UL)    /*!< SSELC (Bitfield-Mask: 0x01)                           */
22810  #define R_GPT0_GTSSR_SSCBFAH_Pos          (15UL)         /*!< SSCBFAH (Bit 15)                                      */
22811  #define R_GPT0_GTSSR_SSCBFAH_Msk          (0x8000UL)     /*!< SSCBFAH (Bitfield-Mask: 0x01)                         */
22812  #define R_GPT0_GTSSR_SSCBFAL_Pos          (14UL)         /*!< SSCBFAL (Bit 14)                                      */
22813  #define R_GPT0_GTSSR_SSCBFAL_Msk          (0x4000UL)     /*!< SSCBFAL (Bitfield-Mask: 0x01)                         */
22814  #define R_GPT0_GTSSR_SSCBRAH_Pos          (13UL)         /*!< SSCBRAH (Bit 13)                                      */
22815  #define R_GPT0_GTSSR_SSCBRAH_Msk          (0x2000UL)     /*!< SSCBRAH (Bitfield-Mask: 0x01)                         */
22816  #define R_GPT0_GTSSR_SSCBRAL_Pos          (12UL)         /*!< SSCBRAL (Bit 12)                                      */
22817  #define R_GPT0_GTSSR_SSCBRAL_Msk          (0x1000UL)     /*!< SSCBRAL (Bitfield-Mask: 0x01)                         */
22818  #define R_GPT0_GTSSR_SSCAFBH_Pos          (11UL)         /*!< SSCAFBH (Bit 11)                                      */
22819  #define R_GPT0_GTSSR_SSCAFBH_Msk          (0x800UL)      /*!< SSCAFBH (Bitfield-Mask: 0x01)                         */
22820  #define R_GPT0_GTSSR_SSCAFBL_Pos          (10UL)         /*!< SSCAFBL (Bit 10)                                      */
22821  #define R_GPT0_GTSSR_SSCAFBL_Msk          (0x400UL)      /*!< SSCAFBL (Bitfield-Mask: 0x01)                         */
22822  #define R_GPT0_GTSSR_SSCARBH_Pos          (9UL)          /*!< SSCARBH (Bit 9)                                       */
22823  #define R_GPT0_GTSSR_SSCARBH_Msk          (0x200UL)      /*!< SSCARBH (Bitfield-Mask: 0x01)                         */
22824  #define R_GPT0_GTSSR_SSCARBL_Pos          (8UL)          /*!< SSCARBL (Bit 8)                                       */
22825  #define R_GPT0_GTSSR_SSCARBL_Msk          (0x100UL)      /*!< SSCARBL (Bitfield-Mask: 0x01)                         */
22826  #define R_GPT0_GTSSR_SSGTRGF_Pos          (1UL)          /*!< SSGTRGF (Bit 1)                                       */
22827  #define R_GPT0_GTSSR_SSGTRGF_Msk          (0x2UL)        /*!< SSGTRGF (Bitfield-Mask: 0x01)                         */
22828  #define R_GPT0_GTSSR_SSGTRGR_Pos          (0UL)          /*!< SSGTRGR (Bit 0)                                       */
22829  #define R_GPT0_GTSSR_SSGTRGR_Msk          (0x1UL)        /*!< SSGTRGR (Bitfield-Mask: 0x01)                         */
22830 /* =========================================================  GTPSR  ========================================================= */
22831  #define R_GPT0_GTPSR_CSTOP_Pos            (31UL)         /*!< CSTOP (Bit 31)                                        */
22832  #define R_GPT0_GTPSR_CSTOP_Msk            (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
22833  #define R_GPT0_GTPSR_PSELC_Pos            (16UL)         /*!< PSELC (Bit 16)                                        */
22834  #define R_GPT0_GTPSR_PSELC_Msk            (0x10000UL)    /*!< PSELC (Bitfield-Mask: 0x01)                           */
22835  #define R_GPT0_GTPSR_PSCBFAH_Pos          (15UL)         /*!< PSCBFAH (Bit 15)                                      */
22836  #define R_GPT0_GTPSR_PSCBFAH_Msk          (0x8000UL)     /*!< PSCBFAH (Bitfield-Mask: 0x01)                         */
22837  #define R_GPT0_GTPSR_PSCBFAL_Pos          (14UL)         /*!< PSCBFAL (Bit 14)                                      */
22838  #define R_GPT0_GTPSR_PSCBFAL_Msk          (0x4000UL)     /*!< PSCBFAL (Bitfield-Mask: 0x01)                         */
22839  #define R_GPT0_GTPSR_PSCBRAH_Pos          (13UL)         /*!< PSCBRAH (Bit 13)                                      */
22840  #define R_GPT0_GTPSR_PSCBRAH_Msk          (0x2000UL)     /*!< PSCBRAH (Bitfield-Mask: 0x01)                         */
22841  #define R_GPT0_GTPSR_PSCBRAL_Pos          (12UL)         /*!< PSCBRAL (Bit 12)                                      */
22842  #define R_GPT0_GTPSR_PSCBRAL_Msk          (0x1000UL)     /*!< PSCBRAL (Bitfield-Mask: 0x01)                         */
22843  #define R_GPT0_GTPSR_PSCAFBH_Pos          (11UL)         /*!< PSCAFBH (Bit 11)                                      */
22844  #define R_GPT0_GTPSR_PSCAFBH_Msk          (0x800UL)      /*!< PSCAFBH (Bitfield-Mask: 0x01)                         */
22845  #define R_GPT0_GTPSR_PSCAFBL_Pos          (10UL)         /*!< PSCAFBL (Bit 10)                                      */
22846  #define R_GPT0_GTPSR_PSCAFBL_Msk          (0x400UL)      /*!< PSCAFBL (Bitfield-Mask: 0x01)                         */
22847  #define R_GPT0_GTPSR_PSCARBH_Pos          (9UL)          /*!< PSCARBH (Bit 9)                                       */
22848  #define R_GPT0_GTPSR_PSCARBH_Msk          (0x200UL)      /*!< PSCARBH (Bitfield-Mask: 0x01)                         */
22849  #define R_GPT0_GTPSR_PSCARBL_Pos          (8UL)          /*!< PSCARBL (Bit 8)                                       */
22850  #define R_GPT0_GTPSR_PSCARBL_Msk          (0x100UL)      /*!< PSCARBL (Bitfield-Mask: 0x01)                         */
22851  #define R_GPT0_GTPSR_PSGTRGF_Pos          (1UL)          /*!< PSGTRGF (Bit 1)                                       */
22852  #define R_GPT0_GTPSR_PSGTRGF_Msk          (0x2UL)        /*!< PSGTRGF (Bitfield-Mask: 0x01)                         */
22853  #define R_GPT0_GTPSR_PSGTRGR_Pos          (0UL)          /*!< PSGTRGR (Bit 0)                                       */
22854  #define R_GPT0_GTPSR_PSGTRGR_Msk          (0x1UL)        /*!< PSGTRGR (Bitfield-Mask: 0x01)                         */
22855 /* =========================================================  GTCSR  ========================================================= */
22856  #define R_GPT0_GTCSR_CCLR_Pos             (31UL)         /*!< CCLR (Bit 31)                                         */
22857  #define R_GPT0_GTCSR_CCLR_Msk             (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
22858  #define R_GPT0_GTCSR_CP1CCE_Pos           (27UL)         /*!< CP1CCE (Bit 27)                                       */
22859  #define R_GPT0_GTCSR_CP1CCE_Msk           (0x8000000UL)  /*!< CP1CCE (Bitfield-Mask: 0x01)                          */
22860  #define R_GPT0_GTCSR_CSCMSC_Pos           (24UL)         /*!< CSCMSC (Bit 24)                                       */
22861  #define R_GPT0_GTCSR_CSCMSC_Msk           (0x7000000UL)  /*!< CSCMSC (Bitfield-Mask: 0x07)                          */
22862  #define R_GPT0_GTCSR_CSELC_Pos            (16UL)         /*!< CSELC (Bit 16)                                        */
22863  #define R_GPT0_GTCSR_CSELC_Msk            (0x10000UL)    /*!< CSELC (Bitfield-Mask: 0x01)                           */
22864  #define R_GPT0_GTCSR_CSCBFAH_Pos          (15UL)         /*!< CSCBFAH (Bit 15)                                      */
22865  #define R_GPT0_GTCSR_CSCBFAH_Msk          (0x8000UL)     /*!< CSCBFAH (Bitfield-Mask: 0x01)                         */
22866  #define R_GPT0_GTCSR_CSCBFAL_Pos          (14UL)         /*!< CSCBFAL (Bit 14)                                      */
22867  #define R_GPT0_GTCSR_CSCBFAL_Msk          (0x4000UL)     /*!< CSCBFAL (Bitfield-Mask: 0x01)                         */
22868  #define R_GPT0_GTCSR_CSCBRAH_Pos          (13UL)         /*!< CSCBRAH (Bit 13)                                      */
22869  #define R_GPT0_GTCSR_CSCBRAH_Msk          (0x2000UL)     /*!< CSCBRAH (Bitfield-Mask: 0x01)                         */
22870  #define R_GPT0_GTCSR_CSCBRAL_Pos          (12UL)         /*!< CSCBRAL (Bit 12)                                      */
22871  #define R_GPT0_GTCSR_CSCBRAL_Msk          (0x1000UL)     /*!< CSCBRAL (Bitfield-Mask: 0x01)                         */
22872  #define R_GPT0_GTCSR_CSCAFBH_Pos          (11UL)         /*!< CSCAFBH (Bit 11)                                      */
22873  #define R_GPT0_GTCSR_CSCAFBH_Msk          (0x800UL)      /*!< CSCAFBH (Bitfield-Mask: 0x01)                         */
22874  #define R_GPT0_GTCSR_CSCAFBL_Pos          (10UL)         /*!< CSCAFBL (Bit 10)                                      */
22875  #define R_GPT0_GTCSR_CSCAFBL_Msk          (0x400UL)      /*!< CSCAFBL (Bitfield-Mask: 0x01)                         */
22876  #define R_GPT0_GTCSR_CSCARBH_Pos          (9UL)          /*!< CSCARBH (Bit 9)                                       */
22877  #define R_GPT0_GTCSR_CSCARBH_Msk          (0x200UL)      /*!< CSCARBH (Bitfield-Mask: 0x01)                         */
22878  #define R_GPT0_GTCSR_CSCARBL_Pos          (8UL)          /*!< CSCARBL (Bit 8)                                       */
22879  #define R_GPT0_GTCSR_CSCARBL_Msk          (0x100UL)      /*!< CSCARBL (Bitfield-Mask: 0x01)                         */
22880  #define R_GPT0_GTCSR_CSGTRGF_Pos          (1UL)          /*!< CSGTRGF (Bit 1)                                       */
22881  #define R_GPT0_GTCSR_CSGTRGF_Msk          (0x2UL)        /*!< CSGTRGF (Bitfield-Mask: 0x01)                         */
22882  #define R_GPT0_GTCSR_CSGTRGR_Pos          (0UL)          /*!< CSGTRGR (Bit 0)                                       */
22883  #define R_GPT0_GTCSR_CSGTRGR_Msk          (0x1UL)        /*!< CSGTRGR (Bitfield-Mask: 0x01)                         */
22884 /* ========================================================  GTUPSR  ========================================================= */
22885  #define R_GPT0_GTUPSR_USILVL_Pos          (24UL)         /*!< USILVL (Bit 24)                                       */
22886  #define R_GPT0_GTUPSR_USILVL_Msk          (0xf000000UL)  /*!< USILVL (Bitfield-Mask: 0x0f)                          */
22887  #define R_GPT0_GTUPSR_USELC_Pos           (16UL)         /*!< USELC (Bit 16)                                        */
22888  #define R_GPT0_GTUPSR_USELC_Msk           (0x10000UL)    /*!< USELC (Bitfield-Mask: 0x01)                           */
22889  #define R_GPT0_GTUPSR_USCBFAH_Pos         (15UL)         /*!< USCBFAH (Bit 15)                                      */
22890  #define R_GPT0_GTUPSR_USCBFAH_Msk         (0x8000UL)     /*!< USCBFAH (Bitfield-Mask: 0x01)                         */
22891  #define R_GPT0_GTUPSR_USCBFAL_Pos         (14UL)         /*!< USCBFAL (Bit 14)                                      */
22892  #define R_GPT0_GTUPSR_USCBFAL_Msk         (0x4000UL)     /*!< USCBFAL (Bitfield-Mask: 0x01)                         */
22893  #define R_GPT0_GTUPSR_USCBRAH_Pos         (13UL)         /*!< USCBRAH (Bit 13)                                      */
22894  #define R_GPT0_GTUPSR_USCBRAH_Msk         (0x2000UL)     /*!< USCBRAH (Bitfield-Mask: 0x01)                         */
22895  #define R_GPT0_GTUPSR_USCBRAL_Pos         (12UL)         /*!< USCBRAL (Bit 12)                                      */
22896  #define R_GPT0_GTUPSR_USCBRAL_Msk         (0x1000UL)     /*!< USCBRAL (Bitfield-Mask: 0x01)                         */
22897  #define R_GPT0_GTUPSR_USCAFBH_Pos         (11UL)         /*!< USCAFBH (Bit 11)                                      */
22898  #define R_GPT0_GTUPSR_USCAFBH_Msk         (0x800UL)      /*!< USCAFBH (Bitfield-Mask: 0x01)                         */
22899  #define R_GPT0_GTUPSR_USCAFBL_Pos         (10UL)         /*!< USCAFBL (Bit 10)                                      */
22900  #define R_GPT0_GTUPSR_USCAFBL_Msk         (0x400UL)      /*!< USCAFBL (Bitfield-Mask: 0x01)                         */
22901  #define R_GPT0_GTUPSR_USCARBH_Pos         (9UL)          /*!< USCARBH (Bit 9)                                       */
22902  #define R_GPT0_GTUPSR_USCARBH_Msk         (0x200UL)      /*!< USCARBH (Bitfield-Mask: 0x01)                         */
22903  #define R_GPT0_GTUPSR_USCARBL_Pos         (8UL)          /*!< USCARBL (Bit 8)                                       */
22904  #define R_GPT0_GTUPSR_USCARBL_Msk         (0x100UL)      /*!< USCARBL (Bitfield-Mask: 0x01)                         */
22905  #define R_GPT0_GTUPSR_USGTRGF_Pos         (1UL)          /*!< USGTRGF (Bit 1)                                       */
22906  #define R_GPT0_GTUPSR_USGTRGF_Msk         (0x2UL)        /*!< USGTRGF (Bitfield-Mask: 0x01)                         */
22907  #define R_GPT0_GTUPSR_USGTRGR_Pos         (0UL)          /*!< USGTRGR (Bit 0)                                       */
22908  #define R_GPT0_GTUPSR_USGTRGR_Msk         (0x1UL)        /*!< USGTRGR (Bitfield-Mask: 0x01)                         */
22909 /* ========================================================  GTDNSR  ========================================================= */
22910  #define R_GPT0_GTDNSR_DSILVL_Pos          (24UL)         /*!< DSILVL (Bit 24)                                       */
22911  #define R_GPT0_GTDNSR_DSILVL_Msk          (0xf000000UL)  /*!< DSILVL (Bitfield-Mask: 0x0f)                          */
22912  #define R_GPT0_GTDNSR_DSELC_Pos           (16UL)         /*!< DSELC (Bit 16)                                        */
22913  #define R_GPT0_GTDNSR_DSELC_Msk           (0x10000UL)    /*!< DSELC (Bitfield-Mask: 0x01)                           */
22914  #define R_GPT0_GTDNSR_DSCBFAH_Pos         (15UL)         /*!< DSCBFAH (Bit 15)                                      */
22915  #define R_GPT0_GTDNSR_DSCBFAH_Msk         (0x8000UL)     /*!< DSCBFAH (Bitfield-Mask: 0x01)                         */
22916  #define R_GPT0_GTDNSR_DSCBFAL_Pos         (14UL)         /*!< DSCBFAL (Bit 14)                                      */
22917  #define R_GPT0_GTDNSR_DSCBFAL_Msk         (0x4000UL)     /*!< DSCBFAL (Bitfield-Mask: 0x01)                         */
22918  #define R_GPT0_GTDNSR_DSCBRAH_Pos         (13UL)         /*!< DSCBRAH (Bit 13)                                      */
22919  #define R_GPT0_GTDNSR_DSCBRAH_Msk         (0x2000UL)     /*!< DSCBRAH (Bitfield-Mask: 0x01)                         */
22920  #define R_GPT0_GTDNSR_DSCBRAL_Pos         (12UL)         /*!< DSCBRAL (Bit 12)                                      */
22921  #define R_GPT0_GTDNSR_DSCBRAL_Msk         (0x1000UL)     /*!< DSCBRAL (Bitfield-Mask: 0x01)                         */
22922  #define R_GPT0_GTDNSR_DSCAFBH_Pos         (11UL)         /*!< DSCAFBH (Bit 11)                                      */
22923  #define R_GPT0_GTDNSR_DSCAFBH_Msk         (0x800UL)      /*!< DSCAFBH (Bitfield-Mask: 0x01)                         */
22924  #define R_GPT0_GTDNSR_DSCAFBL_Pos         (10UL)         /*!< DSCAFBL (Bit 10)                                      */
22925  #define R_GPT0_GTDNSR_DSCAFBL_Msk         (0x400UL)      /*!< DSCAFBL (Bitfield-Mask: 0x01)                         */
22926  #define R_GPT0_GTDNSR_DSCARBH_Pos         (9UL)          /*!< DSCARBH (Bit 9)                                       */
22927  #define R_GPT0_GTDNSR_DSCARBH_Msk         (0x200UL)      /*!< DSCARBH (Bitfield-Mask: 0x01)                         */
22928  #define R_GPT0_GTDNSR_DSCARBL_Pos         (8UL)          /*!< DSCARBL (Bit 8)                                       */
22929  #define R_GPT0_GTDNSR_DSCARBL_Msk         (0x100UL)      /*!< DSCARBL (Bitfield-Mask: 0x01)                         */
22930  #define R_GPT0_GTDNSR_DSGTRGF_Pos         (1UL)          /*!< DSGTRGF (Bit 1)                                       */
22931  #define R_GPT0_GTDNSR_DSGTRGF_Msk         (0x2UL)        /*!< DSGTRGF (Bitfield-Mask: 0x01)                         */
22932  #define R_GPT0_GTDNSR_DSGTRGR_Pos         (0UL)          /*!< DSGTRGR (Bit 0)                                       */
22933  #define R_GPT0_GTDNSR_DSGTRGR_Msk         (0x1UL)        /*!< DSGTRGR (Bitfield-Mask: 0x01)                         */
22934 /* ========================================================  GTICASR  ======================================================== */
22935  #define R_GPT0_GTICASR_ASELC_Pos          (16UL)         /*!< ASELC (Bit 16)                                        */
22936  #define R_GPT0_GTICASR_ASELC_Msk          (0x10000UL)    /*!< ASELC (Bitfield-Mask: 0x01)                           */
22937  #define R_GPT0_GTICASR_ASCBFAH_Pos        (15UL)         /*!< ASCBFAH (Bit 15)                                      */
22938  #define R_GPT0_GTICASR_ASCBFAH_Msk        (0x8000UL)     /*!< ASCBFAH (Bitfield-Mask: 0x01)                         */
22939  #define R_GPT0_GTICASR_ASCBFAL_Pos        (14UL)         /*!< ASCBFAL (Bit 14)                                      */
22940  #define R_GPT0_GTICASR_ASCBFAL_Msk        (0x4000UL)     /*!< ASCBFAL (Bitfield-Mask: 0x01)                         */
22941  #define R_GPT0_GTICASR_ASCBRAH_Pos        (13UL)         /*!< ASCBRAH (Bit 13)                                      */
22942  #define R_GPT0_GTICASR_ASCBRAH_Msk        (0x2000UL)     /*!< ASCBRAH (Bitfield-Mask: 0x01)                         */
22943  #define R_GPT0_GTICASR_ASCBRAL_Pos        (12UL)         /*!< ASCBRAL (Bit 12)                                      */
22944  #define R_GPT0_GTICASR_ASCBRAL_Msk        (0x1000UL)     /*!< ASCBRAL (Bitfield-Mask: 0x01)                         */
22945  #define R_GPT0_GTICASR_ASCAFBH_Pos        (11UL)         /*!< ASCAFBH (Bit 11)                                      */
22946  #define R_GPT0_GTICASR_ASCAFBH_Msk        (0x800UL)      /*!< ASCAFBH (Bitfield-Mask: 0x01)                         */
22947  #define R_GPT0_GTICASR_ASCAFBL_Pos        (10UL)         /*!< ASCAFBL (Bit 10)                                      */
22948  #define R_GPT0_GTICASR_ASCAFBL_Msk        (0x400UL)      /*!< ASCAFBL (Bitfield-Mask: 0x01)                         */
22949  #define R_GPT0_GTICASR_ASCARBH_Pos        (9UL)          /*!< ASCARBH (Bit 9)                                       */
22950  #define R_GPT0_GTICASR_ASCARBH_Msk        (0x200UL)      /*!< ASCARBH (Bitfield-Mask: 0x01)                         */
22951  #define R_GPT0_GTICASR_ASCARBL_Pos        (8UL)          /*!< ASCARBL (Bit 8)                                       */
22952  #define R_GPT0_GTICASR_ASCARBL_Msk        (0x100UL)      /*!< ASCARBL (Bitfield-Mask: 0x01)                         */
22953  #define R_GPT0_GTICASR_ASGTRGF_Pos        (1UL)          /*!< ASGTRGF (Bit 1)                                       */
22954  #define R_GPT0_GTICASR_ASGTRGF_Msk        (0x2UL)        /*!< ASGTRGF (Bitfield-Mask: 0x01)                         */
22955  #define R_GPT0_GTICASR_ASGTRGR_Pos        (0UL)          /*!< ASGTRGR (Bit 0)                                       */
22956  #define R_GPT0_GTICASR_ASGTRGR_Msk        (0x1UL)        /*!< ASGTRGR (Bitfield-Mask: 0x01)                         */
22957 /* ========================================================  GTICBSR  ======================================================== */
22958  #define R_GPT0_GTICBSR_BSELC_Pos          (16UL)         /*!< BSELC (Bit 16)                                        */
22959  #define R_GPT0_GTICBSR_BSELC_Msk          (0x10000UL)    /*!< BSELC (Bitfield-Mask: 0x01)                           */
22960  #define R_GPT0_GTICBSR_BSCBFAH_Pos        (15UL)         /*!< BSCBFAH (Bit 15)                                      */
22961  #define R_GPT0_GTICBSR_BSCBFAH_Msk        (0x8000UL)     /*!< BSCBFAH (Bitfield-Mask: 0x01)                         */
22962  #define R_GPT0_GTICBSR_BSCBFAL_Pos        (14UL)         /*!< BSCBFAL (Bit 14)                                      */
22963  #define R_GPT0_GTICBSR_BSCBFAL_Msk        (0x4000UL)     /*!< BSCBFAL (Bitfield-Mask: 0x01)                         */
22964  #define R_GPT0_GTICBSR_BSCBRAH_Pos        (13UL)         /*!< BSCBRAH (Bit 13)                                      */
22965  #define R_GPT0_GTICBSR_BSCBRAH_Msk        (0x2000UL)     /*!< BSCBRAH (Bitfield-Mask: 0x01)                         */
22966  #define R_GPT0_GTICBSR_BSCBRAL_Pos        (12UL)         /*!< BSCBRAL (Bit 12)                                      */
22967  #define R_GPT0_GTICBSR_BSCBRAL_Msk        (0x1000UL)     /*!< BSCBRAL (Bitfield-Mask: 0x01)                         */
22968  #define R_GPT0_GTICBSR_BSCAFBH_Pos        (11UL)         /*!< BSCAFBH (Bit 11)                                      */
22969  #define R_GPT0_GTICBSR_BSCAFBH_Msk        (0x800UL)      /*!< BSCAFBH (Bitfield-Mask: 0x01)                         */
22970  #define R_GPT0_GTICBSR_BSCAFBL_Pos        (10UL)         /*!< BSCAFBL (Bit 10)                                      */
22971  #define R_GPT0_GTICBSR_BSCAFBL_Msk        (0x400UL)      /*!< BSCAFBL (Bitfield-Mask: 0x01)                         */
22972  #define R_GPT0_GTICBSR_BSCARBH_Pos        (9UL)          /*!< BSCARBH (Bit 9)                                       */
22973  #define R_GPT0_GTICBSR_BSCARBH_Msk        (0x200UL)      /*!< BSCARBH (Bitfield-Mask: 0x01)                         */
22974  #define R_GPT0_GTICBSR_BSCARBL_Pos        (8UL)          /*!< BSCARBL (Bit 8)                                       */
22975  #define R_GPT0_GTICBSR_BSCARBL_Msk        (0x100UL)      /*!< BSCARBL (Bitfield-Mask: 0x01)                         */
22976  #define R_GPT0_GTICBSR_BSGTRGF_Pos        (1UL)          /*!< BSGTRGF (Bit 1)                                       */
22977  #define R_GPT0_GTICBSR_BSGTRGF_Msk        (0x2UL)        /*!< BSGTRGF (Bitfield-Mask: 0x01)                         */
22978  #define R_GPT0_GTICBSR_BSGTRGR_Pos        (0UL)          /*!< BSGTRGR (Bit 0)                                       */
22979  #define R_GPT0_GTICBSR_BSGTRGR_Msk        (0x1UL)        /*!< BSGTRGR (Bitfield-Mask: 0x01)                         */
22980 /* =========================================================  GTCR  ========================================================== */
22981  #define R_GPT0_GTCR_CKEG_Pos              (27UL)         /*!< CKEG (Bit 27)                                         */
22982  #define R_GPT0_GTCR_CKEG_Msk              (0x18000000UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
22983  #define R_GPT0_GTCR_TPCS_Pos              (23UL)         /*!< TPCS (Bit 23)                                         */
22984  #define R_GPT0_GTCR_TPCS_Msk              (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
22985  #define R_GPT0_GTCR_MD_Pos                (16UL)         /*!< MD (Bit 16)                                           */
22986  #define R_GPT0_GTCR_MD_Msk                (0xf0000UL)    /*!< MD (Bitfield-Mask: 0x0f)                              */
22987  #define R_GPT0_GTCR_SSCEN_Pos             (15UL)         /*!< SSCEN (Bit 15)                                        */
22988  #define R_GPT0_GTCR_SSCEN_Msk             (0x8000UL)     /*!< SSCEN (Bitfield-Mask: 0x01)                           */
22989  #define R_GPT0_GTCR_CPSCD_Pos             (12UL)         /*!< CPSCD (Bit 12)                                        */
22990  #define R_GPT0_GTCR_CPSCD_Msk             (0x1000UL)     /*!< CPSCD (Bitfield-Mask: 0x01)                           */
22991  #define R_GPT0_GTCR_SSCGRP_Pos            (10UL)         /*!< SSCGRP (Bit 10)                                       */
22992  #define R_GPT0_GTCR_SSCGRP_Msk            (0xc00UL)      /*!< SSCGRP (Bitfield-Mask: 0x03)                          */
22993  #define R_GPT0_GTCR_SCGTIOC_Pos           (9UL)          /*!< SCGTIOC (Bit 9)                                       */
22994  #define R_GPT0_GTCR_SCGTIOC_Msk           (0x200UL)      /*!< SCGTIOC (Bitfield-Mask: 0x01)                         */
22995  #define R_GPT0_GTCR_ICDS_Pos              (8UL)          /*!< ICDS (Bit 8)                                          */
22996  #define R_GPT0_GTCR_ICDS_Msk              (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
22997  #define R_GPT0_GTCR_CST_Pos               (0UL)          /*!< CST (Bit 0)                                           */
22998  #define R_GPT0_GTCR_CST_Msk               (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
22999 /* =======================================================  GTUDDTYC  ======================================================== */
23000  #define R_GPT0_GTUDDTYC_OBDTYR_Pos        (27UL)         /*!< OBDTYR (Bit 27)                                       */
23001  #define R_GPT0_GTUDDTYC_OBDTYR_Msk        (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
23002  #define R_GPT0_GTUDDTYC_OBDTYF_Pos        (26UL)         /*!< OBDTYF (Bit 26)                                       */
23003  #define R_GPT0_GTUDDTYC_OBDTYF_Msk        (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
23004  #define R_GPT0_GTUDDTYC_OBDTY_Pos         (24UL)         /*!< OBDTY (Bit 24)                                        */
23005  #define R_GPT0_GTUDDTYC_OBDTY_Msk         (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
23006  #define R_GPT0_GTUDDTYC_OADTYR_Pos        (19UL)         /*!< OADTYR (Bit 19)                                       */
23007  #define R_GPT0_GTUDDTYC_OADTYR_Msk        (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
23008  #define R_GPT0_GTUDDTYC_OADTYF_Pos        (18UL)         /*!< OADTYF (Bit 18)                                       */
23009  #define R_GPT0_GTUDDTYC_OADTYF_Msk        (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
23010  #define R_GPT0_GTUDDTYC_OADTY_Pos         (16UL)         /*!< OADTY (Bit 16)                                        */
23011  #define R_GPT0_GTUDDTYC_OADTY_Msk         (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
23012  #define R_GPT0_GTUDDTYC_UDF_Pos           (1UL)          /*!< UDF (Bit 1)                                           */
23013  #define R_GPT0_GTUDDTYC_UDF_Msk           (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
23014  #define R_GPT0_GTUDDTYC_UD_Pos            (0UL)          /*!< UD (Bit 0)                                            */
23015  #define R_GPT0_GTUDDTYC_UD_Msk            (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
23016 /* =========================================================  GTIOR  ========================================================= */
23017  #define R_GPT0_GTIOR_NFCSB_Pos            (30UL)         /*!< NFCSB (Bit 30)                                        */
23018  #define R_GPT0_GTIOR_NFCSB_Msk            (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
23019  #define R_GPT0_GTIOR_NFBEN_Pos            (29UL)         /*!< NFBEN (Bit 29)                                        */
23020  #define R_GPT0_GTIOR_NFBEN_Msk            (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
23021  #define R_GPT0_GTIOR_OBEOCD_Pos           (27UL)         /*!< OBEOCD (Bit 27)                                       */
23022  #define R_GPT0_GTIOR_OBEOCD_Msk           (0x8000000UL)  /*!< OBEOCD (Bitfield-Mask: 0x01)                          */
23023  #define R_GPT0_GTIOR_OBDF_Pos             (25UL)         /*!< OBDF (Bit 25)                                         */
23024  #define R_GPT0_GTIOR_OBDF_Msk             (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
23025  #define R_GPT0_GTIOR_OBE_Pos              (24UL)         /*!< OBE (Bit 24)                                          */
23026  #define R_GPT0_GTIOR_OBE_Msk              (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
23027  #define R_GPT0_GTIOR_OBHLD_Pos            (23UL)         /*!< OBHLD (Bit 23)                                        */
23028  #define R_GPT0_GTIOR_OBHLD_Msk            (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
23029  #define R_GPT0_GTIOR_OBDFLT_Pos           (22UL)         /*!< OBDFLT (Bit 22)                                       */
23030  #define R_GPT0_GTIOR_OBDFLT_Msk           (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
23031  #define R_GPT0_GTIOR_GTIOB_Pos            (16UL)         /*!< GTIOB (Bit 16)                                        */
23032  #define R_GPT0_GTIOR_GTIOB_Msk            (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
23033  #define R_GPT0_GTIOR_NFCSA_Pos            (14UL)         /*!< NFCSA (Bit 14)                                        */
23034  #define R_GPT0_GTIOR_NFCSA_Msk            (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
23035  #define R_GPT0_GTIOR_NFAEN_Pos            (13UL)         /*!< NFAEN (Bit 13)                                        */
23036  #define R_GPT0_GTIOR_NFAEN_Msk            (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
23037  #define R_GPT0_GTIOR_PSYE_Pos             (12UL)         /*!< PSYE (Bit 12)                                         */
23038  #define R_GPT0_GTIOR_PSYE_Msk             (0x1000UL)     /*!< PSYE (Bitfield-Mask: 0x01)                            */
23039  #define R_GPT0_GTIOR_OAEOCD_Pos           (11UL)         /*!< OAEOCD (Bit 11)                                       */
23040  #define R_GPT0_GTIOR_OAEOCD_Msk           (0x800UL)      /*!< OAEOCD (Bitfield-Mask: 0x01)                          */
23041  #define R_GPT0_GTIOR_OADF_Pos             (9UL)          /*!< OADF (Bit 9)                                          */
23042  #define R_GPT0_GTIOR_OADF_Msk             (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
23043  #define R_GPT0_GTIOR_OAE_Pos              (8UL)          /*!< OAE (Bit 8)                                           */
23044  #define R_GPT0_GTIOR_OAE_Msk              (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
23045  #define R_GPT0_GTIOR_OAHLD_Pos            (7UL)          /*!< OAHLD (Bit 7)                                         */
23046  #define R_GPT0_GTIOR_OAHLD_Msk            (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
23047  #define R_GPT0_GTIOR_OADFLT_Pos           (6UL)          /*!< OADFLT (Bit 6)                                        */
23048  #define R_GPT0_GTIOR_OADFLT_Msk           (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
23049  #define R_GPT0_GTIOR_CPSCIR_Pos           (5UL)          /*!< CPSCIR (Bit 5)                                        */
23050  #define R_GPT0_GTIOR_CPSCIR_Msk           (0x20UL)       /*!< CPSCIR (Bitfield-Mask: 0x01)                          */
23051  #define R_GPT0_GTIOR_GTIOA_Pos            (0UL)          /*!< GTIOA (Bit 0)                                         */
23052  #define R_GPT0_GTIOR_GTIOA_Msk            (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
23053 /* ========================================================  GTINTAD  ======================================================== */
23054  #define R_GPT0_GTINTAD_GTINTPC_Pos        (31UL)         /*!< GTINTPC (Bit 31)                                      */
23055  #define R_GPT0_GTINTAD_GTINTPC_Msk        (0x80000000UL) /*!< GTINTPC (Bitfield-Mask: 0x01)                         */
23056  #define R_GPT0_GTINTAD_GRPABL_Pos         (30UL)         /*!< GRPABL (Bit 30)                                       */
23057  #define R_GPT0_GTINTAD_GRPABL_Msk         (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
23058  #define R_GPT0_GTINTAD_GRPABH_Pos         (29UL)         /*!< GRPABH (Bit 29)                                       */
23059  #define R_GPT0_GTINTAD_GRPABH_Msk         (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
23060  #define R_GPT0_GTINTAD_GRPDTE_Pos         (28UL)         /*!< GRPDTE (Bit 28)                                       */
23061  #define R_GPT0_GTINTAD_GRPDTE_Msk         (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
23062  #define R_GPT0_GTINTAD_GRP_Pos            (24UL)         /*!< GRP (Bit 24)                                          */
23063  #define R_GPT0_GTINTAD_GRP_Msk            (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
23064  #define R_GPT0_GTINTAD_ADTRDEN_Pos        (17UL)         /*!< ADTRDEN (Bit 17)                                      */
23065  #define R_GPT0_GTINTAD_ADTRDEN_Msk        (0x20000UL)    /*!< ADTRDEN (Bitfield-Mask: 0x01)                         */
23066  #define R_GPT0_GTINTAD_ADTRUEN_Pos        (16UL)         /*!< ADTRUEN (Bit 16)                                      */
23067  #define R_GPT0_GTINTAD_ADTRUEN_Msk        (0x10000UL)    /*!< ADTRUEN (Bitfield-Mask: 0x01)                         */
23068  #define R_GPT0_GTINTAD_SCFPU_Pos          (15UL)         /*!< SCFPU (Bit 15)                                        */
23069  #define R_GPT0_GTINTAD_SCFPU_Msk          (0x8000UL)     /*!< SCFPU (Bitfield-Mask: 0x01)                           */
23070  #define R_GPT0_GTINTAD_SCFPO_Pos          (14UL)         /*!< SCFPO (Bit 14)                                        */
23071  #define R_GPT0_GTINTAD_SCFPO_Msk          (0x4000UL)     /*!< SCFPO (Bitfield-Mask: 0x01)                           */
23072  #define R_GPT0_GTINTAD_SCF_Pos            (8UL)          /*!< SCF (Bit 8)                                           */
23073  #define R_GPT0_GTINTAD_SCF_Msk            (0x100UL)      /*!< SCF (Bitfield-Mask: 0x01)                             */
23074 /* =========================================================  GTST  ========================================================== */
23075  #define R_GPT0_GTST_OABLF_Pos             (30UL)         /*!< OABLF (Bit 30)                                        */
23076  #define R_GPT0_GTST_OABLF_Msk             (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
23077  #define R_GPT0_GTST_OABHF_Pos             (29UL)         /*!< OABHF (Bit 29)                                        */
23078  #define R_GPT0_GTST_OABHF_Msk             (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
23079  #define R_GPT0_GTST_DTEF_Pos              (28UL)         /*!< DTEF (Bit 28)                                         */
23080  #define R_GPT0_GTST_DTEF_Msk              (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
23081  #define R_GPT0_GTST_ODF_Pos               (24UL)         /*!< ODF (Bit 24)                                          */
23082  #define R_GPT0_GTST_ODF_Msk               (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
23083  #define R_GPT0_GTST_ADTRBDF_Pos           (19UL)         /*!< ADTRBDF (Bit 19)                                      */
23084  #define R_GPT0_GTST_ADTRBDF_Msk           (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
23085  #define R_GPT0_GTST_ADTRBUF_Pos           (18UL)         /*!< ADTRBUF (Bit 18)                                      */
23086  #define R_GPT0_GTST_ADTRBUF_Msk           (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
23087  #define R_GPT0_GTST_ADTRADF_Pos           (17UL)         /*!< ADTRADF (Bit 17)                                      */
23088  #define R_GPT0_GTST_ADTRADF_Msk           (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
23089  #define R_GPT0_GTST_ADTRAUF_Pos           (16UL)         /*!< ADTRAUF (Bit 16)                                      */
23090  #define R_GPT0_GTST_ADTRAUF_Msk           (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
23091  #define R_GPT0_GTST_TUCF_Pos              (15UL)         /*!< TUCF (Bit 15)                                         */
23092  #define R_GPT0_GTST_TUCF_Msk              (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
23093  #define R_GPT0_GTST_ITCNT_Pos             (8UL)          /*!< ITCNT (Bit 8)                                         */
23094  #define R_GPT0_GTST_ITCNT_Msk             (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
23095  #define R_GPT0_GTST_TCFPU_Pos             (7UL)          /*!< TCFPU (Bit 7)                                         */
23096  #define R_GPT0_GTST_TCFPU_Msk             (0x80UL)       /*!< TCFPU (Bitfield-Mask: 0x01)                           */
23097  #define R_GPT0_GTST_TCFPO_Pos             (6UL)          /*!< TCFPO (Bit 6)                                         */
23098  #define R_GPT0_GTST_TCFPO_Msk             (0x40UL)       /*!< TCFPO (Bitfield-Mask: 0x01)                           */
23099  #define R_GPT0_GTST_TCFF_Pos              (5UL)          /*!< TCFF (Bit 5)                                          */
23100  #define R_GPT0_GTST_TCFF_Msk              (0x20UL)       /*!< TCFF (Bitfield-Mask: 0x01)                            */
23101  #define R_GPT0_GTST_TCFE_Pos              (4UL)          /*!< TCFE (Bit 4)                                          */
23102  #define R_GPT0_GTST_TCFE_Msk              (0x10UL)       /*!< TCFE (Bitfield-Mask: 0x01)                            */
23103  #define R_GPT0_GTST_TCFD_Pos              (3UL)          /*!< TCFD (Bit 3)                                          */
23104  #define R_GPT0_GTST_TCFD_Msk              (0x8UL)        /*!< TCFD (Bitfield-Mask: 0x01)                            */
23105  #define R_GPT0_GTST_TCFC_Pos              (2UL)          /*!< TCFC (Bit 2)                                          */
23106  #define R_GPT0_GTST_TCFC_Msk              (0x4UL)        /*!< TCFC (Bitfield-Mask: 0x01)                            */
23107  #define R_GPT0_GTST_TCFB_Pos              (1UL)          /*!< TCFB (Bit 1)                                          */
23108  #define R_GPT0_GTST_TCFB_Msk              (0x2UL)        /*!< TCFB (Bitfield-Mask: 0x01)                            */
23109  #define R_GPT0_GTST_TCFA_Pos              (0UL)          /*!< TCFA (Bit 0)                                          */
23110  #define R_GPT0_GTST_TCFA_Msk              (0x1UL)        /*!< TCFA (Bitfield-Mask: 0x01)                            */
23111  #define R_GPT0_GTST_PCF_Pos               (31UL)         /*!< PCF (Bit 31)                                          */
23112  #define R_GPT0_GTST_PCF_Msk               (0x80000000UL) /*!< PCF (Bitfield-Mask: 0x01)                             */
23113 /* =========================================================  GTBER  ========================================================= */
23114  #define R_GPT0_GTBER_ADTDB_Pos            (30UL)         /*!< ADTDB (Bit 30)                                        */
23115  #define R_GPT0_GTBER_ADTDB_Msk            (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
23116  #define R_GPT0_GTBER_ADTTB_Pos            (28UL)         /*!< ADTTB (Bit 28)                                        */
23117  #define R_GPT0_GTBER_ADTTB_Msk            (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
23118  #define R_GPT0_GTBER_ADTDA_Pos            (26UL)         /*!< ADTDA (Bit 26)                                        */
23119  #define R_GPT0_GTBER_ADTDA_Msk            (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
23120  #define R_GPT0_GTBER_ADTTA_Pos            (24UL)         /*!< ADTTA (Bit 24)                                        */
23121  #define R_GPT0_GTBER_ADTTA_Msk            (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
23122  #define R_GPT0_GTBER_CCRSWT_Pos           (22UL)         /*!< CCRSWT (Bit 22)                                       */
23123  #define R_GPT0_GTBER_CCRSWT_Msk           (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
23124  #define R_GPT0_GTBER_PR_Pos               (20UL)         /*!< PR (Bit 20)                                           */
23125  #define R_GPT0_GTBER_PR_Msk               (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
23126  #define R_GPT0_GTBER_CCRB_Pos             (18UL)         /*!< CCRB (Bit 18)                                         */
23127  #define R_GPT0_GTBER_CCRB_Msk             (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
23128  #define R_GPT0_GTBER_CCRA_Pos             (16UL)         /*!< CCRA (Bit 16)                                         */
23129  #define R_GPT0_GTBER_CCRA_Msk             (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
23130  #define R_GPT0_GTBER_DBRTEC_Pos           (8UL)          /*!< DBRTEC (Bit 8)                                        */
23131  #define R_GPT0_GTBER_DBRTEC_Msk           (0x100UL)      /*!< DBRTEC (Bitfield-Mask: 0x01)                          */
23132  #define R_GPT0_GTBER_BD3_Pos              (3UL)          /*!< BD3 (Bit 3)                                           */
23133  #define R_GPT0_GTBER_BD3_Msk              (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
23134  #define R_GPT0_GTBER_BD2_Pos              (2UL)          /*!< BD2 (Bit 2)                                           */
23135  #define R_GPT0_GTBER_BD2_Msk              (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
23136  #define R_GPT0_GTBER_BD1_Pos              (1UL)          /*!< BD1 (Bit 1)                                           */
23137  #define R_GPT0_GTBER_BD1_Msk              (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
23138  #define R_GPT0_GTBER_BD0_Pos              (0UL)          /*!< BD0 (Bit 0)                                           */
23139  #define R_GPT0_GTBER_BD0_Msk              (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
23140 /* =========================================================  GTITC  ========================================================= */
23141  #define R_GPT0_GTITC_ADTBL_Pos            (14UL)         /*!< ADTBL (Bit 14)                                        */
23142  #define R_GPT0_GTITC_ADTBL_Msk            (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
23143  #define R_GPT0_GTITC_ADTAL_Pos            (12UL)         /*!< ADTAL (Bit 12)                                        */
23144  #define R_GPT0_GTITC_ADTAL_Msk            (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
23145  #define R_GPT0_GTITC_IVTT_Pos             (8UL)          /*!< IVTT (Bit 8)                                          */
23146  #define R_GPT0_GTITC_IVTT_Msk             (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
23147  #define R_GPT0_GTITC_IVTC_Pos             (6UL)          /*!< IVTC (Bit 6)                                          */
23148  #define R_GPT0_GTITC_IVTC_Msk             (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
23149  #define R_GPT0_GTITC_ITLF_Pos             (5UL)          /*!< ITLF (Bit 5)                                          */
23150  #define R_GPT0_GTITC_ITLF_Msk             (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
23151  #define R_GPT0_GTITC_ITLE_Pos             (4UL)          /*!< ITLE (Bit 4)                                          */
23152  #define R_GPT0_GTITC_ITLE_Msk             (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
23153  #define R_GPT0_GTITC_ITLD_Pos             (3UL)          /*!< ITLD (Bit 3)                                          */
23154  #define R_GPT0_GTITC_ITLD_Msk             (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
23155  #define R_GPT0_GTITC_ITLC_Pos             (2UL)          /*!< ITLC (Bit 2)                                          */
23156  #define R_GPT0_GTITC_ITLC_Msk             (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
23157  #define R_GPT0_GTITC_ITLB_Pos             (1UL)          /*!< ITLB (Bit 1)                                          */
23158  #define R_GPT0_GTITC_ITLB_Msk             (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
23159  #define R_GPT0_GTITC_ITLA_Pos             (0UL)          /*!< ITLA (Bit 0)                                          */
23160  #define R_GPT0_GTITC_ITLA_Msk             (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
23161 /* =========================================================  GTCNT  ========================================================= */
23162  #define R_GPT0_GTCNT_GTCNT_Pos            (0UL)          /*!< GTCNT (Bit 0)                                         */
23163  #define R_GPT0_GTCNT_GTCNT_Msk            (0xffffffffUL) /*!< GTCNT (Bitfield-Mask: 0xffffffff)                     */
23164 /* =========================================================  GTCCR  ========================================================= */
23165  #define R_GPT0_GTCCR_GTCCR_Pos            (0UL)          /*!< GTCCR (Bit 0)                                         */
23166  #define R_GPT0_GTCCR_GTCCR_Msk            (0xffffffffUL) /*!< GTCCR (Bitfield-Mask: 0xffffffff)                     */
23167 /* =========================================================  GTPR  ========================================================== */
23168  #define R_GPT0_GTPR_GTPR_Pos              (0UL)          /*!< GTPR (Bit 0)                                          */
23169  #define R_GPT0_GTPR_GTPR_Msk              (0xffffffffUL) /*!< GTPR (Bitfield-Mask: 0xffffffff)                      */
23170 /* =========================================================  GTPBR  ========================================================= */
23171  #define R_GPT0_GTPBR_GTPBR_Pos            (0UL)          /*!< GTPBR (Bit 0)                                         */
23172  #define R_GPT0_GTPBR_GTPBR_Msk            (0xffffffffUL) /*!< GTPBR (Bitfield-Mask: 0xffffffff)                     */
23173 /* ========================================================  GTPDBR  ========================================================= */
23174  #define R_GPT0_GTPDBR_GTPDBR_Pos          (0UL)          /*!< GTPDBR (Bit 0)                                        */
23175  #define R_GPT0_GTPDBR_GTPDBR_Msk          (0xffffffffUL) /*!< GTPDBR (Bitfield-Mask: 0xffffffff)                    */
23176 /* ========================================================  GTADTRA  ======================================================== */
23177  #define R_GPT0_GTADTRA_GTADTRA_Pos        (0UL)          /*!< GTADTRA (Bit 0)                                       */
23178  #define R_GPT0_GTADTRA_GTADTRA_Msk        (0xffffffffUL) /*!< GTADTRA (Bitfield-Mask: 0xffffffff)                   */
23179 /* ========================================================  GTADTRB  ======================================================== */
23180  #define R_GPT0_GTADTRB_GTADTRB_Pos        (0UL)          /*!< GTADTRB (Bit 0)                                       */
23181  #define R_GPT0_GTADTRB_GTADTRB_Msk        (0xffffffffUL) /*!< GTADTRB (Bitfield-Mask: 0xffffffff)                   */
23182 /* =======================================================  GTADTBRA  ======================================================== */
23183  #define R_GPT0_GTADTBRA_GTADTBRA_Pos      (0UL)          /*!< GTADTBRA (Bit 0)                                      */
23184  #define R_GPT0_GTADTBRA_GTADTBRA_Msk      (0xffffffffUL) /*!< GTADTBRA (Bitfield-Mask: 0xffffffff)                  */
23185 /* =======================================================  GTADTBRB  ======================================================== */
23186  #define R_GPT0_GTADTBRB_GTADTBRB_Pos      (0UL)          /*!< GTADTBRB (Bit 0)                                      */
23187  #define R_GPT0_GTADTBRB_GTADTBRB_Msk      (0xffffffffUL) /*!< GTADTBRB (Bitfield-Mask: 0xffffffff)                  */
23188 /* =======================================================  GTADTDBRA  ======================================================= */
23189  #define R_GPT0_GTADTDBRA_GTADTDBRA_Pos    (0UL)          /*!< GTADTDBRA (Bit 0)                                     */
23190  #define R_GPT0_GTADTDBRA_GTADTDBRA_Msk    (0xffffffffUL) /*!< GTADTDBRA (Bitfield-Mask: 0xffffffff)                 */
23191 /* =======================================================  GTADTDBRB  ======================================================= */
23192  #define R_GPT0_GTADTDBRB_GTADTDBRB_Pos    (0UL)          /*!< GTADTDBRB (Bit 0)                                     */
23193  #define R_GPT0_GTADTDBRB_GTADTDBRB_Msk    (0xffffffffUL) /*!< GTADTDBRB (Bitfield-Mask: 0xffffffff)                 */
23194 /* ========================================================  GTDTCR  ========================================================= */
23195  #define R_GPT0_GTDTCR_TDFER_Pos           (8UL)          /*!< TDFER (Bit 8)                                         */
23196  #define R_GPT0_GTDTCR_TDFER_Msk           (0x100UL)      /*!< TDFER (Bitfield-Mask: 0x01)                           */
23197  #define R_GPT0_GTDTCR_TDBDE_Pos           (5UL)          /*!< TDBDE (Bit 5)                                         */
23198  #define R_GPT0_GTDTCR_TDBDE_Msk           (0x20UL)       /*!< TDBDE (Bitfield-Mask: 0x01)                           */
23199  #define R_GPT0_GTDTCR_TDBUE_Pos           (4UL)          /*!< TDBUE (Bit 4)                                         */
23200  #define R_GPT0_GTDTCR_TDBUE_Msk           (0x10UL)       /*!< TDBUE (Bitfield-Mask: 0x01)                           */
23201  #define R_GPT0_GTDTCR_TDE_Pos             (0UL)          /*!< TDE (Bit 0)                                           */
23202  #define R_GPT0_GTDTCR_TDE_Msk             (0x1UL)        /*!< TDE (Bitfield-Mask: 0x01)                             */
23203 /* =========================================================  GTDVU  ========================================================= */
23204  #define R_GPT0_GTDVU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
23205  #define R_GPT0_GTDVU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
23206 /* =========================================================  GTDVD  ========================================================= */
23207  #define R_GPT0_GTDVD_GTDVD_Pos            (0UL)          /*!< GTDVD (Bit 0)                                         */
23208  #define R_GPT0_GTDVD_GTDVD_Msk            (0xffffffffUL) /*!< GTDVD (Bitfield-Mask: 0xffffffff)                     */
23209 /* =========================================================  GTDBU  ========================================================= */
23210  #define R_GPT0_GTDBU_GTDVU_Pos            (0UL)          /*!< GTDVU (Bit 0)                                         */
23211  #define R_GPT0_GTDBU_GTDVU_Msk            (0xffffffffUL) /*!< GTDVU (Bitfield-Mask: 0xffffffff)                     */
23212 /* =========================================================  GTDBD  ========================================================= */
23213  #define R_GPT0_GTDBD_GTDBD_Pos            (0UL)          /*!< GTDBD (Bit 0)                                         */
23214  #define R_GPT0_GTDBD_GTDBD_Msk            (0xffffffffUL) /*!< GTDBD (Bitfield-Mask: 0xffffffff)                     */
23215 /* =========================================================  GTSOS  ========================================================= */
23216  #define R_GPT0_GTSOS_SOS_Pos              (0UL)          /*!< SOS (Bit 0)                                           */
23217  #define R_GPT0_GTSOS_SOS_Msk              (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
23218 /* ========================================================  GTSOTR  ========================================================= */
23219  #define R_GPT0_GTSOTR_SOTR_Pos            (0UL)          /*!< SOTR (Bit 0)                                          */
23220  #define R_GPT0_GTSOTR_SOTR_Msk            (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
23221 /* ========================================================  GTADSMR  ======================================================== */
23222  #define R_GPT0_GTADSMR_ADSMS0_Pos         (0UL)          /*!< ADSMS0 (Bit 0)                                        */
23223  #define R_GPT0_GTADSMR_ADSMS0_Msk         (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
23224  #define R_GPT0_GTADSMR_ADSMEN0_Pos        (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
23225  #define R_GPT0_GTADSMR_ADSMEN0_Msk        (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
23226  #define R_GPT0_GTADSMR_ADSMS1_Pos         (16UL)         /*!< ADSMS1 (Bit 16)                                       */
23227  #define R_GPT0_GTADSMR_ADSMS1_Msk         (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
23228  #define R_GPT0_GTADSMR_ADSMEN1_Pos        (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
23229  #define R_GPT0_GTADSMR_ADSMEN1_Msk        (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
23230 /* ========================================================  GTEITC  ========================================================= */
23231  #define R_GPT0_GTEITC_EIVTC1_Pos          (0UL)          /*!< EIVTC1 (Bit 0)                                        */
23232  #define R_GPT0_GTEITC_EIVTC1_Msk          (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
23233  #define R_GPT0_GTEITC_EIVTT1_Pos          (4UL)          /*!< EIVTT1 (Bit 4)                                        */
23234  #define R_GPT0_GTEITC_EIVTT1_Msk          (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
23235  #define R_GPT0_GTEITC_EITCNT1_Pos         (12UL)         /*!< EITCNT1 (Bit 12)                                      */
23236  #define R_GPT0_GTEITC_EITCNT1_Msk         (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
23237  #define R_GPT0_GTEITC_EIVTC2_Pos          (16UL)         /*!< EIVTC2 (Bit 16)                                       */
23238  #define R_GPT0_GTEITC_EIVTC2_Msk          (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
23239  #define R_GPT0_GTEITC_EIVTT2_Pos          (20UL)         /*!< EIVTT2 (Bit 20)                                       */
23240  #define R_GPT0_GTEITC_EIVTT2_Msk          (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
23241  #define R_GPT0_GTEITC_EITCNT2IV_Pos       (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
23242  #define R_GPT0_GTEITC_EITCNT2IV_Msk       (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
23243  #define R_GPT0_GTEITC_EITCNT2_Pos         (28UL)         /*!< EITCNT2 (Bit 28)                                      */
23244  #define R_GPT0_GTEITC_EITCNT2_Msk         (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
23245 /* =======================================================  GTEITLI1  ======================================================== */
23246  #define R_GPT0_GTEITLI1_EITLA_Pos         (0UL)          /*!< EITLA (Bit 0)                                         */
23247  #define R_GPT0_GTEITLI1_EITLA_Msk         (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
23248  #define R_GPT0_GTEITLI1_EITLB_Pos         (4UL)          /*!< EITLB (Bit 4)                                         */
23249  #define R_GPT0_GTEITLI1_EITLB_Msk         (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
23250  #define R_GPT0_GTEITLI1_EITLC_Pos         (8UL)          /*!< EITLC (Bit 8)                                         */
23251  #define R_GPT0_GTEITLI1_EITLC_Msk         (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
23252  #define R_GPT0_GTEITLI1_EITLD_Pos         (12UL)         /*!< EITLD (Bit 12)                                        */
23253  #define R_GPT0_GTEITLI1_EITLD_Msk         (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
23254  #define R_GPT0_GTEITLI1_EITLE_Pos         (16UL)         /*!< EITLE (Bit 16)                                        */
23255  #define R_GPT0_GTEITLI1_EITLE_Msk         (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
23256  #define R_GPT0_GTEITLI1_EITLF_Pos         (20UL)         /*!< EITLF (Bit 20)                                        */
23257  #define R_GPT0_GTEITLI1_EITLF_Msk         (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
23258  #define R_GPT0_GTEITLI1_EITLV_Pos         (24UL)         /*!< EITLV (Bit 24)                                        */
23259  #define R_GPT0_GTEITLI1_EITLV_Msk         (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
23260  #define R_GPT0_GTEITLI1_EITLU_Pos         (28UL)         /*!< EITLU (Bit 28)                                        */
23261  #define R_GPT0_GTEITLI1_EITLU_Msk         (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
23262 /* =======================================================  GTEITLI2  ======================================================== */
23263  #define R_GPT0_GTEITLI2_EADTAL_Pos        (0UL)          /*!< EADTAL (Bit 0)                                        */
23264  #define R_GPT0_GTEITLI2_EADTAL_Msk        (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
23265  #define R_GPT0_GTEITLI2_EADTBL_Pos        (4UL)          /*!< EADTBL (Bit 4)                                        */
23266  #define R_GPT0_GTEITLI2_EADTBL_Msk        (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
23267 /* ========================================================  GTEITLB  ======================================================== */
23268  #define R_GPT0_GTEITLB_EBTLCA_Pos         (0UL)          /*!< EBTLCA (Bit 0)                                        */
23269  #define R_GPT0_GTEITLB_EBTLCA_Msk         (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
23270  #define R_GPT0_GTEITLB_EBTLCB_Pos         (4UL)          /*!< EBTLCB (Bit 4)                                        */
23271  #define R_GPT0_GTEITLB_EBTLCB_Msk         (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
23272  #define R_GPT0_GTEITLB_EBTLPR_Pos         (8UL)          /*!< EBTLPR (Bit 8)                                        */
23273  #define R_GPT0_GTEITLB_EBTLPR_Msk         (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
23274  #define R_GPT0_GTEITLB_EBTLADA_Pos        (16UL)         /*!< EBTLADA (Bit 16)                                      */
23275  #define R_GPT0_GTEITLB_EBTLADA_Msk        (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
23276  #define R_GPT0_GTEITLB_EBTLADB_Pos        (20UL)         /*!< EBTLADB (Bit 20)                                      */
23277  #define R_GPT0_GTEITLB_EBTLADB_Msk        (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
23278  #define R_GPT0_GTEITLB_EBTLDVU_Pos        (24UL)         /*!< EBTLDVU (Bit 24)                                      */
23279  #define R_GPT0_GTEITLB_EBTLDVU_Msk        (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
23280  #define R_GPT0_GTEITLB_EBTLDVD_Pos        (28UL)         /*!< EBTLDVD (Bit 28)                                      */
23281  #define R_GPT0_GTEITLB_EBTLDVD_Msk        (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
23282 /* ========================================================  GTICLF  ========================================================= */
23283  #define R_GPT0_GTICLF_ICLFA_Pos           (0UL)          /*!< ICLFA (Bit 0)                                         */
23284  #define R_GPT0_GTICLF_ICLFA_Msk           (0x7UL)        /*!< ICLFA (Bitfield-Mask: 0x07)                           */
23285  #define R_GPT0_GTICLF_ICLFSELC_Pos        (4UL)          /*!< ICLFSELC (Bit 4)                                      */
23286  #define R_GPT0_GTICLF_ICLFSELC_Msk        (0x3f0UL)      /*!< ICLFSELC (Bitfield-Mask: 0x3f)                        */
23287  #define R_GPT0_GTICLF_ICLFB_Pos           (16UL)         /*!< ICLFB (Bit 16)                                        */
23288  #define R_GPT0_GTICLF_ICLFB_Msk           (0x70000UL)    /*!< ICLFB (Bitfield-Mask: 0x07)                           */
23289  #define R_GPT0_GTICLF_ICLFSELD_Pos        (20UL)         /*!< ICLFSELD (Bit 20)                                     */
23290  #define R_GPT0_GTICLF_ICLFSELD_Msk        (0x3f00000UL)  /*!< ICLFSELD (Bitfield-Mask: 0x3f)                        */
23291 /* =========================================================  GTPC  ========================================================== */
23292  #define R_GPT0_GTPC_PCEN_Pos              (0UL)          /*!< PCEN (Bit 0)                                          */
23293  #define R_GPT0_GTPC_PCEN_Msk              (0x1UL)        /*!< PCEN (Bitfield-Mask: 0x01)                            */
23294  #define R_GPT0_GTPC_ASTP_Pos              (8UL)          /*!< ASTP (Bit 8)                                          */
23295  #define R_GPT0_GTPC_ASTP_Msk              (0x100UL)      /*!< ASTP (Bitfield-Mask: 0x01)                            */
23296  #define R_GPT0_GTPC_PCNT_Pos              (16UL)         /*!< PCNT (Bit 16)                                         */
23297  #define R_GPT0_GTPC_PCNT_Msk              (0xfff0000UL)  /*!< PCNT (Bitfield-Mask: 0xfff)                           */
23298 /* ========================================================  GTSECSR  ======================================================== */
23299  #define R_GPT0_GTSECSR_SECSEL0_Pos        (0UL)          /*!< SECSEL0 (Bit 0)                                       */
23300  #define R_GPT0_GTSECSR_SECSEL0_Msk        (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
23301  #define R_GPT0_GTSECSR_SECSEL1_Pos        (1UL)          /*!< SECSEL1 (Bit 1)                                       */
23302  #define R_GPT0_GTSECSR_SECSEL1_Msk        (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
23303  #define R_GPT0_GTSECSR_SECSEL2_Pos        (2UL)          /*!< SECSEL2 (Bit 2)                                       */
23304  #define R_GPT0_GTSECSR_SECSEL2_Msk        (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
23305  #define R_GPT0_GTSECSR_SECSEL3_Pos        (3UL)          /*!< SECSEL3 (Bit 3)                                       */
23306  #define R_GPT0_GTSECSR_SECSEL3_Msk        (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
23307  #define R_GPT0_GTSECSR_SECSEL4_Pos        (4UL)          /*!< SECSEL4 (Bit 4)                                       */
23308  #define R_GPT0_GTSECSR_SECSEL4_Msk        (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
23309  #define R_GPT0_GTSECSR_SECSEL5_Pos        (5UL)          /*!< SECSEL5 (Bit 5)                                       */
23310  #define R_GPT0_GTSECSR_SECSEL5_Msk        (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
23311  #define R_GPT0_GTSECSR_SECSEL6_Pos        (6UL)          /*!< SECSEL6 (Bit 6)                                       */
23312  #define R_GPT0_GTSECSR_SECSEL6_Msk        (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
23313  #define R_GPT0_GTSECSR_SECSEL7_Pos        (7UL)          /*!< SECSEL7 (Bit 7)                                       */
23314  #define R_GPT0_GTSECSR_SECSEL7_Msk        (0x80UL)       /*!< SECSEL7 (Bitfield-Mask: 0x01)                         */
23315  #define R_GPT0_GTSECSR_SECSEL8_Pos        (8UL)          /*!< SECSEL8 (Bit 8)                                       */
23316  #define R_GPT0_GTSECSR_SECSEL8_Msk        (0x100UL)      /*!< SECSEL8 (Bitfield-Mask: 0x01)                         */
23317  #define R_GPT0_GTSECSR_SECSEL9_Pos        (9UL)          /*!< SECSEL9 (Bit 9)                                       */
23318  #define R_GPT0_GTSECSR_SECSEL9_Msk        (0x200UL)      /*!< SECSEL9 (Bitfield-Mask: 0x01)                         */
23319 /* ========================================================  GTSECR  ========================================================= */
23320  #define R_GPT0_GTSECR_SBDCE_Pos           (0UL)          /*!< SBDCE (Bit 0)                                         */
23321  #define R_GPT0_GTSECR_SBDCE_Msk           (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
23322  #define R_GPT0_GTSECR_SBDPE_Pos           (1UL)          /*!< SBDPE (Bit 1)                                         */
23323  #define R_GPT0_GTSECR_SBDPE_Msk           (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
23324  #define R_GPT0_GTSECR_SBDAE_Pos           (2UL)          /*!< SBDAE (Bit 2)                                         */
23325  #define R_GPT0_GTSECR_SBDAE_Msk           (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
23326  #define R_GPT0_GTSECR_SBDDE_Pos           (3UL)          /*!< SBDDE (Bit 3)                                         */
23327  #define R_GPT0_GTSECR_SBDDE_Msk           (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
23328  #define R_GPT0_GTSECR_SBDCD_Pos           (8UL)          /*!< SBDCD (Bit 8)                                         */
23329  #define R_GPT0_GTSECR_SBDCD_Msk           (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
23330  #define R_GPT0_GTSECR_SBDPD_Pos           (9UL)          /*!< SBDPD (Bit 9)                                         */
23331  #define R_GPT0_GTSECR_SBDPD_Msk           (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
23332  #define R_GPT0_GTSECR_SBDAD_Pos           (10UL)         /*!< SBDAD (Bit 10)                                        */
23333  #define R_GPT0_GTSECR_SBDAD_Msk           (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
23334  #define R_GPT0_GTSECR_SBDDD_Pos           (11UL)         /*!< SBDDD (Bit 11)                                        */
23335  #define R_GPT0_GTSECR_SBDDD_Msk           (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
23336  #define R_GPT0_GTSECR_SPCE_Pos            (16UL)         /*!< SPCE (Bit 16)                                         */
23337  #define R_GPT0_GTSECR_SPCE_Msk            (0x10000UL)    /*!< SPCE (Bitfield-Mask: 0x01)                            */
23338  #define R_GPT0_GTSECR_SSCE_Pos            (17UL)         /*!< SSCE (Bit 17)                                         */
23339  #define R_GPT0_GTSECR_SSCE_Msk            (0x20000UL)    /*!< SSCE (Bitfield-Mask: 0x01)                            */
23340  #define R_GPT0_GTSECR_SPCD_Pos            (24UL)         /*!< SPCD (Bit 24)                                         */
23341  #define R_GPT0_GTSECR_SPCD_Msk            (0x1000000UL)  /*!< SPCD (Bitfield-Mask: 0x01)                            */
23342  #define R_GPT0_GTSECR_SSCD_Pos            (25UL)         /*!< SSCD (Bit 25)                                         */
23343  #define R_GPT0_GTSECR_SSCD_Msk            (0x2000000UL)  /*!< SSCD (Bitfield-Mask: 0x01)                            */
23344 /* ========================================================  GTBER2  ========================================================= */
23345  #define R_GPT0_GTBER2_CCTCA_Pos           (0UL)          /*!< CCTCA (Bit 0)                                         */
23346  #define R_GPT0_GTBER2_CCTCA_Msk           (0x1UL)        /*!< CCTCA (Bitfield-Mask: 0x01)                           */
23347  #define R_GPT0_GTBER2_CCTCB_Pos           (1UL)          /*!< CCTCB (Bit 1)                                         */
23348  #define R_GPT0_GTBER2_CCTCB_Msk           (0x2UL)        /*!< CCTCB (Bitfield-Mask: 0x01)                           */
23349  #define R_GPT0_GTBER2_CCTPR_Pos           (2UL)          /*!< CCTPR (Bit 2)                                         */
23350  #define R_GPT0_GTBER2_CCTPR_Msk           (0x4UL)        /*!< CCTPR (Bitfield-Mask: 0x01)                           */
23351  #define R_GPT0_GTBER2_CCTADA_Pos          (3UL)          /*!< CCTADA (Bit 3)                                        */
23352  #define R_GPT0_GTBER2_CCTADA_Msk          (0x8UL)        /*!< CCTADA (Bitfield-Mask: 0x01)                          */
23353  #define R_GPT0_GTBER2_CCTADB_Pos          (4UL)          /*!< CCTADB (Bit 4)                                        */
23354  #define R_GPT0_GTBER2_CCTADB_Msk          (0x10UL)       /*!< CCTADB (Bitfield-Mask: 0x01)                          */
23355  #define R_GPT0_GTBER2_CCTDV_Pos           (5UL)          /*!< CCTDV (Bit 5)                                         */
23356  #define R_GPT0_GTBER2_CCTDV_Msk           (0x20UL)       /*!< CCTDV (Bitfield-Mask: 0x01)                           */
23357  #define R_GPT0_GTBER2_CMTCA_Pos           (8UL)          /*!< CMTCA (Bit 8)                                         */
23358  #define R_GPT0_GTBER2_CMTCA_Msk           (0x300UL)      /*!< CMTCA (Bitfield-Mask: 0x03)                           */
23359  #define R_GPT0_GTBER2_CMTCB_Pos           (10UL)         /*!< CMTCB (Bit 10)                                        */
23360  #define R_GPT0_GTBER2_CMTCB_Msk           (0xc00UL)      /*!< CMTCB (Bitfield-Mask: 0x03)                           */
23361  #define R_GPT0_GTBER2_CMTADA_Pos          (13UL)         /*!< CMTADA (Bit 13)                                       */
23362  #define R_GPT0_GTBER2_CMTADA_Msk          (0x2000UL)     /*!< CMTADA (Bitfield-Mask: 0x01)                          */
23363  #define R_GPT0_GTBER2_CMTADB_Pos          (14UL)         /*!< CMTADB (Bit 14)                                       */
23364  #define R_GPT0_GTBER2_CMTADB_Msk          (0x4000UL)     /*!< CMTADB (Bitfield-Mask: 0x01)                          */
23365  #define R_GPT0_GTBER2_CPTCA_Pos           (16UL)         /*!< CPTCA (Bit 16)                                        */
23366  #define R_GPT0_GTBER2_CPTCA_Msk           (0x10000UL)    /*!< CPTCA (Bitfield-Mask: 0x01)                           */
23367  #define R_GPT0_GTBER2_CPTCB_Pos           (17UL)         /*!< CPTCB (Bit 17)                                        */
23368  #define R_GPT0_GTBER2_CPTCB_Msk           (0x20000UL)    /*!< CPTCB (Bitfield-Mask: 0x01)                           */
23369  #define R_GPT0_GTBER2_CPTPR_Pos           (18UL)         /*!< CPTPR (Bit 18)                                        */
23370  #define R_GPT0_GTBER2_CPTPR_Msk           (0x40000UL)    /*!< CPTPR (Bitfield-Mask: 0x01)                           */
23371  #define R_GPT0_GTBER2_CPTADA_Pos          (19UL)         /*!< CPTADA (Bit 19)                                       */
23372  #define R_GPT0_GTBER2_CPTADA_Msk          (0x80000UL)    /*!< CPTADA (Bitfield-Mask: 0x01)                          */
23373  #define R_GPT0_GTBER2_CPTADB_Pos          (20UL)         /*!< CPTADB (Bit 20)                                       */
23374  #define R_GPT0_GTBER2_CPTADB_Msk          (0x100000UL)   /*!< CPTADB (Bitfield-Mask: 0x01)                          */
23375  #define R_GPT0_GTBER2_CPTDV_Pos           (21UL)         /*!< CPTDV (Bit 21)                                        */
23376  #define R_GPT0_GTBER2_CPTDV_Msk           (0x200000UL)   /*!< CPTDV (Bitfield-Mask: 0x01)                           */
23377  #define R_GPT0_GTBER2_CP3DB_Pos           (24UL)         /*!< CP3DB (Bit 24)                                        */
23378  #define R_GPT0_GTBER2_CP3DB_Msk           (0x1000000UL)  /*!< CP3DB (Bitfield-Mask: 0x01)                           */
23379  #define R_GPT0_GTBER2_CPBTD_Pos           (25UL)         /*!< CPBTD (Bit 25)                                        */
23380  #define R_GPT0_GTBER2_CPBTD_Msk           (0x2000000UL)  /*!< CPBTD (Bitfield-Mask: 0x01)                           */
23381  #define R_GPT0_GTBER2_OLTTA_Pos           (26UL)         /*!< OLTTA (Bit 26)                                        */
23382  #define R_GPT0_GTBER2_OLTTA_Msk           (0xc000000UL)  /*!< OLTTA (Bitfield-Mask: 0x03)                           */
23383  #define R_GPT0_GTBER2_OLTTB_Pos           (28UL)         /*!< OLTTB (Bit 28)                                        */
23384  #define R_GPT0_GTBER2_OLTTB_Msk           (0x30000000UL) /*!< OLTTB (Bitfield-Mask: 0x03)                           */
23385 /* ========================================================  GTOLBR  ========================================================= */
23386  #define R_GPT0_GTOLBR_GTIOAB_Pos          (0UL)          /*!< GTIOAB (Bit 0)                                        */
23387  #define R_GPT0_GTOLBR_GTIOAB_Msk          (0x1fUL)       /*!< GTIOAB (Bitfield-Mask: 0x1f)                          */
23388  #define R_GPT0_GTOLBR_GTIOBB_Pos          (16UL)         /*!< GTIOBB (Bit 16)                                       */
23389  #define R_GPT0_GTOLBR_GTIOBB_Msk          (0x1f0000UL)   /*!< GTIOBB (Bitfield-Mask: 0x1f)                          */
23390 /* ========================================================  GTICCR  ========================================================= */
23391  #define R_GPT0_GTICCR_ICAFA_Pos           (0UL)          /*!< ICAFA (Bit 0)                                         */
23392  #define R_GPT0_GTICCR_ICAFA_Msk           (0x1UL)        /*!< ICAFA (Bitfield-Mask: 0x01)                           */
23393  #define R_GPT0_GTICCR_ICAFB_Pos           (1UL)          /*!< ICAFB (Bit 1)                                         */
23394  #define R_GPT0_GTICCR_ICAFB_Msk           (0x2UL)        /*!< ICAFB (Bitfield-Mask: 0x01)                           */
23395  #define R_GPT0_GTICCR_ICAFC_Pos           (2UL)          /*!< ICAFC (Bit 2)                                         */
23396  #define R_GPT0_GTICCR_ICAFC_Msk           (0x4UL)        /*!< ICAFC (Bitfield-Mask: 0x01)                           */
23397  #define R_GPT0_GTICCR_ICAFD_Pos           (3UL)          /*!< ICAFD (Bit 3)                                         */
23398  #define R_GPT0_GTICCR_ICAFD_Msk           (0x8UL)        /*!< ICAFD (Bitfield-Mask: 0x01)                           */
23399  #define R_GPT0_GTICCR_ICAFE_Pos           (4UL)          /*!< ICAFE (Bit 4)                                         */
23400  #define R_GPT0_GTICCR_ICAFE_Msk           (0x10UL)       /*!< ICAFE (Bitfield-Mask: 0x01)                           */
23401  #define R_GPT0_GTICCR_ICAFF_Pos           (5UL)          /*!< ICAFF (Bit 5)                                         */
23402  #define R_GPT0_GTICCR_ICAFF_Msk           (0x20UL)       /*!< ICAFF (Bitfield-Mask: 0x01)                           */
23403  #define R_GPT0_GTICCR_ICAFPO_Pos          (6UL)          /*!< ICAFPO (Bit 6)                                        */
23404  #define R_GPT0_GTICCR_ICAFPO_Msk          (0x40UL)       /*!< ICAFPO (Bitfield-Mask: 0x01)                          */
23405  #define R_GPT0_GTICCR_ICAFPU_Pos          (7UL)          /*!< ICAFPU (Bit 7)                                        */
23406  #define R_GPT0_GTICCR_ICAFPU_Msk          (0x80UL)       /*!< ICAFPU (Bitfield-Mask: 0x01)                          */
23407  #define R_GPT0_GTICCR_ICACLK_Pos          (8UL)          /*!< ICACLK (Bit 8)                                        */
23408  #define R_GPT0_GTICCR_ICACLK_Msk          (0x100UL)      /*!< ICACLK (Bitfield-Mask: 0x01)                          */
23409  #define R_GPT0_GTICCR_ICAGRP_Pos          (14UL)         /*!< ICAGRP (Bit 14)                                       */
23410  #define R_GPT0_GTICCR_ICAGRP_Msk          (0xc000UL)     /*!< ICAGRP (Bitfield-Mask: 0x03)                          */
23411  #define R_GPT0_GTICCR_ICBFA_Pos           (16UL)         /*!< ICBFA (Bit 16)                                        */
23412  #define R_GPT0_GTICCR_ICBFA_Msk           (0x10000UL)    /*!< ICBFA (Bitfield-Mask: 0x01)                           */
23413  #define R_GPT0_GTICCR_ICBFB_Pos           (17UL)         /*!< ICBFB (Bit 17)                                        */
23414  #define R_GPT0_GTICCR_ICBFB_Msk           (0x20000UL)    /*!< ICBFB (Bitfield-Mask: 0x01)                           */
23415  #define R_GPT0_GTICCR_ICBFC_Pos           (18UL)         /*!< ICBFC (Bit 18)                                        */
23416  #define R_GPT0_GTICCR_ICBFC_Msk           (0x40000UL)    /*!< ICBFC (Bitfield-Mask: 0x01)                           */
23417  #define R_GPT0_GTICCR_ICBFD_Pos           (19UL)         /*!< ICBFD (Bit 19)                                        */
23418  #define R_GPT0_GTICCR_ICBFD_Msk           (0x80000UL)    /*!< ICBFD (Bitfield-Mask: 0x01)                           */
23419  #define R_GPT0_GTICCR_ICBFE_Pos           (20UL)         /*!< ICBFE (Bit 20)                                        */
23420  #define R_GPT0_GTICCR_ICBFE_Msk           (0x100000UL)   /*!< ICBFE (Bitfield-Mask: 0x01)                           */
23421  #define R_GPT0_GTICCR_ICBFF_Pos           (21UL)         /*!< ICBFF (Bit 21)                                        */
23422  #define R_GPT0_GTICCR_ICBFF_Msk           (0x200000UL)   /*!< ICBFF (Bitfield-Mask: 0x01)                           */
23423  #define R_GPT0_GTICCR_ICBFPO_Pos          (22UL)         /*!< ICBFPO (Bit 22)                                       */
23424  #define R_GPT0_GTICCR_ICBFPO_Msk          (0x400000UL)   /*!< ICBFPO (Bitfield-Mask: 0x01)                          */
23425  #define R_GPT0_GTICCR_ICBFPU_Pos          (23UL)         /*!< ICBFPU (Bit 23)                                       */
23426  #define R_GPT0_GTICCR_ICBFPU_Msk          (0x800000UL)   /*!< ICBFPU (Bitfield-Mask: 0x01)                          */
23427  #define R_GPT0_GTICCR_ICBCLK_Pos          (24UL)         /*!< ICBCLK (Bit 24)                                       */
23428  #define R_GPT0_GTICCR_ICBCLK_Msk          (0x1000000UL)  /*!< ICBCLK (Bitfield-Mask: 0x01)                          */
23429  #define R_GPT0_GTICCR_ICBGRP_Pos          (30UL)         /*!< ICBGRP (Bit 30)                                       */
23430  #define R_GPT0_GTICCR_ICBGRP_Msk          (0xc0000000UL) /*!< ICBGRP (Bitfield-Mask: 0x03)                          */
23431 
23432 /* =========================================================================================================================== */
23433 /* ================                                         R_GPT_OPS                                         ================ */
23434 /* =========================================================================================================================== */
23435 
23436 /* =========================================================  OPSCR  ========================================================= */
23437  #define R_GPT_OPS_OPSCR_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
23438  #define R_GPT_OPS_OPSCR_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
23439  #define R_GPT_OPS_OPSCR_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
23440  #define R_GPT_OPS_OPSCR_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
23441  #define R_GPT_OPS_OPSCR_GODF_Pos     (26UL)         /*!< GODF (Bit 26)                                         */
23442  #define R_GPT_OPS_OPSCR_GODF_Msk     (0x4000000UL)  /*!< GODF (Bitfield-Mask: 0x01)                            */
23443  #define R_GPT_OPS_OPSCR_GRP_Pos      (24UL)         /*!< GRP (Bit 24)                                          */
23444  #define R_GPT_OPS_OPSCR_GRP_Msk      (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
23445  #define R_GPT_OPS_OPSCR_ALIGN_Pos    (21UL)         /*!< ALIGN (Bit 21)                                        */
23446  #define R_GPT_OPS_OPSCR_ALIGN_Msk    (0x200000UL)   /*!< ALIGN (Bitfield-Mask: 0x01)                           */
23447  #define R_GPT_OPS_OPSCR_RV_Pos       (20UL)         /*!< RV (Bit 20)                                           */
23448  #define R_GPT_OPS_OPSCR_RV_Msk       (0x100000UL)   /*!< RV (Bitfield-Mask: 0x01)                              */
23449  #define R_GPT_OPS_OPSCR_INV_Pos      (19UL)         /*!< INV (Bit 19)                                          */
23450  #define R_GPT_OPS_OPSCR_INV_Msk      (0x80000UL)    /*!< INV (Bitfield-Mask: 0x01)                             */
23451  #define R_GPT_OPS_OPSCR_N_Pos        (18UL)         /*!< N (Bit 18)                                            */
23452  #define R_GPT_OPS_OPSCR_N_Msk        (0x40000UL)    /*!< N (Bitfield-Mask: 0x01)                               */
23453  #define R_GPT_OPS_OPSCR_P_Pos        (17UL)         /*!< P (Bit 17)                                            */
23454  #define R_GPT_OPS_OPSCR_P_Msk        (0x20000UL)    /*!< P (Bitfield-Mask: 0x01)                               */
23455  #define R_GPT_OPS_OPSCR_FB_Pos       (16UL)         /*!< FB (Bit 16)                                           */
23456  #define R_GPT_OPS_OPSCR_FB_Msk       (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
23457  #define R_GPT_OPS_OPSCR_EN_Pos       (8UL)          /*!< EN (Bit 8)                                            */
23458  #define R_GPT_OPS_OPSCR_EN_Msk       (0x100UL)      /*!< EN (Bitfield-Mask: 0x01)                              */
23459  #define R_GPT_OPS_OPSCR_W_Pos        (6UL)          /*!< W (Bit 6)                                             */
23460  #define R_GPT_OPS_OPSCR_W_Msk        (0x40UL)       /*!< W (Bitfield-Mask: 0x01)                               */
23461  #define R_GPT_OPS_OPSCR_V_Pos        (5UL)          /*!< V (Bit 5)                                             */
23462  #define R_GPT_OPS_OPSCR_V_Msk        (0x20UL)       /*!< V (Bitfield-Mask: 0x01)                               */
23463  #define R_GPT_OPS_OPSCR_U_Pos        (4UL)          /*!< U (Bit 4)                                             */
23464  #define R_GPT_OPS_OPSCR_U_Msk        (0x10UL)       /*!< U (Bitfield-Mask: 0x01)                               */
23465  #define R_GPT_OPS_OPSCR_WF_Pos       (2UL)          /*!< WF (Bit 2)                                            */
23466  #define R_GPT_OPS_OPSCR_WF_Msk       (0x4UL)        /*!< WF (Bitfield-Mask: 0x01)                              */
23467  #define R_GPT_OPS_OPSCR_VF_Pos       (1UL)          /*!< VF (Bit 1)                                            */
23468  #define R_GPT_OPS_OPSCR_VF_Msk       (0x2UL)        /*!< VF (Bitfield-Mask: 0x01)                              */
23469  #define R_GPT_OPS_OPSCR_UF_Pos       (0UL)          /*!< UF (Bit 0)                                            */
23470  #define R_GPT_OPS_OPSCR_UF_Msk       (0x1UL)        /*!< UF (Bitfield-Mask: 0x01)                              */
23471 
23472 /* =========================================================================================================================== */
23473 /* ================                                        R_GPT_POEG0                                        ================ */
23474 /* =========================================================================================================================== */
23475 
23476 /* =========================================================  POEGG  ========================================================= */
23477  #define R_GPT_POEG0_POEGG_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
23478  #define R_GPT_POEG0_POEGG_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
23479  #define R_GPT_POEG0_POEGG_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
23480  #define R_GPT_POEG0_POEGG_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
23481  #define R_GPT_POEG0_POEGG_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
23482  #define R_GPT_POEG0_POEGG_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
23483  #define R_GPT_POEG0_POEGG_DERRE_Pos      (26UL)         /*!< DERRE (Bit 26)                                        */
23484  #define R_GPT_POEG0_POEGG_DERRE_Msk      (0x4000000UL)  /*!< DERRE (Bitfield-Mask: 0x01)                           */
23485  #define R_GPT_POEG0_POEGG_DERRST_Pos     (24UL)         /*!< DERRST (Bit 24)                                       */
23486  #define R_GPT_POEG0_POEGG_DERRST_Msk     (0x1000000UL)  /*!< DERRST (Bitfield-Mask: 0x01)                          */
23487  #define R_GPT_POEG0_POEGG_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
23488  #define R_GPT_POEG0_POEGG_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
23489  #define R_GPT_POEG0_POEGG_CDRE_Pos       (8UL)          /*!< CDRE (Bit 8)                                          */
23490  #define R_GPT_POEG0_POEGG_CDRE_Msk       (0x100UL)      /*!< CDRE (Bitfield-Mask: 0x01)                            */
23491  #define R_GPT_POEG0_POEGG_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
23492  #define R_GPT_POEG0_POEGG_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
23493  #define R_GPT_POEG0_POEGG_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
23494  #define R_GPT_POEG0_POEGG_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
23495  #define R_GPT_POEG0_POEGG_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
23496  #define R_GPT_POEG0_POEGG_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
23497  #define R_GPT_POEG0_POEGG_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
23498  #define R_GPT_POEG0_POEGG_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
23499  #define R_GPT_POEG0_POEGG_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
23500  #define R_GPT_POEG0_POEGG_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
23501  #define R_GPT_POEG0_POEGG_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
23502  #define R_GPT_POEG0_POEGG_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
23503  #define R_GPT_POEG0_POEGG_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
23504  #define R_GPT_POEG0_POEGG_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
23505 /* ========================================================  GTONCWP  ======================================================== */
23506  #define R_GPT_POEG0_GTONCWP_WP_Pos       (0UL)          /*!< WP (Bit 0)                                            */
23507  #define R_GPT_POEG0_GTONCWP_WP_Msk       (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
23508  #define R_GPT_POEG0_GTONCWP_PRKEY_Pos    (8UL)          /*!< PRKEY (Bit 8)                                         */
23509  #define R_GPT_POEG0_GTONCWP_PRKEY_Msk    (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
23510 /* ========================================================  GTONCCR  ======================================================== */
23511  #define R_GPT_POEG0_GTONCCR_NE_Pos       (0UL)          /*!< NE (Bit 0)                                            */
23512  #define R_GPT_POEG0_GTONCCR_NE_Msk       (0x1UL)        /*!< NE (Bitfield-Mask: 0x01)                              */
23513  #define R_GPT_POEG0_GTONCCR_NFS_Pos      (4UL)          /*!< NFS (Bit 4)                                           */
23514  #define R_GPT_POEG0_GTONCCR_NFS_Msk      (0xf0UL)       /*!< NFS (Bitfield-Mask: 0x0f)                             */
23515  #define R_GPT_POEG0_GTONCCR_NFV_Pos      (8UL)          /*!< NFV (Bit 8)                                           */
23516  #define R_GPT_POEG0_GTONCCR_NFV_Msk      (0x100UL)      /*!< NFV (Bitfield-Mask: 0x01)                             */
23517 
23518 /* =========================================================================================================================== */
23519 /* ================                                           R_ICU                                           ================ */
23520 /* =========================================================================================================================== */
23521 
23522 /* =========================================================  IRQCR  ========================================================= */
23523  #define R_ICU_IRQCR_FLTEN_Pos           (7UL)          /*!< FLTEN (Bit 7)                                         */
23524  #define R_ICU_IRQCR_FLTEN_Msk           (0x80UL)       /*!< FLTEN (Bitfield-Mask: 0x01)                           */
23525  #define R_ICU_IRQCR_FCLKSEL_Pos         (4UL)          /*!< FCLKSEL (Bit 4)                                       */
23526  #define R_ICU_IRQCR_FCLKSEL_Msk         (0x30UL)       /*!< FCLKSEL (Bitfield-Mask: 0x03)                         */
23527  #define R_ICU_IRQCR_IRQMD_Pos           (0UL)          /*!< IRQMD (Bit 0)                                         */
23528  #define R_ICU_IRQCR_IRQMD_Msk           (0x3UL)        /*!< IRQMD (Bitfield-Mask: 0x03)                           */
23529 /* =========================================================  NMISR  ========================================================= */
23530  #define R_ICU_NMISR_SPEST_Pos           (12UL)         /*!< SPEST (Bit 12)                                        */
23531  #define R_ICU_NMISR_SPEST_Msk           (0x1000UL)     /*!< SPEST (Bitfield-Mask: 0x01)                           */
23532  #define R_ICU_NMISR_BUSMST_Pos          (11UL)         /*!< BUSMST (Bit 11)                                       */
23533  #define R_ICU_NMISR_BUSMST_Msk          (0x800UL)      /*!< BUSMST (Bitfield-Mask: 0x01)                          */
23534  #define R_ICU_NMISR_BUSSST_Pos          (10UL)         /*!< BUSSST (Bit 10)                                       */
23535  #define R_ICU_NMISR_BUSSST_Msk          (0x400UL)      /*!< BUSSST (Bitfield-Mask: 0x01)                          */
23536  #define R_ICU_NMISR_RECCST_Pos          (9UL)          /*!< RECCST (Bit 9)                                        */
23537  #define R_ICU_NMISR_RECCST_Msk          (0x200UL)      /*!< RECCST (Bitfield-Mask: 0x01)                          */
23538  #define R_ICU_NMISR_RPEST_Pos           (8UL)          /*!< RPEST (Bit 8)                                         */
23539  #define R_ICU_NMISR_RPEST_Msk           (0x100UL)      /*!< RPEST (Bitfield-Mask: 0x01)                           */
23540  #define R_ICU_NMISR_NMIST_Pos           (7UL)          /*!< NMIST (Bit 7)                                         */
23541  #define R_ICU_NMISR_NMIST_Msk           (0x80UL)       /*!< NMIST (Bitfield-Mask: 0x01)                           */
23542  #define R_ICU_NMISR_OSTST_Pos           (6UL)          /*!< OSTST (Bit 6)                                         */
23543  #define R_ICU_NMISR_OSTST_Msk           (0x40UL)       /*!< OSTST (Bitfield-Mask: 0x01)                           */
23544  #define R_ICU_NMISR_VBATTST_Pos         (4UL)          /*!< VBATTST (Bit 4)                                       */
23545  #define R_ICU_NMISR_VBATTST_Msk         (0x10UL)       /*!< VBATTST (Bitfield-Mask: 0x01)                         */
23546  #define R_ICU_NMISR_LVD2ST_Pos          (3UL)          /*!< LVD2ST (Bit 3)                                        */
23547  #define R_ICU_NMISR_LVD2ST_Msk          (0x8UL)        /*!< LVD2ST (Bitfield-Mask: 0x01)                          */
23548  #define R_ICU_NMISR_LVD1ST_Pos          (2UL)          /*!< LVD1ST (Bit 2)                                        */
23549  #define R_ICU_NMISR_LVD1ST_Msk          (0x4UL)        /*!< LVD1ST (Bitfield-Mask: 0x01)                          */
23550  #define R_ICU_NMISR_WDTST_Pos           (1UL)          /*!< WDTST (Bit 1)                                         */
23551  #define R_ICU_NMISR_WDTST_Msk           (0x2UL)        /*!< WDTST (Bitfield-Mask: 0x01)                           */
23552  #define R_ICU_NMISR_IWDTST_Pos          (0UL)          /*!< IWDTST (Bit 0)                                        */
23553  #define R_ICU_NMISR_IWDTST_Msk          (0x1UL)        /*!< IWDTST (Bitfield-Mask: 0x01)                          */
23554  #define R_ICU_NMISR_TZFST_Pos           (13UL)         /*!< TZFST (Bit 13)                                        */
23555  #define R_ICU_NMISR_TZFST_Msk           (0x2000UL)     /*!< TZFST (Bitfield-Mask: 0x01)                           */
23556  #define R_ICU_NMISR_CPEST_Pos           (15UL)         /*!< CPEST (Bit 15)                                        */
23557  #define R_ICU_NMISR_CPEST_Msk           (0x8000UL)     /*!< CPEST (Bitfield-Mask: 0x01)                           */
23558 /* =========================================================  NMIER  ========================================================= */
23559  #define R_ICU_NMIER_SPEEN_Pos           (12UL)         /*!< SPEEN (Bit 12)                                        */
23560  #define R_ICU_NMIER_SPEEN_Msk           (0x1000UL)     /*!< SPEEN (Bitfield-Mask: 0x01)                           */
23561  #define R_ICU_NMIER_BUSMEN_Pos          (11UL)         /*!< BUSMEN (Bit 11)                                       */
23562  #define R_ICU_NMIER_BUSMEN_Msk          (0x800UL)      /*!< BUSMEN (Bitfield-Mask: 0x01)                          */
23563  #define R_ICU_NMIER_BUSSEN_Pos          (10UL)         /*!< BUSSEN (Bit 10)                                       */
23564  #define R_ICU_NMIER_BUSSEN_Msk          (0x400UL)      /*!< BUSSEN (Bitfield-Mask: 0x01)                          */
23565  #define R_ICU_NMIER_RECCEN_Pos          (9UL)          /*!< RECCEN (Bit 9)                                        */
23566  #define R_ICU_NMIER_RECCEN_Msk          (0x200UL)      /*!< RECCEN (Bitfield-Mask: 0x01)                          */
23567  #define R_ICU_NMIER_RPEEN_Pos           (8UL)          /*!< RPEEN (Bit 8)                                         */
23568  #define R_ICU_NMIER_RPEEN_Msk           (0x100UL)      /*!< RPEEN (Bitfield-Mask: 0x01)                           */
23569  #define R_ICU_NMIER_NMIEN_Pos           (7UL)          /*!< NMIEN (Bit 7)                                         */
23570  #define R_ICU_NMIER_NMIEN_Msk           (0x80UL)       /*!< NMIEN (Bitfield-Mask: 0x01)                           */
23571  #define R_ICU_NMIER_OSTEN_Pos           (6UL)          /*!< OSTEN (Bit 6)                                         */
23572  #define R_ICU_NMIER_OSTEN_Msk           (0x40UL)       /*!< OSTEN (Bitfield-Mask: 0x01)                           */
23573  #define R_ICU_NMIER_VBATTEN_Pos         (4UL)          /*!< VBATTEN (Bit 4)                                       */
23574  #define R_ICU_NMIER_VBATTEN_Msk         (0x10UL)       /*!< VBATTEN (Bitfield-Mask: 0x01)                         */
23575  #define R_ICU_NMIER_LVD2EN_Pos          (3UL)          /*!< LVD2EN (Bit 3)                                        */
23576  #define R_ICU_NMIER_LVD2EN_Msk          (0x8UL)        /*!< LVD2EN (Bitfield-Mask: 0x01)                          */
23577  #define R_ICU_NMIER_LVD1EN_Pos          (2UL)          /*!< LVD1EN (Bit 2)                                        */
23578  #define R_ICU_NMIER_LVD1EN_Msk          (0x4UL)        /*!< LVD1EN (Bitfield-Mask: 0x01)                          */
23579  #define R_ICU_NMIER_WDTEN_Pos           (1UL)          /*!< WDTEN (Bit 1)                                         */
23580  #define R_ICU_NMIER_WDTEN_Msk           (0x2UL)        /*!< WDTEN (Bitfield-Mask: 0x01)                           */
23581  #define R_ICU_NMIER_IWDTEN_Pos          (0UL)          /*!< IWDTEN (Bit 0)                                        */
23582  #define R_ICU_NMIER_IWDTEN_Msk          (0x1UL)        /*!< IWDTEN (Bitfield-Mask: 0x01)                          */
23583  #define R_ICU_NMIER_TZFEN_Pos           (13UL)         /*!< TZFEN (Bit 13)                                        */
23584  #define R_ICU_NMIER_TZFEN_Msk           (0x2000UL)     /*!< TZFEN (Bitfield-Mask: 0x01)                           */
23585  #define R_ICU_NMIER_CPEEN_Pos           (15UL)         /*!< CPEEN (Bit 15)                                        */
23586  #define R_ICU_NMIER_CPEEN_Msk           (0x8000UL)     /*!< CPEEN (Bitfield-Mask: 0x01)                           */
23587 /* ========================================================  NMICLR  ========================================================= */
23588  #define R_ICU_NMICLR_SPECLR_Pos         (12UL)         /*!< SPECLR (Bit 12)                                       */
23589  #define R_ICU_NMICLR_SPECLR_Msk         (0x1000UL)     /*!< SPECLR (Bitfield-Mask: 0x01)                          */
23590  #define R_ICU_NMICLR_BUSMCLR_Pos        (11UL)         /*!< BUSMCLR (Bit 11)                                      */
23591  #define R_ICU_NMICLR_BUSMCLR_Msk        (0x800UL)      /*!< BUSMCLR (Bitfield-Mask: 0x01)                         */
23592  #define R_ICU_NMICLR_BUSSCLR_Pos        (10UL)         /*!< BUSSCLR (Bit 10)                                      */
23593  #define R_ICU_NMICLR_BUSSCLR_Msk        (0x400UL)      /*!< BUSSCLR (Bitfield-Mask: 0x01)                         */
23594  #define R_ICU_NMICLR_RECCCLR_Pos        (9UL)          /*!< RECCCLR (Bit 9)                                       */
23595  #define R_ICU_NMICLR_RECCCLR_Msk        (0x200UL)      /*!< RECCCLR (Bitfield-Mask: 0x01)                         */
23596  #define R_ICU_NMICLR_RPECLR_Pos         (8UL)          /*!< RPECLR (Bit 8)                                        */
23597  #define R_ICU_NMICLR_RPECLR_Msk         (0x100UL)      /*!< RPECLR (Bitfield-Mask: 0x01)                          */
23598  #define R_ICU_NMICLR_NMICLR_Pos         (7UL)          /*!< NMICLR (Bit 7)                                        */
23599  #define R_ICU_NMICLR_NMICLR_Msk         (0x80UL)       /*!< NMICLR (Bitfield-Mask: 0x01)                          */
23600  #define R_ICU_NMICLR_OSTCLR_Pos         (6UL)          /*!< OSTCLR (Bit 6)                                        */
23601  #define R_ICU_NMICLR_OSTCLR_Msk         (0x40UL)       /*!< OSTCLR (Bitfield-Mask: 0x01)                          */
23602  #define R_ICU_NMICLR_VBATTCLR_Pos       (4UL)          /*!< VBATTCLR (Bit 4)                                      */
23603  #define R_ICU_NMICLR_VBATTCLR_Msk       (0x10UL)       /*!< VBATTCLR (Bitfield-Mask: 0x01)                        */
23604  #define R_ICU_NMICLR_LVD2CLR_Pos        (3UL)          /*!< LVD2CLR (Bit 3)                                       */
23605  #define R_ICU_NMICLR_LVD2CLR_Msk        (0x8UL)        /*!< LVD2CLR (Bitfield-Mask: 0x01)                         */
23606  #define R_ICU_NMICLR_LVD1CLR_Pos        (2UL)          /*!< LVD1CLR (Bit 2)                                       */
23607  #define R_ICU_NMICLR_LVD1CLR_Msk        (0x4UL)        /*!< LVD1CLR (Bitfield-Mask: 0x01)                         */
23608  #define R_ICU_NMICLR_WDTCLR_Pos         (1UL)          /*!< WDTCLR (Bit 1)                                        */
23609  #define R_ICU_NMICLR_WDTCLR_Msk         (0x2UL)        /*!< WDTCLR (Bitfield-Mask: 0x01)                          */
23610  #define R_ICU_NMICLR_IWDTCLR_Pos        (0UL)          /*!< IWDTCLR (Bit 0)                                       */
23611  #define R_ICU_NMICLR_IWDTCLR_Msk        (0x1UL)        /*!< IWDTCLR (Bitfield-Mask: 0x01)                         */
23612  #define R_ICU_NMICLR_TZFCLR_Pos         (13UL)         /*!< TZFCLR (Bit 13)                                       */
23613  #define R_ICU_NMICLR_TZFCLR_Msk         (0x2000UL)     /*!< TZFCLR (Bitfield-Mask: 0x01)                          */
23614  #define R_ICU_NMICLR_CPECLR_Pos         (15UL)         /*!< CPECLR (Bit 15)                                       */
23615  #define R_ICU_NMICLR_CPECLR_Msk         (0x8000UL)     /*!< CPECLR (Bitfield-Mask: 0x01)                          */
23616 /* =========================================================  NMICR  ========================================================= */
23617  #define R_ICU_NMICR_NFLTEN_Pos          (7UL)          /*!< NFLTEN (Bit 7)                                        */
23618  #define R_ICU_NMICR_NFLTEN_Msk          (0x80UL)       /*!< NFLTEN (Bitfield-Mask: 0x01)                          */
23619  #define R_ICU_NMICR_NFCLKSEL_Pos        (4UL)          /*!< NFCLKSEL (Bit 4)                                      */
23620  #define R_ICU_NMICR_NFCLKSEL_Msk        (0x30UL)       /*!< NFCLKSEL (Bitfield-Mask: 0x03)                        */
23621  #define R_ICU_NMICR_NMIMD_Pos           (0UL)          /*!< NMIMD (Bit 0)                                         */
23622  #define R_ICU_NMICR_NMIMD_Msk           (0x1UL)        /*!< NMIMD (Bitfield-Mask: 0x01)                           */
23623 /* =========================================================  IELSR  ========================================================= */
23624  #define R_ICU_IELSR_DTCE_Pos            (24UL)         /*!< DTCE (Bit 24)                                         */
23625  #define R_ICU_IELSR_DTCE_Msk            (0x1000000UL)  /*!< DTCE (Bitfield-Mask: 0x01)                            */
23626  #define R_ICU_IELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
23627  #define R_ICU_IELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
23628  #define R_ICU_IELSR_IELS_Pos            (0UL)          /*!< IELS (Bit 0)                                          */
23629  #define R_ICU_IELSR_IELS_Msk            (0x1ffUL)      /*!< IELS (Bitfield-Mask: 0x1ff)                           */
23630 /* =========================================================  DELSR  ========================================================= */
23631  #define R_ICU_DELSR_IR_Pos              (16UL)         /*!< IR (Bit 16)                                           */
23632  #define R_ICU_DELSR_IR_Msk              (0x10000UL)    /*!< IR (Bitfield-Mask: 0x01)                              */
23633  #define R_ICU_DELSR_DELS_Pos            (0UL)          /*!< DELS (Bit 0)                                          */
23634  #define R_ICU_DELSR_DELS_Msk            (0x1ffUL)      /*!< DELS (Bitfield-Mask: 0x1ff)                           */
23635 /* ========================================================  SELSR0  ========================================================= */
23636  #define R_ICU_SELSR0_SELS_Pos           (0UL)          /*!< SELS (Bit 0)                                          */
23637  #define R_ICU_SELSR0_SELS_Msk           (0x1ffUL)      /*!< SELS (Bitfield-Mask: 0x1ff)                           */
23638 /* =========================================================  WUPEN  ========================================================= */
23639  #define R_ICU_WUPEN_IIC0WUPEN_Pos       (31UL)         /*!< IIC0WUPEN (Bit 31)                                    */
23640  #define R_ICU_WUPEN_IIC0WUPEN_Msk       (0x80000000UL) /*!< IIC0WUPEN (Bitfield-Mask: 0x01)                       */
23641  #define R_ICU_WUPEN_AGT1CBWUPEN_Pos     (30UL)         /*!< AGT1CBWUPEN (Bit 30)                                  */
23642  #define R_ICU_WUPEN_AGT1CBWUPEN_Msk     (0x40000000UL) /*!< AGT1CBWUPEN (Bitfield-Mask: 0x01)                     */
23643  #define R_ICU_WUPEN_AGT1CAWUPEN_Pos     (29UL)         /*!< AGT1CAWUPEN (Bit 29)                                  */
23644  #define R_ICU_WUPEN_AGT1CAWUPEN_Msk     (0x20000000UL) /*!< AGT1CAWUPEN (Bitfield-Mask: 0x01)                     */
23645  #define R_ICU_WUPEN_AGT1UDWUPEN_Pos     (28UL)         /*!< AGT1UDWUPEN (Bit 28)                                  */
23646  #define R_ICU_WUPEN_AGT1UDWUPEN_Msk     (0x10000000UL) /*!< AGT1UDWUPEN (Bitfield-Mask: 0x01)                     */
23647  #define R_ICU_WUPEN_USBFSWUPEN_Pos      (27UL)         /*!< USBFSWUPEN (Bit 27)                                   */
23648  #define R_ICU_WUPEN_USBFSWUPEN_Msk      (0x8000000UL)  /*!< USBFSWUPEN (Bitfield-Mask: 0x01)                      */
23649  #define R_ICU_WUPEN_USBHSWUPEN_Pos      (26UL)         /*!< USBHSWUPEN (Bit 26)                                   */
23650  #define R_ICU_WUPEN_USBHSWUPEN_Msk      (0x4000000UL)  /*!< USBHSWUPEN (Bitfield-Mask: 0x01)                      */
23651  #define R_ICU_WUPEN_RTCPRDWUPEN_Pos     (25UL)         /*!< RTCPRDWUPEN (Bit 25)                                  */
23652  #define R_ICU_WUPEN_RTCPRDWUPEN_Msk     (0x2000000UL)  /*!< RTCPRDWUPEN (Bitfield-Mask: 0x01)                     */
23653  #define R_ICU_WUPEN_RTCALMWUPEN_Pos     (24UL)         /*!< RTCALMWUPEN (Bit 24)                                  */
23654  #define R_ICU_WUPEN_RTCALMWUPEN_Msk     (0x1000000UL)  /*!< RTCALMWUPEN (Bitfield-Mask: 0x01)                     */
23655  #define R_ICU_WUPEN_ACMPLP0WUPEN_Pos    (23UL)         /*!< ACMPLP0WUPEN (Bit 23)                                 */
23656  #define R_ICU_WUPEN_ACMPLP0WUPEN_Msk    (0x800000UL)   /*!< ACMPLP0WUPEN (Bitfield-Mask: 0x01)                    */
23657  #define R_ICU_WUPEN_ACMPHS0WUPEN_Pos    (22UL)         /*!< ACMPHS0WUPEN (Bit 22)                                 */
23658  #define R_ICU_WUPEN_ACMPHS0WUPEN_Msk    (0x400000UL)   /*!< ACMPHS0WUPEN (Bitfield-Mask: 0x01)                    */
23659  #define R_ICU_WUPEN_VBATTWUPEN_Pos      (20UL)         /*!< VBATTWUPEN (Bit 20)                                   */
23660  #define R_ICU_WUPEN_VBATTWUPEN_Msk      (0x100000UL)   /*!< VBATTWUPEN (Bitfield-Mask: 0x01)                      */
23661  #define R_ICU_WUPEN_LVD2WUPEN_Pos       (19UL)         /*!< LVD2WUPEN (Bit 19)                                    */
23662  #define R_ICU_WUPEN_LVD2WUPEN_Msk       (0x80000UL)    /*!< LVD2WUPEN (Bitfield-Mask: 0x01)                       */
23663  #define R_ICU_WUPEN_LVD1WUPEN_Pos       (18UL)         /*!< LVD1WUPEN (Bit 18)                                    */
23664  #define R_ICU_WUPEN_LVD1WUPEN_Msk       (0x40000UL)    /*!< LVD1WUPEN (Bitfield-Mask: 0x01)                       */
23665  #define R_ICU_WUPEN_KEYWUPEN_Pos        (17UL)         /*!< KEYWUPEN (Bit 17)                                     */
23666  #define R_ICU_WUPEN_KEYWUPEN_Msk        (0x20000UL)    /*!< KEYWUPEN (Bitfield-Mask: 0x01)                        */
23667  #define R_ICU_WUPEN_IWDTWUPEN_Pos       (16UL)         /*!< IWDTWUPEN (Bit 16)                                    */
23668  #define R_ICU_WUPEN_IWDTWUPEN_Msk       (0x10000UL)    /*!< IWDTWUPEN (Bitfield-Mask: 0x01)                       */
23669  #define R_ICU_WUPEN_IRQWUPEN_Pos        (0UL)          /*!< IRQWUPEN (Bit 0)                                      */
23670  #define R_ICU_WUPEN_IRQWUPEN_Msk        (0x1UL)        /*!< IRQWUPEN (Bitfield-Mask: 0x01)                        */
23671 /* ========================================================  WUPEN1  ========================================================= */
23672  #define R_ICU_WUPEN1_AGT3UDWUPEN_Pos    (0UL)          /*!< AGT3UDWUPEN (Bit 0)                                   */
23673  #define R_ICU_WUPEN1_AGT3UDWUPEN_Msk    (0x1UL)        /*!< AGT3UDWUPEN (Bitfield-Mask: 0x01)                     */
23674  #define R_ICU_WUPEN1_AGT3CAWUPEN_Pos    (1UL)          /*!< AGT3CAWUPEN (Bit 1)                                   */
23675  #define R_ICU_WUPEN1_AGT3CAWUPEN_Msk    (0x2UL)        /*!< AGT3CAWUPEN (Bitfield-Mask: 0x01)                     */
23676  #define R_ICU_WUPEN1_AGT3CBWUPEN_Pos    (2UL)          /*!< AGT3CBWUPEN (Bit 2)                                   */
23677  #define R_ICU_WUPEN1_AGT3CBWUPEN_Msk    (0x4UL)        /*!< AGT3CBWUPEN (Bitfield-Mask: 0x01)                     */
23678 /* =========================================================  IELEN  ========================================================= */
23679  #define R_ICU_IELEN_IELEN_Pos           (1UL)          /*!< IELEN (Bit 1)                                         */
23680  #define R_ICU_IELEN_IELEN_Msk           (0x2UL)        /*!< IELEN (Bitfield-Mask: 0x01)                           */
23681  #define R_ICU_IELEN_RTCINTEN_Pos        (0UL)          /*!< RTCINTEN (Bit 0)                                      */
23682  #define R_ICU_IELEN_RTCINTEN_Msk        (0x1UL)        /*!< RTCINTEN (Bitfield-Mask: 0x01)                        */
23683 
23684 /* =========================================================================================================================== */
23685 /* ================                                          R_IIC0                                           ================ */
23686 /* =========================================================================================================================== */
23687 
23688 /* =========================================================  ICCR1  ========================================================= */
23689  #define R_IIC0_ICCR1_ICE_Pos        (7UL)    /*!< ICE (Bit 7)                                           */
23690  #define R_IIC0_ICCR1_ICE_Msk        (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
23691  #define R_IIC0_ICCR1_IICRST_Pos     (6UL)    /*!< IICRST (Bit 6)                                        */
23692  #define R_IIC0_ICCR1_IICRST_Msk     (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
23693  #define R_IIC0_ICCR1_CLO_Pos        (5UL)    /*!< CLO (Bit 5)                                           */
23694  #define R_IIC0_ICCR1_CLO_Msk        (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
23695  #define R_IIC0_ICCR1_SOWP_Pos       (4UL)    /*!< SOWP (Bit 4)                                          */
23696  #define R_IIC0_ICCR1_SOWP_Msk       (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
23697  #define R_IIC0_ICCR1_SCLO_Pos       (3UL)    /*!< SCLO (Bit 3)                                          */
23698  #define R_IIC0_ICCR1_SCLO_Msk       (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
23699  #define R_IIC0_ICCR1_SDAO_Pos       (2UL)    /*!< SDAO (Bit 2)                                          */
23700  #define R_IIC0_ICCR1_SDAO_Msk       (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
23701  #define R_IIC0_ICCR1_SCLI_Pos       (1UL)    /*!< SCLI (Bit 1)                                          */
23702  #define R_IIC0_ICCR1_SCLI_Msk       (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
23703  #define R_IIC0_ICCR1_SDAI_Pos       (0UL)    /*!< SDAI (Bit 0)                                          */
23704  #define R_IIC0_ICCR1_SDAI_Msk       (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
23705 /* =========================================================  ICCR2  ========================================================= */
23706  #define R_IIC0_ICCR2_BBSY_Pos       (7UL)    /*!< BBSY (Bit 7)                                          */
23707  #define R_IIC0_ICCR2_BBSY_Msk       (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
23708  #define R_IIC0_ICCR2_MST_Pos        (6UL)    /*!< MST (Bit 6)                                           */
23709  #define R_IIC0_ICCR2_MST_Msk        (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
23710  #define R_IIC0_ICCR2_TRS_Pos        (5UL)    /*!< TRS (Bit 5)                                           */
23711  #define R_IIC0_ICCR2_TRS_Msk        (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
23712  #define R_IIC0_ICCR2_SP_Pos         (3UL)    /*!< SP (Bit 3)                                            */
23713  #define R_IIC0_ICCR2_SP_Msk         (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
23714  #define R_IIC0_ICCR2_RS_Pos         (2UL)    /*!< RS (Bit 2)                                            */
23715  #define R_IIC0_ICCR2_RS_Msk         (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
23716  #define R_IIC0_ICCR2_ST_Pos         (1UL)    /*!< ST (Bit 1)                                            */
23717  #define R_IIC0_ICCR2_ST_Msk         (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
23718 /* =========================================================  ICMR1  ========================================================= */
23719  #define R_IIC0_ICMR1_MTWP_Pos       (7UL)    /*!< MTWP (Bit 7)                                          */
23720  #define R_IIC0_ICMR1_MTWP_Msk       (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
23721  #define R_IIC0_ICMR1_CKS_Pos        (4UL)    /*!< CKS (Bit 4)                                           */
23722  #define R_IIC0_ICMR1_CKS_Msk        (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
23723  #define R_IIC0_ICMR1_BCWP_Pos       (3UL)    /*!< BCWP (Bit 3)                                          */
23724  #define R_IIC0_ICMR1_BCWP_Msk       (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
23725  #define R_IIC0_ICMR1_BC_Pos         (0UL)    /*!< BC (Bit 0)                                            */
23726  #define R_IIC0_ICMR1_BC_Msk         (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
23727 /* =========================================================  ICMR2  ========================================================= */
23728  #define R_IIC0_ICMR2_DLCS_Pos       (7UL)    /*!< DLCS (Bit 7)                                          */
23729  #define R_IIC0_ICMR2_DLCS_Msk       (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
23730  #define R_IIC0_ICMR2_SDDL_Pos       (4UL)    /*!< SDDL (Bit 4)                                          */
23731  #define R_IIC0_ICMR2_SDDL_Msk       (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
23732  #define R_IIC0_ICMR2_TMOH_Pos       (2UL)    /*!< TMOH (Bit 2)                                          */
23733  #define R_IIC0_ICMR2_TMOH_Msk       (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
23734  #define R_IIC0_ICMR2_TMOL_Pos       (1UL)    /*!< TMOL (Bit 1)                                          */
23735  #define R_IIC0_ICMR2_TMOL_Msk       (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
23736  #define R_IIC0_ICMR2_TMOS_Pos       (0UL)    /*!< TMOS (Bit 0)                                          */
23737  #define R_IIC0_ICMR2_TMOS_Msk       (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
23738 /* =========================================================  ICMR3  ========================================================= */
23739  #define R_IIC0_ICMR3_SMBS_Pos       (7UL)    /*!< SMBS (Bit 7)                                          */
23740  #define R_IIC0_ICMR3_SMBS_Msk       (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
23741  #define R_IIC0_ICMR3_WAIT_Pos       (6UL)    /*!< WAIT (Bit 6)                                          */
23742  #define R_IIC0_ICMR3_WAIT_Msk       (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
23743  #define R_IIC0_ICMR3_RDRFS_Pos      (5UL)    /*!< RDRFS (Bit 5)                                         */
23744  #define R_IIC0_ICMR3_RDRFS_Msk      (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
23745  #define R_IIC0_ICMR3_ACKWP_Pos      (4UL)    /*!< ACKWP (Bit 4)                                         */
23746  #define R_IIC0_ICMR3_ACKWP_Msk      (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
23747  #define R_IIC0_ICMR3_ACKBT_Pos      (3UL)    /*!< ACKBT (Bit 3)                                         */
23748  #define R_IIC0_ICMR3_ACKBT_Msk      (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
23749  #define R_IIC0_ICMR3_ACKBR_Pos      (2UL)    /*!< ACKBR (Bit 2)                                         */
23750  #define R_IIC0_ICMR3_ACKBR_Msk      (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
23751  #define R_IIC0_ICMR3_NF_Pos         (0UL)    /*!< NF (Bit 0)                                            */
23752  #define R_IIC0_ICMR3_NF_Msk         (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
23753 /* =========================================================  ICFER  ========================================================= */
23754  #define R_IIC0_ICFER_FMPE_Pos       (7UL)    /*!< FMPE (Bit 7)                                          */
23755  #define R_IIC0_ICFER_FMPE_Msk       (0x80UL) /*!< FMPE (Bitfield-Mask: 0x01)                            */
23756  #define R_IIC0_ICFER_SCLE_Pos       (6UL)    /*!< SCLE (Bit 6)                                          */
23757  #define R_IIC0_ICFER_SCLE_Msk       (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
23758  #define R_IIC0_ICFER_NFE_Pos        (5UL)    /*!< NFE (Bit 5)                                           */
23759  #define R_IIC0_ICFER_NFE_Msk        (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
23760  #define R_IIC0_ICFER_NACKE_Pos      (4UL)    /*!< NACKE (Bit 4)                                         */
23761  #define R_IIC0_ICFER_NACKE_Msk      (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
23762  #define R_IIC0_ICFER_SALE_Pos       (3UL)    /*!< SALE (Bit 3)                                          */
23763  #define R_IIC0_ICFER_SALE_Msk       (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
23764  #define R_IIC0_ICFER_NALE_Pos       (2UL)    /*!< NALE (Bit 2)                                          */
23765  #define R_IIC0_ICFER_NALE_Msk       (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
23766  #define R_IIC0_ICFER_MALE_Pos       (1UL)    /*!< MALE (Bit 1)                                          */
23767  #define R_IIC0_ICFER_MALE_Msk       (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
23768  #define R_IIC0_ICFER_TMOE_Pos       (0UL)    /*!< TMOE (Bit 0)                                          */
23769  #define R_IIC0_ICFER_TMOE_Msk       (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
23770 /* =========================================================  ICSER  ========================================================= */
23771  #define R_IIC0_ICSER_HOAE_Pos       (7UL)    /*!< HOAE (Bit 7)                                          */
23772  #define R_IIC0_ICSER_HOAE_Msk       (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
23773  #define R_IIC0_ICSER_DIDE_Pos       (5UL)    /*!< DIDE (Bit 5)                                          */
23774  #define R_IIC0_ICSER_DIDE_Msk       (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
23775  #define R_IIC0_ICSER_GCAE_Pos       (3UL)    /*!< GCAE (Bit 3)                                          */
23776  #define R_IIC0_ICSER_GCAE_Msk       (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
23777  #define R_IIC0_ICSER_SAR2E_Pos      (2UL)    /*!< SAR2E (Bit 2)                                         */
23778  #define R_IIC0_ICSER_SAR2E_Msk      (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
23779  #define R_IIC0_ICSER_SAR1E_Pos      (1UL)    /*!< SAR1E (Bit 1)                                         */
23780  #define R_IIC0_ICSER_SAR1E_Msk      (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
23781  #define R_IIC0_ICSER_SAR0E_Pos      (0UL)    /*!< SAR0E (Bit 0)                                         */
23782  #define R_IIC0_ICSER_SAR0E_Msk      (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
23783 /* =========================================================  ICIER  ========================================================= */
23784  #define R_IIC0_ICIER_TIE_Pos        (7UL)    /*!< TIE (Bit 7)                                           */
23785  #define R_IIC0_ICIER_TIE_Msk        (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
23786  #define R_IIC0_ICIER_TEIE_Pos       (6UL)    /*!< TEIE (Bit 6)                                          */
23787  #define R_IIC0_ICIER_TEIE_Msk       (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
23788  #define R_IIC0_ICIER_RIE_Pos        (5UL)    /*!< RIE (Bit 5)                                           */
23789  #define R_IIC0_ICIER_RIE_Msk        (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
23790  #define R_IIC0_ICIER_NAKIE_Pos      (4UL)    /*!< NAKIE (Bit 4)                                         */
23791  #define R_IIC0_ICIER_NAKIE_Msk      (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
23792  #define R_IIC0_ICIER_SPIE_Pos       (3UL)    /*!< SPIE (Bit 3)                                          */
23793  #define R_IIC0_ICIER_SPIE_Msk       (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
23794  #define R_IIC0_ICIER_STIE_Pos       (2UL)    /*!< STIE (Bit 2)                                          */
23795  #define R_IIC0_ICIER_STIE_Msk       (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
23796  #define R_IIC0_ICIER_ALIE_Pos       (1UL)    /*!< ALIE (Bit 1)                                          */
23797  #define R_IIC0_ICIER_ALIE_Msk       (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
23798  #define R_IIC0_ICIER_TMOIE_Pos      (0UL)    /*!< TMOIE (Bit 0)                                         */
23799  #define R_IIC0_ICIER_TMOIE_Msk      (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
23800 /* =========================================================  ICSR1  ========================================================= */
23801  #define R_IIC0_ICSR1_HOA_Pos        (7UL)    /*!< HOA (Bit 7)                                           */
23802  #define R_IIC0_ICSR1_HOA_Msk        (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
23803  #define R_IIC0_ICSR1_DID_Pos        (5UL)    /*!< DID (Bit 5)                                           */
23804  #define R_IIC0_ICSR1_DID_Msk        (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
23805  #define R_IIC0_ICSR1_GCA_Pos        (3UL)    /*!< GCA (Bit 3)                                           */
23806  #define R_IIC0_ICSR1_GCA_Msk        (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
23807  #define R_IIC0_ICSR1_AAS2_Pos       (2UL)    /*!< AAS2 (Bit 2)                                          */
23808  #define R_IIC0_ICSR1_AAS2_Msk       (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
23809  #define R_IIC0_ICSR1_AAS1_Pos       (1UL)    /*!< AAS1 (Bit 1)                                          */
23810  #define R_IIC0_ICSR1_AAS1_Msk       (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
23811  #define R_IIC0_ICSR1_AAS0_Pos       (0UL)    /*!< AAS0 (Bit 0)                                          */
23812  #define R_IIC0_ICSR1_AAS0_Msk       (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
23813 /* =========================================================  ICSR2  ========================================================= */
23814  #define R_IIC0_ICSR2_TDRE_Pos       (7UL)    /*!< TDRE (Bit 7)                                          */
23815  #define R_IIC0_ICSR2_TDRE_Msk       (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
23816  #define R_IIC0_ICSR2_TEND_Pos       (6UL)    /*!< TEND (Bit 6)                                          */
23817  #define R_IIC0_ICSR2_TEND_Msk       (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
23818  #define R_IIC0_ICSR2_RDRF_Pos       (5UL)    /*!< RDRF (Bit 5)                                          */
23819  #define R_IIC0_ICSR2_RDRF_Msk       (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
23820  #define R_IIC0_ICSR2_NACKF_Pos      (4UL)    /*!< NACKF (Bit 4)                                         */
23821  #define R_IIC0_ICSR2_NACKF_Msk      (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
23822  #define R_IIC0_ICSR2_STOP_Pos       (3UL)    /*!< STOP (Bit 3)                                          */
23823  #define R_IIC0_ICSR2_STOP_Msk       (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
23824  #define R_IIC0_ICSR2_START_Pos      (2UL)    /*!< START (Bit 2)                                         */
23825  #define R_IIC0_ICSR2_START_Msk      (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
23826  #define R_IIC0_ICSR2_AL_Pos         (1UL)    /*!< AL (Bit 1)                                            */
23827  #define R_IIC0_ICSR2_AL_Msk         (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
23828  #define R_IIC0_ICSR2_TMOF_Pos       (0UL)    /*!< TMOF (Bit 0)                                          */
23829  #define R_IIC0_ICSR2_TMOF_Msk       (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
23830 /* =========================================================  ICBRL  ========================================================= */
23831  #define R_IIC0_ICBRL_BRL_Pos        (0UL)    /*!< BRL (Bit 0)                                           */
23832  #define R_IIC0_ICBRL_BRL_Msk        (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
23833 /* =========================================================  ICBRH  ========================================================= */
23834  #define R_IIC0_ICBRH_BRH_Pos        (0UL)    /*!< BRH (Bit 0)                                           */
23835  #define R_IIC0_ICBRH_BRH_Msk        (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
23836 /* =========================================================  ICDRT  ========================================================= */
23837  #define R_IIC0_ICDRT_ICDRT_Pos      (0UL)    /*!< ICDRT (Bit 0)                                         */
23838  #define R_IIC0_ICDRT_ICDRT_Msk      (0xffUL) /*!< ICDRT (Bitfield-Mask: 0xff)                           */
23839 /* =========================================================  ICDRR  ========================================================= */
23840  #define R_IIC0_ICDRR_ICDRR_Pos      (0UL)    /*!< ICDRR (Bit 0)                                         */
23841  #define R_IIC0_ICDRR_ICDRR_Msk      (0xffUL) /*!< ICDRR (Bitfield-Mask: 0xff)                           */
23842 /* =========================================================  ICWUR  ========================================================= */
23843  #define R_IIC0_ICWUR_WUE_Pos        (7UL)    /*!< WUE (Bit 7)                                           */
23844  #define R_IIC0_ICWUR_WUE_Msk        (0x80UL) /*!< WUE (Bitfield-Mask: 0x01)                             */
23845  #define R_IIC0_ICWUR_WUIE_Pos       (6UL)    /*!< WUIE (Bit 6)                                          */
23846  #define R_IIC0_ICWUR_WUIE_Msk       (0x40UL) /*!< WUIE (Bitfield-Mask: 0x01)                            */
23847  #define R_IIC0_ICWUR_WUF_Pos        (5UL)    /*!< WUF (Bit 5)                                           */
23848  #define R_IIC0_ICWUR_WUF_Msk        (0x20UL) /*!< WUF (Bitfield-Mask: 0x01)                             */
23849  #define R_IIC0_ICWUR_WUACK_Pos      (4UL)    /*!< WUACK (Bit 4)                                         */
23850  #define R_IIC0_ICWUR_WUACK_Msk      (0x10UL) /*!< WUACK (Bitfield-Mask: 0x01)                           */
23851  #define R_IIC0_ICWUR_WUAFA_Pos      (0UL)    /*!< WUAFA (Bit 0)                                         */
23852  #define R_IIC0_ICWUR_WUAFA_Msk      (0x1UL)  /*!< WUAFA (Bitfield-Mask: 0x01)                           */
23853 /* ========================================================  ICWUR2  ========================================================= */
23854  #define R_IIC0_ICWUR2_WUSYF_Pos     (2UL)    /*!< WUSYF (Bit 2)                                         */
23855  #define R_IIC0_ICWUR2_WUSYF_Msk     (0x4UL)  /*!< WUSYF (Bitfield-Mask: 0x01)                           */
23856  #define R_IIC0_ICWUR2_WUASYF_Pos    (1UL)    /*!< WUASYF (Bit 1)                                        */
23857  #define R_IIC0_ICWUR2_WUASYF_Msk    (0x2UL)  /*!< WUASYF (Bitfield-Mask: 0x01)                          */
23858  #define R_IIC0_ICWUR2_WUSEN_Pos     (0UL)    /*!< WUSEN (Bit 0)                                         */
23859  #define R_IIC0_ICWUR2_WUSEN_Msk     (0x1UL)  /*!< WUSEN (Bitfield-Mask: 0x01)                           */
23860 
23861 /* =========================================================================================================================== */
23862 /* ================                                          R_IWDT                                           ================ */
23863 /* =========================================================================================================================== */
23864 
23865 /* ========================================================  IWDTRR  ========================================================= */
23866  #define R_IWDT_IWDTRR_IWDTRR_Pos       (0UL)      /*!< IWDTRR (Bit 0)                                        */
23867  #define R_IWDT_IWDTRR_IWDTRR_Msk       (0xffUL)   /*!< IWDTRR (Bitfield-Mask: 0xff)                          */
23868 /* ========================================================  IWDTCR  ========================================================= */
23869  #define R_IWDT_IWDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
23870  #define R_IWDT_IWDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
23871  #define R_IWDT_IWDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
23872  #define R_IWDT_IWDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
23873  #define R_IWDT_IWDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
23874  #define R_IWDT_IWDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
23875  #define R_IWDT_IWDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
23876  #define R_IWDT_IWDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
23877 /* ========================================================  IWDTSR  ========================================================= */
23878  #define R_IWDT_IWDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
23879  #define R_IWDT_IWDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
23880  #define R_IWDT_IWDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
23881  #define R_IWDT_IWDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
23882  #define R_IWDT_IWDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
23883  #define R_IWDT_IWDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
23884 /* ========================================================  IWDTRCR  ======================================================== */
23885  #define R_IWDT_IWDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
23886  #define R_IWDT_IWDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
23887 /* =======================================================  IWDTCSTPR  ======================================================= */
23888  #define R_IWDT_IWDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
23889  #define R_IWDT_IWDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
23890 
23891 /* =========================================================================================================================== */
23892 /* ================                                          R_I3C0                                           ================ */
23893 /* =========================================================================================================================== */
23894 
23895 /* =========================================================  PRTS  ========================================================== */
23896  #define R_I3C0_PRTS_PRTMD_Pos          (0UL)          /*!< PRTMD (Bit 0)                                         */
23897  #define R_I3C0_PRTS_PRTMD_Msk          (0x1UL)        /*!< PRTMD (Bitfield-Mask: 0x01)                           */
23898 /* =========================================================  CECTL  ========================================================= */
23899  #define R_I3C0_CECTL_CLKE_Pos          (0UL)          /*!< CLKE (Bit 0)                                          */
23900  #define R_I3C0_CECTL_CLKE_Msk          (0x1UL)        /*!< CLKE (Bitfield-Mask: 0x01)                            */
23901 /* =========================================================  BCTL  ========================================================== */
23902  #define R_I3C0_BCTL_INCBA_Pos          (0UL)          /*!< INCBA (Bit 0)                                         */
23903  #define R_I3C0_BCTL_INCBA_Msk          (0x1UL)        /*!< INCBA (Bitfield-Mask: 0x01)                           */
23904  #define R_I3C0_BCTL_BMDS_Pos           (7UL)          /*!< BMDS (Bit 7)                                          */
23905  #define R_I3C0_BCTL_BMDS_Msk           (0x80UL)       /*!< BMDS (Bitfield-Mask: 0x01)                            */
23906  #define R_I3C0_BCTL_HJACKCTL_Pos       (8UL)          /*!< HJACKCTL (Bit 8)                                      */
23907  #define R_I3C0_BCTL_HJACKCTL_Msk       (0x100UL)      /*!< HJACKCTL (Bitfield-Mask: 0x01)                        */
23908  #define R_I3C0_BCTL_ABT_Pos            (29UL)         /*!< ABT (Bit 29)                                          */
23909  #define R_I3C0_BCTL_ABT_Msk            (0x20000000UL) /*!< ABT (Bitfield-Mask: 0x01)                             */
23910  #define R_I3C0_BCTL_RSM_Pos            (30UL)         /*!< RSM (Bit 30)                                          */
23911  #define R_I3C0_BCTL_RSM_Msk            (0x40000000UL) /*!< RSM (Bitfield-Mask: 0x01)                             */
23912  #define R_I3C0_BCTL_BUSE_Pos           (31UL)         /*!< BUSE (Bit 31)                                         */
23913  #define R_I3C0_BCTL_BUSE_Msk           (0x80000000UL) /*!< BUSE (Bitfield-Mask: 0x01)                            */
23914 /* ========================================================  MSDVAD  ========================================================= */
23915  #define R_I3C0_MSDVAD_MDYAD_Pos        (16UL)         /*!< MDYAD (Bit 16)                                        */
23916  #define R_I3C0_MSDVAD_MDYAD_Msk        (0x7f0000UL)   /*!< MDYAD (Bitfield-Mask: 0x7f)                           */
23917  #define R_I3C0_MSDVAD_MDYADV_Pos       (31UL)         /*!< MDYADV (Bit 31)                                       */
23918  #define R_I3C0_MSDVAD_MDYADV_Msk       (0x80000000UL) /*!< MDYADV (Bitfield-Mask: 0x01)                          */
23919 /* ========================================================  RSTCTL  ========================================================= */
23920  #define R_I3C0_RSTCTL_RI3CRST_Pos      (0UL)          /*!< RI3CRST (Bit 0)                                       */
23921  #define R_I3C0_RSTCTL_RI3CRST_Msk      (0x1UL)        /*!< RI3CRST (Bitfield-Mask: 0x01)                         */
23922  #define R_I3C0_RSTCTL_CMDQRST_Pos      (1UL)          /*!< CMDQRST (Bit 1)                                       */
23923  #define R_I3C0_RSTCTL_CMDQRST_Msk      (0x2UL)        /*!< CMDQRST (Bitfield-Mask: 0x01)                         */
23924  #define R_I3C0_RSTCTL_RSPQRST_Pos      (2UL)          /*!< RSPQRST (Bit 2)                                       */
23925  #define R_I3C0_RSTCTL_RSPQRST_Msk      (0x4UL)        /*!< RSPQRST (Bitfield-Mask: 0x01)                         */
23926  #define R_I3C0_RSTCTL_TDBRST_Pos       (3UL)          /*!< TDBRST (Bit 3)                                        */
23927  #define R_I3C0_RSTCTL_TDBRST_Msk       (0x8UL)        /*!< TDBRST (Bitfield-Mask: 0x01)                          */
23928  #define R_I3C0_RSTCTL_RDBRST_Pos       (4UL)          /*!< RDBRST (Bit 4)                                        */
23929  #define R_I3C0_RSTCTL_RDBRST_Msk       (0x10UL)       /*!< RDBRST (Bitfield-Mask: 0x01)                          */
23930  #define R_I3C0_RSTCTL_IBIQRST_Pos      (5UL)          /*!< IBIQRST (Bit 5)                                       */
23931  #define R_I3C0_RSTCTL_IBIQRST_Msk      (0x20UL)       /*!< IBIQRST (Bitfield-Mask: 0x01)                         */
23932  #define R_I3C0_RSTCTL_RSQRST_Pos       (6UL)          /*!< RSQRST (Bit 6)                                        */
23933  #define R_I3C0_RSTCTL_RSQRST_Msk       (0x40UL)       /*!< RSQRST (Bitfield-Mask: 0x01)                          */
23934  #define R_I3C0_RSTCTL_INTLRST_Pos      (16UL)         /*!< INTLRST (Bit 16)                                      */
23935  #define R_I3C0_RSTCTL_INTLRST_Msk      (0x10000UL)    /*!< INTLRST (Bitfield-Mask: 0x01)                         */
23936 /* =========================================================  PRSST  ========================================================= */
23937  #define R_I3C0_PRSST_CRMS_Pos          (2UL)          /*!< CRMS (Bit 2)                                          */
23938  #define R_I3C0_PRSST_CRMS_Msk          (0x4UL)        /*!< CRMS (Bitfield-Mask: 0x01)                            */
23939  #define R_I3C0_PRSST_TRMD_Pos          (4UL)          /*!< TRMD (Bit 4)                                          */
23940  #define R_I3C0_PRSST_TRMD_Msk          (0x10UL)       /*!< TRMD (Bitfield-Mask: 0x01)                            */
23941  #define R_I3C0_PRSST_PRSSTWP_Pos       (7UL)          /*!< PRSSTWP (Bit 7)                                       */
23942  #define R_I3C0_PRSST_PRSSTWP_Msk       (0x80UL)       /*!< PRSSTWP (Bitfield-Mask: 0x01)                         */
23943 /* =========================================================  INST  ========================================================== */
23944  #define R_I3C0_INST_INEF_Pos           (10UL)         /*!< INEF (Bit 10)                                         */
23945  #define R_I3C0_INST_INEF_Msk           (0x400UL)      /*!< INEF (Bitfield-Mask: 0x01)                            */
23946 /* =========================================================  INSTE  ========================================================= */
23947  #define R_I3C0_INSTE_INEE_Pos          (10UL)         /*!< INEE (Bit 10)                                         */
23948  #define R_I3C0_INSTE_INEE_Msk          (0x400UL)      /*!< INEE (Bitfield-Mask: 0x01)                            */
23949 /* =========================================================  INIE  ========================================================== */
23950  #define R_I3C0_INIE_INEIE_Pos          (10UL)         /*!< INEIE (Bit 10)                                        */
23951  #define R_I3C0_INIE_INEIE_Msk          (0x400UL)      /*!< INEIE (Bitfield-Mask: 0x01)                           */
23952 /* ========================================================  INSTFC  ========================================================= */
23953  #define R_I3C0_INSTFC_INEFC_Pos        (10UL)         /*!< INEFC (Bit 10)                                        */
23954  #define R_I3C0_INSTFC_INEFC_Msk        (0x400UL)      /*!< INEFC (Bitfield-Mask: 0x01)                           */
23955 /* =========================================================  DVCT  ========================================================== */
23956  #define R_I3C0_DVCT_IDX_Pos            (19UL)         /*!< IDX (Bit 19)                                          */
23957  #define R_I3C0_DVCT_IDX_Msk            (0xf80000UL)   /*!< IDX (Bitfield-Mask: 0x1f)                             */
23958 /* ========================================================  IBINCTL  ======================================================== */
23959  #define R_I3C0_IBINCTL_NRHJCTL_Pos     (0UL)          /*!< NRHJCTL (Bit 0)                                       */
23960  #define R_I3C0_IBINCTL_NRHJCTL_Msk     (0x1UL)        /*!< NRHJCTL (Bitfield-Mask: 0x01)                         */
23961  #define R_I3C0_IBINCTL_NRMRCTL_Pos     (1UL)          /*!< NRMRCTL (Bit 1)                                       */
23962  #define R_I3C0_IBINCTL_NRMRCTL_Msk     (0x2UL)        /*!< NRMRCTL (Bitfield-Mask: 0x01)                         */
23963  #define R_I3C0_IBINCTL_NRSIRCTL_Pos    (3UL)          /*!< NRSIRCTL (Bit 3)                                      */
23964  #define R_I3C0_IBINCTL_NRSIRCTL_Msk    (0x8UL)        /*!< NRSIRCTL (Bitfield-Mask: 0x01)                        */
23965 /* =========================================================  BFCTL  ========================================================= */
23966  #define R_I3C0_BFCTL_MALE_Pos          (0UL)          /*!< MALE (Bit 0)                                          */
23967  #define R_I3C0_BFCTL_MALE_Msk          (0x1UL)        /*!< MALE (Bitfield-Mask: 0x01)                            */
23968  #define R_I3C0_BFCTL_NALE_Pos          (1UL)          /*!< NALE (Bit 1)                                          */
23969  #define R_I3C0_BFCTL_NALE_Msk          (0x2UL)        /*!< NALE (Bitfield-Mask: 0x01)                            */
23970  #define R_I3C0_BFCTL_SALE_Pos          (2UL)          /*!< SALE (Bit 2)                                          */
23971  #define R_I3C0_BFCTL_SALE_Msk          (0x4UL)        /*!< SALE (Bitfield-Mask: 0x01)                            */
23972  #define R_I3C0_BFCTL_SCSYNE_Pos        (8UL)          /*!< SCSYNE (Bit 8)                                        */
23973  #define R_I3C0_BFCTL_SCSYNE_Msk        (0x100UL)      /*!< SCSYNE (Bitfield-Mask: 0x01)                          */
23974  #define R_I3C0_BFCTL_SMBS_Pos          (12UL)         /*!< SMBS (Bit 12)                                         */
23975  #define R_I3C0_BFCTL_SMBS_Msk          (0x1000UL)     /*!< SMBS (Bitfield-Mask: 0x01)                            */
23976  #define R_I3C0_BFCTL_FMPE_Pos          (14UL)         /*!< FMPE (Bit 14)                                         */
23977  #define R_I3C0_BFCTL_FMPE_Msk          (0x4000UL)     /*!< FMPE (Bitfield-Mask: 0x01)                            */
23978  #define R_I3C0_BFCTL_HSME_Pos          (15UL)         /*!< HSME (Bit 15)                                         */
23979  #define R_I3C0_BFCTL_HSME_Msk          (0x8000UL)     /*!< HSME (Bitfield-Mask: 0x01)                            */
23980 /* =========================================================  SVCTL  ========================================================= */
23981  #define R_I3C0_SVCTL_GCAE_Pos          (0UL)          /*!< GCAE (Bit 0)                                          */
23982  #define R_I3C0_SVCTL_GCAE_Msk          (0x1UL)        /*!< GCAE (Bitfield-Mask: 0x01)                            */
23983  #define R_I3C0_SVCTL_HSMCE_Pos         (5UL)          /*!< HSMCE (Bit 5)                                         */
23984  #define R_I3C0_SVCTL_HSMCE_Msk         (0x20UL)       /*!< HSMCE (Bitfield-Mask: 0x01)                           */
23985  #define R_I3C0_SVCTL_DVIDE_Pos         (6UL)          /*!< DVIDE (Bit 6)                                         */
23986  #define R_I3C0_SVCTL_DVIDE_Msk         (0x40UL)       /*!< DVIDE (Bitfield-Mask: 0x01)                           */
23987  #define R_I3C0_SVCTL_HOAE_Pos          (15UL)         /*!< HOAE (Bit 15)                                         */
23988  #define R_I3C0_SVCTL_HOAE_Msk          (0x8000UL)     /*!< HOAE (Bitfield-Mask: 0x01)                            */
23989  #define R_I3C0_SVCTL_SVAEn_Pos         (16UL)         /*!< SVAEn (Bit 16)                                        */
23990  #define R_I3C0_SVCTL_SVAEn_Msk         (0x10000UL)    /*!< SVAEn (Bitfield-Mask: 0x01)                           */
23991 /* =======================================================  REFCKCTL  ======================================================== */
23992  #define R_I3C0_REFCKCTL_IREFCKS_Pos    (0UL)          /*!< IREFCKS (Bit 0)                                       */
23993  #define R_I3C0_REFCKCTL_IREFCKS_Msk    (0x7UL)        /*!< IREFCKS (Bitfield-Mask: 0x07)                         */
23994 /* =========================================================  STDBR  ========================================================= */
23995  #define R_I3C0_STDBR_SBRLO_Pos         (0UL)          /*!< SBRLO (Bit 0)                                         */
23996  #define R_I3C0_STDBR_SBRLO_Msk         (0xffUL)       /*!< SBRLO (Bitfield-Mask: 0xff)                           */
23997  #define R_I3C0_STDBR_SBRHO_Pos         (8UL)          /*!< SBRHO (Bit 8)                                         */
23998  #define R_I3C0_STDBR_SBRHO_Msk         (0xff00UL)     /*!< SBRHO (Bitfield-Mask: 0xff)                           */
23999  #define R_I3C0_STDBR_SBRLP_Pos         (16UL)         /*!< SBRLP (Bit 16)                                        */
24000  #define R_I3C0_STDBR_SBRLP_Msk         (0x3f0000UL)   /*!< SBRLP (Bitfield-Mask: 0x3f)                           */
24001  #define R_I3C0_STDBR_SBRHP_Pos         (24UL)         /*!< SBRHP (Bit 24)                                        */
24002  #define R_I3C0_STDBR_SBRHP_Msk         (0x3f000000UL) /*!< SBRHP (Bitfield-Mask: 0x3f)                           */
24003  #define R_I3C0_STDBR_DSBRPO_Pos        (31UL)         /*!< DSBRPO (Bit 31)                                       */
24004  #define R_I3C0_STDBR_DSBRPO_Msk        (0x80000000UL) /*!< DSBRPO (Bitfield-Mask: 0x01)                          */
24005 /* =========================================================  EXTBR  ========================================================= */
24006  #define R_I3C0_EXTBR_EBRLO_Pos         (0UL)          /*!< EBRLO (Bit 0)                                         */
24007  #define R_I3C0_EXTBR_EBRLO_Msk         (0xffUL)       /*!< EBRLO (Bitfield-Mask: 0xff)                           */
24008  #define R_I3C0_EXTBR_EBRHO_Pos         (8UL)          /*!< EBRHO (Bit 8)                                         */
24009  #define R_I3C0_EXTBR_EBRHO_Msk         (0xff00UL)     /*!< EBRHO (Bitfield-Mask: 0xff)                           */
24010  #define R_I3C0_EXTBR_EBRLP_Pos         (16UL)         /*!< EBRLP (Bit 16)                                        */
24011  #define R_I3C0_EXTBR_EBRLP_Msk         (0x3f0000UL)   /*!< EBRLP (Bitfield-Mask: 0x3f)                           */
24012  #define R_I3C0_EXTBR_EBRHP_Pos         (24UL)         /*!< EBRHP (Bit 24)                                        */
24013  #define R_I3C0_EXTBR_EBRHP_Msk         (0x3f000000UL) /*!< EBRHP (Bitfield-Mask: 0x3f)                           */
24014 /* ========================================================  BFRECDT  ======================================================== */
24015  #define R_I3C0_BFRECDT_FRECYC_Pos      (0UL)          /*!< FRECYC (Bit 0)                                        */
24016  #define R_I3C0_BFRECDT_FRECYC_Msk      (0x1ffUL)      /*!< FRECYC (Bitfield-Mask: 0x1ff)                         */
24017 /* ========================================================  BAVLCDT  ======================================================== */
24018  #define R_I3C0_BAVLCDT_AVLCYC_Pos      (0UL)          /*!< AVLCYC (Bit 0)                                        */
24019  #define R_I3C0_BAVLCDT_AVLCYC_Msk      (0x1ffUL)      /*!< AVLCYC (Bitfield-Mask: 0x1ff)                         */
24020 /* ========================================================  BIDLCDT  ======================================================== */
24021  #define R_I3C0_BIDLCDT_IDLCYC_Pos      (0UL)          /*!< IDLCYC (Bit 0)                                        */
24022  #define R_I3C0_BIDLCDT_IDLCYC_Msk      (0x3ffffUL)    /*!< IDLCYC (Bitfield-Mask: 0x3ffff)                       */
24023 /* ========================================================  OUTCTL  ========================================================= */
24024  #define R_I3C0_OUTCTL_SDOC_Pos         (0UL)          /*!< SDOC (Bit 0)                                          */
24025  #define R_I3C0_OUTCTL_SDOC_Msk         (0x1UL)        /*!< SDOC (Bitfield-Mask: 0x01)                            */
24026  #define R_I3C0_OUTCTL_SCOC_Pos         (1UL)          /*!< SCOC (Bit 1)                                          */
24027  #define R_I3C0_OUTCTL_SCOC_Msk         (0x2UL)        /*!< SCOC (Bitfield-Mask: 0x01)                            */
24028  #define R_I3C0_OUTCTL_SOCWP_Pos        (2UL)          /*!< SOCWP (Bit 2)                                         */
24029  #define R_I3C0_OUTCTL_SOCWP_Msk        (0x4UL)        /*!< SOCWP (Bitfield-Mask: 0x01)                           */
24030  #define R_I3C0_OUTCTL_EXCYC_Pos        (4UL)          /*!< EXCYC (Bit 4)                                         */
24031  #define R_I3C0_OUTCTL_EXCYC_Msk        (0x10UL)       /*!< EXCYC (Bitfield-Mask: 0x01)                           */
24032  #define R_I3C0_OUTCTL_SDOD_Pos         (8UL)          /*!< SDOD (Bit 8)                                          */
24033  #define R_I3C0_OUTCTL_SDOD_Msk         (0x700UL)      /*!< SDOD (Bitfield-Mask: 0x07)                            */
24034  #define R_I3C0_OUTCTL_SDODCS_Pos       (15UL)         /*!< SDODCS (Bit 15)                                       */
24035  #define R_I3C0_OUTCTL_SDODCS_Msk       (0x8000UL)     /*!< SDODCS (Bitfield-Mask: 0x01)                          */
24036 /* =========================================================  INCTL  ========================================================= */
24037  #define R_I3C0_INCTL_DNFS_Pos          (0UL)          /*!< DNFS (Bit 0)                                          */
24038  #define R_I3C0_INCTL_DNFS_Msk          (0xfUL)        /*!< DNFS (Bitfield-Mask: 0x0f)                            */
24039  #define R_I3C0_INCTL_DNFE_Pos          (4UL)          /*!< DNFE (Bit 4)                                          */
24040  #define R_I3C0_INCTL_DNFE_Msk          (0x10UL)       /*!< DNFE (Bitfield-Mask: 0x01)                            */
24041 /* ========================================================  TMOCTL  ========================================================= */
24042  #define R_I3C0_TMOCTL_TODTS_Pos        (0UL)          /*!< TODTS (Bit 0)                                         */
24043  #define R_I3C0_TMOCTL_TODTS_Msk        (0x3UL)        /*!< TODTS (Bitfield-Mask: 0x03)                           */
24044  #define R_I3C0_TMOCTL_TOLCTL_Pos       (4UL)          /*!< TOLCTL (Bit 4)                                        */
24045  #define R_I3C0_TMOCTL_TOLCTL_Msk       (0x10UL)       /*!< TOLCTL (Bitfield-Mask: 0x01)                          */
24046  #define R_I3C0_TMOCTL_TOHCTL_Pos       (5UL)          /*!< TOHCTL (Bit 5)                                        */
24047  #define R_I3C0_TMOCTL_TOHCTL_Msk       (0x20UL)       /*!< TOHCTL (Bitfield-Mask: 0x01)                          */
24048  #define R_I3C0_TMOCTL_TOMDS_Pos        (6UL)          /*!< TOMDS (Bit 6)                                         */
24049  #define R_I3C0_TMOCTL_TOMDS_Msk        (0xc0UL)       /*!< TOMDS (Bitfield-Mask: 0x03)                           */
24050 /* =========================================================  WUCTL  ========================================================= */
24051  #define R_I3C0_WUCTL_WUACKS_Pos        (0UL)          /*!< WUACKS (Bit 0)                                        */
24052  #define R_I3C0_WUCTL_WUACKS_Msk        (0x1UL)        /*!< WUACKS (Bitfield-Mask: 0x01)                          */
24053  #define R_I3C0_WUCTL_WUANFS_Pos        (4UL)          /*!< WUANFS (Bit 4)                                        */
24054  #define R_I3C0_WUCTL_WUANFS_Msk        (0x10UL)       /*!< WUANFS (Bitfield-Mask: 0x01)                          */
24055  #define R_I3C0_WUCTL_WUFSYNE_Pos       (6UL)          /*!< WUFSYNE (Bit 6)                                       */
24056  #define R_I3C0_WUCTL_WUFSYNE_Msk       (0x40UL)       /*!< WUFSYNE (Bitfield-Mask: 0x01)                         */
24057  #define R_I3C0_WUCTL_WUFE_Pos          (7UL)          /*!< WUFE (Bit 7)                                          */
24058  #define R_I3C0_WUCTL_WUFE_Msk          (0x80UL)       /*!< WUFE (Bitfield-Mask: 0x01)                            */
24059 /* ========================================================  ACKCTL  ========================================================= */
24060  #define R_I3C0_ACKCTL_ACKR_Pos         (0UL)          /*!< ACKR (Bit 0)                                          */
24061  #define R_I3C0_ACKCTL_ACKR_Msk         (0x1UL)        /*!< ACKR (Bitfield-Mask: 0x01)                            */
24062  #define R_I3C0_ACKCTL_ACKT_Pos         (1UL)          /*!< ACKT (Bit 1)                                          */
24063  #define R_I3C0_ACKCTL_ACKT_Msk         (0x2UL)        /*!< ACKT (Bitfield-Mask: 0x01)                            */
24064  #define R_I3C0_ACKCTL_ACKTWP_Pos       (2UL)          /*!< ACKTWP (Bit 2)                                        */
24065  #define R_I3C0_ACKCTL_ACKTWP_Msk       (0x4UL)        /*!< ACKTWP (Bitfield-Mask: 0x01)                          */
24066 /* =======================================================  SCSTRCTL  ======================================================== */
24067  #define R_I3C0_SCSTRCTL_ACKTWE_Pos     (0UL)          /*!< ACKTWE (Bit 0)                                        */
24068  #define R_I3C0_SCSTRCTL_ACKTWE_Msk     (0x1UL)        /*!< ACKTWE (Bitfield-Mask: 0x01)                          */
24069  #define R_I3C0_SCSTRCTL_RWE_Pos        (1UL)          /*!< RWE (Bit 1)                                           */
24070  #define R_I3C0_SCSTRCTL_RWE_Msk        (0x2UL)        /*!< RWE (Bitfield-Mask: 0x01)                             */
24071 /* =======================================================  SCSTLCTL  ======================================================== */
24072  #define R_I3C0_SCSTLCTL_STLCYC_Pos     (0UL)          /*!< STLCYC (Bit 0)                                        */
24073  #define R_I3C0_SCSTLCTL_STLCYC_Msk     (0xffffUL)     /*!< STLCYC (Bitfield-Mask: 0xffff)                        */
24074  #define R_I3C0_SCSTLCTL_AAPE_Pos       (28UL)         /*!< AAPE (Bit 28)                                         */
24075  #define R_I3C0_SCSTLCTL_AAPE_Msk       (0x10000000UL) /*!< AAPE (Bitfield-Mask: 0x01)                            */
24076  #define R_I3C0_SCSTLCTL_TRAPE_Pos      (29UL)         /*!< TRAPE (Bit 29)                                        */
24077  #define R_I3C0_SCSTLCTL_TRAPE_Msk      (0x20000000UL) /*!< TRAPE (Bitfield-Mask: 0x01)                           */
24078  #define R_I3C0_SCSTLCTL_PARPE_Pos      (30UL)         /*!< PARPE (Bit 30)                                        */
24079  #define R_I3C0_SCSTLCTL_PARPE_Msk      (0x40000000UL) /*!< PARPE (Bitfield-Mask: 0x01)                           */
24080  #define R_I3C0_SCSTLCTL_ACKPE_Pos      (31UL)         /*!< ACKPE (Bit 31)                                        */
24081  #define R_I3C0_SCSTLCTL_ACKPE_Msk      (0x80000000UL) /*!< ACKPE (Bitfield-Mask: 0x01)                           */
24082 /* ========================================================  SVTDLG0  ======================================================== */
24083  #define R_I3C0_SVTDLG0_STDLG_Pos       (16UL)         /*!< STDLG (Bit 16)                                        */
24084  #define R_I3C0_SVTDLG0_STDLG_Msk       (0xffff0000UL) /*!< STDLG (Bitfield-Mask: 0xffff)                         */
24085 /* ========================================================  CNDCTL  ========================================================= */
24086  #define R_I3C0_CNDCTL_STCND_Pos        (0UL)          /*!< STCND (Bit 0)                                         */
24087  #define R_I3C0_CNDCTL_STCND_Msk        (0x1UL)        /*!< STCND (Bitfield-Mask: 0x01)                           */
24088  #define R_I3C0_CNDCTL_SRCND_Pos        (1UL)          /*!< SRCND (Bit 1)                                         */
24089  #define R_I3C0_CNDCTL_SRCND_Msk        (0x2UL)        /*!< SRCND (Bitfield-Mask: 0x01)                           */
24090  #define R_I3C0_CNDCTL_SPCND_Pos        (2UL)          /*!< SPCND (Bit 2)                                         */
24091  #define R_I3C0_CNDCTL_SPCND_Msk        (0x4UL)        /*!< SPCND (Bitfield-Mask: 0x01)                           */
24092 /* ========================================================  NCMDQP  ========================================================= */
24093 /* ========================================================  NRSPQP  ========================================================= */
24094 /* ========================================================  NTDTBP0  ======================================================== */
24095 /* ========================================================  NIBIQP  ========================================================= */
24096 /* =========================================================  NRSQP  ========================================================= */
24097 /* ========================================================  NQTHCTL  ======================================================== */
24098  #define R_I3C0_NQTHCTL_CMDQTH_Pos      (0UL)          /*!< CMDQTH (Bit 0)                                        */
24099  #define R_I3C0_NQTHCTL_CMDQTH_Msk      (0xffUL)       /*!< CMDQTH (Bitfield-Mask: 0xff)                          */
24100  #define R_I3C0_NQTHCTL_RSPQTH_Pos      (8UL)          /*!< RSPQTH (Bit 8)                                        */
24101  #define R_I3C0_NQTHCTL_RSPQTH_Msk      (0xff00UL)     /*!< RSPQTH (Bitfield-Mask: 0xff)                          */
24102  #define R_I3C0_NQTHCTL_IBIDSSZ_Pos     (16UL)         /*!< IBIDSSZ (Bit 16)                                      */
24103  #define R_I3C0_NQTHCTL_IBIDSSZ_Msk     (0xff0000UL)   /*!< IBIDSSZ (Bitfield-Mask: 0xff)                         */
24104  #define R_I3C0_NQTHCTL_IBIQTH_Pos      (24UL)         /*!< IBIQTH (Bit 24)                                       */
24105  #define R_I3C0_NQTHCTL_IBIQTH_Msk      (0xff000000UL) /*!< IBIQTH (Bitfield-Mask: 0xff)                          */
24106 /* =======================================================  NTBTHCTL0  ======================================================= */
24107  #define R_I3C0_NTBTHCTL0_TXDBTH_Pos    (0UL)          /*!< TXDBTH (Bit 0)                                        */
24108  #define R_I3C0_NTBTHCTL0_TXDBTH_Msk    (0x7UL)        /*!< TXDBTH (Bitfield-Mask: 0x07)                          */
24109  #define R_I3C0_NTBTHCTL0_RXDBTH_Pos    (8UL)          /*!< RXDBTH (Bit 8)                                        */
24110  #define R_I3C0_NTBTHCTL0_RXDBTH_Msk    (0x700UL)      /*!< RXDBTH (Bitfield-Mask: 0x07)                          */
24111  #define R_I3C0_NTBTHCTL0_TXSTTH_Pos    (16UL)         /*!< TXSTTH (Bit 16)                                       */
24112  #define R_I3C0_NTBTHCTL0_TXSTTH_Msk    (0x70000UL)    /*!< TXSTTH (Bitfield-Mask: 0x07)                          */
24113  #define R_I3C0_NTBTHCTL0_RXSTTH_Pos    (24UL)         /*!< RXSTTH (Bit 24)                                       */
24114  #define R_I3C0_NTBTHCTL0_RXSTTH_Msk    (0x7000000UL)  /*!< RXSTTH (Bitfield-Mask: 0x07)                          */
24115 /* =======================================================  NRQTHCTL  ======================================================== */
24116  #define R_I3C0_NRQTHCTL_RSQTH_Pos      (0UL)          /*!< RSQTH (Bit 0)                                         */
24117  #define R_I3C0_NRQTHCTL_RSQTH_Msk      (0xffUL)       /*!< RSQTH (Bitfield-Mask: 0xff)                           */
24118 /* ==========================================================  BST  ========================================================== */
24119  #define R_I3C0_BST_STCNDDF_Pos         (0UL)          /*!< STCNDDF (Bit 0)                                       */
24120  #define R_I3C0_BST_STCNDDF_Msk         (0x1UL)        /*!< STCNDDF (Bitfield-Mask: 0x01)                         */
24121  #define R_I3C0_BST_SPCNDDF_Pos         (1UL)          /*!< SPCNDDF (Bit 1)                                       */
24122  #define R_I3C0_BST_SPCNDDF_Msk         (0x2UL)        /*!< SPCNDDF (Bitfield-Mask: 0x01)                         */
24123  #define R_I3C0_BST_HDREXDF_Pos         (2UL)          /*!< HDREXDF (Bit 2)                                       */
24124  #define R_I3C0_BST_HDREXDF_Msk         (0x4UL)        /*!< HDREXDF (Bitfield-Mask: 0x01)                         */
24125  #define R_I3C0_BST_NACKDF_Pos          (4UL)          /*!< NACKDF (Bit 4)                                        */
24126  #define R_I3C0_BST_NACKDF_Msk          (0x10UL)       /*!< NACKDF (Bitfield-Mask: 0x01)                          */
24127  #define R_I3C0_BST_TENDF_Pos           (8UL)          /*!< TENDF (Bit 8)                                         */
24128  #define R_I3C0_BST_TENDF_Msk           (0x100UL)      /*!< TENDF (Bitfield-Mask: 0x01)                           */
24129  #define R_I3C0_BST_ALF_Pos             (16UL)         /*!< ALF (Bit 16)                                          */
24130  #define R_I3C0_BST_ALF_Msk             (0x10000UL)    /*!< ALF (Bitfield-Mask: 0x01)                             */
24131  #define R_I3C0_BST_TODF_Pos            (20UL)         /*!< TODF (Bit 20)                                         */
24132  #define R_I3C0_BST_TODF_Msk            (0x100000UL)   /*!< TODF (Bitfield-Mask: 0x01)                            */
24133 /* =========================================================  BSTE  ========================================================== */
24134  #define R_I3C0_BSTE_STCNDDE_Pos        (0UL)          /*!< STCNDDE (Bit 0)                                       */
24135  #define R_I3C0_BSTE_STCNDDE_Msk        (0x1UL)        /*!< STCNDDE (Bitfield-Mask: 0x01)                         */
24136  #define R_I3C0_BSTE_SPCNDDE_Pos        (1UL)          /*!< SPCNDDE (Bit 1)                                       */
24137  #define R_I3C0_BSTE_SPCNDDE_Msk        (0x2UL)        /*!< SPCNDDE (Bitfield-Mask: 0x01)                         */
24138  #define R_I3C0_BSTE_HDREXDE_Pos        (2UL)          /*!< HDREXDE (Bit 2)                                       */
24139  #define R_I3C0_BSTE_HDREXDE_Msk        (0x4UL)        /*!< HDREXDE (Bitfield-Mask: 0x01)                         */
24140  #define R_I3C0_BSTE_NACKDE_Pos         (4UL)          /*!< NACKDE (Bit 4)                                        */
24141  #define R_I3C0_BSTE_NACKDE_Msk         (0x10UL)       /*!< NACKDE (Bitfield-Mask: 0x01)                          */
24142  #define R_I3C0_BSTE_TENDE_Pos          (8UL)          /*!< TENDE (Bit 8)                                         */
24143  #define R_I3C0_BSTE_TENDE_Msk          (0x100UL)      /*!< TENDE (Bitfield-Mask: 0x01)                           */
24144  #define R_I3C0_BSTE_ALE_Pos            (16UL)         /*!< ALE (Bit 16)                                          */
24145  #define R_I3C0_BSTE_ALE_Msk            (0x10000UL)    /*!< ALE (Bitfield-Mask: 0x01)                             */
24146  #define R_I3C0_BSTE_TODE_Pos           (20UL)         /*!< TODE (Bit 20)                                         */
24147  #define R_I3C0_BSTE_TODE_Msk           (0x100000UL)   /*!< TODE (Bitfield-Mask: 0x01)                            */
24148 /* ==========================================================  BIE  ========================================================== */
24149  #define R_I3C0_BIE_STCNDDIE_Pos        (0UL)          /*!< STCNDDIE (Bit 0)                                      */
24150  #define R_I3C0_BIE_STCNDDIE_Msk        (0x1UL)        /*!< STCNDDIE (Bitfield-Mask: 0x01)                        */
24151  #define R_I3C0_BIE_SPCNDDIE_Pos        (1UL)          /*!< SPCNDDIE (Bit 1)                                      */
24152  #define R_I3C0_BIE_SPCNDDIE_Msk        (0x2UL)        /*!< SPCNDDIE (Bitfield-Mask: 0x01)                        */
24153  #define R_I3C0_BIE_HDREXDIE_Pos        (2UL)          /*!< HDREXDIE (Bit 2)                                      */
24154  #define R_I3C0_BIE_HDREXDIE_Msk        (0x4UL)        /*!< HDREXDIE (Bitfield-Mask: 0x01)                        */
24155  #define R_I3C0_BIE_NACKDIE_Pos         (4UL)          /*!< NACKDIE (Bit 4)                                       */
24156  #define R_I3C0_BIE_NACKDIE_Msk         (0x10UL)       /*!< NACKDIE (Bitfield-Mask: 0x01)                         */
24157  #define R_I3C0_BIE_TENDIE_Pos          (8UL)          /*!< TENDIE (Bit 8)                                        */
24158  #define R_I3C0_BIE_TENDIE_Msk          (0x100UL)      /*!< TENDIE (Bitfield-Mask: 0x01)                          */
24159  #define R_I3C0_BIE_ALIE_Pos            (16UL)         /*!< ALIE (Bit 16)                                         */
24160  #define R_I3C0_BIE_ALIE_Msk            (0x10000UL)    /*!< ALIE (Bitfield-Mask: 0x01)                            */
24161  #define R_I3C0_BIE_TODIE_Pos           (20UL)         /*!< TODIE (Bit 20)                                        */
24162  #define R_I3C0_BIE_TODIE_Msk           (0x100000UL)   /*!< TODIE (Bitfield-Mask: 0x01)                           */
24163 /* =========================================================  BSTFC  ========================================================= */
24164  #define R_I3C0_BSTFC_STCNDDFC_Pos      (0UL)          /*!< STCNDDFC (Bit 0)                                      */
24165  #define R_I3C0_BSTFC_STCNDDFC_Msk      (0x1UL)        /*!< STCNDDFC (Bitfield-Mask: 0x01)                        */
24166  #define R_I3C0_BSTFC_SPCNDDFC_Pos      (1UL)          /*!< SPCNDDFC (Bit 1)                                      */
24167  #define R_I3C0_BSTFC_SPCNDDFC_Msk      (0x2UL)        /*!< SPCNDDFC (Bitfield-Mask: 0x01)                        */
24168  #define R_I3C0_BSTFC_HDREXDFC_Pos      (2UL)          /*!< HDREXDFC (Bit 2)                                      */
24169  #define R_I3C0_BSTFC_HDREXDFC_Msk      (0x4UL)        /*!< HDREXDFC (Bitfield-Mask: 0x01)                        */
24170  #define R_I3C0_BSTFC_NACKDFC_Pos       (4UL)          /*!< NACKDFC (Bit 4)                                       */
24171  #define R_I3C0_BSTFC_NACKDFC_Msk       (0x10UL)       /*!< NACKDFC (Bitfield-Mask: 0x01)                         */
24172  #define R_I3C0_BSTFC_TENDFC_Pos        (8UL)          /*!< TENDFC (Bit 8)                                        */
24173  #define R_I3C0_BSTFC_TENDFC_Msk        (0x100UL)      /*!< TENDFC (Bitfield-Mask: 0x01)                          */
24174  #define R_I3C0_BSTFC_ALFC_Pos          (16UL)         /*!< ALFC (Bit 16)                                         */
24175  #define R_I3C0_BSTFC_ALFC_Msk          (0x10000UL)    /*!< ALFC (Bitfield-Mask: 0x01)                            */
24176  #define R_I3C0_BSTFC_TODFC_Pos         (20UL)         /*!< TODFC (Bit 20)                                        */
24177  #define R_I3C0_BSTFC_TODFC_Msk         (0x100000UL)   /*!< TODFC (Bitfield-Mask: 0x01)                           */
24178 /* =========================================================  NTST  ========================================================== */
24179  #define R_I3C0_NTST_TDBEF0_Pos         (0UL)          /*!< TDBEF0 (Bit 0)                                        */
24180  #define R_I3C0_NTST_TDBEF0_Msk         (0x1UL)        /*!< TDBEF0 (Bitfield-Mask: 0x01)                          */
24181  #define R_I3C0_NTST_RDBFF0_Pos         (1UL)          /*!< RDBFF0 (Bit 1)                                        */
24182  #define R_I3C0_NTST_RDBFF0_Msk         (0x2UL)        /*!< RDBFF0 (Bitfield-Mask: 0x01)                          */
24183  #define R_I3C0_NTST_IBIQEFF_Pos        (2UL)          /*!< IBIQEFF (Bit 2)                                       */
24184  #define R_I3C0_NTST_IBIQEFF_Msk        (0x4UL)        /*!< IBIQEFF (Bitfield-Mask: 0x01)                         */
24185  #define R_I3C0_NTST_CMDQEF_Pos         (3UL)          /*!< CMDQEF (Bit 3)                                        */
24186  #define R_I3C0_NTST_CMDQEF_Msk         (0x8UL)        /*!< CMDQEF (Bitfield-Mask: 0x01)                          */
24187  #define R_I3C0_NTST_RSPQFF_Pos         (4UL)          /*!< RSPQFF (Bit 4)                                        */
24188  #define R_I3C0_NTST_RSPQFF_Msk         (0x10UL)       /*!< RSPQFF (Bitfield-Mask: 0x01)                          */
24189  #define R_I3C0_NTST_TABTF_Pos          (5UL)          /*!< TABTF (Bit 5)                                         */
24190  #define R_I3C0_NTST_TABTF_Msk          (0x20UL)       /*!< TABTF (Bitfield-Mask: 0x01)                           */
24191  #define R_I3C0_NTST_TEF_Pos            (9UL)          /*!< TEF (Bit 9)                                           */
24192  #define R_I3C0_NTST_TEF_Msk            (0x200UL)      /*!< TEF (Bitfield-Mask: 0x01)                             */
24193  #define R_I3C0_NTST_RSQFF_Pos          (20UL)         /*!< RSQFF (Bit 20)                                        */
24194  #define R_I3C0_NTST_RSQFF_Msk          (0x100000UL)   /*!< RSQFF (Bitfield-Mask: 0x01)                           */
24195 /* =========================================================  NTSTE  ========================================================= */
24196  #define R_I3C0_NTSTE_TDBEE0_Pos        (0UL)          /*!< TDBEE0 (Bit 0)                                        */
24197  #define R_I3C0_NTSTE_TDBEE0_Msk        (0x1UL)        /*!< TDBEE0 (Bitfield-Mask: 0x01)                          */
24198  #define R_I3C0_NTSTE_RDBFE0_Pos        (1UL)          /*!< RDBFE0 (Bit 1)                                        */
24199  #define R_I3C0_NTSTE_RDBFE0_Msk        (0x2UL)        /*!< RDBFE0 (Bitfield-Mask: 0x01)                          */
24200  #define R_I3C0_NTSTE_IBIQEFE_Pos       (2UL)          /*!< IBIQEFE (Bit 2)                                       */
24201  #define R_I3C0_NTSTE_IBIQEFE_Msk       (0x4UL)        /*!< IBIQEFE (Bitfield-Mask: 0x01)                         */
24202  #define R_I3C0_NTSTE_CMDQEE_Pos        (3UL)          /*!< CMDQEE (Bit 3)                                        */
24203  #define R_I3C0_NTSTE_CMDQEE_Msk        (0x8UL)        /*!< CMDQEE (Bitfield-Mask: 0x01)                          */
24204  #define R_I3C0_NTSTE_RSPQFE_Pos        (4UL)          /*!< RSPQFE (Bit 4)                                        */
24205  #define R_I3C0_NTSTE_RSPQFE_Msk        (0x10UL)       /*!< RSPQFE (Bitfield-Mask: 0x01)                          */
24206  #define R_I3C0_NTSTE_TABTE_Pos         (5UL)          /*!< TABTE (Bit 5)                                         */
24207  #define R_I3C0_NTSTE_TABTE_Msk         (0x20UL)       /*!< TABTE (Bitfield-Mask: 0x01)                           */
24208  #define R_I3C0_NTSTE_TEE_Pos           (9UL)          /*!< TEE (Bit 9)                                           */
24209  #define R_I3C0_NTSTE_TEE_Msk           (0x200UL)      /*!< TEE (Bitfield-Mask: 0x01)                             */
24210  #define R_I3C0_NTSTE_RSQFE_Pos         (20UL)         /*!< RSQFE (Bit 20)                                        */
24211  #define R_I3C0_NTSTE_RSQFE_Msk         (0x100000UL)   /*!< RSQFE (Bitfield-Mask: 0x01)                           */
24212 /* =========================================================  NTIE  ========================================================== */
24213  #define R_I3C0_NTIE_TDBEIE0_Pos        (0UL)          /*!< TDBEIE0 (Bit 0)                                       */
24214  #define R_I3C0_NTIE_TDBEIE0_Msk        (0x1UL)        /*!< TDBEIE0 (Bitfield-Mask: 0x01)                         */
24215  #define R_I3C0_NTIE_RDBFIE0_Pos        (1UL)          /*!< RDBFIE0 (Bit 1)                                       */
24216  #define R_I3C0_NTIE_RDBFIE0_Msk        (0x2UL)        /*!< RDBFIE0 (Bitfield-Mask: 0x01)                         */
24217  #define R_I3C0_NTIE_IBIQEFIE_Pos       (2UL)          /*!< IBIQEFIE (Bit 2)                                      */
24218  #define R_I3C0_NTIE_IBIQEFIE_Msk       (0x4UL)        /*!< IBIQEFIE (Bitfield-Mask: 0x01)                        */
24219  #define R_I3C0_NTIE_CMDQEIE_Pos        (3UL)          /*!< CMDQEIE (Bit 3)                                       */
24220  #define R_I3C0_NTIE_CMDQEIE_Msk        (0x8UL)        /*!< CMDQEIE (Bitfield-Mask: 0x01)                         */
24221  #define R_I3C0_NTIE_RSPQFIE_Pos        (4UL)          /*!< RSPQFIE (Bit 4)                                       */
24222  #define R_I3C0_NTIE_RSPQFIE_Msk        (0x10UL)       /*!< RSPQFIE (Bitfield-Mask: 0x01)                         */
24223  #define R_I3C0_NTIE_TABTIE_Pos         (5UL)          /*!< TABTIE (Bit 5)                                        */
24224  #define R_I3C0_NTIE_TABTIE_Msk         (0x20UL)       /*!< TABTIE (Bitfield-Mask: 0x01)                          */
24225  #define R_I3C0_NTIE_TEIE_Pos           (9UL)          /*!< TEIE (Bit 9)                                          */
24226  #define R_I3C0_NTIE_TEIE_Msk           (0x200UL)      /*!< TEIE (Bitfield-Mask: 0x01)                            */
24227  #define R_I3C0_NTIE_RSQFIE_Pos         (20UL)         /*!< RSQFIE (Bit 20)                                       */
24228  #define R_I3C0_NTIE_RSQFIE_Msk         (0x100000UL)   /*!< RSQFIE (Bitfield-Mask: 0x01)                          */
24229 /* ========================================================  NTSTFC  ========================================================= */
24230  #define R_I3C0_NTSTFC_TDBEFC0_Pos      (0UL)          /*!< TDBEFC0 (Bit 0)                                       */
24231  #define R_I3C0_NTSTFC_TDBEFC0_Msk      (0x1UL)        /*!< TDBEFC0 (Bitfield-Mask: 0x01)                         */
24232  #define R_I3C0_NTSTFC_RDBFFC0_Pos      (1UL)          /*!< RDBFFC0 (Bit 1)                                       */
24233  #define R_I3C0_NTSTFC_RDBFFC0_Msk      (0x2UL)        /*!< RDBFFC0 (Bitfield-Mask: 0x01)                         */
24234  #define R_I3C0_NTSTFC_IBIQEFFC_Pos     (2UL)          /*!< IBIQEFFC (Bit 2)                                      */
24235  #define R_I3C0_NTSTFC_IBIQEFFC_Msk     (0x4UL)        /*!< IBIQEFFC (Bitfield-Mask: 0x01)                        */
24236  #define R_I3C0_NTSTFC_CMDQEFC_Pos      (3UL)          /*!< CMDQEFC (Bit 3)                                       */
24237  #define R_I3C0_NTSTFC_CMDQEFC_Msk      (0x8UL)        /*!< CMDQEFC (Bitfield-Mask: 0x01)                         */
24238  #define R_I3C0_NTSTFC_RSPQFFC_Pos      (4UL)          /*!< RSPQFFC (Bit 4)                                       */
24239  #define R_I3C0_NTSTFC_RSPQFFC_Msk      (0x10UL)       /*!< RSPQFFC (Bitfield-Mask: 0x01)                         */
24240  #define R_I3C0_NTSTFC_TABTFC_Pos       (5UL)          /*!< TABTFC (Bit 5)                                        */
24241  #define R_I3C0_NTSTFC_TABTFC_Msk       (0x20UL)       /*!< TABTFC (Bitfield-Mask: 0x01)                          */
24242  #define R_I3C0_NTSTFC_TEFC_Pos         (9UL)          /*!< TEFC (Bit 9)                                          */
24243  #define R_I3C0_NTSTFC_TEFC_Msk         (0x200UL)      /*!< TEFC (Bitfield-Mask: 0x01)                            */
24244  #define R_I3C0_NTSTFC_RSQFFC_Pos       (20UL)         /*!< RSQFFC (Bit 20)                                       */
24245  #define R_I3C0_NTSTFC_RSQFFC_Msk       (0x100000UL)   /*!< RSQFFC (Bitfield-Mask: 0x01)                          */
24246 /* =========================================================  BCST  ========================================================== */
24247  #define R_I3C0_BCST_BFREF_Pos          (0UL)          /*!< BFREF (Bit 0)                                         */
24248  #define R_I3C0_BCST_BFREF_Msk          (0x1UL)        /*!< BFREF (Bitfield-Mask: 0x01)                           */
24249  #define R_I3C0_BCST_BAVLF_Pos          (1UL)          /*!< BAVLF (Bit 1)                                         */
24250  #define R_I3C0_BCST_BAVLF_Msk          (0x2UL)        /*!< BAVLF (Bitfield-Mask: 0x01)                           */
24251  #define R_I3C0_BCST_BIDLF_Pos          (2UL)          /*!< BIDLF (Bit 2)                                         */
24252  #define R_I3C0_BCST_BIDLF_Msk          (0x4UL)        /*!< BIDLF (Bitfield-Mask: 0x01)                           */
24253 /* =========================================================  SVST  ========================================================== */
24254  #define R_I3C0_SVST_GCAF_Pos           (0UL)          /*!< GCAF (Bit 0)                                          */
24255  #define R_I3C0_SVST_GCAF_Msk           (0x1UL)        /*!< GCAF (Bitfield-Mask: 0x01)                            */
24256  #define R_I3C0_SVST_HSMCF_Pos          (5UL)          /*!< HSMCF (Bit 5)                                         */
24257  #define R_I3C0_SVST_HSMCF_Msk          (0x20UL)       /*!< HSMCF (Bitfield-Mask: 0x01)                           */
24258  #define R_I3C0_SVST_DVIDF_Pos          (6UL)          /*!< DVIDF (Bit 6)                                         */
24259  #define R_I3C0_SVST_DVIDF_Msk          (0x40UL)       /*!< DVIDF (Bitfield-Mask: 0x01)                           */
24260  #define R_I3C0_SVST_HOAF_Pos           (15UL)         /*!< HOAF (Bit 15)                                         */
24261  #define R_I3C0_SVST_HOAF_Msk           (0x8000UL)     /*!< HOAF (Bitfield-Mask: 0x01)                            */
24262  #define R_I3C0_SVST_SVAFn_Pos          (16UL)         /*!< SVAFn (Bit 16)                                        */
24263  #define R_I3C0_SVST_SVAFn_Msk          (0x10000UL)    /*!< SVAFn (Bitfield-Mask: 0x01)                           */
24264 /* =========================================================  WUST  ========================================================== */
24265  #define R_I3C0_WUST_WUASYNF_Pos        (0UL)          /*!< WUASYNF (Bit 0)                                       */
24266  #define R_I3C0_WUST_WUASYNF_Msk        (0x1UL)        /*!< WUASYNF (Bitfield-Mask: 0x01)                         */
24267 /* ========================================================  DATBAS0  ======================================================== */
24268  #define R_I3C0_DATBAS0_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
24269  #define R_I3C0_DATBAS0_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
24270  #define R_I3C0_DATBAS0_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
24271  #define R_I3C0_DATBAS0_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
24272  #define R_I3C0_DATBAS0_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
24273  #define R_I3C0_DATBAS0_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
24274  #define R_I3C0_DATBAS0_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
24275  #define R_I3C0_DATBAS0_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
24276  #define R_I3C0_DATBAS0_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
24277  #define R_I3C0_DATBAS0_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
24278  #define R_I3C0_DATBAS0_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
24279  #define R_I3C0_DATBAS0_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
24280  #define R_I3C0_DATBAS0_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
24281  #define R_I3C0_DATBAS0_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
24282  #define R_I3C0_DATBAS0_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
24283  #define R_I3C0_DATBAS0_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
24284 /* ========================================================  DATBAS1  ======================================================== */
24285  #define R_I3C0_DATBAS1_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
24286  #define R_I3C0_DATBAS1_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
24287  #define R_I3C0_DATBAS1_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
24288  #define R_I3C0_DATBAS1_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
24289  #define R_I3C0_DATBAS1_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
24290  #define R_I3C0_DATBAS1_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
24291  #define R_I3C0_DATBAS1_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
24292  #define R_I3C0_DATBAS1_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
24293  #define R_I3C0_DATBAS1_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
24294  #define R_I3C0_DATBAS1_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
24295  #define R_I3C0_DATBAS1_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
24296  #define R_I3C0_DATBAS1_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
24297  #define R_I3C0_DATBAS1_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
24298  #define R_I3C0_DATBAS1_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
24299  #define R_I3C0_DATBAS1_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
24300  #define R_I3C0_DATBAS1_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
24301 /* ========================================================  DATBAS2  ======================================================== */
24302  #define R_I3C0_DATBAS2_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
24303  #define R_I3C0_DATBAS2_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
24304  #define R_I3C0_DATBAS2_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
24305  #define R_I3C0_DATBAS2_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
24306  #define R_I3C0_DATBAS2_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
24307  #define R_I3C0_DATBAS2_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
24308  #define R_I3C0_DATBAS2_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
24309  #define R_I3C0_DATBAS2_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
24310  #define R_I3C0_DATBAS2_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
24311  #define R_I3C0_DATBAS2_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
24312  #define R_I3C0_DATBAS2_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
24313  #define R_I3C0_DATBAS2_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
24314  #define R_I3C0_DATBAS2_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
24315  #define R_I3C0_DATBAS2_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
24316  #define R_I3C0_DATBAS2_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
24317  #define R_I3C0_DATBAS2_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
24318 /* ========================================================  DATBAS3  ======================================================== */
24319  #define R_I3C0_DATBAS3_DVSTAD_Pos      (0UL)          /*!< DVSTAD (Bit 0)                                        */
24320  #define R_I3C0_DATBAS3_DVSTAD_Msk      (0x7fUL)       /*!< DVSTAD (Bitfield-Mask: 0x7f)                          */
24321  #define R_I3C0_DATBAS3_DVIBIPL_Pos     (12UL)         /*!< DVIBIPL (Bit 12)                                      */
24322  #define R_I3C0_DATBAS3_DVIBIPL_Msk     (0x1000UL)     /*!< DVIBIPL (Bitfield-Mask: 0x01)                         */
24323  #define R_I3C0_DATBAS3_DVSIRRJ_Pos     (13UL)         /*!< DVSIRRJ (Bit 13)                                      */
24324  #define R_I3C0_DATBAS3_DVSIRRJ_Msk     (0x2000UL)     /*!< DVSIRRJ (Bitfield-Mask: 0x01)                         */
24325  #define R_I3C0_DATBAS3_DVMRRJ_Pos      (14UL)         /*!< DVMRRJ (Bit 14)                                       */
24326  #define R_I3C0_DATBAS3_DVMRRJ_Msk      (0x4000UL)     /*!< DVMRRJ (Bitfield-Mask: 0x01)                          */
24327  #define R_I3C0_DATBAS3_DVIBITS_Pos     (15UL)         /*!< DVIBITS (Bit 15)                                      */
24328  #define R_I3C0_DATBAS3_DVIBITS_Msk     (0x8000UL)     /*!< DVIBITS (Bitfield-Mask: 0x01)                         */
24329  #define R_I3C0_DATBAS3_DVDYAD_Pos      (16UL)         /*!< DVDYAD (Bit 16)                                       */
24330  #define R_I3C0_DATBAS3_DVDYAD_Msk      (0xff0000UL)   /*!< DVDYAD (Bitfield-Mask: 0xff)                          */
24331  #define R_I3C0_DATBAS3_DVNACK_Pos      (29UL)         /*!< DVNACK (Bit 29)                                       */
24332  #define R_I3C0_DATBAS3_DVNACK_Msk      (0x60000000UL) /*!< DVNACK (Bitfield-Mask: 0x03)                          */
24333  #define R_I3C0_DATBAS3_DVTYP_Pos       (31UL)         /*!< DVTYP (Bit 31)                                        */
24334  #define R_I3C0_DATBAS3_DVTYP_Msk       (0x80000000UL) /*!< DVTYP (Bitfield-Mask: 0x01)                           */
24335 /* =======================================================  EXDATBAS  ======================================================== */
24336  #define R_I3C0_EXDATBAS_EDSTAD_Pos     (0UL)          /*!< EDSTAD (Bit 0)                                        */
24337  #define R_I3C0_EXDATBAS_EDSTAD_Msk     (0x7fUL)       /*!< EDSTAD (Bitfield-Mask: 0x7f)                          */
24338  #define R_I3C0_EXDATBAS_EDDYAD_Pos     (16UL)         /*!< EDDYAD (Bit 16)                                       */
24339  #define R_I3C0_EXDATBAS_EDDYAD_Msk     (0xff0000UL)   /*!< EDDYAD (Bitfield-Mask: 0xff)                          */
24340  #define R_I3C0_EXDATBAS_EDNACK_Pos     (29UL)         /*!< EDNACK (Bit 29)                                       */
24341  #define R_I3C0_EXDATBAS_EDNACK_Msk     (0x60000000UL) /*!< EDNACK (Bitfield-Mask: 0x03)                          */
24342  #define R_I3C0_EXDATBAS_EDTYP_Pos      (31UL)         /*!< EDTYP (Bit 31)                                        */
24343  #define R_I3C0_EXDATBAS_EDTYP_Msk      (0x80000000UL) /*!< EDTYP (Bitfield-Mask: 0x01)                           */
24344 /* =======================================================  SDATBAS0  ======================================================== */
24345  #define R_I3C0_SDATBAS0_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
24346  #define R_I3C0_SDATBAS0_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
24347  #define R_I3C0_SDATBAS0_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
24348  #define R_I3C0_SDATBAS0_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
24349  #define R_I3C0_SDATBAS0_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
24350  #define R_I3C0_SDATBAS0_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
24351  #define R_I3C0_SDATBAS0_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
24352  #define R_I3C0_SDATBAS0_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
24353 /* =======================================================  SDATBAS1  ======================================================== */
24354  #define R_I3C0_SDATBAS1_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
24355  #define R_I3C0_SDATBAS1_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
24356  #define R_I3C0_SDATBAS1_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
24357  #define R_I3C0_SDATBAS1_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
24358  #define R_I3C0_SDATBAS1_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
24359  #define R_I3C0_SDATBAS1_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
24360  #define R_I3C0_SDATBAS1_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
24361  #define R_I3C0_SDATBAS1_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
24362 /* =======================================================  SDATBAS2  ======================================================== */
24363  #define R_I3C0_SDATBAS2_SDSTAD_Pos     (0UL)          /*!< SDSTAD (Bit 0)                                        */
24364  #define R_I3C0_SDATBAS2_SDSTAD_Msk     (0x3ffUL)      /*!< SDSTAD (Bitfield-Mask: 0x3ff)                         */
24365  #define R_I3C0_SDATBAS2_SDADLS_Pos     (10UL)         /*!< SDADLS (Bit 10)                                       */
24366  #define R_I3C0_SDATBAS2_SDADLS_Msk     (0x400UL)      /*!< SDADLS (Bitfield-Mask: 0x01)                          */
24367  #define R_I3C0_SDATBAS2_SDIBIPL_Pos    (12UL)         /*!< SDIBIPL (Bit 12)                                      */
24368  #define R_I3C0_SDATBAS2_SDIBIPL_Msk    (0x1000UL)     /*!< SDIBIPL (Bitfield-Mask: 0x01)                         */
24369  #define R_I3C0_SDATBAS2_SDDYAD_Pos     (16UL)         /*!< SDDYAD (Bit 16)                                       */
24370  #define R_I3C0_SDATBAS2_SDDYAD_Msk     (0x7f0000UL)   /*!< SDDYAD (Bitfield-Mask: 0x7f)                          */
24371 /* ========================================================  MSDCT0  ========================================================= */
24372  #define R_I3C0_MSDCT0_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
24373  #define R_I3C0_MSDCT0_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
24374  #define R_I3C0_MSDCT0_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
24375  #define R_I3C0_MSDCT0_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
24376  #define R_I3C0_MSDCT0_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
24377  #define R_I3C0_MSDCT0_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
24378  #define R_I3C0_MSDCT0_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
24379  #define R_I3C0_MSDCT0_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
24380  #define R_I3C0_MSDCT0_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
24381  #define R_I3C0_MSDCT0_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
24382 /* ========================================================  MSDCT1  ========================================================= */
24383  #define R_I3C0_MSDCT1_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
24384  #define R_I3C0_MSDCT1_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
24385  #define R_I3C0_MSDCT1_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
24386  #define R_I3C0_MSDCT1_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
24387  #define R_I3C0_MSDCT1_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
24388  #define R_I3C0_MSDCT1_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
24389  #define R_I3C0_MSDCT1_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
24390  #define R_I3C0_MSDCT1_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
24391  #define R_I3C0_MSDCT1_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
24392  #define R_I3C0_MSDCT1_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
24393 /* ========================================================  MSDCT2  ========================================================= */
24394  #define R_I3C0_MSDCT2_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
24395  #define R_I3C0_MSDCT2_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
24396  #define R_I3C0_MSDCT2_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
24397  #define R_I3C0_MSDCT2_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
24398  #define R_I3C0_MSDCT2_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
24399  #define R_I3C0_MSDCT2_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
24400  #define R_I3C0_MSDCT2_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
24401  #define R_I3C0_MSDCT2_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
24402  #define R_I3C0_MSDCT2_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
24403  #define R_I3C0_MSDCT2_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
24404 /* ========================================================  MSDCT3  ========================================================= */
24405  #define R_I3C0_MSDCT3_RBCR0_Pos        (8UL)          /*!< RBCR0 (Bit 8)                                         */
24406  #define R_I3C0_MSDCT3_RBCR0_Msk        (0x100UL)      /*!< RBCR0 (Bitfield-Mask: 0x01)                           */
24407  #define R_I3C0_MSDCT3_RBCR1_Pos        (9UL)          /*!< RBCR1 (Bit 9)                                         */
24408  #define R_I3C0_MSDCT3_RBCR1_Msk        (0x200UL)      /*!< RBCR1 (Bitfield-Mask: 0x01)                           */
24409  #define R_I3C0_MSDCT3_RBCR2_Pos        (10UL)         /*!< RBCR2 (Bit 10)                                        */
24410  #define R_I3C0_MSDCT3_RBCR2_Msk        (0x400UL)      /*!< RBCR2 (Bitfield-Mask: 0x01)                           */
24411  #define R_I3C0_MSDCT3_RBCR3_Pos        (11UL)         /*!< RBCR3 (Bit 11)                                        */
24412  #define R_I3C0_MSDCT3_RBCR3_Msk        (0x800UL)      /*!< RBCR3 (Bitfield-Mask: 0x01)                           */
24413  #define R_I3C0_MSDCT3_RBCR76_Pos       (14UL)         /*!< RBCR76 (Bit 14)                                       */
24414  #define R_I3C0_MSDCT3_RBCR76_Msk       (0xc000UL)     /*!< RBCR76 (Bitfield-Mask: 0x03)                          */
24415 /* =========================================================  SVDCT  ========================================================= */
24416  #define R_I3C0_SVDCT_TDCR_Pos          (0UL)          /*!< TDCR (Bit 0)                                          */
24417  #define R_I3C0_SVDCT_TDCR_Msk          (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
24418  #define R_I3C0_SVDCT_TBCR0_Pos         (8UL)          /*!< TBCR0 (Bit 8)                                         */
24419  #define R_I3C0_SVDCT_TBCR0_Msk         (0x100UL)      /*!< TBCR0 (Bitfield-Mask: 0x01)                           */
24420  #define R_I3C0_SVDCT_TBCR1_Pos         (9UL)          /*!< TBCR1 (Bit 9)                                         */
24421  #define R_I3C0_SVDCT_TBCR1_Msk         (0x200UL)      /*!< TBCR1 (Bitfield-Mask: 0x01)                           */
24422  #define R_I3C0_SVDCT_TBCR2_Pos         (10UL)         /*!< TBCR2 (Bit 10)                                        */
24423  #define R_I3C0_SVDCT_TBCR2_Msk         (0x400UL)      /*!< TBCR2 (Bitfield-Mask: 0x01)                           */
24424  #define R_I3C0_SVDCT_TBCR3_Pos         (11UL)         /*!< TBCR3 (Bit 11)                                        */
24425  #define R_I3C0_SVDCT_TBCR3_Msk         (0x800UL)      /*!< TBCR3 (Bitfield-Mask: 0x01)                           */
24426  #define R_I3C0_SVDCT_TBCR76_Pos        (14UL)         /*!< TBCR76 (Bit 14)                                       */
24427  #define R_I3C0_SVDCT_TBCR76_Msk        (0xc000UL)     /*!< TBCR76 (Bitfield-Mask: 0x03)                          */
24428 /* =======================================================  SDCTPIDL  ======================================================== */
24429 /* =======================================================  SDCTPIDH  ======================================================== */
24430 /* ========================================================  SVDVAD0  ======================================================== */
24431  #define R_I3C0_SVDVAD0_SVAD_Pos        (16UL)         /*!< SVAD (Bit 16)                                         */
24432  #define R_I3C0_SVDVAD0_SVAD_Msk        (0x3ff0000UL)  /*!< SVAD (Bitfield-Mask: 0x3ff)                           */
24433  #define R_I3C0_SVDVAD0_SADLG_Pos       (27UL)         /*!< SADLG (Bit 27)                                        */
24434  #define R_I3C0_SVDVAD0_SADLG_Msk       (0x8000000UL)  /*!< SADLG (Bitfield-Mask: 0x01)                           */
24435  #define R_I3C0_SVDVAD0_SSTADV_Pos      (30UL)         /*!< SSTADV (Bit 30)                                       */
24436  #define R_I3C0_SVDVAD0_SSTADV_Msk      (0x40000000UL) /*!< SSTADV (Bitfield-Mask: 0x01)                          */
24437  #define R_I3C0_SVDVAD0_SDYADV_Pos      (31UL)         /*!< SDYADV (Bit 31)                                       */
24438  #define R_I3C0_SVDVAD0_SDYADV_Msk      (0x80000000UL) /*!< SDYADV (Bitfield-Mask: 0x01)                          */
24439 /* ========================================================  CSECMD  ========================================================= */
24440  #define R_I3C0_CSECMD_SVIRQE_Pos       (0UL)          /*!< SVIRQE (Bit 0)                                        */
24441  #define R_I3C0_CSECMD_SVIRQE_Msk       (0x1UL)        /*!< SVIRQE (Bitfield-Mask: 0x01)                          */
24442  #define R_I3C0_CSECMD_MSRQE_Pos        (1UL)          /*!< MSRQE (Bit 1)                                         */
24443  #define R_I3C0_CSECMD_MSRQE_Msk        (0x2UL)        /*!< MSRQE (Bitfield-Mask: 0x01)                           */
24444  #define R_I3C0_CSECMD_HJEVE_Pos        (3UL)          /*!< HJEVE (Bit 3)                                         */
24445  #define R_I3C0_CSECMD_HJEVE_Msk        (0x8UL)        /*!< HJEVE (Bitfield-Mask: 0x01)                           */
24446 /* ========================================================  CEACTST  ======================================================== */
24447  #define R_I3C0_CEACTST_ACTST_Pos       (0UL)          /*!< ACTST (Bit 0)                                         */
24448  #define R_I3C0_CEACTST_ACTST_Msk       (0xfUL)        /*!< ACTST (Bitfield-Mask: 0x0f)                           */
24449 /* =========================================================  CMWLG  ========================================================= */
24450  #define R_I3C0_CMWLG_MWLG_Pos          (0UL)          /*!< MWLG (Bit 0)                                          */
24451  #define R_I3C0_CMWLG_MWLG_Msk          (0xffffUL)     /*!< MWLG (Bitfield-Mask: 0xffff)                          */
24452 /* =========================================================  CMRLG  ========================================================= */
24453  #define R_I3C0_CMRLG_MRLG_Pos          (0UL)          /*!< MRLG (Bit 0)                                          */
24454  #define R_I3C0_CMRLG_MRLG_Msk          (0xffffUL)     /*!< MRLG (Bitfield-Mask: 0xffff)                          */
24455  #define R_I3C0_CMRLG_IBIPSZ_Pos        (16UL)         /*!< IBIPSZ (Bit 16)                                       */
24456  #define R_I3C0_CMRLG_IBIPSZ_Msk        (0xff0000UL)   /*!< IBIPSZ (Bitfield-Mask: 0xff)                          */
24457 /* ========================================================  CETSTMD  ======================================================== */
24458  #define R_I3C0_CETSTMD_TSTMD_Pos       (0UL)          /*!< TSTMD (Bit 0)                                         */
24459  #define R_I3C0_CETSTMD_TSTMD_Msk       (0xffUL)       /*!< TSTMD (Bitfield-Mask: 0xff)                           */
24460 /* ========================================================  CGDVST  ========================================================= */
24461  #define R_I3C0_CGDVST_PNDINT_Pos       (0UL)          /*!< PNDINT (Bit 0)                                        */
24462  #define R_I3C0_CGDVST_PNDINT_Msk       (0xfUL)        /*!< PNDINT (Bitfield-Mask: 0x0f)                          */
24463  #define R_I3C0_CGDVST_PRTE_Pos         (5UL)          /*!< PRTE (Bit 5)                                          */
24464  #define R_I3C0_CGDVST_PRTE_Msk         (0x20UL)       /*!< PRTE (Bitfield-Mask: 0x01)                            */
24465  #define R_I3C0_CGDVST_ACTMD_Pos        (6UL)          /*!< ACTMD (Bit 6)                                         */
24466  #define R_I3C0_CGDVST_ACTMD_Msk        (0xc0UL)       /*!< ACTMD (Bitfield-Mask: 0x03)                           */
24467  #define R_I3C0_CGDVST_VDRSV_Pos        (8UL)          /*!< VDRSV (Bit 8)                                         */
24468  #define R_I3C0_CGDVST_VDRSV_Msk        (0xff00UL)     /*!< VDRSV (Bitfield-Mask: 0xff)                           */
24469 /* ========================================================  CMDSPW  ========================================================= */
24470  #define R_I3C0_CMDSPW_MSWDR_Pos        (0UL)          /*!< MSWDR (Bit 0)                                         */
24471  #define R_I3C0_CMDSPW_MSWDR_Msk        (0x7UL)        /*!< MSWDR (Bitfield-Mask: 0x07)                           */
24472 /* ========================================================  CMDSPR  ========================================================= */
24473  #define R_I3C0_CMDSPR_MSRDR_Pos        (0UL)          /*!< MSRDR (Bit 0)                                         */
24474  #define R_I3C0_CMDSPR_MSRDR_Msk        (0x7UL)        /*!< MSRDR (Bitfield-Mask: 0x07)                           */
24475  #define R_I3C0_CMDSPR_CDTTIM_Pos       (3UL)          /*!< CDTTIM (Bit 3)                                        */
24476  #define R_I3C0_CMDSPR_CDTTIM_Msk       (0x38UL)       /*!< CDTTIM (Bitfield-Mask: 0x07)                          */
24477 /* ========================================================  CMDSPT  ========================================================= */
24478  #define R_I3C0_CMDSPT_MRTTIM_Pos       (0UL)          /*!< MRTTIM (Bit 0)                                        */
24479  #define R_I3C0_CMDSPT_MRTTIM_Msk       (0xffffffUL)   /*!< MRTTIM (Bitfield-Mask: 0xffffff)                      */
24480  #define R_I3C0_CMDSPT_MRTE_Pos         (31UL)         /*!< MRTE (Bit 31)                                         */
24481  #define R_I3C0_CMDSPT_MRTE_Msk         (0x80000000UL) /*!< MRTE (Bitfield-Mask: 0x01)                            */
24482 /* =========================================================  CETSM  ========================================================= */
24483  #define R_I3C0_CETSM_FREQ_Pos          (8UL)          /*!< FREQ (Bit 8)                                          */
24484  #define R_I3C0_CETSM_FREQ_Msk          (0xff00UL)     /*!< FREQ (Bitfield-Mask: 0xff)                            */
24485  #define R_I3C0_CETSM_INAC_Pos          (16UL)         /*!< INAC (Bit 16)                                         */
24486  #define R_I3C0_CETSM_INAC_Msk          (0xff0000UL)   /*!< INAC (Bitfield-Mask: 0xff)                            */
24487 /* ========================================================  BITCNT  ========================================================= */
24488  #define R_I3C0_BITCNT_BCNT_Pos         (0UL)          /*!< BCNT (Bit 0)                                          */
24489  #define R_I3C0_BITCNT_BCNT_Msk         (0x1fUL)       /*!< BCNT (Bitfield-Mask: 0x1f)                            */
24490  #define R_I3C0_BITCNT_BCNTWP_Pos       (7UL)          /*!< BCNTWP (Bit 7)                                        */
24491  #define R_I3C0_BITCNT_BCNTWP_Msk       (0x80UL)       /*!< BCNTWP (Bitfield-Mask: 0x01)                          */
24492 /* ========================================================  NQSTLV  ========================================================= */
24493  #define R_I3C0_NQSTLV_CMDQFLV_Pos      (0UL)          /*!< CMDQFLV (Bit 0)                                       */
24494  #define R_I3C0_NQSTLV_CMDQFLV_Msk      (0xffUL)       /*!< CMDQFLV (Bitfield-Mask: 0xff)                         */
24495  #define R_I3C0_NQSTLV_RSPQLV_Pos       (8UL)          /*!< RSPQLV (Bit 8)                                        */
24496  #define R_I3C0_NQSTLV_RSPQLV_Msk       (0xff00UL)     /*!< RSPQLV (Bitfield-Mask: 0xff)                          */
24497  #define R_I3C0_NQSTLV_IBIQLV_Pos       (16UL)         /*!< IBIQLV (Bit 16)                                       */
24498  #define R_I3C0_NQSTLV_IBIQLV_Msk       (0xff0000UL)   /*!< IBIQLV (Bitfield-Mask: 0xff)                          */
24499  #define R_I3C0_NQSTLV_IBISCNT_Pos      (24UL)         /*!< IBISCNT (Bit 24)                                      */
24500  #define R_I3C0_NQSTLV_IBISCNT_Msk      (0x1f000000UL) /*!< IBISCNT (Bitfield-Mask: 0x1f)                         */
24501 /* =======================================================  NDBSTLV0  ======================================================== */
24502  #define R_I3C0_NDBSTLV0_TDBFLV_Pos     (0UL)          /*!< TDBFLV (Bit 0)                                        */
24503  #define R_I3C0_NDBSTLV0_TDBFLV_Msk     (0xffUL)       /*!< TDBFLV (Bitfield-Mask: 0xff)                          */
24504  #define R_I3C0_NDBSTLV0_RDBLV_Pos      (8UL)          /*!< RDBLV (Bit 8)                                         */
24505  #define R_I3C0_NDBSTLV0_RDBLV_Msk      (0xff00UL)     /*!< RDBLV (Bitfield-Mask: 0xff)                           */
24506 /* =======================================================  NRSQSTLV  ======================================================== */
24507  #define R_I3C0_NRSQSTLV_RSQLV_Pos      (0UL)          /*!< RSQLV (Bit 0)                                         */
24508  #define R_I3C0_NRSQSTLV_RSQLV_Msk      (0xffUL)       /*!< RSQLV (Bitfield-Mask: 0xff)                           */
24509 /* ========================================================  PRSTDBG  ======================================================== */
24510  #define R_I3C0_PRSTDBG_SCILV_Pos       (0UL)          /*!< SCILV (Bit 0)                                         */
24511  #define R_I3C0_PRSTDBG_SCILV_Msk       (0x1UL)        /*!< SCILV (Bitfield-Mask: 0x01)                           */
24512  #define R_I3C0_PRSTDBG_SDILV_Pos       (1UL)          /*!< SDILV (Bit 1)                                         */
24513  #define R_I3C0_PRSTDBG_SDILV_Msk       (0x2UL)        /*!< SDILV (Bitfield-Mask: 0x01)                           */
24514  #define R_I3C0_PRSTDBG_SCOLV_Pos       (2UL)          /*!< SCOLV (Bit 2)                                         */
24515  #define R_I3C0_PRSTDBG_SCOLV_Msk       (0x4UL)        /*!< SCOLV (Bitfield-Mask: 0x01)                           */
24516  #define R_I3C0_PRSTDBG_SDOLV_Pos       (3UL)          /*!< SDOLV (Bit 3)                                         */
24517  #define R_I3C0_PRSTDBG_SDOLV_Msk       (0x8UL)        /*!< SDOLV (Bitfield-Mask: 0x01)                           */
24518 /* =======================================================  MSERRCNT  ======================================================== */
24519  #define R_I3C0_MSERRCNT_M2ECNT_Pos     (0UL)          /*!< M2ECNT (Bit 0)                                        */
24520  #define R_I3C0_MSERRCNT_M2ECNT_Msk     (0xffUL)       /*!< M2ECNT (Bitfield-Mask: 0xff)                          */
24521 
24522 /* =========================================================================================================================== */
24523 /* ================                                        R_MPU_MMPU                                         ================ */
24524 /* =========================================================================================================================== */
24525 
24526 /* ==========================================================  OAD  ========================================================== */
24527  #define R_MPU_MMPU_OAD_KEY_Pos          (8UL)      /*!< KEY (Bit 8)                                           */
24528  #define R_MPU_MMPU_OAD_KEY_Msk          (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
24529  #define R_MPU_MMPU_OAD_OAD_Pos          (0UL)      /*!< OAD (Bit 0)                                           */
24530  #define R_MPU_MMPU_OAD_OAD_Msk          (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
24531 /* =========================================================  OADPT  ========================================================= */
24532  #define R_MPU_MMPU_OADPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
24533  #define R_MPU_MMPU_OADPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
24534  #define R_MPU_MMPU_OADPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
24535  #define R_MPU_MMPU_OADPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
24536 
24537 /* =========================================================================================================================== */
24538 /* ================                                        R_MPU_SPMON                                        ================ */
24539 /* =========================================================================================================================== */
24540 
24541 /* =========================================================================================================================== */
24542 /* ================                                          R_MSTP                                           ================ */
24543 /* =========================================================================================================================== */
24544 
24545 /* ========================================================  MSTPCRA  ======================================================== */
24546  #define R_MSTP_MSTPCRA_MSTPA_Pos        (0UL)      /*!< MSTPA (Bit 0)                                         */
24547  #define R_MSTP_MSTPCRA_MSTPA_Msk        (0x1UL)    /*!< MSTPA (Bitfield-Mask: 0x01)                           */
24548 /* ========================================================  MSTPCRB  ======================================================== */
24549  #define R_MSTP_MSTPCRB_MSTPB_Pos        (0UL)      /*!< MSTPB (Bit 0)                                         */
24550  #define R_MSTP_MSTPCRB_MSTPB_Msk        (0x1UL)    /*!< MSTPB (Bitfield-Mask: 0x01)                           */
24551 /* ========================================================  MSTPCRC  ======================================================== */
24552  #define R_MSTP_MSTPCRC_MSTPC_Pos        (0UL)      /*!< MSTPC (Bit 0)                                         */
24553  #define R_MSTP_MSTPCRC_MSTPC_Msk        (0x1UL)    /*!< MSTPC (Bitfield-Mask: 0x01)                           */
24554 /* ========================================================  MSTPCRD  ======================================================== */
24555  #define R_MSTP_MSTPCRD_MSTPD_Pos        (0UL)      /*!< MSTPD (Bit 0)                                         */
24556  #define R_MSTP_MSTPCRD_MSTPD_Msk        (0x1UL)    /*!< MSTPD (Bitfield-Mask: 0x01)                           */
24557 /* ========================================================  MSTPCRE  ======================================================== */
24558  #define R_MSTP_MSTPCRE_MSTPE_Pos        (0UL)      /*!< MSTPE (Bit 0)                                         */
24559  #define R_MSTP_MSTPCRE_MSTPE_Msk        (0x1UL)    /*!< MSTPE (Bitfield-Mask: 0x01)                           */
24560 /* =======================================================  LSMRWDIS  ======================================================== */
24561  #define R_MSTP_LSMRWDIS_RTCRWDIS_Pos    (0UL)      /*!< RTCRWDIS (Bit 0)                                      */
24562  #define R_MSTP_LSMRWDIS_RTCRWDIS_Msk    (0x1UL)    /*!< RTCRWDIS (Bitfield-Mask: 0x01)                        */
24563  #define R_MSTP_LSMRWDIS_WDTDIS_Pos      (1UL)      /*!< WDTDIS (Bit 1)                                        */
24564  #define R_MSTP_LSMRWDIS_WDTDIS_Msk      (0x2UL)    /*!< WDTDIS (Bitfield-Mask: 0x01)                          */
24565  #define R_MSTP_LSMRWDIS_IWDTIDS_Pos     (2UL)      /*!< IWDTIDS (Bit 2)                                       */
24566  #define R_MSTP_LSMRWDIS_IWDTIDS_Msk     (0x4UL)    /*!< IWDTIDS (Bitfield-Mask: 0x01)                         */
24567  #define R_MSTP_LSMRWDIS_WREN_Pos        (7UL)      /*!< WREN (Bit 7)                                          */
24568  #define R_MSTP_LSMRWDIS_WREN_Msk        (0x80UL)   /*!< WREN (Bitfield-Mask: 0x01)                            */
24569  #define R_MSTP_LSMRWDIS_PRKEY_Pos       (8UL)      /*!< PRKEY (Bit 8)                                         */
24570  #define R_MSTP_LSMRWDIS_PRKEY_Msk       (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
24571 
24572 /* =========================================================================================================================== */
24573 /* ================                                          R_PORT0                                          ================ */
24574 /* =========================================================================================================================== */
24575 
24576 /* ========================================================  PCNTR1  ========================================================= */
24577  #define R_PORT0_PCNTR1_PODR_Pos    (16UL)         /*!< PODR (Bit 16)                                         */
24578  #define R_PORT0_PCNTR1_PODR_Msk    (0xffff0000UL) /*!< PODR (Bitfield-Mask: 0xffff)                          */
24579  #define R_PORT0_PCNTR1_PDR_Pos     (0UL)          /*!< PDR (Bit 0)                                           */
24580  #define R_PORT0_PCNTR1_PDR_Msk     (0xffffUL)     /*!< PDR (Bitfield-Mask: 0xffff)                           */
24581 /* =========================================================  PODR  ========================================================== */
24582  #define R_PORT0_PODR_PODR_Pos      (0UL)          /*!< PODR (Bit 0)                                          */
24583  #define R_PORT0_PODR_PODR_Msk      (0x1UL)        /*!< PODR (Bitfield-Mask: 0x01)                            */
24584 /* ==========================================================  PDR  ========================================================== */
24585  #define R_PORT0_PDR_PDR_Pos        (0UL)          /*!< PDR (Bit 0)                                           */
24586  #define R_PORT0_PDR_PDR_Msk        (0x1UL)        /*!< PDR (Bitfield-Mask: 0x01)                             */
24587 /* ========================================================  PCNTR2  ========================================================= */
24588  #define R_PORT0_PCNTR2_EIDR_Pos    (16UL)         /*!< EIDR (Bit 16)                                         */
24589  #define R_PORT0_PCNTR2_EIDR_Msk    (0xffff0000UL) /*!< EIDR (Bitfield-Mask: 0xffff)                          */
24590  #define R_PORT0_PCNTR2_PIDR_Pos    (0UL)          /*!< PIDR (Bit 0)                                          */
24591  #define R_PORT0_PCNTR2_PIDR_Msk    (0xffffUL)     /*!< PIDR (Bitfield-Mask: 0xffff)                          */
24592 /* =========================================================  EIDR  ========================================================== */
24593  #define R_PORT0_EIDR_EIDR_Pos      (0UL)          /*!< EIDR (Bit 0)                                          */
24594  #define R_PORT0_EIDR_EIDR_Msk      (0x1UL)        /*!< EIDR (Bitfield-Mask: 0x01)                            */
24595 /* =========================================================  PIDR  ========================================================== */
24596  #define R_PORT0_PIDR_PIDR_Pos      (0UL)          /*!< PIDR (Bit 0)                                          */
24597  #define R_PORT0_PIDR_PIDR_Msk      (0x1UL)        /*!< PIDR (Bitfield-Mask: 0x01)                            */
24598 /* ========================================================  PCNTR3  ========================================================= */
24599  #define R_PORT0_PCNTR3_PORR_Pos    (16UL)         /*!< PORR (Bit 16)                                         */
24600  #define R_PORT0_PCNTR3_PORR_Msk    (0xffff0000UL) /*!< PORR (Bitfield-Mask: 0xffff)                          */
24601  #define R_PORT0_PCNTR3_POSR_Pos    (0UL)          /*!< POSR (Bit 0)                                          */
24602  #define R_PORT0_PCNTR3_POSR_Msk    (0xffffUL)     /*!< POSR (Bitfield-Mask: 0xffff)                          */
24603 /* =========================================================  PORR  ========================================================== */
24604  #define R_PORT0_PORR_PORR_Pos      (0UL)          /*!< PORR (Bit 0)                                          */
24605  #define R_PORT0_PORR_PORR_Msk      (0x1UL)        /*!< PORR (Bitfield-Mask: 0x01)                            */
24606 /* =========================================================  POSR  ========================================================== */
24607  #define R_PORT0_POSR_POSR_Pos      (0UL)          /*!< POSR (Bit 0)                                          */
24608  #define R_PORT0_POSR_POSR_Msk      (0x1UL)        /*!< POSR (Bitfield-Mask: 0x01)                            */
24609 /* ========================================================  PCNTR4  ========================================================= */
24610  #define R_PORT0_PCNTR4_EORR_Pos    (16UL)         /*!< EORR (Bit 16)                                         */
24611  #define R_PORT0_PCNTR4_EORR_Msk    (0xffff0000UL) /*!< EORR (Bitfield-Mask: 0xffff)                          */
24612  #define R_PORT0_PCNTR4_EOSR_Pos    (0UL)          /*!< EOSR (Bit 0)                                          */
24613  #define R_PORT0_PCNTR4_EOSR_Msk    (0xffffUL)     /*!< EOSR (Bitfield-Mask: 0xffff)                          */
24614 /* =========================================================  EORR  ========================================================== */
24615  #define R_PORT0_EORR_EORR_Pos      (0UL)          /*!< EORR (Bit 0)                                          */
24616  #define R_PORT0_EORR_EORR_Msk      (0x1UL)        /*!< EORR (Bitfield-Mask: 0x01)                            */
24617 /* =========================================================  EOSR  ========================================================== */
24618  #define R_PORT0_EOSR_EOSR_Pos      (0UL)          /*!< EOSR (Bit 0)                                          */
24619  #define R_PORT0_EOSR_EOSR_Msk      (0x1UL)        /*!< EOSR (Bitfield-Mask: 0x01)                            */
24620 
24621 /* =========================================================================================================================== */
24622 /* ================                                           R_PFS                                           ================ */
24623 /* =========================================================================================================================== */
24624 
24625 /* =========================================================================================================================== */
24626 /* ================                                          R_PMISC                                          ================ */
24627 /* =========================================================================================================================== */
24628 
24629 /* ========================================================  PFENET  ========================================================= */
24630  #define R_PMISC_PFENET_PHYMODE1_Pos    (5UL)    /*!< PHYMODE1 (Bit 5)                                      */
24631  #define R_PMISC_PFENET_PHYMODE1_Msk    (0x20UL) /*!< PHYMODE1 (Bitfield-Mask: 0x01)                        */
24632  #define R_PMISC_PFENET_PHYMODE0_Pos    (4UL)    /*!< PHYMODE0 (Bit 4)                                      */
24633  #define R_PMISC_PFENET_PHYMODE0_Msk    (0x10UL) /*!< PHYMODE0 (Bitfield-Mask: 0x01)                        */
24634 /* =========================================================  PWPR  ========================================================== */
24635  #define R_PMISC_PWPR_PFSWE_Pos         (6UL)    /*!< PFSWE (Bit 6)                                         */
24636  #define R_PMISC_PWPR_PFSWE_Msk         (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
24637  #define R_PMISC_PWPR_B0WI_Pos          (7UL)    /*!< B0WI (Bit 7)                                          */
24638  #define R_PMISC_PWPR_B0WI_Msk          (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
24639 /* =========================================================  PWPRS  ========================================================= */
24640  #define R_PMISC_PWPRS_PFSWE_Pos        (6UL)    /*!< PFSWE (Bit 6)                                         */
24641  #define R_PMISC_PWPRS_PFSWE_Msk        (0x40UL) /*!< PFSWE (Bitfield-Mask: 0x01)                           */
24642  #define R_PMISC_PWPRS_B0WI_Pos         (7UL)    /*!< B0WI (Bit 7)                                          */
24643  #define R_PMISC_PWPRS_B0WI_Msk         (0x80UL) /*!< B0WI (Bitfield-Mask: 0x01)                            */
24644 /* ========================================================  PRWCNTR  ======================================================== */
24645  #define R_PMISC_PRWCNTR_WAIT_Pos       (0UL)    /*!< WAIT (Bit 0)                                          */
24646  #define R_PMISC_PRWCNTR_WAIT_Msk       (0x3UL)  /*!< WAIT (Bitfield-Mask: 0x03)                            */
24647 
24648 /* =========================================================================================================================== */
24649 /* ================                                          R_QSPI                                           ================ */
24650 /* =========================================================================================================================== */
24651 
24652 /* ========================================================  SFMSMD  ========================================================= */
24653  #define R_QSPI_SFMSMD_SFMCCE_Pos       (15UL)         /*!< SFMCCE (Bit 15)                                       */
24654  #define R_QSPI_SFMSMD_SFMCCE_Msk       (0x8000UL)     /*!< SFMCCE (Bitfield-Mask: 0x01)                          */
24655  #define R_QSPI_SFMSMD_SFMOSW_Pos       (11UL)         /*!< SFMOSW (Bit 11)                                       */
24656  #define R_QSPI_SFMSMD_SFMOSW_Msk       (0x800UL)      /*!< SFMOSW (Bitfield-Mask: 0x01)                          */
24657  #define R_QSPI_SFMSMD_SFMOHW_Pos       (10UL)         /*!< SFMOHW (Bit 10)                                       */
24658  #define R_QSPI_SFMSMD_SFMOHW_Msk       (0x400UL)      /*!< SFMOHW (Bitfield-Mask: 0x01)                          */
24659  #define R_QSPI_SFMSMD_SFMOEX_Pos       (9UL)          /*!< SFMOEX (Bit 9)                                        */
24660  #define R_QSPI_SFMSMD_SFMOEX_Msk       (0x200UL)      /*!< SFMOEX (Bitfield-Mask: 0x01)                          */
24661  #define R_QSPI_SFMSMD_SFMMD3_Pos       (8UL)          /*!< SFMMD3 (Bit 8)                                        */
24662  #define R_QSPI_SFMSMD_SFMMD3_Msk       (0x100UL)      /*!< SFMMD3 (Bitfield-Mask: 0x01)                          */
24663  #define R_QSPI_SFMSMD_SFMPAE_Pos       (7UL)          /*!< SFMPAE (Bit 7)                                        */
24664  #define R_QSPI_SFMSMD_SFMPAE_Msk       (0x80UL)       /*!< SFMPAE (Bitfield-Mask: 0x01)                          */
24665  #define R_QSPI_SFMSMD_SFMPFE_Pos       (6UL)          /*!< SFMPFE (Bit 6)                                        */
24666  #define R_QSPI_SFMSMD_SFMPFE_Msk       (0x40UL)       /*!< SFMPFE (Bitfield-Mask: 0x01)                          */
24667  #define R_QSPI_SFMSMD_SFMSE_Pos        (4UL)          /*!< SFMSE (Bit 4)                                         */
24668  #define R_QSPI_SFMSMD_SFMSE_Msk        (0x30UL)       /*!< SFMSE (Bitfield-Mask: 0x03)                           */
24669  #define R_QSPI_SFMSMD_SFMRM_Pos        (0UL)          /*!< SFMRM (Bit 0)                                         */
24670  #define R_QSPI_SFMSMD_SFMRM_Msk        (0x7UL)        /*!< SFMRM (Bitfield-Mask: 0x07)                           */
24671 /* ========================================================  SFMSSC  ========================================================= */
24672  #define R_QSPI_SFMSSC_SFMSLD_Pos       (5UL)          /*!< SFMSLD (Bit 5)                                        */
24673  #define R_QSPI_SFMSSC_SFMSLD_Msk       (0x20UL)       /*!< SFMSLD (Bitfield-Mask: 0x01)                          */
24674  #define R_QSPI_SFMSSC_SFMSHD_Pos       (4UL)          /*!< SFMSHD (Bit 4)                                        */
24675  #define R_QSPI_SFMSSC_SFMSHD_Msk       (0x10UL)       /*!< SFMSHD (Bitfield-Mask: 0x01)                          */
24676  #define R_QSPI_SFMSSC_SFMSW_Pos        (0UL)          /*!< SFMSW (Bit 0)                                         */
24677  #define R_QSPI_SFMSSC_SFMSW_Msk        (0xfUL)        /*!< SFMSW (Bitfield-Mask: 0x0f)                           */
24678 /* ========================================================  SFMSKC  ========================================================= */
24679  #define R_QSPI_SFMSKC_SFMDTY_Pos       (5UL)          /*!< SFMDTY (Bit 5)                                        */
24680  #define R_QSPI_SFMSKC_SFMDTY_Msk       (0x20UL)       /*!< SFMDTY (Bitfield-Mask: 0x01)                          */
24681  #define R_QSPI_SFMSKC_SFMDV_Pos        (0UL)          /*!< SFMDV (Bit 0)                                         */
24682  #define R_QSPI_SFMSKC_SFMDV_Msk        (0x1fUL)       /*!< SFMDV (Bitfield-Mask: 0x1f)                           */
24683 /* ========================================================  SFMSST  ========================================================= */
24684  #define R_QSPI_SFMSST_PFOFF_Pos        (7UL)          /*!< PFOFF (Bit 7)                                         */
24685  #define R_QSPI_SFMSST_PFOFF_Msk        (0x80UL)       /*!< PFOFF (Bitfield-Mask: 0x01)                           */
24686  #define R_QSPI_SFMSST_PFFUL_Pos        (6UL)          /*!< PFFUL (Bit 6)                                         */
24687  #define R_QSPI_SFMSST_PFFUL_Msk        (0x40UL)       /*!< PFFUL (Bitfield-Mask: 0x01)                           */
24688  #define R_QSPI_SFMSST_PFCNT_Pos        (0UL)          /*!< PFCNT (Bit 0)                                         */
24689  #define R_QSPI_SFMSST_PFCNT_Msk        (0x1fUL)       /*!< PFCNT (Bitfield-Mask: 0x1f)                           */
24690 /* ========================================================  SFMCOM  ========================================================= */
24691  #define R_QSPI_SFMCOM_SFMD_Pos         (0UL)          /*!< SFMD (Bit 0)                                          */
24692  #define R_QSPI_SFMCOM_SFMD_Msk         (0xffUL)       /*!< SFMD (Bitfield-Mask: 0xff)                            */
24693 /* ========================================================  SFMCMD  ========================================================= */
24694  #define R_QSPI_SFMCMD_DCOM_Pos         (0UL)          /*!< DCOM (Bit 0)                                          */
24695  #define R_QSPI_SFMCMD_DCOM_Msk         (0x1UL)        /*!< DCOM (Bitfield-Mask: 0x01)                            */
24696 /* ========================================================  SFMCST  ========================================================= */
24697  #define R_QSPI_SFMCST_EROMR_Pos        (7UL)          /*!< EROMR (Bit 7)                                         */
24698  #define R_QSPI_SFMCST_EROMR_Msk        (0x80UL)       /*!< EROMR (Bitfield-Mask: 0x01)                           */
24699  #define R_QSPI_SFMCST_COMBSY_Pos       (0UL)          /*!< COMBSY (Bit 0)                                        */
24700  #define R_QSPI_SFMCST_COMBSY_Msk       (0x1UL)        /*!< COMBSY (Bitfield-Mask: 0x01)                          */
24701 /* ========================================================  SFMSIC  ========================================================= */
24702  #define R_QSPI_SFMSIC_SFMCIC_Pos       (0UL)          /*!< SFMCIC (Bit 0)                                        */
24703  #define R_QSPI_SFMSIC_SFMCIC_Msk       (0xffUL)       /*!< SFMCIC (Bitfield-Mask: 0xff)                          */
24704 /* ========================================================  SFMSAC  ========================================================= */
24705  #define R_QSPI_SFMSAC_SFM4BC_Pos       (4UL)          /*!< SFM4BC (Bit 4)                                        */
24706  #define R_QSPI_SFMSAC_SFM4BC_Msk       (0x10UL)       /*!< SFM4BC (Bitfield-Mask: 0x01)                          */
24707  #define R_QSPI_SFMSAC_SFMAS_Pos        (0UL)          /*!< SFMAS (Bit 0)                                         */
24708  #define R_QSPI_SFMSAC_SFMAS_Msk        (0x3UL)        /*!< SFMAS (Bitfield-Mask: 0x03)                           */
24709 /* ========================================================  SFMSDC  ========================================================= */
24710  #define R_QSPI_SFMSDC_SFMXD_Pos        (8UL)          /*!< SFMXD (Bit 8)                                         */
24711  #define R_QSPI_SFMSDC_SFMXD_Msk        (0xff00UL)     /*!< SFMXD (Bitfield-Mask: 0xff)                           */
24712  #define R_QSPI_SFMSDC_SFMXEN_Pos       (7UL)          /*!< SFMXEN (Bit 7)                                        */
24713  #define R_QSPI_SFMSDC_SFMXEN_Msk       (0x80UL)       /*!< SFMXEN (Bitfield-Mask: 0x01)                          */
24714  #define R_QSPI_SFMSDC_SFMXST_Pos       (6UL)          /*!< SFMXST (Bit 6)                                        */
24715  #define R_QSPI_SFMSDC_SFMXST_Msk       (0x40UL)       /*!< SFMXST (Bitfield-Mask: 0x01)                          */
24716  #define R_QSPI_SFMSDC_SFMDN_Pos        (0UL)          /*!< SFMDN (Bit 0)                                         */
24717  #define R_QSPI_SFMSDC_SFMDN_Msk        (0xfUL)        /*!< SFMDN (Bitfield-Mask: 0x0f)                           */
24718 /* ========================================================  SFMSPC  ========================================================= */
24719  #define R_QSPI_SFMSPC_SFMSDE_Pos       (4UL)          /*!< SFMSDE (Bit 4)                                        */
24720  #define R_QSPI_SFMSPC_SFMSDE_Msk       (0x10UL)       /*!< SFMSDE (Bitfield-Mask: 0x01)                          */
24721  #define R_QSPI_SFMSPC_SFMSPI_Pos       (0UL)          /*!< SFMSPI (Bit 0)                                        */
24722  #define R_QSPI_SFMSPC_SFMSPI_Msk       (0x3UL)        /*!< SFMSPI (Bitfield-Mask: 0x03)                          */
24723 /* ========================================================  SFMPMD  ========================================================= */
24724  #define R_QSPI_SFMPMD_SFMWPL_Pos       (2UL)          /*!< SFMWPL (Bit 2)                                        */
24725  #define R_QSPI_SFMPMD_SFMWPL_Msk       (0x4UL)        /*!< SFMWPL (Bitfield-Mask: 0x01)                          */
24726 /* ========================================================  SFMCNT1  ======================================================== */
24727  #define R_QSPI_SFMCNT1_QSPI_EXT_Pos    (26UL)         /*!< QSPI_EXT (Bit 26)                                     */
24728  #define R_QSPI_SFMCNT1_QSPI_EXT_Msk    (0xfc000000UL) /*!< QSPI_EXT (Bitfield-Mask: 0x3f)                        */
24729 
24730 /* =========================================================================================================================== */
24731 /* ================                                           R_RTC                                           ================ */
24732 /* =========================================================================================================================== */
24733 
24734 /* ========================================================  R64CNT  ========================================================= */
24735  #define R_RTC_R64CNT_F1HZ_Pos        (6UL)      /*!< F1HZ (Bit 6)                                          */
24736  #define R_RTC_R64CNT_F1HZ_Msk        (0x40UL)   /*!< F1HZ (Bitfield-Mask: 0x01)                            */
24737  #define R_RTC_R64CNT_F2HZ_Pos        (5UL)      /*!< F2HZ (Bit 5)                                          */
24738  #define R_RTC_R64CNT_F2HZ_Msk        (0x20UL)   /*!< F2HZ (Bitfield-Mask: 0x01)                            */
24739  #define R_RTC_R64CNT_F4HZ_Pos        (4UL)      /*!< F4HZ (Bit 4)                                          */
24740  #define R_RTC_R64CNT_F4HZ_Msk        (0x10UL)   /*!< F4HZ (Bitfield-Mask: 0x01)                            */
24741  #define R_RTC_R64CNT_F8HZ_Pos        (3UL)      /*!< F8HZ (Bit 3)                                          */
24742  #define R_RTC_R64CNT_F8HZ_Msk        (0x8UL)    /*!< F8HZ (Bitfield-Mask: 0x01)                            */
24743  #define R_RTC_R64CNT_F16HZ_Pos       (2UL)      /*!< F16HZ (Bit 2)                                         */
24744  #define R_RTC_R64CNT_F16HZ_Msk       (0x4UL)    /*!< F16HZ (Bitfield-Mask: 0x01)                           */
24745  #define R_RTC_R64CNT_F32HZ_Pos       (1UL)      /*!< F32HZ (Bit 1)                                         */
24746  #define R_RTC_R64CNT_F32HZ_Msk       (0x2UL)    /*!< F32HZ (Bitfield-Mask: 0x01)                           */
24747  #define R_RTC_R64CNT_F64HZ_Pos       (0UL)      /*!< F64HZ (Bit 0)                                         */
24748  #define R_RTC_R64CNT_F64HZ_Msk       (0x1UL)    /*!< F64HZ (Bitfield-Mask: 0x01)                           */
24749 /* =========================================================  BCNT0  ========================================================= */
24750  #define R_RTC_BCNT0_BCNT0_Pos        (0UL)      /*!< BCNT0 (Bit 0)                                         */
24751  #define R_RTC_BCNT0_BCNT0_Msk        (0xffUL)   /*!< BCNT0 (Bitfield-Mask: 0xff)                           */
24752 /* ========================================================  RSECCNT  ======================================================== */
24753  #define R_RTC_RSECCNT_SEC10_Pos      (4UL)      /*!< SEC10 (Bit 4)                                         */
24754  #define R_RTC_RSECCNT_SEC10_Msk      (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
24755  #define R_RTC_RSECCNT_SEC1_Pos       (0UL)      /*!< SEC1 (Bit 0)                                          */
24756  #define R_RTC_RSECCNT_SEC1_Msk       (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
24757 /* =========================================================  BCNT1  ========================================================= */
24758  #define R_RTC_BCNT1_BCNT1_Pos        (0UL)      /*!< BCNT1 (Bit 0)                                         */
24759  #define R_RTC_BCNT1_BCNT1_Msk        (0xffUL)   /*!< BCNT1 (Bitfield-Mask: 0xff)                           */
24760 /* ========================================================  RMINCNT  ======================================================== */
24761  #define R_RTC_RMINCNT_MIN10_Pos      (4UL)      /*!< MIN10 (Bit 4)                                         */
24762  #define R_RTC_RMINCNT_MIN10_Msk      (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
24763  #define R_RTC_RMINCNT_MIN1_Pos       (0UL)      /*!< MIN1 (Bit 0)                                          */
24764  #define R_RTC_RMINCNT_MIN1_Msk       (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
24765 /* =========================================================  BCNT2  ========================================================= */
24766  #define R_RTC_BCNT2_BCNT2_Pos        (0UL)      /*!< BCNT2 (Bit 0)                                         */
24767  #define R_RTC_BCNT2_BCNT2_Msk        (0xffUL)   /*!< BCNT2 (Bitfield-Mask: 0xff)                           */
24768 /* ========================================================  RHRCNT  ========================================================= */
24769  #define R_RTC_RHRCNT_PM_Pos          (6UL)      /*!< PM (Bit 6)                                            */
24770  #define R_RTC_RHRCNT_PM_Msk          (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
24771  #define R_RTC_RHRCNT_HR10_Pos        (4UL)      /*!< HR10 (Bit 4)                                          */
24772  #define R_RTC_RHRCNT_HR10_Msk        (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
24773  #define R_RTC_RHRCNT_HR1_Pos         (0UL)      /*!< HR1 (Bit 0)                                           */
24774  #define R_RTC_RHRCNT_HR1_Msk         (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
24775 /* =========================================================  BCNT3  ========================================================= */
24776  #define R_RTC_BCNT3_BCNT3_Pos        (0UL)      /*!< BCNT3 (Bit 0)                                         */
24777  #define R_RTC_BCNT3_BCNT3_Msk        (0xffUL)   /*!< BCNT3 (Bitfield-Mask: 0xff)                           */
24778 /* ========================================================  RWKCNT  ========================================================= */
24779  #define R_RTC_RWKCNT_DAYW_Pos        (0UL)      /*!< DAYW (Bit 0)                                          */
24780  #define R_RTC_RWKCNT_DAYW_Msk        (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
24781 /* ========================================================  RDAYCNT  ======================================================== */
24782  #define R_RTC_RDAYCNT_DATE10_Pos     (4UL)      /*!< DATE10 (Bit 4)                                        */
24783  #define R_RTC_RDAYCNT_DATE10_Msk     (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
24784  #define R_RTC_RDAYCNT_DATE1_Pos      (0UL)      /*!< DATE1 (Bit 0)                                         */
24785  #define R_RTC_RDAYCNT_DATE1_Msk      (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
24786 /* ========================================================  RMONCNT  ======================================================== */
24787  #define R_RTC_RMONCNT_MON10_Pos      (4UL)      /*!< MON10 (Bit 4)                                         */
24788  #define R_RTC_RMONCNT_MON10_Msk      (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
24789  #define R_RTC_RMONCNT_MON1_Pos       (0UL)      /*!< MON1 (Bit 0)                                          */
24790  #define R_RTC_RMONCNT_MON1_Msk       (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
24791 /* ========================================================  RYRCNT  ========================================================= */
24792  #define R_RTC_RYRCNT_YR10_Pos        (4UL)      /*!< YR10 (Bit 4)                                          */
24793  #define R_RTC_RYRCNT_YR10_Msk        (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
24794  #define R_RTC_RYRCNT_YR1_Pos         (0UL)      /*!< YR1 (Bit 0)                                           */
24795  #define R_RTC_RYRCNT_YR1_Msk         (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
24796 /* ========================================================  BCNT0AR  ======================================================== */
24797  #define R_RTC_BCNT0AR_BCNT0AR_Pos    (0UL)      /*!< BCNT0AR (Bit 0)                                       */
24798  #define R_RTC_BCNT0AR_BCNT0AR_Msk    (0xffUL)   /*!< BCNT0AR (Bitfield-Mask: 0xff)                         */
24799 /* ========================================================  RSECAR  ========================================================= */
24800  #define R_RTC_RSECAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
24801  #define R_RTC_RSECAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
24802  #define R_RTC_RSECAR_SEC10_Pos       (4UL)      /*!< SEC10 (Bit 4)                                         */
24803  #define R_RTC_RSECAR_SEC10_Msk       (0x70UL)   /*!< SEC10 (Bitfield-Mask: 0x07)                           */
24804  #define R_RTC_RSECAR_SEC1_Pos        (0UL)      /*!< SEC1 (Bit 0)                                          */
24805  #define R_RTC_RSECAR_SEC1_Msk        (0xfUL)    /*!< SEC1 (Bitfield-Mask: 0x0f)                            */
24806 /* ========================================================  BCNT1AR  ======================================================== */
24807  #define R_RTC_BCNT1AR_BCNT1AR_Pos    (0UL)      /*!< BCNT1AR (Bit 0)                                       */
24808  #define R_RTC_BCNT1AR_BCNT1AR_Msk    (0xffUL)   /*!< BCNT1AR (Bitfield-Mask: 0xff)                         */
24809 /* ========================================================  RMINAR  ========================================================= */
24810  #define R_RTC_RMINAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
24811  #define R_RTC_RMINAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
24812  #define R_RTC_RMINAR_MIN10_Pos       (4UL)      /*!< MIN10 (Bit 4)                                         */
24813  #define R_RTC_RMINAR_MIN10_Msk       (0x70UL)   /*!< MIN10 (Bitfield-Mask: 0x07)                           */
24814  #define R_RTC_RMINAR_MIN1_Pos        (0UL)      /*!< MIN1 (Bit 0)                                          */
24815  #define R_RTC_RMINAR_MIN1_Msk        (0xfUL)    /*!< MIN1 (Bitfield-Mask: 0x0f)                            */
24816 /* ========================================================  BCNT2AR  ======================================================== */
24817  #define R_RTC_BCNT2AR_BCNT2AR_Pos    (0UL)      /*!< BCNT2AR (Bit 0)                                       */
24818  #define R_RTC_BCNT2AR_BCNT2AR_Msk    (0xffUL)   /*!< BCNT2AR (Bitfield-Mask: 0xff)                         */
24819 /* =========================================================  RHRAR  ========================================================= */
24820  #define R_RTC_RHRAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
24821  #define R_RTC_RHRAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
24822  #define R_RTC_RHRAR_PM_Pos           (6UL)      /*!< PM (Bit 6)                                            */
24823  #define R_RTC_RHRAR_PM_Msk           (0x40UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
24824  #define R_RTC_RHRAR_HR10_Pos         (4UL)      /*!< HR10 (Bit 4)                                          */
24825  #define R_RTC_RHRAR_HR10_Msk         (0x30UL)   /*!< HR10 (Bitfield-Mask: 0x03)                            */
24826  #define R_RTC_RHRAR_HR1_Pos          (0UL)      /*!< HR1 (Bit 0)                                           */
24827  #define R_RTC_RHRAR_HR1_Msk          (0xfUL)    /*!< HR1 (Bitfield-Mask: 0x0f)                             */
24828 /* ========================================================  BCNT3AR  ======================================================== */
24829  #define R_RTC_BCNT3AR_BCNT3AR_Pos    (0UL)      /*!< BCNT3AR (Bit 0)                                       */
24830  #define R_RTC_BCNT3AR_BCNT3AR_Msk    (0xffUL)   /*!< BCNT3AR (Bitfield-Mask: 0xff)                         */
24831 /* =========================================================  RWKAR  ========================================================= */
24832  #define R_RTC_RWKAR_ENB_Pos          (7UL)      /*!< ENB (Bit 7)                                           */
24833  #define R_RTC_RWKAR_ENB_Msk          (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
24834  #define R_RTC_RWKAR_DAYW_Pos         (0UL)      /*!< DAYW (Bit 0)                                          */
24835  #define R_RTC_RWKAR_DAYW_Msk         (0x7UL)    /*!< DAYW (Bitfield-Mask: 0x07)                            */
24836 /* =======================================================  BCNT0AER  ======================================================== */
24837  #define R_RTC_BCNT0AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
24838  #define R_RTC_BCNT0AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
24839 /* ========================================================  RDAYAR  ========================================================= */
24840  #define R_RTC_RDAYAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
24841  #define R_RTC_RDAYAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
24842  #define R_RTC_RDAYAR_DATE10_Pos      (4UL)      /*!< DATE10 (Bit 4)                                        */
24843  #define R_RTC_RDAYAR_DATE10_Msk      (0x30UL)   /*!< DATE10 (Bitfield-Mask: 0x03)                          */
24844  #define R_RTC_RDAYAR_DATE1_Pos       (0UL)      /*!< DATE1 (Bit 0)                                         */
24845  #define R_RTC_RDAYAR_DATE1_Msk       (0xfUL)    /*!< DATE1 (Bitfield-Mask: 0x0f)                           */
24846 /* =======================================================  BCNT1AER  ======================================================== */
24847  #define R_RTC_BCNT1AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
24848  #define R_RTC_BCNT1AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
24849 /* ========================================================  RMONAR  ========================================================= */
24850  #define R_RTC_RMONAR_ENB_Pos         (7UL)      /*!< ENB (Bit 7)                                           */
24851  #define R_RTC_RMONAR_ENB_Msk         (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
24852  #define R_RTC_RMONAR_MON10_Pos       (4UL)      /*!< MON10 (Bit 4)                                         */
24853  #define R_RTC_RMONAR_MON10_Msk       (0x10UL)   /*!< MON10 (Bitfield-Mask: 0x01)                           */
24854  #define R_RTC_RMONAR_MON1_Pos        (0UL)      /*!< MON1 (Bit 0)                                          */
24855  #define R_RTC_RMONAR_MON1_Msk        (0xfUL)    /*!< MON1 (Bitfield-Mask: 0x0f)                            */
24856 /* =======================================================  BCNT2AER  ======================================================== */
24857  #define R_RTC_BCNT2AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
24858  #define R_RTC_BCNT2AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
24859 /* =========================================================  RYRAR  ========================================================= */
24860  #define R_RTC_RYRAR_YR10_Pos         (4UL)      /*!< YR10 (Bit 4)                                          */
24861  #define R_RTC_RYRAR_YR10_Msk         (0xf0UL)   /*!< YR10 (Bitfield-Mask: 0x0f)                            */
24862  #define R_RTC_RYRAR_YR1_Pos          (0UL)      /*!< YR1 (Bit 0)                                           */
24863  #define R_RTC_RYRAR_YR1_Msk          (0xfUL)    /*!< YR1 (Bitfield-Mask: 0x0f)                             */
24864 /* =======================================================  BCNT3AER  ======================================================== */
24865  #define R_RTC_BCNT3AER_ENB_Pos       (0UL)      /*!< ENB (Bit 0)                                           */
24866  #define R_RTC_BCNT3AER_ENB_Msk       (0xffUL)   /*!< ENB (Bitfield-Mask: 0xff)                             */
24867 /* ========================================================  RYRAREN  ======================================================== */
24868  #define R_RTC_RYRAREN_ENB_Pos        (7UL)      /*!< ENB (Bit 7)                                           */
24869  #define R_RTC_RYRAREN_ENB_Msk        (0x80UL)   /*!< ENB (Bitfield-Mask: 0x01)                             */
24870 /* =========================================================  RCR1  ========================================================== */
24871  #define R_RTC_RCR1_PES_Pos           (4UL)      /*!< PES (Bit 4)                                           */
24872  #define R_RTC_RCR1_PES_Msk           (0xf0UL)   /*!< PES (Bitfield-Mask: 0x0f)                             */
24873  #define R_RTC_RCR1_RTCOS_Pos         (3UL)      /*!< RTCOS (Bit 3)                                         */
24874  #define R_RTC_RCR1_RTCOS_Msk         (0x8UL)    /*!< RTCOS (Bitfield-Mask: 0x01)                           */
24875  #define R_RTC_RCR1_PIE_Pos           (2UL)      /*!< PIE (Bit 2)                                           */
24876  #define R_RTC_RCR1_PIE_Msk           (0x4UL)    /*!< PIE (Bitfield-Mask: 0x01)                             */
24877  #define R_RTC_RCR1_CIE_Pos           (1UL)      /*!< CIE (Bit 1)                                           */
24878  #define R_RTC_RCR1_CIE_Msk           (0x2UL)    /*!< CIE (Bitfield-Mask: 0x01)                             */
24879  #define R_RTC_RCR1_AIE_Pos           (0UL)      /*!< AIE (Bit 0)                                           */
24880  #define R_RTC_RCR1_AIE_Msk           (0x1UL)    /*!< AIE (Bitfield-Mask: 0x01)                             */
24881 /* =========================================================  RCR2  ========================================================== */
24882  #define R_RTC_RCR2_CNTMD_Pos         (7UL)      /*!< CNTMD (Bit 7)                                         */
24883  #define R_RTC_RCR2_CNTMD_Msk         (0x80UL)   /*!< CNTMD (Bitfield-Mask: 0x01)                           */
24884  #define R_RTC_RCR2_HR24_Pos          (6UL)      /*!< HR24 (Bit 6)                                          */
24885  #define R_RTC_RCR2_HR24_Msk          (0x40UL)   /*!< HR24 (Bitfield-Mask: 0x01)                            */
24886  #define R_RTC_RCR2_AADJP_Pos         (5UL)      /*!< AADJP (Bit 5)                                         */
24887  #define R_RTC_RCR2_AADJP_Msk         (0x20UL)   /*!< AADJP (Bitfield-Mask: 0x01)                           */
24888  #define R_RTC_RCR2_AADJE_Pos         (4UL)      /*!< AADJE (Bit 4)                                         */
24889  #define R_RTC_RCR2_AADJE_Msk         (0x10UL)   /*!< AADJE (Bitfield-Mask: 0x01)                           */
24890  #define R_RTC_RCR2_RTCOE_Pos         (3UL)      /*!< RTCOE (Bit 3)                                         */
24891  #define R_RTC_RCR2_RTCOE_Msk         (0x8UL)    /*!< RTCOE (Bitfield-Mask: 0x01)                           */
24892  #define R_RTC_RCR2_ADJ30_Pos         (2UL)      /*!< ADJ30 (Bit 2)                                         */
24893  #define R_RTC_RCR2_ADJ30_Msk         (0x4UL)    /*!< ADJ30 (Bitfield-Mask: 0x01)                           */
24894  #define R_RTC_RCR2_RESET_Pos         (1UL)      /*!< RESET (Bit 1)                                         */
24895  #define R_RTC_RCR2_RESET_Msk         (0x2UL)    /*!< RESET (Bitfield-Mask: 0x01)                           */
24896  #define R_RTC_RCR2_START_Pos         (0UL)      /*!< START (Bit 0)                                         */
24897  #define R_RTC_RCR2_START_Msk         (0x1UL)    /*!< START (Bitfield-Mask: 0x01)                           */
24898 /* =========================================================  RCR4  ========================================================== */
24899  #define R_RTC_RCR4_RCKSEL_Pos        (0UL)      /*!< RCKSEL (Bit 0)                                        */
24900  #define R_RTC_RCR4_RCKSEL_Msk        (0x1UL)    /*!< RCKSEL (Bitfield-Mask: 0x01)                          */
24901  #define R_RTC_RCR4_ROPSEL_Pos        (7UL)      /*!< ROPSEL (Bit 7)                                        */
24902  #define R_RTC_RCR4_ROPSEL_Msk        (0x80UL)   /*!< ROPSEL (Bitfield-Mask: 0x01)                          */
24903 /* =========================================================  RFRH  ========================================================== */
24904  #define R_RTC_RFRH_RFC16_Pos         (0UL)      /*!< RFC16 (Bit 0)                                         */
24905  #define R_RTC_RFRH_RFC16_Msk         (0x1UL)    /*!< RFC16 (Bitfield-Mask: 0x01)                           */
24906 /* =========================================================  RFRL  ========================================================== */
24907  #define R_RTC_RFRL_RFC_Pos           (0UL)      /*!< RFC (Bit 0)                                           */
24908  #define R_RTC_RFRL_RFC_Msk           (0xffffUL) /*!< RFC (Bitfield-Mask: 0xffff)                           */
24909 /* =========================================================  RADJ  ========================================================== */
24910  #define R_RTC_RADJ_PMADJ_Pos         (6UL)      /*!< PMADJ (Bit 6)                                         */
24911  #define R_RTC_RADJ_PMADJ_Msk         (0xc0UL)   /*!< PMADJ (Bitfield-Mask: 0x03)                           */
24912  #define R_RTC_RADJ_ADJ_Pos           (0UL)      /*!< ADJ (Bit 0)                                           */
24913  #define R_RTC_RADJ_ADJ_Msk           (0x3fUL)   /*!< ADJ (Bitfield-Mask: 0x3f)                             */
24914 
24915 /* =========================================================================================================================== */
24916 /* ================                                          R_SCI0                                           ================ */
24917 /* =========================================================================================================================== */
24918 
24919 /* ==========================================================  SMR  ========================================================== */
24920  #define R_SCI0_SMR_CM_Pos              (7UL)      /*!< CM (Bit 7)                                            */
24921  #define R_SCI0_SMR_CM_Msk              (0x80UL)   /*!< CM (Bitfield-Mask: 0x01)                              */
24922  #define R_SCI0_SMR_CHR_Pos             (6UL)      /*!< CHR (Bit 6)                                           */
24923  #define R_SCI0_SMR_CHR_Msk             (0x40UL)   /*!< CHR (Bitfield-Mask: 0x01)                             */
24924  #define R_SCI0_SMR_PE_Pos              (5UL)      /*!< PE (Bit 5)                                            */
24925  #define R_SCI0_SMR_PE_Msk              (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
24926  #define R_SCI0_SMR_PM_Pos              (4UL)      /*!< PM (Bit 4)                                            */
24927  #define R_SCI0_SMR_PM_Msk              (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
24928  #define R_SCI0_SMR_STOP_Pos            (3UL)      /*!< STOP (Bit 3)                                          */
24929  #define R_SCI0_SMR_STOP_Msk            (0x8UL)    /*!< STOP (Bitfield-Mask: 0x01)                            */
24930  #define R_SCI0_SMR_MP_Pos              (2UL)      /*!< MP (Bit 2)                                            */
24931  #define R_SCI0_SMR_MP_Msk              (0x4UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
24932  #define R_SCI0_SMR_CKS_Pos             (0UL)      /*!< CKS (Bit 0)                                           */
24933  #define R_SCI0_SMR_CKS_Msk             (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
24934 /* =======================================================  SMR_SMCI  ======================================================== */
24935  #define R_SCI0_SMR_SMCI_GM_Pos         (7UL)      /*!< GM (Bit 7)                                            */
24936  #define R_SCI0_SMR_SMCI_GM_Msk         (0x80UL)   /*!< GM (Bitfield-Mask: 0x01)                              */
24937  #define R_SCI0_SMR_SMCI_BLK_Pos        (6UL)      /*!< BLK (Bit 6)                                           */
24938  #define R_SCI0_SMR_SMCI_BLK_Msk        (0x40UL)   /*!< BLK (Bitfield-Mask: 0x01)                             */
24939  #define R_SCI0_SMR_SMCI_PE_Pos         (5UL)      /*!< PE (Bit 5)                                            */
24940  #define R_SCI0_SMR_SMCI_PE_Msk         (0x20UL)   /*!< PE (Bitfield-Mask: 0x01)                              */
24941  #define R_SCI0_SMR_SMCI_PM_Pos         (4UL)      /*!< PM (Bit 4)                                            */
24942  #define R_SCI0_SMR_SMCI_PM_Msk         (0x10UL)   /*!< PM (Bitfield-Mask: 0x01)                              */
24943  #define R_SCI0_SMR_SMCI_BCP_Pos        (2UL)      /*!< BCP (Bit 2)                                           */
24944  #define R_SCI0_SMR_SMCI_BCP_Msk        (0xcUL)    /*!< BCP (Bitfield-Mask: 0x03)                             */
24945  #define R_SCI0_SMR_SMCI_CKS_Pos        (0UL)      /*!< CKS (Bit 0)                                           */
24946  #define R_SCI0_SMR_SMCI_CKS_Msk        (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
24947 /* ==========================================================  BRR  ========================================================== */
24948  #define R_SCI0_BRR_BRR_Pos             (0UL)      /*!< BRR (Bit 0)                                           */
24949  #define R_SCI0_BRR_BRR_Msk             (0xffUL)   /*!< BRR (Bitfield-Mask: 0xff)                             */
24950 /* ==========================================================  SCR  ========================================================== */
24951  #define R_SCI0_SCR_TIE_Pos             (7UL)      /*!< TIE (Bit 7)                                           */
24952  #define R_SCI0_SCR_TIE_Msk             (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
24953  #define R_SCI0_SCR_RIE_Pos             (6UL)      /*!< RIE (Bit 6)                                           */
24954  #define R_SCI0_SCR_RIE_Msk             (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
24955  #define R_SCI0_SCR_TE_Pos              (5UL)      /*!< TE (Bit 5)                                            */
24956  #define R_SCI0_SCR_TE_Msk              (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
24957  #define R_SCI0_SCR_RE_Pos              (4UL)      /*!< RE (Bit 4)                                            */
24958  #define R_SCI0_SCR_RE_Msk              (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
24959  #define R_SCI0_SCR_MPIE_Pos            (3UL)      /*!< MPIE (Bit 3)                                          */
24960  #define R_SCI0_SCR_MPIE_Msk            (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
24961  #define R_SCI0_SCR_TEIE_Pos            (2UL)      /*!< TEIE (Bit 2)                                          */
24962  #define R_SCI0_SCR_TEIE_Msk            (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
24963  #define R_SCI0_SCR_CKE_Pos             (0UL)      /*!< CKE (Bit 0)                                           */
24964  #define R_SCI0_SCR_CKE_Msk             (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
24965 /* =======================================================  SCR_SMCI  ======================================================== */
24966  #define R_SCI0_SCR_SMCI_TIE_Pos        (7UL)      /*!< TIE (Bit 7)                                           */
24967  #define R_SCI0_SCR_SMCI_TIE_Msk        (0x80UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
24968  #define R_SCI0_SCR_SMCI_RIE_Pos        (6UL)      /*!< RIE (Bit 6)                                           */
24969  #define R_SCI0_SCR_SMCI_RIE_Msk        (0x40UL)   /*!< RIE (Bitfield-Mask: 0x01)                             */
24970  #define R_SCI0_SCR_SMCI_TE_Pos         (5UL)      /*!< TE (Bit 5)                                            */
24971  #define R_SCI0_SCR_SMCI_TE_Msk         (0x20UL)   /*!< TE (Bitfield-Mask: 0x01)                              */
24972  #define R_SCI0_SCR_SMCI_RE_Pos         (4UL)      /*!< RE (Bit 4)                                            */
24973  #define R_SCI0_SCR_SMCI_RE_Msk         (0x10UL)   /*!< RE (Bitfield-Mask: 0x01)                              */
24974  #define R_SCI0_SCR_SMCI_MPIE_Pos       (3UL)      /*!< MPIE (Bit 3)                                          */
24975  #define R_SCI0_SCR_SMCI_MPIE_Msk       (0x8UL)    /*!< MPIE (Bitfield-Mask: 0x01)                            */
24976  #define R_SCI0_SCR_SMCI_TEIE_Pos       (2UL)      /*!< TEIE (Bit 2)                                          */
24977  #define R_SCI0_SCR_SMCI_TEIE_Msk       (0x4UL)    /*!< TEIE (Bitfield-Mask: 0x01)                            */
24978  #define R_SCI0_SCR_SMCI_CKE_Pos        (0UL)      /*!< CKE (Bit 0)                                           */
24979  #define R_SCI0_SCR_SMCI_CKE_Msk        (0x3UL)    /*!< CKE (Bitfield-Mask: 0x03)                             */
24980 /* ==========================================================  TDR  ========================================================== */
24981  #define R_SCI0_TDR_TDR_Pos             (0UL)      /*!< TDR (Bit 0)                                           */
24982  #define R_SCI0_TDR_TDR_Msk             (0xffUL)   /*!< TDR (Bitfield-Mask: 0xff)                             */
24983 /* ==========================================================  SSR  ========================================================== */
24984  #define R_SCI0_SSR_TDRE_Pos            (7UL)      /*!< TDRE (Bit 7)                                          */
24985  #define R_SCI0_SSR_TDRE_Msk            (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
24986  #define R_SCI0_SSR_RDRF_Pos            (6UL)      /*!< RDRF (Bit 6)                                          */
24987  #define R_SCI0_SSR_RDRF_Msk            (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
24988  #define R_SCI0_SSR_ORER_Pos            (5UL)      /*!< ORER (Bit 5)                                          */
24989  #define R_SCI0_SSR_ORER_Msk            (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
24990  #define R_SCI0_SSR_FER_Pos             (4UL)      /*!< FER (Bit 4)                                           */
24991  #define R_SCI0_SSR_FER_Msk             (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
24992  #define R_SCI0_SSR_PER_Pos             (3UL)      /*!< PER (Bit 3)                                           */
24993  #define R_SCI0_SSR_PER_Msk             (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
24994  #define R_SCI0_SSR_TEND_Pos            (2UL)      /*!< TEND (Bit 2)                                          */
24995  #define R_SCI0_SSR_TEND_Msk            (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
24996  #define R_SCI0_SSR_MPB_Pos             (1UL)      /*!< MPB (Bit 1)                                           */
24997  #define R_SCI0_SSR_MPB_Msk             (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
24998  #define R_SCI0_SSR_MPBT_Pos            (0UL)      /*!< MPBT (Bit 0)                                          */
24999  #define R_SCI0_SSR_MPBT_Msk            (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
25000 /* =======================================================  SSR_FIFO  ======================================================== */
25001  #define R_SCI0_SSR_FIFO_TDFE_Pos       (7UL)      /*!< TDFE (Bit 7)                                          */
25002  #define R_SCI0_SSR_FIFO_TDFE_Msk       (0x80UL)   /*!< TDFE (Bitfield-Mask: 0x01)                            */
25003  #define R_SCI0_SSR_FIFO_RDF_Pos        (6UL)      /*!< RDF (Bit 6)                                           */
25004  #define R_SCI0_SSR_FIFO_RDF_Msk        (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
25005  #define R_SCI0_SSR_FIFO_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
25006  #define R_SCI0_SSR_FIFO_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
25007  #define R_SCI0_SSR_FIFO_FER_Pos        (4UL)      /*!< FER (Bit 4)                                           */
25008  #define R_SCI0_SSR_FIFO_FER_Msk        (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
25009  #define R_SCI0_SSR_FIFO_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
25010  #define R_SCI0_SSR_FIFO_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
25011  #define R_SCI0_SSR_FIFO_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
25012  #define R_SCI0_SSR_FIFO_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
25013  #define R_SCI0_SSR_FIFO_DR_Pos         (0UL)      /*!< DR (Bit 0)                                            */
25014  #define R_SCI0_SSR_FIFO_DR_Msk         (0x1UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
25015 /* =======================================================  SSR_SMCI  ======================================================== */
25016  #define R_SCI0_SSR_SMCI_TDRE_Pos       (7UL)      /*!< TDRE (Bit 7)                                          */
25017  #define R_SCI0_SSR_SMCI_TDRE_Msk       (0x80UL)   /*!< TDRE (Bitfield-Mask: 0x01)                            */
25018  #define R_SCI0_SSR_SMCI_RDRF_Pos       (6UL)      /*!< RDRF (Bit 6)                                          */
25019  #define R_SCI0_SSR_SMCI_RDRF_Msk       (0x40UL)   /*!< RDRF (Bitfield-Mask: 0x01)                            */
25020  #define R_SCI0_SSR_SMCI_ORER_Pos       (5UL)      /*!< ORER (Bit 5)                                          */
25021  #define R_SCI0_SSR_SMCI_ORER_Msk       (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
25022  #define R_SCI0_SSR_SMCI_ERS_Pos        (4UL)      /*!< ERS (Bit 4)                                           */
25023  #define R_SCI0_SSR_SMCI_ERS_Msk        (0x10UL)   /*!< ERS (Bitfield-Mask: 0x01)                             */
25024  #define R_SCI0_SSR_SMCI_PER_Pos        (3UL)      /*!< PER (Bit 3)                                           */
25025  #define R_SCI0_SSR_SMCI_PER_Msk        (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
25026  #define R_SCI0_SSR_SMCI_TEND_Pos       (2UL)      /*!< TEND (Bit 2)                                          */
25027  #define R_SCI0_SSR_SMCI_TEND_Msk       (0x4UL)    /*!< TEND (Bitfield-Mask: 0x01)                            */
25028  #define R_SCI0_SSR_SMCI_MPB_Pos        (1UL)      /*!< MPB (Bit 1)                                           */
25029  #define R_SCI0_SSR_SMCI_MPB_Msk        (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
25030  #define R_SCI0_SSR_SMCI_MPBT_Pos       (0UL)      /*!< MPBT (Bit 0)                                          */
25031  #define R_SCI0_SSR_SMCI_MPBT_Msk       (0x1UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
25032 /* ==========================================================  RDR  ========================================================== */
25033  #define R_SCI0_RDR_RDR_Pos             (0UL)      /*!< RDR (Bit 0)                                           */
25034  #define R_SCI0_RDR_RDR_Msk             (0xffUL)   /*!< RDR (Bitfield-Mask: 0xff)                             */
25035 /* =========================================================  SCMR  ========================================================== */
25036  #define R_SCI0_SCMR_BCP2_Pos           (7UL)      /*!< BCP2 (Bit 7)                                          */
25037  #define R_SCI0_SCMR_BCP2_Msk           (0x80UL)   /*!< BCP2 (Bitfield-Mask: 0x01)                            */
25038  #define R_SCI0_SCMR_CHR1_Pos           (4UL)      /*!< CHR1 (Bit 4)                                          */
25039  #define R_SCI0_SCMR_CHR1_Msk           (0x10UL)   /*!< CHR1 (Bitfield-Mask: 0x01)                            */
25040  #define R_SCI0_SCMR_SDIR_Pos           (3UL)      /*!< SDIR (Bit 3)                                          */
25041  #define R_SCI0_SCMR_SDIR_Msk           (0x8UL)    /*!< SDIR (Bitfield-Mask: 0x01)                            */
25042  #define R_SCI0_SCMR_SINV_Pos           (2UL)      /*!< SINV (Bit 2)                                          */
25043  #define R_SCI0_SCMR_SINV_Msk           (0x4UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
25044  #define R_SCI0_SCMR_SMIF_Pos           (0UL)      /*!< SMIF (Bit 0)                                          */
25045  #define R_SCI0_SCMR_SMIF_Msk           (0x1UL)    /*!< SMIF (Bitfield-Mask: 0x01)                            */
25046 /* =========================================================  SEMR  ========================================================== */
25047  #define R_SCI0_SEMR_RXDESEL_Pos        (7UL)      /*!< RXDESEL (Bit 7)                                       */
25048  #define R_SCI0_SEMR_RXDESEL_Msk        (0x80UL)   /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
25049  #define R_SCI0_SEMR_BGDM_Pos           (6UL)      /*!< BGDM (Bit 6)                                          */
25050  #define R_SCI0_SEMR_BGDM_Msk           (0x40UL)   /*!< BGDM (Bitfield-Mask: 0x01)                            */
25051  #define R_SCI0_SEMR_NFEN_Pos           (5UL)      /*!< NFEN (Bit 5)                                          */
25052  #define R_SCI0_SEMR_NFEN_Msk           (0x20UL)   /*!< NFEN (Bitfield-Mask: 0x01)                            */
25053  #define R_SCI0_SEMR_ABCS_Pos           (4UL)      /*!< ABCS (Bit 4)                                          */
25054  #define R_SCI0_SEMR_ABCS_Msk           (0x10UL)   /*!< ABCS (Bitfield-Mask: 0x01)                            */
25055  #define R_SCI0_SEMR_ABCSE_Pos          (3UL)      /*!< ABCSE (Bit 3)                                         */
25056  #define R_SCI0_SEMR_ABCSE_Msk          (0x8UL)    /*!< ABCSE (Bitfield-Mask: 0x01)                           */
25057  #define R_SCI0_SEMR_BRME_Pos           (2UL)      /*!< BRME (Bit 2)                                          */
25058  #define R_SCI0_SEMR_BRME_Msk           (0x4UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
25059  #define R_SCI0_SEMR_PADIS_Pos          (1UL)      /*!< PADIS (Bit 1)                                         */
25060  #define R_SCI0_SEMR_PADIS_Msk          (0x2UL)    /*!< PADIS (Bitfield-Mask: 0x01)                           */
25061  #define R_SCI0_SEMR_ACS0_Pos           (0UL)      /*!< ACS0 (Bit 0)                                          */
25062  #define R_SCI0_SEMR_ACS0_Msk           (0x1UL)    /*!< ACS0 (Bitfield-Mask: 0x01)                            */
25063 /* =========================================================  SNFR  ========================================================== */
25064  #define R_SCI0_SNFR_NFCS_Pos           (0UL)      /*!< NFCS (Bit 0)                                          */
25065  #define R_SCI0_SNFR_NFCS_Msk           (0x7UL)    /*!< NFCS (Bitfield-Mask: 0x07)                            */
25066 /* =========================================================  SIMR1  ========================================================= */
25067  #define R_SCI0_SIMR1_IICDL_Pos         (3UL)      /*!< IICDL (Bit 3)                                         */
25068  #define R_SCI0_SIMR1_IICDL_Msk         (0xf8UL)   /*!< IICDL (Bitfield-Mask: 0x1f)                           */
25069  #define R_SCI0_SIMR1_IICM_Pos          (0UL)      /*!< IICM (Bit 0)                                          */
25070  #define R_SCI0_SIMR1_IICM_Msk          (0x1UL)    /*!< IICM (Bitfield-Mask: 0x01)                            */
25071 /* =========================================================  SIMR2  ========================================================= */
25072  #define R_SCI0_SIMR2_IICACKT_Pos       (5UL)      /*!< IICACKT (Bit 5)                                       */
25073  #define R_SCI0_SIMR2_IICACKT_Msk       (0x20UL)   /*!< IICACKT (Bitfield-Mask: 0x01)                         */
25074  #define R_SCI0_SIMR2_IICCSC_Pos        (1UL)      /*!< IICCSC (Bit 1)                                        */
25075  #define R_SCI0_SIMR2_IICCSC_Msk        (0x2UL)    /*!< IICCSC (Bitfield-Mask: 0x01)                          */
25076  #define R_SCI0_SIMR2_IICINTM_Pos       (0UL)      /*!< IICINTM (Bit 0)                                       */
25077  #define R_SCI0_SIMR2_IICINTM_Msk       (0x1UL)    /*!< IICINTM (Bitfield-Mask: 0x01)                         */
25078 /* =========================================================  SIMR3  ========================================================= */
25079  #define R_SCI0_SIMR3_IICSCLS_Pos       (6UL)      /*!< IICSCLS (Bit 6)                                       */
25080  #define R_SCI0_SIMR3_IICSCLS_Msk       (0xc0UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
25081  #define R_SCI0_SIMR3_IICSDAS_Pos       (4UL)      /*!< IICSDAS (Bit 4)                                       */
25082  #define R_SCI0_SIMR3_IICSDAS_Msk       (0x30UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
25083  #define R_SCI0_SIMR3_IICSTIF_Pos       (3UL)      /*!< IICSTIF (Bit 3)                                       */
25084  #define R_SCI0_SIMR3_IICSTIF_Msk       (0x8UL)    /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
25085  #define R_SCI0_SIMR3_IICSTPREQ_Pos     (2UL)      /*!< IICSTPREQ (Bit 2)                                     */
25086  #define R_SCI0_SIMR3_IICSTPREQ_Msk     (0x4UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
25087  #define R_SCI0_SIMR3_IICRSTAREQ_Pos    (1UL)      /*!< IICRSTAREQ (Bit 1)                                    */
25088  #define R_SCI0_SIMR3_IICRSTAREQ_Msk    (0x2UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
25089  #define R_SCI0_SIMR3_IICSTAREQ_Pos     (0UL)      /*!< IICSTAREQ (Bit 0)                                     */
25090  #define R_SCI0_SIMR3_IICSTAREQ_Msk     (0x1UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
25091 /* =========================================================  SISR  ========================================================== */
25092  #define R_SCI0_SISR_IICACKR_Pos        (0UL)      /*!< IICACKR (Bit 0)                                       */
25093  #define R_SCI0_SISR_IICACKR_Msk        (0x1UL)    /*!< IICACKR (Bitfield-Mask: 0x01)                         */
25094 /* =========================================================  SPMR  ========================================================== */
25095  #define R_SCI0_SPMR_CKPH_Pos           (7UL)      /*!< CKPH (Bit 7)                                          */
25096  #define R_SCI0_SPMR_CKPH_Msk           (0x80UL)   /*!< CKPH (Bitfield-Mask: 0x01)                            */
25097  #define R_SCI0_SPMR_CKPOL_Pos          (6UL)      /*!< CKPOL (Bit 6)                                         */
25098  #define R_SCI0_SPMR_CKPOL_Msk          (0x40UL)   /*!< CKPOL (Bitfield-Mask: 0x01)                           */
25099  #define R_SCI0_SPMR_MFF_Pos            (4UL)      /*!< MFF (Bit 4)                                           */
25100  #define R_SCI0_SPMR_MFF_Msk            (0x10UL)   /*!< MFF (Bitfield-Mask: 0x01)                             */
25101  #define R_SCI0_SPMR_CSTPEN_Pos         (3UL)      /*!< CSTPEN (Bit 3)                                        */
25102  #define R_SCI0_SPMR_CSTPEN_Msk         (0x8UL)    /*!< CSTPEN (Bitfield-Mask: 0x01)                          */
25103  #define R_SCI0_SPMR_MSS_Pos            (2UL)      /*!< MSS (Bit 2)                                           */
25104  #define R_SCI0_SPMR_MSS_Msk            (0x4UL)    /*!< MSS (Bitfield-Mask: 0x01)                             */
25105  #define R_SCI0_SPMR_CTSE_Pos           (1UL)      /*!< CTSE (Bit 1)                                          */
25106  #define R_SCI0_SPMR_CTSE_Msk           (0x2UL)    /*!< CTSE (Bitfield-Mask: 0x01)                            */
25107  #define R_SCI0_SPMR_SSE_Pos            (0UL)      /*!< SSE (Bit 0)                                           */
25108  #define R_SCI0_SPMR_SSE_Msk            (0x1UL)    /*!< SSE (Bitfield-Mask: 0x01)                             */
25109 /* =========================================================  TDRHL  ========================================================= */
25110  #define R_SCI0_TDRHL_TDRHL_Pos         (0UL)      /*!< TDRHL (Bit 0)                                         */
25111  #define R_SCI0_TDRHL_TDRHL_Msk         (0xffffUL) /*!< TDRHL (Bitfield-Mask: 0xffff)                         */
25112 /* ========================================================  FTDRHL  ========================================================= */
25113  #define R_SCI0_FTDRHL_MPBT_Pos         (9UL)      /*!< MPBT (Bit 9)                                          */
25114  #define R_SCI0_FTDRHL_MPBT_Msk         (0x200UL)  /*!< MPBT (Bitfield-Mask: 0x01)                            */
25115  #define R_SCI0_FTDRHL_TDAT_Pos         (0UL)      /*!< TDAT (Bit 0)                                          */
25116  #define R_SCI0_FTDRHL_TDAT_Msk         (0x1ffUL)  /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
25117 /* =========================================================  FTDRH  ========================================================= */
25118  #define R_SCI0_FTDRH_MPBT_Pos          (1UL)      /*!< MPBT (Bit 1)                                          */
25119  #define R_SCI0_FTDRH_MPBT_Msk          (0x2UL)    /*!< MPBT (Bitfield-Mask: 0x01)                            */
25120  #define R_SCI0_FTDRH_TDATH_Pos         (0UL)      /*!< TDATH (Bit 0)                                         */
25121  #define R_SCI0_FTDRH_TDATH_Msk         (0x1UL)    /*!< TDATH (Bitfield-Mask: 0x01)                           */
25122 /* =========================================================  FTDRL  ========================================================= */
25123  #define R_SCI0_FTDRL_TDATL_Pos         (0UL)      /*!< TDATL (Bit 0)                                         */
25124  #define R_SCI0_FTDRL_TDATL_Msk         (0xffUL)   /*!< TDATL (Bitfield-Mask: 0xff)                           */
25125 /* =========================================================  RDRHL  ========================================================= */
25126  #define R_SCI0_RDRHL_RDRHL_Pos         (0UL)      /*!< RDRHL (Bit 0)                                         */
25127  #define R_SCI0_RDRHL_RDRHL_Msk         (0xffffUL) /*!< RDRHL (Bitfield-Mask: 0xffff)                         */
25128 /* ========================================================  FRDRHL  ========================================================= */
25129  #define R_SCI0_FRDRHL_RDF_Pos          (14UL)     /*!< RDF (Bit 14)                                          */
25130  #define R_SCI0_FRDRHL_RDF_Msk          (0x4000UL) /*!< RDF (Bitfield-Mask: 0x01)                             */
25131  #define R_SCI0_FRDRHL_ORER_Pos         (13UL)     /*!< ORER (Bit 13)                                         */
25132  #define R_SCI0_FRDRHL_ORER_Msk         (0x2000UL) /*!< ORER (Bitfield-Mask: 0x01)                            */
25133  #define R_SCI0_FRDRHL_FER_Pos          (12UL)     /*!< FER (Bit 12)                                          */
25134  #define R_SCI0_FRDRHL_FER_Msk          (0x1000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
25135  #define R_SCI0_FRDRHL_PER_Pos          (11UL)     /*!< PER (Bit 11)                                          */
25136  #define R_SCI0_FRDRHL_PER_Msk          (0x800UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
25137  #define R_SCI0_FRDRHL_DR_Pos           (10UL)     /*!< DR (Bit 10)                                           */
25138  #define R_SCI0_FRDRHL_DR_Msk           (0x400UL)  /*!< DR (Bitfield-Mask: 0x01)                              */
25139  #define R_SCI0_FRDRHL_MPB_Pos          (9UL)      /*!< MPB (Bit 9)                                           */
25140  #define R_SCI0_FRDRHL_MPB_Msk          (0x200UL)  /*!< MPB (Bitfield-Mask: 0x01)                             */
25141  #define R_SCI0_FRDRHL_RDAT_Pos         (0UL)      /*!< RDAT (Bit 0)                                          */
25142  #define R_SCI0_FRDRHL_RDAT_Msk         (0x1ffUL)  /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
25143 /* =========================================================  FRDRH  ========================================================= */
25144  #define R_SCI0_FRDRH_RDF_Pos           (6UL)      /*!< RDF (Bit 6)                                           */
25145  #define R_SCI0_FRDRH_RDF_Msk           (0x40UL)   /*!< RDF (Bitfield-Mask: 0x01)                             */
25146  #define R_SCI0_FRDRH_ORER_Pos          (5UL)      /*!< ORER (Bit 5)                                          */
25147  #define R_SCI0_FRDRH_ORER_Msk          (0x20UL)   /*!< ORER (Bitfield-Mask: 0x01)                            */
25148  #define R_SCI0_FRDRH_FER_Pos           (4UL)      /*!< FER (Bit 4)                                           */
25149  #define R_SCI0_FRDRH_FER_Msk           (0x10UL)   /*!< FER (Bitfield-Mask: 0x01)                             */
25150  #define R_SCI0_FRDRH_PER_Pos           (3UL)      /*!< PER (Bit 3)                                           */
25151  #define R_SCI0_FRDRH_PER_Msk           (0x8UL)    /*!< PER (Bitfield-Mask: 0x01)                             */
25152  #define R_SCI0_FRDRH_DR_Pos            (2UL)      /*!< DR (Bit 2)                                            */
25153  #define R_SCI0_FRDRH_DR_Msk            (0x4UL)    /*!< DR (Bitfield-Mask: 0x01)                              */
25154  #define R_SCI0_FRDRH_MPB_Pos           (1UL)      /*!< MPB (Bit 1)                                           */
25155  #define R_SCI0_FRDRH_MPB_Msk           (0x2UL)    /*!< MPB (Bitfield-Mask: 0x01)                             */
25156  #define R_SCI0_FRDRH_RDATH_Pos         (0UL)      /*!< RDATH (Bit 0)                                         */
25157  #define R_SCI0_FRDRH_RDATH_Msk         (0x1UL)    /*!< RDATH (Bitfield-Mask: 0x01)                           */
25158 /* =========================================================  FRDRL  ========================================================= */
25159  #define R_SCI0_FRDRL_RDATL_Pos         (0UL)      /*!< RDATL (Bit 0)                                         */
25160  #define R_SCI0_FRDRL_RDATL_Msk         (0xffUL)   /*!< RDATL (Bitfield-Mask: 0xff)                           */
25161 /* =========================================================  MDDR  ========================================================== */
25162  #define R_SCI0_MDDR_MDDR_Pos           (0UL)      /*!< MDDR (Bit 0)                                          */
25163  #define R_SCI0_MDDR_MDDR_Msk           (0xffUL)   /*!< MDDR (Bitfield-Mask: 0xff)                            */
25164 /* =========================================================  DCCR  ========================================================== */
25165  #define R_SCI0_DCCR_DCME_Pos           (7UL)      /*!< DCME (Bit 7)                                          */
25166  #define R_SCI0_DCCR_DCME_Msk           (0x80UL)   /*!< DCME (Bitfield-Mask: 0x01)                            */
25167  #define R_SCI0_DCCR_IDSEL_Pos          (6UL)      /*!< IDSEL (Bit 6)                                         */
25168  #define R_SCI0_DCCR_IDSEL_Msk          (0x40UL)   /*!< IDSEL (Bitfield-Mask: 0x01)                           */
25169  #define R_SCI0_DCCR_DFER_Pos           (4UL)      /*!< DFER (Bit 4)                                          */
25170  #define R_SCI0_DCCR_DFER_Msk           (0x10UL)   /*!< DFER (Bitfield-Mask: 0x01)                            */
25171  #define R_SCI0_DCCR_DPER_Pos           (3UL)      /*!< DPER (Bit 3)                                          */
25172  #define R_SCI0_DCCR_DPER_Msk           (0x8UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
25173  #define R_SCI0_DCCR_DCMF_Pos           (0UL)      /*!< DCMF (Bit 0)                                          */
25174  #define R_SCI0_DCCR_DCMF_Msk           (0x1UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
25175 /* ==========================================================  FCR  ========================================================== */
25176  #define R_SCI0_FCR_RSTRG_Pos           (12UL)     /*!< RSTRG (Bit 12)                                        */
25177  #define R_SCI0_FCR_RSTRG_Msk           (0xf000UL) /*!< RSTRG (Bitfield-Mask: 0x0f)                           */
25178  #define R_SCI0_FCR_RTRG_Pos            (8UL)      /*!< RTRG (Bit 8)                                          */
25179  #define R_SCI0_FCR_RTRG_Msk            (0xf00UL)  /*!< RTRG (Bitfield-Mask: 0x0f)                            */
25180  #define R_SCI0_FCR_TTRG_Pos            (4UL)      /*!< TTRG (Bit 4)                                          */
25181  #define R_SCI0_FCR_TTRG_Msk            (0xf0UL)   /*!< TTRG (Bitfield-Mask: 0x0f)                            */
25182  #define R_SCI0_FCR_DRES_Pos            (3UL)      /*!< DRES (Bit 3)                                          */
25183  #define R_SCI0_FCR_DRES_Msk            (0x8UL)    /*!< DRES (Bitfield-Mask: 0x01)                            */
25184  #define R_SCI0_FCR_TFRST_Pos           (2UL)      /*!< TFRST (Bit 2)                                         */
25185  #define R_SCI0_FCR_TFRST_Msk           (0x4UL)    /*!< TFRST (Bitfield-Mask: 0x01)                           */
25186  #define R_SCI0_FCR_RFRST_Pos           (1UL)      /*!< RFRST (Bit 1)                                         */
25187  #define R_SCI0_FCR_RFRST_Msk           (0x2UL)    /*!< RFRST (Bitfield-Mask: 0x01)                           */
25188  #define R_SCI0_FCR_FM_Pos              (0UL)      /*!< FM (Bit 0)                                            */
25189  #define R_SCI0_FCR_FM_Msk              (0x1UL)    /*!< FM (Bitfield-Mask: 0x01)                              */
25190 /* ==========================================================  FDR  ========================================================== */
25191  #define R_SCI0_FDR_T_Pos               (8UL)      /*!< T (Bit 8)                                             */
25192  #define R_SCI0_FDR_T_Msk               (0x1f00UL) /*!< T (Bitfield-Mask: 0x1f)                               */
25193  #define R_SCI0_FDR_R_Pos               (0UL)      /*!< R (Bit 0)                                             */
25194  #define R_SCI0_FDR_R_Msk               (0x1fUL)   /*!< R (Bitfield-Mask: 0x1f)                               */
25195 /* ==========================================================  LSR  ========================================================== */
25196  #define R_SCI0_LSR_PNUM_Pos            (8UL)      /*!< PNUM (Bit 8)                                          */
25197  #define R_SCI0_LSR_PNUM_Msk            (0x1f00UL) /*!< PNUM (Bitfield-Mask: 0x1f)                            */
25198  #define R_SCI0_LSR_FNUM_Pos            (2UL)      /*!< FNUM (Bit 2)                                          */
25199  #define R_SCI0_LSR_FNUM_Msk            (0x7cUL)   /*!< FNUM (Bitfield-Mask: 0x1f)                            */
25200  #define R_SCI0_LSR_ORER_Pos            (0UL)      /*!< ORER (Bit 0)                                          */
25201  #define R_SCI0_LSR_ORER_Msk            (0x1UL)    /*!< ORER (Bitfield-Mask: 0x01)                            */
25202 /* ==========================================================  CDR  ========================================================== */
25203  #define R_SCI0_CDR_CMPD_Pos            (0UL)      /*!< CMPD (Bit 0)                                          */
25204  #define R_SCI0_CDR_CMPD_Msk            (0x1ffUL)  /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
25205 /* =========================================================  SPTR  ========================================================== */
25206  #define R_SCI0_SPTR_SPB2IO_Pos         (2UL)      /*!< SPB2IO (Bit 2)                                        */
25207  #define R_SCI0_SPTR_SPB2IO_Msk         (0x4UL)    /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
25208  #define R_SCI0_SPTR_SPB2DT_Pos         (1UL)      /*!< SPB2DT (Bit 1)                                        */
25209  #define R_SCI0_SPTR_SPB2DT_Msk         (0x2UL)    /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
25210  #define R_SCI0_SPTR_RXDMON_Pos         (0UL)      /*!< RXDMON (Bit 0)                                        */
25211  #define R_SCI0_SPTR_RXDMON_Msk         (0x1UL)    /*!< RXDMON (Bitfield-Mask: 0x01)                          */
25212  #define R_SCI0_SPTR_RINV_Pos           (4UL)      /*!< RINV (Bit 4)                                          */
25213  #define R_SCI0_SPTR_RINV_Msk           (0x10UL)   /*!< RINV (Bitfield-Mask: 0x01)                            */
25214  #define R_SCI0_SPTR_TINV_Pos           (5UL)      /*!< TINV (Bit 5)                                          */
25215  #define R_SCI0_SPTR_TINV_Msk           (0x20UL)   /*!< TINV (Bitfield-Mask: 0x01)                            */
25216  #define R_SCI0_SPTR_ASEN_Pos           (6UL)      /*!< ASEN (Bit 6)                                          */
25217  #define R_SCI0_SPTR_ASEN_Msk           (0x40UL)   /*!< ASEN (Bitfield-Mask: 0x01)                            */
25218  #define R_SCI0_SPTR_ATEN_Pos           (7UL)      /*!< ATEN (Bit 7)                                          */
25219  #define R_SCI0_SPTR_ATEN_Msk           (0x80UL)   /*!< ATEN (Bitfield-Mask: 0x01)                            */
25220 /* =========================================================  ACTR  ========================================================== */
25221  #define R_SCI0_ACTR_AST_Pos            (0UL)      /*!< AST (Bit 0)                                           */
25222  #define R_SCI0_ACTR_AST_Msk            (0x7UL)    /*!< AST (Bitfield-Mask: 0x07)                             */
25223  #define R_SCI0_ACTR_AJD_Pos            (3UL)      /*!< AJD (Bit 3)                                           */
25224  #define R_SCI0_ACTR_AJD_Msk            (0x8UL)    /*!< AJD (Bitfield-Mask: 0x01)                             */
25225  #define R_SCI0_ACTR_ATT_Pos            (4UL)      /*!< ATT (Bit 4)                                           */
25226  #define R_SCI0_ACTR_ATT_Msk            (0x70UL)   /*!< ATT (Bitfield-Mask: 0x07)                             */
25227  #define R_SCI0_ACTR_AET_Pos            (7UL)      /*!< AET (Bit 7)                                           */
25228  #define R_SCI0_ACTR_AET_Msk            (0x80UL)   /*!< AET (Bitfield-Mask: 0x01)                             */
25229 /* =========================================================  ESMER  ========================================================= */
25230  #define R_SCI0_ESMER_ESME_Pos          (0UL)      /*!< ESME (Bit 0)                                          */
25231  #define R_SCI0_ESMER_ESME_Msk          (0x1UL)    /*!< ESME (Bitfield-Mask: 0x01)                            */
25232 /* ==========================================================  CR0  ========================================================== */
25233  #define R_SCI0_CR0_SFSF_Pos            (1UL)      /*!< SFSF (Bit 1)                                          */
25234  #define R_SCI0_CR0_SFSF_Msk            (0x2UL)    /*!< SFSF (Bitfield-Mask: 0x01)                            */
25235  #define R_SCI0_CR0_RXDSF_Pos           (2UL)      /*!< RXDSF (Bit 2)                                         */
25236  #define R_SCI0_CR0_RXDSF_Msk           (0x4UL)    /*!< RXDSF (Bitfield-Mask: 0x01)                           */
25237  #define R_SCI0_CR0_BRME_Pos            (3UL)      /*!< BRME (Bit 3)                                          */
25238  #define R_SCI0_CR0_BRME_Msk            (0x8UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
25239 /* ==========================================================  CR1  ========================================================== */
25240  #define R_SCI0_CR1_BFE_Pos             (0UL)      /*!< BFE (Bit 0)                                           */
25241  #define R_SCI0_CR1_BFE_Msk             (0x1UL)    /*!< BFE (Bitfield-Mask: 0x01)                             */
25242  #define R_SCI0_CR1_CF0RE_Pos           (1UL)      /*!< CF0RE (Bit 1)                                         */
25243  #define R_SCI0_CR1_CF0RE_Msk           (0x2UL)    /*!< CF0RE (Bitfield-Mask: 0x01)                           */
25244  #define R_SCI0_CR1_CF1DS_Pos           (2UL)      /*!< CF1DS (Bit 2)                                         */
25245  #define R_SCI0_CR1_CF1DS_Msk           (0xcUL)    /*!< CF1DS (Bitfield-Mask: 0x03)                           */
25246  #define R_SCI0_CR1_PIBE_Pos            (4UL)      /*!< PIBE (Bit 4)                                          */
25247  #define R_SCI0_CR1_PIBE_Msk            (0x10UL)   /*!< PIBE (Bitfield-Mask: 0x01)                            */
25248  #define R_SCI0_CR1_PIBS_Pos            (5UL)      /*!< PIBS (Bit 5)                                          */
25249  #define R_SCI0_CR1_PIBS_Msk            (0xe0UL)   /*!< PIBS (Bitfield-Mask: 0x07)                            */
25250 /* ==========================================================  CR2  ========================================================== */
25251  #define R_SCI0_CR2_DFCS_Pos            (0UL)      /*!< DFCS (Bit 0)                                          */
25252  #define R_SCI0_CR2_DFCS_Msk            (0x7UL)    /*!< DFCS (Bitfield-Mask: 0x07)                            */
25253  #define R_SCI0_CR2_BCCS_Pos            (4UL)      /*!< BCCS (Bit 4)                                          */
25254  #define R_SCI0_CR2_BCCS_Msk            (0x30UL)   /*!< BCCS (Bitfield-Mask: 0x03)                            */
25255  #define R_SCI0_CR2_RTS_Pos             (6UL)      /*!< RTS (Bit 6)                                           */
25256  #define R_SCI0_CR2_RTS_Msk             (0xc0UL)   /*!< RTS (Bitfield-Mask: 0x03)                             */
25257 /* ==========================================================  CR3  ========================================================== */
25258  #define R_SCI0_CR3_SDST_Pos            (0UL)      /*!< SDST (Bit 0)                                          */
25259  #define R_SCI0_CR3_SDST_Msk            (0x1UL)    /*!< SDST (Bitfield-Mask: 0x01)                            */
25260 /* ==========================================================  PCR  ========================================================== */
25261  #define R_SCI0_PCR_TXDXPS_Pos          (0UL)      /*!< TXDXPS (Bit 0)                                        */
25262  #define R_SCI0_PCR_TXDXPS_Msk          (0x1UL)    /*!< TXDXPS (Bitfield-Mask: 0x01)                          */
25263  #define R_SCI0_PCR_RXDXPS_Pos          (1UL)      /*!< RXDXPS (Bit 1)                                        */
25264  #define R_SCI0_PCR_RXDXPS_Msk          (0x2UL)    /*!< RXDXPS (Bitfield-Mask: 0x01)                          */
25265  #define R_SCI0_PCR_SHARPS_Pos          (4UL)      /*!< SHARPS (Bit 4)                                        */
25266  #define R_SCI0_PCR_SHARPS_Msk          (0x10UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
25267 /* ==========================================================  ICR  ========================================================== */
25268  #define R_SCI0_ICR_BFDIE_Pos           (0UL)      /*!< BFDIE (Bit 0)                                         */
25269  #define R_SCI0_ICR_BFDIE_Msk           (0x1UL)    /*!< BFDIE (Bitfield-Mask: 0x01)                           */
25270  #define R_SCI0_ICR_CF0MIE_Pos          (1UL)      /*!< CF0MIE (Bit 1)                                        */
25271  #define R_SCI0_ICR_CF0MIE_Msk          (0x2UL)    /*!< CF0MIE (Bitfield-Mask: 0x01)                          */
25272  #define R_SCI0_ICR_CF1MIE_Pos          (2UL)      /*!< CF1MIE (Bit 2)                                        */
25273  #define R_SCI0_ICR_CF1MIE_Msk          (0x4UL)    /*!< CF1MIE (Bitfield-Mask: 0x01)                          */
25274  #define R_SCI0_ICR_PIBDIE_Pos          (3UL)      /*!< PIBDIE (Bit 3)                                        */
25275  #define R_SCI0_ICR_PIBDIE_Msk          (0x8UL)    /*!< PIBDIE (Bitfield-Mask: 0x01)                          */
25276  #define R_SCI0_ICR_BCDIE_Pos           (4UL)      /*!< BCDIE (Bit 4)                                         */
25277  #define R_SCI0_ICR_BCDIE_Msk           (0x10UL)   /*!< BCDIE (Bitfield-Mask: 0x01)                           */
25278  #define R_SCI0_ICR_AEDIE_Pos           (5UL)      /*!< AEDIE (Bit 5)                                         */
25279  #define R_SCI0_ICR_AEDIE_Msk           (0x20UL)   /*!< AEDIE (Bitfield-Mask: 0x01)                           */
25280 /* ==========================================================  STR  ========================================================== */
25281  #define R_SCI0_STR_BFDF_Pos            (0UL)      /*!< BFDF (Bit 0)                                          */
25282  #define R_SCI0_STR_BFDF_Msk            (0x1UL)    /*!< BFDF (Bitfield-Mask: 0x01)                            */
25283  #define R_SCI0_STR_CF0MF_Pos           (1UL)      /*!< CF0MF (Bit 1)                                         */
25284  #define R_SCI0_STR_CF0MF_Msk           (0x2UL)    /*!< CF0MF (Bitfield-Mask: 0x01)                           */
25285  #define R_SCI0_STR_CF1MF_Pos           (2UL)      /*!< CF1MF (Bit 2)                                         */
25286  #define R_SCI0_STR_CF1MF_Msk           (0x4UL)    /*!< CF1MF (Bitfield-Mask: 0x01)                           */
25287  #define R_SCI0_STR_PIBDF_Pos           (3UL)      /*!< PIBDF (Bit 3)                                         */
25288  #define R_SCI0_STR_PIBDF_Msk           (0x8UL)    /*!< PIBDF (Bitfield-Mask: 0x01)                           */
25289  #define R_SCI0_STR_BCDF_Pos            (4UL)      /*!< BCDF (Bit 4)                                          */
25290  #define R_SCI0_STR_BCDF_Msk            (0x10UL)   /*!< BCDF (Bitfield-Mask: 0x01)                            */
25291  #define R_SCI0_STR_AEDF_Pos            (5UL)      /*!< AEDF (Bit 5)                                          */
25292  #define R_SCI0_STR_AEDF_Msk            (0x20UL)   /*!< AEDF (Bitfield-Mask: 0x01)                            */
25293 /* =========================================================  STCR  ========================================================== */
25294  #define R_SCI0_STCR_BFDCL_Pos          (0UL)      /*!< BFDCL (Bit 0)                                         */
25295  #define R_SCI0_STCR_BFDCL_Msk          (0x1UL)    /*!< BFDCL (Bitfield-Mask: 0x01)                           */
25296  #define R_SCI0_STCR_CF0MCL_Pos         (1UL)      /*!< CF0MCL (Bit 1)                                        */
25297  #define R_SCI0_STCR_CF0MCL_Msk         (0x2UL)    /*!< CF0MCL (Bitfield-Mask: 0x01)                          */
25298  #define R_SCI0_STCR_CF1MCL_Pos         (2UL)      /*!< CF1MCL (Bit 2)                                        */
25299  #define R_SCI0_STCR_CF1MCL_Msk         (0x4UL)    /*!< CF1MCL (Bitfield-Mask: 0x01)                          */
25300  #define R_SCI0_STCR_PIBDCL_Pos         (3UL)      /*!< PIBDCL (Bit 3)                                        */
25301  #define R_SCI0_STCR_PIBDCL_Msk         (0x8UL)    /*!< PIBDCL (Bitfield-Mask: 0x01)                          */
25302  #define R_SCI0_STCR_BCDCL_Pos          (4UL)      /*!< BCDCL (Bit 4)                                         */
25303  #define R_SCI0_STCR_BCDCL_Msk          (0x10UL)   /*!< BCDCL (Bitfield-Mask: 0x01)                           */
25304  #define R_SCI0_STCR_AEDCL_Pos          (5UL)      /*!< AEDCL (Bit 5)                                         */
25305  #define R_SCI0_STCR_AEDCL_Msk          (0x20UL)   /*!< AEDCL (Bitfield-Mask: 0x01)                           */
25306 /* =========================================================  CF0DR  ========================================================= */
25307 /* =========================================================  CF0CR  ========================================================= */
25308  #define R_SCI0_CF0CR_CF0CE0_Pos        (0UL)      /*!< CF0CE0 (Bit 0)                                        */
25309  #define R_SCI0_CF0CR_CF0CE0_Msk        (0x1UL)    /*!< CF0CE0 (Bitfield-Mask: 0x01)                          */
25310  #define R_SCI0_CF0CR_CF0CE1_Pos        (1UL)      /*!< CF0CE1 (Bit 1)                                        */
25311  #define R_SCI0_CF0CR_CF0CE1_Msk        (0x2UL)    /*!< CF0CE1 (Bitfield-Mask: 0x01)                          */
25312  #define R_SCI0_CF0CR_CF0CE2_Pos        (2UL)      /*!< CF0CE2 (Bit 2)                                        */
25313  #define R_SCI0_CF0CR_CF0CE2_Msk        (0x4UL)    /*!< CF0CE2 (Bitfield-Mask: 0x01)                          */
25314  #define R_SCI0_CF0CR_CF0CE3_Pos        (3UL)      /*!< CF0CE3 (Bit 3)                                        */
25315  #define R_SCI0_CF0CR_CF0CE3_Msk        (0x8UL)    /*!< CF0CE3 (Bitfield-Mask: 0x01)                          */
25316  #define R_SCI0_CF0CR_CF0CE4_Pos        (4UL)      /*!< CF0CE4 (Bit 4)                                        */
25317  #define R_SCI0_CF0CR_CF0CE4_Msk        (0x10UL)   /*!< CF0CE4 (Bitfield-Mask: 0x01)                          */
25318  #define R_SCI0_CF0CR_CF0CE5_Pos        (5UL)      /*!< CF0CE5 (Bit 5)                                        */
25319  #define R_SCI0_CF0CR_CF0CE5_Msk        (0x20UL)   /*!< CF0CE5 (Bitfield-Mask: 0x01)                          */
25320  #define R_SCI0_CF0CR_CF0CE6_Pos        (6UL)      /*!< CF0CE6 (Bit 6)                                        */
25321  #define R_SCI0_CF0CR_CF0CE6_Msk        (0x40UL)   /*!< CF0CE6 (Bitfield-Mask: 0x01)                          */
25322  #define R_SCI0_CF0CR_CF0CE7_Pos        (7UL)      /*!< CF0CE7 (Bit 7)                                        */
25323  #define R_SCI0_CF0CR_CF0CE7_Msk        (0x80UL)   /*!< CF0CE7 (Bitfield-Mask: 0x01)                          */
25324 /* =========================================================  CF0RR  ========================================================= */
25325 /* ========================================================  PCF1DR  ========================================================= */
25326 /* ========================================================  SCF1DR  ========================================================= */
25327 /* =========================================================  CF1CR  ========================================================= */
25328  #define R_SCI0_CF1CR_CF1CE0_Pos        (0UL)    /*!< CF1CE0 (Bit 0)                                        */
25329  #define R_SCI0_CF1CR_CF1CE0_Msk        (0x1UL)  /*!< CF1CE0 (Bitfield-Mask: 0x01)                          */
25330  #define R_SCI0_CF1CR_CF1CE1_Pos        (1UL)    /*!< CF1CE1 (Bit 1)                                        */
25331  #define R_SCI0_CF1CR_CF1CE1_Msk        (0x2UL)  /*!< CF1CE1 (Bitfield-Mask: 0x01)                          */
25332  #define R_SCI0_CF1CR_CF1CE2_Pos        (2UL)    /*!< CF1CE2 (Bit 2)                                        */
25333  #define R_SCI0_CF1CR_CF1CE2_Msk        (0x4UL)  /*!< CF1CE2 (Bitfield-Mask: 0x01)                          */
25334  #define R_SCI0_CF1CR_CF1CE3_Pos        (3UL)    /*!< CF1CE3 (Bit 3)                                        */
25335  #define R_SCI0_CF1CR_CF1CE3_Msk        (0x8UL)  /*!< CF1CE3 (Bitfield-Mask: 0x01)                          */
25336  #define R_SCI0_CF1CR_CF1CE4_Pos        (4UL)    /*!< CF1CE4 (Bit 4)                                        */
25337  #define R_SCI0_CF1CR_CF1CE4_Msk        (0x10UL) /*!< CF1CE4 (Bitfield-Mask: 0x01)                          */
25338  #define R_SCI0_CF1CR_CF1CE5_Pos        (5UL)    /*!< CF1CE5 (Bit 5)                                        */
25339  #define R_SCI0_CF1CR_CF1CE5_Msk        (0x20UL) /*!< CF1CE5 (Bitfield-Mask: 0x01)                          */
25340  #define R_SCI0_CF1CR_CF1CE6_Pos        (6UL)    /*!< CF1CE6 (Bit 6)                                        */
25341  #define R_SCI0_CF1CR_CF1CE6_Msk        (0x40UL) /*!< CF1CE6 (Bitfield-Mask: 0x01)                          */
25342  #define R_SCI0_CF1CR_CF1CE7_Pos        (7UL)    /*!< CF1CE7 (Bit 7)                                        */
25343  #define R_SCI0_CF1CR_CF1CE7_Msk        (0x80UL) /*!< CF1CE7 (Bitfield-Mask: 0x01)                          */
25344 /* =========================================================  CF1RR  ========================================================= */
25345 /* ==========================================================  TCR  ========================================================== */
25346  #define R_SCI0_TCR_TCST_Pos            (0UL)    /*!< TCST (Bit 0)                                          */
25347  #define R_SCI0_TCR_TCST_Msk            (0x1UL)  /*!< TCST (Bitfield-Mask: 0x01)                            */
25348 /* ==========================================================  TMR  ========================================================== */
25349  #define R_SCI0_TMR_TOMS_Pos            (0UL)    /*!< TOMS (Bit 0)                                          */
25350  #define R_SCI0_TMR_TOMS_Msk            (0x3UL)  /*!< TOMS (Bitfield-Mask: 0x03)                            */
25351  #define R_SCI0_TMR_TWRC_Pos            (3UL)    /*!< TWRC (Bit 3)                                          */
25352  #define R_SCI0_TMR_TWRC_Msk            (0x8UL)  /*!< TWRC (Bitfield-Mask: 0x01)                            */
25353  #define R_SCI0_TMR_TCSS_Pos            (4UL)    /*!< TCSS (Bit 4)                                          */
25354  #define R_SCI0_TMR_TCSS_Msk            (0x70UL) /*!< TCSS (Bitfield-Mask: 0x07)                            */
25355 /* =========================================================  TPRE  ========================================================== */
25356 /* =========================================================  TCNT  ========================================================== */
25357 
25358 /* =========================================================================================================================== */
25359 /* ================                                          R_SDHI0                                          ================ */
25360 /* =========================================================================================================================== */
25361 
25362 /* ========================================================  SD_CMD  ========================================================= */
25363  #define R_SDHI0_SD_CMD_CMD12AT_Pos              (14UL)         /*!< CMD12AT (Bit 14)                                      */
25364  #define R_SDHI0_SD_CMD_CMD12AT_Msk              (0xc000UL)     /*!< CMD12AT (Bitfield-Mask: 0x03)                         */
25365  #define R_SDHI0_SD_CMD_TRSTP_Pos                (13UL)         /*!< TRSTP (Bit 13)                                        */
25366  #define R_SDHI0_SD_CMD_TRSTP_Msk                (0x2000UL)     /*!< TRSTP (Bitfield-Mask: 0x01)                           */
25367  #define R_SDHI0_SD_CMD_CMDRW_Pos                (12UL)         /*!< CMDRW (Bit 12)                                        */
25368  #define R_SDHI0_SD_CMD_CMDRW_Msk                (0x1000UL)     /*!< CMDRW (Bitfield-Mask: 0x01)                           */
25369  #define R_SDHI0_SD_CMD_CMDTP_Pos                (11UL)         /*!< CMDTP (Bit 11)                                        */
25370  #define R_SDHI0_SD_CMD_CMDTP_Msk                (0x800UL)      /*!< CMDTP (Bitfield-Mask: 0x01)                           */
25371  #define R_SDHI0_SD_CMD_RSPTP_Pos                (8UL)          /*!< RSPTP (Bit 8)                                         */
25372  #define R_SDHI0_SD_CMD_RSPTP_Msk                (0x700UL)      /*!< RSPTP (Bitfield-Mask: 0x07)                           */
25373  #define R_SDHI0_SD_CMD_ACMD_Pos                 (6UL)          /*!< ACMD (Bit 6)                                          */
25374  #define R_SDHI0_SD_CMD_ACMD_Msk                 (0xc0UL)       /*!< ACMD (Bitfield-Mask: 0x03)                            */
25375  #define R_SDHI0_SD_CMD_CMDIDX_Pos               (0UL)          /*!< CMDIDX (Bit 0)                                        */
25376  #define R_SDHI0_SD_CMD_CMDIDX_Msk               (0x3fUL)       /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
25377 /* ========================================================  SD_ARG  ========================================================= */
25378  #define R_SDHI0_SD_ARG_SD_ARG_Pos               (0UL)          /*!< SD_ARG (Bit 0)                                        */
25379  #define R_SDHI0_SD_ARG_SD_ARG_Msk               (0xffffffffUL) /*!< SD_ARG (Bitfield-Mask: 0xffffffff)                    */
25380 /* ========================================================  SD_ARG1  ======================================================== */
25381  #define R_SDHI0_SD_ARG1_SD_ARG1_Pos             (0UL)          /*!< SD_ARG1 (Bit 0)                                       */
25382  #define R_SDHI0_SD_ARG1_SD_ARG1_Msk             (0xffffUL)     /*!< SD_ARG1 (Bitfield-Mask: 0xffff)                       */
25383 /* ========================================================  SD_STOP  ======================================================== */
25384  #define R_SDHI0_SD_STOP_SEC_Pos                 (8UL)          /*!< SEC (Bit 8)                                           */
25385  #define R_SDHI0_SD_STOP_SEC_Msk                 (0x100UL)      /*!< SEC (Bitfield-Mask: 0x01)                             */
25386  #define R_SDHI0_SD_STOP_STP_Pos                 (0UL)          /*!< STP (Bit 0)                                           */
25387  #define R_SDHI0_SD_STOP_STP_Msk                 (0x1UL)        /*!< STP (Bitfield-Mask: 0x01)                             */
25388 /* =======================================================  SD_SECCNT  ======================================================= */
25389  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Pos         (0UL)          /*!< SD_SECCNT (Bit 0)                                     */
25390  #define R_SDHI0_SD_SECCNT_SD_SECCNT_Msk         (0xffffffffUL) /*!< SD_SECCNT (Bitfield-Mask: 0xffffffff)                 */
25391 /* =======================================================  SD_RSP10  ======================================================== */
25392  #define R_SDHI0_SD_RSP10_SD_RSP10_Pos           (0UL)          /*!< SD_RSP10 (Bit 0)                                      */
25393  #define R_SDHI0_SD_RSP10_SD_RSP10_Msk           (0xffffffffUL) /*!< SD_RSP10 (Bitfield-Mask: 0xffffffff)                  */
25394 /* ========================================================  SD_RSP1  ======================================================== */
25395  #define R_SDHI0_SD_RSP1_SD_RSP1_Pos             (0UL)          /*!< SD_RSP1 (Bit 0)                                       */
25396  #define R_SDHI0_SD_RSP1_SD_RSP1_Msk             (0xffffUL)     /*!< SD_RSP1 (Bitfield-Mask: 0xffff)                       */
25397 /* =======================================================  SD_RSP32  ======================================================== */
25398  #define R_SDHI0_SD_RSP32_SD_RSP32_Pos           (0UL)          /*!< SD_RSP32 (Bit 0)                                      */
25399  #define R_SDHI0_SD_RSP32_SD_RSP32_Msk           (0xffffffffUL) /*!< SD_RSP32 (Bitfield-Mask: 0xffffffff)                  */
25400 /* ========================================================  SD_RSP3  ======================================================== */
25401  #define R_SDHI0_SD_RSP3_SD_RSP3_Pos             (0UL)          /*!< SD_RSP3 (Bit 0)                                       */
25402  #define R_SDHI0_SD_RSP3_SD_RSP3_Msk             (0xffffUL)     /*!< SD_RSP3 (Bitfield-Mask: 0xffff)                       */
25403 /* =======================================================  SD_RSP54  ======================================================== */
25404  #define R_SDHI0_SD_RSP54_SD_RSP54_Pos           (0UL)          /*!< SD_RSP54 (Bit 0)                                      */
25405  #define R_SDHI0_SD_RSP54_SD_RSP54_Msk           (0xffffffffUL) /*!< SD_RSP54 (Bitfield-Mask: 0xffffffff)                  */
25406 /* ========================================================  SD_RSP5  ======================================================== */
25407  #define R_SDHI0_SD_RSP5_SD_RSP5_Pos             (0UL)          /*!< SD_RSP5 (Bit 0)                                       */
25408  #define R_SDHI0_SD_RSP5_SD_RSP5_Msk             (0xffffUL)     /*!< SD_RSP5 (Bitfield-Mask: 0xffff)                       */
25409 /* =======================================================  SD_RSP76  ======================================================== */
25410  #define R_SDHI0_SD_RSP76_SD_RSP76_Pos           (0UL)          /*!< SD_RSP76 (Bit 0)                                      */
25411  #define R_SDHI0_SD_RSP76_SD_RSP76_Msk           (0xffffffUL)   /*!< SD_RSP76 (Bitfield-Mask: 0xffffff)                    */
25412 /* ========================================================  SD_RSP7  ======================================================== */
25413  #define R_SDHI0_SD_RSP7_SD_RSP7_Pos             (0UL)          /*!< SD_RSP7 (Bit 0)                                       */
25414  #define R_SDHI0_SD_RSP7_SD_RSP7_Msk             (0xffUL)       /*!< SD_RSP7 (Bitfield-Mask: 0xff)                         */
25415 /* =======================================================  SD_INFO1  ======================================================== */
25416  #define R_SDHI0_SD_INFO1_SDD3MON_Pos            (10UL)         /*!< SDD3MON (Bit 10)                                      */
25417  #define R_SDHI0_SD_INFO1_SDD3MON_Msk            (0x400UL)      /*!< SDD3MON (Bitfield-Mask: 0x01)                         */
25418  #define R_SDHI0_SD_INFO1_SDD3IN_Pos             (9UL)          /*!< SDD3IN (Bit 9)                                        */
25419  #define R_SDHI0_SD_INFO1_SDD3IN_Msk             (0x200UL)      /*!< SDD3IN (Bitfield-Mask: 0x01)                          */
25420  #define R_SDHI0_SD_INFO1_SDD3RM_Pos             (8UL)          /*!< SDD3RM (Bit 8)                                        */
25421  #define R_SDHI0_SD_INFO1_SDD3RM_Msk             (0x100UL)      /*!< SDD3RM (Bitfield-Mask: 0x01)                          */
25422  #define R_SDHI0_SD_INFO1_SDWPMON_Pos            (7UL)          /*!< SDWPMON (Bit 7)                                       */
25423  #define R_SDHI0_SD_INFO1_SDWPMON_Msk            (0x80UL)       /*!< SDWPMON (Bitfield-Mask: 0x01)                         */
25424  #define R_SDHI0_SD_INFO1_SDCDMON_Pos            (5UL)          /*!< SDCDMON (Bit 5)                                       */
25425  #define R_SDHI0_SD_INFO1_SDCDMON_Msk            (0x20UL)       /*!< SDCDMON (Bitfield-Mask: 0x01)                         */
25426  #define R_SDHI0_SD_INFO1_SDCDIN_Pos             (4UL)          /*!< SDCDIN (Bit 4)                                        */
25427  #define R_SDHI0_SD_INFO1_SDCDIN_Msk             (0x10UL)       /*!< SDCDIN (Bitfield-Mask: 0x01)                          */
25428  #define R_SDHI0_SD_INFO1_SDCDRM_Pos             (3UL)          /*!< SDCDRM (Bit 3)                                        */
25429  #define R_SDHI0_SD_INFO1_SDCDRM_Msk             (0x8UL)        /*!< SDCDRM (Bitfield-Mask: 0x01)                          */
25430  #define R_SDHI0_SD_INFO1_ACEND_Pos              (2UL)          /*!< ACEND (Bit 2)                                         */
25431  #define R_SDHI0_SD_INFO1_ACEND_Msk              (0x4UL)        /*!< ACEND (Bitfield-Mask: 0x01)                           */
25432  #define R_SDHI0_SD_INFO1_RSPEND_Pos             (0UL)          /*!< RSPEND (Bit 0)                                        */
25433  #define R_SDHI0_SD_INFO1_RSPEND_Msk             (0x1UL)        /*!< RSPEND (Bitfield-Mask: 0x01)                          */
25434 /* =======================================================  SD_INFO2  ======================================================== */
25435  #define R_SDHI0_SD_INFO2_ILA_Pos                (15UL)         /*!< ILA (Bit 15)                                          */
25436  #define R_SDHI0_SD_INFO2_ILA_Msk                (0x8000UL)     /*!< ILA (Bitfield-Mask: 0x01)                             */
25437  #define R_SDHI0_SD_INFO2_CBSY_Pos               (14UL)         /*!< CBSY (Bit 14)                                         */
25438  #define R_SDHI0_SD_INFO2_CBSY_Msk               (0x4000UL)     /*!< CBSY (Bitfield-Mask: 0x01)                            */
25439  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Pos      (13UL)         /*!< SD_CLK_CTRLEN (Bit 13)                                */
25440  #define R_SDHI0_SD_INFO2_SD_CLK_CTRLEN_Msk      (0x2000UL)     /*!< SD_CLK_CTRLEN (Bitfield-Mask: 0x01)                   */
25441  #define R_SDHI0_SD_INFO2_BWE_Pos                (9UL)          /*!< BWE (Bit 9)                                           */
25442  #define R_SDHI0_SD_INFO2_BWE_Msk                (0x200UL)      /*!< BWE (Bitfield-Mask: 0x01)                             */
25443  #define R_SDHI0_SD_INFO2_BRE_Pos                (8UL)          /*!< BRE (Bit 8)                                           */
25444  #define R_SDHI0_SD_INFO2_BRE_Msk                (0x100UL)      /*!< BRE (Bitfield-Mask: 0x01)                             */
25445  #define R_SDHI0_SD_INFO2_SDD0MON_Pos            (7UL)          /*!< SDD0MON (Bit 7)                                       */
25446  #define R_SDHI0_SD_INFO2_SDD0MON_Msk            (0x80UL)       /*!< SDD0MON (Bitfield-Mask: 0x01)                         */
25447  #define R_SDHI0_SD_INFO2_RSPTO_Pos              (6UL)          /*!< RSPTO (Bit 6)                                         */
25448  #define R_SDHI0_SD_INFO2_RSPTO_Msk              (0x40UL)       /*!< RSPTO (Bitfield-Mask: 0x01)                           */
25449  #define R_SDHI0_SD_INFO2_ILR_Pos                (5UL)          /*!< ILR (Bit 5)                                           */
25450  #define R_SDHI0_SD_INFO2_ILR_Msk                (0x20UL)       /*!< ILR (Bitfield-Mask: 0x01)                             */
25451  #define R_SDHI0_SD_INFO2_ILW_Pos                (4UL)          /*!< ILW (Bit 4)                                           */
25452  #define R_SDHI0_SD_INFO2_ILW_Msk                (0x10UL)       /*!< ILW (Bitfield-Mask: 0x01)                             */
25453  #define R_SDHI0_SD_INFO2_DTO_Pos                (3UL)          /*!< DTO (Bit 3)                                           */
25454  #define R_SDHI0_SD_INFO2_DTO_Msk                (0x8UL)        /*!< DTO (Bitfield-Mask: 0x01)                             */
25455  #define R_SDHI0_SD_INFO2_ENDE_Pos               (2UL)          /*!< ENDE (Bit 2)                                          */
25456  #define R_SDHI0_SD_INFO2_ENDE_Msk               (0x4UL)        /*!< ENDE (Bitfield-Mask: 0x01)                            */
25457  #define R_SDHI0_SD_INFO2_CRCE_Pos               (1UL)          /*!< CRCE (Bit 1)                                          */
25458  #define R_SDHI0_SD_INFO2_CRCE_Msk               (0x2UL)        /*!< CRCE (Bitfield-Mask: 0x01)                            */
25459  #define R_SDHI0_SD_INFO2_CMDE_Pos               (0UL)          /*!< CMDE (Bit 0)                                          */
25460  #define R_SDHI0_SD_INFO2_CMDE_Msk               (0x1UL)        /*!< CMDE (Bitfield-Mask: 0x01)                            */
25461 /* =====================================================  SD_INFO1_MASK  ===================================================== */
25462  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Pos       (9UL)          /*!< SDD3INM (Bit 9)                                       */
25463  #define R_SDHI0_SD_INFO1_MASK_SDD3INM_Msk       (0x200UL)      /*!< SDD3INM (Bitfield-Mask: 0x01)                         */
25464  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Pos       (8UL)          /*!< SDD3RMM (Bit 8)                                       */
25465  #define R_SDHI0_SD_INFO1_MASK_SDD3RMM_Msk       (0x100UL)      /*!< SDD3RMM (Bitfield-Mask: 0x01)                         */
25466  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Pos       (4UL)          /*!< SDCDINM (Bit 4)                                       */
25467  #define R_SDHI0_SD_INFO1_MASK_SDCDINM_Msk       (0x10UL)       /*!< SDCDINM (Bitfield-Mask: 0x01)                         */
25468  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Pos       (3UL)          /*!< SDCDRMM (Bit 3)                                       */
25469  #define R_SDHI0_SD_INFO1_MASK_SDCDRMM_Msk       (0x8UL)        /*!< SDCDRMM (Bitfield-Mask: 0x01)                         */
25470  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Pos        (2UL)          /*!< ACENDM (Bit 2)                                        */
25471  #define R_SDHI0_SD_INFO1_MASK_ACENDM_Msk        (0x4UL)        /*!< ACENDM (Bitfield-Mask: 0x01)                          */
25472  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Pos       (0UL)          /*!< RSPENDM (Bit 0)                                       */
25473  #define R_SDHI0_SD_INFO1_MASK_RSPENDM_Msk       (0x1UL)        /*!< RSPENDM (Bitfield-Mask: 0x01)                         */
25474 /* =====================================================  SD_INFO2_MASK  ===================================================== */
25475  #define R_SDHI0_SD_INFO2_MASK_ILAM_Pos          (15UL)         /*!< ILAM (Bit 15)                                         */
25476  #define R_SDHI0_SD_INFO2_MASK_ILAM_Msk          (0x8000UL)     /*!< ILAM (Bitfield-Mask: 0x01)                            */
25477  #define R_SDHI0_SD_INFO2_MASK_BWEM_Pos          (9UL)          /*!< BWEM (Bit 9)                                          */
25478  #define R_SDHI0_SD_INFO2_MASK_BWEM_Msk          (0x200UL)      /*!< BWEM (Bitfield-Mask: 0x01)                            */
25479  #define R_SDHI0_SD_INFO2_MASK_BREM_Pos          (8UL)          /*!< BREM (Bit 8)                                          */
25480  #define R_SDHI0_SD_INFO2_MASK_BREM_Msk          (0x100UL)      /*!< BREM (Bitfield-Mask: 0x01)                            */
25481  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Pos        (6UL)          /*!< RSPTOM (Bit 6)                                        */
25482  #define R_SDHI0_SD_INFO2_MASK_RSPTOM_Msk        (0x40UL)       /*!< RSPTOM (Bitfield-Mask: 0x01)                          */
25483  #define R_SDHI0_SD_INFO2_MASK_ILRM_Pos          (5UL)          /*!< ILRM (Bit 5)                                          */
25484  #define R_SDHI0_SD_INFO2_MASK_ILRM_Msk          (0x20UL)       /*!< ILRM (Bitfield-Mask: 0x01)                            */
25485  #define R_SDHI0_SD_INFO2_MASK_ILWM_Pos          (4UL)          /*!< ILWM (Bit 4)                                          */
25486  #define R_SDHI0_SD_INFO2_MASK_ILWM_Msk          (0x10UL)       /*!< ILWM (Bitfield-Mask: 0x01)                            */
25487  #define R_SDHI0_SD_INFO2_MASK_DTOM_Pos          (3UL)          /*!< DTOM (Bit 3)                                          */
25488  #define R_SDHI0_SD_INFO2_MASK_DTOM_Msk          (0x8UL)        /*!< DTOM (Bitfield-Mask: 0x01)                            */
25489  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Pos         (2UL)          /*!< ENDEM (Bit 2)                                         */
25490  #define R_SDHI0_SD_INFO2_MASK_ENDEM_Msk         (0x4UL)        /*!< ENDEM (Bitfield-Mask: 0x01)                           */
25491  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Pos         (1UL)          /*!< CRCEM (Bit 1)                                         */
25492  #define R_SDHI0_SD_INFO2_MASK_CRCEM_Msk         (0x2UL)        /*!< CRCEM (Bitfield-Mask: 0x01)                           */
25493  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Pos         (0UL)          /*!< CMDEM (Bit 0)                                         */
25494  #define R_SDHI0_SD_INFO2_MASK_CMDEM_Msk         (0x1UL)        /*!< CMDEM (Bitfield-Mask: 0x01)                           */
25495 /* ======================================================  SD_CLK_CTRL  ====================================================== */
25496  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Pos       (9UL)          /*!< CLKCTRLEN (Bit 9)                                     */
25497  #define R_SDHI0_SD_CLK_CTRL_CLKCTRLEN_Msk       (0x200UL)      /*!< CLKCTRLEN (Bitfield-Mask: 0x01)                       */
25498  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Pos           (8UL)          /*!< CLKEN (Bit 8)                                         */
25499  #define R_SDHI0_SD_CLK_CTRL_CLKEN_Msk           (0x100UL)      /*!< CLKEN (Bitfield-Mask: 0x01)                           */
25500  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Pos          (0UL)          /*!< CLKSEL (Bit 0)                                        */
25501  #define R_SDHI0_SD_CLK_CTRL_CLKSEL_Msk          (0xffUL)       /*!< CLKSEL (Bitfield-Mask: 0xff)                          */
25502 /* ========================================================  SD_SIZE  ======================================================== */
25503  #define R_SDHI0_SD_SIZE_LEN_Pos                 (0UL)          /*!< LEN (Bit 0)                                           */
25504  #define R_SDHI0_SD_SIZE_LEN_Msk                 (0x3ffUL)      /*!< LEN (Bitfield-Mask: 0x3ff)                            */
25505 /* =======================================================  SD_OPTION  ======================================================= */
25506  #define R_SDHI0_SD_OPTION_WIDTH_Pos             (15UL)         /*!< WIDTH (Bit 15)                                        */
25507  #define R_SDHI0_SD_OPTION_WIDTH_Msk             (0x8000UL)     /*!< WIDTH (Bitfield-Mask: 0x01)                           */
25508  #define R_SDHI0_SD_OPTION_WIDTH8_Pos            (13UL)         /*!< WIDTH8 (Bit 13)                                       */
25509  #define R_SDHI0_SD_OPTION_WIDTH8_Msk            (0x2000UL)     /*!< WIDTH8 (Bitfield-Mask: 0x01)                          */
25510  #define R_SDHI0_SD_OPTION_TOUTMASK_Pos          (8UL)          /*!< TOUTMASK (Bit 8)                                      */
25511  #define R_SDHI0_SD_OPTION_TOUTMASK_Msk          (0x100UL)      /*!< TOUTMASK (Bitfield-Mask: 0x01)                        */
25512  #define R_SDHI0_SD_OPTION_TOP_Pos               (4UL)          /*!< TOP (Bit 4)                                           */
25513  #define R_SDHI0_SD_OPTION_TOP_Msk               (0xf0UL)       /*!< TOP (Bitfield-Mask: 0x0f)                             */
25514  #define R_SDHI0_SD_OPTION_CTOP_Pos              (0UL)          /*!< CTOP (Bit 0)                                          */
25515  #define R_SDHI0_SD_OPTION_CTOP_Msk              (0xfUL)        /*!< CTOP (Bitfield-Mask: 0x0f)                            */
25516 /* ======================================================  SD_ERR_STS1  ====================================================== */
25517  #define R_SDHI0_SD_ERR_STS1_CRCTK_Pos           (12UL)         /*!< CRCTK (Bit 12)                                        */
25518  #define R_SDHI0_SD_ERR_STS1_CRCTK_Msk           (0x7000UL)     /*!< CRCTK (Bitfield-Mask: 0x07)                           */
25519  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Pos          (11UL)         /*!< CRCTKE (Bit 11)                                       */
25520  #define R_SDHI0_SD_ERR_STS1_CRCTKE_Msk          (0x800UL)      /*!< CRCTKE (Bitfield-Mask: 0x01)                          */
25521  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Pos          (10UL)         /*!< RDCRCE (Bit 10)                                       */
25522  #define R_SDHI0_SD_ERR_STS1_RDCRCE_Msk          (0x400UL)      /*!< RDCRCE (Bitfield-Mask: 0x01)                          */
25523  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Pos        (9UL)          /*!< RSPCRCE1 (Bit 9)                                      */
25524  #define R_SDHI0_SD_ERR_STS1_RSPCRCE1_Msk        (0x200UL)      /*!< RSPCRCE1 (Bitfield-Mask: 0x01)                        */
25525  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Pos        (8UL)          /*!< RSPCRCE0 (Bit 8)                                      */
25526  #define R_SDHI0_SD_ERR_STS1_RSPCRCE0_Msk        (0x100UL)      /*!< RSPCRCE0 (Bitfield-Mask: 0x01)                        */
25527  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Pos         (5UL)          /*!< CRCLENE (Bit 5)                                       */
25528  #define R_SDHI0_SD_ERR_STS1_CRCLENE_Msk         (0x20UL)       /*!< CRCLENE (Bitfield-Mask: 0x01)                         */
25529  #define R_SDHI0_SD_ERR_STS1_RDLENE_Pos          (4UL)          /*!< RDLENE (Bit 4)                                        */
25530  #define R_SDHI0_SD_ERR_STS1_RDLENE_Msk          (0x10UL)       /*!< RDLENE (Bitfield-Mask: 0x01)                          */
25531  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Pos        (3UL)          /*!< RSPLENE1 (Bit 3)                                      */
25532  #define R_SDHI0_SD_ERR_STS1_RSPLENE1_Msk        (0x8UL)        /*!< RSPLENE1 (Bitfield-Mask: 0x01)                        */
25533  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Pos        (2UL)          /*!< RSPLENE0 (Bit 2)                                      */
25534  #define R_SDHI0_SD_ERR_STS1_RSPLENE0_Msk        (0x4UL)        /*!< RSPLENE0 (Bitfield-Mask: 0x01)                        */
25535  #define R_SDHI0_SD_ERR_STS1_CMDE1_Pos           (1UL)          /*!< CMDE1 (Bit 1)                                         */
25536  #define R_SDHI0_SD_ERR_STS1_CMDE1_Msk           (0x2UL)        /*!< CMDE1 (Bitfield-Mask: 0x01)                           */
25537  #define R_SDHI0_SD_ERR_STS1_CMDE0_Pos           (0UL)          /*!< CMDE0 (Bit 0)                                         */
25538  #define R_SDHI0_SD_ERR_STS1_CMDE0_Msk           (0x1UL)        /*!< CMDE0 (Bitfield-Mask: 0x01)                           */
25539 /* ======================================================  SD_ERR_STS2  ====================================================== */
25540  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Pos        (6UL)          /*!< CRCBSYTO (Bit 6)                                      */
25541  #define R_SDHI0_SD_ERR_STS2_CRCBSYTO_Msk        (0x40UL)       /*!< CRCBSYTO (Bitfield-Mask: 0x01)                        */
25542  #define R_SDHI0_SD_ERR_STS2_CRCTO_Pos           (5UL)          /*!< CRCTO (Bit 5)                                         */
25543  #define R_SDHI0_SD_ERR_STS2_CRCTO_Msk           (0x20UL)       /*!< CRCTO (Bitfield-Mask: 0x01)                           */
25544  #define R_SDHI0_SD_ERR_STS2_RDTO_Pos            (4UL)          /*!< RDTO (Bit 4)                                          */
25545  #define R_SDHI0_SD_ERR_STS2_RDTO_Msk            (0x10UL)       /*!< RDTO (Bitfield-Mask: 0x01)                            */
25546  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Pos          (3UL)          /*!< BSYTO1 (Bit 3)                                        */
25547  #define R_SDHI0_SD_ERR_STS2_BSYTO1_Msk          (0x8UL)        /*!< BSYTO1 (Bitfield-Mask: 0x01)                          */
25548  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Pos          (2UL)          /*!< BSYTO0 (Bit 2)                                        */
25549  #define R_SDHI0_SD_ERR_STS2_BSYTO0_Msk          (0x4UL)        /*!< BSYTO0 (Bitfield-Mask: 0x01)                          */
25550  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Pos          (1UL)          /*!< RSPTO1 (Bit 1)                                        */
25551  #define R_SDHI0_SD_ERR_STS2_RSPTO1_Msk          (0x2UL)        /*!< RSPTO1 (Bitfield-Mask: 0x01)                          */
25552  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Pos          (0UL)          /*!< RSPTO0 (Bit 0)                                        */
25553  #define R_SDHI0_SD_ERR_STS2_RSPTO0_Msk          (0x1UL)        /*!< RSPTO0 (Bitfield-Mask: 0x01)                          */
25554 /* ========================================================  SD_BUF0  ======================================================== */
25555  #define R_SDHI0_SD_BUF0_SD_BUF_Pos              (0UL)          /*!< SD_BUF (Bit 0)                                        */
25556  #define R_SDHI0_SD_BUF0_SD_BUF_Msk              (0xffffffffUL) /*!< SD_BUF (Bitfield-Mask: 0xffffffff)                    */
25557 /* =======================================================  SDIO_MODE  ======================================================= */
25558  #define R_SDHI0_SDIO_MODE_C52PUB_Pos            (9UL)          /*!< C52PUB (Bit 9)                                        */
25559  #define R_SDHI0_SDIO_MODE_C52PUB_Msk            (0x200UL)      /*!< C52PUB (Bitfield-Mask: 0x01)                          */
25560  #define R_SDHI0_SDIO_MODE_IOABT_Pos             (8UL)          /*!< IOABT (Bit 8)                                         */
25561  #define R_SDHI0_SDIO_MODE_IOABT_Msk             (0x100UL)      /*!< IOABT (Bitfield-Mask: 0x01)                           */
25562  #define R_SDHI0_SDIO_MODE_RWREQ_Pos             (2UL)          /*!< RWREQ (Bit 2)                                         */
25563  #define R_SDHI0_SDIO_MODE_RWREQ_Msk             (0x4UL)        /*!< RWREQ (Bitfield-Mask: 0x01)                           */
25564  #define R_SDHI0_SDIO_MODE_INTEN_Pos             (0UL)          /*!< INTEN (Bit 0)                                         */
25565  #define R_SDHI0_SDIO_MODE_INTEN_Msk             (0x1UL)        /*!< INTEN (Bitfield-Mask: 0x01)                           */
25566 /* ======================================================  SDIO_INFO1  ======================================================= */
25567  #define R_SDHI0_SDIO_INFO1_EXWT_Pos             (15UL)         /*!< EXWT (Bit 15)                                         */
25568  #define R_SDHI0_SDIO_INFO1_EXWT_Msk             (0x8000UL)     /*!< EXWT (Bitfield-Mask: 0x01)                            */
25569  #define R_SDHI0_SDIO_INFO1_EXPUB52_Pos          (14UL)         /*!< EXPUB52 (Bit 14)                                      */
25570  #define R_SDHI0_SDIO_INFO1_EXPUB52_Msk          (0x4000UL)     /*!< EXPUB52 (Bitfield-Mask: 0x01)                         */
25571  #define R_SDHI0_SDIO_INFO1_IOIRQ_Pos            (0UL)          /*!< IOIRQ (Bit 0)                                         */
25572  #define R_SDHI0_SDIO_INFO1_IOIRQ_Msk            (0x1UL)        /*!< IOIRQ (Bitfield-Mask: 0x01)                           */
25573 /* ====================================================  SDIO_INFO1_MASK  ==================================================== */
25574  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Pos       (15UL)         /*!< EXWTM (Bit 15)                                        */
25575  #define R_SDHI0_SDIO_INFO1_MASK_EXWTM_Msk       (0x8000UL)     /*!< EXWTM (Bitfield-Mask: 0x01)                           */
25576  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Pos    (14UL)         /*!< EXPUB52M (Bit 14)                                     */
25577  #define R_SDHI0_SDIO_INFO1_MASK_EXPUB52M_Msk    (0x4000UL)     /*!< EXPUB52M (Bitfield-Mask: 0x01)                        */
25578  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Pos      (0UL)          /*!< IOIRQM (Bit 0)                                        */
25579  #define R_SDHI0_SDIO_INFO1_MASK_IOIRQM_Msk      (0x1UL)        /*!< IOIRQM (Bitfield-Mask: 0x01)                          */
25580 /* =======================================================  SD_DMAEN  ======================================================== */
25581  #define R_SDHI0_SD_DMAEN_DMAEN_Pos              (1UL)          /*!< DMAEN (Bit 1)                                         */
25582  #define R_SDHI0_SD_DMAEN_DMAEN_Msk              (0x2UL)        /*!< DMAEN (Bitfield-Mask: 0x01)                           */
25583 /* =======================================================  SOFT_RST  ======================================================== */
25584  #define R_SDHI0_SOFT_RST_SDRST_Pos              (0UL)          /*!< SDRST (Bit 0)                                         */
25585  #define R_SDHI0_SOFT_RST_SDRST_Msk              (0x1UL)        /*!< SDRST (Bitfield-Mask: 0x01)                           */
25586 /* =======================================================  SDIF_MODE  ======================================================= */
25587  #define R_SDHI0_SDIF_MODE_NOCHKCR_Pos           (8UL)          /*!< NOCHKCR (Bit 8)                                       */
25588  #define R_SDHI0_SDIF_MODE_NOCHKCR_Msk           (0x100UL)      /*!< NOCHKCR (Bitfield-Mask: 0x01)                         */
25589 /* =======================================================  EXT_SWAP  ======================================================== */
25590  #define R_SDHI0_EXT_SWAP_BRSWP_Pos              (7UL)          /*!< BRSWP (Bit 7)                                         */
25591  #define R_SDHI0_EXT_SWAP_BRSWP_Msk              (0x80UL)       /*!< BRSWP (Bitfield-Mask: 0x01)                           */
25592  #define R_SDHI0_EXT_SWAP_BWSWP_Pos              (6UL)          /*!< BWSWP (Bit 6)                                         */
25593  #define R_SDHI0_EXT_SWAP_BWSWP_Msk              (0x40UL)       /*!< BWSWP (Bitfield-Mask: 0x01)                           */
25594 
25595 /* =========================================================================================================================== */
25596 /* ================                                          R_SPI0                                           ================ */
25597 /* =========================================================================================================================== */
25598 
25599 /* =========================================================  SPCR  ========================================================== */
25600  #define R_SPI0_SPCR_SPRIE_Pos      (7UL)    /*!< SPRIE (Bit 7)                                         */
25601  #define R_SPI0_SPCR_SPRIE_Msk      (0x80UL) /*!< SPRIE (Bitfield-Mask: 0x01)                           */
25602  #define R_SPI0_SPCR_SPE_Pos        (6UL)    /*!< SPE (Bit 6)                                           */
25603  #define R_SPI0_SPCR_SPE_Msk        (0x40UL) /*!< SPE (Bitfield-Mask: 0x01)                             */
25604  #define R_SPI0_SPCR_SPTIE_Pos      (5UL)    /*!< SPTIE (Bit 5)                                         */
25605  #define R_SPI0_SPCR_SPTIE_Msk      (0x20UL) /*!< SPTIE (Bitfield-Mask: 0x01)                           */
25606  #define R_SPI0_SPCR_SPEIE_Pos      (4UL)    /*!< SPEIE (Bit 4)                                         */
25607  #define R_SPI0_SPCR_SPEIE_Msk      (0x10UL) /*!< SPEIE (Bitfield-Mask: 0x01)                           */
25608  #define R_SPI0_SPCR_MSTR_Pos       (3UL)    /*!< MSTR (Bit 3)                                          */
25609  #define R_SPI0_SPCR_MSTR_Msk       (0x8UL)  /*!< MSTR (Bitfield-Mask: 0x01)                            */
25610  #define R_SPI0_SPCR_MODFEN_Pos     (2UL)    /*!< MODFEN (Bit 2)                                        */
25611  #define R_SPI0_SPCR_MODFEN_Msk     (0x4UL)  /*!< MODFEN (Bitfield-Mask: 0x01)                          */
25612  #define R_SPI0_SPCR_TXMD_Pos       (1UL)    /*!< TXMD (Bit 1)                                          */
25613  #define R_SPI0_SPCR_TXMD_Msk       (0x2UL)  /*!< TXMD (Bitfield-Mask: 0x01)                            */
25614  #define R_SPI0_SPCR_SPMS_Pos       (0UL)    /*!< SPMS (Bit 0)                                          */
25615  #define R_SPI0_SPCR_SPMS_Msk       (0x1UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
25616 /* =========================================================  SSLP  ========================================================== */
25617  #define R_SPI0_SSLP_SSL3P_Pos      (3UL)    /*!< SSL3P (Bit 3)                                         */
25618  #define R_SPI0_SSLP_SSL3P_Msk      (0x8UL)  /*!< SSL3P (Bitfield-Mask: 0x01)                           */
25619  #define R_SPI0_SSLP_SSL2P_Pos      (2UL)    /*!< SSL2P (Bit 2)                                         */
25620  #define R_SPI0_SSLP_SSL2P_Msk      (0x4UL)  /*!< SSL2P (Bitfield-Mask: 0x01)                           */
25621  #define R_SPI0_SSLP_SSL1P_Pos      (1UL)    /*!< SSL1P (Bit 1)                                         */
25622  #define R_SPI0_SSLP_SSL1P_Msk      (0x2UL)  /*!< SSL1P (Bitfield-Mask: 0x01)                           */
25623  #define R_SPI0_SSLP_SSL0P_Pos      (0UL)    /*!< SSL0P (Bit 0)                                         */
25624  #define R_SPI0_SSLP_SSL0P_Msk      (0x1UL)  /*!< SSL0P (Bitfield-Mask: 0x01)                           */
25625  #define R_SPI0_SSLP_SSL4P_Pos      (4UL)    /*!< SSL4P (Bit 4)                                         */
25626  #define R_SPI0_SSLP_SSL4P_Msk      (0x10UL) /*!< SSL4P (Bitfield-Mask: 0x01)                           */
25627  #define R_SPI0_SSLP_SSL5P_Pos      (5UL)    /*!< SSL5P (Bit 5)                                         */
25628  #define R_SPI0_SSLP_SSL5P_Msk      (0x20UL) /*!< SSL5P (Bitfield-Mask: 0x01)                           */
25629  #define R_SPI0_SSLP_SSL6P_Pos      (6UL)    /*!< SSL6P (Bit 6)                                         */
25630  #define R_SPI0_SSLP_SSL6P_Msk      (0x40UL) /*!< SSL6P (Bitfield-Mask: 0x01)                           */
25631  #define R_SPI0_SSLP_SSL7P_Pos      (7UL)    /*!< SSL7P (Bit 7)                                         */
25632  #define R_SPI0_SSLP_SSL7P_Msk      (0x80UL) /*!< SSL7P (Bitfield-Mask: 0x01)                           */
25633 /* =========================================================  SPPCR  ========================================================= */
25634  #define R_SPI0_SPPCR_MOIFE_Pos     (5UL)    /*!< MOIFE (Bit 5)                                         */
25635  #define R_SPI0_SPPCR_MOIFE_Msk     (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01)                           */
25636  #define R_SPI0_SPPCR_MOIFV_Pos     (4UL)    /*!< MOIFV (Bit 4)                                         */
25637  #define R_SPI0_SPPCR_MOIFV_Msk     (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01)                           */
25638  #define R_SPI0_SPPCR_SPLP2_Pos     (1UL)    /*!< SPLP2 (Bit 1)                                         */
25639  #define R_SPI0_SPPCR_SPLP2_Msk     (0x2UL)  /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
25640  #define R_SPI0_SPPCR_SPLP_Pos      (0UL)    /*!< SPLP (Bit 0)                                          */
25641  #define R_SPI0_SPPCR_SPLP_Msk      (0x1UL)  /*!< SPLP (Bitfield-Mask: 0x01)                            */
25642 /* =========================================================  SPSR  ========================================================== */
25643  #define R_SPI0_SPSR_SPRF_Pos       (7UL)    /*!< SPRF (Bit 7)                                          */
25644  #define R_SPI0_SPSR_SPRF_Msk       (0x80UL) /*!< SPRF (Bitfield-Mask: 0x01)                            */
25645  #define R_SPI0_SPSR_SPTEF_Pos      (5UL)    /*!< SPTEF (Bit 5)                                         */
25646  #define R_SPI0_SPSR_SPTEF_Msk      (0x20UL) /*!< SPTEF (Bitfield-Mask: 0x01)                           */
25647  #define R_SPI0_SPSR_UDRF_Pos       (4UL)    /*!< UDRF (Bit 4)                                          */
25648  #define R_SPI0_SPSR_UDRF_Msk       (0x10UL) /*!< UDRF (Bitfield-Mask: 0x01)                            */
25649  #define R_SPI0_SPSR_PERF_Pos       (3UL)    /*!< PERF (Bit 3)                                          */
25650  #define R_SPI0_SPSR_PERF_Msk       (0x8UL)  /*!< PERF (Bitfield-Mask: 0x01)                            */
25651  #define R_SPI0_SPSR_MODF_Pos       (2UL)    /*!< MODF (Bit 2)                                          */
25652  #define R_SPI0_SPSR_MODF_Msk       (0x4UL)  /*!< MODF (Bitfield-Mask: 0x01)                            */
25653  #define R_SPI0_SPSR_IDLNF_Pos      (1UL)    /*!< IDLNF (Bit 1)                                         */
25654  #define R_SPI0_SPSR_IDLNF_Msk      (0x2UL)  /*!< IDLNF (Bitfield-Mask: 0x01)                           */
25655  #define R_SPI0_SPSR_OVRF_Pos       (0UL)    /*!< OVRF (Bit 0)                                          */
25656  #define R_SPI0_SPSR_OVRF_Msk       (0x1UL)  /*!< OVRF (Bitfield-Mask: 0x01)                            */
25657  #define R_SPI0_SPSR_CENDF_Pos      (6UL)    /*!< CENDF (Bit 6)                                         */
25658  #define R_SPI0_SPSR_CENDF_Msk      (0x40UL) /*!< CENDF (Bitfield-Mask: 0x01)                           */
25659 /* =========================================================  SPDR  ========================================================== */
25660 /* ========================================================  SPDR_HA  ======================================================== */
25661 /* ========================================================  SPDR_BY  ======================================================== */
25662 /* =========================================================  SPSCR  ========================================================= */
25663  #define R_SPI0_SPSCR_SPSLN_Pos     (0UL)      /*!< SPSLN (Bit 0)                                         */
25664  #define R_SPI0_SPSCR_SPSLN_Msk     (0x7UL)    /*!< SPSLN (Bitfield-Mask: 0x07)                           */
25665 /* =========================================================  SPBR  ========================================================== */
25666  #define R_SPI0_SPBR_SPR_Pos        (0UL)      /*!< SPR (Bit 0)                                           */
25667  #define R_SPI0_SPBR_SPR_Msk        (0xffUL)   /*!< SPR (Bitfield-Mask: 0xff)                             */
25668 /* =========================================================  SPDCR  ========================================================= */
25669  #define R_SPI0_SPDCR_SPBYT_Pos     (6UL)      /*!< SPBYT (Bit 6)                                         */
25670  #define R_SPI0_SPDCR_SPBYT_Msk     (0x40UL)   /*!< SPBYT (Bitfield-Mask: 0x01)                           */
25671  #define R_SPI0_SPDCR_SPLW_Pos      (5UL)      /*!< SPLW (Bit 5)                                          */
25672  #define R_SPI0_SPDCR_SPLW_Msk      (0x20UL)   /*!< SPLW (Bitfield-Mask: 0x01)                            */
25673  #define R_SPI0_SPDCR_SPRDTD_Pos    (4UL)      /*!< SPRDTD (Bit 4)                                        */
25674  #define R_SPI0_SPDCR_SPRDTD_Msk    (0x10UL)   /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
25675  #define R_SPI0_SPDCR_SPFC_Pos      (0UL)      /*!< SPFC (Bit 0)                                          */
25676  #define R_SPI0_SPDCR_SPFC_Msk      (0x3UL)    /*!< SPFC (Bitfield-Mask: 0x03)                            */
25677  #define R_SPI0_SPDCR_SLSEL_Pos     (2UL)      /*!< SLSEL (Bit 2)                                         */
25678  #define R_SPI0_SPDCR_SLSEL_Msk     (0xcUL)    /*!< SLSEL (Bitfield-Mask: 0x03)                           */
25679 /* =========================================================  SPCKD  ========================================================= */
25680  #define R_SPI0_SPCKD_SCKDL_Pos     (0UL)      /*!< SCKDL (Bit 0)                                         */
25681  #define R_SPI0_SPCKD_SCKDL_Msk     (0x7UL)    /*!< SCKDL (Bitfield-Mask: 0x07)                           */
25682 /* =========================================================  SSLND  ========================================================= */
25683  #define R_SPI0_SSLND_SLNDL_Pos     (0UL)      /*!< SLNDL (Bit 0)                                         */
25684  #define R_SPI0_SSLND_SLNDL_Msk     (0x7UL)    /*!< SLNDL (Bitfield-Mask: 0x07)                           */
25685 /* =========================================================  SPND  ========================================================== */
25686  #define R_SPI0_SPND_SPNDL_Pos      (0UL)      /*!< SPNDL (Bit 0)                                         */
25687  #define R_SPI0_SPND_SPNDL_Msk      (0x7UL)    /*!< SPNDL (Bitfield-Mask: 0x07)                           */
25688 /* =========================================================  SPCR2  ========================================================= */
25689  #define R_SPI0_SPCR2_SCKASE_Pos    (4UL)      /*!< SCKASE (Bit 4)                                        */
25690  #define R_SPI0_SPCR2_SCKASE_Msk    (0x10UL)   /*!< SCKASE (Bitfield-Mask: 0x01)                          */
25691  #define R_SPI0_SPCR2_PTE_Pos       (3UL)      /*!< PTE (Bit 3)                                           */
25692  #define R_SPI0_SPCR2_PTE_Msk       (0x8UL)    /*!< PTE (Bitfield-Mask: 0x01)                             */
25693  #define R_SPI0_SPCR2_SPIIE_Pos     (2UL)      /*!< SPIIE (Bit 2)                                         */
25694  #define R_SPI0_SPCR2_SPIIE_Msk     (0x4UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
25695  #define R_SPI0_SPCR2_SPOE_Pos      (1UL)      /*!< SPOE (Bit 1)                                          */
25696  #define R_SPI0_SPCR2_SPOE_Msk      (0x2UL)    /*!< SPOE (Bitfield-Mask: 0x01)                            */
25697  #define R_SPI0_SPCR2_SPPE_Pos      (0UL)      /*!< SPPE (Bit 0)                                          */
25698  #define R_SPI0_SPCR2_SPPE_Msk      (0x1UL)    /*!< SPPE (Bitfield-Mask: 0x01)                            */
25699  #define R_SPI0_SPCR2_SPTDDL_Pos    (5UL)      /*!< SPTDDL (Bit 5)                                        */
25700  #define R_SPI0_SPCR2_SPTDDL_Msk    (0xe0UL)   /*!< SPTDDL (Bitfield-Mask: 0x07)                          */
25701 /* =========================================================  SPCMD  ========================================================= */
25702  #define R_SPI0_SPCMD_SCKDEN_Pos    (15UL)     /*!< SCKDEN (Bit 15)                                       */
25703  #define R_SPI0_SPCMD_SCKDEN_Msk    (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
25704  #define R_SPI0_SPCMD_SLNDEN_Pos    (14UL)     /*!< SLNDEN (Bit 14)                                       */
25705  #define R_SPI0_SPCMD_SLNDEN_Msk    (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
25706  #define R_SPI0_SPCMD_SPNDEN_Pos    (13UL)     /*!< SPNDEN (Bit 13)                                       */
25707  #define R_SPI0_SPCMD_SPNDEN_Msk    (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
25708  #define R_SPI0_SPCMD_LSBF_Pos      (12UL)     /*!< LSBF (Bit 12)                                         */
25709  #define R_SPI0_SPCMD_LSBF_Msk      (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01)                            */
25710  #define R_SPI0_SPCMD_SPB_Pos       (8UL)      /*!< SPB (Bit 8)                                           */
25711  #define R_SPI0_SPCMD_SPB_Msk       (0xf00UL)  /*!< SPB (Bitfield-Mask: 0x0f)                             */
25712  #define R_SPI0_SPCMD_SSLKP_Pos     (7UL)      /*!< SSLKP (Bit 7)                                         */
25713  #define R_SPI0_SPCMD_SSLKP_Msk     (0x80UL)   /*!< SSLKP (Bitfield-Mask: 0x01)                           */
25714  #define R_SPI0_SPCMD_SSLA_Pos      (4UL)      /*!< SSLA (Bit 4)                                          */
25715  #define R_SPI0_SPCMD_SSLA_Msk      (0x70UL)   /*!< SSLA (Bitfield-Mask: 0x07)                            */
25716  #define R_SPI0_SPCMD_BRDV_Pos      (2UL)      /*!< BRDV (Bit 2)                                          */
25717  #define R_SPI0_SPCMD_BRDV_Msk      (0xcUL)    /*!< BRDV (Bitfield-Mask: 0x03)                            */
25718  #define R_SPI0_SPCMD_CPOL_Pos      (1UL)      /*!< CPOL (Bit 1)                                          */
25719  #define R_SPI0_SPCMD_CPOL_Msk      (0x2UL)    /*!< CPOL (Bitfield-Mask: 0x01)                            */
25720  #define R_SPI0_SPCMD_CPHA_Pos      (0UL)      /*!< CPHA (Bit 0)                                          */
25721  #define R_SPI0_SPCMD_CPHA_Msk      (0x1UL)    /*!< CPHA (Bitfield-Mask: 0x01)                            */
25722 /* ========================================================  SPDCR2  ========================================================= */
25723  #define R_SPI0_SPDCR2_BYSW_Pos     (0UL)      /*!< BYSW (Bit 0)                                          */
25724  #define R_SPI0_SPDCR2_BYSW_Msk     (0x1UL)    /*!< BYSW (Bitfield-Mask: 0x01)                            */
25725  #define R_SPI0_SPDCR2_SINV_Pos     (1UL)      /*!< SINV (Bit 1)                                          */
25726  #define R_SPI0_SPDCR2_SINV_Msk     (0x2UL)    /*!< SINV (Bitfield-Mask: 0x01)                            */
25727 /* =========================================================  SPSSR  ========================================================= */
25728  #define R_SPI0_SPSSR_SPCP_Pos      (0UL)      /*!< SPCP (Bit 0)                                          */
25729  #define R_SPI0_SPSSR_SPCP_Msk      (0x7UL)    /*!< SPCP (Bitfield-Mask: 0x07)                            */
25730  #define R_SPI0_SPSSR_SPECM_Pos     (4UL)      /*!< SPECM (Bit 4)                                         */
25731  #define R_SPI0_SPSSR_SPECM_Msk     (0x70UL)   /*!< SPECM (Bitfield-Mask: 0x07)                           */
25732 /* =========================================================  SPCR3  ========================================================= */
25733  #define R_SPI0_SPCR3_ETXMD_Pos     (0UL)      /*!< ETXMD (Bit 0)                                         */
25734  #define R_SPI0_SPCR3_ETXMD_Msk     (0x1UL)    /*!< ETXMD (Bitfield-Mask: 0x01)                           */
25735  #define R_SPI0_SPCR3_BFDS_Pos      (1UL)      /*!< BFDS (Bit 1)                                          */
25736  #define R_SPI0_SPCR3_BFDS_Msk      (0x2UL)    /*!< BFDS (Bitfield-Mask: 0x01)                            */
25737  #define R_SPI0_SPCR3_CENDIE_Pos    (4UL)      /*!< CENDIE (Bit 4)                                        */
25738  #define R_SPI0_SPCR3_CENDIE_Msk    (0x10UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
25739 /* =========================================================  SPPR  ========================================================== */
25740  #define R_SPI0_SPPR_BUFWID_Pos     (4UL)      /*!< BUFWID (Bit 4)                                        */
25741  #define R_SPI0_SPPR_BUFWID_Msk     (0x10UL)   /*!< BUFWID (Bitfield-Mask: 0x01)                          */
25742  #define R_SPI0_SPPR_BUFNUM_Pos     (8UL)      /*!< BUFNUM (Bit 8)                                        */
25743  #define R_SPI0_SPPR_BUFNUM_Msk     (0x700UL)  /*!< BUFNUM (Bitfield-Mask: 0x07)                          */
25744  #define R_SPI0_SPPR_CMDNUM_Pos     (12UL)     /*!< CMDNUM (Bit 12)                                       */
25745  #define R_SPI0_SPPR_CMDNUM_Msk     (0xf000UL) /*!< CMDNUM (Bitfield-Mask: 0x0f)                          */
25746 
25747 /* =========================================================================================================================== */
25748 /* ================                                          R_SRAM                                           ================ */
25749 /* =========================================================================================================================== */
25750 
25751 /* ========================================================  PARIOAD  ======================================================== */
25752  #define R_SRAM_PARIOAD_OAD_Pos            (0UL)    /*!< OAD (Bit 0)                                           */
25753  #define R_SRAM_PARIOAD_OAD_Msk            (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
25754 /* =======================================================  SRAMPRCR  ======================================================== */
25755  #define R_SRAM_SRAMPRCR_KW_Pos            (1UL)    /*!< KW (Bit 1)                                            */
25756  #define R_SRAM_SRAMPRCR_KW_Msk            (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
25757  #define R_SRAM_SRAMPRCR_SRAMPRCR_Pos      (0UL)    /*!< SRAMPRCR (Bit 0)                                      */
25758  #define R_SRAM_SRAMPRCR_SRAMPRCR_Msk      (0x1UL)  /*!< SRAMPRCR (Bitfield-Mask: 0x01)                        */
25759 /* =======================================================  SRAMWTSC  ======================================================== */
25760 /* ========================================================  ECCMODE  ======================================================== */
25761  #define R_SRAM_ECCMODE_ECCMOD_Pos         (0UL)    /*!< ECCMOD (Bit 0)                                        */
25762  #define R_SRAM_ECCMODE_ECCMOD_Msk         (0x3UL)  /*!< ECCMOD (Bitfield-Mask: 0x03)                          */
25763 /* ========================================================  ECC2STS  ======================================================== */
25764  #define R_SRAM_ECC2STS_ECC2ERR_Pos        (0UL)    /*!< ECC2ERR (Bit 0)                                       */
25765  #define R_SRAM_ECC2STS_ECC2ERR_Msk        (0x1UL)  /*!< ECC2ERR (Bitfield-Mask: 0x01)                         */
25766 /* =======================================================  ECC1STSEN  ======================================================= */
25767  #define R_SRAM_ECC1STSEN_E1STSEN_Pos      (0UL)    /*!< E1STSEN (Bit 0)                                       */
25768  #define R_SRAM_ECC1STSEN_E1STSEN_Msk      (0x1UL)  /*!< E1STSEN (Bitfield-Mask: 0x01)                         */
25769 /* ========================================================  ECC1STS  ======================================================== */
25770  #define R_SRAM_ECC1STS_ECC1ERR_Pos        (0UL)    /*!< ECC1ERR (Bit 0)                                       */
25771  #define R_SRAM_ECC1STS_ECC1ERR_Msk        (0x1UL)  /*!< ECC1ERR (Bitfield-Mask: 0x01)                         */
25772 /* ========================================================  ECCPRCR  ======================================================== */
25773  #define R_SRAM_ECCPRCR_KW_Pos             (1UL)    /*!< KW (Bit 1)                                            */
25774  #define R_SRAM_ECCPRCR_KW_Msk             (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
25775  #define R_SRAM_ECCPRCR_ECCPRCR_Pos        (0UL)    /*!< ECCPRCR (Bit 0)                                       */
25776  #define R_SRAM_ECCPRCR_ECCPRCR_Msk        (0x1UL)  /*!< ECCPRCR (Bitfield-Mask: 0x01)                         */
25777 /* =======================================================  ECCPRCR2  ======================================================== */
25778  #define R_SRAM_ECCPRCR2_KW2_Pos           (1UL)    /*!< KW2 (Bit 1)                                           */
25779  #define R_SRAM_ECCPRCR2_KW2_Msk           (0xfeUL) /*!< KW2 (Bitfield-Mask: 0x7f)                             */
25780  #define R_SRAM_ECCPRCR2_ECCPRCR2_Pos      (0UL)    /*!< ECCPRCR2 (Bit 0)                                      */
25781  #define R_SRAM_ECCPRCR2_ECCPRCR2_Msk      (0x1UL)  /*!< ECCPRCR2 (Bitfield-Mask: 0x01)                        */
25782 /* ========================================================  ECCETST  ======================================================== */
25783  #define R_SRAM_ECCETST_TSTBYP_Pos         (0UL)    /*!< TSTBYP (Bit 0)                                        */
25784  #define R_SRAM_ECCETST_TSTBYP_Msk         (0x1UL)  /*!< TSTBYP (Bitfield-Mask: 0x01)                          */
25785 /* ========================================================  ECCOAD  ========================================================= */
25786  #define R_SRAM_ECCOAD_OAD_Pos             (0UL)    /*!< OAD (Bit 0)                                           */
25787  #define R_SRAM_ECCOAD_OAD_Msk             (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
25788 /* =======================================================  SRAMPRCR2  ======================================================= */
25789  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Pos    (0UL)    /*!< SRAMPRCR2 (Bit 0)                                     */
25790  #define R_SRAM_SRAMPRCR2_SRAMPRCR2_Msk    (0x1UL)  /*!< SRAMPRCR2 (Bitfield-Mask: 0x01)                       */
25791  #define R_SRAM_SRAMPRCR2_KW_Pos           (1UL)    /*!< KW (Bit 1)                                            */
25792  #define R_SRAM_SRAMPRCR2_KW_Msk           (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
25793 
25794 /* =========================================================================================================================== */
25795 /* ================                                          R_SSI0                                           ================ */
25796 /* =========================================================================================================================== */
25797 
25798 /* =========================================================  SSICR  ========================================================= */
25799  #define R_SSI0_SSICR_CKS_Pos          (30UL)         /*!< CKS (Bit 30)                                          */
25800  #define R_SSI0_SSICR_CKS_Msk          (0x40000000UL) /*!< CKS (Bitfield-Mask: 0x01)                             */
25801  #define R_SSI0_SSICR_TUIEN_Pos        (29UL)         /*!< TUIEN (Bit 29)                                        */
25802  #define R_SSI0_SSICR_TUIEN_Msk        (0x20000000UL) /*!< TUIEN (Bitfield-Mask: 0x01)                           */
25803  #define R_SSI0_SSICR_TOIEN_Pos        (28UL)         /*!< TOIEN (Bit 28)                                        */
25804  #define R_SSI0_SSICR_TOIEN_Msk        (0x10000000UL) /*!< TOIEN (Bitfield-Mask: 0x01)                           */
25805  #define R_SSI0_SSICR_RUIEN_Pos        (27UL)         /*!< RUIEN (Bit 27)                                        */
25806  #define R_SSI0_SSICR_RUIEN_Msk        (0x8000000UL)  /*!< RUIEN (Bitfield-Mask: 0x01)                           */
25807  #define R_SSI0_SSICR_ROIEN_Pos        (26UL)         /*!< ROIEN (Bit 26)                                        */
25808  #define R_SSI0_SSICR_ROIEN_Msk        (0x4000000UL)  /*!< ROIEN (Bitfield-Mask: 0x01)                           */
25809  #define R_SSI0_SSICR_IIEN_Pos         (25UL)         /*!< IIEN (Bit 25)                                         */
25810  #define R_SSI0_SSICR_IIEN_Msk         (0x2000000UL)  /*!< IIEN (Bitfield-Mask: 0x01)                            */
25811  #define R_SSI0_SSICR_FRM_Pos          (22UL)         /*!< FRM (Bit 22)                                          */
25812  #define R_SSI0_SSICR_FRM_Msk          (0xc00000UL)   /*!< FRM (Bitfield-Mask: 0x03)                             */
25813  #define R_SSI0_SSICR_DWL_Pos          (19UL)         /*!< DWL (Bit 19)                                          */
25814  #define R_SSI0_SSICR_DWL_Msk          (0x380000UL)   /*!< DWL (Bitfield-Mask: 0x07)                             */
25815  #define R_SSI0_SSICR_SWL_Pos          (16UL)         /*!< SWL (Bit 16)                                          */
25816  #define R_SSI0_SSICR_SWL_Msk          (0x70000UL)    /*!< SWL (Bitfield-Mask: 0x07)                             */
25817  #define R_SSI0_SSICR_MST_Pos          (14UL)         /*!< MST (Bit 14)                                          */
25818  #define R_SSI0_SSICR_MST_Msk          (0x4000UL)     /*!< MST (Bitfield-Mask: 0x01)                             */
25819  #define R_SSI0_SSICR_BCKP_Pos         (13UL)         /*!< BCKP (Bit 13)                                         */
25820  #define R_SSI0_SSICR_BCKP_Msk         (0x2000UL)     /*!< BCKP (Bitfield-Mask: 0x01)                            */
25821  #define R_SSI0_SSICR_LRCKP_Pos        (12UL)         /*!< LRCKP (Bit 12)                                        */
25822  #define R_SSI0_SSICR_LRCKP_Msk        (0x1000UL)     /*!< LRCKP (Bitfield-Mask: 0x01)                           */
25823  #define R_SSI0_SSICR_SPDP_Pos         (11UL)         /*!< SPDP (Bit 11)                                         */
25824  #define R_SSI0_SSICR_SPDP_Msk         (0x800UL)      /*!< SPDP (Bitfield-Mask: 0x01)                            */
25825  #define R_SSI0_SSICR_SDTA_Pos         (10UL)         /*!< SDTA (Bit 10)                                         */
25826  #define R_SSI0_SSICR_SDTA_Msk         (0x400UL)      /*!< SDTA (Bitfield-Mask: 0x01)                            */
25827  #define R_SSI0_SSICR_PDTA_Pos         (9UL)          /*!< PDTA (Bit 9)                                          */
25828  #define R_SSI0_SSICR_PDTA_Msk         (0x200UL)      /*!< PDTA (Bitfield-Mask: 0x01)                            */
25829  #define R_SSI0_SSICR_DEL_Pos          (8UL)          /*!< DEL (Bit 8)                                           */
25830  #define R_SSI0_SSICR_DEL_Msk          (0x100UL)      /*!< DEL (Bitfield-Mask: 0x01)                             */
25831  #define R_SSI0_SSICR_CKDV_Pos         (4UL)          /*!< CKDV (Bit 4)                                          */
25832  #define R_SSI0_SSICR_CKDV_Msk         (0xf0UL)       /*!< CKDV (Bitfield-Mask: 0x0f)                            */
25833  #define R_SSI0_SSICR_MUEN_Pos         (3UL)          /*!< MUEN (Bit 3)                                          */
25834  #define R_SSI0_SSICR_MUEN_Msk         (0x8UL)        /*!< MUEN (Bitfield-Mask: 0x01)                            */
25835  #define R_SSI0_SSICR_TEN_Pos          (1UL)          /*!< TEN (Bit 1)                                           */
25836  #define R_SSI0_SSICR_TEN_Msk          (0x2UL)        /*!< TEN (Bitfield-Mask: 0x01)                             */
25837  #define R_SSI0_SSICR_REN_Pos          (0UL)          /*!< REN (Bit 0)                                           */
25838  #define R_SSI0_SSICR_REN_Msk          (0x1UL)        /*!< REN (Bitfield-Mask: 0x01)                             */
25839 /* =========================================================  SSISR  ========================================================= */
25840  #define R_SSI0_SSISR_TUIRQ_Pos        (29UL)         /*!< TUIRQ (Bit 29)                                        */
25841  #define R_SSI0_SSISR_TUIRQ_Msk        (0x20000000UL) /*!< TUIRQ (Bitfield-Mask: 0x01)                           */
25842  #define R_SSI0_SSISR_TOIRQ_Pos        (28UL)         /*!< TOIRQ (Bit 28)                                        */
25843  #define R_SSI0_SSISR_TOIRQ_Msk        (0x10000000UL) /*!< TOIRQ (Bitfield-Mask: 0x01)                           */
25844  #define R_SSI0_SSISR_RUIRQ_Pos        (27UL)         /*!< RUIRQ (Bit 27)                                        */
25845  #define R_SSI0_SSISR_RUIRQ_Msk        (0x8000000UL)  /*!< RUIRQ (Bitfield-Mask: 0x01)                           */
25846  #define R_SSI0_SSISR_ROIRQ_Pos        (26UL)         /*!< ROIRQ (Bit 26)                                        */
25847  #define R_SSI0_SSISR_ROIRQ_Msk        (0x4000000UL)  /*!< ROIRQ (Bitfield-Mask: 0x01)                           */
25848  #define R_SSI0_SSISR_IIRQ_Pos         (25UL)         /*!< IIRQ (Bit 25)                                         */
25849  #define R_SSI0_SSISR_IIRQ_Msk         (0x2000000UL)  /*!< IIRQ (Bitfield-Mask: 0x01)                            */
25850  #define R_SSI0_SSISR_TCHNO_Pos        (5UL)          /*!< TCHNO (Bit 5)                                         */
25851  #define R_SSI0_SSISR_TCHNO_Msk        (0x60UL)       /*!< TCHNO (Bitfield-Mask: 0x03)                           */
25852  #define R_SSI0_SSISR_TSWNO_Pos        (4UL)          /*!< TSWNO (Bit 4)                                         */
25853  #define R_SSI0_SSISR_TSWNO_Msk        (0x10UL)       /*!< TSWNO (Bitfield-Mask: 0x01)                           */
25854  #define R_SSI0_SSISR_RCHNO_Pos        (2UL)          /*!< RCHNO (Bit 2)                                         */
25855  #define R_SSI0_SSISR_RCHNO_Msk        (0xcUL)        /*!< RCHNO (Bitfield-Mask: 0x03)                           */
25856  #define R_SSI0_SSISR_RSWNO_Pos        (1UL)          /*!< RSWNO (Bit 1)                                         */
25857  #define R_SSI0_SSISR_RSWNO_Msk        (0x2UL)        /*!< RSWNO (Bitfield-Mask: 0x01)                           */
25858  #define R_SSI0_SSISR_IDST_Pos         (0UL)          /*!< IDST (Bit 0)                                          */
25859  #define R_SSI0_SSISR_IDST_Msk         (0x1UL)        /*!< IDST (Bitfield-Mask: 0x01)                            */
25860 /* ========================================================  SSIFCR  ========================================================= */
25861  #define R_SSI0_SSIFCR_AUCKE_Pos       (31UL)         /*!< AUCKE (Bit 31)                                        */
25862  #define R_SSI0_SSIFCR_AUCKE_Msk       (0x80000000UL) /*!< AUCKE (Bitfield-Mask: 0x01)                           */
25863  #define R_SSI0_SSIFCR_SSIRST_Pos      (16UL)         /*!< SSIRST (Bit 16)                                       */
25864  #define R_SSI0_SSIFCR_SSIRST_Msk      (0x10000UL)    /*!< SSIRST (Bitfield-Mask: 0x01)                          */
25865  #define R_SSI0_SSIFCR_TTRG_Pos        (6UL)          /*!< TTRG (Bit 6)                                          */
25866  #define R_SSI0_SSIFCR_TTRG_Msk        (0xc0UL)       /*!< TTRG (Bitfield-Mask: 0x03)                            */
25867  #define R_SSI0_SSIFCR_RTRG_Pos        (4UL)          /*!< RTRG (Bit 4)                                          */
25868  #define R_SSI0_SSIFCR_RTRG_Msk        (0x30UL)       /*!< RTRG (Bitfield-Mask: 0x03)                            */
25869  #define R_SSI0_SSIFCR_TIE_Pos         (3UL)          /*!< TIE (Bit 3)                                           */
25870  #define R_SSI0_SSIFCR_TIE_Msk         (0x8UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
25871  #define R_SSI0_SSIFCR_RIE_Pos         (2UL)          /*!< RIE (Bit 2)                                           */
25872  #define R_SSI0_SSIFCR_RIE_Msk         (0x4UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
25873  #define R_SSI0_SSIFCR_TFRST_Pos       (1UL)          /*!< TFRST (Bit 1)                                         */
25874  #define R_SSI0_SSIFCR_TFRST_Msk       (0x2UL)        /*!< TFRST (Bitfield-Mask: 0x01)                           */
25875  #define R_SSI0_SSIFCR_RFRST_Pos       (0UL)          /*!< RFRST (Bit 0)                                         */
25876  #define R_SSI0_SSIFCR_RFRST_Msk       (0x1UL)        /*!< RFRST (Bitfield-Mask: 0x01)                           */
25877  #define R_SSI0_SSIFCR_BSW_Pos         (11UL)         /*!< BSW (Bit 11)                                          */
25878  #define R_SSI0_SSIFCR_BSW_Msk         (0x800UL)      /*!< BSW (Bitfield-Mask: 0x01)                             */
25879 /* ========================================================  SSIFSR  ========================================================= */
25880  #define R_SSI0_SSIFSR_TDC_Pos         (24UL)         /*!< TDC (Bit 24)                                          */
25881  #define R_SSI0_SSIFSR_TDC_Msk         (0x3f000000UL) /*!< TDC (Bitfield-Mask: 0x3f)                             */
25882  #define R_SSI0_SSIFSR_TDE_Pos         (16UL)         /*!< TDE (Bit 16)                                          */
25883  #define R_SSI0_SSIFSR_TDE_Msk         (0x10000UL)    /*!< TDE (Bitfield-Mask: 0x01)                             */
25884  #define R_SSI0_SSIFSR_RDC_Pos         (8UL)          /*!< RDC (Bit 8)                                           */
25885  #define R_SSI0_SSIFSR_RDC_Msk         (0x3f00UL)     /*!< RDC (Bitfield-Mask: 0x3f)                             */
25886  #define R_SSI0_SSIFSR_RDF_Pos         (0UL)          /*!< RDF (Bit 0)                                           */
25887  #define R_SSI0_SSIFSR_RDF_Msk         (0x1UL)        /*!< RDF (Bitfield-Mask: 0x01)                             */
25888 /* ========================================================  SSIFTDR  ======================================================== */
25889  #define R_SSI0_SSIFTDR_SSIFTDR_Pos    (0UL)          /*!< SSIFTDR (Bit 0)                                       */
25890  #define R_SSI0_SSIFTDR_SSIFTDR_Msk    (0xffffffffUL) /*!< SSIFTDR (Bitfield-Mask: 0xffffffff)                   */
25891 /* =======================================================  SSIFTDR16  ======================================================= */
25892 /* =======================================================  SSIFTDR8  ======================================================== */
25893 /* ========================================================  SSIFRDR  ======================================================== */
25894  #define R_SSI0_SSIFRDR_SSIFRDR_Pos    (0UL)          /*!< SSIFRDR (Bit 0)                                       */
25895  #define R_SSI0_SSIFRDR_SSIFRDR_Msk    (0xffffffffUL) /*!< SSIFRDR (Bitfield-Mask: 0xffffffff)                   */
25896 /* =======================================================  SSIFRDR16  ======================================================= */
25897 /* =======================================================  SSIFRDR8  ======================================================== */
25898 /* ========================================================  SSIOFR  ========================================================= */
25899  #define R_SSI0_SSIOFR_BCKASTP_Pos     (9UL)          /*!< BCKASTP (Bit 9)                                       */
25900  #define R_SSI0_SSIOFR_BCKASTP_Msk     (0x200UL)      /*!< BCKASTP (Bitfield-Mask: 0x01)                         */
25901  #define R_SSI0_SSIOFR_LRCONT_Pos      (8UL)          /*!< LRCONT (Bit 8)                                        */
25902  #define R_SSI0_SSIOFR_LRCONT_Msk      (0x100UL)      /*!< LRCONT (Bitfield-Mask: 0x01)                          */
25903  #define R_SSI0_SSIOFR_OMOD_Pos        (0UL)          /*!< OMOD (Bit 0)                                          */
25904  #define R_SSI0_SSIOFR_OMOD_Msk        (0x3UL)        /*!< OMOD (Bitfield-Mask: 0x03)                            */
25905 /* ========================================================  SSISCR  ========================================================= */
25906  #define R_SSI0_SSISCR_TDES_Pos        (8UL)          /*!< TDES (Bit 8)                                          */
25907  #define R_SSI0_SSISCR_TDES_Msk        (0x1f00UL)     /*!< TDES (Bitfield-Mask: 0x1f)                            */
25908  #define R_SSI0_SSISCR_RDFS_Pos        (0UL)          /*!< RDFS (Bit 0)                                          */
25909  #define R_SSI0_SSISCR_RDFS_Msk        (0x1fUL)       /*!< RDFS (Bitfield-Mask: 0x1f)                            */
25910 
25911 /* =========================================================================================================================== */
25912 /* ================                                         R_SYSTEM                                          ================ */
25913 /* =========================================================================================================================== */
25914 
25915 /* =========================================================  SBYCR  ========================================================= */
25916  #define R_SYSTEM_SBYCR_SSBY_Pos                   (15UL)         /*!< SSBY (Bit 15)                                         */
25917  #define R_SYSTEM_SBYCR_SSBY_Msk                   (0x8000UL)     /*!< SSBY (Bitfield-Mask: 0x01)                            */
25918  #define R_SYSTEM_SBYCR_OPE_Pos                    (14UL)         /*!< OPE (Bit 14)                                          */
25919  #define R_SYSTEM_SBYCR_OPE_Msk                    (0x4000UL)     /*!< OPE (Bitfield-Mask: 0x01)                             */
25920 /* ========================================================  MSTPCRA  ======================================================== */
25921  #define R_SYSTEM_MSTPCRA_MSTPA_Pos                (0UL)          /*!< MSTPA (Bit 0)                                         */
25922  #define R_SYSTEM_MSTPCRA_MSTPA_Msk                (0x1UL)        /*!< MSTPA (Bitfield-Mask: 0x01)                           */
25923 /* =======================================================  SCKDIVCR  ======================================================== */
25924  #define R_SYSTEM_SCKDIVCR_FCK_Pos                 (28UL)         /*!< FCK (Bit 28)                                          */
25925  #define R_SYSTEM_SCKDIVCR_FCK_Msk                 (0x70000000UL) /*!< FCK (Bitfield-Mask: 0x07)                             */
25926  #define R_SYSTEM_SCKDIVCR_ICK_Pos                 (24UL)         /*!< ICK (Bit 24)                                          */
25927  #define R_SYSTEM_SCKDIVCR_ICK_Msk                 (0x7000000UL)  /*!< ICK (Bitfield-Mask: 0x07)                             */
25928  #define R_SYSTEM_SCKDIVCR_BCK_Pos                 (16UL)         /*!< BCK (Bit 16)                                          */
25929  #define R_SYSTEM_SCKDIVCR_BCK_Msk                 (0x70000UL)    /*!< BCK (Bitfield-Mask: 0x07)                             */
25930  #define R_SYSTEM_SCKDIVCR_PCKA_Pos                (12UL)         /*!< PCKA (Bit 12)                                         */
25931  #define R_SYSTEM_SCKDIVCR_PCKA_Msk                (0x7000UL)     /*!< PCKA (Bitfield-Mask: 0x07)                            */
25932  #define R_SYSTEM_SCKDIVCR_PCKB_Pos                (8UL)          /*!< PCKB (Bit 8)                                          */
25933  #define R_SYSTEM_SCKDIVCR_PCKB_Msk                (0x700UL)      /*!< PCKB (Bitfield-Mask: 0x07)                            */
25934  #define R_SYSTEM_SCKDIVCR_PCKC_Pos                (4UL)          /*!< PCKC (Bit 4)                                          */
25935  #define R_SYSTEM_SCKDIVCR_PCKC_Msk                (0x70UL)       /*!< PCKC (Bitfield-Mask: 0x07)                            */
25936  #define R_SYSTEM_SCKDIVCR_PCKD_Pos                (0UL)          /*!< PCKD (Bit 0)                                          */
25937  #define R_SYSTEM_SCKDIVCR_PCKD_Msk                (0x7UL)        /*!< PCKD (Bitfield-Mask: 0x07)                            */
25938 /* =======================================================  SCKDIVCR2  ======================================================= */
25939  #define R_SYSTEM_SCKDIVCR2_UCK_Pos                (4UL)          /*!< UCK (Bit 4)                                           */
25940  #define R_SYSTEM_SCKDIVCR2_UCK_Msk                (0x70UL)       /*!< UCK (Bitfield-Mask: 0x07)                             */
25941 /* ========================================================  SCKSCR  ========================================================= */
25942  #define R_SYSTEM_SCKSCR_CKSEL_Pos                 (0UL)          /*!< CKSEL (Bit 0)                                         */
25943  #define R_SYSTEM_SCKSCR_CKSEL_Msk                 (0x7UL)        /*!< CKSEL (Bitfield-Mask: 0x07)                           */
25944 /* ========================================================  PLLCCR  ========================================================= */
25945  #define R_SYSTEM_PLLCCR_PLLMUL_Pos                (8UL)          /*!< PLLMUL (Bit 8)                                        */
25946  #define R_SYSTEM_PLLCCR_PLLMUL_Msk                (0x3f00UL)     /*!< PLLMUL (Bitfield-Mask: 0x3f)                          */
25947  #define R_SYSTEM_PLLCCR_PLSRCSEL_Pos              (4UL)          /*!< PLSRCSEL (Bit 4)                                      */
25948  #define R_SYSTEM_PLLCCR_PLSRCSEL_Msk              (0x10UL)       /*!< PLSRCSEL (Bitfield-Mask: 0x01)                        */
25949  #define R_SYSTEM_PLLCCR_PLIDIV_Pos                (0UL)          /*!< PLIDIV (Bit 0)                                        */
25950  #define R_SYSTEM_PLLCCR_PLIDIV_Msk                (0x3UL)        /*!< PLIDIV (Bitfield-Mask: 0x03)                          */
25951 /* =========================================================  PLLCR  ========================================================= */
25952  #define R_SYSTEM_PLLCR_PLLSTP_Pos                 (0UL)          /*!< PLLSTP (Bit 0)                                        */
25953  #define R_SYSTEM_PLLCR_PLLSTP_Msk                 (0x1UL)        /*!< PLLSTP (Bitfield-Mask: 0x01)                          */
25954 /* ========================================================  PLLCCR2  ======================================================== */
25955  #define R_SYSTEM_PLLCCR2_PLODIV_Pos               (6UL)          /*!< PLODIV (Bit 6)                                        */
25956  #define R_SYSTEM_PLLCCR2_PLODIV_Msk               (0xc0UL)       /*!< PLODIV (Bitfield-Mask: 0x03)                          */
25957  #define R_SYSTEM_PLLCCR2_PLLMUL_Pos               (0UL)          /*!< PLLMUL (Bit 0)                                        */
25958  #define R_SYSTEM_PLLCCR2_PLLMUL_Msk               (0x1fUL)       /*!< PLLMUL (Bitfield-Mask: 0x1f)                          */
25959 /* =========================================================  BCKCR  ========================================================= */
25960  #define R_SYSTEM_BCKCR_BCLKDIV_Pos                (0UL)          /*!< BCLKDIV (Bit 0)                                       */
25961  #define R_SYSTEM_BCKCR_BCLKDIV_Msk                (0x1UL)        /*!< BCLKDIV (Bitfield-Mask: 0x01)                         */
25962 /* ========================================================  MEMWAIT  ======================================================== */
25963  #define R_SYSTEM_MEMWAIT_MEMWAIT_Pos              (0UL)          /*!< MEMWAIT (Bit 0)                                       */
25964  #define R_SYSTEM_MEMWAIT_MEMWAIT_Msk              (0x1UL)        /*!< MEMWAIT (Bitfield-Mask: 0x01)                         */
25965 /* ========================================================  MOSCCR  ========================================================= */
25966  #define R_SYSTEM_MOSCCR_MOSTP_Pos                 (0UL)          /*!< MOSTP (Bit 0)                                         */
25967  #define R_SYSTEM_MOSCCR_MOSTP_Msk                 (0x1UL)        /*!< MOSTP (Bitfield-Mask: 0x01)                           */
25968 /* ========================================================  HOCOCR  ========================================================= */
25969  #define R_SYSTEM_HOCOCR_HCSTP_Pos                 (0UL)          /*!< HCSTP (Bit 0)                                         */
25970  #define R_SYSTEM_HOCOCR_HCSTP_Msk                 (0x1UL)        /*!< HCSTP (Bitfield-Mask: 0x01)                           */
25971 /* ========================================================  HOCOCR2  ======================================================== */
25972  #define R_SYSTEM_HOCOCR2_HCFRQ0_Pos               (0UL)          /*!< HCFRQ0 (Bit 0)                                        */
25973  #define R_SYSTEM_HOCOCR2_HCFRQ0_Msk               (0x3UL)        /*!< HCFRQ0 (Bitfield-Mask: 0x03)                          */
25974  #define R_SYSTEM_HOCOCR2_HCFRQ1_Pos               (3UL)          /*!< HCFRQ1 (Bit 3)                                        */
25975  #define R_SYSTEM_HOCOCR2_HCFRQ1_Msk               (0x38UL)       /*!< HCFRQ1 (Bitfield-Mask: 0x07)                          */
25976 /* ========================================================  MOCOCR  ========================================================= */
25977  #define R_SYSTEM_MOCOCR_MCSTP_Pos                 (0UL)          /*!< MCSTP (Bit 0)                                         */
25978  #define R_SYSTEM_MOCOCR_MCSTP_Msk                 (0x1UL)        /*!< MCSTP (Bitfield-Mask: 0x01)                           */
25979 /* ========================================================  FLLCR1  ========================================================= */
25980  #define R_SYSTEM_FLLCR1_FLLEN_Pos                 (0UL)          /*!< FLLEN (Bit 0)                                         */
25981  #define R_SYSTEM_FLLCR1_FLLEN_Msk                 (0x1UL)        /*!< FLLEN (Bitfield-Mask: 0x01)                           */
25982 /* ========================================================  FLLCR2  ========================================================= */
25983  #define R_SYSTEM_FLLCR2_FLLCNTL_Pos               (0UL)          /*!< FLLCNTL (Bit 0)                                       */
25984  #define R_SYSTEM_FLLCR2_FLLCNTL_Msk               (0x7ffUL)      /*!< FLLCNTL (Bitfield-Mask: 0x7ff)                        */
25985 /* =========================================================  OSCSF  ========================================================= */
25986  #define R_SYSTEM_OSCSF_PLLSF_Pos                  (5UL)          /*!< PLLSF (Bit 5)                                         */
25987  #define R_SYSTEM_OSCSF_PLLSF_Msk                  (0x20UL)       /*!< PLLSF (Bitfield-Mask: 0x01)                           */
25988  #define R_SYSTEM_OSCSF_MOSCSF_Pos                 (3UL)          /*!< MOSCSF (Bit 3)                                        */
25989  #define R_SYSTEM_OSCSF_MOSCSF_Msk                 (0x8UL)        /*!< MOSCSF (Bitfield-Mask: 0x01)                          */
25990  #define R_SYSTEM_OSCSF_HOCOSF_Pos                 (0UL)          /*!< HOCOSF (Bit 0)                                        */
25991  #define R_SYSTEM_OSCSF_HOCOSF_Msk                 (0x1UL)        /*!< HOCOSF (Bitfield-Mask: 0x01)                          */
25992  #define R_SYSTEM_OSCSF_PLL2SF_Pos                 (6UL)          /*!< PLL2SF (Bit 6)                                        */
25993  #define R_SYSTEM_OSCSF_PLL2SF_Msk                 (0x40UL)       /*!< PLL2SF (Bitfield-Mask: 0x01)                          */
25994 /* =========================================================  CKOCR  ========================================================= */
25995  #define R_SYSTEM_CKOCR_CKOEN_Pos                  (7UL)          /*!< CKOEN (Bit 7)                                         */
25996  #define R_SYSTEM_CKOCR_CKOEN_Msk                  (0x80UL)       /*!< CKOEN (Bitfield-Mask: 0x01)                           */
25997  #define R_SYSTEM_CKOCR_CKODIV_Pos                 (4UL)          /*!< CKODIV (Bit 4)                                        */
25998  #define R_SYSTEM_CKOCR_CKODIV_Msk                 (0x70UL)       /*!< CKODIV (Bitfield-Mask: 0x07)                          */
25999  #define R_SYSTEM_CKOCR_CKOSEL_Pos                 (0UL)          /*!< CKOSEL (Bit 0)                                        */
26000  #define R_SYSTEM_CKOCR_CKOSEL_Msk                 (0x7UL)        /*!< CKOSEL (Bitfield-Mask: 0x07)                          */
26001 /* ========================================================  TRCKCR  ========================================================= */
26002  #define R_SYSTEM_TRCKCR_TRCKEN_Pos                (7UL)          /*!< TRCKEN (Bit 7)                                        */
26003  #define R_SYSTEM_TRCKCR_TRCKEN_Msk                (0x80UL)       /*!< TRCKEN (Bitfield-Mask: 0x01)                          */
26004  #define R_SYSTEM_TRCKCR_TRCK_Pos                  (0UL)          /*!< TRCK (Bit 0)                                          */
26005  #define R_SYSTEM_TRCKCR_TRCK_Msk                  (0xfUL)        /*!< TRCK (Bitfield-Mask: 0x0f)                            */
26006 /* ========================================================  OSTDCR  ========================================================= */
26007  #define R_SYSTEM_OSTDCR_OSTDE_Pos                 (7UL)          /*!< OSTDE (Bit 7)                                         */
26008  #define R_SYSTEM_OSTDCR_OSTDE_Msk                 (0x80UL)       /*!< OSTDE (Bitfield-Mask: 0x01)                           */
26009  #define R_SYSTEM_OSTDCR_OSTDIE_Pos                (0UL)          /*!< OSTDIE (Bit 0)                                        */
26010  #define R_SYSTEM_OSTDCR_OSTDIE_Msk                (0x1UL)        /*!< OSTDIE (Bitfield-Mask: 0x01)                          */
26011 /* ========================================================  OSTDSR  ========================================================= */
26012  #define R_SYSTEM_OSTDSR_OSTDF_Pos                 (0UL)          /*!< OSTDF (Bit 0)                                         */
26013  #define R_SYSTEM_OSTDSR_OSTDF_Msk                 (0x1UL)        /*!< OSTDF (Bitfield-Mask: 0x01)                           */
26014 /* =========================================================  LPOPT  ========================================================= */
26015  #define R_SYSTEM_LPOPT_LPOPTEN_Pos                (7UL)          /*!< LPOPTEN (Bit 7)                                       */
26016  #define R_SYSTEM_LPOPT_LPOPTEN_Msk                (0x80UL)       /*!< LPOPTEN (Bitfield-Mask: 0x01)                         */
26017  #define R_SYSTEM_LPOPT_BPFCLKDIS_Pos              (3UL)          /*!< BPFCLKDIS (Bit 3)                                     */
26018  #define R_SYSTEM_LPOPT_BPFCLKDIS_Msk              (0x8UL)        /*!< BPFCLKDIS (Bitfield-Mask: 0x01)                       */
26019  #define R_SYSTEM_LPOPT_DCLKDIS_Pos                (1UL)          /*!< DCLKDIS (Bit 1)                                       */
26020  #define R_SYSTEM_LPOPT_DCLKDIS_Msk                (0x6UL)        /*!< DCLKDIS (Bitfield-Mask: 0x03)                         */
26021  #define R_SYSTEM_LPOPT_MPUDIS_Pos                 (0UL)          /*!< MPUDIS (Bit 0)                                        */
26022  #define R_SYSTEM_LPOPT_MPUDIS_Msk                 (0x1UL)        /*!< MPUDIS (Bitfield-Mask: 0x01)                          */
26023 /* =======================================================  SLCDSCKCR  ======================================================= */
26024  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Pos           (7UL)          /*!< LCDSCKEN (Bit 7)                                      */
26025  #define R_SYSTEM_SLCDSCKCR_LCDSCKEN_Msk           (0x80UL)       /*!< LCDSCKEN (Bitfield-Mask: 0x01)                        */
26026  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Pos          (0UL)          /*!< LCDSCKSEL (Bit 0)                                     */
26027  #define R_SYSTEM_SLCDSCKCR_LCDSCKSEL_Msk          (0x7UL)        /*!< LCDSCKSEL (Bitfield-Mask: 0x07)                       */
26028 /* ========================================================  EBCKOCR  ======================================================== */
26029  #define R_SYSTEM_EBCKOCR_EBCKOEN_Pos              (0UL)          /*!< EBCKOEN (Bit 0)                                       */
26030  #define R_SYSTEM_EBCKOCR_EBCKOEN_Msk              (0x1UL)        /*!< EBCKOEN (Bitfield-Mask: 0x01)                         */
26031 /* ========================================================  SDCKOCR  ======================================================== */
26032  #define R_SYSTEM_SDCKOCR_SDCKOEN_Pos              (0UL)          /*!< SDCKOEN (Bit 0)                                       */
26033  #define R_SYSTEM_SDCKOCR_SDCKOEN_Msk              (0x1UL)        /*!< SDCKOEN (Bitfield-Mask: 0x01)                         */
26034 /* =======================================================  MOCOUTCR  ======================================================== */
26035  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Pos            (0UL)          /*!< MOCOUTRM (Bit 0)                                      */
26036  #define R_SYSTEM_MOCOUTCR_MOCOUTRM_Msk            (0xffUL)       /*!< MOCOUTRM (Bitfield-Mask: 0xff)                        */
26037 /* =======================================================  HOCOUTCR  ======================================================== */
26038  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Pos            (0UL)          /*!< HOCOUTRM (Bit 0)                                      */
26039  #define R_SYSTEM_HOCOUTCR_HOCOUTRM_Msk            (0xffUL)       /*!< HOCOUTRM (Bitfield-Mask: 0xff)                        */
26040 /* =========================================================  SNZCR  ========================================================= */
26041  #define R_SYSTEM_SNZCR_SNZE_Pos                   (7UL)          /*!< SNZE (Bit 7)                                          */
26042  #define R_SYSTEM_SNZCR_SNZE_Msk                   (0x80UL)       /*!< SNZE (Bitfield-Mask: 0x01)                            */
26043  #define R_SYSTEM_SNZCR_SNZDTCEN_Pos               (1UL)          /*!< SNZDTCEN (Bit 1)                                      */
26044  #define R_SYSTEM_SNZCR_SNZDTCEN_Msk               (0x2UL)        /*!< SNZDTCEN (Bitfield-Mask: 0x01)                        */
26045  #define R_SYSTEM_SNZCR_RXDREQEN_Pos               (0UL)          /*!< RXDREQEN (Bit 0)                                      */
26046  #define R_SYSTEM_SNZCR_RXDREQEN_Msk               (0x1UL)        /*!< RXDREQEN (Bitfield-Mask: 0x01)                        */
26047 /* ========================================================  SNZEDCR  ======================================================== */
26048  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Pos            (7UL)          /*!< SCI0UMTED (Bit 7)                                     */
26049  #define R_SYSTEM_SNZEDCR_SCI0UMTED_Msk            (0x80UL)       /*!< SCI0UMTED (Bitfield-Mask: 0x01)                       */
26050  #define R_SYSTEM_SNZEDCR_AD1UMTED_Pos             (6UL)          /*!< AD1UMTED (Bit 6)                                      */
26051  #define R_SYSTEM_SNZEDCR_AD1UMTED_Msk             (0x40UL)       /*!< AD1UMTED (Bitfield-Mask: 0x01)                        */
26052  #define R_SYSTEM_SNZEDCR_AD1MATED_Pos             (5UL)          /*!< AD1MATED (Bit 5)                                      */
26053  #define R_SYSTEM_SNZEDCR_AD1MATED_Msk             (0x20UL)       /*!< AD1MATED (Bitfield-Mask: 0x01)                        */
26054  #define R_SYSTEM_SNZEDCR_AD0UMTED_Pos             (4UL)          /*!< AD0UMTED (Bit 4)                                      */
26055  #define R_SYSTEM_SNZEDCR_AD0UMTED_Msk             (0x10UL)       /*!< AD0UMTED (Bitfield-Mask: 0x01)                        */
26056  #define R_SYSTEM_SNZEDCR_AD0MATED_Pos             (3UL)          /*!< AD0MATED (Bit 3)                                      */
26057  #define R_SYSTEM_SNZEDCR_AD0MATED_Msk             (0x8UL)        /*!< AD0MATED (Bitfield-Mask: 0x01)                        */
26058  #define R_SYSTEM_SNZEDCR_DTCNZRED_Pos             (2UL)          /*!< DTCNZRED (Bit 2)                                      */
26059  #define R_SYSTEM_SNZEDCR_DTCNZRED_Msk             (0x4UL)        /*!< DTCNZRED (Bitfield-Mask: 0x01)                        */
26060  #define R_SYSTEM_SNZEDCR_DTCZRED_Pos              (1UL)          /*!< DTCZRED (Bit 1)                                       */
26061  #define R_SYSTEM_SNZEDCR_DTCZRED_Msk              (0x2UL)        /*!< DTCZRED (Bitfield-Mask: 0x01)                         */
26062  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Pos            (0UL)          /*!< AGT1UNFED (Bit 0)                                     */
26063  #define R_SYSTEM_SNZEDCR_AGT1UNFED_Msk            (0x1UL)        /*!< AGT1UNFED (Bitfield-Mask: 0x01)                       */
26064 /* =======================================================  SNZREQCR  ======================================================== */
26065  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Pos          (30UL)         /*!< SNZREQEN30 (Bit 30)                                   */
26066  #define R_SYSTEM_SNZREQCR_SNZREQEN30_Msk          (0x40000000UL) /*!< SNZREQEN30 (Bitfield-Mask: 0x01)                      */
26067  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Pos          (29UL)         /*!< SNZREQEN29 (Bit 29)                                   */
26068  #define R_SYSTEM_SNZREQCR_SNZREQEN29_Msk          (0x20000000UL) /*!< SNZREQEN29 (Bitfield-Mask: 0x01)                      */
26069  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Pos          (28UL)         /*!< SNZREQEN28 (Bit 28)                                   */
26070  #define R_SYSTEM_SNZREQCR_SNZREQEN28_Msk          (0x10000000UL) /*!< SNZREQEN28 (Bitfield-Mask: 0x01)                      */
26071  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Pos          (25UL)         /*!< SNZREQEN25 (Bit 25)                                   */
26072  #define R_SYSTEM_SNZREQCR_SNZREQEN25_Msk          (0x2000000UL)  /*!< SNZREQEN25 (Bitfield-Mask: 0x01)                      */
26073  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Pos          (24UL)         /*!< SNZREQEN24 (Bit 24)                                   */
26074  #define R_SYSTEM_SNZREQCR_SNZREQEN24_Msk          (0x1000000UL)  /*!< SNZREQEN24 (Bitfield-Mask: 0x01)                      */
26075  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Pos          (23UL)         /*!< SNZREQEN23 (Bit 23)                                   */
26076  #define R_SYSTEM_SNZREQCR_SNZREQEN23_Msk          (0x800000UL)   /*!< SNZREQEN23 (Bitfield-Mask: 0x01)                      */
26077  #define R_SYSTEM_SNZREQCR_SNZREQEN22_Pos          (22UL)         /*!< SNZREQEN22 (Bit 22)                                   */
26078  #define R_SYSTEM_SNZREQCR_SNZREQEN22_Msk          (0x400000UL)   /*!< SNZREQEN22 (Bitfield-Mask: 0x01)                      */
26079  #define R_SYSTEM_SNZREQCR_SNZREQEN17_Pos          (17UL)         /*!< SNZREQEN17 (Bit 17)                                   */
26080  #define R_SYSTEM_SNZREQCR_SNZREQEN17_Msk          (0x20000UL)    /*!< SNZREQEN17 (Bitfield-Mask: 0x01)                      */
26081  #define R_SYSTEM_SNZREQCR_SNZREQEN_Pos            (0UL)          /*!< SNZREQEN (Bit 0)                                      */
26082  #define R_SYSTEM_SNZREQCR_SNZREQEN_Msk            (0x1UL)        /*!< SNZREQEN (Bitfield-Mask: 0x01)                        */
26083 /* ========================================================  FLSTOP  ========================================================= */
26084  #define R_SYSTEM_FLSTOP_FLSTPF_Pos                (4UL)          /*!< FLSTPF (Bit 4)                                        */
26085  #define R_SYSTEM_FLSTOP_FLSTPF_Msk                (0x10UL)       /*!< FLSTPF (Bitfield-Mask: 0x01)                          */
26086  #define R_SYSTEM_FLSTOP_FLSTOP_Pos                (0UL)          /*!< FLSTOP (Bit 0)                                        */
26087  #define R_SYSTEM_FLSTOP_FLSTOP_Msk                (0x1UL)        /*!< FLSTOP (Bitfield-Mask: 0x01)                          */
26088 /* =========================================================  PSMCR  ========================================================= */
26089  #define R_SYSTEM_PSMCR_PSMC_Pos                   (0UL)          /*!< PSMC (Bit 0)                                          */
26090  #define R_SYSTEM_PSMCR_PSMC_Msk                   (0x3UL)        /*!< PSMC (Bitfield-Mask: 0x03)                            */
26091 /* =========================================================  OPCCR  ========================================================= */
26092  #define R_SYSTEM_OPCCR_OPCMTSF_Pos                (4UL)          /*!< OPCMTSF (Bit 4)                                       */
26093  #define R_SYSTEM_OPCCR_OPCMTSF_Msk                (0x10UL)       /*!< OPCMTSF (Bitfield-Mask: 0x01)                         */
26094  #define R_SYSTEM_OPCCR_OPCM_Pos                   (0UL)          /*!< OPCM (Bit 0)                                          */
26095  #define R_SYSTEM_OPCCR_OPCM_Msk                   (0x3UL)        /*!< OPCM (Bitfield-Mask: 0x03)                            */
26096 /* ========================================================  SOPCCR  ========================================================= */
26097  #define R_SYSTEM_SOPCCR_SOPCMTSF_Pos              (4UL)          /*!< SOPCMTSF (Bit 4)                                      */
26098  #define R_SYSTEM_SOPCCR_SOPCMTSF_Msk              (0x10UL)       /*!< SOPCMTSF (Bitfield-Mask: 0x01)                        */
26099  #define R_SYSTEM_SOPCCR_SOPCM_Pos                 (0UL)          /*!< SOPCM (Bit 0)                                         */
26100  #define R_SYSTEM_SOPCCR_SOPCM_Msk                 (0x1UL)        /*!< SOPCM (Bitfield-Mask: 0x01)                           */
26101 /* =======================================================  MOSCWTCR  ======================================================== */
26102  #define R_SYSTEM_MOSCWTCR_MSTS_Pos                (0UL)          /*!< MSTS (Bit 0)                                          */
26103  #define R_SYSTEM_MOSCWTCR_MSTS_Msk                (0xfUL)        /*!< MSTS (Bitfield-Mask: 0x0f)                            */
26104 /* =======================================================  HOCOWTCR  ======================================================== */
26105  #define R_SYSTEM_HOCOWTCR_HSTS_Pos                (0UL)          /*!< HSTS (Bit 0)                                          */
26106  #define R_SYSTEM_HOCOWTCR_HSTS_Msk                (0x7UL)        /*!< HSTS (Bitfield-Mask: 0x07)                            */
26107 /* ========================================================  RSTSR1  ========================================================= */
26108  #define R_SYSTEM_RSTSR1_SPERF_Pos                 (12UL)         /*!< SPERF (Bit 12)                                        */
26109  #define R_SYSTEM_RSTSR1_SPERF_Msk                 (0x1000UL)     /*!< SPERF (Bitfield-Mask: 0x01)                           */
26110  #define R_SYSTEM_RSTSR1_BUSMRF_Pos                (11UL)         /*!< BUSMRF (Bit 11)                                       */
26111  #define R_SYSTEM_RSTSR1_BUSMRF_Msk                (0x800UL)      /*!< BUSMRF (Bitfield-Mask: 0x01)                          */
26112  #define R_SYSTEM_RSTSR1_BUSSRF_Pos                (10UL)         /*!< BUSSRF (Bit 10)                                       */
26113  #define R_SYSTEM_RSTSR1_BUSSRF_Msk                (0x400UL)      /*!< BUSSRF (Bitfield-Mask: 0x01)                          */
26114  #define R_SYSTEM_RSTSR1_REERF_Pos                 (9UL)          /*!< REERF (Bit 9)                                         */
26115  #define R_SYSTEM_RSTSR1_REERF_Msk                 (0x200UL)      /*!< REERF (Bitfield-Mask: 0x01)                           */
26116  #define R_SYSTEM_RSTSR1_RPERF_Pos                 (8UL)          /*!< RPERF (Bit 8)                                         */
26117  #define R_SYSTEM_RSTSR1_RPERF_Msk                 (0x100UL)      /*!< RPERF (Bitfield-Mask: 0x01)                           */
26118  #define R_SYSTEM_RSTSR1_SWRF_Pos                  (2UL)          /*!< SWRF (Bit 2)                                          */
26119  #define R_SYSTEM_RSTSR1_SWRF_Msk                  (0x4UL)        /*!< SWRF (Bitfield-Mask: 0x01)                            */
26120  #define R_SYSTEM_RSTSR1_WDTRF_Pos                 (1UL)          /*!< WDTRF (Bit 1)                                         */
26121  #define R_SYSTEM_RSTSR1_WDTRF_Msk                 (0x2UL)        /*!< WDTRF (Bitfield-Mask: 0x01)                           */
26122  #define R_SYSTEM_RSTSR1_IWDTRF_Pos                (0UL)          /*!< IWDTRF (Bit 0)                                        */
26123  #define R_SYSTEM_RSTSR1_IWDTRF_Msk                (0x1UL)        /*!< IWDTRF (Bitfield-Mask: 0x01)                          */
26124  #define R_SYSTEM_RSTSR1_TZERF_Pos                 (13UL)         /*!< TZERF (Bit 13)                                        */
26125  #define R_SYSTEM_RSTSR1_TZERF_Msk                 (0x2000UL)     /*!< TZERF (Bitfield-Mask: 0x01)                           */
26126  #define R_SYSTEM_RSTSR1_CPERF_Pos                 (15UL)         /*!< CPERF (Bit 15)                                        */
26127  #define R_SYSTEM_RSTSR1_CPERF_Msk                 (0x8000UL)     /*!< CPERF (Bitfield-Mask: 0x01)                           */
26128 /* ========================================================  STCONR  ========================================================= */
26129  #define R_SYSTEM_STCONR_STCON_Pos                 (0UL)          /*!< STCON (Bit 0)                                         */
26130  #define R_SYSTEM_STCONR_STCON_Msk                 (0x3UL)        /*!< STCON (Bitfield-Mask: 0x03)                           */
26131 /* ========================================================  LVD1CR1  ======================================================== */
26132  #define R_SYSTEM_LVD1CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
26133  #define R_SYSTEM_LVD1CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
26134  #define R_SYSTEM_LVD1CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
26135  #define R_SYSTEM_LVD1CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
26136 /* ========================================================  LVD2CR1  ======================================================== */
26137  #define R_SYSTEM_LVD2CR1_IRQSEL_Pos               (2UL)          /*!< IRQSEL (Bit 2)                                        */
26138  #define R_SYSTEM_LVD2CR1_IRQSEL_Msk               (0x4UL)        /*!< IRQSEL (Bitfield-Mask: 0x01)                          */
26139  #define R_SYSTEM_LVD2CR1_IDTSEL_Pos               (0UL)          /*!< IDTSEL (Bit 0)                                        */
26140  #define R_SYSTEM_LVD2CR1_IDTSEL_Msk               (0x3UL)        /*!< IDTSEL (Bitfield-Mask: 0x03)                          */
26141 /* ======================================================  USBCKCR_ALT  ====================================================== */
26142  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Pos        (0UL)          /*!< USBCLKSEL (Bit 0)                                     */
26143  #define R_SYSTEM_USBCKCR_ALT_USBCLKSEL_Msk        (0x1UL)        /*!< USBCLKSEL (Bitfield-Mask: 0x01)                       */
26144 /* =======================================================  SDADCCKCR  ======================================================= */
26145  #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Pos         (0UL)          /*!< SDADCCKSEL (Bit 0)                                    */
26146  #define R_SYSTEM_SDADCCKCR_SDADCCKSEL_Msk         (0x1UL)        /*!< SDADCCKSEL (Bitfield-Mask: 0x01)                      */
26147  #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Pos          (7UL)          /*!< SDADCCKEN (Bit 7)                                     */
26148  #define R_SYSTEM_SDADCCKCR_SDADCCKEN_Msk          (0x80UL)       /*!< SDADCCKEN (Bitfield-Mask: 0x01)                       */
26149 /* ========================================================  LVD1SR  ========================================================= */
26150  #define R_SYSTEM_LVD1SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
26151  #define R_SYSTEM_LVD1SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
26152  #define R_SYSTEM_LVD1SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
26153  #define R_SYSTEM_LVD1SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
26154 /* ========================================================  LVD2SR  ========================================================= */
26155  #define R_SYSTEM_LVD2SR_MON_Pos                   (1UL)          /*!< MON (Bit 1)                                           */
26156  #define R_SYSTEM_LVD2SR_MON_Msk                   (0x2UL)        /*!< MON (Bitfield-Mask: 0x01)                             */
26157  #define R_SYSTEM_LVD2SR_DET_Pos                   (0UL)          /*!< DET (Bit 0)                                           */
26158  #define R_SYSTEM_LVD2SR_DET_Msk                   (0x1UL)        /*!< DET (Bitfield-Mask: 0x01)                             */
26159 /* =========================================================  PRCR  ========================================================== */
26160  #define R_SYSTEM_PRCR_PRKEY_Pos                   (8UL)          /*!< PRKEY (Bit 8)                                         */
26161  #define R_SYSTEM_PRCR_PRKEY_Msk                   (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
26162  #define R_SYSTEM_PRCR_PRC3_Pos                    (3UL)          /*!< PRC3 (Bit 3)                                          */
26163  #define R_SYSTEM_PRCR_PRC3_Msk                    (0x8UL)        /*!< PRC3 (Bitfield-Mask: 0x01)                            */
26164  #define R_SYSTEM_PRCR_PRC1_Pos                    (1UL)          /*!< PRC1 (Bit 1)                                          */
26165  #define R_SYSTEM_PRCR_PRC1_Msk                    (0x2UL)        /*!< PRC1 (Bitfield-Mask: 0x01)                            */
26166  #define R_SYSTEM_PRCR_PRC0_Pos                    (0UL)          /*!< PRC0 (Bit 0)                                          */
26167  #define R_SYSTEM_PRCR_PRC0_Msk                    (0x1UL)        /*!< PRC0 (Bitfield-Mask: 0x01)                            */
26168  #define R_SYSTEM_PRCR_PRC4_Pos                    (4UL)          /*!< PRC4 (Bit 4)                                          */
26169  #define R_SYSTEM_PRCR_PRC4_Msk                    (0x10UL)       /*!< PRC4 (Bitfield-Mask: 0x01)                            */
26170 /* ========================================================  DPSIER0  ======================================================== */
26171  #define R_SYSTEM_DPSIER0_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
26172  #define R_SYSTEM_DPSIER0_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
26173 /* ========================================================  DPSIER1  ======================================================== */
26174  #define R_SYSTEM_DPSIER1_DIRQE_Pos                (0UL)          /*!< DIRQE (Bit 0)                                         */
26175  #define R_SYSTEM_DPSIER1_DIRQE_Msk                (0x1UL)        /*!< DIRQE (Bitfield-Mask: 0x01)                           */
26176 /* ========================================================  DPSIER2  ======================================================== */
26177  #define R_SYSTEM_DPSIER2_DNMIE_Pos                (4UL)          /*!< DNMIE (Bit 4)                                         */
26178  #define R_SYSTEM_DPSIER2_DNMIE_Msk                (0x10UL)       /*!< DNMIE (Bitfield-Mask: 0x01)                           */
26179  #define R_SYSTEM_DPSIER2_DRTCAIE_Pos              (3UL)          /*!< DRTCAIE (Bit 3)                                       */
26180  #define R_SYSTEM_DPSIER2_DRTCAIE_Msk              (0x8UL)        /*!< DRTCAIE (Bitfield-Mask: 0x01)                         */
26181  #define R_SYSTEM_DPSIER2_DTRTCIIE_Pos             (2UL)          /*!< DTRTCIIE (Bit 2)                                      */
26182  #define R_SYSTEM_DPSIER2_DTRTCIIE_Msk             (0x4UL)        /*!< DTRTCIIE (Bitfield-Mask: 0x01)                        */
26183  #define R_SYSTEM_DPSIER2_DLVD2IE_Pos              (1UL)          /*!< DLVD2IE (Bit 1)                                       */
26184  #define R_SYSTEM_DPSIER2_DLVD2IE_Msk              (0x2UL)        /*!< DLVD2IE (Bitfield-Mask: 0x01)                         */
26185  #define R_SYSTEM_DPSIER2_DLVD1IE_Pos              (0UL)          /*!< DLVD1IE (Bit 0)                                       */
26186  #define R_SYSTEM_DPSIER2_DLVD1IE_Msk              (0x1UL)        /*!< DLVD1IE (Bitfield-Mask: 0x01)                         */
26187 /* ========================================================  DPSIER3  ======================================================== */
26188  #define R_SYSTEM_DPSIER3_DAGT1IE_Pos              (2UL)          /*!< DAGT1IE (Bit 2)                                       */
26189  #define R_SYSTEM_DPSIER3_DAGT1IE_Msk              (0x4UL)        /*!< DAGT1IE (Bitfield-Mask: 0x01)                         */
26190  #define R_SYSTEM_DPSIER3_DUSBHSIE_Pos             (1UL)          /*!< DUSBHSIE (Bit 1)                                      */
26191  #define R_SYSTEM_DPSIER3_DUSBHSIE_Msk             (0x2UL)        /*!< DUSBHSIE (Bitfield-Mask: 0x01)                        */
26192  #define R_SYSTEM_DPSIER3_DUSBFSIE_Pos             (0UL)          /*!< DUSBFSIE (Bit 0)                                      */
26193  #define R_SYSTEM_DPSIER3_DUSBFSIE_Msk             (0x1UL)        /*!< DUSBFSIE (Bitfield-Mask: 0x01)                        */
26194  #define R_SYSTEM_DPSIER3_DAGT3IE_Pos              (3UL)          /*!< DAGT3IE (Bit 3)                                       */
26195  #define R_SYSTEM_DPSIER3_DAGT3IE_Msk              (0x8UL)        /*!< DAGT3IE (Bitfield-Mask: 0x01)                         */
26196 /* ========================================================  DPSIFR0  ======================================================== */
26197  #define R_SYSTEM_DPSIFR0_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
26198  #define R_SYSTEM_DPSIFR0_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
26199 /* ========================================================  DPSIFR1  ======================================================== */
26200  #define R_SYSTEM_DPSIFR1_DIRQF_Pos                (0UL)          /*!< DIRQF (Bit 0)                                         */
26201  #define R_SYSTEM_DPSIFR1_DIRQF_Msk                (0x1UL)        /*!< DIRQF (Bitfield-Mask: 0x01)                           */
26202 /* ========================================================  DPSIFR2  ======================================================== */
26203  #define R_SYSTEM_DPSIFR2_DNMIF_Pos                (4UL)          /*!< DNMIF (Bit 4)                                         */
26204  #define R_SYSTEM_DPSIFR2_DNMIF_Msk                (0x10UL)       /*!< DNMIF (Bitfield-Mask: 0x01)                           */
26205  #define R_SYSTEM_DPSIFR2_DRTCAIF_Pos              (3UL)          /*!< DRTCAIF (Bit 3)                                       */
26206  #define R_SYSTEM_DPSIFR2_DRTCAIF_Msk              (0x8UL)        /*!< DRTCAIF (Bitfield-Mask: 0x01)                         */
26207  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Pos             (2UL)          /*!< DTRTCIIF (Bit 2)                                      */
26208  #define R_SYSTEM_DPSIFR2_DTRTCIIF_Msk             (0x4UL)        /*!< DTRTCIIF (Bitfield-Mask: 0x01)                        */
26209  #define R_SYSTEM_DPSIFR2_DLVD2IF_Pos              (1UL)          /*!< DLVD2IF (Bit 1)                                       */
26210  #define R_SYSTEM_DPSIFR2_DLVD2IF_Msk              (0x2UL)        /*!< DLVD2IF (Bitfield-Mask: 0x01)                         */
26211  #define R_SYSTEM_DPSIFR2_DLVD1IF_Pos              (0UL)          /*!< DLVD1IF (Bit 0)                                       */
26212  #define R_SYSTEM_DPSIFR2_DLVD1IF_Msk              (0x1UL)        /*!< DLVD1IF (Bitfield-Mask: 0x01)                         */
26213 /* ========================================================  DPSIFR3  ======================================================== */
26214  #define R_SYSTEM_DPSIFR3_DAGT1IF_Pos              (2UL)          /*!< DAGT1IF (Bit 2)                                       */
26215  #define R_SYSTEM_DPSIFR3_DAGT1IF_Msk              (0x4UL)        /*!< DAGT1IF (Bitfield-Mask: 0x01)                         */
26216  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Pos             (1UL)          /*!< DUSBHSIF (Bit 1)                                      */
26217  #define R_SYSTEM_DPSIFR3_DUSBHSIF_Msk             (0x2UL)        /*!< DUSBHSIF (Bitfield-Mask: 0x01)                        */
26218  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Pos             (0UL)          /*!< DUSBFSIF (Bit 0)                                      */
26219  #define R_SYSTEM_DPSIFR3_DUSBFSIF_Msk             (0x1UL)        /*!< DUSBFSIF (Bitfield-Mask: 0x01)                        */
26220  #define R_SYSTEM_DPSIFR3_DAGT3IF_Pos              (3UL)          /*!< DAGT3IF (Bit 3)                                       */
26221  #define R_SYSTEM_DPSIFR3_DAGT3IF_Msk              (0x8UL)        /*!< DAGT3IF (Bitfield-Mask: 0x01)                         */
26222 /* =======================================================  DPSIEGR0  ======================================================== */
26223  #define R_SYSTEM_DPSIEGR0_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
26224  #define R_SYSTEM_DPSIEGR0_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
26225 /* =======================================================  DPSIEGR1  ======================================================== */
26226  #define R_SYSTEM_DPSIEGR1_DIRQEG_Pos              (0UL)          /*!< DIRQEG (Bit 0)                                        */
26227  #define R_SYSTEM_DPSIEGR1_DIRQEG_Msk              (0x1UL)        /*!< DIRQEG (Bitfield-Mask: 0x01)                          */
26228 /* =======================================================  DPSIEGR2  ======================================================== */
26229  #define R_SYSTEM_DPSIEGR2_DNMIEG_Pos              (4UL)          /*!< DNMIEG (Bit 4)                                        */
26230  #define R_SYSTEM_DPSIEGR2_DNMIEG_Msk              (0x10UL)       /*!< DNMIEG (Bitfield-Mask: 0x01)                          */
26231  #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Pos            (1UL)          /*!< DLVD2IEG (Bit 1)                                      */
26232  #define R_SYSTEM_DPSIEGR2_DLVD2IEG_Msk            (0x2UL)        /*!< DLVD2IEG (Bitfield-Mask: 0x01)                        */
26233  #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Pos            (0UL)          /*!< DLVD1IEG (Bit 0)                                      */
26234  #define R_SYSTEM_DPSIEGR2_DLVD1IEG_Msk            (0x1UL)        /*!< DLVD1IEG (Bitfield-Mask: 0x01)                        */
26235 /* ========================================================  DPSBYCR  ======================================================== */
26236  #define R_SYSTEM_DPSBYCR_DPSBY_Pos                (7UL)          /*!< DPSBY (Bit 7)                                         */
26237  #define R_SYSTEM_DPSBYCR_DPSBY_Msk                (0x80UL)       /*!< DPSBY (Bitfield-Mask: 0x01)                           */
26238  #define R_SYSTEM_DPSBYCR_IOKEEP_Pos               (6UL)          /*!< IOKEEP (Bit 6)                                        */
26239  #define R_SYSTEM_DPSBYCR_IOKEEP_Msk               (0x40UL)       /*!< IOKEEP (Bitfield-Mask: 0x01)                          */
26240  #define R_SYSTEM_DPSBYCR_DEEPCUT_Pos              (0UL)          /*!< DEEPCUT (Bit 0)                                       */
26241  #define R_SYSTEM_DPSBYCR_DEEPCUT_Msk              (0x3UL)        /*!< DEEPCUT (Bitfield-Mask: 0x03)                         */
26242 /* ========================================================  SYOCDCR  ======================================================== */
26243  #define R_SYSTEM_SYOCDCR_DBGEN_Pos                (7UL)          /*!< DBGEN (Bit 7)                                         */
26244  #define R_SYSTEM_SYOCDCR_DBGEN_Msk                (0x80UL)       /*!< DBGEN (Bitfield-Mask: 0x01)                           */
26245  #define R_SYSTEM_SYOCDCR_DOCDF_Pos                (0UL)          /*!< DOCDF (Bit 0)                                         */
26246  #define R_SYSTEM_SYOCDCR_DOCDF_Msk                (0x1UL)        /*!< DOCDF (Bitfield-Mask: 0x01)                           */
26247 /* =========================================================  MOMCR  ========================================================= */
26248  #define R_SYSTEM_MOMCR_AUTODRVEN_Pos              (7UL)          /*!< AUTODRVEN (Bit 7)                                     */
26249  #define R_SYSTEM_MOMCR_AUTODRVEN_Msk              (0x80UL)       /*!< AUTODRVEN (Bitfield-Mask: 0x01)                       */
26250  #define R_SYSTEM_MOMCR_MOSEL_Pos                  (6UL)          /*!< MOSEL (Bit 6)                                         */
26251  #define R_SYSTEM_MOMCR_MOSEL_Msk                  (0x40UL)       /*!< MOSEL (Bitfield-Mask: 0x01)                           */
26252  #define R_SYSTEM_MOMCR_MODRV0_Pos                 (4UL)          /*!< MODRV0 (Bit 4)                                        */
26253  #define R_SYSTEM_MOMCR_MODRV0_Msk                 (0x30UL)       /*!< MODRV0 (Bitfield-Mask: 0x03)                          */
26254  #define R_SYSTEM_MOMCR_MODRV1_Pos                 (3UL)          /*!< MODRV1 (Bit 3)                                        */
26255  #define R_SYSTEM_MOMCR_MODRV1_Msk                 (0x8UL)        /*!< MODRV1 (Bitfield-Mask: 0x01)                          */
26256 /* ========================================================  RSTSR0  ========================================================= */
26257  #define R_SYSTEM_RSTSR0_DPSRSTF_Pos               (7UL)          /*!< DPSRSTF (Bit 7)                                       */
26258  #define R_SYSTEM_RSTSR0_DPSRSTF_Msk               (0x80UL)       /*!< DPSRSTF (Bitfield-Mask: 0x01)                         */
26259  #define R_SYSTEM_RSTSR0_LVD2RF_Pos                (3UL)          /*!< LVD2RF (Bit 3)                                        */
26260  #define R_SYSTEM_RSTSR0_LVD2RF_Msk                (0x8UL)        /*!< LVD2RF (Bitfield-Mask: 0x01)                          */
26261  #define R_SYSTEM_RSTSR0_LVD1RF_Pos                (2UL)          /*!< LVD1RF (Bit 2)                                        */
26262  #define R_SYSTEM_RSTSR0_LVD1RF_Msk                (0x4UL)        /*!< LVD1RF (Bitfield-Mask: 0x01)                          */
26263  #define R_SYSTEM_RSTSR0_LVD0RF_Pos                (1UL)          /*!< LVD0RF (Bit 1)                                        */
26264  #define R_SYSTEM_RSTSR0_LVD0RF_Msk                (0x2UL)        /*!< LVD0RF (Bitfield-Mask: 0x01)                          */
26265  #define R_SYSTEM_RSTSR0_PORF_Pos                  (0UL)          /*!< PORF (Bit 0)                                          */
26266  #define R_SYSTEM_RSTSR0_PORF_Msk                  (0x1UL)        /*!< PORF (Bitfield-Mask: 0x01)                            */
26267 /* ========================================================  RSTSR2  ========================================================= */
26268  #define R_SYSTEM_RSTSR2_CWSF_Pos                  (0UL)          /*!< CWSF (Bit 0)                                          */
26269  #define R_SYSTEM_RSTSR2_CWSF_Msk                  (0x1UL)        /*!< CWSF (Bitfield-Mask: 0x01)                            */
26270 /* ========================================================  LVCMPCR  ======================================================== */
26271  #define R_SYSTEM_LVCMPCR_LVD2E_Pos                (6UL)          /*!< LVD2E (Bit 6)                                         */
26272  #define R_SYSTEM_LVCMPCR_LVD2E_Msk                (0x40UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
26273  #define R_SYSTEM_LVCMPCR_LVD1E_Pos                (5UL)          /*!< LVD1E (Bit 5)                                         */
26274  #define R_SYSTEM_LVCMPCR_LVD1E_Msk                (0x20UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
26275 /* =======================================================  LVD1CMPCR  ======================================================= */
26276  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Pos            (0UL)          /*!< LVD1LVL (Bit 0)                                       */
26277  #define R_SYSTEM_LVD1CMPCR_LVD1LVL_Msk            (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
26278  #define R_SYSTEM_LVD1CMPCR_LVD1E_Pos              (7UL)          /*!< LVD1E (Bit 7)                                         */
26279  #define R_SYSTEM_LVD1CMPCR_LVD1E_Msk              (0x80UL)       /*!< LVD1E (Bitfield-Mask: 0x01)                           */
26280 /* ========================================================  LVDLVLR  ======================================================== */
26281  #define R_SYSTEM_LVDLVLR_LVD2LVL_Pos              (5UL)          /*!< LVD2LVL (Bit 5)                                       */
26282  #define R_SYSTEM_LVDLVLR_LVD2LVL_Msk              (0xe0UL)       /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
26283  #define R_SYSTEM_LVDLVLR_LVD1LVL_Pos              (0UL)          /*!< LVD1LVL (Bit 0)                                       */
26284  #define R_SYSTEM_LVDLVLR_LVD1LVL_Msk              (0x1fUL)       /*!< LVD1LVL (Bitfield-Mask: 0x1f)                         */
26285 /* =======================================================  LVD2CMPCR  ======================================================= */
26286  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Pos            (0UL)          /*!< LVD2LVL (Bit 0)                                       */
26287  #define R_SYSTEM_LVD2CMPCR_LVD2LVL_Msk            (0x7UL)        /*!< LVD2LVL (Bitfield-Mask: 0x07)                         */
26288  #define R_SYSTEM_LVD2CMPCR_LVD2E_Pos              (7UL)          /*!< LVD2E (Bit 7)                                         */
26289  #define R_SYSTEM_LVD2CMPCR_LVD2E_Msk              (0x80UL)       /*!< LVD2E (Bitfield-Mask: 0x01)                           */
26290 /* ========================================================  LVD1CR0  ======================================================== */
26291  #define R_SYSTEM_LVD1CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
26292  #define R_SYSTEM_LVD1CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
26293  #define R_SYSTEM_LVD1CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
26294  #define R_SYSTEM_LVD1CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
26295  #define R_SYSTEM_LVD1CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
26296  #define R_SYSTEM_LVD1CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
26297  #define R_SYSTEM_LVD1CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
26298  #define R_SYSTEM_LVD1CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
26299  #define R_SYSTEM_LVD1CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
26300  #define R_SYSTEM_LVD1CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
26301  #define R_SYSTEM_LVD1CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
26302  #define R_SYSTEM_LVD1CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
26303 /* ========================================================  LVD2CR0  ======================================================== */
26304  #define R_SYSTEM_LVD2CR0_RN_Pos                   (7UL)          /*!< RN (Bit 7)                                            */
26305  #define R_SYSTEM_LVD2CR0_RN_Msk                   (0x80UL)       /*!< RN (Bitfield-Mask: 0x01)                              */
26306  #define R_SYSTEM_LVD2CR0_RI_Pos                   (6UL)          /*!< RI (Bit 6)                                            */
26307  #define R_SYSTEM_LVD2CR0_RI_Msk                   (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
26308  #define R_SYSTEM_LVD2CR0_FSAMP_Pos                (4UL)          /*!< FSAMP (Bit 4)                                         */
26309  #define R_SYSTEM_LVD2CR0_FSAMP_Msk                (0x30UL)       /*!< FSAMP (Bitfield-Mask: 0x03)                           */
26310  #define R_SYSTEM_LVD2CR0_CMPE_Pos                 (2UL)          /*!< CMPE (Bit 2)                                          */
26311  #define R_SYSTEM_LVD2CR0_CMPE_Msk                 (0x4UL)        /*!< CMPE (Bitfield-Mask: 0x01)                            */
26312  #define R_SYSTEM_LVD2CR0_DFDIS_Pos                (1UL)          /*!< DFDIS (Bit 1)                                         */
26313  #define R_SYSTEM_LVD2CR0_DFDIS_Msk                (0x2UL)        /*!< DFDIS (Bitfield-Mask: 0x01)                           */
26314  #define R_SYSTEM_LVD2CR0_RIE_Pos                  (0UL)          /*!< RIE (Bit 0)                                           */
26315  #define R_SYSTEM_LVD2CR0_RIE_Msk                  (0x1UL)        /*!< RIE (Bitfield-Mask: 0x01)                             */
26316 /* ========================================================  VBTCR1  ========================================================= */
26317  #define R_SYSTEM_VBTCR1_BPWSWSTP_Pos              (0UL)          /*!< BPWSWSTP (Bit 0)                                      */
26318  #define R_SYSTEM_VBTCR1_BPWSWSTP_Msk              (0x1UL)        /*!< BPWSWSTP (Bitfield-Mask: 0x01)                        */
26319 /* ========================================================  DCDCCTL  ======================================================== */
26320  #define R_SYSTEM_DCDCCTL_PD_Pos                   (7UL)          /*!< PD (Bit 7)                                            */
26321  #define R_SYSTEM_DCDCCTL_PD_Msk                   (0x80UL)       /*!< PD (Bitfield-Mask: 0x01)                              */
26322  #define R_SYSTEM_DCDCCTL_FST_Pos                  (6UL)          /*!< FST (Bit 6)                                           */
26323  #define R_SYSTEM_DCDCCTL_FST_Msk                  (0x40UL)       /*!< FST (Bitfield-Mask: 0x01)                             */
26324  #define R_SYSTEM_DCDCCTL_LCBOOST_Pos              (5UL)          /*!< LCBOOST (Bit 5)                                       */
26325  #define R_SYSTEM_DCDCCTL_LCBOOST_Msk              (0x20UL)       /*!< LCBOOST (Bitfield-Mask: 0x01)                         */
26326  #define R_SYSTEM_DCDCCTL_STOPZA_Pos               (4UL)          /*!< STOPZA (Bit 4)                                        */
26327  #define R_SYSTEM_DCDCCTL_STOPZA_Msk               (0x10UL)       /*!< STOPZA (Bitfield-Mask: 0x01)                          */
26328  #define R_SYSTEM_DCDCCTL_OCPEN_Pos                (1UL)          /*!< OCPEN (Bit 1)                                         */
26329  #define R_SYSTEM_DCDCCTL_OCPEN_Msk                (0x2UL)        /*!< OCPEN (Bitfield-Mask: 0x01)                           */
26330  #define R_SYSTEM_DCDCCTL_DCDCON_Pos               (0UL)          /*!< DCDCON (Bit 0)                                        */
26331  #define R_SYSTEM_DCDCCTL_DCDCON_Msk               (0x1UL)        /*!< DCDCON (Bitfield-Mask: 0x01)                          */
26332 /* ========================================================  VCCSEL  ========================================================= */
26333  #define R_SYSTEM_VCCSEL_VCCSEL_Pos                (0UL)          /*!< VCCSEL (Bit 0)                                        */
26334  #define R_SYSTEM_VCCSEL_VCCSEL_Msk                (0x3UL)        /*!< VCCSEL (Bitfield-Mask: 0x03)                          */
26335 /* ========================================================  LDOSCR  ========================================================= */
26336  #define R_SYSTEM_LDOSCR_LDOSTP0_Pos               (0UL)          /*!< LDOSTP0 (Bit 0)                                       */
26337  #define R_SYSTEM_LDOSCR_LDOSTP0_Msk               (0x1UL)        /*!< LDOSTP0 (Bitfield-Mask: 0x01)                         */
26338  #define R_SYSTEM_LDOSCR_LDOSTP1_Pos               (1UL)          /*!< LDOSTP1 (Bit 1)                                       */
26339  #define R_SYSTEM_LDOSCR_LDOSTP1_Msk               (0x2UL)        /*!< LDOSTP1 (Bitfield-Mask: 0x01)                         */
26340 /* =======================================================  PL2LDOSCR  ======================================================= */
26341  #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Pos          (0UL)          /*!< PL2LDOSTP (Bit 0)                                     */
26342  #define R_SYSTEM_PL2LDOSCR_PL2LDOSTP_Msk          (0x1UL)        /*!< PL2LDOSTP (Bitfield-Mask: 0x01)                       */
26343 /* ========================================================  SOSCCR  ========================================================= */
26344  #define R_SYSTEM_SOSCCR_SOSTP_Pos                 (0UL)          /*!< SOSTP (Bit 0)                                         */
26345  #define R_SYSTEM_SOSCCR_SOSTP_Msk                 (0x1UL)        /*!< SOSTP (Bitfield-Mask: 0x01)                           */
26346 /* =========================================================  SOMCR  ========================================================= */
26347  #define R_SYSTEM_SOMCR_SODRV_Pos                  (0UL)          /*!< SODRV (Bit 0)                                         */
26348  #define R_SYSTEM_SOMCR_SODRV_Msk                  (0x3UL)        /*!< SODRV (Bitfield-Mask: 0x03)                           */
26349 /* =========================================================  SOMRG  ========================================================= */
26350  #define R_SYSTEM_SOMRG_SOSCMRG_Pos                (0UL)          /*!< SOSCMRG (Bit 0)                                       */
26351  #define R_SYSTEM_SOMRG_SOSCMRG_Msk                (0x3UL)        /*!< SOSCMRG (Bitfield-Mask: 0x03)                         */
26352 /* ========================================================  LOCOCR  ========================================================= */
26353  #define R_SYSTEM_LOCOCR_LCSTP_Pos                 (0UL)          /*!< LCSTP (Bit 0)                                         */
26354  #define R_SYSTEM_LOCOCR_LCSTP_Msk                 (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
26355 /* =======================================================  LOCOUTCR  ======================================================== */
26356  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Pos            (0UL)          /*!< LOCOUTRM (Bit 0)                                      */
26357  #define R_SYSTEM_LOCOUTCR_LOCOUTRM_Msk            (0xffUL)       /*!< LOCOUTRM (Bitfield-Mask: 0xff)                        */
26358 /* ========================================================  VBTCR2  ========================================================= */
26359  #define R_SYSTEM_VBTCR2_VBTLVDLVL_Pos             (6UL)          /*!< VBTLVDLVL (Bit 6)                                     */
26360  #define R_SYSTEM_VBTCR2_VBTLVDLVL_Msk             (0xc0UL)       /*!< VBTLVDLVL (Bitfield-Mask: 0x03)                       */
26361  #define R_SYSTEM_VBTCR2_VBTLVDEN_Pos              (4UL)          /*!< VBTLVDEN (Bit 4)                                      */
26362  #define R_SYSTEM_VBTCR2_VBTLVDEN_Msk              (0x10UL)       /*!< VBTLVDEN (Bitfield-Mask: 0x01)                        */
26363 /* =========================================================  VBTSR  ========================================================= */
26364  #define R_SYSTEM_VBTSR_VBTRVLD_Pos                (4UL)          /*!< VBTRVLD (Bit 4)                                       */
26365  #define R_SYSTEM_VBTSR_VBTRVLD_Msk                (0x10UL)       /*!< VBTRVLD (Bitfield-Mask: 0x01)                         */
26366  #define R_SYSTEM_VBTSR_VBTBLDF_Pos                (1UL)          /*!< VBTBLDF (Bit 1)                                       */
26367  #define R_SYSTEM_VBTSR_VBTBLDF_Msk                (0x2UL)        /*!< VBTBLDF (Bitfield-Mask: 0x01)                         */
26368  #define R_SYSTEM_VBTSR_VBTRDF_Pos                 (0UL)          /*!< VBTRDF (Bit 0)                                        */
26369  #define R_SYSTEM_VBTSR_VBTRDF_Msk                 (0x1UL)        /*!< VBTRDF (Bitfield-Mask: 0x01)                          */
26370 /* =======================================================  VBTCMPCR  ======================================================== */
26371  #define R_SYSTEM_VBTCMPCR_VBTCMPE_Pos             (0UL)          /*!< VBTCMPE (Bit 0)                                       */
26372  #define R_SYSTEM_VBTCMPCR_VBTCMPE_Msk             (0x1UL)        /*!< VBTCMPE (Bitfield-Mask: 0x01)                         */
26373 /* =======================================================  VBTLVDICR  ======================================================= */
26374  #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Pos         (1UL)          /*!< VBTLVDISEL (Bit 1)                                    */
26375  #define R_SYSTEM_VBTLVDICR_VBTLVDISEL_Msk         (0x2UL)        /*!< VBTLVDISEL (Bitfield-Mask: 0x01)                      */
26376  #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Pos           (0UL)          /*!< VBTLVDIE (Bit 0)                                      */
26377  #define R_SYSTEM_VBTLVDICR_VBTLVDIE_Msk           (0x1UL)        /*!< VBTLVDIE (Bitfield-Mask: 0x01)                        */
26378 /* =======================================================  VBTWCTLR  ======================================================== */
26379  #define R_SYSTEM_VBTWCTLR_VWEN_Pos                (0UL)          /*!< VWEN (Bit 0)                                          */
26380  #define R_SYSTEM_VBTWCTLR_VWEN_Msk                (0x1UL)        /*!< VWEN (Bitfield-Mask: 0x01)                            */
26381 /* ======================================================  VBTWCH0OTSR  ====================================================== */
26382  #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Pos       (5UL)          /*!< CH0VAGTUTE (Bit 5)                                    */
26383  #define R_SYSTEM_VBTWCH0OTSR_CH0VAGTUTE_Msk       (0x20UL)       /*!< CH0VAGTUTE (Bitfield-Mask: 0x01)                      */
26384  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Pos       (4UL)          /*!< CH0VRTCATE (Bit 4)                                    */
26385  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCATE_Msk       (0x10UL)       /*!< CH0VRTCATE (Bitfield-Mask: 0x01)                      */
26386  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Pos        (3UL)          /*!< CH0VRTCTE (Bit 3)                                     */
26387  #define R_SYSTEM_VBTWCH0OTSR_CH0VRTCTE_Msk        (0x8UL)        /*!< CH0VRTCTE (Bitfield-Mask: 0x01)                       */
26388  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Pos        (2UL)          /*!< CH0VCH2TE (Bit 2)                                     */
26389  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH2TE_Msk        (0x4UL)        /*!< CH0VCH2TE (Bitfield-Mask: 0x01)                       */
26390  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Pos        (1UL)          /*!< CH0VCH1TE (Bit 1)                                     */
26391  #define R_SYSTEM_VBTWCH0OTSR_CH0VCH1TE_Msk        (0x2UL)        /*!< CH0VCH1TE (Bitfield-Mask: 0x01)                       */
26392 /* ======================================================  VBTWCH1OTSR  ====================================================== */
26393  #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Pos       (5UL)          /*!< CH1VAGTUTE (Bit 5)                                    */
26394  #define R_SYSTEM_VBTWCH1OTSR_CH1VAGTUTE_Msk       (0x20UL)       /*!< CH1VAGTUTE (Bitfield-Mask: 0x01)                      */
26395  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Pos       (4UL)          /*!< CH1VRTCATE (Bit 4)                                    */
26396  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCATE_Msk       (0x10UL)       /*!< CH1VRTCATE (Bitfield-Mask: 0x01)                      */
26397  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Pos        (3UL)          /*!< CH1VRTCTE (Bit 3)                                     */
26398  #define R_SYSTEM_VBTWCH1OTSR_CH1VRTCTE_Msk        (0x8UL)        /*!< CH1VRTCTE (Bitfield-Mask: 0x01)                       */
26399  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Pos        (2UL)          /*!< CH1VCH2TE (Bit 2)                                     */
26400  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH2TE_Msk        (0x4UL)        /*!< CH1VCH2TE (Bitfield-Mask: 0x01)                       */
26401  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Pos        (0UL)          /*!< CH1VCH0TE (Bit 0)                                     */
26402  #define R_SYSTEM_VBTWCH1OTSR_CH1VCH0TE_Msk        (0x1UL)        /*!< CH1VCH0TE (Bitfield-Mask: 0x01)                       */
26403 /* ======================================================  VBTWCH2OTSR  ====================================================== */
26404  #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Pos       (5UL)          /*!< CH2VAGTUTE (Bit 5)                                    */
26405  #define R_SYSTEM_VBTWCH2OTSR_CH2VAGTUTE_Msk       (0x20UL)       /*!< CH2VAGTUTE (Bitfield-Mask: 0x01)                      */
26406  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Pos       (4UL)          /*!< CH2VRTCATE (Bit 4)                                    */
26407  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCATE_Msk       (0x10UL)       /*!< CH2VRTCATE (Bitfield-Mask: 0x01)                      */
26408  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Pos        (3UL)          /*!< CH2VRTCTE (Bit 3)                                     */
26409  #define R_SYSTEM_VBTWCH2OTSR_CH2VRTCTE_Msk        (0x8UL)        /*!< CH2VRTCTE (Bitfield-Mask: 0x01)                       */
26410  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Pos        (1UL)          /*!< CH2VCH1TE (Bit 1)                                     */
26411  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH1TE_Msk        (0x2UL)        /*!< CH2VCH1TE (Bitfield-Mask: 0x01)                       */
26412  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Pos        (0UL)          /*!< CH2VCH0TE (Bit 0)                                     */
26413  #define R_SYSTEM_VBTWCH2OTSR_CH2VCH0TE_Msk        (0x1UL)        /*!< CH2VCH0TE (Bitfield-Mask: 0x01)                       */
26414 /* =======================================================  VBTICTLR  ======================================================== */
26415  #define R_SYSTEM_VBTICTLR_VCH2INEN_Pos            (2UL)          /*!< VCH2INEN (Bit 2)                                      */
26416  #define R_SYSTEM_VBTICTLR_VCH2INEN_Msk            (0x4UL)        /*!< VCH2INEN (Bitfield-Mask: 0x01)                        */
26417  #define R_SYSTEM_VBTICTLR_VCH1INEN_Pos            (1UL)          /*!< VCH1INEN (Bit 1)                                      */
26418  #define R_SYSTEM_VBTICTLR_VCH1INEN_Msk            (0x2UL)        /*!< VCH1INEN (Bitfield-Mask: 0x01)                        */
26419  #define R_SYSTEM_VBTICTLR_VCH0INEN_Pos            (0UL)          /*!< VCH0INEN (Bit 0)                                      */
26420  #define R_SYSTEM_VBTICTLR_VCH0INEN_Msk            (0x1UL)        /*!< VCH0INEN (Bitfield-Mask: 0x01)                        */
26421 /* =======================================================  VBTOCTLR  ======================================================== */
26422  #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Pos           (5UL)          /*!< VOUT2LSEL (Bit 5)                                     */
26423  #define R_SYSTEM_VBTOCTLR_VOUT2LSEL_Msk           (0x20UL)       /*!< VOUT2LSEL (Bitfield-Mask: 0x01)                       */
26424  #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Pos           (4UL)          /*!< VCOU1LSEL (Bit 4)                                     */
26425  #define R_SYSTEM_VBTOCTLR_VCOU1LSEL_Msk           (0x10UL)       /*!< VCOU1LSEL (Bitfield-Mask: 0x01)                       */
26426  #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Pos           (3UL)          /*!< VOUT0LSEL (Bit 3)                                     */
26427  #define R_SYSTEM_VBTOCTLR_VOUT0LSEL_Msk           (0x8UL)        /*!< VOUT0LSEL (Bitfield-Mask: 0x01)                       */
26428  #define R_SYSTEM_VBTOCTLR_VCH2OEN_Pos             (2UL)          /*!< VCH2OEN (Bit 2)                                       */
26429  #define R_SYSTEM_VBTOCTLR_VCH2OEN_Msk             (0x4UL)        /*!< VCH2OEN (Bitfield-Mask: 0x01)                         */
26430  #define R_SYSTEM_VBTOCTLR_VCH1OEN_Pos             (1UL)          /*!< VCH1OEN (Bit 1)                                       */
26431  #define R_SYSTEM_VBTOCTLR_VCH1OEN_Msk             (0x2UL)        /*!< VCH1OEN (Bitfield-Mask: 0x01)                         */
26432  #define R_SYSTEM_VBTOCTLR_VCH0OEN_Pos             (0UL)          /*!< VCH0OEN (Bit 0)                                       */
26433  #define R_SYSTEM_VBTOCTLR_VCH0OEN_Msk             (0x1UL)        /*!< VCH0OEN (Bitfield-Mask: 0x01)                         */
26434 /* ========================================================  VBTWTER  ======================================================== */
26435  #define R_SYSTEM_VBTWTER_VAGTUE_Pos               (5UL)          /*!< VAGTUE (Bit 5)                                        */
26436  #define R_SYSTEM_VBTWTER_VAGTUE_Msk               (0x20UL)       /*!< VAGTUE (Bitfield-Mask: 0x01)                          */
26437  #define R_SYSTEM_VBTWTER_VRTCAE_Pos               (4UL)          /*!< VRTCAE (Bit 4)                                        */
26438  #define R_SYSTEM_VBTWTER_VRTCAE_Msk               (0x10UL)       /*!< VRTCAE (Bitfield-Mask: 0x01)                          */
26439  #define R_SYSTEM_VBTWTER_VRTCIE_Pos               (3UL)          /*!< VRTCIE (Bit 3)                                        */
26440  #define R_SYSTEM_VBTWTER_VRTCIE_Msk               (0x8UL)        /*!< VRTCIE (Bitfield-Mask: 0x01)                          */
26441  #define R_SYSTEM_VBTWTER_VCH2E_Pos                (2UL)          /*!< VCH2E (Bit 2)                                         */
26442  #define R_SYSTEM_VBTWTER_VCH2E_Msk                (0x4UL)        /*!< VCH2E (Bitfield-Mask: 0x01)                           */
26443  #define R_SYSTEM_VBTWTER_VCH1E_Pos                (1UL)          /*!< VCH1E (Bit 1)                                         */
26444  #define R_SYSTEM_VBTWTER_VCH1E_Msk                (0x2UL)        /*!< VCH1E (Bitfield-Mask: 0x01)                           */
26445  #define R_SYSTEM_VBTWTER_VCH0E_Pos                (0UL)          /*!< VCH0E (Bit 0)                                         */
26446  #define R_SYSTEM_VBTWTER_VCH0E_Msk                (0x1UL)        /*!< VCH0E (Bitfield-Mask: 0x01)                           */
26447 /* ========================================================  VBTWEGR  ======================================================== */
26448  #define R_SYSTEM_VBTWEGR_VCH2EG_Pos               (2UL)          /*!< VCH2EG (Bit 2)                                        */
26449  #define R_SYSTEM_VBTWEGR_VCH2EG_Msk               (0x4UL)        /*!< VCH2EG (Bitfield-Mask: 0x01)                          */
26450  #define R_SYSTEM_VBTWEGR_VCH1EG_Pos               (1UL)          /*!< VCH1EG (Bit 1)                                        */
26451  #define R_SYSTEM_VBTWEGR_VCH1EG_Msk               (0x2UL)        /*!< VCH1EG (Bitfield-Mask: 0x01)                          */
26452  #define R_SYSTEM_VBTWEGR_VCH0EG_Pos               (0UL)          /*!< VCH0EG (Bit 0)                                        */
26453  #define R_SYSTEM_VBTWEGR_VCH0EG_Msk               (0x1UL)        /*!< VCH0EG (Bitfield-Mask: 0x01)                          */
26454 /* ========================================================  VBTWFR  ========================================================= */
26455  #define R_SYSTEM_VBTWFR_VAGTUF_Pos                (5UL)          /*!< VAGTUF (Bit 5)                                        */
26456  #define R_SYSTEM_VBTWFR_VAGTUF_Msk                (0x20UL)       /*!< VAGTUF (Bitfield-Mask: 0x01)                          */
26457  #define R_SYSTEM_VBTWFR_VRTCAF_Pos                (4UL)          /*!< VRTCAF (Bit 4)                                        */
26458  #define R_SYSTEM_VBTWFR_VRTCAF_Msk                (0x10UL)       /*!< VRTCAF (Bitfield-Mask: 0x01)                          */
26459  #define R_SYSTEM_VBTWFR_VRTCIF_Pos                (3UL)          /*!< VRTCIF (Bit 3)                                        */
26460  #define R_SYSTEM_VBTWFR_VRTCIF_Msk                (0x8UL)        /*!< VRTCIF (Bitfield-Mask: 0x01)                          */
26461  #define R_SYSTEM_VBTWFR_VCH2F_Pos                 (2UL)          /*!< VCH2F (Bit 2)                                         */
26462  #define R_SYSTEM_VBTWFR_VCH2F_Msk                 (0x4UL)        /*!< VCH2F (Bitfield-Mask: 0x01)                           */
26463  #define R_SYSTEM_VBTWFR_VCH1F_Pos                 (1UL)          /*!< VCH1F (Bit 1)                                         */
26464  #define R_SYSTEM_VBTWFR_VCH1F_Msk                 (0x2UL)        /*!< VCH1F (Bitfield-Mask: 0x01)                           */
26465  #define R_SYSTEM_VBTWFR_VCH0F_Pos                 (0UL)          /*!< VCH0F (Bit 0)                                         */
26466  #define R_SYSTEM_VBTWFR_VCH0F_Msk                 (0x1UL)        /*!< VCH0F (Bitfield-Mask: 0x01)                           */
26467 /* ========================================================  VBTBKR  ========================================================= */
26468  #define R_SYSTEM_VBTBKR_VBTBKR_Pos                (0UL)          /*!< VBTBKR (Bit 0)                                        */
26469  #define R_SYSTEM_VBTBKR_VBTBKR_Msk                (0xffUL)       /*!< VBTBKR (Bitfield-Mask: 0xff)                          */
26470 /* ========================================================  FWEPROR  ======================================================== */
26471  #define R_SYSTEM_FWEPROR_FLWE_Pos                 (0UL)          /*!< FLWE (Bit 0)                                          */
26472  #define R_SYSTEM_FWEPROR_FLWE_Msk                 (0x3UL)        /*!< FLWE (Bitfield-Mask: 0x03)                            */
26473 /* ========================================================  PLL2CCR  ======================================================== */
26474  #define R_SYSTEM_PLL2CCR_PL2IDIV_Pos              (0UL)          /*!< PL2IDIV (Bit 0)                                       */
26475  #define R_SYSTEM_PLL2CCR_PL2IDIV_Msk              (0x3UL)        /*!< PL2IDIV (Bitfield-Mask: 0x03)                         */
26476  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Pos            (4UL)          /*!< PL2SRCSEL (Bit 4)                                     */
26477  #define R_SYSTEM_PLL2CCR_PL2SRCSEL_Msk            (0x10UL)       /*!< PL2SRCSEL (Bitfield-Mask: 0x01)                       */
26478  #define R_SYSTEM_PLL2CCR_PLL2MUL_Pos              (8UL)          /*!< PLL2MUL (Bit 8)                                       */
26479  #define R_SYSTEM_PLL2CCR_PLL2MUL_Msk              (0x3f00UL)     /*!< PLL2MUL (Bitfield-Mask: 0x3f)                         */
26480 /* ========================================================  PLL2CR  ========================================================= */
26481  #define R_SYSTEM_PLL2CR_PLL2STP_Pos               (0UL)          /*!< PLL2STP (Bit 0)                                       */
26482  #define R_SYSTEM_PLL2CR_PLL2STP_Msk               (0x1UL)        /*!< PLL2STP (Bitfield-Mask: 0x01)                         */
26483 /* ======================================================  USBCKDIVCR  ======================================================= */
26484  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Pos          (0UL)          /*!< USBCKDIV (Bit 0)                                      */
26485  #define R_SYSTEM_USBCKDIVCR_USBCKDIV_Msk          (0x7UL)        /*!< USBCKDIV (Bitfield-Mask: 0x07)                        */
26486 /* ======================================================  OCTACKDIVCR  ====================================================== */
26487  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Pos        (0UL)          /*!< OCTACKDIV (Bit 0)                                     */
26488  #define R_SYSTEM_OCTACKDIVCR_OCTACKDIV_Msk        (0x7UL)        /*!< OCTACKDIV (Bitfield-Mask: 0x07)                       */
26489 /* =====================================================  SCISPICKDIVCR  ===================================================== */
26490  #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Pos    (0UL)          /*!< SCISPICKDIV (Bit 0)                                   */
26491  #define R_SYSTEM_SCISPICKDIVCR_SCISPICKDIV_Msk    (0x7UL)        /*!< SCISPICKDIV (Bitfield-Mask: 0x07)                     */
26492 /* =====================================================  CANFDCKDIVCR  ====================================================== */
26493  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Pos      (0UL)          /*!< CANFDCKDIV (Bit 0)                                    */
26494  #define R_SYSTEM_CANFDCKDIVCR_CANFDCKDIV_Msk      (0x7UL)        /*!< CANFDCKDIV (Bitfield-Mask: 0x07)                      */
26495 /* ======================================================  GPTCKDIVCR  ======================================================= */
26496  #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos          (0UL)          /*!< GPTCKDIV (Bit 0)                                      */
26497  #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk          (0x7UL)        /*!< GPTCKDIV (Bitfield-Mask: 0x07)                        */
26498 /* =====================================================  USB60CKDIVCR  ====================================================== */
26499  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos      (0UL)          /*!< USB60CKDIV (Bit 0)                                    */
26500  #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk      (0x7UL)        /*!< USB60CKDIV (Bitfield-Mask: 0x07)                      */
26501 /* ======================================================  CECCKDIVCR  ======================================================= */
26502  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos          (0UL)          /*!< CECCKDIV (Bit 0)                                      */
26503  #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk          (0x7UL)        /*!< CECCKDIV (Bitfield-Mask: 0x07)                        */
26504 /* ======================================================  I3CCKDIVCR  ======================================================= */
26505  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Pos          (0UL)          /*!< I3CCKDIV (Bit 0)                                      */
26506  #define R_SYSTEM_I3CCKDIVCR_I3CCKDIV_Msk          (0x7UL)        /*!< I3CCKDIV (Bitfield-Mask: 0x07)                        */
26507 /* ======================================================  IICCKDIVCR  ======================================================= */
26508  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos          (0UL)          /*!< IICCKDIV (Bit 0)                                      */
26509  #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk          (0x7UL)        /*!< IICCKDIV (Bitfield-Mask: 0x07)                        */
26510 /* ========================================================  USBCKCR  ======================================================== */
26511  #define R_SYSTEM_USBCKCR_USBCKSEL_Pos             (0UL)          /*!< USBCKSEL (Bit 0)                                      */
26512  #define R_SYSTEM_USBCKCR_USBCKSEL_Msk             (0x7UL)        /*!< USBCKSEL (Bitfield-Mask: 0x07)                        */
26513  #define R_SYSTEM_USBCKCR_USBCKSREQ_Pos            (6UL)          /*!< USBCKSREQ (Bit 6)                                     */
26514  #define R_SYSTEM_USBCKCR_USBCKSREQ_Msk            (0x40UL)       /*!< USBCKSREQ (Bitfield-Mask: 0x01)                       */
26515  #define R_SYSTEM_USBCKCR_USBCKSRDY_Pos            (7UL)          /*!< USBCKSRDY (Bit 7)                                     */
26516  #define R_SYSTEM_USBCKCR_USBCKSRDY_Msk            (0x80UL)       /*!< USBCKSRDY (Bitfield-Mask: 0x01)                       */
26517 /* =======================================================  OCTACKCR  ======================================================== */
26518  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Pos           (0UL)          /*!< OCTACKSEL (Bit 0)                                     */
26519  #define R_SYSTEM_OCTACKCR_OCTACKSEL_Msk           (0x7UL)        /*!< OCTACKSEL (Bitfield-Mask: 0x07)                       */
26520  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Pos          (6UL)          /*!< OCTACKSREQ (Bit 6)                                    */
26521  #define R_SYSTEM_OCTACKCR_OCTACKSREQ_Msk          (0x40UL)       /*!< OCTACKSREQ (Bitfield-Mask: 0x01)                      */
26522  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Pos          (7UL)          /*!< OCTACKSRDY (Bit 7)                                    */
26523  #define R_SYSTEM_OCTACKCR_OCTACKSRDY_Msk          (0x80UL)       /*!< OCTACKSRDY (Bitfield-Mask: 0x01)                      */
26524 /* ======================================================  SCISPICKCR  ======================================================= */
26525  #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Pos       (0UL)          /*!< SCISPICKSEL (Bit 0)                                   */
26526  #define R_SYSTEM_SCISPICKCR_SCISPICKSEL_Msk       (0x7UL)        /*!< SCISPICKSEL (Bitfield-Mask: 0x07)                     */
26527  #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Pos      (6UL)          /*!< SCISPICKSREQ (Bit 6)                                  */
26528  #define R_SYSTEM_SCISPICKCR_SCISPICKSREQ_Msk      (0x40UL)       /*!< SCISPICKSREQ (Bitfield-Mask: 0x01)                    */
26529  #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Pos      (7UL)          /*!< SCISPICKSRDY (Bit 7)                                  */
26530  #define R_SYSTEM_SCISPICKCR_SCISPICKSRDY_Msk      (0x80UL)       /*!< SCISPICKSRDY (Bitfield-Mask: 0x01)                    */
26531 /* =======================================================  CANFDCKCR  ======================================================= */
26532  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Pos         (0UL)          /*!< CANFDCKSEL (Bit 0)                                    */
26533  #define R_SYSTEM_CANFDCKCR_CANFDCKSEL_Msk         (0x7UL)        /*!< CANFDCKSEL (Bitfield-Mask: 0x07)                      */
26534  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Pos        (6UL)          /*!< CANFDCKSREQ (Bit 6)                                   */
26535  #define R_SYSTEM_CANFDCKCR_CANFDCKSREQ_Msk        (0x40UL)       /*!< CANFDCKSREQ (Bitfield-Mask: 0x01)                     */
26536  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Pos        (7UL)          /*!< CANFDCKSRDY (Bit 7)                                   */
26537  #define R_SYSTEM_CANFDCKCR_CANFDCKSRDY_Msk        (0x80UL)       /*!< CANFDCKSRDY (Bitfield-Mask: 0x01)                     */
26538 /* ========================================================  GPTCKCR  ======================================================== */
26539  #define R_SYSTEM_GPTCKCR_GPTCKSEL_Pos             (0UL)          /*!< GPTCKSEL (Bit 0)                                      */
26540  #define R_SYSTEM_GPTCKCR_GPTCKSEL_Msk             (0x7UL)        /*!< GPTCKSEL (Bitfield-Mask: 0x07)                        */
26541  #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Pos            (6UL)          /*!< GPTCKSREQ (Bit 6)                                     */
26542  #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk            (0x40UL)       /*!< GPTCKSREQ (Bitfield-Mask: 0x01)                       */
26543  #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos            (7UL)          /*!< GPTCKSRDY (Bit 7)                                     */
26544  #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk            (0x80UL)       /*!< GPTCKSRDY (Bitfield-Mask: 0x01)                       */
26545 /* =======================================================  USB60CKCR  ======================================================= */
26546  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos         (0UL)          /*!< USB60CKSEL (Bit 0)                                    */
26547  #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk         (0xfUL)        /*!< USB60CKSEL (Bitfield-Mask: 0x0f)                      */
26548  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos        (6UL)          /*!< USB60CKSREQ (Bit 6)                                   */
26549  #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk        (0x40UL)       /*!< USB60CKSREQ (Bitfield-Mask: 0x01)                     */
26550  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos        (7UL)          /*!< USB60CKSRDY (Bit 7)                                   */
26551  #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk        (0x80UL)       /*!< USB60CKSRDY (Bitfield-Mask: 0x01)                     */
26552 /* ========================================================  CECCKCR  ======================================================== */
26553  #define R_SYSTEM_CECCKCR_CECCKSEL_Pos             (0UL)          /*!< CECCKSEL (Bit 0)                                      */
26554  #define R_SYSTEM_CECCKCR_CECCKSEL_Msk             (0x7UL)        /*!< CECCKSEL (Bitfield-Mask: 0x07)                        */
26555  #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos            (6UL)          /*!< CECCKSREQ (Bit 6)                                     */
26556  #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk            (0x40UL)       /*!< CECCKSREQ (Bitfield-Mask: 0x01)                       */
26557  #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos            (7UL)          /*!< CECCKSRDY (Bit 7)                                     */
26558  #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk            (0x80UL)       /*!< CECCKSRDY (Bitfield-Mask: 0x01)                       */
26559 /* ========================================================  IICCKCR  ======================================================== */
26560  #define R_SYSTEM_IICCKCR_IICCKSEL_Pos             (0UL)          /*!< IICCKSEL (Bit 0)                                      */
26561  #define R_SYSTEM_IICCKCR_IICCKSEL_Msk             (0x7UL)        /*!< IICCKSEL (Bitfield-Mask: 0x07)                        */
26562  #define R_SYSTEM_IICCKCR_IICCKSREQ_Pos            (6UL)          /*!< IICCKSREQ (Bit 6)                                     */
26563  #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk            (0x40UL)       /*!< IICCKSREQ (Bitfield-Mask: 0x01)                       */
26564  #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos            (7UL)          /*!< IICCKSRDY (Bit 7)                                     */
26565  #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk            (0x80UL)       /*!< IICCKSRDY (Bitfield-Mask: 0x01)                       */
26566 /* ========================================================  I3CCKCR  ======================================================== */
26567  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos             (0UL)          /*!< I3CCKSEL (Bit 0)                                      */
26568  #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk             (0x7UL)        /*!< I3CCKSEL (Bitfield-Mask: 0x07)                        */
26569  #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos            (6UL)          /*!< I3CCKSREQ (Bit 6)                                     */
26570  #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk            (0x40UL)       /*!< I3CCKSREQ (Bitfield-Mask: 0x01)                       */
26571  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos            (7UL)          /*!< I3CCKSRDY (Bit 7)                                     */
26572  #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk            (0x80UL)       /*!< I3CCKSRDY (Bitfield-Mask: 0x01)                       */
26573 /* =======================================================  SNZREQCR1  ======================================================= */
26574  #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos          (0UL)          /*!< SNZREQEN0 (Bit 0)                                     */
26575  #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk          (0x1UL)        /*!< SNZREQEN0 (Bitfield-Mask: 0x01)                       */
26576  #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Pos          (1UL)          /*!< SNZREQEN1 (Bit 1)                                     */
26577  #define R_SYSTEM_SNZREQCR1_SNZREQEN1_Msk          (0x2UL)        /*!< SNZREQEN1 (Bitfield-Mask: 0x01)                       */
26578  #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Pos          (2UL)          /*!< SNZREQEN2 (Bit 2)                                     */
26579  #define R_SYSTEM_SNZREQCR1_SNZREQEN2_Msk          (0x4UL)        /*!< SNZREQEN2 (Bitfield-Mask: 0x01)                       */
26580 /* =======================================================  SNZEDCR1  ======================================================== */
26581  #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Pos           (0UL)          /*!< AGT3UNFED (Bit 0)                                     */
26582  #define R_SYSTEM_SNZEDCR1_AGT3UNFED_Msk           (0x1UL)        /*!< AGT3UNFED (Bitfield-Mask: 0x01)                       */
26583 /* ========================================================  CGFSAR  ========================================================= */
26584  #define R_SYSTEM_CGFSAR_NONSEC00_Pos              (0UL)          /*!< NONSEC00 (Bit 0)                                      */
26585  #define R_SYSTEM_CGFSAR_NONSEC00_Msk              (0x1UL)        /*!< NONSEC00 (Bitfield-Mask: 0x01)                        */
26586  #define R_SYSTEM_CGFSAR_NONSEC02_Pos              (2UL)          /*!< NONSEC02 (Bit 2)                                      */
26587  #define R_SYSTEM_CGFSAR_NONSEC02_Msk              (0x4UL)        /*!< NONSEC02 (Bitfield-Mask: 0x01)                        */
26588  #define R_SYSTEM_CGFSAR_NONSEC03_Pos              (3UL)          /*!< NONSEC03 (Bit 3)                                      */
26589  #define R_SYSTEM_CGFSAR_NONSEC03_Msk              (0x8UL)        /*!< NONSEC03 (Bitfield-Mask: 0x01)                        */
26590  #define R_SYSTEM_CGFSAR_NONSEC04_Pos              (4UL)          /*!< NONSEC04 (Bit 4)                                      */
26591  #define R_SYSTEM_CGFSAR_NONSEC04_Msk              (0x10UL)       /*!< NONSEC04 (Bitfield-Mask: 0x01)                        */
26592  #define R_SYSTEM_CGFSAR_NONSEC05_Pos              (5UL)          /*!< NONSEC05 (Bit 5)                                      */
26593  #define R_SYSTEM_CGFSAR_NONSEC05_Msk              (0x20UL)       /*!< NONSEC05 (Bitfield-Mask: 0x01)                        */
26594  #define R_SYSTEM_CGFSAR_NONSEC06_Pos              (6UL)          /*!< NONSEC06 (Bit 6)                                      */
26595  #define R_SYSTEM_CGFSAR_NONSEC06_Msk              (0x40UL)       /*!< NONSEC06 (Bitfield-Mask: 0x01)                        */
26596  #define R_SYSTEM_CGFSAR_NONSEC07_Pos              (7UL)          /*!< NONSEC07 (Bit 7)                                      */
26597  #define R_SYSTEM_CGFSAR_NONSEC07_Msk              (0x80UL)       /*!< NONSEC07 (Bitfield-Mask: 0x01)                        */
26598  #define R_SYSTEM_CGFSAR_NONSEC08_Pos              (8UL)          /*!< NONSEC08 (Bit 8)                                      */
26599  #define R_SYSTEM_CGFSAR_NONSEC08_Msk              (0x100UL)      /*!< NONSEC08 (Bitfield-Mask: 0x01)                        */
26600  #define R_SYSTEM_CGFSAR_NONSEC09_Pos              (9UL)          /*!< NONSEC09 (Bit 9)                                      */
26601  #define R_SYSTEM_CGFSAR_NONSEC09_Msk              (0x200UL)      /*!< NONSEC09 (Bitfield-Mask: 0x01)                        */
26602  #define R_SYSTEM_CGFSAR_NONSEC11_Pos              (11UL)         /*!< NONSEC11 (Bit 11)                                     */
26603  #define R_SYSTEM_CGFSAR_NONSEC11_Msk              (0x800UL)      /*!< NONSEC11 (Bitfield-Mask: 0x01)                        */
26604  #define R_SYSTEM_CGFSAR_NONSEC12_Pos              (12UL)         /*!< NONSEC12 (Bit 12)                                     */
26605  #define R_SYSTEM_CGFSAR_NONSEC12_Msk              (0x1000UL)     /*!< NONSEC12 (Bitfield-Mask: 0x01)                        */
26606  #define R_SYSTEM_CGFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
26607  #define R_SYSTEM_CGFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
26608  #define R_SYSTEM_CGFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
26609  #define R_SYSTEM_CGFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
26610 /* ========================================================  LPMSAR  ========================================================= */
26611  #define R_SYSTEM_LPMSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
26612  #define R_SYSTEM_LPMSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
26613  #define R_SYSTEM_LPMSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
26614  #define R_SYSTEM_LPMSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
26615  #define R_SYSTEM_LPMSAR_NONSEC4_Pos               (4UL)          /*!< NONSEC4 (Bit 4)                                       */
26616  #define R_SYSTEM_LPMSAR_NONSEC4_Msk               (0x10UL)       /*!< NONSEC4 (Bitfield-Mask: 0x01)                         */
26617  #define R_SYSTEM_LPMSAR_NONSEC8_Pos               (8UL)          /*!< NONSEC8 (Bit 8)                                       */
26618  #define R_SYSTEM_LPMSAR_NONSEC8_Msk               (0x100UL)      /*!< NONSEC8 (Bitfield-Mask: 0x01)                         */
26619  #define R_SYSTEM_LPMSAR_NONSEC9_Pos               (9UL)          /*!< NONSEC9 (Bit 9)                                       */
26620  #define R_SYSTEM_LPMSAR_NONSEC9_Msk               (0x200UL)      /*!< NONSEC9 (Bitfield-Mask: 0x01)                         */
26621 /* ========================================================  LVDSAR  ========================================================= */
26622  #define R_SYSTEM_LVDSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
26623  #define R_SYSTEM_LVDSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
26624  #define R_SYSTEM_LVDSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
26625  #define R_SYSTEM_LVDSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
26626 /* ========================================================  RSTSAR  ========================================================= */
26627  #define R_SYSTEM_RSTSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
26628  #define R_SYSTEM_RSTSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
26629  #define R_SYSTEM_RSTSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
26630  #define R_SYSTEM_RSTSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
26631  #define R_SYSTEM_RSTSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
26632  #define R_SYSTEM_RSTSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
26633 /* ========================================================  BBFSAR  ========================================================= */
26634  #define R_SYSTEM_BBFSAR_NONSEC0_Pos               (0UL)          /*!< NONSEC0 (Bit 0)                                       */
26635  #define R_SYSTEM_BBFSAR_NONSEC0_Msk               (0x1UL)        /*!< NONSEC0 (Bitfield-Mask: 0x01)                         */
26636  #define R_SYSTEM_BBFSAR_NONSEC1_Pos               (1UL)          /*!< NONSEC1 (Bit 1)                                       */
26637  #define R_SYSTEM_BBFSAR_NONSEC1_Msk               (0x2UL)        /*!< NONSEC1 (Bitfield-Mask: 0x01)                         */
26638  #define R_SYSTEM_BBFSAR_NONSEC2_Pos               (2UL)          /*!< NONSEC2 (Bit 2)                                       */
26639  #define R_SYSTEM_BBFSAR_NONSEC2_Msk               (0x4UL)        /*!< NONSEC2 (Bitfield-Mask: 0x01)                         */
26640  #define R_SYSTEM_BBFSAR_NONSEC16_Pos              (16UL)         /*!< NONSEC16 (Bit 16)                                     */
26641  #define R_SYSTEM_BBFSAR_NONSEC16_Msk              (0x10000UL)    /*!< NONSEC16 (Bitfield-Mask: 0x01)                        */
26642  #define R_SYSTEM_BBFSAR_NONSEC17_Pos              (17UL)         /*!< NONSEC17 (Bit 17)                                     */
26643  #define R_SYSTEM_BBFSAR_NONSEC17_Msk              (0x20000UL)    /*!< NONSEC17 (Bitfield-Mask: 0x01)                        */
26644  #define R_SYSTEM_BBFSAR_NONSEC18_Pos              (18UL)         /*!< NONSEC18 (Bit 18)                                     */
26645  #define R_SYSTEM_BBFSAR_NONSEC18_Msk              (0x40000UL)    /*!< NONSEC18 (Bitfield-Mask: 0x01)                        */
26646  #define R_SYSTEM_BBFSAR_NONSEC19_Pos              (19UL)         /*!< NONSEC19 (Bit 19)                                     */
26647  #define R_SYSTEM_BBFSAR_NONSEC19_Msk              (0x80000UL)    /*!< NONSEC19 (Bitfield-Mask: 0x01)                        */
26648  #define R_SYSTEM_BBFSAR_NONSEC20_Pos              (20UL)         /*!< NONSEC20 (Bit 20)                                     */
26649  #define R_SYSTEM_BBFSAR_NONSEC20_Msk              (0x100000UL)   /*!< NONSEC20 (Bitfield-Mask: 0x01)                        */
26650  #define R_SYSTEM_BBFSAR_NONSEC21_Pos              (21UL)         /*!< NONSEC21 (Bit 21)                                     */
26651  #define R_SYSTEM_BBFSAR_NONSEC21_Msk              (0x200000UL)   /*!< NONSEC21 (Bitfield-Mask: 0x01)                        */
26652  #define R_SYSTEM_BBFSAR_NONSEC22_Pos              (22UL)         /*!< NONSEC22 (Bit 22)                                     */
26653  #define R_SYSTEM_BBFSAR_NONSEC22_Msk              (0x400000UL)   /*!< NONSEC22 (Bitfield-Mask: 0x01)                        */
26654  #define R_SYSTEM_BBFSAR_NONSEC23_Pos              (23UL)         /*!< NONSEC23 (Bit 23)                                     */
26655  #define R_SYSTEM_BBFSAR_NONSEC23_Msk              (0x800000UL)   /*!< NONSEC23 (Bitfield-Mask: 0x01)                        */
26656 /* ========================================================  DPFSAR  ========================================================= */
26657  #define R_SYSTEM_DPFSAR_DPFSA0_Pos                (0UL)          /*!< DPFSA0 (Bit 0)                                        */
26658  #define R_SYSTEM_DPFSAR_DPFSA0_Msk                (0x1UL)        /*!< DPFSA0 (Bitfield-Mask: 0x01)                          */
26659  #define R_SYSTEM_DPFSAR_DPFSA1_Pos                (1UL)          /*!< DPFSA1 (Bit 1)                                        */
26660  #define R_SYSTEM_DPFSAR_DPFSA1_Msk                (0x2UL)        /*!< DPFSA1 (Bitfield-Mask: 0x01)                          */
26661  #define R_SYSTEM_DPFSAR_DPFSA2_Pos                (2UL)          /*!< DPFSA2 (Bit 2)                                        */
26662  #define R_SYSTEM_DPFSAR_DPFSA2_Msk                (0x4UL)        /*!< DPFSA2 (Bitfield-Mask: 0x01)                          */
26663  #define R_SYSTEM_DPFSAR_DPFSA3_Pos                (3UL)          /*!< DPFSA3 (Bit 3)                                        */
26664  #define R_SYSTEM_DPFSAR_DPFSA3_Msk                (0x8UL)        /*!< DPFSA3 (Bitfield-Mask: 0x01)                          */
26665  #define R_SYSTEM_DPFSAR_DPFSA4_Pos                (4UL)          /*!< DPFSA4 (Bit 4)                                        */
26666  #define R_SYSTEM_DPFSAR_DPFSA4_Msk                (0x10UL)       /*!< DPFSA4 (Bitfield-Mask: 0x01)                          */
26667  #define R_SYSTEM_DPFSAR_DPFSA5_Pos                (5UL)          /*!< DPFSA5 (Bit 5)                                        */
26668  #define R_SYSTEM_DPFSAR_DPFSA5_Msk                (0x20UL)       /*!< DPFSA5 (Bitfield-Mask: 0x01)                          */
26669  #define R_SYSTEM_DPFSAR_DPFSA6_Pos                (6UL)          /*!< DPFSA6 (Bit 6)                                        */
26670  #define R_SYSTEM_DPFSAR_DPFSA6_Msk                (0x40UL)       /*!< DPFSA6 (Bitfield-Mask: 0x01)                          */
26671  #define R_SYSTEM_DPFSAR_DPFSA7_Pos                (7UL)          /*!< DPFSA7 (Bit 7)                                        */
26672  #define R_SYSTEM_DPFSAR_DPFSA7_Msk                (0x80UL)       /*!< DPFSA7 (Bitfield-Mask: 0x01)                          */
26673  #define R_SYSTEM_DPFSAR_DPFSA8_Pos                (8UL)          /*!< DPFSA8 (Bit 8)                                        */
26674  #define R_SYSTEM_DPFSAR_DPFSA8_Msk                (0x100UL)      /*!< DPFSA8 (Bitfield-Mask: 0x01)                          */
26675  #define R_SYSTEM_DPFSAR_DPFSA9_Pos                (9UL)          /*!< DPFSA9 (Bit 9)                                        */
26676  #define R_SYSTEM_DPFSAR_DPFSA9_Msk                (0x200UL)      /*!< DPFSA9 (Bitfield-Mask: 0x01)                          */
26677  #define R_SYSTEM_DPFSAR_DPFSA10_Pos               (10UL)         /*!< DPFSA10 (Bit 10)                                      */
26678  #define R_SYSTEM_DPFSAR_DPFSA10_Msk               (0x400UL)      /*!< DPFSA10 (Bitfield-Mask: 0x01)                         */
26679  #define R_SYSTEM_DPFSAR_DPFSA11_Pos               (11UL)         /*!< DPFSA11 (Bit 11)                                      */
26680  #define R_SYSTEM_DPFSAR_DPFSA11_Msk               (0x800UL)      /*!< DPFSA11 (Bitfield-Mask: 0x01)                         */
26681  #define R_SYSTEM_DPFSAR_DPFSA12_Pos               (12UL)         /*!< DPFSA12 (Bit 12)                                      */
26682  #define R_SYSTEM_DPFSAR_DPFSA12_Msk               (0x1000UL)     /*!< DPFSA12 (Bitfield-Mask: 0x01)                         */
26683  #define R_SYSTEM_DPFSAR_DPFSA13_Pos               (13UL)         /*!< DPFSA13 (Bit 13)                                      */
26684  #define R_SYSTEM_DPFSAR_DPFSA13_Msk               (0x2000UL)     /*!< DPFSA13 (Bitfield-Mask: 0x01)                         */
26685  #define R_SYSTEM_DPFSAR_DPFSA14_Pos               (14UL)         /*!< DPFSA14 (Bit 14)                                      */
26686  #define R_SYSTEM_DPFSAR_DPFSA14_Msk               (0x4000UL)     /*!< DPFSA14 (Bitfield-Mask: 0x01)                         */
26687  #define R_SYSTEM_DPFSAR_DPFSA15_Pos               (15UL)         /*!< DPFSA15 (Bit 15)                                      */
26688  #define R_SYSTEM_DPFSAR_DPFSA15_Msk               (0x8000UL)     /*!< DPFSA15 (Bitfield-Mask: 0x01)                         */
26689  #define R_SYSTEM_DPFSAR_DPFSA16_Pos               (16UL)         /*!< DPFSA16 (Bit 16)                                      */
26690  #define R_SYSTEM_DPFSAR_DPFSA16_Msk               (0x10000UL)    /*!< DPFSA16 (Bitfield-Mask: 0x01)                         */
26691  #define R_SYSTEM_DPFSAR_DPFSA17_Pos               (17UL)         /*!< DPFSA17 (Bit 17)                                      */
26692  #define R_SYSTEM_DPFSAR_DPFSA17_Msk               (0x20000UL)    /*!< DPFSA17 (Bitfield-Mask: 0x01)                         */
26693  #define R_SYSTEM_DPFSAR_DPFSA18_Pos               (18UL)         /*!< DPFSA18 (Bit 18)                                      */
26694  #define R_SYSTEM_DPFSAR_DPFSA18_Msk               (0x40000UL)    /*!< DPFSA18 (Bitfield-Mask: 0x01)                         */
26695  #define R_SYSTEM_DPFSAR_DPFSA19_Pos               (19UL)         /*!< DPFSA19 (Bit 19)                                      */
26696  #define R_SYSTEM_DPFSAR_DPFSA19_Msk               (0x80000UL)    /*!< DPFSA19 (Bitfield-Mask: 0x01)                         */
26697  #define R_SYSTEM_DPFSAR_DPFSA20_Pos               (20UL)         /*!< DPFSA20 (Bit 20)                                      */
26698  #define R_SYSTEM_DPFSAR_DPFSA20_Msk               (0x100000UL)   /*!< DPFSA20 (Bitfield-Mask: 0x01)                         */
26699  #define R_SYSTEM_DPFSAR_DPFSA24_Pos               (24UL)         /*!< DPFSA24 (Bit 24)                                      */
26700  #define R_SYSTEM_DPFSAR_DPFSA24_Msk               (0x1000000UL)  /*!< DPFSA24 (Bitfield-Mask: 0x01)                         */
26701  #define R_SYSTEM_DPFSAR_DPFSA26_Pos               (26UL)         /*!< DPFSA26 (Bit 26)                                      */
26702  #define R_SYSTEM_DPFSAR_DPFSA26_Msk               (0x4000000UL)  /*!< DPFSA26 (Bitfield-Mask: 0x01)                         */
26703  #define R_SYSTEM_DPFSAR_DPFSA27_Pos               (27UL)         /*!< DPFSA27 (Bit 27)                                      */
26704  #define R_SYSTEM_DPFSAR_DPFSA27_Msk               (0x8000000UL)  /*!< DPFSA27 (Bitfield-Mask: 0x01)                         */
26705 /* ========================================================  DPSWCR  ========================================================= */
26706  #define R_SYSTEM_DPSWCR_WTSTS_Pos                 (0UL)          /*!< WTSTS (Bit 0)                                         */
26707  #define R_SYSTEM_DPSWCR_WTSTS_Msk                 (0x3fUL)       /*!< WTSTS (Bitfield-Mask: 0x3f)                           */
26708 /* ======================================================  VBATTMNSELR  ====================================================== */
26709  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Pos       (0UL)          /*!< VBATTMNSEL (Bit 0)                                    */
26710  #define R_SYSTEM_VBATTMNSELR_VBATTMNSEL_Msk       (0x1UL)        /*!< VBATTMNSEL (Bitfield-Mask: 0x01)                      */
26711 /* =======================================================  VBATTMONR  ======================================================= */
26712  #define R_SYSTEM_VBATTMONR_VBATTMON_Pos           (0UL)          /*!< VBATTMON (Bit 0)                                      */
26713  #define R_SYSTEM_VBATTMONR_VBATTMON_Msk           (0x1UL)        /*!< VBATTMON (Bitfield-Mask: 0x01)                        */
26714 /* ========================================================  VBTBER  ========================================================= */
26715  #define R_SYSTEM_VBTBER_VBAE_Pos                  (3UL)          /*!< VBAE (Bit 3)                                          */
26716  #define R_SYSTEM_VBTBER_VBAE_Msk                  (0x8UL)        /*!< VBAE (Bitfield-Mask: 0x01)                            */
26717 
26718 /* =========================================================================================================================== */
26719 /* ================                                         R_TSN_CAL                                         ================ */
26720 /* =========================================================================================================================== */
26721 
26722 /* =========================================================  TSCDR  ========================================================= */
26723  #define R_TSN_CAL_TSCDR_TSCDR_Pos    (0UL)          /*!< TSCDR (Bit 0)                                         */
26724  #define R_TSN_CAL_TSCDR_TSCDR_Msk    (0xffffffffUL) /*!< TSCDR (Bitfield-Mask: 0xffffffff)                     */
26725 
26726 /* =========================================================================================================================== */
26727 /* ================                                        R_TSN_CTRL                                         ================ */
26728 /* =========================================================================================================================== */
26729 
26730 /* =========================================================  TSCR  ========================================================== */
26731  #define R_TSN_CTRL_TSCR_TSEN_Pos    (7UL)    /*!< TSEN (Bit 7)                                          */
26732  #define R_TSN_CTRL_TSCR_TSEN_Msk    (0x80UL) /*!< TSEN (Bitfield-Mask: 0x01)                            */
26733  #define R_TSN_CTRL_TSCR_TSOE_Pos    (4UL)    /*!< TSOE (Bit 4)                                          */
26734  #define R_TSN_CTRL_TSCR_TSOE_Msk    (0x10UL) /*!< TSOE (Bitfield-Mask: 0x01)                            */
26735 
26736 /* =========================================================================================================================== */
26737 /* ================                                         R_USB_FS0                                         ================ */
26738 /* =========================================================================================================================== */
26739 
26740 /* ========================================================  SYSCFG  ========================================================= */
26741  #define R_USB_FS0_SYSCFG_SCKE_Pos         (10UL)     /*!< SCKE (Bit 10)                                         */
26742  #define R_USB_FS0_SYSCFG_SCKE_Msk         (0x400UL)  /*!< SCKE (Bitfield-Mask: 0x01)                            */
26743  #define R_USB_FS0_SYSCFG_CNEN_Pos         (8UL)      /*!< CNEN (Bit 8)                                          */
26744  #define R_USB_FS0_SYSCFG_CNEN_Msk         (0x100UL)  /*!< CNEN (Bitfield-Mask: 0x01)                            */
26745  #define R_USB_FS0_SYSCFG_DCFM_Pos         (6UL)      /*!< DCFM (Bit 6)                                          */
26746  #define R_USB_FS0_SYSCFG_DCFM_Msk         (0x40UL)   /*!< DCFM (Bitfield-Mask: 0x01)                            */
26747  #define R_USB_FS0_SYSCFG_DRPD_Pos         (5UL)      /*!< DRPD (Bit 5)                                          */
26748  #define R_USB_FS0_SYSCFG_DRPD_Msk         (0x20UL)   /*!< DRPD (Bitfield-Mask: 0x01)                            */
26749  #define R_USB_FS0_SYSCFG_DPRPU_Pos        (4UL)      /*!< DPRPU (Bit 4)                                         */
26750  #define R_USB_FS0_SYSCFG_DPRPU_Msk        (0x10UL)   /*!< DPRPU (Bitfield-Mask: 0x01)                           */
26751  #define R_USB_FS0_SYSCFG_DMRPU_Pos        (3UL)      /*!< DMRPU (Bit 3)                                         */
26752  #define R_USB_FS0_SYSCFG_DMRPU_Msk        (0x8UL)    /*!< DMRPU (Bitfield-Mask: 0x01)                           */
26753  #define R_USB_FS0_SYSCFG_USBE_Pos         (0UL)      /*!< USBE (Bit 0)                                          */
26754  #define R_USB_FS0_SYSCFG_USBE_Msk         (0x1UL)    /*!< USBE (Bitfield-Mask: 0x01)                            */
26755 /* ========================================================  BUSWAIT  ======================================================== */
26756  #define R_USB_FS0_BUSWAIT_BWAIT_Pos       (0UL)      /*!< BWAIT (Bit 0)                                         */
26757  #define R_USB_FS0_BUSWAIT_BWAIT_Msk       (0xfUL)    /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
26758 /* ========================================================  SYSSTS0  ======================================================== */
26759  #define R_USB_FS0_SYSSTS0_OVCMON_Pos      (14UL)     /*!< OVCMON (Bit 14)                                       */
26760  #define R_USB_FS0_SYSSTS0_OVCMON_Msk      (0xc000UL) /*!< OVCMON (Bitfield-Mask: 0x03)                          */
26761  #define R_USB_FS0_SYSSTS0_HTACT_Pos       (6UL)      /*!< HTACT (Bit 6)                                         */
26762  #define R_USB_FS0_SYSSTS0_HTACT_Msk       (0x40UL)   /*!< HTACT (Bitfield-Mask: 0x01)                           */
26763  #define R_USB_FS0_SYSSTS0_SOFEA_Pos       (5UL)      /*!< SOFEA (Bit 5)                                         */
26764  #define R_USB_FS0_SYSSTS0_SOFEA_Msk       (0x20UL)   /*!< SOFEA (Bitfield-Mask: 0x01)                           */
26765  #define R_USB_FS0_SYSSTS0_IDMON_Pos       (2UL)      /*!< IDMON (Bit 2)                                         */
26766  #define R_USB_FS0_SYSSTS0_IDMON_Msk       (0x4UL)    /*!< IDMON (Bitfield-Mask: 0x01)                           */
26767  #define R_USB_FS0_SYSSTS0_LNST_Pos        (0UL)      /*!< LNST (Bit 0)                                          */
26768  #define R_USB_FS0_SYSSTS0_LNST_Msk        (0x3UL)    /*!< LNST (Bitfield-Mask: 0x03)                            */
26769 /* ========================================================  PLLSTA  ========================================================= */
26770  #define R_USB_FS0_PLLSTA_PLLLOCK_Pos      (0UL)      /*!< PLLLOCK (Bit 0)                                       */
26771  #define R_USB_FS0_PLLSTA_PLLLOCK_Msk      (0x1UL)    /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
26772 /* =======================================================  DVSTCTR0  ======================================================== */
26773  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Pos    (11UL)     /*!< HNPBTOA (Bit 11)                                      */
26774  #define R_USB_FS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)  /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
26775  #define R_USB_FS0_DVSTCTR0_EXICEN_Pos     (10UL)     /*!< EXICEN (Bit 10)                                       */
26776  #define R_USB_FS0_DVSTCTR0_EXICEN_Msk     (0x400UL)  /*!< EXICEN (Bitfield-Mask: 0x01)                          */
26777  #define R_USB_FS0_DVSTCTR0_VBUSEN_Pos     (9UL)      /*!< VBUSEN (Bit 9)                                        */
26778  #define R_USB_FS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)  /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
26779  #define R_USB_FS0_DVSTCTR0_WKUP_Pos       (8UL)      /*!< WKUP (Bit 8)                                          */
26780  #define R_USB_FS0_DVSTCTR0_WKUP_Msk       (0x100UL)  /*!< WKUP (Bitfield-Mask: 0x01)                            */
26781  #define R_USB_FS0_DVSTCTR0_RWUPE_Pos      (7UL)      /*!< RWUPE (Bit 7)                                         */
26782  #define R_USB_FS0_DVSTCTR0_RWUPE_Msk      (0x80UL)   /*!< RWUPE (Bitfield-Mask: 0x01)                           */
26783  #define R_USB_FS0_DVSTCTR0_USBRST_Pos     (6UL)      /*!< USBRST (Bit 6)                                        */
26784  #define R_USB_FS0_DVSTCTR0_USBRST_Msk     (0x40UL)   /*!< USBRST (Bitfield-Mask: 0x01)                          */
26785  #define R_USB_FS0_DVSTCTR0_RESUME_Pos     (5UL)      /*!< RESUME (Bit 5)                                        */
26786  #define R_USB_FS0_DVSTCTR0_RESUME_Msk     (0x20UL)   /*!< RESUME (Bitfield-Mask: 0x01)                          */
26787  #define R_USB_FS0_DVSTCTR0_UACT_Pos       (4UL)      /*!< UACT (Bit 4)                                          */
26788  #define R_USB_FS0_DVSTCTR0_UACT_Msk       (0x10UL)   /*!< UACT (Bitfield-Mask: 0x01)                            */
26789  #define R_USB_FS0_DVSTCTR0_RHST_Pos       (0UL)      /*!< RHST (Bit 0)                                          */
26790  #define R_USB_FS0_DVSTCTR0_RHST_Msk       (0x7UL)    /*!< RHST (Bitfield-Mask: 0x07)                            */
26791 /* =======================================================  TESTMODE  ======================================================== */
26792  #define R_USB_FS0_TESTMODE_UTST_Pos       (0UL)      /*!< UTST (Bit 0)                                          */
26793  #define R_USB_FS0_TESTMODE_UTST_Msk       (0xfUL)    /*!< UTST (Bitfield-Mask: 0x0f)                            */
26794 /* ========================================================  CFIFOL  ========================================================= */
26795 /* ========================================================  CFIFOLL  ======================================================== */
26796 /* =========================================================  CFIFO  ========================================================= */
26797 /* ========================================================  CFIFOH  ========================================================= */
26798 /* ========================================================  CFIFOHH  ======================================================== */
26799 /* ========================================================  D0FIFOL  ======================================================== */
26800 /* =======================================================  D0FIFOLL  ======================================================== */
26801 /* ========================================================  D0FIFO  ========================================================= */
26802 /* ========================================================  D0FIFOH  ======================================================== */
26803 /* =======================================================  D0FIFOHH  ======================================================== */
26804 /* ========================================================  D1FIFOL  ======================================================== */
26805 /* =======================================================  D1FIFOLL  ======================================================== */
26806 /* ========================================================  D1FIFO  ========================================================= */
26807 /* ========================================================  D1FIFOH  ======================================================== */
26808 /* =======================================================  D1FIFOHH  ======================================================== */
26809 /* =======================================================  CFIFOSEL  ======================================================== */
26810  #define R_USB_FS0_CFIFOSEL_RCNT_Pos            (15UL)       /*!< RCNT (Bit 15)                                         */
26811  #define R_USB_FS0_CFIFOSEL_RCNT_Msk            (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
26812  #define R_USB_FS0_CFIFOSEL_REW_Pos             (14UL)       /*!< REW (Bit 14)                                          */
26813  #define R_USB_FS0_CFIFOSEL_REW_Msk             (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
26814  #define R_USB_FS0_CFIFOSEL_MBW_Pos             (10UL)       /*!< MBW (Bit 10)                                          */
26815  #define R_USB_FS0_CFIFOSEL_MBW_Msk             (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
26816  #define R_USB_FS0_CFIFOSEL_BIGEND_Pos          (8UL)        /*!< BIGEND (Bit 8)                                        */
26817  #define R_USB_FS0_CFIFOSEL_BIGEND_Msk          (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
26818  #define R_USB_FS0_CFIFOSEL_ISEL_Pos            (5UL)        /*!< ISEL (Bit 5)                                          */
26819  #define R_USB_FS0_CFIFOSEL_ISEL_Msk            (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
26820  #define R_USB_FS0_CFIFOSEL_CURPIPE_Pos         (0UL)        /*!< CURPIPE (Bit 0)                                       */
26821  #define R_USB_FS0_CFIFOSEL_CURPIPE_Msk         (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
26822 /* =======================================================  CFIFOCTR  ======================================================== */
26823  #define R_USB_FS0_CFIFOCTR_BVAL_Pos            (15UL)       /*!< BVAL (Bit 15)                                         */
26824  #define R_USB_FS0_CFIFOCTR_BVAL_Msk            (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
26825  #define R_USB_FS0_CFIFOCTR_BCLR_Pos            (14UL)       /*!< BCLR (Bit 14)                                         */
26826  #define R_USB_FS0_CFIFOCTR_BCLR_Msk            (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
26827  #define R_USB_FS0_CFIFOCTR_FRDY_Pos            (13UL)       /*!< FRDY (Bit 13)                                         */
26828  #define R_USB_FS0_CFIFOCTR_FRDY_Msk            (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
26829  #define R_USB_FS0_CFIFOCTR_DTLN_Pos            (0UL)        /*!< DTLN (Bit 0)                                          */
26830  #define R_USB_FS0_CFIFOCTR_DTLN_Msk            (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
26831 /* =======================================================  D0FIFOSEL  ======================================================= */
26832  #define R_USB_FS0_D0FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
26833  #define R_USB_FS0_D0FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
26834  #define R_USB_FS0_D0FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
26835  #define R_USB_FS0_D0FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
26836  #define R_USB_FS0_D0FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
26837  #define R_USB_FS0_D0FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
26838  #define R_USB_FS0_D0FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
26839  #define R_USB_FS0_D0FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
26840  #define R_USB_FS0_D0FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
26841  #define R_USB_FS0_D0FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
26842  #define R_USB_FS0_D0FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
26843  #define R_USB_FS0_D0FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
26844  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
26845  #define R_USB_FS0_D0FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
26846 /* =======================================================  D0FIFOCTR  ======================================================= */
26847  #define R_USB_FS0_D0FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
26848  #define R_USB_FS0_D0FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
26849  #define R_USB_FS0_D0FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
26850  #define R_USB_FS0_D0FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
26851  #define R_USB_FS0_D0FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
26852  #define R_USB_FS0_D0FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
26853  #define R_USB_FS0_D0FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
26854  #define R_USB_FS0_D0FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
26855 /* =======================================================  D1FIFOSEL  ======================================================= */
26856  #define R_USB_FS0_D1FIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
26857  #define R_USB_FS0_D1FIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
26858  #define R_USB_FS0_D1FIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
26859  #define R_USB_FS0_D1FIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
26860  #define R_USB_FS0_D1FIFOSEL_DCLRM_Pos          (13UL)       /*!< DCLRM (Bit 13)                                        */
26861  #define R_USB_FS0_D1FIFOSEL_DCLRM_Msk          (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
26862  #define R_USB_FS0_D1FIFOSEL_DREQE_Pos          (12UL)       /*!< DREQE (Bit 12)                                        */
26863  #define R_USB_FS0_D1FIFOSEL_DREQE_Msk          (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
26864  #define R_USB_FS0_D1FIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
26865  #define R_USB_FS0_D1FIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
26866  #define R_USB_FS0_D1FIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
26867  #define R_USB_FS0_D1FIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
26868  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
26869  #define R_USB_FS0_D1FIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
26870 /* =======================================================  D1FIFOCTR  ======================================================= */
26871  #define R_USB_FS0_D1FIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
26872  #define R_USB_FS0_D1FIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
26873  #define R_USB_FS0_D1FIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
26874  #define R_USB_FS0_D1FIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
26875  #define R_USB_FS0_D1FIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
26876  #define R_USB_FS0_D1FIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
26877  #define R_USB_FS0_D1FIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
26878  #define R_USB_FS0_D1FIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
26879 /* ========================================================  INTENB0  ======================================================== */
26880  #define R_USB_FS0_INTENB0_VBSE_Pos             (15UL)       /*!< VBSE (Bit 15)                                         */
26881  #define R_USB_FS0_INTENB0_VBSE_Msk             (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
26882  #define R_USB_FS0_INTENB0_RSME_Pos             (14UL)       /*!< RSME (Bit 14)                                         */
26883  #define R_USB_FS0_INTENB0_RSME_Msk             (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
26884  #define R_USB_FS0_INTENB0_SOFE_Pos             (13UL)       /*!< SOFE (Bit 13)                                         */
26885  #define R_USB_FS0_INTENB0_SOFE_Msk             (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
26886  #define R_USB_FS0_INTENB0_DVSE_Pos             (12UL)       /*!< DVSE (Bit 12)                                         */
26887  #define R_USB_FS0_INTENB0_DVSE_Msk             (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
26888  #define R_USB_FS0_INTENB0_CTRE_Pos             (11UL)       /*!< CTRE (Bit 11)                                         */
26889  #define R_USB_FS0_INTENB0_CTRE_Msk             (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
26890  #define R_USB_FS0_INTENB0_BEMPE_Pos            (10UL)       /*!< BEMPE (Bit 10)                                        */
26891  #define R_USB_FS0_INTENB0_BEMPE_Msk            (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
26892  #define R_USB_FS0_INTENB0_NRDYE_Pos            (9UL)        /*!< NRDYE (Bit 9)                                         */
26893  #define R_USB_FS0_INTENB0_NRDYE_Msk            (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
26894  #define R_USB_FS0_INTENB0_BRDYE_Pos            (8UL)        /*!< BRDYE (Bit 8)                                         */
26895  #define R_USB_FS0_INTENB0_BRDYE_Msk            (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
26896 /* ========================================================  INTENB1  ======================================================== */
26897  #define R_USB_FS0_INTENB1_OVRCRE_Pos           (15UL)       /*!< OVRCRE (Bit 15)                                       */
26898  #define R_USB_FS0_INTENB1_OVRCRE_Msk           (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
26899  #define R_USB_FS0_INTENB1_BCHGE_Pos            (14UL)       /*!< BCHGE (Bit 14)                                        */
26900  #define R_USB_FS0_INTENB1_BCHGE_Msk            (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
26901  #define R_USB_FS0_INTENB1_DTCHE_Pos            (12UL)       /*!< DTCHE (Bit 12)                                        */
26902  #define R_USB_FS0_INTENB1_DTCHE_Msk            (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
26903  #define R_USB_FS0_INTENB1_ATTCHE_Pos           (11UL)       /*!< ATTCHE (Bit 11)                                       */
26904  #define R_USB_FS0_INTENB1_ATTCHE_Msk           (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
26905  #define R_USB_FS0_INTENB1_EOFERRE_Pos          (6UL)        /*!< EOFERRE (Bit 6)                                       */
26906  #define R_USB_FS0_INTENB1_EOFERRE_Msk          (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
26907  #define R_USB_FS0_INTENB1_SIGNE_Pos            (5UL)        /*!< SIGNE (Bit 5)                                         */
26908  #define R_USB_FS0_INTENB1_SIGNE_Msk            (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
26909  #define R_USB_FS0_INTENB1_SACKE_Pos            (4UL)        /*!< SACKE (Bit 4)                                         */
26910  #define R_USB_FS0_INTENB1_SACKE_Msk            (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
26911  #define R_USB_FS0_INTENB1_PDDETINTE0_Pos       (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
26912  #define R_USB_FS0_INTENB1_PDDETINTE0_Msk       (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
26913 /* ========================================================  BRDYENB  ======================================================== */
26914  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Pos        (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
26915  #define R_USB_FS0_BRDYENB_PIPEBRDYE_Msk        (0x1UL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x01)                       */
26916 /* ========================================================  NRDYENB  ======================================================== */
26917  #define R_USB_FS0_NRDYENB_PIPENRDYE_Pos        (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
26918  #define R_USB_FS0_NRDYENB_PIPENRDYE_Msk        (0x1UL)      /*!< PIPENRDYE (Bitfield-Mask: 0x01)                       */
26919 /* ========================================================  BEMPENB  ======================================================== */
26920  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Pos        (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
26921  #define R_USB_FS0_BEMPENB_PIPEBEMPE_Msk        (0x1UL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x01)                       */
26922 /* ========================================================  SOFCFG  ========================================================= */
26923  #define R_USB_FS0_SOFCFG_TRNENSEL_Pos          (8UL)        /*!< TRNENSEL (Bit 8)                                      */
26924  #define R_USB_FS0_SOFCFG_TRNENSEL_Msk          (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
26925  #define R_USB_FS0_SOFCFG_BRDYM_Pos             (6UL)        /*!< BRDYM (Bit 6)                                         */
26926  #define R_USB_FS0_SOFCFG_BRDYM_Msk             (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
26927  #define R_USB_FS0_SOFCFG_INTL_Pos              (5UL)        /*!< INTL (Bit 5)                                          */
26928  #define R_USB_FS0_SOFCFG_INTL_Msk              (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
26929  #define R_USB_FS0_SOFCFG_EDGESTS_Pos           (4UL)        /*!< EDGESTS (Bit 4)                                       */
26930  #define R_USB_FS0_SOFCFG_EDGESTS_Msk           (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
26931 /* ========================================================  PHYSET  ========================================================= */
26932  #define R_USB_FS0_PHYSET_HSEB_Pos              (15UL)       /*!< HSEB (Bit 15)                                         */
26933  #define R_USB_FS0_PHYSET_HSEB_Msk              (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
26934  #define R_USB_FS0_PHYSET_REPSTART_Pos          (11UL)       /*!< REPSTART (Bit 11)                                     */
26935  #define R_USB_FS0_PHYSET_REPSTART_Msk          (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
26936  #define R_USB_FS0_PHYSET_REPSEL_Pos            (8UL)        /*!< REPSEL (Bit 8)                                        */
26937  #define R_USB_FS0_PHYSET_REPSEL_Msk            (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
26938  #define R_USB_FS0_PHYSET_CLKSEL_Pos            (4UL)        /*!< CLKSEL (Bit 4)                                        */
26939  #define R_USB_FS0_PHYSET_CLKSEL_Msk            (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
26940  #define R_USB_FS0_PHYSET_CDPEN_Pos             (3UL)        /*!< CDPEN (Bit 3)                                         */
26941  #define R_USB_FS0_PHYSET_CDPEN_Msk             (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
26942  #define R_USB_FS0_PHYSET_PLLRESET_Pos          (1UL)        /*!< PLLRESET (Bit 1)                                      */
26943  #define R_USB_FS0_PHYSET_PLLRESET_Msk          (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
26944  #define R_USB_FS0_PHYSET_DIRPD_Pos             (0UL)        /*!< DIRPD (Bit 0)                                         */
26945  #define R_USB_FS0_PHYSET_DIRPD_Msk             (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
26946 /* ========================================================  INTSTS0  ======================================================== */
26947  #define R_USB_FS0_INTSTS0_VBINT_Pos            (15UL)       /*!< VBINT (Bit 15)                                        */
26948  #define R_USB_FS0_INTSTS0_VBINT_Msk            (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
26949  #define R_USB_FS0_INTSTS0_RESM_Pos             (14UL)       /*!< RESM (Bit 14)                                         */
26950  #define R_USB_FS0_INTSTS0_RESM_Msk             (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
26951  #define R_USB_FS0_INTSTS0_SOFR_Pos             (13UL)       /*!< SOFR (Bit 13)                                         */
26952  #define R_USB_FS0_INTSTS0_SOFR_Msk             (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
26953  #define R_USB_FS0_INTSTS0_DVST_Pos             (12UL)       /*!< DVST (Bit 12)                                         */
26954  #define R_USB_FS0_INTSTS0_DVST_Msk             (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
26955  #define R_USB_FS0_INTSTS0_CTRT_Pos             (11UL)       /*!< CTRT (Bit 11)                                         */
26956  #define R_USB_FS0_INTSTS0_CTRT_Msk             (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
26957  #define R_USB_FS0_INTSTS0_BEMP_Pos             (10UL)       /*!< BEMP (Bit 10)                                         */
26958  #define R_USB_FS0_INTSTS0_BEMP_Msk             (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
26959  #define R_USB_FS0_INTSTS0_NRDY_Pos             (9UL)        /*!< NRDY (Bit 9)                                          */
26960  #define R_USB_FS0_INTSTS0_NRDY_Msk             (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
26961  #define R_USB_FS0_INTSTS0_BRDY_Pos             (8UL)        /*!< BRDY (Bit 8)                                          */
26962  #define R_USB_FS0_INTSTS0_BRDY_Msk             (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
26963  #define R_USB_FS0_INTSTS0_VBSTS_Pos            (7UL)        /*!< VBSTS (Bit 7)                                         */
26964  #define R_USB_FS0_INTSTS0_VBSTS_Msk            (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
26965  #define R_USB_FS0_INTSTS0_DVSQ_Pos             (4UL)        /*!< DVSQ (Bit 4)                                          */
26966  #define R_USB_FS0_INTSTS0_DVSQ_Msk             (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
26967  #define R_USB_FS0_INTSTS0_VALID_Pos            (3UL)        /*!< VALID (Bit 3)                                         */
26968  #define R_USB_FS0_INTSTS0_VALID_Msk            (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
26969  #define R_USB_FS0_INTSTS0_CTSQ_Pos             (0UL)        /*!< CTSQ (Bit 0)                                          */
26970  #define R_USB_FS0_INTSTS0_CTSQ_Msk             (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
26971 /* ========================================================  INTSTS1  ======================================================== */
26972  #define R_USB_FS0_INTSTS1_OVRCR_Pos            (15UL)       /*!< OVRCR (Bit 15)                                        */
26973  #define R_USB_FS0_INTSTS1_OVRCR_Msk            (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
26974  #define R_USB_FS0_INTSTS1_BCHG_Pos             (14UL)       /*!< BCHG (Bit 14)                                         */
26975  #define R_USB_FS0_INTSTS1_BCHG_Msk             (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
26976  #define R_USB_FS0_INTSTS1_DTCH_Pos             (12UL)       /*!< DTCH (Bit 12)                                         */
26977  #define R_USB_FS0_INTSTS1_DTCH_Msk             (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
26978  #define R_USB_FS0_INTSTS1_ATTCH_Pos            (11UL)       /*!< ATTCH (Bit 11)                                        */
26979  #define R_USB_FS0_INTSTS1_ATTCH_Msk            (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
26980  #define R_USB_FS0_INTSTS1_L1RSMEND_Pos         (9UL)        /*!< L1RSMEND (Bit 9)                                      */
26981  #define R_USB_FS0_INTSTS1_L1RSMEND_Msk         (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
26982  #define R_USB_FS0_INTSTS1_LPMEND_Pos           (8UL)        /*!< LPMEND (Bit 8)                                        */
26983  #define R_USB_FS0_INTSTS1_LPMEND_Msk           (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
26984  #define R_USB_FS0_INTSTS1_EOFERR_Pos           (6UL)        /*!< EOFERR (Bit 6)                                        */
26985  #define R_USB_FS0_INTSTS1_EOFERR_Msk           (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
26986  #define R_USB_FS0_INTSTS1_SIGN_Pos             (5UL)        /*!< SIGN (Bit 5)                                          */
26987  #define R_USB_FS0_INTSTS1_SIGN_Msk             (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
26988  #define R_USB_FS0_INTSTS1_SACK_Pos             (4UL)        /*!< SACK (Bit 4)                                          */
26989  #define R_USB_FS0_INTSTS1_SACK_Msk             (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
26990  #define R_USB_FS0_INTSTS1_PDDETINT0_Pos        (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
26991  #define R_USB_FS0_INTSTS1_PDDETINT0_Msk        (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
26992 /* ========================================================  BRDYSTS  ======================================================== */
26993  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Pos         (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
26994  #define R_USB_FS0_BRDYSTS_PIPEBRDY_Msk         (0x1UL)      /*!< PIPEBRDY (Bitfield-Mask: 0x01)                        */
26995 /* ========================================================  NRDYSTS  ======================================================== */
26996  #define R_USB_FS0_NRDYSTS_PIPENRDY_Pos         (0UL)        /*!< PIPENRDY (Bit 0)                                      */
26997  #define R_USB_FS0_NRDYSTS_PIPENRDY_Msk         (0x1UL)      /*!< PIPENRDY (Bitfield-Mask: 0x01)                        */
26998 /* ========================================================  BEMPSTS  ======================================================== */
26999  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Pos         (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
27000  #define R_USB_FS0_BEMPSTS_PIPEBEMP_Msk         (0x1UL)      /*!< PIPEBEMP (Bitfield-Mask: 0x01)                        */
27001 /* ========================================================  FRMNUM  ========================================================= */
27002  #define R_USB_FS0_FRMNUM_OVRN_Pos              (15UL)       /*!< OVRN (Bit 15)                                         */
27003  #define R_USB_FS0_FRMNUM_OVRN_Msk              (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
27004  #define R_USB_FS0_FRMNUM_CRCE_Pos              (14UL)       /*!< CRCE (Bit 14)                                         */
27005  #define R_USB_FS0_FRMNUM_CRCE_Msk              (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
27006  #define R_USB_FS0_FRMNUM_FRNM_Pos              (0UL)        /*!< FRNM (Bit 0)                                          */
27007  #define R_USB_FS0_FRMNUM_FRNM_Msk              (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
27008 /* ========================================================  UFRMNUM  ======================================================== */
27009  #define R_USB_FS0_UFRMNUM_DVCHG_Pos            (15UL)       /*!< DVCHG (Bit 15)                                        */
27010  #define R_USB_FS0_UFRMNUM_DVCHG_Msk            (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
27011  #define R_USB_FS0_UFRMNUM_UFRNM_Pos            (0UL)        /*!< UFRNM (Bit 0)                                         */
27012  #define R_USB_FS0_UFRMNUM_UFRNM_Msk            (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
27013 /* ========================================================  USBADDR  ======================================================== */
27014  #define R_USB_FS0_USBADDR_STSRECOV0_Pos        (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
27015  #define R_USB_FS0_USBADDR_STSRECOV0_Msk        (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
27016  #define R_USB_FS0_USBADDR_USBADDR_Pos          (0UL)        /*!< USBADDR (Bit 0)                                       */
27017  #define R_USB_FS0_USBADDR_USBADDR_Msk          (0x7fUL)     /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
27018 /* ========================================================  USBREQ  ========================================================= */
27019  #define R_USB_FS0_USBREQ_BREQUEST_Pos          (8UL)        /*!< BREQUEST (Bit 8)                                      */
27020  #define R_USB_FS0_USBREQ_BREQUEST_Msk          (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
27021  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Pos     (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
27022  #define R_USB_FS0_USBREQ_BMREQUESTTYPE_Msk     (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
27023 /* ========================================================  USBVAL  ========================================================= */
27024  #define R_USB_FS0_USBVAL_WVALUE_Pos            (0UL)        /*!< WVALUE (Bit 0)                                        */
27025  #define R_USB_FS0_USBVAL_WVALUE_Msk            (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
27026 /* ========================================================  USBINDX  ======================================================== */
27027  #define R_USB_FS0_USBINDX_WINDEX_Pos           (0UL)        /*!< WINDEX (Bit 0)                                        */
27028  #define R_USB_FS0_USBINDX_WINDEX_Msk           (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
27029 /* ========================================================  USBLENG  ======================================================== */
27030  #define R_USB_FS0_USBLENG_WLENGTH_Pos          (0UL)        /*!< WLENGTH (Bit 0)                                       */
27031  #define R_USB_FS0_USBLENG_WLENGTH_Msk          (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
27032 /* ========================================================  DCPCFG  ========================================================= */
27033  #define R_USB_FS0_DCPCFG_CNTMD_Pos             (8UL)        /*!< CNTMD (Bit 8)                                         */
27034  #define R_USB_FS0_DCPCFG_CNTMD_Msk             (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
27035  #define R_USB_FS0_DCPCFG_SHTNAK_Pos            (7UL)        /*!< SHTNAK (Bit 7)                                        */
27036  #define R_USB_FS0_DCPCFG_SHTNAK_Msk            (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
27037  #define R_USB_FS0_DCPCFG_DIR_Pos               (4UL)        /*!< DIR (Bit 4)                                           */
27038  #define R_USB_FS0_DCPCFG_DIR_Msk               (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
27039 /* ========================================================  DCPMAXP  ======================================================== */
27040  #define R_USB_FS0_DCPMAXP_DEVSEL_Pos           (12UL)       /*!< DEVSEL (Bit 12)                                       */
27041  #define R_USB_FS0_DCPMAXP_DEVSEL_Msk           (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
27042  #define R_USB_FS0_DCPMAXP_MXPS_Pos             (0UL)        /*!< MXPS (Bit 0)                                          */
27043  #define R_USB_FS0_DCPMAXP_MXPS_Msk             (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
27044 /* ========================================================  DCPCTR  ========================================================= */
27045  #define R_USB_FS0_DCPCTR_BSTS_Pos              (15UL)       /*!< BSTS (Bit 15)                                         */
27046  #define R_USB_FS0_DCPCTR_BSTS_Msk              (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
27047  #define R_USB_FS0_DCPCTR_SUREQ_Pos             (14UL)       /*!< SUREQ (Bit 14)                                        */
27048  #define R_USB_FS0_DCPCTR_SUREQ_Msk             (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
27049  #define R_USB_FS0_DCPCTR_SUREQCLR_Pos          (11UL)       /*!< SUREQCLR (Bit 11)                                     */
27050  #define R_USB_FS0_DCPCTR_SUREQCLR_Msk          (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
27051  #define R_USB_FS0_DCPCTR_SQCLR_Pos             (8UL)        /*!< SQCLR (Bit 8)                                         */
27052  #define R_USB_FS0_DCPCTR_SQCLR_Msk             (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
27053  #define R_USB_FS0_DCPCTR_SQSET_Pos             (7UL)        /*!< SQSET (Bit 7)                                         */
27054  #define R_USB_FS0_DCPCTR_SQSET_Msk             (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
27055  #define R_USB_FS0_DCPCTR_SQMON_Pos             (6UL)        /*!< SQMON (Bit 6)                                         */
27056  #define R_USB_FS0_DCPCTR_SQMON_Msk             (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
27057  #define R_USB_FS0_DCPCTR_PBUSY_Pos             (5UL)        /*!< PBUSY (Bit 5)                                         */
27058  #define R_USB_FS0_DCPCTR_PBUSY_Msk             (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
27059  #define R_USB_FS0_DCPCTR_CCPL_Pos              (2UL)        /*!< CCPL (Bit 2)                                          */
27060  #define R_USB_FS0_DCPCTR_CCPL_Msk              (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
27061  #define R_USB_FS0_DCPCTR_PID_Pos               (0UL)        /*!< PID (Bit 0)                                           */
27062  #define R_USB_FS0_DCPCTR_PID_Msk               (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
27063 /* ========================================================  PIPESEL  ======================================================== */
27064  #define R_USB_FS0_PIPESEL_PIPESEL_Pos          (0UL)        /*!< PIPESEL (Bit 0)                                       */
27065  #define R_USB_FS0_PIPESEL_PIPESEL_Msk          (0xfUL)      /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
27066 /* ========================================================  PIPECFG  ======================================================== */
27067  #define R_USB_FS0_PIPECFG_TYPE_Pos             (14UL)       /*!< TYPE (Bit 14)                                         */
27068  #define R_USB_FS0_PIPECFG_TYPE_Msk             (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
27069  #define R_USB_FS0_PIPECFG_BFRE_Pos             (10UL)       /*!< BFRE (Bit 10)                                         */
27070  #define R_USB_FS0_PIPECFG_BFRE_Msk             (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
27071  #define R_USB_FS0_PIPECFG_DBLB_Pos             (9UL)        /*!< DBLB (Bit 9)                                          */
27072  #define R_USB_FS0_PIPECFG_DBLB_Msk             (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
27073  #define R_USB_FS0_PIPECFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
27074  #define R_USB_FS0_PIPECFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
27075  #define R_USB_FS0_PIPECFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
27076  #define R_USB_FS0_PIPECFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
27077  #define R_USB_FS0_PIPECFG_EPNUM_Pos            (0UL)        /*!< EPNUM (Bit 0)                                         */
27078  #define R_USB_FS0_PIPECFG_EPNUM_Msk            (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
27079 /* =======================================================  PIPEMAXP  ======================================================== */
27080  #define R_USB_FS0_PIPEMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
27081  #define R_USB_FS0_PIPEMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
27082  #define R_USB_FS0_PIPEMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
27083  #define R_USB_FS0_PIPEMAXP_MXPS_Msk            (0x1ffUL)    /*!< MXPS (Bitfield-Mask: 0x1ff)                           */
27084 /* =======================================================  PIPEPERI  ======================================================== */
27085  #define R_USB_FS0_PIPEPERI_IFIS_Pos            (12UL)       /*!< IFIS (Bit 12)                                         */
27086  #define R_USB_FS0_PIPEPERI_IFIS_Msk            (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
27087  #define R_USB_FS0_PIPEPERI_IITV_Pos            (0UL)        /*!< IITV (Bit 0)                                          */
27088  #define R_USB_FS0_PIPEPERI_IITV_Msk            (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
27089 /* =======================================================  PIPE_CTR  ======================================================== */
27090  #define R_USB_FS0_PIPE_CTR_BSTS_Pos            (15UL)       /*!< BSTS (Bit 15)                                         */
27091  #define R_USB_FS0_PIPE_CTR_BSTS_Msk            (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
27092  #define R_USB_FS0_PIPE_CTR_INBUFM_Pos          (14UL)       /*!< INBUFM (Bit 14)                                       */
27093  #define R_USB_FS0_PIPE_CTR_INBUFM_Msk          (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
27094  #define R_USB_FS0_PIPE_CTR_CSCLR_Pos           (13UL)       /*!< CSCLR (Bit 13)                                        */
27095  #define R_USB_FS0_PIPE_CTR_CSCLR_Msk           (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
27096  #define R_USB_FS0_PIPE_CTR_CSSTS_Pos           (12UL)       /*!< CSSTS (Bit 12)                                        */
27097  #define R_USB_FS0_PIPE_CTR_CSSTS_Msk           (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
27098  #define R_USB_FS0_PIPE_CTR_ATREPM_Pos          (10UL)       /*!< ATREPM (Bit 10)                                       */
27099  #define R_USB_FS0_PIPE_CTR_ATREPM_Msk          (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
27100  #define R_USB_FS0_PIPE_CTR_ACLRM_Pos           (9UL)        /*!< ACLRM (Bit 9)                                         */
27101  #define R_USB_FS0_PIPE_CTR_ACLRM_Msk           (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
27102  #define R_USB_FS0_PIPE_CTR_SQCLR_Pos           (8UL)        /*!< SQCLR (Bit 8)                                         */
27103  #define R_USB_FS0_PIPE_CTR_SQCLR_Msk           (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
27104  #define R_USB_FS0_PIPE_CTR_SQSET_Pos           (7UL)        /*!< SQSET (Bit 7)                                         */
27105  #define R_USB_FS0_PIPE_CTR_SQSET_Msk           (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
27106  #define R_USB_FS0_PIPE_CTR_SQMON_Pos           (6UL)        /*!< SQMON (Bit 6)                                         */
27107  #define R_USB_FS0_PIPE_CTR_SQMON_Msk           (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
27108  #define R_USB_FS0_PIPE_CTR_PBUSY_Pos           (5UL)        /*!< PBUSY (Bit 5)                                         */
27109  #define R_USB_FS0_PIPE_CTR_PBUSY_Msk           (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
27110  #define R_USB_FS0_PIPE_CTR_PID_Pos             (0UL)        /*!< PID (Bit 0)                                           */
27111  #define R_USB_FS0_PIPE_CTR_PID_Msk             (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
27112 /* ========================================================  DEVADD  ========================================================= */
27113  #define R_USB_FS0_DEVADD_UPPHUB_Pos            (11UL)       /*!< UPPHUB (Bit 11)                                       */
27114  #define R_USB_FS0_DEVADD_UPPHUB_Msk            (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
27115  #define R_USB_FS0_DEVADD_HUBPORT_Pos           (8UL)        /*!< HUBPORT (Bit 8)                                       */
27116  #define R_USB_FS0_DEVADD_HUBPORT_Msk           (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
27117  #define R_USB_FS0_DEVADD_USBSPD_Pos            (6UL)        /*!< USBSPD (Bit 6)                                        */
27118  #define R_USB_FS0_DEVADD_USBSPD_Msk            (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
27119 /* ======================================================  USBBCCTRL0  ======================================================= */
27120  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Pos     (9UL)        /*!< PDDETSTS0 (Bit 9)                                     */
27121  #define R_USB_FS0_USBBCCTRL0_PDDETSTS0_Msk     (0x200UL)    /*!< PDDETSTS0 (Bitfield-Mask: 0x01)                       */
27122  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Pos    (8UL)        /*!< CHGDETSTS0 (Bit 8)                                    */
27123  #define R_USB_FS0_USBBCCTRL0_CHGDETSTS0_Msk    (0x100UL)    /*!< CHGDETSTS0 (Bitfield-Mask: 0x01)                      */
27124  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Pos      (7UL)        /*!< BATCHGE0 (Bit 7)                                      */
27125  #define R_USB_FS0_USBBCCTRL0_BATCHGE0_Msk      (0x80UL)     /*!< BATCHGE0 (Bitfield-Mask: 0x01)                        */
27126  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Pos      (5UL)        /*!< VDMSRCE0 (Bit 5)                                      */
27127  #define R_USB_FS0_USBBCCTRL0_VDMSRCE0_Msk      (0x20UL)     /*!< VDMSRCE0 (Bitfield-Mask: 0x01)                        */
27128  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Pos     (4UL)        /*!< IDPSINKE0 (Bit 4)                                     */
27129  #define R_USB_FS0_USBBCCTRL0_IDPSINKE0_Msk     (0x10UL)     /*!< IDPSINKE0 (Bitfield-Mask: 0x01)                       */
27130  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Pos      (3UL)        /*!< VDPSRCE0 (Bit 3)                                      */
27131  #define R_USB_FS0_USBBCCTRL0_VDPSRCE0_Msk      (0x8UL)      /*!< VDPSRCE0 (Bitfield-Mask: 0x01)                        */
27132  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Pos     (2UL)        /*!< IDMSINKE0 (Bit 2)                                     */
27133  #define R_USB_FS0_USBBCCTRL0_IDMSINKE0_Msk     (0x4UL)      /*!< IDMSINKE0 (Bitfield-Mask: 0x01)                       */
27134  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Pos      (1UL)        /*!< IDPSRCE0 (Bit 1)                                      */
27135  #define R_USB_FS0_USBBCCTRL0_IDPSRCE0_Msk      (0x2UL)      /*!< IDPSRCE0 (Bitfield-Mask: 0x01)                        */
27136  #define R_USB_FS0_USBBCCTRL0_RPDME0_Pos        (0UL)        /*!< RPDME0 (Bit 0)                                        */
27137  #define R_USB_FS0_USBBCCTRL0_RPDME0_Msk        (0x1UL)      /*!< RPDME0 (Bitfield-Mask: 0x01)                          */
27138 /* ========================================================  UCKSEL  ========================================================= */
27139  #define R_USB_FS0_UCKSEL_UCKSELC_Pos           (0UL)        /*!< UCKSELC (Bit 0)                                       */
27140  #define R_USB_FS0_UCKSEL_UCKSELC_Msk           (0x1UL)      /*!< UCKSELC (Bitfield-Mask: 0x01)                         */
27141 /* =========================================================  USBMC  ========================================================= */
27142  #define R_USB_FS0_USBMC_VDCEN_Pos              (7UL)        /*!< VDCEN (Bit 7)                                         */
27143  #define R_USB_FS0_USBMC_VDCEN_Msk              (0x80UL)     /*!< VDCEN (Bitfield-Mask: 0x01)                           */
27144  #define R_USB_FS0_USBMC_VDDUSBE_Pos            (0UL)        /*!< VDDUSBE (Bit 0)                                       */
27145  #define R_USB_FS0_USBMC_VDDUSBE_Msk            (0x1UL)      /*!< VDDUSBE (Bitfield-Mask: 0x01)                         */
27146 /* ========================================================  PHYSLEW  ======================================================== */
27147  #define R_USB_FS0_PHYSLEW_SLEWF01_Pos          (3UL)        /*!< SLEWF01 (Bit 3)                                       */
27148  #define R_USB_FS0_PHYSLEW_SLEWF01_Msk          (0x8UL)      /*!< SLEWF01 (Bitfield-Mask: 0x01)                         */
27149  #define R_USB_FS0_PHYSLEW_SLEWF00_Pos          (2UL)        /*!< SLEWF00 (Bit 2)                                       */
27150  #define R_USB_FS0_PHYSLEW_SLEWF00_Msk          (0x4UL)      /*!< SLEWF00 (Bitfield-Mask: 0x01)                         */
27151  #define R_USB_FS0_PHYSLEW_SLEWR01_Pos          (1UL)        /*!< SLEWR01 (Bit 1)                                       */
27152  #define R_USB_FS0_PHYSLEW_SLEWR01_Msk          (0x2UL)      /*!< SLEWR01 (Bitfield-Mask: 0x01)                         */
27153  #define R_USB_FS0_PHYSLEW_SLEWR00_Pos          (0UL)        /*!< SLEWR00 (Bit 0)                                       */
27154  #define R_USB_FS0_PHYSLEW_SLEWR00_Msk          (0x1UL)      /*!< SLEWR00 (Bitfield-Mask: 0x01)                         */
27155 /* ========================================================  LPCTRL  ========================================================= */
27156  #define R_USB_FS0_LPCTRL_HWUPM_Pos             (7UL)        /*!< HWUPM (Bit 7)                                         */
27157  #define R_USB_FS0_LPCTRL_HWUPM_Msk             (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
27158 /* =========================================================  LPSTS  ========================================================= */
27159  #define R_USB_FS0_LPSTS_SUSPENDM_Pos           (14UL)       /*!< SUSPENDM (Bit 14)                                     */
27160  #define R_USB_FS0_LPSTS_SUSPENDM_Msk           (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
27161 /* ========================================================  BCCTRL  ========================================================= */
27162  #define R_USB_FS0_BCCTRL_PDDETSTS_Pos          (9UL)        /*!< PDDETSTS (Bit 9)                                      */
27163  #define R_USB_FS0_BCCTRL_PDDETSTS_Msk          (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
27164  #define R_USB_FS0_BCCTRL_CHGDETSTS_Pos         (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
27165  #define R_USB_FS0_BCCTRL_CHGDETSTS_Msk         (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
27166  #define R_USB_FS0_BCCTRL_DCPMODE_Pos           (5UL)        /*!< DCPMODE (Bit 5)                                       */
27167  #define R_USB_FS0_BCCTRL_DCPMODE_Msk           (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
27168  #define R_USB_FS0_BCCTRL_VDMSRCE_Pos           (4UL)        /*!< VDMSRCE (Bit 4)                                       */
27169  #define R_USB_FS0_BCCTRL_VDMSRCE_Msk           (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
27170  #define R_USB_FS0_BCCTRL_IDPSINKE_Pos          (3UL)        /*!< IDPSINKE (Bit 3)                                      */
27171  #define R_USB_FS0_BCCTRL_IDPSINKE_Msk          (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
27172  #define R_USB_FS0_BCCTRL_VDPSRCE_Pos           (2UL)        /*!< VDPSRCE (Bit 2)                                       */
27173  #define R_USB_FS0_BCCTRL_VDPSRCE_Msk           (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
27174  #define R_USB_FS0_BCCTRL_IDMSINKE_Pos          (1UL)        /*!< IDMSINKE (Bit 1)                                      */
27175  #define R_USB_FS0_BCCTRL_IDMSINKE_Msk          (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
27176  #define R_USB_FS0_BCCTRL_IDPSRCE_Pos           (0UL)        /*!< IDPSRCE (Bit 0)                                       */
27177  #define R_USB_FS0_BCCTRL_IDPSRCE_Msk           (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
27178 /* =======================================================  PL1CTRL1  ======================================================== */
27179  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Pos         (14UL)       /*!< L1EXTMD (Bit 14)                                      */
27180  #define R_USB_FS0_PL1CTRL1_L1EXTMD_Msk         (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
27181  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Pos         (8UL)        /*!< HIRDTHR (Bit 8)                                       */
27182  #define R_USB_FS0_PL1CTRL1_HIRDTHR_Msk         (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
27183  #define R_USB_FS0_PL1CTRL1_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
27184  #define R_USB_FS0_PL1CTRL1_DVSQ_Msk            (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
27185  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Pos        (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
27186  #define R_USB_FS0_PL1CTRL1_L1NEGOMD_Msk        (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
27187  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Pos        (1UL)        /*!< L1RESPMD (Bit 1)                                      */
27188  #define R_USB_FS0_PL1CTRL1_L1RESPMD_Msk        (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
27189  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Pos        (0UL)        /*!< L1RESPEN (Bit 0)                                      */
27190  #define R_USB_FS0_PL1CTRL1_L1RESPEN_Msk        (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
27191 /* =======================================================  PL1CTRL2  ======================================================== */
27192  #define R_USB_FS0_PL1CTRL2_RWEMON_Pos          (12UL)       /*!< RWEMON (Bit 12)                                       */
27193  #define R_USB_FS0_PL1CTRL2_RWEMON_Msk          (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
27194  #define R_USB_FS0_PL1CTRL2_HIRDMON_Pos         (8UL)        /*!< HIRDMON (Bit 8)                                       */
27195  #define R_USB_FS0_PL1CTRL2_HIRDMON_Msk         (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
27196 /* =======================================================  HL1CTRL1  ======================================================== */
27197  #define R_USB_FS0_HL1CTRL1_L1STATUS_Pos        (1UL)        /*!< L1STATUS (Bit 1)                                      */
27198  #define R_USB_FS0_HL1CTRL1_L1STATUS_Msk        (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
27199  #define R_USB_FS0_HL1CTRL1_L1REQ_Pos           (0UL)        /*!< L1REQ (Bit 0)                                         */
27200  #define R_USB_FS0_HL1CTRL1_L1REQ_Msk           (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
27201 /* =======================================================  HL1CTRL2  ======================================================== */
27202  #define R_USB_FS0_HL1CTRL2_BESL_Pos            (15UL)       /*!< BESL (Bit 15)                                         */
27203  #define R_USB_FS0_HL1CTRL2_BESL_Msk            (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
27204  #define R_USB_FS0_HL1CTRL2_L1RWE_Pos           (12UL)       /*!< L1RWE (Bit 12)                                        */
27205  #define R_USB_FS0_HL1CTRL2_L1RWE_Msk           (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
27206  #define R_USB_FS0_HL1CTRL2_HIRD_Pos            (8UL)        /*!< HIRD (Bit 8)                                          */
27207  #define R_USB_FS0_HL1CTRL2_HIRD_Msk            (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
27208  #define R_USB_FS0_HL1CTRL2_L1ADDR_Pos          (0UL)        /*!< L1ADDR (Bit 0)                                        */
27209  #define R_USB_FS0_HL1CTRL2_L1ADDR_Msk          (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
27210 /* ========================================================  DPUSR0R  ======================================================== */
27211  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Pos         (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
27212  #define R_USB_FS0_DPUSR0R_DVBSTSHM_Msk         (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
27213  #define R_USB_FS0_DPUSR0R_DOVCBHM_Pos          (21UL)       /*!< DOVCBHM (Bit 21)                                      */
27214  #define R_USB_FS0_DPUSR0R_DOVCBHM_Msk          (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
27215  #define R_USB_FS0_DPUSR0R_DOVCAHM_Pos          (20UL)       /*!< DOVCAHM (Bit 20)                                      */
27216  #define R_USB_FS0_DPUSR0R_DOVCAHM_Msk          (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
27217 /* ========================================================  DPUSR1R  ======================================================== */
27218  #define R_USB_FS0_DPUSR1R_DVBSTSH_Pos          (23UL)       /*!< DVBSTSH (Bit 23)                                      */
27219  #define R_USB_FS0_DPUSR1R_DVBSTSH_Msk          (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
27220  #define R_USB_FS0_DPUSR1R_DOVCBH_Pos           (21UL)       /*!< DOVCBH (Bit 21)                                       */
27221  #define R_USB_FS0_DPUSR1R_DOVCBH_Msk           (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
27222  #define R_USB_FS0_DPUSR1R_DOVCAH_Pos           (20UL)       /*!< DOVCAH (Bit 20)                                       */
27223  #define R_USB_FS0_DPUSR1R_DOVCAH_Msk           (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
27224  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Pos         (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
27225  #define R_USB_FS0_DPUSR1R_DVBSTSHE_Msk         (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
27226  #define R_USB_FS0_DPUSR1R_DOVCBHE_Pos          (5UL)        /*!< DOVCBHE (Bit 5)                                       */
27227  #define R_USB_FS0_DPUSR1R_DOVCBHE_Msk          (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
27228  #define R_USB_FS0_DPUSR1R_DOVCAHE_Pos          (4UL)        /*!< DOVCAHE (Bit 4)                                       */
27229  #define R_USB_FS0_DPUSR1R_DOVCAHE_Msk          (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
27230 /* ========================================================  DPUSR2R  ======================================================== */
27231  #define R_USB_FS0_DPUSR2R_DMINTE_Pos           (9UL)        /*!< DMINTE (Bit 9)                                        */
27232  #define R_USB_FS0_DPUSR2R_DMINTE_Msk           (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
27233  #define R_USB_FS0_DPUSR2R_DPINTE_Pos           (8UL)        /*!< DPINTE (Bit 8)                                        */
27234  #define R_USB_FS0_DPUSR2R_DPINTE_Msk           (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
27235  #define R_USB_FS0_DPUSR2R_DMVAL_Pos            (5UL)        /*!< DMVAL (Bit 5)                                         */
27236  #define R_USB_FS0_DPUSR2R_DMVAL_Msk            (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
27237  #define R_USB_FS0_DPUSR2R_DPVAL_Pos            (4UL)        /*!< DPVAL (Bit 4)                                         */
27238  #define R_USB_FS0_DPUSR2R_DPVAL_Msk            (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
27239  #define R_USB_FS0_DPUSR2R_DMINT_Pos            (1UL)        /*!< DMINT (Bit 1)                                         */
27240  #define R_USB_FS0_DPUSR2R_DMINT_Msk            (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
27241  #define R_USB_FS0_DPUSR2R_DPINT_Pos            (0UL)        /*!< DPINT (Bit 0)                                         */
27242  #define R_USB_FS0_DPUSR2R_DPINT_Msk            (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
27243 /* ========================================================  DPUSRCR  ======================================================== */
27244  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Pos         (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
27245  #define R_USB_FS0_DPUSRCR_FIXPHYPD_Msk         (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
27246  #define R_USB_FS0_DPUSRCR_FIXPHY_Pos           (0UL)        /*!< FIXPHY (Bit 0)                                        */
27247  #define R_USB_FS0_DPUSRCR_FIXPHY_Msk           (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
27248 /* ======================================================  DPUSR0R_FS  ======================================================= */
27249  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Pos       (23UL)       /*!< DVBSTS0 (Bit 23)                                      */
27250  #define R_USB_FS0_DPUSR0R_FS_DVBSTS0_Msk       (0x800000UL) /*!< DVBSTS0 (Bitfield-Mask: 0x01)                         */
27251  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Pos        (21UL)       /*!< DOVCB0 (Bit 21)                                       */
27252  #define R_USB_FS0_DPUSR0R_FS_DOVCB0_Msk        (0x200000UL) /*!< DOVCB0 (Bitfield-Mask: 0x01)                          */
27253  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Pos        (20UL)       /*!< DOVCA0 (Bit 20)                                       */
27254  #define R_USB_FS0_DPUSR0R_FS_DOVCA0_Msk        (0x100000UL) /*!< DOVCA0 (Bitfield-Mask: 0x01)                          */
27255  #define R_USB_FS0_DPUSR0R_FS_DM0_Pos           (17UL)       /*!< DM0 (Bit 17)                                          */
27256  #define R_USB_FS0_DPUSR0R_FS_DM0_Msk           (0x20000UL)  /*!< DM0 (Bitfield-Mask: 0x01)                             */
27257  #define R_USB_FS0_DPUSR0R_FS_DP0_Pos           (16UL)       /*!< DP0 (Bit 16)                                          */
27258  #define R_USB_FS0_DPUSR0R_FS_DP0_Msk           (0x10000UL)  /*!< DP0 (Bitfield-Mask: 0x01)                             */
27259  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Pos       (4UL)        /*!< FIXPHY0 (Bit 4)                                       */
27260  #define R_USB_FS0_DPUSR0R_FS_FIXPHY0_Msk       (0x10UL)     /*!< FIXPHY0 (Bitfield-Mask: 0x01)                         */
27261  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Pos         (3UL)        /*!< DRPD0 (Bit 3)                                         */
27262  #define R_USB_FS0_DPUSR0R_FS_DRPD0_Msk         (0x8UL)      /*!< DRPD0 (Bitfield-Mask: 0x01)                           */
27263  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Pos         (1UL)        /*!< RPUE0 (Bit 1)                                         */
27264  #define R_USB_FS0_DPUSR0R_FS_RPUE0_Msk         (0x2UL)      /*!< RPUE0 (Bitfield-Mask: 0x01)                           */
27265  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Pos         (0UL)        /*!< SRPC0 (Bit 0)                                         */
27266  #define R_USB_FS0_DPUSR0R_FS_SRPC0_Msk         (0x1UL)      /*!< SRPC0 (Bitfield-Mask: 0x01)                           */
27267 /* ======================================================  DPUSR1R_FS  ======================================================= */
27268  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Pos       (23UL)       /*!< DVBINT0 (Bit 23)                                      */
27269  #define R_USB_FS0_DPUSR1R_FS_DVBINT0_Msk       (0x800000UL) /*!< DVBINT0 (Bitfield-Mask: 0x01)                         */
27270  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Pos      (21UL)       /*!< DOVRCRB0 (Bit 21)                                     */
27271  #define R_USB_FS0_DPUSR1R_FS_DOVRCRB0_Msk      (0x200000UL) /*!< DOVRCRB0 (Bitfield-Mask: 0x01)                        */
27272  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Pos      (20UL)       /*!< DOVRCRA0 (Bit 20)                                     */
27273  #define R_USB_FS0_DPUSR1R_FS_DOVRCRA0_Msk      (0x100000UL) /*!< DOVRCRA0 (Bitfield-Mask: 0x01)                        */
27274  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Pos        (17UL)       /*!< DMINT0 (Bit 17)                                       */
27275  #define R_USB_FS0_DPUSR1R_FS_DMINT0_Msk        (0x20000UL)  /*!< DMINT0 (Bitfield-Mask: 0x01)                          */
27276  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Pos        (16UL)       /*!< DPINT0 (Bit 16)                                       */
27277  #define R_USB_FS0_DPUSR1R_FS_DPINT0_Msk        (0x10000UL)  /*!< DPINT0 (Bitfield-Mask: 0x01)                          */
27278  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Pos        (7UL)        /*!< DVBSE0 (Bit 7)                                        */
27279  #define R_USB_FS0_DPUSR1R_FS_DVBSE0_Msk        (0x80UL)     /*!< DVBSE0 (Bitfield-Mask: 0x01)                          */
27280  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Pos     (5UL)        /*!< DOVRCRBE0 (Bit 5)                                     */
27281  #define R_USB_FS0_DPUSR1R_FS_DOVRCRBE0_Msk     (0x20UL)     /*!< DOVRCRBE0 (Bitfield-Mask: 0x01)                       */
27282  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Pos     (4UL)        /*!< DOVRCRAE0 (Bit 4)                                     */
27283  #define R_USB_FS0_DPUSR1R_FS_DOVRCRAE0_Msk     (0x10UL)     /*!< DOVRCRAE0 (Bitfield-Mask: 0x01)                       */
27284  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Pos       (1UL)        /*!< DMINTE0 (Bit 1)                                       */
27285  #define R_USB_FS0_DPUSR1R_FS_DMINTE0_Msk       (0x2UL)      /*!< DMINTE0 (Bitfield-Mask: 0x01)                         */
27286  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Pos       (0UL)        /*!< DPINTE0 (Bit 0)                                       */
27287  #define R_USB_FS0_DPUSR1R_FS_DPINTE0_Msk       (0x1UL)      /*!< DPINTE0 (Bitfield-Mask: 0x01)                         */
27288 
27289 /* =========================================================================================================================== */
27290 /* ================                                           R_WDT                                           ================ */
27291 /* =========================================================================================================================== */
27292 
27293 /* =========================================================  WDTRR  ========================================================= */
27294  #define R_WDT_WDTRR_WDTRR_Pos        (0UL)      /*!< WDTRR (Bit 0)                                         */
27295  #define R_WDT_WDTRR_WDTRR_Msk        (0xffUL)   /*!< WDTRR (Bitfield-Mask: 0xff)                           */
27296 /* =========================================================  WDTCR  ========================================================= */
27297  #define R_WDT_WDTCR_RPSS_Pos         (12UL)     /*!< RPSS (Bit 12)                                         */
27298  #define R_WDT_WDTCR_RPSS_Msk         (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
27299  #define R_WDT_WDTCR_RPES_Pos         (8UL)      /*!< RPES (Bit 8)                                          */
27300  #define R_WDT_WDTCR_RPES_Msk         (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
27301  #define R_WDT_WDTCR_CKS_Pos          (4UL)      /*!< CKS (Bit 4)                                           */
27302  #define R_WDT_WDTCR_CKS_Msk          (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
27303  #define R_WDT_WDTCR_TOPS_Pos         (0UL)      /*!< TOPS (Bit 0)                                          */
27304  #define R_WDT_WDTCR_TOPS_Msk         (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
27305 /* =========================================================  WDTSR  ========================================================= */
27306  #define R_WDT_WDTSR_REFEF_Pos        (15UL)     /*!< REFEF (Bit 15)                                        */
27307  #define R_WDT_WDTSR_REFEF_Msk        (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
27308  #define R_WDT_WDTSR_UNDFF_Pos        (14UL)     /*!< UNDFF (Bit 14)                                        */
27309  #define R_WDT_WDTSR_UNDFF_Msk        (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
27310  #define R_WDT_WDTSR_CNTVAL_Pos       (0UL)      /*!< CNTVAL (Bit 0)                                        */
27311  #define R_WDT_WDTSR_CNTVAL_Msk       (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
27312 /* ========================================================  WDTRCR  ========================================================= */
27313  #define R_WDT_WDTRCR_RSTIRQS_Pos     (7UL)      /*!< RSTIRQS (Bit 7)                                       */
27314  #define R_WDT_WDTRCR_RSTIRQS_Msk     (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
27315 /* =======================================================  WDTCSTPR  ======================================================== */
27316  #define R_WDT_WDTCSTPR_SLCSTP_Pos    (7UL)      /*!< SLCSTP (Bit 7)                                        */
27317  #define R_WDT_WDTCSTPR_SLCSTP_Msk    (0x80UL)   /*!< SLCSTP (Bitfield-Mask: 0x01)                          */
27318 
27319 /* =========================================================================================================================== */
27320 /* ================                                           R_TZF                                           ================ */
27321 /* =========================================================================================================================== */
27322 
27323 /* ========================================================  TZFOAD  ========================================================= */
27324  #define R_TZF_TZFOAD_OAD_Pos       (0UL)      /*!< OAD (Bit 0)                                           */
27325  #define R_TZF_TZFOAD_OAD_Msk       (0x1UL)    /*!< OAD (Bitfield-Mask: 0x01)                             */
27326  #define R_TZF_TZFOAD_KEY_Pos       (8UL)      /*!< KEY (Bit 8)                                           */
27327  #define R_TZF_TZFOAD_KEY_Msk       (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
27328 /* =========================================================  TZFPT  ========================================================= */
27329  #define R_TZF_TZFPT_PROTECT_Pos    (0UL)      /*!< PROTECT (Bit 0)                                       */
27330  #define R_TZF_TZFPT_PROTECT_Msk    (0x1UL)    /*!< PROTECT (Bitfield-Mask: 0x01)                         */
27331  #define R_TZF_TZFPT_KEY_Pos        (8UL)      /*!< KEY (Bit 8)                                           */
27332  #define R_TZF_TZFPT_KEY_Msk        (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff)                             */
27333 /* ========================================================  TZFSAR  ========================================================= */
27334  #define R_TZF_TZFSAR_TZFSA0_Pos    (0UL)      /*!< TZFSA0 (Bit 0)                                        */
27335  #define R_TZF_TZFSAR_TZFSA0_Msk    (0x1UL)    /*!< TZFSA0 (Bitfield-Mask: 0x01)                          */
27336 
27337 /* =========================================================================================================================== */
27338 /* ================                                          R_CACHE                                          ================ */
27339 /* =========================================================================================================================== */
27340 
27341 /* ========================================================  CCACTL  ========================================================= */
27342  #define R_CACHE_CCACTL_ENC_Pos     (0UL)    /*!< ENC (Bit 0)                                           */
27343  #define R_CACHE_CCACTL_ENC_Msk     (0x1UL)  /*!< ENC (Bitfield-Mask: 0x01)                             */
27344 /* ========================================================  CCAFCT  ========================================================= */
27345  #define R_CACHE_CCAFCT_FC_Pos      (0UL)    /*!< FC (Bit 0)                                            */
27346  #define R_CACHE_CCAFCT_FC_Msk      (0x1UL)  /*!< FC (Bitfield-Mask: 0x01)                              */
27347 /* ========================================================  CCALCF  ========================================================= */
27348  #define R_CACHE_CCALCF_CC_Pos      (0UL)    /*!< CC (Bit 0)                                            */
27349  #define R_CACHE_CCALCF_CC_Msk      (0x3UL)  /*!< CC (Bitfield-Mask: 0x03)                              */
27350 /* ========================================================  SCACTL  ========================================================= */
27351  #define R_CACHE_SCACTL_ENS_Pos     (0UL)    /*!< ENS (Bit 0)                                           */
27352  #define R_CACHE_SCACTL_ENS_Msk     (0x1UL)  /*!< ENS (Bitfield-Mask: 0x01)                             */
27353 /* ========================================================  SCAFCT  ========================================================= */
27354  #define R_CACHE_SCAFCT_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
27355  #define R_CACHE_SCAFCT_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
27356 /* ========================================================  SCALCF  ========================================================= */
27357  #define R_CACHE_SCALCF_CS_Pos      (0UL)    /*!< CS (Bit 0)                                            */
27358  #define R_CACHE_SCALCF_CS_Msk      (0x3UL)  /*!< CS (Bitfield-Mask: 0x03)                              */
27359 /* ========================================================  CAPOAD  ========================================================= */
27360  #define R_CACHE_CAPOAD_OAD_Pos     (0UL)    /*!< OAD (Bit 0)                                           */
27361  #define R_CACHE_CAPOAD_OAD_Msk     (0x1UL)  /*!< OAD (Bitfield-Mask: 0x01)                             */
27362 /* ========================================================  CAPRCR  ========================================================= */
27363  #define R_CACHE_CAPRCR_PRCR_Pos    (0UL)    /*!< PRCR (Bit 0)                                          */
27364  #define R_CACHE_CAPRCR_PRCR_Msk    (0x1UL)  /*!< PRCR (Bitfield-Mask: 0x01)                            */
27365  #define R_CACHE_CAPRCR_KW_Pos      (1UL)    /*!< KW (Bit 1)                                            */
27366  #define R_CACHE_CAPRCR_KW_Msk      (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f)                              */
27367 
27368 /* =========================================================================================================================== */
27369 /* ================                                          R_CPSCU                                          ================ */
27370 /* =========================================================================================================================== */
27371 
27372 /* =========================================================  CSAR  ========================================================== */
27373  #define R_CPSCU_CSAR_CACHESA_Pos            (0UL)          /*!< CACHESA (Bit 0)                                       */
27374  #define R_CPSCU_CSAR_CACHESA_Msk            (0x1UL)        /*!< CACHESA (Bitfield-Mask: 0x01)                         */
27375  #define R_CPSCU_CSAR_CACHELSA_Pos           (1UL)          /*!< CACHELSA (Bit 1)                                      */
27376  #define R_CPSCU_CSAR_CACHELSA_Msk           (0x2UL)        /*!< CACHELSA (Bitfield-Mask: 0x01)                        */
27377  #define R_CPSCU_CSAR_CACHEESA_Pos           (2UL)          /*!< CACHEESA (Bit 2)                                      */
27378  #define R_CPSCU_CSAR_CACHEESA_Msk           (0x4UL)        /*!< CACHEESA (Bitfield-Mask: 0x01)                        */
27379 /* ========================================================  SRAMSAR  ======================================================== */
27380  #define R_CPSCU_SRAMSAR_SRAMSA0_Pos         (0UL)          /*!< SRAMSA0 (Bit 0)                                       */
27381  #define R_CPSCU_SRAMSAR_SRAMSA0_Msk         (0x1UL)        /*!< SRAMSA0 (Bitfield-Mask: 0x01)                         */
27382  #define R_CPSCU_SRAMSAR_SRAMSA1_Pos         (1UL)          /*!< SRAMSA1 (Bit 1)                                       */
27383  #define R_CPSCU_SRAMSAR_SRAMSA1_Msk         (0x2UL)        /*!< SRAMSA1 (Bitfield-Mask: 0x01)                         */
27384  #define R_CPSCU_SRAMSAR_SRAMSA2_Pos         (2UL)          /*!< SRAMSA2 (Bit 2)                                       */
27385  #define R_CPSCU_SRAMSAR_SRAMSA2_Msk         (0x4UL)        /*!< SRAMSA2 (Bitfield-Mask: 0x01)                         */
27386 /* =======================================================  STBRAMSAR  ======================================================= */
27387  #define R_CPSCU_STBRAMSAR_NSBSTBR_Pos       (0UL)          /*!< NSBSTBR (Bit 0)                                       */
27388  #define R_CPSCU_STBRAMSAR_NSBSTBR_Msk       (0xfUL)        /*!< NSBSTBR (Bitfield-Mask: 0x0f)                         */
27389 /* ========================================================  DTCSAR  ========================================================= */
27390  #define R_CPSCU_DTCSAR_DTCSTSA_Pos          (0UL)          /*!< DTCSTSA (Bit 0)                                       */
27391  #define R_CPSCU_DTCSAR_DTCSTSA_Msk          (0x1UL)        /*!< DTCSTSA (Bitfield-Mask: 0x01)                         */
27392 /* ========================================================  DMACSAR  ======================================================== */
27393  #define R_CPSCU_DMACSAR_DMASTSA_Pos         (0UL)          /*!< DMASTSA (Bit 0)                                       */
27394  #define R_CPSCU_DMACSAR_DMASTSA_Msk         (0x1UL)        /*!< DMASTSA (Bitfield-Mask: 0x01)                         */
27395 /* ========================================================  ICUSARA  ======================================================== */
27396  #define R_CPSCU_ICUSARA_SAIRQCRn_Pos        (0UL)          /*!< SAIRQCRn (Bit 0)                                      */
27397  #define R_CPSCU_ICUSARA_SAIRQCRn_Msk        (0xffffUL)     /*!< SAIRQCRn (Bitfield-Mask: 0xffff)                      */
27398 /* ========================================================  ICUSARB  ======================================================== */
27399  #define R_CPSCU_ICUSARB_SANMI_Pos           (0UL)          /*!< SANMI (Bit 0)                                         */
27400  #define R_CPSCU_ICUSARB_SANMI_Msk           (0x1UL)        /*!< SANMI (Bitfield-Mask: 0x01)                           */
27401 /* ========================================================  ICUSARC  ======================================================== */
27402  #define R_CPSCU_ICUSARC_SADMACn_Pos         (0UL)          /*!< SADMACn (Bit 0)                                       */
27403  #define R_CPSCU_ICUSARC_SADMACn_Msk         (0xffUL)       /*!< SADMACn (Bitfield-Mask: 0xff)                         */
27404 /* ========================================================  ICUSARD  ======================================================== */
27405  #define R_CPSCU_ICUSARD_SASELSR0_Pos        (0UL)          /*!< SASELSR0 (Bit 0)                                      */
27406  #define R_CPSCU_ICUSARD_SASELSR0_Msk        (0x1UL)        /*!< SASELSR0 (Bitfield-Mask: 0x01)                        */
27407 /* ========================================================  ICUSARE  ======================================================== */
27408  #define R_CPSCU_ICUSARE_SAIWDTWUP_Pos       (16UL)         /*!< SAIWDTWUP (Bit 16)                                    */
27409  #define R_CPSCU_ICUSARE_SAIWDTWUP_Msk       (0x10000UL)    /*!< SAIWDTWUP (Bitfield-Mask: 0x01)                       */
27410  #define R_CPSCU_ICUSARE_SALVD1WUP_Pos       (18UL)         /*!< SALVD1WUP (Bit 18)                                    */
27411  #define R_CPSCU_ICUSARE_SALVD1WUP_Msk       (0x40000UL)    /*!< SALVD1WUP (Bitfield-Mask: 0x01)                       */
27412  #define R_CPSCU_ICUSARE_SALVD2WUP_Pos       (19UL)         /*!< SALVD2WUP (Bit 19)                                    */
27413  #define R_CPSCU_ICUSARE_SALVD2WUP_Msk       (0x80000UL)    /*!< SALVD2WUP (Bitfield-Mask: 0x01)                       */
27414  #define R_CPSCU_ICUSARE_SAVBATTWUP_Pos      (20UL)         /*!< SAVBATTWUP (Bit 20)                                   */
27415  #define R_CPSCU_ICUSARE_SAVBATTWUP_Msk      (0x100000UL)   /*!< SAVBATTWUP (Bitfield-Mask: 0x01)                      */
27416  #define R_CPSCU_ICUSARE_SARTCALMWUP_Pos     (24UL)         /*!< SARTCALMWUP (Bit 24)                                  */
27417  #define R_CPSCU_ICUSARE_SARTCALMWUP_Msk     (0x1000000UL)  /*!< SARTCALMWUP (Bitfield-Mask: 0x01)                     */
27418  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Pos     (25UL)         /*!< SARTCPRDWUP (Bit 25)                                  */
27419  #define R_CPSCU_ICUSARE_SARTCPRDWUP_Msk     (0x2000000UL)  /*!< SARTCPRDWUP (Bitfield-Mask: 0x01)                     */
27420  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Pos     (27UL)         /*!< SAUSBFS0WUP (Bit 27)                                  */
27421  #define R_CPSCU_ICUSARE_SAUSBFS0WUP_Msk     (0x8000000UL)  /*!< SAUSBFS0WUP (Bitfield-Mask: 0x01)                     */
27422  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Pos     (28UL)         /*!< SAAGT1UDWUP (Bit 28)                                  */
27423  #define R_CPSCU_ICUSARE_SAAGT1UDWUP_Msk     (0x10000000UL) /*!< SAAGT1UDWUP (Bitfield-Mask: 0x01)                     */
27424  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Pos     (29UL)         /*!< SAAGT1CAWUP (Bit 29)                                  */
27425  #define R_CPSCU_ICUSARE_SAAGT1CAWUP_Msk     (0x20000000UL) /*!< SAAGT1CAWUP (Bitfield-Mask: 0x01)                     */
27426  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Pos     (30UL)         /*!< SAAGT1CBWUP (Bit 30)                                  */
27427  #define R_CPSCU_ICUSARE_SAAGT1CBWUP_Msk     (0x40000000UL) /*!< SAAGT1CBWUP (Bitfield-Mask: 0x01)                     */
27428  #define R_CPSCU_ICUSARE_SAIIC0WUP_Pos       (31UL)         /*!< SAIIC0WUP (Bit 31)                                    */
27429  #define R_CPSCU_ICUSARE_SAIIC0WUP_Msk       (0x80000000UL) /*!< SAIIC0WUP (Bitfield-Mask: 0x01)                       */
27430 /* ========================================================  ICUSARF  ======================================================== */
27431  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Pos     (0UL)          /*!< SAAGT3UDWUP (Bit 0)                                   */
27432  #define R_CPSCU_ICUSARF_SAAGT3UDWUP_Msk     (0x1UL)        /*!< SAAGT3UDWUP (Bitfield-Mask: 0x01)                     */
27433  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Pos     (1UL)          /*!< SAAGT3CAWUP (Bit 1)                                   */
27434  #define R_CPSCU_ICUSARF_SAAGT3CAWUP_Msk     (0x2UL)        /*!< SAAGT3CAWUP (Bitfield-Mask: 0x01)                     */
27435  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Pos     (2UL)          /*!< SAAGT3CBWUP (Bit 2)                                   */
27436  #define R_CPSCU_ICUSARF_SAAGT3CBWUP_Msk     (0x4UL)        /*!< SAAGT3CBWUP (Bitfield-Mask: 0x01)                     */
27437  #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Pos    (3UL)          /*!< SACOMPHS0WUP (Bit 3)                                  */
27438  #define R_CPSCU_ICUSARF_SACOMPHS0WUP_Msk    (0x8UL)        /*!< SACOMPHS0WUP (Bitfield-Mask: 0x01)                    */
27439  #define R_CPSCU_ICUSARF_SAULP0UWUP_Pos      (8UL)          /*!< SAULP0UWUP (Bit 8)                                    */
27440  #define R_CPSCU_ICUSARF_SAULP0UWUP_Msk      (0x100UL)      /*!< SAULP0UWUP (Bitfield-Mask: 0x01)                      */
27441  #define R_CPSCU_ICUSARF_SAULP0AWUP_Pos      (9UL)          /*!< SAULP0AWUP (Bit 9)                                    */
27442  #define R_CPSCU_ICUSARF_SAULP0AWUP_Msk      (0x200UL)      /*!< SAULP0AWUP (Bitfield-Mask: 0x01)                      */
27443  #define R_CPSCU_ICUSARF_SAULP0BWUP_Pos      (10UL)         /*!< SAULP0BWUP (Bit 10)                                   */
27444  #define R_CPSCU_ICUSARF_SAULP0BWUP_Msk      (0x400UL)      /*!< SAULP0BWUP (Bitfield-Mask: 0x01)                      */
27445  #define R_CPSCU_ICUSARF_SAI3CWUP_Pos        (11UL)         /*!< SAI3CWUP (Bit 11)                                     */
27446  #define R_CPSCU_ICUSARF_SAI3CWUP_Msk        (0x800UL)      /*!< SAI3CWUP (Bitfield-Mask: 0x01)                        */
27447  #define R_CPSCU_ICUSARF_SAULP1UWUP_Pos      (12UL)         /*!< SAULP1UWUP (Bit 12)                                   */
27448  #define R_CPSCU_ICUSARF_SAULP1UWUP_Msk      (0x1000UL)     /*!< SAULP1UWUP (Bitfield-Mask: 0x01)                      */
27449  #define R_CPSCU_ICUSARF_SAULP1AWUP_Pos      (13UL)         /*!< SAULP1AWUP (Bit 13)                                   */
27450  #define R_CPSCU_ICUSARF_SAULP1AWUP_Msk      (0x2000UL)     /*!< SAULP1AWUP (Bitfield-Mask: 0x01)                      */
27451  #define R_CPSCU_ICUSARF_SAULP1BWUP_Pos      (14UL)         /*!< SAULP1BWUP (Bit 14)                                   */
27452  #define R_CPSCU_ICUSARF_SAULP1BWUP_Msk      (0x4000UL)     /*!< SAULP1BWUP (Bitfield-Mask: 0x01)                      */
27453 /* ========================================================  ICUSARG  ======================================================== */
27454  #define R_CPSCU_ICUSARG_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
27455  #define R_CPSCU_ICUSARG_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
27456 /* ========================================================  ICUSARH  ======================================================== */
27457  #define R_CPSCU_ICUSARH_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
27458  #define R_CPSCU_ICUSARH_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
27459 /* ========================================================  ICUSARI  ======================================================== */
27460  #define R_CPSCU_ICUSARI_SAIELSRn_Pos        (0UL)          /*!< SAIELSRn (Bit 0)                                      */
27461  #define R_CPSCU_ICUSARI_SAIELSRn_Msk        (0xffffffffUL) /*!< SAIELSRn (Bitfield-Mask: 0xffffffff)                  */
27462 /* ========================================================  BUSSARA  ======================================================== */
27463  #define R_CPSCU_BUSSARA_BUSSA0_Pos          (0UL)          /*!< BUSSA0 (Bit 0)                                        */
27464  #define R_CPSCU_BUSSARA_BUSSA0_Msk          (0x1UL)        /*!< BUSSA0 (Bitfield-Mask: 0x01)                          */
27465 /* ========================================================  BUSSARB  ======================================================== */
27466  #define R_CPSCU_BUSSARB_BUSSB0_Pos          (0UL)          /*!< BUSSB0 (Bit 0)                                        */
27467  #define R_CPSCU_BUSSARB_BUSSB0_Msk          (0x1UL)        /*!< BUSSB0 (Bitfield-Mask: 0x01)                          */
27468 /* =======================================================  MMPUSARA  ======================================================== */
27469  #define R_CPSCU_MMPUSARA_MMPUAnSA_Pos       (0UL)          /*!< MMPUAnSA (Bit 0)                                      */
27470  #define R_CPSCU_MMPUSARA_MMPUAnSA_Msk       (0xffUL)       /*!< MMPUAnSA (Bitfield-Mask: 0xff)                        */
27471 /* =======================================================  MMPUSARB  ======================================================== */
27472  #define R_CPSCU_MMPUSARB_MMPUB0SA_Pos       (0UL)          /*!< MMPUB0SA (Bit 0)                                      */
27473  #define R_CPSCU_MMPUSARB_MMPUB0SA_Msk       (0x1UL)        /*!< MMPUB0SA (Bitfield-Mask: 0x01)                        */
27474 /* =======================================================  DMACCHSAR  ======================================================= */
27475  #define R_CPSCU_DMACCHSAR_DMACCHSARn_Pos    (0UL)          /*!< DMACCHSARn (Bit 0)                                    */
27476  #define R_CPSCU_DMACCHSAR_DMACCHSARn_Msk    (0xffUL)       /*!< DMACCHSARn (Bitfield-Mask: 0xff)                      */
27477 /* ========================================================  CPUDSAR  ======================================================== */
27478  #define R_CPSCU_CPUDSAR_CPUDSA0_Pos         (0UL)          /*!< CPUDSA0 (Bit 0)                                       */
27479  #define R_CPSCU_CPUDSAR_CPUDSA0_Msk         (0x1UL)        /*!< CPUDSA0 (Bitfield-Mask: 0x01)                         */
27480 /* ======================================================  SRAMSABAR0  ======================================================= */
27481  #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Pos    (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
27482  #define R_CPSCU_SRAMSABAR0_SRAMSABAR_Msk    (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
27483 /* ======================================================  SRAMSABAR1  ======================================================= */
27484  #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Pos    (13UL)         /*!< SRAMSABAR (Bit 13)                                    */
27485  #define R_CPSCU_SRAMSABAR1_SRAMSABAR_Msk    (0x1fe000UL)   /*!< SRAMSABAR (Bitfield-Mask: 0xff)                       */
27486 /* ========================================================  TEVTRCR  ======================================================== */
27487  #define R_CPSCU_TEVTRCR_TEVTE_Pos           (0UL)          /*!< TEVTE (Bit 0)                                         */
27488  #define R_CPSCU_TEVTRCR_TEVTE_Msk           (0x1UL)        /*!< TEVTE (Bitfield-Mask: 0x01)                           */
27489 
27490 /* =========================================================================================================================== */
27491 /* ================                                           R_CEC                                           ================ */
27492 /* =========================================================================================================================== */
27493 
27494 /* =========================================================  CADR  ========================================================== */
27495  #define R_CEC_CADR_ADR00_Pos            (0UL)      /*!< ADR00 (Bit 0)                                         */
27496  #define R_CEC_CADR_ADR00_Msk            (0x1UL)    /*!< ADR00 (Bitfield-Mask: 0x01)                           */
27497  #define R_CEC_CADR_ADR01_Pos            (1UL)      /*!< ADR01 (Bit 1)                                         */
27498  #define R_CEC_CADR_ADR01_Msk            (0x2UL)    /*!< ADR01 (Bitfield-Mask: 0x01)                           */
27499  #define R_CEC_CADR_ADR02_Pos            (2UL)      /*!< ADR02 (Bit 2)                                         */
27500  #define R_CEC_CADR_ADR02_Msk            (0x4UL)    /*!< ADR02 (Bitfield-Mask: 0x01)                           */
27501  #define R_CEC_CADR_ADR03_Pos            (3UL)      /*!< ADR03 (Bit 3)                                         */
27502  #define R_CEC_CADR_ADR03_Msk            (0x8UL)    /*!< ADR03 (Bitfield-Mask: 0x01)                           */
27503  #define R_CEC_CADR_ADR04_Pos            (4UL)      /*!< ADR04 (Bit 4)                                         */
27504  #define R_CEC_CADR_ADR04_Msk            (0x10UL)   /*!< ADR04 (Bitfield-Mask: 0x01)                           */
27505  #define R_CEC_CADR_ADR05_Pos            (5UL)      /*!< ADR05 (Bit 5)                                         */
27506  #define R_CEC_CADR_ADR05_Msk            (0x20UL)   /*!< ADR05 (Bitfield-Mask: 0x01)                           */
27507  #define R_CEC_CADR_ADR06_Pos            (6UL)      /*!< ADR06 (Bit 6)                                         */
27508  #define R_CEC_CADR_ADR06_Msk            (0x40UL)   /*!< ADR06 (Bitfield-Mask: 0x01)                           */
27509  #define R_CEC_CADR_ADR07_Pos            (7UL)      /*!< ADR07 (Bit 7)                                         */
27510  #define R_CEC_CADR_ADR07_Msk            (0x80UL)   /*!< ADR07 (Bitfield-Mask: 0x01)                           */
27511  #define R_CEC_CADR_ADR08_Pos            (8UL)      /*!< ADR08 (Bit 8)                                         */
27512  #define R_CEC_CADR_ADR08_Msk            (0x100UL)  /*!< ADR08 (Bitfield-Mask: 0x01)                           */
27513  #define R_CEC_CADR_ADR09_Pos            (9UL)      /*!< ADR09 (Bit 9)                                         */
27514  #define R_CEC_CADR_ADR09_Msk            (0x200UL)  /*!< ADR09 (Bitfield-Mask: 0x01)                           */
27515  #define R_CEC_CADR_ADR10_Pos            (10UL)     /*!< ADR10 (Bit 10)                                        */
27516  #define R_CEC_CADR_ADR10_Msk            (0x400UL)  /*!< ADR10 (Bitfield-Mask: 0x01)                           */
27517  #define R_CEC_CADR_ADR11_Pos            (11UL)     /*!< ADR11 (Bit 11)                                        */
27518  #define R_CEC_CADR_ADR11_Msk            (0x800UL)  /*!< ADR11 (Bitfield-Mask: 0x01)                           */
27519  #define R_CEC_CADR_ADR12_Pos            (12UL)     /*!< ADR12 (Bit 12)                                        */
27520  #define R_CEC_CADR_ADR12_Msk            (0x1000UL) /*!< ADR12 (Bitfield-Mask: 0x01)                           */
27521  #define R_CEC_CADR_ADR13_Pos            (13UL)     /*!< ADR13 (Bit 13)                                        */
27522  #define R_CEC_CADR_ADR13_Msk            (0x2000UL) /*!< ADR13 (Bitfield-Mask: 0x01)                           */
27523  #define R_CEC_CADR_ADR14_Pos            (14UL)     /*!< ADR14 (Bit 14)                                        */
27524  #define R_CEC_CADR_ADR14_Msk            (0x4000UL) /*!< ADR14 (Bitfield-Mask: 0x01)                           */
27525 /* ========================================================  CECCTL1  ======================================================== */
27526  #define R_CEC_CECCTL1_SFT_Pos           (0UL)      /*!< SFT (Bit 0)                                           */
27527  #define R_CEC_CECCTL1_SFT_Msk           (0x3UL)    /*!< SFT (Bitfield-Mask: 0x03)                             */
27528  #define R_CEC_CECCTL1_CESEL_Pos         (2UL)      /*!< CESEL (Bit 2)                                         */
27529  #define R_CEC_CECCTL1_CESEL_Msk         (0xcUL)    /*!< CESEL (Bitfield-Mask: 0x03)                           */
27530  #define R_CEC_CECCTL1_STERRD_Pos        (4UL)      /*!< STERRD (Bit 4)                                        */
27531  #define R_CEC_CECCTL1_STERRD_Msk        (0x10UL)   /*!< STERRD (Bitfield-Mask: 0x01)                          */
27532  #define R_CEC_CECCTL1_BLERRD_Pos        (5UL)      /*!< BLERRD (Bit 5)                                        */
27533  #define R_CEC_CECCTL1_BLERRD_Msk        (0x20UL)   /*!< BLERRD (Bitfield-Mask: 0x01)                          */
27534  #define R_CEC_CECCTL1_CINTMK_Pos        (6UL)      /*!< CINTMK (Bit 6)                                        */
27535  #define R_CEC_CECCTL1_CINTMK_Msk        (0x40UL)   /*!< CINTMK (Bitfield-Mask: 0x01)                          */
27536  #define R_CEC_CECCTL1_CDFC_Pos          (7UL)      /*!< CDFC (Bit 7)                                          */
27537  #define R_CEC_CECCTL1_CDFC_Msk          (0x80UL)   /*!< CDFC (Bitfield-Mask: 0x01)                            */
27538 /* =========================================================  STATB  ========================================================= */
27539  #define R_CEC_STATB_STATB_Pos           (0UL)      /*!< STATB (Bit 0)                                         */
27540  #define R_CEC_STATB_STATB_Msk           (0x1ffUL)  /*!< STATB (Bitfield-Mask: 0x1ff)                          */
27541 /* =========================================================  STATL  ========================================================= */
27542  #define R_CEC_STATL_STATL_Pos           (0UL)      /*!< STATL (Bit 0)                                         */
27543  #define R_CEC_STATL_STATL_Msk           (0x1ffUL)  /*!< STATL (Bitfield-Mask: 0x1ff)                          */
27544 /* =========================================================  LGC0L  ========================================================= */
27545  #define R_CEC_LGC0L_LGC0L_Pos           (0UL)      /*!< LGC0L (Bit 0)                                         */
27546  #define R_CEC_LGC0L_LGC0L_Msk           (0x1ffUL)  /*!< LGC0L (Bitfield-Mask: 0x1ff)                          */
27547 /* =========================================================  LGC1L  ========================================================= */
27548  #define R_CEC_LGC1L_LGC1L_Pos           (0UL)      /*!< LGC1L (Bit 0)                                         */
27549  #define R_CEC_LGC1L_LGC1L_Msk           (0x1ffUL)  /*!< LGC1L (Bitfield-Mask: 0x1ff)                          */
27550 /* =========================================================  DATB  ========================================================== */
27551  #define R_CEC_DATB_DATB_Pos             (0UL)      /*!< DATB (Bit 0)                                          */
27552  #define R_CEC_DATB_DATB_Msk             (0x1ffUL)  /*!< DATB (Bitfield-Mask: 0x1ff)                           */
27553 /* =========================================================  NOMT  ========================================================== */
27554  #define R_CEC_NOMT_NOMT_Pos             (0UL)      /*!< NOMT (Bit 0)                                          */
27555  #define R_CEC_NOMT_NOMT_Msk             (0x1ffUL)  /*!< NOMT (Bitfield-Mask: 0x1ff)                           */
27556 /* ========================================================  STATLL  ========================================================= */
27557  #define R_CEC_STATLL_STATLL_Pos         (0UL)      /*!< STATLL (Bit 0)                                        */
27558  #define R_CEC_STATLL_STATLL_Msk         (0x1ffUL)  /*!< STATLL (Bitfield-Mask: 0x1ff)                         */
27559 /* ========================================================  STATLH  ========================================================= */
27560  #define R_CEC_STATLH_STATLH_Pos         (0UL)      /*!< STATLH (Bit 0)                                        */
27561  #define R_CEC_STATLH_STATLH_Msk         (0x1ffUL)  /*!< STATLH (Bitfield-Mask: 0x1ff)                         */
27562 /* ========================================================  STATBL  ========================================================= */
27563  #define R_CEC_STATBL_STATBL_Pos         (0UL)      /*!< STATBL (Bit 0)                                        */
27564  #define R_CEC_STATBL_STATBL_Msk         (0x1ffUL)  /*!< STATBL (Bitfield-Mask: 0x1ff)                         */
27565 /* ========================================================  STATBH  ========================================================= */
27566  #define R_CEC_STATBH_STATBH_Pos         (0UL)      /*!< STATBH (Bit 0)                                        */
27567  #define R_CEC_STATBH_STATBH_Msk         (0x1ffUL)  /*!< STATBH (Bitfield-Mask: 0x1ff)                         */
27568 /* ========================================================  LGC0LL  ========================================================= */
27569  #define R_CEC_LGC0LL_LGC0LL_Pos         (0UL)      /*!< LGC0LL (Bit 0)                                        */
27570  #define R_CEC_LGC0LL_LGC0LL_Msk         (0x1ffUL)  /*!< LGC0LL (Bitfield-Mask: 0x1ff)                         */
27571 /* ========================================================  LGC0LH  ========================================================= */
27572  #define R_CEC_LGC0LH_LGC0LH_Pos         (0UL)      /*!< LGC0LH (Bit 0)                                        */
27573  #define R_CEC_LGC0LH_LGC0LH_Msk         (0x1ffUL)  /*!< LGC0LH (Bitfield-Mask: 0x1ff)                         */
27574 /* ========================================================  LGC1LL  ========================================================= */
27575  #define R_CEC_LGC1LL_LGC1LL_Pos         (0UL)      /*!< LGC1LL (Bit 0)                                        */
27576  #define R_CEC_LGC1LL_LGC1LL_Msk         (0x1ffUL)  /*!< LGC1LL (Bitfield-Mask: 0x1ff)                         */
27577 /* ========================================================  LGC1LH  ========================================================= */
27578  #define R_CEC_LGC1LH_LGC1LH_Pos         (0UL)      /*!< LGC1LH (Bit 0)                                        */
27579  #define R_CEC_LGC1LH_LGC1LH_Msk         (0x1ffUL)  /*!< LGC1LH (Bitfield-Mask: 0x1ff)                         */
27580 /* =========================================================  DATBL  ========================================================= */
27581  #define R_CEC_DATBL_DATBL_Pos           (0UL)      /*!< DATBL (Bit 0)                                         */
27582  #define R_CEC_DATBL_DATBL_Msk           (0x1ffUL)  /*!< DATBL (Bitfield-Mask: 0x1ff)                          */
27583 /* =========================================================  DATBH  ========================================================= */
27584  #define R_CEC_DATBH_DATBH_Pos           (0UL)      /*!< DATBH (Bit 0)                                         */
27585  #define R_CEC_DATBH_DATBH_Msk           (0x1ffUL)  /*!< DATBH (Bitfield-Mask: 0x1ff)                          */
27586 /* =========================================================  NOMP  ========================================================== */
27587  #define R_CEC_NOMP_NOMP_Pos             (0UL)      /*!< NOMP (Bit 0)                                          */
27588  #define R_CEC_NOMP_NOMP_Msk             (0x1ffUL)  /*!< NOMP (Bitfield-Mask: 0x1ff)                           */
27589 /* ========================================================  CECEXMD  ======================================================== */
27590  #define R_CEC_CECEXMD_LERPLEN_Pos       (4UL)      /*!< LERPLEN (Bit 4)                                       */
27591  #define R_CEC_CECEXMD_LERPLEN_Msk       (0x10UL)   /*!< LERPLEN (Bitfield-Mask: 0x01)                         */
27592  #define R_CEC_CECEXMD_RERCVEN_Pos       (5UL)      /*!< RERCVEN (Bit 5)                                       */
27593  #define R_CEC_CECEXMD_RERCVEN_Msk       (0x20UL)   /*!< RERCVEN (Bitfield-Mask: 0x01)                         */
27594  #define R_CEC_CECEXMD_RCVINTDSEL_Pos    (7UL)      /*!< RCVINTDSEL (Bit 7)                                    */
27595  #define R_CEC_CECEXMD_RCVINTDSEL_Msk    (0x80UL)   /*!< RCVINTDSEL (Bitfield-Mask: 0x01)                      */
27596 /* =======================================================  CECEXMON  ======================================================== */
27597  #define R_CEC_CECEXMON_CECLNMON_Pos     (0UL)      /*!< CECLNMON (Bit 0)                                      */
27598  #define R_CEC_CECEXMON_CECLNMON_Msk     (0x1UL)    /*!< CECLNMON (Bitfield-Mask: 0x01)                        */
27599  #define R_CEC_CECEXMON_ACKF_Pos         (1UL)      /*!< ACKF (Bit 1)                                          */
27600  #define R_CEC_CECEXMON_ACKF_Msk         (0x2UL)    /*!< ACKF (Bitfield-Mask: 0x01)                            */
27601 /* =========================================================  CTXD  ========================================================== */
27602 /* =========================================================  CRXD  ========================================================== */
27603 /* =========================================================  CECES  ========================================================= */
27604  #define R_CEC_CECES_OERR_Pos            (0UL)      /*!< OERR (Bit 0)                                          */
27605  #define R_CEC_CECES_OERR_Msk            (0x1UL)    /*!< OERR (Bitfield-Mask: 0x01)                            */
27606  #define R_CEC_CECES_UERR_Pos            (1UL)      /*!< UERR (Bit 1)                                          */
27607  #define R_CEC_CECES_UERR_Msk            (0x2UL)    /*!< UERR (Bitfield-Mask: 0x01)                            */
27608  #define R_CEC_CECES_ACKERR_Pos          (2UL)      /*!< ACKERR (Bit 2)                                        */
27609  #define R_CEC_CECES_ACKERR_Msk          (0x4UL)    /*!< ACKERR (Bitfield-Mask: 0x01)                          */
27610  #define R_CEC_CECES_TERR_Pos            (3UL)      /*!< TERR (Bit 3)                                          */
27611  #define R_CEC_CECES_TERR_Msk            (0x8UL)    /*!< TERR (Bitfield-Mask: 0x01)                            */
27612  #define R_CEC_CECES_TXERR_Pos           (4UL)      /*!< TXERR (Bit 4)                                         */
27613  #define R_CEC_CECES_TXERR_Msk           (0x10UL)   /*!< TXERR (Bitfield-Mask: 0x01)                           */
27614  #define R_CEC_CECES_AERR_Pos            (5UL)      /*!< AERR (Bit 5)                                          */
27615  #define R_CEC_CECES_AERR_Msk            (0x20UL)   /*!< AERR (Bitfield-Mask: 0x01)                            */
27616  #define R_CEC_CECES_BLERR_Pos           (6UL)      /*!< BLERR (Bit 6)                                         */
27617  #define R_CEC_CECES_BLERR_Msk           (0x40UL)   /*!< BLERR (Bitfield-Mask: 0x01)                           */
27618 /* =========================================================  CECS  ========================================================== */
27619  #define R_CEC_CECS_ADRF_Pos             (0UL)      /*!< ADRF (Bit 0)                                          */
27620  #define R_CEC_CECS_ADRF_Msk             (0x1UL)    /*!< ADRF (Bitfield-Mask: 0x01)                            */
27621  #define R_CEC_CECS_BUSST_Pos            (1UL)      /*!< BUSST (Bit 1)                                         */
27622  #define R_CEC_CECS_BUSST_Msk            (0x2UL)    /*!< BUSST (Bitfield-Mask: 0x01)                           */
27623  #define R_CEC_CECS_TXST_Pos             (2UL)      /*!< TXST (Bit 2)                                          */
27624  #define R_CEC_CECS_TXST_Msk             (0x4UL)    /*!< TXST (Bitfield-Mask: 0x01)                            */
27625  #define R_CEC_CECS_EOMF_Pos             (3UL)      /*!< EOMF (Bit 3)                                          */
27626  #define R_CEC_CECS_EOMF_Msk             (0x8UL)    /*!< EOMF (Bitfield-Mask: 0x01)                            */
27627  #define R_CEC_CECS_ITCEF_Pos            (4UL)      /*!< ITCEF (Bit 4)                                         */
27628  #define R_CEC_CECS_ITCEF_Msk            (0x10UL)   /*!< ITCEF (Bitfield-Mask: 0x01)                           */
27629  #define R_CEC_CECS_SFTST_Pos            (7UL)      /*!< SFTST (Bit 7)                                         */
27630  #define R_CEC_CECS_SFTST_Msk            (0x80UL)   /*!< SFTST (Bitfield-Mask: 0x01)                           */
27631 /* =========================================================  CECFC  ========================================================= */
27632  #define R_CEC_CECFC_OCTRG_Pos           (0UL)      /*!< OCTRG (Bit 0)                                         */
27633  #define R_CEC_CECFC_OCTRG_Msk           (0x1UL)    /*!< OCTRG (Bitfield-Mask: 0x01)                           */
27634  #define R_CEC_CECFC_UCTRG_Pos           (1UL)      /*!< UCTRG (Bit 1)                                         */
27635  #define R_CEC_CECFC_UCTRG_Msk           (0x2UL)    /*!< UCTRG (Bitfield-Mask: 0x01)                           */
27636  #define R_CEC_CECFC_ACKCTRG_Pos         (2UL)      /*!< ACKCTRG (Bit 2)                                       */
27637  #define R_CEC_CECFC_ACKCTRG_Msk         (0x4UL)    /*!< ACKCTRG (Bitfield-Mask: 0x01)                         */
27638  #define R_CEC_CECFC_TCTRG_Pos           (3UL)      /*!< TCTRG (Bit 3)                                         */
27639  #define R_CEC_CECFC_TCTRG_Msk           (0x8UL)    /*!< TCTRG (Bitfield-Mask: 0x01)                           */
27640  #define R_CEC_CECFC_TXCTRG_Pos          (4UL)      /*!< TXCTRG (Bit 4)                                        */
27641  #define R_CEC_CECFC_TXCTRG_Msk          (0x10UL)   /*!< TXCTRG (Bitfield-Mask: 0x01)                          */
27642  #define R_CEC_CECFC_ACTRG_Pos           (5UL)      /*!< ACTRG (Bit 5)                                         */
27643  #define R_CEC_CECFC_ACTRG_Msk           (0x20UL)   /*!< ACTRG (Bitfield-Mask: 0x01)                           */
27644  #define R_CEC_CECFC_BLCTRG_Pos          (6UL)      /*!< BLCTRG (Bit 6)                                        */
27645  #define R_CEC_CECFC_BLCTRG_Msk          (0x40UL)   /*!< BLCTRG (Bitfield-Mask: 0x01)                          */
27646 /* ========================================================  CECCTL0  ======================================================== */
27647  #define R_CEC_CECCTL0_EOM_Pos           (0UL)      /*!< EOM (Bit 0)                                           */
27648  #define R_CEC_CECCTL0_EOM_Msk           (0x1UL)    /*!< EOM (Bitfield-Mask: 0x01)                             */
27649  #define R_CEC_CECCTL0_CECRXEN_Pos       (1UL)      /*!< CECRXEN (Bit 1)                                       */
27650  #define R_CEC_CECCTL0_CECRXEN_Msk       (0x2UL)    /*!< CECRXEN (Bitfield-Mask: 0x01)                         */
27651  #define R_CEC_CECCTL0_TXTRG_Pos         (2UL)      /*!< TXTRG (Bit 2)                                         */
27652  #define R_CEC_CECCTL0_TXTRG_Msk         (0x4UL)    /*!< TXTRG (Bitfield-Mask: 0x01)                           */
27653  #define R_CEC_CECCTL0_CCL_Pos           (3UL)      /*!< CCL (Bit 3)                                           */
27654  #define R_CEC_CECCTL0_CCL_Msk           (0x38UL)   /*!< CCL (Bitfield-Mask: 0x07)                             */
27655  #define R_CEC_CECCTL0_ACKTEN_Pos        (6UL)      /*!< ACKTEN (Bit 6)                                        */
27656  #define R_CEC_CECCTL0_ACKTEN_Msk        (0x40UL)   /*!< ACKTEN (Bitfield-Mask: 0x01)                          */
27657  #define R_CEC_CECCTL0_CECE_Pos          (7UL)      /*!< CECE (Bit 7)                                          */
27658  #define R_CEC_CECCTL0_CECE_Msk          (0x80UL)   /*!< CECE (Bitfield-Mask: 0x01)                            */
27659 
27660 /* =========================================================================================================================== */
27661 /* ================                                          R_OSPI                                           ================ */
27662 /* =========================================================================================================================== */
27663 
27664 /* ==========================================================  DCR  ========================================================== */
27665  #define R_OSPI_DCR_DVCMD0_Pos         (0UL)          /*!< DVCMD0 (Bit 0)                                        */
27666  #define R_OSPI_DCR_DVCMD0_Msk         (0xffUL)       /*!< DVCMD0 (Bitfield-Mask: 0xff)                          */
27667  #define R_OSPI_DCR_DVCMD1_Pos         (8UL)          /*!< DVCMD1 (Bit 8)                                        */
27668  #define R_OSPI_DCR_DVCMD1_Msk         (0xff00UL)     /*!< DVCMD1 (Bitfield-Mask: 0xff)                          */
27669 /* ==========================================================  DAR  ========================================================== */
27670  #define R_OSPI_DAR_DVAD0_Pos          (0UL)          /*!< DVAD0 (Bit 0)                                         */
27671  #define R_OSPI_DAR_DVAD0_Msk          (0xffUL)       /*!< DVAD0 (Bitfield-Mask: 0xff)                           */
27672  #define R_OSPI_DAR_DVAD1_Pos          (8UL)          /*!< DVAD1 (Bit 8)                                         */
27673  #define R_OSPI_DAR_DVAD1_Msk          (0xff00UL)     /*!< DVAD1 (Bitfield-Mask: 0xff)                           */
27674  #define R_OSPI_DAR_DVAD2_Pos          (16UL)         /*!< DVAD2 (Bit 16)                                        */
27675  #define R_OSPI_DAR_DVAD2_Msk          (0xff0000UL)   /*!< DVAD2 (Bitfield-Mask: 0xff)                           */
27676  #define R_OSPI_DAR_DVAD3_Pos          (24UL)         /*!< DVAD3 (Bit 24)                                        */
27677  #define R_OSPI_DAR_DVAD3_Msk          (0xff000000UL) /*!< DVAD3 (Bitfield-Mask: 0xff)                           */
27678 /* =========================================================  DCSR  ========================================================== */
27679  #define R_OSPI_DCSR_DALEN_Pos         (0UL)          /*!< DALEN (Bit 0)                                         */
27680  #define R_OSPI_DCSR_DALEN_Msk         (0xffUL)       /*!< DALEN (Bitfield-Mask: 0xff)                           */
27681  #define R_OSPI_DCSR_DMLEN_Pos         (8UL)          /*!< DMLEN (Bit 8)                                         */
27682  #define R_OSPI_DCSR_DMLEN_Msk         (0xff00UL)     /*!< DMLEN (Bitfield-Mask: 0xff)                           */
27683  #define R_OSPI_DCSR_ACDV_Pos          (19UL)         /*!< ACDV (Bit 19)                                         */
27684  #define R_OSPI_DCSR_ACDV_Msk          (0x80000UL)    /*!< ACDV (Bitfield-Mask: 0x01)                            */
27685  #define R_OSPI_DCSR_CMDLEN_Pos        (20UL)         /*!< CMDLEN (Bit 20)                                       */
27686  #define R_OSPI_DCSR_CMDLEN_Msk        (0x700000UL)   /*!< CMDLEN (Bitfield-Mask: 0x07)                          */
27687  #define R_OSPI_DCSR_DAOR_Pos          (23UL)         /*!< DAOR (Bit 23)                                         */
27688  #define R_OSPI_DCSR_DAOR_Msk          (0x800000UL)   /*!< DAOR (Bitfield-Mask: 0x01)                            */
27689  #define R_OSPI_DCSR_ADLEN_Pos         (24UL)         /*!< ADLEN (Bit 24)                                        */
27690  #define R_OSPI_DCSR_ADLEN_Msk         (0x7000000UL)  /*!< ADLEN (Bitfield-Mask: 0x07)                           */
27691  #define R_OSPI_DCSR_DOPI_Pos          (27UL)         /*!< DOPI (Bit 27)                                         */
27692  #define R_OSPI_DCSR_DOPI_Msk          (0x8000000UL)  /*!< DOPI (Bitfield-Mask: 0x01)                            */
27693  #define R_OSPI_DCSR_ACDA_Pos          (28UL)         /*!< ACDA (Bit 28)                                         */
27694  #define R_OSPI_DCSR_ACDA_Msk          (0x10000000UL) /*!< ACDA (Bitfield-Mask: 0x01)                            */
27695  #define R_OSPI_DCSR_PREN_Pos          (29UL)         /*!< PREN (Bit 29)                                         */
27696  #define R_OSPI_DCSR_PREN_Msk          (0x20000000UL) /*!< PREN (Bitfield-Mask: 0x01)                            */
27697 /* ==========================================================  DSR  ========================================================== */
27698  #define R_OSPI_DSR_DVSZ_Pos           (0UL)          /*!< DVSZ (Bit 0)                                          */
27699  #define R_OSPI_DSR_DVSZ_Msk           (0x3fffffffUL) /*!< DVSZ (Bitfield-Mask: 0x3fffffff)                      */
27700  #define R_OSPI_DSR_DVTYP_Pos          (30UL)         /*!< DVTYP (Bit 30)                                        */
27701  #define R_OSPI_DSR_DVTYP_Msk          (0xc0000000UL) /*!< DVTYP (Bitfield-Mask: 0x03)                           */
27702 /* =========================================================  MDTR  ========================================================== */
27703  #define R_OSPI_MDTR_DV0DEL_Pos        (0UL)          /*!< DV0DEL (Bit 0)                                        */
27704  #define R_OSPI_MDTR_DV0DEL_Msk        (0xffUL)       /*!< DV0DEL (Bitfield-Mask: 0xff)                          */
27705  #define R_OSPI_MDTR_DQSERAM_Pos       (8UL)          /*!< DQSERAM (Bit 8)                                       */
27706  #define R_OSPI_MDTR_DQSERAM_Msk       (0xf00UL)      /*!< DQSERAM (Bitfield-Mask: 0x0f)                         */
27707  #define R_OSPI_MDTR_DQSESOPI_Pos      (12UL)         /*!< DQSESOPI (Bit 12)                                     */
27708  #define R_OSPI_MDTR_DQSESOPI_Msk      (0xf000UL)     /*!< DQSESOPI (Bitfield-Mask: 0x0f)                        */
27709  #define R_OSPI_MDTR_DV1DEL_Pos        (16UL)         /*!< DV1DEL (Bit 16)                                       */
27710  #define R_OSPI_MDTR_DV1DEL_Msk        (0xff0000UL)   /*!< DV1DEL (Bitfield-Mask: 0xff)                          */
27711  #define R_OSPI_MDTR_DQSEDOPI_Pos      (24UL)         /*!< DQSEDOPI (Bit 24)                                     */
27712  #define R_OSPI_MDTR_DQSEDOPI_Msk      (0xf000000UL)  /*!< DQSEDOPI (Bitfield-Mask: 0x0f)                        */
27713 /* =========================================================  ACTR  ========================================================== */
27714  #define R_OSPI_ACTR_CTP_Pos           (0UL)          /*!< CTP (Bit 0)                                           */
27715  #define R_OSPI_ACTR_CTP_Msk           (0xffffffffUL) /*!< CTP (Bitfield-Mask: 0xffffffff)                       */
27716 /* =========================================================  ACAR  ========================================================== */
27717  #define R_OSPI_ACAR_CAD_Pos           (0UL)          /*!< CAD (Bit 0)                                           */
27718  #define R_OSPI_ACAR_CAD_Msk           (0xffffffffUL) /*!< CAD (Bitfield-Mask: 0xffffffff)                       */
27719 /* ========================================================  DRCSTR  ========================================================= */
27720  #define R_OSPI_DRCSTR_CTRW0_Pos       (0UL)          /*!< CTRW0 (Bit 0)                                         */
27721  #define R_OSPI_DRCSTR_CTRW0_Msk       (0x7fUL)       /*!< CTRW0 (Bitfield-Mask: 0x7f)                           */
27722  #define R_OSPI_DRCSTR_CTR0_Pos        (7UL)          /*!< CTR0 (Bit 7)                                          */
27723  #define R_OSPI_DRCSTR_CTR0_Msk        (0x80UL)       /*!< CTR0 (Bitfield-Mask: 0x01)                            */
27724  #define R_OSPI_DRCSTR_DVRDCMD0_Pos    (8UL)          /*!< DVRDCMD0 (Bit 8)                                      */
27725  #define R_OSPI_DRCSTR_DVRDCMD0_Msk    (0x700UL)      /*!< DVRDCMD0 (Bitfield-Mask: 0x07)                        */
27726  #define R_OSPI_DRCSTR_DVRDHI0_Pos     (11UL)         /*!< DVRDHI0 (Bit 11)                                      */
27727  #define R_OSPI_DRCSTR_DVRDHI0_Msk     (0x3800UL)     /*!< DVRDHI0 (Bitfield-Mask: 0x07)                         */
27728  #define R_OSPI_DRCSTR_DVRDLO0_Pos     (14UL)         /*!< DVRDLO0 (Bit 14)                                      */
27729  #define R_OSPI_DRCSTR_DVRDLO0_Msk     (0xc000UL)     /*!< DVRDLO0 (Bitfield-Mask: 0x03)                         */
27730  #define R_OSPI_DRCSTR_CTRW1_Pos       (16UL)         /*!< CTRW1 (Bit 16)                                        */
27731  #define R_OSPI_DRCSTR_CTRW1_Msk       (0x7f0000UL)   /*!< CTRW1 (Bitfield-Mask: 0x7f)                           */
27732  #define R_OSPI_DRCSTR_CTR1_Pos        (23UL)         /*!< CTR1 (Bit 23)                                         */
27733  #define R_OSPI_DRCSTR_CTR1_Msk        (0x800000UL)   /*!< CTR1 (Bitfield-Mask: 0x01)                            */
27734  #define R_OSPI_DRCSTR_DVRDCMD1_Pos    (24UL)         /*!< DVRDCMD1 (Bit 24)                                     */
27735  #define R_OSPI_DRCSTR_DVRDCMD1_Msk    (0x7000000UL)  /*!< DVRDCMD1 (Bitfield-Mask: 0x07)                        */
27736  #define R_OSPI_DRCSTR_DVRDHI1_Pos     (27UL)         /*!< DVRDHI1 (Bit 27)                                      */
27737  #define R_OSPI_DRCSTR_DVRDHI1_Msk     (0x38000000UL) /*!< DVRDHI1 (Bitfield-Mask: 0x07)                         */
27738  #define R_OSPI_DRCSTR_DVRDLO1_Pos     (30UL)         /*!< DVRDLO1 (Bit 30)                                      */
27739  #define R_OSPI_DRCSTR_DVRDLO1_Msk     (0xc0000000UL) /*!< DVRDLO1 (Bitfield-Mask: 0x03)                         */
27740 /* ========================================================  DWCSTR  ========================================================= */
27741  #define R_OSPI_DWCSTR_CTWW0_Pos       (0UL)          /*!< CTWW0 (Bit 0)                                         */
27742  #define R_OSPI_DWCSTR_CTWW0_Msk       (0x7fUL)       /*!< CTWW0 (Bitfield-Mask: 0x7f)                           */
27743  #define R_OSPI_DWCSTR_CTW0_Pos        (7UL)          /*!< CTW0 (Bit 7)                                          */
27744  #define R_OSPI_DWCSTR_CTW0_Msk        (0x80UL)       /*!< CTW0 (Bitfield-Mask: 0x01)                            */
27745  #define R_OSPI_DWCSTR_DVWCMD0_Pos     (8UL)          /*!< DVWCMD0 (Bit 8)                                       */
27746  #define R_OSPI_DWCSTR_DVWCMD0_Msk     (0x700UL)      /*!< DVWCMD0 (Bitfield-Mask: 0x07)                         */
27747  #define R_OSPI_DWCSTR_DVWHI0_Pos      (11UL)         /*!< DVWHI0 (Bit 11)                                       */
27748  #define R_OSPI_DWCSTR_DVWHI0_Msk      (0x3800UL)     /*!< DVWHI0 (Bitfield-Mask: 0x07)                          */
27749  #define R_OSPI_DWCSTR_DVWLO0_Pos      (14UL)         /*!< DVWLO0 (Bit 14)                                       */
27750  #define R_OSPI_DWCSTR_DVWLO0_Msk      (0xc000UL)     /*!< DVWLO0 (Bitfield-Mask: 0x03)                          */
27751  #define R_OSPI_DWCSTR_CTWW1_Pos       (16UL)         /*!< CTWW1 (Bit 16)                                        */
27752  #define R_OSPI_DWCSTR_CTWW1_Msk       (0x7f0000UL)   /*!< CTWW1 (Bitfield-Mask: 0x7f)                           */
27753  #define R_OSPI_DWCSTR_CTW1_Pos        (23UL)         /*!< CTW1 (Bit 23)                                         */
27754  #define R_OSPI_DWCSTR_CTW1_Msk        (0x800000UL)   /*!< CTW1 (Bitfield-Mask: 0x01)                            */
27755  #define R_OSPI_DWCSTR_DVWCMD1_Pos     (24UL)         /*!< DVWCMD1 (Bit 24)                                      */
27756  #define R_OSPI_DWCSTR_DVWCMD1_Msk     (0x7000000UL)  /*!< DVWCMD1 (Bitfield-Mask: 0x07)                         */
27757  #define R_OSPI_DWCSTR_DVWHI1_Pos      (27UL)         /*!< DVWHI1 (Bit 27)                                       */
27758  #define R_OSPI_DWCSTR_DVWHI1_Msk      (0x38000000UL) /*!< DVWHI1 (Bitfield-Mask: 0x07)                          */
27759  #define R_OSPI_DWCSTR_DVWLO1_Pos      (30UL)         /*!< DVWLO1 (Bit 30)                                       */
27760  #define R_OSPI_DWCSTR_DVWLO1_Msk      (0xc0000000UL) /*!< DVWLO1 (Bitfield-Mask: 0x03)                          */
27761 /* =========================================================  DCSTR  ========================================================= */
27762  #define R_OSPI_DCSTR_DVSELCMD_Pos     (8UL)          /*!< DVSELCMD (Bit 8)                                      */
27763  #define R_OSPI_DCSTR_DVSELCMD_Msk     (0x700UL)      /*!< DVSELCMD (Bitfield-Mask: 0x07)                        */
27764  #define R_OSPI_DCSTR_DVSELHI_Pos      (11UL)         /*!< DVSELHI (Bit 11)                                      */
27765  #define R_OSPI_DCSTR_DVSELHI_Msk      (0x3800UL)     /*!< DVSELHI (Bitfield-Mask: 0x07)                         */
27766  #define R_OSPI_DCSTR_DVSELLO_Pos      (14UL)         /*!< DVSELLO (Bit 14)                                      */
27767  #define R_OSPI_DCSTR_DVSELLO_Msk      (0xc000UL)     /*!< DVSELLO (Bitfield-Mask: 0x03)                         */
27768 /* =========================================================  CDSR  ========================================================== */
27769  #define R_OSPI_CDSR_DV0TTYP_Pos       (0UL)          /*!< DV0TTYP (Bit 0)                                       */
27770  #define R_OSPI_CDSR_DV0TTYP_Msk       (0x3UL)        /*!< DV0TTYP (Bitfield-Mask: 0x03)                         */
27771  #define R_OSPI_CDSR_DV1TTYP_Pos       (2UL)          /*!< DV1TTYP (Bit 2)                                       */
27772  #define R_OSPI_CDSR_DV1TTYP_Msk       (0xcUL)        /*!< DV1TTYP (Bitfield-Mask: 0x03)                         */
27773  #define R_OSPI_CDSR_DV0PC_Pos         (4UL)          /*!< DV0PC (Bit 4)                                         */
27774  #define R_OSPI_CDSR_DV0PC_Msk         (0x10UL)       /*!< DV0PC (Bitfield-Mask: 0x01)                           */
27775  #define R_OSPI_CDSR_DV1PC_Pos         (5UL)          /*!< DV1PC (Bit 5)                                         */
27776  #define R_OSPI_CDSR_DV1PC_Msk         (0x20UL)       /*!< DV1PC (Bitfield-Mask: 0x01)                           */
27777  #define R_OSPI_CDSR_ACMEME0_Pos       (10UL)         /*!< ACMEME0 (Bit 10)                                      */
27778  #define R_OSPI_CDSR_ACMEME0_Msk       (0x400UL)      /*!< ACMEME0 (Bitfield-Mask: 0x01)                         */
27779  #define R_OSPI_CDSR_ACMEME1_Pos       (11UL)         /*!< ACMEME1 (Bit 11)                                      */
27780  #define R_OSPI_CDSR_ACMEME1_Msk       (0x800UL)      /*!< ACMEME1 (Bitfield-Mask: 0x01)                         */
27781  #define R_OSPI_CDSR_ACMODE_Pos        (12UL)         /*!< ACMODE (Bit 12)                                       */
27782  #define R_OSPI_CDSR_ACMODE_Msk        (0x3000UL)     /*!< ACMODE (Bitfield-Mask: 0x03)                          */
27783  #define R_OSPI_CDSR_DLFT_Pos          (31UL)         /*!< DLFT (Bit 31)                                         */
27784  #define R_OSPI_CDSR_DLFT_Msk          (0x80000000UL) /*!< DLFT (Bitfield-Mask: 0x01)                            */
27785 /* =========================================================  MDLR  ========================================================== */
27786  #define R_OSPI_MDLR_DV0RDL_Pos        (0UL)          /*!< DV0RDL (Bit 0)                                        */
27787  #define R_OSPI_MDLR_DV0RDL_Msk        (0xffUL)       /*!< DV0RDL (Bitfield-Mask: 0xff)                          */
27788  #define R_OSPI_MDLR_DV0WDL_Pos        (8UL)          /*!< DV0WDL (Bit 8)                                        */
27789  #define R_OSPI_MDLR_DV0WDL_Msk        (0xff00UL)     /*!< DV0WDL (Bitfield-Mask: 0xff)                          */
27790  #define R_OSPI_MDLR_DV1RDL_Pos        (16UL)         /*!< DV1RDL (Bit 16)                                       */
27791  #define R_OSPI_MDLR_DV1RDL_Msk        (0xff0000UL)   /*!< DV1RDL (Bitfield-Mask: 0xff)                          */
27792  #define R_OSPI_MDLR_DV1WDL_Pos        (24UL)         /*!< DV1WDL (Bit 24)                                       */
27793  #define R_OSPI_MDLR_DV1WDL_Msk        (0xff000000UL) /*!< DV1WDL (Bitfield-Mask: 0xff)                          */
27794 /* =========================================================  MRWCR  ========================================================= */
27795  #define R_OSPI_MRWCR_DMRCMD0_Pos      (0UL)          /*!< DMRCMD0 (Bit 0)                                       */
27796  #define R_OSPI_MRWCR_DMRCMD0_Msk      (0xffUL)       /*!< DMRCMD0 (Bitfield-Mask: 0xff)                         */
27797  #define R_OSPI_MRWCR_DMRCMD1_Pos      (8UL)          /*!< DMRCMD1 (Bit 8)                                       */
27798  #define R_OSPI_MRWCR_DMRCMD1_Msk      (0xff00UL)     /*!< DMRCMD1 (Bitfield-Mask: 0xff)                         */
27799  #define R_OSPI_MRWCR_DMWCMD0_Pos      (16UL)         /*!< DMWCMD0 (Bit 16)                                      */
27800  #define R_OSPI_MRWCR_DMWCMD0_Msk      (0xff0000UL)   /*!< DMWCMD0 (Bitfield-Mask: 0xff)                         */
27801  #define R_OSPI_MRWCR_DMWCMD1_Pos      (24UL)         /*!< DMWCMD1 (Bit 24)                                      */
27802  #define R_OSPI_MRWCR_DMWCMD1_Msk      (0xff000000UL) /*!< DMWCMD1 (Bitfield-Mask: 0xff)                         */
27803 /* ========================================================  MRWCSR  ========================================================= */
27804  #define R_OSPI_MRWCSR_MRAL0_Pos       (0UL)          /*!< MRAL0 (Bit 0)                                         */
27805  #define R_OSPI_MRWCSR_MRAL0_Msk       (0x7UL)        /*!< MRAL0 (Bitfield-Mask: 0x07)                           */
27806  #define R_OSPI_MRWCSR_MRCL0_Pos       (3UL)          /*!< MRCL0 (Bit 3)                                         */
27807  #define R_OSPI_MRWCSR_MRCL0_Msk       (0x38UL)       /*!< MRCL0 (Bitfield-Mask: 0x07)                           */
27808  #define R_OSPI_MRWCSR_MRO0_Pos        (6UL)          /*!< MRO0 (Bit 6)                                          */
27809  #define R_OSPI_MRWCSR_MRO0_Msk        (0x40UL)       /*!< MRO0 (Bitfield-Mask: 0x01)                            */
27810  #define R_OSPI_MRWCSR_PREN0_Pos       (7UL)          /*!< PREN0 (Bit 7)                                         */
27811  #define R_OSPI_MRWCSR_PREN0_Msk       (0x80UL)       /*!< PREN0 (Bitfield-Mask: 0x01)                           */
27812  #define R_OSPI_MRWCSR_MWAL0_Pos       (8UL)          /*!< MWAL0 (Bit 8)                                         */
27813  #define R_OSPI_MRWCSR_MWAL0_Msk       (0x700UL)      /*!< MWAL0 (Bitfield-Mask: 0x07)                           */
27814  #define R_OSPI_MRWCSR_MWCL0_Pos       (11UL)         /*!< MWCL0 (Bit 11)                                        */
27815  #define R_OSPI_MRWCSR_MWCL0_Msk       (0x3800UL)     /*!< MWCL0 (Bitfield-Mask: 0x07)                           */
27816  #define R_OSPI_MRWCSR_MWO0_Pos        (14UL)         /*!< MWO0 (Bit 14)                                         */
27817  #define R_OSPI_MRWCSR_MWO0_Msk        (0x4000UL)     /*!< MWO0 (Bitfield-Mask: 0x01)                            */
27818  #define R_OSPI_MRWCSR_MRAL1_Pos       (16UL)         /*!< MRAL1 (Bit 16)                                        */
27819  #define R_OSPI_MRWCSR_MRAL1_Msk       (0x70000UL)    /*!< MRAL1 (Bitfield-Mask: 0x07)                           */
27820  #define R_OSPI_MRWCSR_MRCL1_Pos       (19UL)         /*!< MRCL1 (Bit 19)                                        */
27821  #define R_OSPI_MRWCSR_MRCL1_Msk       (0x380000UL)   /*!< MRCL1 (Bitfield-Mask: 0x07)                           */
27822  #define R_OSPI_MRWCSR_MRO1_Pos        (22UL)         /*!< MRO1 (Bit 22)                                         */
27823  #define R_OSPI_MRWCSR_MRO1_Msk        (0x400000UL)   /*!< MRO1 (Bitfield-Mask: 0x01)                            */
27824  #define R_OSPI_MRWCSR_PREN1_Pos       (23UL)         /*!< PREN1 (Bit 23)                                        */
27825  #define R_OSPI_MRWCSR_PREN1_Msk       (0x800000UL)   /*!< PREN1 (Bitfield-Mask: 0x01)                           */
27826  #define R_OSPI_MRWCSR_MWAL1_Pos       (24UL)         /*!< MWAL1 (Bit 24)                                        */
27827  #define R_OSPI_MRWCSR_MWAL1_Msk       (0x7000000UL)  /*!< MWAL1 (Bitfield-Mask: 0x07)                           */
27828  #define R_OSPI_MRWCSR_MWCL1_Pos       (27UL)         /*!< MWCL1 (Bit 27)                                        */
27829  #define R_OSPI_MRWCSR_MWCL1_Msk       (0x38000000UL) /*!< MWCL1 (Bitfield-Mask: 0x07)                           */
27830  #define R_OSPI_MRWCSR_MWO1_Pos        (30UL)         /*!< MWO1 (Bit 30)                                         */
27831  #define R_OSPI_MRWCSR_MWO1_Msk        (0x40000000UL) /*!< MWO1 (Bitfield-Mask: 0x01)                            */
27832 /* ==========================================================  ESR  ========================================================== */
27833  #define R_OSPI_ESR_MRESR_Pos          (0UL)          /*!< MRESR (Bit 0)                                         */
27834  #define R_OSPI_ESR_MRESR_Msk          (0xffUL)       /*!< MRESR (Bitfield-Mask: 0xff)                           */
27835  #define R_OSPI_ESR_MWESR_Pos          (8UL)          /*!< MWESR (Bit 8)                                         */
27836  #define R_OSPI_ESR_MWESR_Msk          (0xff00UL)     /*!< MWESR (Bitfield-Mask: 0xff)                           */
27837 /* =========================================================  CWNDR  ========================================================= */
27838  #define R_OSPI_CWNDR_WND_Pos          (0UL)          /*!< WND (Bit 0)                                           */
27839  #define R_OSPI_CWNDR_WND_Msk          (0xffffffffUL) /*!< WND (Bitfield-Mask: 0xffffffff)                       */
27840 /* =========================================================  CWDR  ========================================================== */
27841  #define R_OSPI_CWDR_WD0_Pos           (0UL)          /*!< WD0 (Bit 0)                                           */
27842  #define R_OSPI_CWDR_WD0_Msk           (0xffUL)       /*!< WD0 (Bitfield-Mask: 0xff)                             */
27843  #define R_OSPI_CWDR_WD1_Pos           (8UL)          /*!< WD1 (Bit 8)                                           */
27844  #define R_OSPI_CWDR_WD1_Msk           (0xff00UL)     /*!< WD1 (Bitfield-Mask: 0xff)                             */
27845  #define R_OSPI_CWDR_WD2_Pos           (16UL)         /*!< WD2 (Bit 16)                                          */
27846  #define R_OSPI_CWDR_WD2_Msk           (0xff0000UL)   /*!< WD2 (Bitfield-Mask: 0xff)                             */
27847  #define R_OSPI_CWDR_WD3_Pos           (24UL)         /*!< WD3 (Bit 24)                                          */
27848  #define R_OSPI_CWDR_WD3_Msk           (0xff000000UL) /*!< WD3 (Bitfield-Mask: 0xff)                             */
27849 /* ==========================================================  CRR  ========================================================== */
27850  #define R_OSPI_CRR_RD0_Pos            (0UL)          /*!< RD0 (Bit 0)                                           */
27851  #define R_OSPI_CRR_RD0_Msk            (0xffUL)       /*!< RD0 (Bitfield-Mask: 0xff)                             */
27852  #define R_OSPI_CRR_RD1_Pos            (8UL)          /*!< RD1 (Bit 8)                                           */
27853  #define R_OSPI_CRR_RD1_Msk            (0xff00UL)     /*!< RD1 (Bitfield-Mask: 0xff)                             */
27854  #define R_OSPI_CRR_RD2_Pos            (16UL)         /*!< RD2 (Bit 16)                                          */
27855  #define R_OSPI_CRR_RD2_Msk            (0xff0000UL)   /*!< RD2 (Bitfield-Mask: 0xff)                             */
27856  #define R_OSPI_CRR_RD3_Pos            (24UL)         /*!< RD3 (Bit 24)                                          */
27857  #define R_OSPI_CRR_RD3_Msk            (0xff000000UL) /*!< RD3 (Bitfield-Mask: 0xff)                             */
27858 /* =========================================================  ACSR  ========================================================== */
27859  #define R_OSPI_ACSR_ACSR0_Pos         (0UL)          /*!< ACSR0 (Bit 0)                                         */
27860  #define R_OSPI_ACSR_ACSR0_Msk         (0x7UL)        /*!< ACSR0 (Bitfield-Mask: 0x07)                           */
27861  #define R_OSPI_ACSR_ACSR1_Pos         (3UL)          /*!< ACSR1 (Bit 3)                                         */
27862  #define R_OSPI_ACSR_ACSR1_Msk         (0x38UL)       /*!< ACSR1 (Bitfield-Mask: 0x07)                           */
27863 /* ========================================================  DCSMXR  ========================================================= */
27864  #define R_OSPI_DCSMXR_CTWMX0_Pos      (0UL)          /*!< CTWMX0 (Bit 0)                                        */
27865  #define R_OSPI_DCSMXR_CTWMX0_Msk      (0x1ffUL)      /*!< CTWMX0 (Bitfield-Mask: 0x1ff)                         */
27866  #define R_OSPI_DCSMXR_CTWMX1_Pos      (16UL)         /*!< CTWMX1 (Bit 16)                                       */
27867  #define R_OSPI_DCSMXR_CTWMX1_Msk      (0x1ff0000UL)  /*!< CTWMX1 (Bitfield-Mask: 0x1ff)                         */
27868 /* ========================================================  DWSCTSR  ======================================================== */
27869  #define R_OSPI_DWSCTSR_CTSN0_Pos      (0UL)          /*!< CTSN0 (Bit 0)                                         */
27870  #define R_OSPI_DWSCTSR_CTSN0_Msk      (0x7ffUL)      /*!< CTSN0 (Bitfield-Mask: 0x7ff)                          */
27871  #define R_OSPI_DWSCTSR_CTSN1_Pos      (16UL)         /*!< CTSN1 (Bit 16)                                        */
27872  #define R_OSPI_DWSCTSR_CTSN1_Msk      (0x7ff0000UL)  /*!< CTSN1 (Bitfield-Mask: 0x7ff)                          */
27873 
27874 /* =========================================================================================================================== */
27875 /* ================                                         R_USB_HS0                                         ================ */
27876 /* =========================================================================================================================== */
27877 
27878 /* ========================================================  SYSCFG  ========================================================= */
27879  #define R_USB_HS0_SYSCFG_CNEN_Pos         (8UL)          /*!< CNEN (Bit 8)                                          */
27880  #define R_USB_HS0_SYSCFG_CNEN_Msk         (0x100UL)      /*!< CNEN (Bitfield-Mask: 0x01)                            */
27881  #define R_USB_HS0_SYSCFG_HSE_Pos          (7UL)          /*!< HSE (Bit 7)                                           */
27882  #define R_USB_HS0_SYSCFG_HSE_Msk          (0x80UL)       /*!< HSE (Bitfield-Mask: 0x01)                             */
27883  #define R_USB_HS0_SYSCFG_DCFM_Pos         (6UL)          /*!< DCFM (Bit 6)                                          */
27884  #define R_USB_HS0_SYSCFG_DCFM_Msk         (0x40UL)       /*!< DCFM (Bitfield-Mask: 0x01)                            */
27885  #define R_USB_HS0_SYSCFG_DRPD_Pos         (5UL)          /*!< DRPD (Bit 5)                                          */
27886  #define R_USB_HS0_SYSCFG_DRPD_Msk         (0x20UL)       /*!< DRPD (Bitfield-Mask: 0x01)                            */
27887  #define R_USB_HS0_SYSCFG_DPRPU_Pos        (4UL)          /*!< DPRPU (Bit 4)                                         */
27888  #define R_USB_HS0_SYSCFG_DPRPU_Msk        (0x10UL)       /*!< DPRPU (Bitfield-Mask: 0x01)                           */
27889  #define R_USB_HS0_SYSCFG_USBE_Pos         (0UL)          /*!< USBE (Bit 0)                                          */
27890  #define R_USB_HS0_SYSCFG_USBE_Msk         (0x1UL)        /*!< USBE (Bitfield-Mask: 0x01)                            */
27891 /* ========================================================  BUSWAIT  ======================================================== */
27892  #define R_USB_HS0_BUSWAIT_BWAIT_Pos       (0UL)          /*!< BWAIT (Bit 0)                                         */
27893  #define R_USB_HS0_BUSWAIT_BWAIT_Msk       (0xfUL)        /*!< BWAIT (Bitfield-Mask: 0x0f)                           */
27894 /* ========================================================  SYSSTS0  ======================================================== */
27895  #define R_USB_HS0_SYSSTS0_HTACT_Pos       (6UL)          /*!< HTACT (Bit 6)                                         */
27896  #define R_USB_HS0_SYSSTS0_HTACT_Msk       (0x40UL)       /*!< HTACT (Bitfield-Mask: 0x01)                           */
27897  #define R_USB_HS0_SYSSTS0_SOFEA_Pos       (5UL)          /*!< SOFEA (Bit 5)                                         */
27898  #define R_USB_HS0_SYSSTS0_SOFEA_Msk       (0x20UL)       /*!< SOFEA (Bitfield-Mask: 0x01)                           */
27899  #define R_USB_HS0_SYSSTS0_IDMON_Pos       (2UL)          /*!< IDMON (Bit 2)                                         */
27900  #define R_USB_HS0_SYSSTS0_IDMON_Msk       (0x4UL)        /*!< IDMON (Bitfield-Mask: 0x01)                           */
27901  #define R_USB_HS0_SYSSTS0_LNST_Pos        (0UL)          /*!< LNST (Bit 0)                                          */
27902  #define R_USB_HS0_SYSSTS0_LNST_Msk        (0x3UL)        /*!< LNST (Bitfield-Mask: 0x03)                            */
27903  #define R_USB_HS0_SYSSTS0_OVCMON_Pos      (14UL)         /*!< OVCMON (Bit 14)                                       */
27904  #define R_USB_HS0_SYSSTS0_OVCMON_Msk      (0xc000UL)     /*!< OVCMON (Bitfield-Mask: 0x03)                          */
27905 /* ========================================================  PLLSTA  ========================================================= */
27906  #define R_USB_HS0_PLLSTA_PLLLOCK_Pos      (0UL)          /*!< PLLLOCK (Bit 0)                                       */
27907  #define R_USB_HS0_PLLSTA_PLLLOCK_Msk      (0x1UL)        /*!< PLLLOCK (Bitfield-Mask: 0x01)                         */
27908 /* =======================================================  DVSTCTR0  ======================================================== */
27909  #define R_USB_HS0_DVSTCTR0_HNPBTOA_Pos    (11UL)         /*!< HNPBTOA (Bit 11)                                      */
27910  #define R_USB_HS0_DVSTCTR0_HNPBTOA_Msk    (0x800UL)      /*!< HNPBTOA (Bitfield-Mask: 0x01)                         */
27911  #define R_USB_HS0_DVSTCTR0_EXICEN_Pos     (10UL)         /*!< EXICEN (Bit 10)                                       */
27912  #define R_USB_HS0_DVSTCTR0_EXICEN_Msk     (0x400UL)      /*!< EXICEN (Bitfield-Mask: 0x01)                          */
27913  #define R_USB_HS0_DVSTCTR0_VBUSEN_Pos     (9UL)          /*!< VBUSEN (Bit 9)                                        */
27914  #define R_USB_HS0_DVSTCTR0_VBUSEN_Msk     (0x200UL)      /*!< VBUSEN (Bitfield-Mask: 0x01)                          */
27915  #define R_USB_HS0_DVSTCTR0_WKUP_Pos       (8UL)          /*!< WKUP (Bit 8)                                          */
27916  #define R_USB_HS0_DVSTCTR0_WKUP_Msk       (0x100UL)      /*!< WKUP (Bitfield-Mask: 0x01)                            */
27917  #define R_USB_HS0_DVSTCTR0_RWUPE_Pos      (7UL)          /*!< RWUPE (Bit 7)                                         */
27918  #define R_USB_HS0_DVSTCTR0_RWUPE_Msk      (0x80UL)       /*!< RWUPE (Bitfield-Mask: 0x01)                           */
27919  #define R_USB_HS0_DVSTCTR0_USBRST_Pos     (6UL)          /*!< USBRST (Bit 6)                                        */
27920  #define R_USB_HS0_DVSTCTR0_USBRST_Msk     (0x40UL)       /*!< USBRST (Bitfield-Mask: 0x01)                          */
27921  #define R_USB_HS0_DVSTCTR0_RESUME_Pos     (5UL)          /*!< RESUME (Bit 5)                                        */
27922  #define R_USB_HS0_DVSTCTR0_RESUME_Msk     (0x20UL)       /*!< RESUME (Bitfield-Mask: 0x01)                          */
27923  #define R_USB_HS0_DVSTCTR0_UACT_Pos       (4UL)          /*!< UACT (Bit 4)                                          */
27924  #define R_USB_HS0_DVSTCTR0_UACT_Msk       (0x10UL)       /*!< UACT (Bitfield-Mask: 0x01)                            */
27925  #define R_USB_HS0_DVSTCTR0_RHST_Pos       (0UL)          /*!< RHST (Bit 0)                                          */
27926  #define R_USB_HS0_DVSTCTR0_RHST_Msk       (0x7UL)        /*!< RHST (Bitfield-Mask: 0x07)                            */
27927 /* =======================================================  TESTMODE  ======================================================== */
27928  #define R_USB_HS0_TESTMODE_UTST_Pos       (0UL)          /*!< UTST (Bit 0)                                          */
27929  #define R_USB_HS0_TESTMODE_UTST_Msk       (0xfUL)        /*!< UTST (Bitfield-Mask: 0x0f)                            */
27930 /* =========================================================  CFIFO  ========================================================= */
27931  #define R_USB_HS0_CFIFO_FIFOPORT_Pos      (0UL)          /*!< FIFOPORT (Bit 0)                                      */
27932  #define R_USB_HS0_CFIFO_FIFOPORT_Msk      (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
27933 /* ========================================================  CFIFOL  ========================================================= */
27934 /* ========================================================  CFIFOH  ========================================================= */
27935 /* ========================================================  CFIFOLL  ======================================================== */
27936 /* ========================================================  CFIFOHH  ======================================================== */
27937 /* ========================================================  D0FIFO  ========================================================= */
27938  #define R_USB_HS0_D0FIFO_FIFOPORT_Pos    (0UL)          /*!< FIFOPORT (Bit 0)                                      */
27939  #define R_USB_HS0_D0FIFO_FIFOPORT_Msk    (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
27940 /* ========================================================  D0FIFOL  ======================================================== */
27941 /* ========================================================  D0FIFOH  ======================================================== */
27942 /* =======================================================  D0FIFOLL  ======================================================== */
27943 /* =======================================================  D0FIFOHH  ======================================================== */
27944 /* ========================================================  D1FIFO  ========================================================= */
27945  #define R_USB_HS0_D1FIFO_FIFOPORT_Pos    (0UL)          /*!< FIFOPORT (Bit 0)                                      */
27946  #define R_USB_HS0_D1FIFO_FIFOPORT_Msk    (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
27947 /* ========================================================  D1FIFOL  ======================================================== */
27948 /* ========================================================  D1FIFOH  ======================================================== */
27949 /* =======================================================  D1FIFOLL  ======================================================== */
27950 /* =======================================================  D1FIFOHH  ======================================================== */
27951 /* =======================================================  CFIFOSEL  ======================================================== */
27952  #define R_USB_HS0_CFIFOSEL_RCNT_Pos           (15UL)       /*!< RCNT (Bit 15)                                         */
27953  #define R_USB_HS0_CFIFOSEL_RCNT_Msk           (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
27954  #define R_USB_HS0_CFIFOSEL_REW_Pos            (14UL)       /*!< REW (Bit 14)                                          */
27955  #define R_USB_HS0_CFIFOSEL_REW_Msk            (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
27956  #define R_USB_HS0_CFIFOSEL_MBW_Pos            (10UL)       /*!< MBW (Bit 10)                                          */
27957  #define R_USB_HS0_CFIFOSEL_MBW_Msk            (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
27958  #define R_USB_HS0_CFIFOSEL_BIGEND_Pos         (8UL)        /*!< BIGEND (Bit 8)                                        */
27959  #define R_USB_HS0_CFIFOSEL_BIGEND_Msk         (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
27960  #define R_USB_HS0_CFIFOSEL_ISEL_Pos           (5UL)        /*!< ISEL (Bit 5)                                          */
27961  #define R_USB_HS0_CFIFOSEL_ISEL_Msk           (0x20UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
27962  #define R_USB_HS0_CFIFOSEL_CURPIPE_Pos        (0UL)        /*!< CURPIPE (Bit 0)                                       */
27963  #define R_USB_HS0_CFIFOSEL_CURPIPE_Msk        (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
27964 /* =======================================================  CFIFOCTR  ======================================================== */
27965  #define R_USB_HS0_CFIFOCTR_BVAL_Pos           (15UL)       /*!< BVAL (Bit 15)                                         */
27966  #define R_USB_HS0_CFIFOCTR_BVAL_Msk           (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
27967  #define R_USB_HS0_CFIFOCTR_BCLR_Pos           (14UL)       /*!< BCLR (Bit 14)                                         */
27968  #define R_USB_HS0_CFIFOCTR_BCLR_Msk           (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
27969  #define R_USB_HS0_CFIFOCTR_FRDY_Pos           (13UL)       /*!< FRDY (Bit 13)                                         */
27970  #define R_USB_HS0_CFIFOCTR_FRDY_Msk           (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
27971  #define R_USB_HS0_CFIFOCTR_DTLN_Pos           (0UL)        /*!< DTLN (Bit 0)                                          */
27972  #define R_USB_HS0_CFIFOCTR_DTLN_Msk           (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
27973 /* =======================================================  D0FIFOSEL  ======================================================= */
27974  #define R_USB_HS0_D0FIFOSEL_RCNT_Pos          (15UL)       /*!< RCNT (Bit 15)                                         */
27975  #define R_USB_HS0_D0FIFOSEL_RCNT_Msk          (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
27976  #define R_USB_HS0_D0FIFOSEL_REW_Pos           (14UL)       /*!< REW (Bit 14)                                          */
27977  #define R_USB_HS0_D0FIFOSEL_REW_Msk           (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
27978  #define R_USB_HS0_D0FIFOSEL_DCLRM_Pos         (13UL)       /*!< DCLRM (Bit 13)                                        */
27979  #define R_USB_HS0_D0FIFOSEL_DCLRM_Msk         (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
27980  #define R_USB_HS0_D0FIFOSEL_DREQE_Pos         (12UL)       /*!< DREQE (Bit 12)                                        */
27981  #define R_USB_HS0_D0FIFOSEL_DREQE_Msk         (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
27982  #define R_USB_HS0_D0FIFOSEL_MBW_Pos           (10UL)       /*!< MBW (Bit 10)                                          */
27983  #define R_USB_HS0_D0FIFOSEL_MBW_Msk           (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
27984  #define R_USB_HS0_D0FIFOSEL_BIGEND_Pos        (8UL)        /*!< BIGEND (Bit 8)                                        */
27985  #define R_USB_HS0_D0FIFOSEL_BIGEND_Msk        (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
27986  #define R_USB_HS0_D0FIFOSEL_CURPIPE_Pos       (0UL)        /*!< CURPIPE (Bit 0)                                       */
27987  #define R_USB_HS0_D0FIFOSEL_CURPIPE_Msk       (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
27988 /* =======================================================  D0FIFOCTR  ======================================================= */
27989  #define R_USB_HS0_D0FIFOCTR_BVAL_Pos          (15UL)       /*!< BVAL (Bit 15)                                         */
27990  #define R_USB_HS0_D0FIFOCTR_BVAL_Msk          (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
27991  #define R_USB_HS0_D0FIFOCTR_BCLR_Pos          (14UL)       /*!< BCLR (Bit 14)                                         */
27992  #define R_USB_HS0_D0FIFOCTR_BCLR_Msk          (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
27993  #define R_USB_HS0_D0FIFOCTR_FRDY_Pos          (13UL)       /*!< FRDY (Bit 13)                                         */
27994  #define R_USB_HS0_D0FIFOCTR_FRDY_Msk          (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
27995  #define R_USB_HS0_D0FIFOCTR_DTLN_Pos          (0UL)        /*!< DTLN (Bit 0)                                          */
27996  #define R_USB_HS0_D0FIFOCTR_DTLN_Msk          (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
27997 /* =======================================================  D1FIFOSEL  ======================================================= */
27998  #define R_USB_HS0_D1FIFOSEL_RCNT_Pos          (15UL)       /*!< RCNT (Bit 15)                                         */
27999  #define R_USB_HS0_D1FIFOSEL_RCNT_Msk          (0x8000UL)   /*!< RCNT (Bitfield-Mask: 0x01)                            */
28000  #define R_USB_HS0_D1FIFOSEL_REW_Pos           (14UL)       /*!< REW (Bit 14)                                          */
28001  #define R_USB_HS0_D1FIFOSEL_REW_Msk           (0x4000UL)   /*!< REW (Bitfield-Mask: 0x01)                             */
28002  #define R_USB_HS0_D1FIFOSEL_DCLRM_Pos         (13UL)       /*!< DCLRM (Bit 13)                                        */
28003  #define R_USB_HS0_D1FIFOSEL_DCLRM_Msk         (0x2000UL)   /*!< DCLRM (Bitfield-Mask: 0x01)                           */
28004  #define R_USB_HS0_D1FIFOSEL_DREQE_Pos         (12UL)       /*!< DREQE (Bit 12)                                        */
28005  #define R_USB_HS0_D1FIFOSEL_DREQE_Msk         (0x1000UL)   /*!< DREQE (Bitfield-Mask: 0x01)                           */
28006  #define R_USB_HS0_D1FIFOSEL_MBW_Pos           (10UL)       /*!< MBW (Bit 10)                                          */
28007  #define R_USB_HS0_D1FIFOSEL_MBW_Msk           (0xc00UL)    /*!< MBW (Bitfield-Mask: 0x03)                             */
28008  #define R_USB_HS0_D1FIFOSEL_BIGEND_Pos        (8UL)        /*!< BIGEND (Bit 8)                                        */
28009  #define R_USB_HS0_D1FIFOSEL_BIGEND_Msk        (0x100UL)    /*!< BIGEND (Bitfield-Mask: 0x01)                          */
28010  #define R_USB_HS0_D1FIFOSEL_CURPIPE_Pos       (0UL)        /*!< CURPIPE (Bit 0)                                       */
28011  #define R_USB_HS0_D1FIFOSEL_CURPIPE_Msk       (0xfUL)      /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
28012 /* =======================================================  D1FIFOCTR  ======================================================= */
28013  #define R_USB_HS0_D1FIFOCTR_BVAL_Pos          (15UL)       /*!< BVAL (Bit 15)                                         */
28014  #define R_USB_HS0_D1FIFOCTR_BVAL_Msk          (0x8000UL)   /*!< BVAL (Bitfield-Mask: 0x01)                            */
28015  #define R_USB_HS0_D1FIFOCTR_BCLR_Pos          (14UL)       /*!< BCLR (Bit 14)                                         */
28016  #define R_USB_HS0_D1FIFOCTR_BCLR_Msk          (0x4000UL)   /*!< BCLR (Bitfield-Mask: 0x01)                            */
28017  #define R_USB_HS0_D1FIFOCTR_FRDY_Pos          (13UL)       /*!< FRDY (Bit 13)                                         */
28018  #define R_USB_HS0_D1FIFOCTR_FRDY_Msk          (0x2000UL)   /*!< FRDY (Bitfield-Mask: 0x01)                            */
28019  #define R_USB_HS0_D1FIFOCTR_DTLN_Pos          (0UL)        /*!< DTLN (Bit 0)                                          */
28020  #define R_USB_HS0_D1FIFOCTR_DTLN_Msk          (0xfffUL)    /*!< DTLN (Bitfield-Mask: 0xfff)                           */
28021 /* ========================================================  INTENB0  ======================================================== */
28022  #define R_USB_HS0_INTENB0_VBSE_Pos            (15UL)       /*!< VBSE (Bit 15)                                         */
28023  #define R_USB_HS0_INTENB0_VBSE_Msk            (0x8000UL)   /*!< VBSE (Bitfield-Mask: 0x01)                            */
28024  #define R_USB_HS0_INTENB0_RSME_Pos            (14UL)       /*!< RSME (Bit 14)                                         */
28025  #define R_USB_HS0_INTENB0_RSME_Msk            (0x4000UL)   /*!< RSME (Bitfield-Mask: 0x01)                            */
28026  #define R_USB_HS0_INTENB0_SOFE_Pos            (13UL)       /*!< SOFE (Bit 13)                                         */
28027  #define R_USB_HS0_INTENB0_SOFE_Msk            (0x2000UL)   /*!< SOFE (Bitfield-Mask: 0x01)                            */
28028  #define R_USB_HS0_INTENB0_DVSE_Pos            (12UL)       /*!< DVSE (Bit 12)                                         */
28029  #define R_USB_HS0_INTENB0_DVSE_Msk            (0x1000UL)   /*!< DVSE (Bitfield-Mask: 0x01)                            */
28030  #define R_USB_HS0_INTENB0_CTRE_Pos            (11UL)       /*!< CTRE (Bit 11)                                         */
28031  #define R_USB_HS0_INTENB0_CTRE_Msk            (0x800UL)    /*!< CTRE (Bitfield-Mask: 0x01)                            */
28032  #define R_USB_HS0_INTENB0_BEMPE_Pos           (10UL)       /*!< BEMPE (Bit 10)                                        */
28033  #define R_USB_HS0_INTENB0_BEMPE_Msk           (0x400UL)    /*!< BEMPE (Bitfield-Mask: 0x01)                           */
28034  #define R_USB_HS0_INTENB0_NRDYE_Pos           (9UL)        /*!< NRDYE (Bit 9)                                         */
28035  #define R_USB_HS0_INTENB0_NRDYE_Msk           (0x200UL)    /*!< NRDYE (Bitfield-Mask: 0x01)                           */
28036  #define R_USB_HS0_INTENB0_BRDYE_Pos           (8UL)        /*!< BRDYE (Bit 8)                                         */
28037  #define R_USB_HS0_INTENB0_BRDYE_Msk           (0x100UL)    /*!< BRDYE (Bitfield-Mask: 0x01)                           */
28038 /* ========================================================  INTENB1  ======================================================== */
28039  #define R_USB_HS0_INTENB1_OVRCRE_Pos          (15UL)       /*!< OVRCRE (Bit 15)                                       */
28040  #define R_USB_HS0_INTENB1_OVRCRE_Msk          (0x8000UL)   /*!< OVRCRE (Bitfield-Mask: 0x01)                          */
28041  #define R_USB_HS0_INTENB1_BCHGE_Pos           (14UL)       /*!< BCHGE (Bit 14)                                        */
28042  #define R_USB_HS0_INTENB1_BCHGE_Msk           (0x4000UL)   /*!< BCHGE (Bitfield-Mask: 0x01)                           */
28043  #define R_USB_HS0_INTENB1_DTCHE_Pos           (12UL)       /*!< DTCHE (Bit 12)                                        */
28044  #define R_USB_HS0_INTENB1_DTCHE_Msk           (0x1000UL)   /*!< DTCHE (Bitfield-Mask: 0x01)                           */
28045  #define R_USB_HS0_INTENB1_ATTCHE_Pos          (11UL)       /*!< ATTCHE (Bit 11)                                       */
28046  #define R_USB_HS0_INTENB1_ATTCHE_Msk          (0x800UL)    /*!< ATTCHE (Bitfield-Mask: 0x01)                          */
28047  #define R_USB_HS0_INTENB1_L1RSMENDE_Pos       (9UL)        /*!< L1RSMENDE (Bit 9)                                     */
28048  #define R_USB_HS0_INTENB1_L1RSMENDE_Msk       (0x200UL)    /*!< L1RSMENDE (Bitfield-Mask: 0x01)                       */
28049  #define R_USB_HS0_INTENB1_LPMENDE_Pos         (8UL)        /*!< LPMENDE (Bit 8)                                       */
28050  #define R_USB_HS0_INTENB1_LPMENDE_Msk         (0x100UL)    /*!< LPMENDE (Bitfield-Mask: 0x01)                         */
28051  #define R_USB_HS0_INTENB1_EOFERRE_Pos         (6UL)        /*!< EOFERRE (Bit 6)                                       */
28052  #define R_USB_HS0_INTENB1_EOFERRE_Msk         (0x40UL)     /*!< EOFERRE (Bitfield-Mask: 0x01)                         */
28053  #define R_USB_HS0_INTENB1_SIGNE_Pos           (5UL)        /*!< SIGNE (Bit 5)                                         */
28054  #define R_USB_HS0_INTENB1_SIGNE_Msk           (0x20UL)     /*!< SIGNE (Bitfield-Mask: 0x01)                           */
28055  #define R_USB_HS0_INTENB1_SACKE_Pos           (4UL)        /*!< SACKE (Bit 4)                                         */
28056  #define R_USB_HS0_INTENB1_SACKE_Msk           (0x10UL)     /*!< SACKE (Bitfield-Mask: 0x01)                           */
28057  #define R_USB_HS0_INTENB1_PDDETINTE0_Pos      (0UL)        /*!< PDDETINTE0 (Bit 0)                                    */
28058  #define R_USB_HS0_INTENB1_PDDETINTE0_Msk      (0x1UL)      /*!< PDDETINTE0 (Bitfield-Mask: 0x01)                      */
28059 /* ========================================================  BRDYENB  ======================================================== */
28060  #define R_USB_HS0_BRDYENB_PIPEBRDYE_Pos       (0UL)        /*!< PIPEBRDYE (Bit 0)                                     */
28061  #define R_USB_HS0_BRDYENB_PIPEBRDYE_Msk       (0x3ffUL)    /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff)                      */
28062 /* ========================================================  NRDYENB  ======================================================== */
28063  #define R_USB_HS0_NRDYENB_PIPENRDYE_Pos       (0UL)        /*!< PIPENRDYE (Bit 0)                                     */
28064  #define R_USB_HS0_NRDYENB_PIPENRDYE_Msk       (0x3ffUL)    /*!< PIPENRDYE (Bitfield-Mask: 0x3ff)                      */
28065 /* ========================================================  BEMPENB  ======================================================== */
28066  #define R_USB_HS0_BEMPENB_PIPEBEMPE_Pos       (0UL)        /*!< PIPEBEMPE (Bit 0)                                     */
28067  #define R_USB_HS0_BEMPENB_PIPEBEMPE_Msk       (0x3ffUL)    /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff)                      */
28068 /* ========================================================  SOFCFG  ========================================================= */
28069  #define R_USB_HS0_SOFCFG_TRNENSEL_Pos         (8UL)        /*!< TRNENSEL (Bit 8)                                      */
28070  #define R_USB_HS0_SOFCFG_TRNENSEL_Msk         (0x100UL)    /*!< TRNENSEL (Bitfield-Mask: 0x01)                        */
28071  #define R_USB_HS0_SOFCFG_BRDYM_Pos            (6UL)        /*!< BRDYM (Bit 6)                                         */
28072  #define R_USB_HS0_SOFCFG_BRDYM_Msk            (0x40UL)     /*!< BRDYM (Bitfield-Mask: 0x01)                           */
28073  #define R_USB_HS0_SOFCFG_INTL_Pos             (5UL)        /*!< INTL (Bit 5)                                          */
28074  #define R_USB_HS0_SOFCFG_INTL_Msk             (0x20UL)     /*!< INTL (Bitfield-Mask: 0x01)                            */
28075  #define R_USB_HS0_SOFCFG_EDGESTS_Pos          (4UL)        /*!< EDGESTS (Bit 4)                                       */
28076  #define R_USB_HS0_SOFCFG_EDGESTS_Msk          (0x10UL)     /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
28077 /* ========================================================  PHYSET  ========================================================= */
28078  #define R_USB_HS0_PHYSET_HSEB_Pos             (15UL)       /*!< HSEB (Bit 15)                                         */
28079  #define R_USB_HS0_PHYSET_HSEB_Msk             (0x8000UL)   /*!< HSEB (Bitfield-Mask: 0x01)                            */
28080  #define R_USB_HS0_PHYSET_REPSTART_Pos         (11UL)       /*!< REPSTART (Bit 11)                                     */
28081  #define R_USB_HS0_PHYSET_REPSTART_Msk         (0x800UL)    /*!< REPSTART (Bitfield-Mask: 0x01)                        */
28082  #define R_USB_HS0_PHYSET_REPSEL_Pos           (8UL)        /*!< REPSEL (Bit 8)                                        */
28083  #define R_USB_HS0_PHYSET_REPSEL_Msk           (0x300UL)    /*!< REPSEL (Bitfield-Mask: 0x03)                          */
28084  #define R_USB_HS0_PHYSET_CLKSEL_Pos           (4UL)        /*!< CLKSEL (Bit 4)                                        */
28085  #define R_USB_HS0_PHYSET_CLKSEL_Msk           (0x30UL)     /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
28086  #define R_USB_HS0_PHYSET_CDPEN_Pos            (3UL)        /*!< CDPEN (Bit 3)                                         */
28087  #define R_USB_HS0_PHYSET_CDPEN_Msk            (0x8UL)      /*!< CDPEN (Bitfield-Mask: 0x01)                           */
28088  #define R_USB_HS0_PHYSET_PLLRESET_Pos         (1UL)        /*!< PLLRESET (Bit 1)                                      */
28089  #define R_USB_HS0_PHYSET_PLLRESET_Msk         (0x2UL)      /*!< PLLRESET (Bitfield-Mask: 0x01)                        */
28090  #define R_USB_HS0_PHYSET_DIRPD_Pos            (0UL)        /*!< DIRPD (Bit 0)                                         */
28091  #define R_USB_HS0_PHYSET_DIRPD_Msk            (0x1UL)      /*!< DIRPD (Bitfield-Mask: 0x01)                           */
28092 /* ========================================================  INTSTS0  ======================================================== */
28093  #define R_USB_HS0_INTSTS0_VBINT_Pos           (15UL)       /*!< VBINT (Bit 15)                                        */
28094  #define R_USB_HS0_INTSTS0_VBINT_Msk           (0x8000UL)   /*!< VBINT (Bitfield-Mask: 0x01)                           */
28095  #define R_USB_HS0_INTSTS0_RESM_Pos            (14UL)       /*!< RESM (Bit 14)                                         */
28096  #define R_USB_HS0_INTSTS0_RESM_Msk            (0x4000UL)   /*!< RESM (Bitfield-Mask: 0x01)                            */
28097  #define R_USB_HS0_INTSTS0_SOFR_Pos            (13UL)       /*!< SOFR (Bit 13)                                         */
28098  #define R_USB_HS0_INTSTS0_SOFR_Msk            (0x2000UL)   /*!< SOFR (Bitfield-Mask: 0x01)                            */
28099  #define R_USB_HS0_INTSTS0_DVST_Pos            (12UL)       /*!< DVST (Bit 12)                                         */
28100  #define R_USB_HS0_INTSTS0_DVST_Msk            (0x1000UL)   /*!< DVST (Bitfield-Mask: 0x01)                            */
28101  #define R_USB_HS0_INTSTS0_CTRT_Pos            (11UL)       /*!< CTRT (Bit 11)                                         */
28102  #define R_USB_HS0_INTSTS0_CTRT_Msk            (0x800UL)    /*!< CTRT (Bitfield-Mask: 0x01)                            */
28103  #define R_USB_HS0_INTSTS0_BEMP_Pos            (10UL)       /*!< BEMP (Bit 10)                                         */
28104  #define R_USB_HS0_INTSTS0_BEMP_Msk            (0x400UL)    /*!< BEMP (Bitfield-Mask: 0x01)                            */
28105  #define R_USB_HS0_INTSTS0_NRDY_Pos            (9UL)        /*!< NRDY (Bit 9)                                          */
28106  #define R_USB_HS0_INTSTS0_NRDY_Msk            (0x200UL)    /*!< NRDY (Bitfield-Mask: 0x01)                            */
28107  #define R_USB_HS0_INTSTS0_BRDY_Pos            (8UL)        /*!< BRDY (Bit 8)                                          */
28108  #define R_USB_HS0_INTSTS0_BRDY_Msk            (0x100UL)    /*!< BRDY (Bitfield-Mask: 0x01)                            */
28109  #define R_USB_HS0_INTSTS0_VBSTS_Pos           (7UL)        /*!< VBSTS (Bit 7)                                         */
28110  #define R_USB_HS0_INTSTS0_VBSTS_Msk           (0x80UL)     /*!< VBSTS (Bitfield-Mask: 0x01)                           */
28111  #define R_USB_HS0_INTSTS0_DVSQ_Pos            (4UL)        /*!< DVSQ (Bit 4)                                          */
28112  #define R_USB_HS0_INTSTS0_DVSQ_Msk            (0x70UL)     /*!< DVSQ (Bitfield-Mask: 0x07)                            */
28113  #define R_USB_HS0_INTSTS0_VALID_Pos           (3UL)        /*!< VALID (Bit 3)                                         */
28114  #define R_USB_HS0_INTSTS0_VALID_Msk           (0x8UL)      /*!< VALID (Bitfield-Mask: 0x01)                           */
28115  #define R_USB_HS0_INTSTS0_CTSQ_Pos            (0UL)        /*!< CTSQ (Bit 0)                                          */
28116  #define R_USB_HS0_INTSTS0_CTSQ_Msk            (0x7UL)      /*!< CTSQ (Bitfield-Mask: 0x07)                            */
28117 /* ========================================================  INTSTS1  ======================================================== */
28118  #define R_USB_HS0_INTSTS1_OVRCR_Pos           (15UL)       /*!< OVRCR (Bit 15)                                        */
28119  #define R_USB_HS0_INTSTS1_OVRCR_Msk           (0x8000UL)   /*!< OVRCR (Bitfield-Mask: 0x01)                           */
28120  #define R_USB_HS0_INTSTS1_BCHG_Pos            (14UL)       /*!< BCHG (Bit 14)                                         */
28121  #define R_USB_HS0_INTSTS1_BCHG_Msk            (0x4000UL)   /*!< BCHG (Bitfield-Mask: 0x01)                            */
28122  #define R_USB_HS0_INTSTS1_DTCH_Pos            (12UL)       /*!< DTCH (Bit 12)                                         */
28123  #define R_USB_HS0_INTSTS1_DTCH_Msk            (0x1000UL)   /*!< DTCH (Bitfield-Mask: 0x01)                            */
28124  #define R_USB_HS0_INTSTS1_ATTCH_Pos           (11UL)       /*!< ATTCH (Bit 11)                                        */
28125  #define R_USB_HS0_INTSTS1_ATTCH_Msk           (0x800UL)    /*!< ATTCH (Bitfield-Mask: 0x01)                           */
28126  #define R_USB_HS0_INTSTS1_L1RSMEND_Pos        (9UL)        /*!< L1RSMEND (Bit 9)                                      */
28127  #define R_USB_HS0_INTSTS1_L1RSMEND_Msk        (0x200UL)    /*!< L1RSMEND (Bitfield-Mask: 0x01)                        */
28128  #define R_USB_HS0_INTSTS1_LPMEND_Pos          (8UL)        /*!< LPMEND (Bit 8)                                        */
28129  #define R_USB_HS0_INTSTS1_LPMEND_Msk          (0x100UL)    /*!< LPMEND (Bitfield-Mask: 0x01)                          */
28130  #define R_USB_HS0_INTSTS1_EOFERR_Pos          (6UL)        /*!< EOFERR (Bit 6)                                        */
28131  #define R_USB_HS0_INTSTS1_EOFERR_Msk          (0x40UL)     /*!< EOFERR (Bitfield-Mask: 0x01)                          */
28132  #define R_USB_HS0_INTSTS1_SIGN_Pos            (5UL)        /*!< SIGN (Bit 5)                                          */
28133  #define R_USB_HS0_INTSTS1_SIGN_Msk            (0x20UL)     /*!< SIGN (Bitfield-Mask: 0x01)                            */
28134  #define R_USB_HS0_INTSTS1_SACK_Pos            (4UL)        /*!< SACK (Bit 4)                                          */
28135  #define R_USB_HS0_INTSTS1_SACK_Msk            (0x10UL)     /*!< SACK (Bitfield-Mask: 0x01)                            */
28136  #define R_USB_HS0_INTSTS1_PDDETINT0_Pos       (0UL)        /*!< PDDETINT0 (Bit 0)                                     */
28137  #define R_USB_HS0_INTSTS1_PDDETINT0_Msk       (0x1UL)      /*!< PDDETINT0 (Bitfield-Mask: 0x01)                       */
28138 /* ========================================================  BRDYSTS  ======================================================== */
28139  #define R_USB_HS0_BRDYSTS_PIPEBRDY_Pos        (0UL)        /*!< PIPEBRDY (Bit 0)                                      */
28140  #define R_USB_HS0_BRDYSTS_PIPEBRDY_Msk        (0x3ffUL)    /*!< PIPEBRDY (Bitfield-Mask: 0x3ff)                       */
28141 /* ========================================================  NRDYSTS  ======================================================== */
28142  #define R_USB_HS0_NRDYSTS_PIPENRDY_Pos        (0UL)        /*!< PIPENRDY (Bit 0)                                      */
28143  #define R_USB_HS0_NRDYSTS_PIPENRDY_Msk        (0x3ffUL)    /*!< PIPENRDY (Bitfield-Mask: 0x3ff)                       */
28144 /* ========================================================  BEMPSTS  ======================================================== */
28145  #define R_USB_HS0_BEMPSTS_PIPEBEMP_Pos        (0UL)        /*!< PIPEBEMP (Bit 0)                                      */
28146  #define R_USB_HS0_BEMPSTS_PIPEBEMP_Msk        (0x3ffUL)    /*!< PIPEBEMP (Bitfield-Mask: 0x3ff)                       */
28147 /* ========================================================  FRMNUM  ========================================================= */
28148  #define R_USB_HS0_FRMNUM_OVRN_Pos             (15UL)       /*!< OVRN (Bit 15)                                         */
28149  #define R_USB_HS0_FRMNUM_OVRN_Msk             (0x8000UL)   /*!< OVRN (Bitfield-Mask: 0x01)                            */
28150  #define R_USB_HS0_FRMNUM_CRCE_Pos             (14UL)       /*!< CRCE (Bit 14)                                         */
28151  #define R_USB_HS0_FRMNUM_CRCE_Msk             (0x4000UL)   /*!< CRCE (Bitfield-Mask: 0x01)                            */
28152  #define R_USB_HS0_FRMNUM_FRNM_Pos             (0UL)        /*!< FRNM (Bit 0)                                          */
28153  #define R_USB_HS0_FRMNUM_FRNM_Msk             (0x7ffUL)    /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
28154 /* ========================================================  UFRMNUM  ======================================================== */
28155  #define R_USB_HS0_UFRMNUM_DVCHG_Pos           (15UL)       /*!< DVCHG (Bit 15)                                        */
28156  #define R_USB_HS0_UFRMNUM_DVCHG_Msk           (0x8000UL)   /*!< DVCHG (Bitfield-Mask: 0x01)                           */
28157  #define R_USB_HS0_UFRMNUM_UFRNM_Pos           (0UL)        /*!< UFRNM (Bit 0)                                         */
28158  #define R_USB_HS0_UFRMNUM_UFRNM_Msk           (0x7UL)      /*!< UFRNM (Bitfield-Mask: 0x07)                           */
28159 /* ========================================================  USBADDR  ======================================================== */
28160  #define R_USB_HS0_USBADDR_STSRECOV0_Pos       (8UL)        /*!< STSRECOV0 (Bit 8)                                     */
28161  #define R_USB_HS0_USBADDR_STSRECOV0_Msk       (0x700UL)    /*!< STSRECOV0 (Bitfield-Mask: 0x07)                       */
28162 /* ========================================================  USBREQ  ========================================================= */
28163  #define R_USB_HS0_USBREQ_BREQUEST_Pos         (8UL)        /*!< BREQUEST (Bit 8)                                      */
28164  #define R_USB_HS0_USBREQ_BREQUEST_Msk         (0xff00UL)   /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
28165  #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Pos    (0UL)        /*!< BMREQUESTTYPE (Bit 0)                                 */
28166  #define R_USB_HS0_USBREQ_BMREQUESTTYPE_Msk    (0xffUL)     /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
28167 /* ========================================================  USBVAL  ========================================================= */
28168  #define R_USB_HS0_USBVAL_WVALUE_Pos           (0UL)        /*!< WVALUE (Bit 0)                                        */
28169  #define R_USB_HS0_USBVAL_WVALUE_Msk           (0xffffUL)   /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
28170 /* ========================================================  USBINDX  ======================================================== */
28171  #define R_USB_HS0_USBINDX_WINDEX_Pos          (0UL)        /*!< WINDEX (Bit 0)                                        */
28172  #define R_USB_HS0_USBINDX_WINDEX_Msk          (0xffffUL)   /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
28173 /* ========================================================  USBLENG  ======================================================== */
28174  #define R_USB_HS0_USBLENG_WLENGTH_Pos         (0UL)        /*!< WLENGTH (Bit 0)                                       */
28175  #define R_USB_HS0_USBLENG_WLENGTH_Msk         (0xffffUL)   /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
28176 /* ========================================================  DCPCFG  ========================================================= */
28177  #define R_USB_HS0_DCPCFG_CNTMD_Pos            (8UL)        /*!< CNTMD (Bit 8)                                         */
28178  #define R_USB_HS0_DCPCFG_CNTMD_Msk            (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
28179  #define R_USB_HS0_DCPCFG_SHTNAK_Pos           (7UL)        /*!< SHTNAK (Bit 7)                                        */
28180  #define R_USB_HS0_DCPCFG_SHTNAK_Msk           (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
28181  #define R_USB_HS0_DCPCFG_DIR_Pos              (4UL)        /*!< DIR (Bit 4)                                           */
28182  #define R_USB_HS0_DCPCFG_DIR_Msk              (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
28183 /* ========================================================  DCPMAXP  ======================================================== */
28184  #define R_USB_HS0_DCPMAXP_DEVSEL_Pos          (12UL)       /*!< DEVSEL (Bit 12)                                       */
28185  #define R_USB_HS0_DCPMAXP_DEVSEL_Msk          (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
28186  #define R_USB_HS0_DCPMAXP_MXPS_Pos            (0UL)        /*!< MXPS (Bit 0)                                          */
28187  #define R_USB_HS0_DCPMAXP_MXPS_Msk            (0x7fUL)     /*!< MXPS (Bitfield-Mask: 0x7f)                            */
28188 /* ========================================================  DCPCTR  ========================================================= */
28189  #define R_USB_HS0_DCPCTR_BSTS_Pos             (15UL)       /*!< BSTS (Bit 15)                                         */
28190  #define R_USB_HS0_DCPCTR_BSTS_Msk             (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
28191  #define R_USB_HS0_DCPCTR_SUREQ_Pos            (14UL)       /*!< SUREQ (Bit 14)                                        */
28192  #define R_USB_HS0_DCPCTR_SUREQ_Msk            (0x4000UL)   /*!< SUREQ (Bitfield-Mask: 0x01)                           */
28193  #define R_USB_HS0_DCPCTR_CSCLR_Pos            (13UL)       /*!< CSCLR (Bit 13)                                        */
28194  #define R_USB_HS0_DCPCTR_CSCLR_Msk            (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
28195  #define R_USB_HS0_DCPCTR_CSSTS_Pos            (12UL)       /*!< CSSTS (Bit 12)                                        */
28196  #define R_USB_HS0_DCPCTR_CSSTS_Msk            (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
28197  #define R_USB_HS0_DCPCTR_SUREQCLR_Pos         (11UL)       /*!< SUREQCLR (Bit 11)                                     */
28198  #define R_USB_HS0_DCPCTR_SUREQCLR_Msk         (0x800UL)    /*!< SUREQCLR (Bitfield-Mask: 0x01)                        */
28199  #define R_USB_HS0_DCPCTR_SQCLR_Pos            (8UL)        /*!< SQCLR (Bit 8)                                         */
28200  #define R_USB_HS0_DCPCTR_SQCLR_Msk            (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
28201  #define R_USB_HS0_DCPCTR_SQSET_Pos            (7UL)        /*!< SQSET (Bit 7)                                         */
28202  #define R_USB_HS0_DCPCTR_SQSET_Msk            (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
28203  #define R_USB_HS0_DCPCTR_SQMON_Pos            (6UL)        /*!< SQMON (Bit 6)                                         */
28204  #define R_USB_HS0_DCPCTR_SQMON_Msk            (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
28205  #define R_USB_HS0_DCPCTR_PBUSY_Pos            (5UL)        /*!< PBUSY (Bit 5)                                         */
28206  #define R_USB_HS0_DCPCTR_PBUSY_Msk            (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
28207  #define R_USB_HS0_DCPCTR_PINGE_Pos            (4UL)        /*!< PINGE (Bit 4)                                         */
28208  #define R_USB_HS0_DCPCTR_PINGE_Msk            (0x10UL)     /*!< PINGE (Bitfield-Mask: 0x01)                           */
28209  #define R_USB_HS0_DCPCTR_CCPL_Pos             (2UL)        /*!< CCPL (Bit 2)                                          */
28210  #define R_USB_HS0_DCPCTR_CCPL_Msk             (0x4UL)      /*!< CCPL (Bitfield-Mask: 0x01)                            */
28211  #define R_USB_HS0_DCPCTR_PID_Pos              (0UL)        /*!< PID (Bit 0)                                           */
28212  #define R_USB_HS0_DCPCTR_PID_Msk              (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
28213 /* ========================================================  PIPESEL  ======================================================== */
28214 /* ========================================================  PIPECFG  ======================================================== */
28215  #define R_USB_HS0_PIPECFG_TYPE_Pos            (14UL)       /*!< TYPE (Bit 14)                                         */
28216  #define R_USB_HS0_PIPECFG_TYPE_Msk            (0xc000UL)   /*!< TYPE (Bitfield-Mask: 0x03)                            */
28217  #define R_USB_HS0_PIPECFG_BFRE_Pos            (10UL)       /*!< BFRE (Bit 10)                                         */
28218  #define R_USB_HS0_PIPECFG_BFRE_Msk            (0x400UL)    /*!< BFRE (Bitfield-Mask: 0x01)                            */
28219  #define R_USB_HS0_PIPECFG_DBLB_Pos            (9UL)        /*!< DBLB (Bit 9)                                          */
28220  #define R_USB_HS0_PIPECFG_DBLB_Msk            (0x200UL)    /*!< DBLB (Bitfield-Mask: 0x01)                            */
28221  #define R_USB_HS0_PIPECFG_CNTMD_Pos           (8UL)        /*!< CNTMD (Bit 8)                                         */
28222  #define R_USB_HS0_PIPECFG_CNTMD_Msk           (0x100UL)    /*!< CNTMD (Bitfield-Mask: 0x01)                           */
28223  #define R_USB_HS0_PIPECFG_SHTNAK_Pos          (7UL)        /*!< SHTNAK (Bit 7)                                        */
28224  #define R_USB_HS0_PIPECFG_SHTNAK_Msk          (0x80UL)     /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
28225  #define R_USB_HS0_PIPECFG_DIR_Pos             (4UL)        /*!< DIR (Bit 4)                                           */
28226  #define R_USB_HS0_PIPECFG_DIR_Msk             (0x10UL)     /*!< DIR (Bitfield-Mask: 0x01)                             */
28227  #define R_USB_HS0_PIPECFG_EPNUM_Pos           (0UL)        /*!< EPNUM (Bit 0)                                         */
28228  #define R_USB_HS0_PIPECFG_EPNUM_Msk           (0xfUL)      /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
28229 /* ========================================================  PIPEBUF  ======================================================== */
28230  #define R_USB_HS0_PIPEBUF_BUFSIZE_Pos         (10UL)       /*!< BUFSIZE (Bit 10)                                      */
28231  #define R_USB_HS0_PIPEBUF_BUFSIZE_Msk         (0x7c00UL)   /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
28232  #define R_USB_HS0_PIPEBUF_BUFNMB_Pos          (0UL)        /*!< BUFNMB (Bit 0)                                        */
28233  #define R_USB_HS0_PIPEBUF_BUFNMB_Msk          (0xffUL)     /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
28234 /* =======================================================  PIPEMAXP  ======================================================== */
28235  #define R_USB_HS0_PIPEMAXP_DEVSEL_Pos         (12UL)       /*!< DEVSEL (Bit 12)                                       */
28236  #define R_USB_HS0_PIPEMAXP_DEVSEL_Msk         (0xf000UL)   /*!< DEVSEL (Bitfield-Mask: 0x0f)                          */
28237  #define R_USB_HS0_PIPEMAXP_MXPS_Pos           (0UL)        /*!< MXPS (Bit 0)                                          */
28238  #define R_USB_HS0_PIPEMAXP_MXPS_Msk           (0x7ffUL)    /*!< MXPS (Bitfield-Mask: 0x7ff)                           */
28239 /* =======================================================  PIPEPERI  ======================================================== */
28240  #define R_USB_HS0_PIPEPERI_IFIS_Pos           (12UL)       /*!< IFIS (Bit 12)                                         */
28241  #define R_USB_HS0_PIPEPERI_IFIS_Msk           (0x1000UL)   /*!< IFIS (Bitfield-Mask: 0x01)                            */
28242  #define R_USB_HS0_PIPEPERI_IITV_Pos           (0UL)        /*!< IITV (Bit 0)                                          */
28243  #define R_USB_HS0_PIPEPERI_IITV_Msk           (0x7UL)      /*!< IITV (Bitfield-Mask: 0x07)                            */
28244 /* =======================================================  PIPE_CTR  ======================================================== */
28245  #define R_USB_HS0_PIPE_CTR_BSTS_Pos           (15UL)       /*!< BSTS (Bit 15)                                         */
28246  #define R_USB_HS0_PIPE_CTR_BSTS_Msk           (0x8000UL)   /*!< BSTS (Bitfield-Mask: 0x01)                            */
28247  #define R_USB_HS0_PIPE_CTR_INBUFM_Pos         (14UL)       /*!< INBUFM (Bit 14)                                       */
28248  #define R_USB_HS0_PIPE_CTR_INBUFM_Msk         (0x4000UL)   /*!< INBUFM (Bitfield-Mask: 0x01)                          */
28249  #define R_USB_HS0_PIPE_CTR_CSCLR_Pos          (13UL)       /*!< CSCLR (Bit 13)                                        */
28250  #define R_USB_HS0_PIPE_CTR_CSCLR_Msk          (0x2000UL)   /*!< CSCLR (Bitfield-Mask: 0x01)                           */
28251  #define R_USB_HS0_PIPE_CTR_CSSTS_Pos          (12UL)       /*!< CSSTS (Bit 12)                                        */
28252  #define R_USB_HS0_PIPE_CTR_CSSTS_Msk          (0x1000UL)   /*!< CSSTS (Bitfield-Mask: 0x01)                           */
28253  #define R_USB_HS0_PIPE_CTR_ATREPM_Pos         (10UL)       /*!< ATREPM (Bit 10)                                       */
28254  #define R_USB_HS0_PIPE_CTR_ATREPM_Msk         (0x400UL)    /*!< ATREPM (Bitfield-Mask: 0x01)                          */
28255  #define R_USB_HS0_PIPE_CTR_ACLRM_Pos          (9UL)        /*!< ACLRM (Bit 9)                                         */
28256  #define R_USB_HS0_PIPE_CTR_ACLRM_Msk          (0x200UL)    /*!< ACLRM (Bitfield-Mask: 0x01)                           */
28257  #define R_USB_HS0_PIPE_CTR_SQCLR_Pos          (8UL)        /*!< SQCLR (Bit 8)                                         */
28258  #define R_USB_HS0_PIPE_CTR_SQCLR_Msk          (0x100UL)    /*!< SQCLR (Bitfield-Mask: 0x01)                           */
28259  #define R_USB_HS0_PIPE_CTR_SQSET_Pos          (7UL)        /*!< SQSET (Bit 7)                                         */
28260  #define R_USB_HS0_PIPE_CTR_SQSET_Msk          (0x80UL)     /*!< SQSET (Bitfield-Mask: 0x01)                           */
28261  #define R_USB_HS0_PIPE_CTR_SQMON_Pos          (6UL)        /*!< SQMON (Bit 6)                                         */
28262  #define R_USB_HS0_PIPE_CTR_SQMON_Msk          (0x40UL)     /*!< SQMON (Bitfield-Mask: 0x01)                           */
28263  #define R_USB_HS0_PIPE_CTR_PBUSY_Pos          (5UL)        /*!< PBUSY (Bit 5)                                         */
28264  #define R_USB_HS0_PIPE_CTR_PBUSY_Msk          (0x20UL)     /*!< PBUSY (Bitfield-Mask: 0x01)                           */
28265  #define R_USB_HS0_PIPE_CTR_PID_Pos            (0UL)        /*!< PID (Bit 0)                                           */
28266  #define R_USB_HS0_PIPE_CTR_PID_Msk            (0x3UL)      /*!< PID (Bitfield-Mask: 0x03)                             */
28267 /* ========================================================  DEVADD  ========================================================= */
28268  #define R_USB_HS0_DEVADD_UPPHUB_Pos           (11UL)       /*!< UPPHUB (Bit 11)                                       */
28269  #define R_USB_HS0_DEVADD_UPPHUB_Msk           (0x7800UL)   /*!< UPPHUB (Bitfield-Mask: 0x0f)                          */
28270  #define R_USB_HS0_DEVADD_HUBPORT_Pos          (8UL)        /*!< HUBPORT (Bit 8)                                       */
28271  #define R_USB_HS0_DEVADD_HUBPORT_Msk          (0x700UL)    /*!< HUBPORT (Bitfield-Mask: 0x07)                         */
28272  #define R_USB_HS0_DEVADD_USBSPD_Pos           (6UL)        /*!< USBSPD (Bit 6)                                        */
28273  #define R_USB_HS0_DEVADD_USBSPD_Msk           (0xc0UL)     /*!< USBSPD (Bitfield-Mask: 0x03)                          */
28274 /* ========================================================  LPCTRL  ========================================================= */
28275  #define R_USB_HS0_LPCTRL_HWUPM_Pos            (7UL)        /*!< HWUPM (Bit 7)                                         */
28276  #define R_USB_HS0_LPCTRL_HWUPM_Msk            (0x80UL)     /*!< HWUPM (Bitfield-Mask: 0x01)                           */
28277 /* =========================================================  LPSTS  ========================================================= */
28278  #define R_USB_HS0_LPSTS_SUSPENDM_Pos          (14UL)       /*!< SUSPENDM (Bit 14)                                     */
28279  #define R_USB_HS0_LPSTS_SUSPENDM_Msk          (0x4000UL)   /*!< SUSPENDM (Bitfield-Mask: 0x01)                        */
28280 /* ========================================================  BCCTRL  ========================================================= */
28281  #define R_USB_HS0_BCCTRL_PDDETSTS_Pos         (9UL)        /*!< PDDETSTS (Bit 9)                                      */
28282  #define R_USB_HS0_BCCTRL_PDDETSTS_Msk         (0x200UL)    /*!< PDDETSTS (Bitfield-Mask: 0x01)                        */
28283  #define R_USB_HS0_BCCTRL_CHGDETSTS_Pos        (8UL)        /*!< CHGDETSTS (Bit 8)                                     */
28284  #define R_USB_HS0_BCCTRL_CHGDETSTS_Msk        (0x100UL)    /*!< CHGDETSTS (Bitfield-Mask: 0x01)                       */
28285  #define R_USB_HS0_BCCTRL_DCPMODE_Pos          (5UL)        /*!< DCPMODE (Bit 5)                                       */
28286  #define R_USB_HS0_BCCTRL_DCPMODE_Msk          (0x20UL)     /*!< DCPMODE (Bitfield-Mask: 0x01)                         */
28287  #define R_USB_HS0_BCCTRL_VDMSRCE_Pos          (4UL)        /*!< VDMSRCE (Bit 4)                                       */
28288  #define R_USB_HS0_BCCTRL_VDMSRCE_Msk          (0x10UL)     /*!< VDMSRCE (Bitfield-Mask: 0x01)                         */
28289  #define R_USB_HS0_BCCTRL_IDPSINKE_Pos         (3UL)        /*!< IDPSINKE (Bit 3)                                      */
28290  #define R_USB_HS0_BCCTRL_IDPSINKE_Msk         (0x8UL)      /*!< IDPSINKE (Bitfield-Mask: 0x01)                        */
28291  #define R_USB_HS0_BCCTRL_VDPSRCE_Pos          (2UL)        /*!< VDPSRCE (Bit 2)                                       */
28292  #define R_USB_HS0_BCCTRL_VDPSRCE_Msk          (0x4UL)      /*!< VDPSRCE (Bitfield-Mask: 0x01)                         */
28293  #define R_USB_HS0_BCCTRL_IDMSINKE_Pos         (1UL)        /*!< IDMSINKE (Bit 1)                                      */
28294  #define R_USB_HS0_BCCTRL_IDMSINKE_Msk         (0x2UL)      /*!< IDMSINKE (Bitfield-Mask: 0x01)                        */
28295  #define R_USB_HS0_BCCTRL_IDPSRCE_Pos          (0UL)        /*!< IDPSRCE (Bit 0)                                       */
28296  #define R_USB_HS0_BCCTRL_IDPSRCE_Msk          (0x1UL)      /*!< IDPSRCE (Bitfield-Mask: 0x01)                         */
28297 /* =======================================================  PL1CTRL1  ======================================================== */
28298  #define R_USB_HS0_PL1CTRL1_L1EXTMD_Pos        (14UL)       /*!< L1EXTMD (Bit 14)                                      */
28299  #define R_USB_HS0_PL1CTRL1_L1EXTMD_Msk        (0x4000UL)   /*!< L1EXTMD (Bitfield-Mask: 0x01)                         */
28300  #define R_USB_HS0_PL1CTRL1_HIRDTHR_Pos        (8UL)        /*!< HIRDTHR (Bit 8)                                       */
28301  #define R_USB_HS0_PL1CTRL1_HIRDTHR_Msk        (0xf00UL)    /*!< HIRDTHR (Bitfield-Mask: 0x0f)                         */
28302  #define R_USB_HS0_PL1CTRL1_DVSQ_Pos           (4UL)        /*!< DVSQ (Bit 4)                                          */
28303  #define R_USB_HS0_PL1CTRL1_DVSQ_Msk           (0xf0UL)     /*!< DVSQ (Bitfield-Mask: 0x0f)                            */
28304  #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Pos       (3UL)        /*!< L1NEGOMD (Bit 3)                                      */
28305  #define R_USB_HS0_PL1CTRL1_L1NEGOMD_Msk       (0x8UL)      /*!< L1NEGOMD (Bitfield-Mask: 0x01)                        */
28306  #define R_USB_HS0_PL1CTRL1_L1RESPMD_Pos       (1UL)        /*!< L1RESPMD (Bit 1)                                      */
28307  #define R_USB_HS0_PL1CTRL1_L1RESPMD_Msk       (0x6UL)      /*!< L1RESPMD (Bitfield-Mask: 0x03)                        */
28308  #define R_USB_HS0_PL1CTRL1_L1RESPEN_Pos       (0UL)        /*!< L1RESPEN (Bit 0)                                      */
28309  #define R_USB_HS0_PL1CTRL1_L1RESPEN_Msk       (0x1UL)      /*!< L1RESPEN (Bitfield-Mask: 0x01)                        */
28310 /* =======================================================  PL1CTRL2  ======================================================== */
28311  #define R_USB_HS0_PL1CTRL2_RWEMON_Pos         (12UL)       /*!< RWEMON (Bit 12)                                       */
28312  #define R_USB_HS0_PL1CTRL2_RWEMON_Msk         (0x1000UL)   /*!< RWEMON (Bitfield-Mask: 0x01)                          */
28313  #define R_USB_HS0_PL1CTRL2_HIRDMON_Pos        (8UL)        /*!< HIRDMON (Bit 8)                                       */
28314  #define R_USB_HS0_PL1CTRL2_HIRDMON_Msk        (0xf00UL)    /*!< HIRDMON (Bitfield-Mask: 0x0f)                         */
28315 /* =======================================================  HL1CTRL1  ======================================================== */
28316  #define R_USB_HS0_HL1CTRL1_L1STATUS_Pos       (1UL)        /*!< L1STATUS (Bit 1)                                      */
28317  #define R_USB_HS0_HL1CTRL1_L1STATUS_Msk       (0x6UL)      /*!< L1STATUS (Bitfield-Mask: 0x03)                        */
28318  #define R_USB_HS0_HL1CTRL1_L1REQ_Pos          (0UL)        /*!< L1REQ (Bit 0)                                         */
28319  #define R_USB_HS0_HL1CTRL1_L1REQ_Msk          (0x1UL)      /*!< L1REQ (Bitfield-Mask: 0x01)                           */
28320 /* =======================================================  HL1CTRL2  ======================================================== */
28321  #define R_USB_HS0_HL1CTRL2_BESL_Pos           (15UL)       /*!< BESL (Bit 15)                                         */
28322  #define R_USB_HS0_HL1CTRL2_BESL_Msk           (0x8000UL)   /*!< BESL (Bitfield-Mask: 0x01)                            */
28323  #define R_USB_HS0_HL1CTRL2_L1RWE_Pos          (12UL)       /*!< L1RWE (Bit 12)                                        */
28324  #define R_USB_HS0_HL1CTRL2_L1RWE_Msk          (0x1000UL)   /*!< L1RWE (Bitfield-Mask: 0x01)                           */
28325  #define R_USB_HS0_HL1CTRL2_HIRD_Pos           (8UL)        /*!< HIRD (Bit 8)                                          */
28326  #define R_USB_HS0_HL1CTRL2_HIRD_Msk           (0xf00UL)    /*!< HIRD (Bitfield-Mask: 0x0f)                            */
28327  #define R_USB_HS0_HL1CTRL2_L1ADDR_Pos         (0UL)        /*!< L1ADDR (Bit 0)                                        */
28328  #define R_USB_HS0_HL1CTRL2_L1ADDR_Msk         (0xfUL)      /*!< L1ADDR (Bitfield-Mask: 0x0f)                          */
28329 /* =======================================================  PHYTRIM1  ======================================================== */
28330  #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Pos      (12UL)       /*!< IMPOFFSET (Bit 12)                                    */
28331  #define R_USB_HS0_PHYTRIM1_IMPOFFSET_Msk      (0x7000UL)   /*!< IMPOFFSET (Bitfield-Mask: 0x07)                       */
28332  #define R_USB_HS0_PHYTRIM1_HSIUP_Pos          (8UL)        /*!< HSIUP (Bit 8)                                         */
28333  #define R_USB_HS0_PHYTRIM1_HSIUP_Msk          (0xf00UL)    /*!< HSIUP (Bitfield-Mask: 0x0f)                           */
28334  #define R_USB_HS0_PHYTRIM1_PCOMPENB_Pos       (7UL)        /*!< PCOMPENB (Bit 7)                                      */
28335  #define R_USB_HS0_PHYTRIM1_PCOMPENB_Msk       (0x80UL)     /*!< PCOMPENB (Bitfield-Mask: 0x01)                        */
28336  #define R_USB_HS0_PHYTRIM1_DFALL_Pos          (2UL)        /*!< DFALL (Bit 2)                                         */
28337  #define R_USB_HS0_PHYTRIM1_DFALL_Msk          (0xcUL)      /*!< DFALL (Bitfield-Mask: 0x03)                           */
28338  #define R_USB_HS0_PHYTRIM1_DRISE_Pos          (0UL)        /*!< DRISE (Bit 0)                                         */
28339  #define R_USB_HS0_PHYTRIM1_DRISE_Msk          (0x3UL)      /*!< DRISE (Bitfield-Mask: 0x03)                           */
28340 /* =======================================================  PHYTRIM2  ======================================================== */
28341  #define R_USB_HS0_PHYTRIM2_DIS_Pos            (12UL)       /*!< DIS (Bit 12)                                          */
28342  #define R_USB_HS0_PHYTRIM2_DIS_Msk            (0x7000UL)   /*!< DIS (Bitfield-Mask: 0x07)                             */
28343  #define R_USB_HS0_PHYTRIM2_PDR_Pos            (8UL)        /*!< PDR (Bit 8)                                           */
28344  #define R_USB_HS0_PHYTRIM2_PDR_Msk            (0x300UL)    /*!< PDR (Bitfield-Mask: 0x03)                             */
28345  #define R_USB_HS0_PHYTRIM2_HSRXENMO_Pos       (7UL)        /*!< HSRXENMO (Bit 7)                                      */
28346  #define R_USB_HS0_PHYTRIM2_HSRXENMO_Msk       (0x80UL)     /*!< HSRXENMO (Bitfield-Mask: 0x01)                        */
28347  #define R_USB_HS0_PHYTRIM2_SQU_Pos            (0UL)        /*!< SQU (Bit 0)                                           */
28348  #define R_USB_HS0_PHYTRIM2_SQU_Msk            (0xfUL)      /*!< SQU (Bitfield-Mask: 0x0f)                             */
28349 /* ========================================================  DPUSR0R  ======================================================== */
28350  #define R_USB_HS0_DPUSR0R_DVBSTSHM_Pos        (23UL)       /*!< DVBSTSHM (Bit 23)                                     */
28351  #define R_USB_HS0_DPUSR0R_DVBSTSHM_Msk        (0x800000UL) /*!< DVBSTSHM (Bitfield-Mask: 0x01)                        */
28352  #define R_USB_HS0_DPUSR0R_DOVCBHM_Pos         (21UL)       /*!< DOVCBHM (Bit 21)                                      */
28353  #define R_USB_HS0_DPUSR0R_DOVCBHM_Msk         (0x200000UL) /*!< DOVCBHM (Bitfield-Mask: 0x01)                         */
28354  #define R_USB_HS0_DPUSR0R_DOVCAHM_Pos         (20UL)       /*!< DOVCAHM (Bit 20)                                      */
28355  #define R_USB_HS0_DPUSR0R_DOVCAHM_Msk         (0x100000UL) /*!< DOVCAHM (Bitfield-Mask: 0x01)                         */
28356 /* ========================================================  DPUSR1R  ======================================================== */
28357  #define R_USB_HS0_DPUSR1R_DVBSTSH_Pos         (23UL)       /*!< DVBSTSH (Bit 23)                                      */
28358  #define R_USB_HS0_DPUSR1R_DVBSTSH_Msk         (0x800000UL) /*!< DVBSTSH (Bitfield-Mask: 0x01)                         */
28359  #define R_USB_HS0_DPUSR1R_DOVCBH_Pos          (21UL)       /*!< DOVCBH (Bit 21)                                       */
28360  #define R_USB_HS0_DPUSR1R_DOVCBH_Msk          (0x200000UL) /*!< DOVCBH (Bitfield-Mask: 0x01)                          */
28361  #define R_USB_HS0_DPUSR1R_DOVCAH_Pos          (20UL)       /*!< DOVCAH (Bit 20)                                       */
28362  #define R_USB_HS0_DPUSR1R_DOVCAH_Msk          (0x100000UL) /*!< DOVCAH (Bitfield-Mask: 0x01)                          */
28363  #define R_USB_HS0_DPUSR1R_DVBSTSHE_Pos        (7UL)        /*!< DVBSTSHE (Bit 7)                                      */
28364  #define R_USB_HS0_DPUSR1R_DVBSTSHE_Msk        (0x80UL)     /*!< DVBSTSHE (Bitfield-Mask: 0x01)                        */
28365  #define R_USB_HS0_DPUSR1R_DOVCBHE_Pos         (5UL)        /*!< DOVCBHE (Bit 5)                                       */
28366  #define R_USB_HS0_DPUSR1R_DOVCBHE_Msk         (0x20UL)     /*!< DOVCBHE (Bitfield-Mask: 0x01)                         */
28367  #define R_USB_HS0_DPUSR1R_DOVCAHE_Pos         (4UL)        /*!< DOVCAHE (Bit 4)                                       */
28368  #define R_USB_HS0_DPUSR1R_DOVCAHE_Msk         (0x10UL)     /*!< DOVCAHE (Bitfield-Mask: 0x01)                         */
28369 /* ========================================================  DPUSR2R  ======================================================== */
28370  #define R_USB_HS0_DPUSR2R_DMINTE_Pos          (9UL)        /*!< DMINTE (Bit 9)                                        */
28371  #define R_USB_HS0_DPUSR2R_DMINTE_Msk          (0x200UL)    /*!< DMINTE (Bitfield-Mask: 0x01)                          */
28372  #define R_USB_HS0_DPUSR2R_DPINTE_Pos          (8UL)        /*!< DPINTE (Bit 8)                                        */
28373  #define R_USB_HS0_DPUSR2R_DPINTE_Msk          (0x100UL)    /*!< DPINTE (Bitfield-Mask: 0x01)                          */
28374  #define R_USB_HS0_DPUSR2R_DMVAL_Pos           (5UL)        /*!< DMVAL (Bit 5)                                         */
28375  #define R_USB_HS0_DPUSR2R_DMVAL_Msk           (0x20UL)     /*!< DMVAL (Bitfield-Mask: 0x01)                           */
28376  #define R_USB_HS0_DPUSR2R_DPVAL_Pos           (4UL)        /*!< DPVAL (Bit 4)                                         */
28377  #define R_USB_HS0_DPUSR2R_DPVAL_Msk           (0x10UL)     /*!< DPVAL (Bitfield-Mask: 0x01)                           */
28378  #define R_USB_HS0_DPUSR2R_DMINT_Pos           (1UL)        /*!< DMINT (Bit 1)                                         */
28379  #define R_USB_HS0_DPUSR2R_DMINT_Msk           (0x2UL)      /*!< DMINT (Bitfield-Mask: 0x01)                           */
28380  #define R_USB_HS0_DPUSR2R_DPINT_Pos           (0UL)        /*!< DPINT (Bit 0)                                         */
28381  #define R_USB_HS0_DPUSR2R_DPINT_Msk           (0x1UL)      /*!< DPINT (Bitfield-Mask: 0x01)                           */
28382 /* ========================================================  DPUSRCR  ======================================================== */
28383  #define R_USB_HS0_DPUSRCR_FIXPHYPD_Pos        (1UL)        /*!< FIXPHYPD (Bit 1)                                      */
28384  #define R_USB_HS0_DPUSRCR_FIXPHYPD_Msk        (0x2UL)      /*!< FIXPHYPD (Bitfield-Mask: 0x01)                        */
28385  #define R_USB_HS0_DPUSRCR_FIXPHY_Pos          (0UL)        /*!< FIXPHY (Bit 0)                                        */
28386  #define R_USB_HS0_DPUSRCR_FIXPHY_Msk          (0x1UL)      /*!< FIXPHY (Bitfield-Mask: 0x01)                          */
28387 
28388 /* =========================================================================================================================== */
28389 /* ================                                          R_AGTX0                                          ================ */
28390 /* =========================================================================================================================== */
28391 
28392 /* =========================================================================================================================== */
28393 /* ================                                          R_FLAD                                           ================ */
28394 /* =========================================================================================================================== */
28395 
28396 /* ========================================================  FCKMHZ  ========================================================= */
28397  #define R_FLAD_FCKMHZ_FCKMHZ_Pos    (0UL)    /*!< FCKMHZ (Bit 0)                                        */
28398  #define R_FLAD_FCKMHZ_FCKMHZ_Msk    (0xffUL) /*!< FCKMHZ (Bitfield-Mask: 0xff)                          */
28399 
28400 /** @} */ /* End of group PosMask_peripherals */
28401 
28402  #ifdef __cplusplus
28403 }
28404  #endif
28405 
28406 #endif                                 /* R7FA6M5BH_H */
28407 
28408 /** @} */ /* End of group R7FA6M5BH */
28409 
28410 /** @} */ /* End of group Renesas Electronics Corporation */
28411