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Searched refs:R_CANFD_CFDC_CTR_CHMDC_Msk (Results 1 – 11 of 11) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/r_canfd/
Dr_canfd.c414 p_reg->CFDC[interlaced_channel].CTR = p_extend->error_interrupts | R_CANFD_CFDC_CTR_CHMDC_Msk; in R_CANFD_Open()
1555 if ((cfdcnctr & R_CANFD_CFDC_CTR_CHMDC_Msk) && !(operation_mode & CAN_OPERATION_MODE_RESET)) in r_canfd_mode_transition()
/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iobitmasks/
Dcanfd_iobitmask.h27 #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_canfd/
Dr_canfd.c425 p_reg->CFDC[interlaced_channel].CTR = p_extend->error_interrupts | R_CANFD_CFDC_CTR_CHMDC_Msk; in R_CANFD_Open()
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA4E2B9.h16357 …#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro
DR7FA6E2BB.h16563 …#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro
DR7FA4L1BD.h17896 …#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro
DR7FA6M5BH.h19838 …#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro
DR7FA8T1AH.h20711 …#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro
DR7FA8M1AH.h22686 …#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro
DR7FA8D1BH.h30539 …#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h30957 …#define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) … macro