1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /*******************************************************************************************************************//**
8 * @defgroup BSP_IO BSP I/O access
9 * @ingroup RENESAS_COMMON
10 * @brief This module provides basic read/write access to port pins.
11 *
12 * @{
13 **********************************************************************************************************************/
14
15 #ifndef BSP_IO_H
16 #define BSP_IO_H
17
18 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
19 FSP_HEADER
20
21 /***********************************************************************************************************************
22 * Macro definitions
23 **********************************************************************************************************************/
24
25 /* Private definition to set enumeration values. */
26 #define BSP_IO_PRV_8BIT_MASK (0xFF)
27 #define BSP_IO_PRV_PIN_MASK (1U)
28 #define BSP_IO_PRV_PORT_OFFSET (8U)
29 #define BSP_IO_PRV_PFCWE_MASK (0xFFFFFFBF)
30 #define BSP_IO_PRV_OENWE_MASK (0xFFFFFFDF)
31 #define BSP_IO_PRV_SET_OEN_ENABLE (0U)
32 #define BSP_IO_PRV_SET_SSEL0_SELCTL2 (0x1000U)
33 #define BSP_IO_PRV_SET_SSEL1_SELCTL0 (0x0100U)
34 #define BSP_IO_PWPR_B0WI_OFFSET (7U)
35 #define BSP_IO_PWPR_PFSWE_OFFSET (6U)
36 #define BSP_IO_PWPR_OENWE_OFFSET (5U)
37 #define BSP_IO_PM_PM_OUTPUT (3U)
38
39 #define BSP_IO_PRV_P_REG_BASE_SET(base) BSP_IO_PRV_P_REG_BASE(base)
40 #define BSP_IO_PRV_P_REG_BASE(base) (&R_GPIO->P ## base)
41 #define BSP_IO_PRV_PM_REG_BASE_SET(base) BSP_IO_PRV_PM_REG_BASE(base)
42 #define BSP_IO_PRV_PM_REG_BASE(base) (&R_GPIO->PM ## base)
43 #define BSP_IO_PRV_PIN_REG_BASE_SET(base) BSP_IO_PRV_PIN_REG_BASE(base)
44 #define BSP_IO_PRV_PIN_REG_BASE(base) (&R_GPIO->PIN ## base)
45
46 /***********************************************************************************************************************
47 * Typedef definitions
48 **********************************************************************************************************************/
49
50 /** Levels that can be set and read for individual pins */
51 typedef enum e_bsp_io_level
52 {
53 BSP_IO_LEVEL_LOW = 0, ///< Low
54 BSP_IO_LEVEL_HIGH ///< High
55 } bsp_io_level_t;
56
57 /** Direction of individual pins */
58 typedef enum e_bsp_io_dir
59 {
60 BSP_IO_DIRECTION_HIZ = 0x0, ///< Hi-Z
61 BSP_IO_DIRECTION_INPUT = 0x4, ///< Input
62 BSP_IO_DIRECTION_OUTPUT = 0x8, ///< Output (Input disable)
63 BSP_IO_DIRECTION_OUTPUT_WITH_INPUT_ENABLE = 0xC ///< Output (Input enable)
64 } bsp_io_direction_t;
65
66 #ifndef BSP_OVERRIDE_BSP_PORT_T
67
68 /** Superset list of all possible IO ports. */
69 typedef enum e_bsp_io_port
70 {
71 BSP_IO_PORT_00 = 0x0000, ///< IO port 0
72 BSP_IO_PORT_01 = 0x0100, ///< IO port 1
73 BSP_IO_PORT_02 = 0x0200, ///< IO port 2
74 BSP_IO_PORT_03 = 0x0300, ///< IO port 3
75 BSP_IO_PORT_04 = 0x0400, ///< IO port 4
76 BSP_IO_PORT_05 = 0x0500, ///< IO port 5
77 BSP_IO_PORT_06 = 0x0600, ///< IO port 6
78 BSP_IO_PORT_07 = 0x0700, ///< IO port 7
79 BSP_IO_PORT_08 = 0x0800, ///< IO port 8
80 BSP_IO_PORT_09 = 0x0900, ///< IO port 9
81 BSP_IO_PORT_10 = 0x0A00, ///< IO port 10
82 BSP_IO_PORT_11 = 0x0B00, ///< IO port 11
83 BSP_IO_PORT_12 = 0x0C00, ///< IO port 12
84 BSP_IO_PORT_13 = 0x0D00, ///< IO port 13
85 BSP_IO_PORT_14 = 0x0E00, ///< IO port 14
86 BSP_IO_PORT_15 = 0x0F00, ///< IO port 15
87 BSP_IO_PORT_16 = 0x1000, ///< IO port 16
88 BSP_IO_PORT_17 = 0x1100, ///< IO port 17
89 BSP_IO_PORT_18 = 0x1200, ///< IO port 18
90 BSP_IO_PORT_19 = 0x1300, ///< IO port 19
91 BSP_IO_PORT_20 = 0x1400, ///< IO port 20
92 BSP_IO_PORT_21 = 0x1500, ///< IO port 21
93 BSP_IO_PORT_22 = 0x1600, ///< IO port 22
94 BSP_IO_PORT_23 = 0x1700, ///< IO port 23
95 BSP_IO_PORT_24 = 0x1800, ///< IO port 24
96 BSP_IO_PORT_25 = 0x1900, ///< IO port 25
97 BSP_IO_PORT_26 = 0x1A00, ///< IO port 26
98 BSP_IO_PORT_27 = 0x1B00, ///< IO port 27
99 BSP_IO_PORT_28 = 0x1C00, ///< IO port 28
100 BSP_IO_PORT_29 = 0x1D00, ///< IO port 29
101 BSP_IO_PORT_30 = 0x1E00, ///< IO port 30
102 BSP_IO_PORT_31 = 0x1F00, ///< IO port 31
103 BSP_IO_PORT_32 = 0x2000, ///< IO port 32
104 BSP_IO_PORT_33 = 0x2100, ///< IO port 33
105 BSP_IO_PORT_34 = 0x2200, ///< IO port 34
106 BSP_IO_PORT_35 = 0x2300, ///< IO port 35
107 BSP_IO_PORT_36 = 0x2400, ///< IO port 36
108 BSP_IO_PORT_37 = 0x2500, ///< IO port 37
109 BSP_IO_PORT_38 = 0x2600, ///< IO port 38
110 BSP_IO_PORT_39 = 0x2700, ///< IO port 39
111 BSP_IO_PORT_40 = 0x2800, ///< IO port 40
112 BSP_IO_PORT_41 = 0x2900, ///< IO port 41
113 BSP_IO_PORT_42 = 0x2A00, ///< IO port 42
114 BSP_IO_PORT_43 = 0x2B00, ///< IO port 43
115 BSP_IO_PORT_44 = 0x2C00, ///< IO port 44
116 BSP_IO_PORT_45 = 0x2D00, ///< IO port 45
117 BSP_IO_PORT_46 = 0x2E00, ///< IO port 46
118 BSP_IO_PORT_47 = 0x2F00, ///< IO port 47
119 BSP_IO_PORT_48 = 0x3000, ///< IO port 48
120 } bsp_io_port_t;
121
122 #endif
123
124 #ifndef BSP_OVERRIDE_BSP_PIN_T
125
126 /** Superset list of all possible IO port pins. */
127 typedef enum e_bsp_io_port_pin_t
128 {
129 BSP_IO_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0
130 BSP_IO_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1
131
132 BSP_IO_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0
133 BSP_IO_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1
134
135 BSP_IO_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0
136 BSP_IO_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1
137
138 BSP_IO_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0
139 BSP_IO_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1
140
141 BSP_IO_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0
142 BSP_IO_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1
143
144 BSP_IO_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0
145 BSP_IO_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1
146 BSP_IO_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2
147
148 BSP_IO_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0
149 BSP_IO_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1
150
151 BSP_IO_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0
152 BSP_IO_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1
153 BSP_IO_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2
154
155 BSP_IO_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0
156 BSP_IO_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1
157 BSP_IO_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2
158
159 BSP_IO_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0
160 BSP_IO_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1
161
162 BSP_IO_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0
163 BSP_IO_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1
164
165 BSP_IO_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0
166 BSP_IO_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1
167
168 BSP_IO_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0
169 BSP_IO_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1
170
171 BSP_IO_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0
172 BSP_IO_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1
173 BSP_IO_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2
174
175 BSP_IO_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0
176 BSP_IO_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1
177
178 BSP_IO_PORT_15_PIN_00 = 0x0F00, ///< IO port 15 pin 0
179 BSP_IO_PORT_15_PIN_01 = 0x0F01, ///< IO port 15 pin 1
180
181 BSP_IO_PORT_16_PIN_00 = 0x1000, ///< IO port 16 pin 0
182 BSP_IO_PORT_16_PIN_01 = 0x1001, ///< IO port 16 pin 1
183
184 BSP_IO_PORT_17_PIN_00 = 0x1100, ///< IO port 17 pin 0
185 BSP_IO_PORT_17_PIN_01 = 0x1101, ///< IO port 17 pin 1
186 BSP_IO_PORT_17_PIN_02 = 0x1102, ///< IO port 17 pin 2
187
188 BSP_IO_PORT_18_PIN_00 = 0x1200, ///< IO port 18 pin 0
189 BSP_IO_PORT_18_PIN_01 = 0x1201, ///< IO port 18 pin 1
190
191 BSP_IO_PORT_19_PIN_00 = 0x1300, ///< IO port 19 pin 0
192 BSP_IO_PORT_19_PIN_01 = 0x1301, ///< IO port 19 pin 1
193
194 BSP_IO_PORT_20_PIN_00 = 0x1400, ///< IO port 20 pin 0
195 BSP_IO_PORT_20_PIN_01 = 0x1401, ///< IO port 20 pin 1
196 BSP_IO_PORT_20_PIN_02 = 0x1402, ///< IO port 20 pin 2
197
198 BSP_IO_PORT_21_PIN_00 = 0x1500, ///< IO port 21 pin 0
199 BSP_IO_PORT_21_PIN_01 = 0x1501, ///< IO port 21 pin 1
200
201 BSP_IO_PORT_22_PIN_00 = 0x1600, ///< IO port 22 pin 0
202 BSP_IO_PORT_22_PIN_01 = 0x1601, ///< IO port 22 pin 1
203
204 BSP_IO_PORT_23_PIN_00 = 0x1700, ///< IO port 23 pin 0
205 BSP_IO_PORT_23_PIN_01 = 0x1701, ///< IO port 23 pin 1
206
207 BSP_IO_PORT_24_PIN_00 = 0x1800, ///< IO port 24 pin 0
208 BSP_IO_PORT_24_PIN_01 = 0x1801, ///< IO port 24 pin 1
209
210 BSP_IO_PORT_25_PIN_00 = 0x1900, ///< IO port 25 pin 0
211 BSP_IO_PORT_25_PIN_01 = 0x1901, ///< IO port 25 pin 1
212
213 BSP_IO_PORT_26_PIN_00 = 0x1A00, ///< IO port 26 pin 0
214 BSP_IO_PORT_26_PIN_01 = 0x1A01, ///< IO port 26 pin 1
215
216 BSP_IO_PORT_27_PIN_00 = 0x1B00, ///< IO port 27 pin 0
217 BSP_IO_PORT_27_PIN_01 = 0x1B01, ///< IO port 27 pin 1
218
219 BSP_IO_PORT_28_PIN_00 = 0x1C00, ///< IO port 28 pin 0
220 BSP_IO_PORT_28_PIN_01 = 0x1C01, ///< IO port 28 pin 1
221
222 BSP_IO_PORT_29_PIN_00 = 0x1D00, ///< IO port 29 pin 0
223 BSP_IO_PORT_29_PIN_01 = 0x1D01, ///< IO port 29 pin 1
224
225 BSP_IO_PORT_30_PIN_00 = 0x1E00, ///< IO port 30 pin 0
226 BSP_IO_PORT_30_PIN_01 = 0x1E01, ///< IO port 30 pin 1
227
228 BSP_IO_PORT_31_PIN_00 = 0x1F00, ///< IO port 31 pin 0
229 BSP_IO_PORT_31_PIN_01 = 0x1F01, ///< IO port 31 pin 1
230
231 BSP_IO_PORT_32_PIN_00 = 0x2000, ///< IO port 32 pin 0
232 BSP_IO_PORT_32_PIN_01 = 0x2001, ///< IO port 32 pin 1
233
234 BSP_IO_PORT_33_PIN_00 = 0x2100, ///< IO port 33 pin 0
235 BSP_IO_PORT_33_PIN_01 = 0x2101, ///< IO port 33 pin 1
236
237 BSP_IO_PORT_34_PIN_00 = 0x2200, ///< IO port 34 pin 0
238 BSP_IO_PORT_34_PIN_01 = 0x2201, ///< IO port 34 pin 1
239
240 BSP_IO_PORT_35_PIN_00 = 0x2300, ///< IO port 35 pin 0
241 BSP_IO_PORT_35_PIN_01 = 0x2301, ///< IO port 35 pin 1
242
243 BSP_IO_PORT_36_PIN_00 = 0x2400, ///< IO port 36 pin 0
244 BSP_IO_PORT_36_PIN_01 = 0x2401, ///< IO port 36 pin 1
245
246 BSP_IO_PORT_37_PIN_00 = 0x2500, ///< IO port 37 pin 0
247 BSP_IO_PORT_37_PIN_01 = 0x2501, ///< IO port 37 pin 1
248 BSP_IO_PORT_37_PIN_02 = 0x2502, ///< IO port 37 pin 2
249
250 BSP_IO_PORT_38_PIN_00 = 0x2600, ///< IO port 38 pin 0
251 BSP_IO_PORT_38_PIN_01 = 0x2601, ///< IO port 38 pin 1
252
253 BSP_IO_PORT_39_PIN_00 = 0x2700, ///< IO port 39 pin 0
254 BSP_IO_PORT_39_PIN_01 = 0x2701, ///< IO port 39 pin 1
255 BSP_IO_PORT_39_PIN_02 = 0x2702, ///< IO port 39 pin 2
256
257 BSP_IO_PORT_40_PIN_00 = 0x2800, ///< IO port 40 pin 0
258 BSP_IO_PORT_40_PIN_01 = 0x2801, ///< IO port 40 pin 1
259 BSP_IO_PORT_40_PIN_02 = 0x2802, ///< IO port 40 pin 2
260
261 BSP_IO_PORT_41_PIN_00 = 0x2900, ///< IO port 41 pin 0
262 BSP_IO_PORT_41_PIN_01 = 0x2901, ///< IO port 41 pin 1
263
264 BSP_IO_PORT_42_PIN_00 = 0x2A00, ///< IO port 42 pin 0
265 BSP_IO_PORT_42_PIN_01 = 0x2A01, ///< IO port 42 pin 1
266 BSP_IO_PORT_42_PIN_02 = 0x2A02, ///< IO port 42 pin 2
267 BSP_IO_PORT_42_PIN_03 = 0x2A03, ///< IO port 42 pin 3
268 BSP_IO_PORT_42_PIN_04 = 0x2A04, ///< IO port 42 pin 4
269
270 BSP_IO_PORT_43_PIN_00 = 0x2B00, ///< IO port 43 pin 0
271 BSP_IO_PORT_43_PIN_01 = 0x2B01, ///< IO port 43 pin 1
272 BSP_IO_PORT_43_PIN_02 = 0x2B02, ///< IO port 43 pin 2
273 BSP_IO_PORT_43_PIN_03 = 0x2B03, ///< IO port 43 pin 3
274
275 BSP_IO_PORT_44_PIN_00 = 0x2C00, ///< IO port 44 pin 0
276 BSP_IO_PORT_44_PIN_01 = 0x2C01, ///< IO port 44 pin 1
277 BSP_IO_PORT_44_PIN_02 = 0x2C02, ///< IO port 44 pin 2
278 BSP_IO_PORT_44_PIN_03 = 0x2C03, ///< IO port 44 pin 3
279
280 BSP_IO_PORT_45_PIN_00 = 0x2D00, ///< IO port 45 pin 0
281 BSP_IO_PORT_45_PIN_01 = 0x2D01, ///< IO port 45 pin 1
282 BSP_IO_PORT_45_PIN_02 = 0x2D02, ///< IO port 45 pin 2
283 BSP_IO_PORT_45_PIN_03 = 0x2D03, ///< IO port 45 pin 3
284
285 BSP_IO_PORT_46_PIN_00 = 0x2E00, ///< IO port 46 pin 0
286 BSP_IO_PORT_46_PIN_01 = 0x2E01, ///< IO port 46 pin 1
287 BSP_IO_PORT_46_PIN_02 = 0x2E02, ///< IO port 46 pin 2
288 BSP_IO_PORT_46_PIN_03 = 0x2E03, ///< IO port 46 pin 3
289
290 BSP_IO_PORT_47_PIN_00 = 0x2F00, ///< IO port 47 pin 0
291 BSP_IO_PORT_47_PIN_01 = 0x2F01, ///< IO port 47 pin 1
292 BSP_IO_PORT_47_PIN_02 = 0x2F02, ///< IO port 47 pin 2
293 BSP_IO_PORT_47_PIN_03 = 0x2F03, ///< IO port 47 pin 3
294
295 BSP_IO_PORT_48_PIN_00 = 0x3000, ///< IO port 48 pin 0
296 BSP_IO_PORT_48_PIN_01 = 0x3001, ///< IO port 48 pin 1
297 BSP_IO_PORT_48_PIN_02 = 0x3002, ///< IO port 48 pin 2
298 BSP_IO_PORT_48_PIN_03 = 0x3003, ///< IO port 48 pin 3
299 BSP_IO_PORT_48_PIN_04 = 0x3004, ///< IO port 48 pin 4
300
301 /* Special purpose port */
302 BSP_IO_NMI = 0xFFFF0100, ///< NMI
303
304 BSP_IO_TMS_SWDIO = 0xFFFF0200, ///< TMS_SWDIO
305
306 BSP_IO_TDO = 0xFFFF0300, ///< TDO
307
308 BSP_IO_AUDIO_CLK1 = 0xFFFF0400, ///< AUDIO_CLK1
309 BSP_IO_AUDIO_CLK2 = 0xFFFF0401, ///< AUDIO_CLK2
310
311 BSP_IO_SD0_CLK = 0xFFFF0600, ///< CD0_CLK
312 BSP_IO_SD0_CMD = 0xFFFF0601, ///< CD0_CMD
313 BSP_IO_SD0_RST_N = 0xFFFF0602, ///< CD0_RST_N
314
315 BSP_IO_SD0_DATA0 = 0xFFFF0700, ///< SD0_DATA0
316 BSP_IO_SD0_DATA1 = 0xFFFF0701, ///< SD0_DATA1
317 BSP_IO_SD0_DATA2 = 0xFFFF0702, ///< SD0_DATA2
318 BSP_IO_SD0_DATA3 = 0xFFFF0703, ///< SD0_DATA3
319 BSP_IO_SD0_DATA4 = 0xFFFF0704, ///< SD0_DATA4
320 BSP_IO_SD0_DATA5 = 0xFFFF0705, ///< SD0_DATA5
321 BSP_IO_SD0_DATA6 = 0xFFFF0706, ///< SD0_DATA6
322 BSP_IO_SD0_DATA7 = 0xFFFF0707, ///< SD0_DATA7
323
324 BSP_IO_SD1_CLK = 0xFFFF0800, ///< SD1_CLK
325 BSP_IO_SD1_CMD = 0xFFFF0801, ///< SD1_CMD
326
327 BSP_IO_SD1_DATA0 = 0xFFFF0900, ///< SD1_DATA0
328 BSP_IO_SD1_DATA1 = 0xFFFF0901, ///< SD1_DATA1
329 BSP_IO_SD1_DATA2 = 0xFFFF0902, ///< SD1_DATA2
330 BSP_IO_SD1_DATA3 = 0xFFFF0903, ///< SD1_DATA3
331
332 BSP_IO_QSPI0_SPCLK = 0xFFFF0A00, ///< QSPI0_SPCLK
333 BSP_IO_QSPI0_IO0 = 0xFFFF0A01, ///< QSPI0_IO0
334 BSP_IO_QSPI0_IO1 = 0xFFFF0A02, ///< QSPI0_IO1
335 BSP_IO_QSPI0_IO2 = 0xFFFF0A03, ///< QSPI0_IO2
336 BSP_IO_QSPI0_IO3 = 0xFFFF0A04, ///< QSPI0_IO3
337 BSP_IO_QSPI0_SSL = 0xFFFF0A05, ///< QSPI0_SSL
338
339 BSP_IO_QSPI1_SPCLK = 0xFFFF0B00, ///< QSPI1_SPCLK
340 BSP_IO_QSPI1_IO0 = 0xFFFF0B01, ///< QSPI1_IO0
341 BSP_IO_QSPI1_IO1 = 0xFFFF0B02, ///< QSPI1_IO1
342 BSP_IO_QSPI1_IO2 = 0xFFFF0B03, ///< QSPI1_IO2
343 BSP_IO_QSPI1_IO3 = 0xFFFF0B04, ///< QSPI1_IO3
344 BSP_IO_QSPI1_SSL = 0xFFFF0B05, ///< QSPI1_SSL
345
346 BSP_IO_QSPI_RESET_N = 0xFFFF0C00, ///< QSPI_RESET_N
347 BSP_IO_QSPI_WP_N = 0xFFFF0C01, ///< QSPI_WP_N
348 BSP_IO_QSPI_INT_N = 0xFFFF0C02, ///< QSPI_INT_N
349
350 BSP_IO_WDTOVF_PERROUT_N = 0xFFFF0D00, ///< WDTOVF_PERROUT_N
351
352 BSP_IO_RIIC0_SDA = 0xFFFF0E00, ///< RIIC0_SDA
353 BSP_IO_RIIC0_SCL = 0xFFFF0E01, ///< RIIC0_SCL
354 BSP_IO_RIIC1_SDA = 0xFFFF0E02, ///< RIIC1_SDA
355 BSP_IO_RIIC1_SCL = 0xFFFF0E03, ///< RIIC1_SCL
356 } bsp_io_port_pin_t;
357
358 #endif
359
360 /** Superset of SD channels. */
361 typedef enum e_bsp_sd_ch
362 {
363 BSP_SD_CHANNEL_0 = 0x00, ///< Used to select SD channel 0
364 BSP_SD_CHANNEL_1 = 0x01, ///< Used to select SD channel 1
365 } bsp_sd_channel_t;
366
367 /** Superset of Ethernet channels. */
368 typedef enum e_bsp_eth_ch
369 {
370 BSP_ETHERNET_CHANNEL_0 = 0x00, ///< Used to select Ethernet channel 0
371 BSP_ETHERNET_CHANNEL_1 = 0x01, ///< Used to select Ethernet channel 1
372 } bsp_ethernet_channel_t;
373
374 /** Superset of SD voltages. */
375 typedef enum e_bsp_sd_voltage
376 {
377 BSP_SD_VOLTAGE_33 = 0x00, ///< SD voltage set to 3.3V
378 BSP_SD_VOLTAGE_18 = 0x01, ///< SD voltage set to 1.8V
379 } bsp_sd_voltage_t;
380
381 /** Superset of QSPI voltages. */
382 typedef enum e_bsp_qspi_voltage
383 {
384 BSP_QSPI_VOLTAGE_33 = 0x00, ///< QSPI voltage set to 3.3V
385 BSP_QSPI_VOLTAGE_18 = 0x01, ///< QSPI voltage set to 1.8V
386 } bsp_qspi_voltage_t;
387
388 /** Superset of XSPI voltages. */
389 typedef enum e_bsp_xspi_voltage
390 {
391 BSP_XSPI_VOLTAGE_33 = 0x00, ///< XSPI voltage set to 3.3V
392 BSP_XSPI_VOLTAGE_18 = 0x01, ///< XSPI voltage set to 1.8V
393 BSP_XSPI_VOLTAGE_25 = 0x02, ///< XSPI voltage set to 2.5V
394 } bsp_xspi_voltage_t;
395
396 /** Superset of Ethernet voltages. */
397 typedef enum e_bsp_eth_voltage
398 {
399 BSP_ETHERNET_VOLTAGE_33 = 0x00, ///< Ethernet voltage set to 3.3V
400 BSP_ETHERNET_VOLTAGE_18 = 0x01, ///< Ethernet voltage set to 1.8V
401 BSP_ETHERNET_VOLTAGE_25 = 0x02, ///< Ethernet voltage set to 2.5V
402 } bsp_ethernet_voltage_t;
403
404 /** Superset of I3C voltages. */
405 typedef enum e_bsp_i3c_voltage
406 {
407 BSP_I3C_VOLTAGE_18 = 0x00, ///< I3C voltage set to 1.8V
408 BSP_I3C_VOLTAGE_12 = 0x01, ///< I3C voltage set to 1.2V
409 } bsp_i3c_voltage_t;
410
411 /** Superset of Ethernet PHY modes. */
412 typedef enum e_bsp_eth_mode
413 {
414 BSP_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to RMII
415 BSP_ETHERNET_MODE_MII = 0x01, ///< Ethernet PHY mode set to MII
416 } bsp_ethernet_mode_t;
417
418 /** Superset of Standby modes for I3C. */
419 typedef enum e_bsp_i3c_mode
420 {
421 BSP_I3C_MODE_STB = 0x00, ///< Standby mode set to Standby mode
422 BSP_I3C_MODE_NOR = 0x01, ///< Standby mode set to Normal mode
423 } bsp_i3c_mode_t;
424
425 /** Superset of oscillator for bypass mode. */
426 typedef enum e_bsp_bypass_oscillator
427 {
428 BSP_BYPASS_OSCILLATOR_RTC = 0x00, ///< Oscillator set to RTC
429 BSP_BYPASS_OSCILLATOR_AUDIO = 0x01, ///< Oscillator set to Audio
430 BSP_BYPASS_OSCILLATOR_EMCLK = 0x02, ///< Oscillator set to EMCLK
431 } bsp_bypass_oscillator_t;
432
433 /** Superset of bypass modes. */
434 typedef enum e_bsp_bypass_mode
435 {
436 BSP_BYPASS_MODE_CRYSTAL_OSC = 0x00, ///< Bypass mode set to Crystal oscillator
437 BSP_BYPASS_MODE_EXTERNAL_CLK = 0x01, ///< Bypass mode set to External clock receive
438 BSP_BYPASS_MODE_POWER_DOWN = 0x02, ///< Bypass mode set to Power-down
439 } bsp_bypass_mode_t;
440
441 /** Superset of frequency range for bypass mode. */
442 typedef enum e_bsp_bypass_freq_range
443 {
444 BSP_BYPASS_FREQ_RANGE_1MHZ = 0x00, ///< Frequency range set to 32KHz to 1MHz
445 BSP_BYPASS_FREQ_RANGE_12MHZ = 0x02, ///< Frequency range set to 1.1MHz to 12MHz
446 BSP_BYPASS_FREQ_RANGE_24MHZ = 0x01, ///< Frequency range set to 12.1MHz to 24MHz
447 BSP_BYPASS_FREQ_RANGE_48MHZ = 0x03, ///< Frequency range set to 24.1MHz to 48MHz
448 } bsp_bypass_freq_range_t;
449
450 /***********************************************************************************************************************
451 * Exported global variables
452 **********************************************************************************************************************/
453 extern volatile uint32_t g_protect_pfswe_counter;
454
455 /***********************************************************************************************************************
456 * Exported global functions (to be accessed by other files)
457 **********************************************************************************************************************/
458
459 /*******************************************************************************************************************//**
460 * Read the current input level of the pin.
461 *
462 * @param[in] pin The pin
463 *
464 * @retval Current input level
465 **********************************************************************************************************************/
R_BSP_PinRead(bsp_io_port_pin_t pin)466 __STATIC_INLINE uint32_t R_BSP_PinRead (bsp_io_port_pin_t pin)
467 {
468 /* Read pin level. */
469 volatile const uint8_t * p_pin;
470
471 p_pin = BSP_IO_PRV_PIN_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM);
472 p_pin = &p_pin[pin >> BSP_IO_PRV_PORT_OFFSET];
473
474 return (uint32_t) ((*p_pin) >> (pin & BSP_IO_PRV_8BIT_MASK)) & BSP_IO_PRV_PIN_MASK;
475 }
476
477 /*******************************************************************************************************************//**
478 * Set a pin to output and set the output level to the level provided
479 *
480 * @param[in] pin The pin
481 * @param[in] level The level
482 **********************************************************************************************************************/
R_BSP_PinWrite(bsp_io_port_pin_t pin,bsp_io_level_t level)483 __STATIC_INLINE void R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level)
484 {
485 /* Set output level and pin direction to output. */
486 volatile uint16_t * p_pm;
487 volatile uint8_t * p_p;
488 uint16_t reg_value_pm;
489 uint8_t reg_value_p;
490 uint16_t mask_pm;
491 uint8_t mask_p;
492 uint16_t write_value_pm;
493 uint8_t write_value_p;
494
495 p_pm = BSP_IO_PRV_PM_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM);
496 p_p = BSP_IO_PRV_P_REG_BASE_SET(BSP_FEATURE_IOPORT_GP_REG_BASE_NUM);
497
498 reg_value_pm = p_pm[pin >> BSP_IO_PRV_PORT_OFFSET];
499 reg_value_p = p_p[pin >> BSP_IO_PRV_PORT_OFFSET];
500
501 mask_pm = (uint16_t) (~(BSP_IO_PM_PM_OUTPUT << ((pin & BSP_IO_PRV_8BIT_MASK) * 2)));
502 mask_p = (uint8_t) (~(1 << (pin & BSP_IO_PRV_8BIT_MASK)));
503
504 write_value_pm = (uint16_t) (BSP_IO_PM_PM_OUTPUT << ((pin & BSP_IO_PRV_8BIT_MASK) * 2));
505 write_value_p = (uint8_t) (level << (pin & BSP_IO_PRV_8BIT_MASK));
506
507 p_pm[pin >> BSP_IO_PRV_PORT_OFFSET] = ((reg_value_pm & mask_pm) | write_value_pm);
508 p_p[pin >> BSP_IO_PRV_PORT_OFFSET] = ((reg_value_p & mask_p) | write_value_p);
509 }
510
511 /*******************************************************************************************************************//**
512 * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur
513 * via multiple threads or an ISR re-entering this code.
514 **********************************************************************************************************************/
R_BSP_PinAccessEnable(void)515 __STATIC_INLINE void R_BSP_PinAccessEnable (void)
516 {
517 #if BSP_CFG_PFS_PROTECT
518
519 /** Get the current state of interrupts */
520 FSP_CRITICAL_SECTION_DEFINE;
521 FSP_CRITICAL_SECTION_ENTER;
522
523 /** If this is first entry then allow writing of PFS. */
524 if (0 == g_protect_pfswe_counter)
525 {
526 #if BSP_FEATURE_BSP_SUPPORT_PFCWE_PROTECT
527 R_GPIO->PWPR = 0; ///< Clear BOWI bit - writing to PFSWE bit enabled
528 R_GPIO->PWPR = 1U << BSP_IO_PWPR_PFSWE_OFFSET; ///< Set PFSWE bit - writing to PFS register enabled
529 #else
530 R_GPIO->PWPR = (uint32_t) ((BSP_IO_PRV_PFCWE_MASK & R_GPIO->PWPR) | (1U << BSP_IO_PWPR_PFSWE_OFFSET));
531 #endif
532 }
533
534 /** Increment the protect counter */
535 g_protect_pfswe_counter++;
536
537 /** Restore the interrupt state */
538 FSP_CRITICAL_SECTION_EXIT;
539 #endif
540 }
541
542 /*******************************************************************************************************************//**
543 * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via
544 * multiple threads or an ISR re-entering this code.
545 **********************************************************************************************************************/
R_BSP_PinAccessDisable(void)546 __STATIC_INLINE void R_BSP_PinAccessDisable (void)
547 {
548 #if BSP_CFG_PFS_PROTECT
549
550 /** Get the current state of interrupts */
551 FSP_CRITICAL_SECTION_DEFINE;
552 FSP_CRITICAL_SECTION_ENTER;
553
554 /** Is it safe to disable PFS register? */
555 if (0 != g_protect_pfswe_counter)
556 {
557 /* Decrement the protect counter */
558 g_protect_pfswe_counter--;
559 }
560
561 /** Is it safe to disable writing of PFS? */
562 if (0 == g_protect_pfswe_counter)
563 {
564 #if BSP_FEATURE_BSP_SUPPORT_PFCWE_PROTECT
565 R_GPIO->PWPR = 0; ///< Clear PFSWE bit - writing to PFS register disabled
566 R_GPIO->PWPR = 1U << BSP_IO_PWPR_B0WI_OFFSET; ///< Set BOWI bit - writing to PFSWE bit disabled
567 #else
568 R_GPIO->PWPR = (uint32_t) (BSP_IO_PRV_PFCWE_MASK & R_GPIO->PWPR);
569 #endif
570 }
571
572 /** Restore the interrupt state */
573 FSP_CRITICAL_SECTION_EXIT;
574 #endif
575 }
576
577 /*******************************************************************************************************************//**
578 * Enable access to the OEN registers.
579 **********************************************************************************************************************/
R_BSP_OENAccessEnable(void)580 __STATIC_INLINE void R_BSP_OENAccessEnable (void)
581 {
582 #if BSP_FEATURE_BSP_SUPPORT_OEN_PROTECT
583 #if BSP_CFG_PFS_PROTECT
584
585 /** Get the current state of interrupts */
586 FSP_CRITICAL_SECTION_DEFINE;
587 FSP_CRITICAL_SECTION_ENTER;
588
589 R_GPIO->PWPR = (uint32_t) ((BSP_IO_PRV_OENWE_MASK & R_GPIO->PWPR) | (1U << BSP_IO_PWPR_OENWE_OFFSET));
590
591 /** Restore the interrupt state */
592 FSP_CRITICAL_SECTION_EXIT;
593 #endif
594 #endif
595 }
596
597 /*******************************************************************************************************************//**
598 * Disable access to the OEN registers.
599 **********************************************************************************************************************/
R_BSP_OENAccessDisable(void)600 __STATIC_INLINE void R_BSP_OENAccessDisable (void)
601 {
602 #if BSP_FEATURE_BSP_SUPPORT_OEN_PROTECT
603 #if BSP_CFG_PFS_PROTECT
604
605 /** Get the current state of interrupts */
606 FSP_CRITICAL_SECTION_DEFINE;
607 FSP_CRITICAL_SECTION_ENTER;
608
609 R_GPIO->PWPR = (uint32_t) (BSP_IO_PRV_OENWE_MASK & R_GPIO->PWPR);
610
611 /** Restore the interrupt state */
612 FSP_CRITICAL_SECTION_EXIT;
613 #endif
614 #endif
615 }
616
617 /*******************************************************************************************************************//**
618 * Configures Ethernet channel PHY mode.
619 **********************************************************************************************************************/
R_BSP_EthernetModeCfg(bsp_ethernet_channel_t channel,bsp_ethernet_mode_t mode)620 __STATIC_INLINE void R_BSP_EthernetModeCfg (bsp_ethernet_channel_t channel, bsp_ethernet_mode_t mode)
621 {
622 #if BSP_FEATURE_BSP_SUPPORT_ETHER_MODE
623 #if BSP_FEATURE_BSP_HAS_PFC_OEN_REG
624 if (mode == BSP_ETHERNET_MODE_RMII)
625 {
626 if (channel == BSP_ETHERNET_CHANNEL_0)
627 {
628 R_CPG->CPG_SSEL0 |= BSP_IO_PRV_SET_SSEL0_SELCTL2;
629 }
630 else
631 {
632 R_CPG->CPG_SSEL1 |= BSP_IO_PRV_SET_SSEL1_SELCTL0;
633 }
634 }
635
636 R_BSP_OENAccessEnable();
637
638 if (BSP_ETHERNET_CHANNEL_0 == channel)
639 {
640 R_GPIO->PFC_OEN_b.OEN0 = mode;
641 }
642 else if (BSP_ETHERNET_CHANNEL_1 == channel)
643 {
644 R_GPIO->PFC_OEN_b.OEN1 = mode;
645 }
646
647 R_BSP_OENAccessDisable();
648 #elif BSP_FEATURE_BSP_HAS_ETHER_MODE_REG
649 uint32_t reg_value = R_GPIO->ETH_MODE;
650
651 reg_value = (uint32_t) ((reg_value & (uint32_t) (~(1 << channel))) | (mode << channel));
652
653 R_GPIO->ETH_MODE = reg_value;
654 #else
655 uint8_t reg_value = R_GPIO->ETH_MII_RGMII;
656
657 reg_value = (uint8_t) ((reg_value & (uint8_t) (~(1 << channel))) | (mode << channel));
658
659 R_GPIO->ETH_MII_RGMII = reg_value;
660 #endif
661 #else
662 FSP_PARAMETER_NOT_USED(channel);
663 FSP_PARAMETER_NOT_USED(mode);
664 #endif
665 }
666
667 /*******************************************************************************************************************//**
668 * Configures SD channel voltage mode.
669 **********************************************************************************************************************/
R_BSP_SDVoltageModeCfg(bsp_sd_channel_t channel,bsp_sd_voltage_t voltage)670 __STATIC_INLINE void R_BSP_SDVoltageModeCfg (bsp_sd_channel_t channel, bsp_sd_voltage_t voltage)
671 {
672 #if BSP_FEATURE_BSP_SUPPORT_SD_VOLT
673 if (BSP_SD_CHANNEL_0 == channel)
674 {
675 #if BSP_FEATURE_BSP_HAS_SD_CH_POC_REG
676 R_GPIO->SD_CH0_POC = voltage;
677 #else
678 R_GPIO->SD_ch0 = voltage;
679 #endif
680 }
681 else if (BSP_SD_CHANNEL_1 == channel)
682 {
683 #if BSP_FEATURE_BSP_HAS_SD_CH_POC_REG
684 R_GPIO->SD_CH1_POC = voltage;
685 #else
686 R_GPIO->SD_ch1 = voltage;
687 #endif
688 }
689 else
690 {
691 /* Do nothing. */
692 FSP_PARAMETER_NOT_USED(voltage);
693 }
694
695 #else
696 FSP_PARAMETER_NOT_USED(channel);
697 FSP_PARAMETER_NOT_USED(voltage);
698 #endif
699 }
700
701 /*******************************************************************************************************************//**
702 * Configures QSPI channel voltage mode.
703 **********************************************************************************************************************/
R_BSP_QSPIVoltageModeCfg(bsp_qspi_voltage_t voltage)704 __STATIC_INLINE void R_BSP_QSPIVoltageModeCfg (bsp_qspi_voltage_t voltage)
705 {
706 #if BSP_FEATURE_BSP_SUPPORT_QSPI_VOLT
707 R_GPIO->QSPI = voltage;
708 #else
709 FSP_PARAMETER_NOT_USED(voltage);
710 #endif
711 }
712
713 /*******************************************************************************************************************//**
714 * Configures XSPI channel voltage mode.
715 **********************************************************************************************************************/
R_BSP_XSPIVoltageModeCfg(bsp_xspi_voltage_t voltage)716 __STATIC_INLINE void R_BSP_XSPIVoltageModeCfg (bsp_xspi_voltage_t voltage)
717 {
718 #if BSP_FEATURE_BSP_SUPPORT_XSPI_VOLT
719 R_GPIO->XSPI_POC = voltage;
720 #else
721 FSP_PARAMETER_NOT_USED(voltage);
722 #endif
723 }
724
725 /*******************************************************************************************************************//**
726 * Configures Ethernet channel voltage mode.
727 **********************************************************************************************************************/
R_BSP_EthernetVoltageModeCfg(bsp_ethernet_channel_t channel,bsp_ethernet_voltage_t voltage)728 __STATIC_INLINE void R_BSP_EthernetVoltageModeCfg (bsp_ethernet_channel_t channel, bsp_ethernet_voltage_t voltage)
729 {
730 #if BSP_FEATURE_BSP_SUPPORT_ETHER_VOLT
731 if (BSP_ETHERNET_CHANNEL_0 == channel)
732 {
733 #if BSP_FEATURE_BSP_HAS_ETH_POC_REG
734 R_GPIO->ETH0_POC = voltage;
735 #else
736 R_GPIO->ETH_ch0 = voltage;
737 #endif
738 }
739 else if (BSP_ETHERNET_CHANNEL_1 == channel)
740 {
741 #if BSP_FEATURE_BSP_HAS_ETH_POC_REG
742 R_GPIO->ETH1_POC = voltage;
743 #else
744 R_GPIO->ETH_ch1 = voltage;
745 #endif
746 }
747 else
748 {
749 /* Do nothing. */
750 FSP_PARAMETER_NOT_USED(voltage);
751 }
752
753 #else
754 FSP_PARAMETER_NOT_USED(channel);
755 FSP_PARAMETER_NOT_USED(voltage);
756 #endif
757 }
758
759 /*******************************************************************************************************************//**
760 * Configures I3C control.
761 **********************************************************************************************************************/
R_BSP_I3CControlCfg(bsp_i3c_voltage_t voltage,bsp_i3c_mode_t mode)762 __STATIC_INLINE void R_BSP_I3CControlCfg (bsp_i3c_voltage_t voltage, bsp_i3c_mode_t mode)
763 {
764 #if BSP_FEATURE_BSP_SUPPORT_I3C
765 R_GPIO->I3C_SET_b.POC = voltage;
766 R_GPIO->I3C_SET_b.STBN = mode;
767 #else
768 FSP_PARAMETER_NOT_USED(voltage);
769 FSP_PARAMETER_NOT_USED(mode);
770 #endif
771 }
772
773 /*******************************************************************************************************************//**
774 * Configures bypass mode for RTC, Audio and EMCLK oscillator.
775 **********************************************************************************************************************/
R_BSP_BypassModeCfg(bsp_bypass_oscillator_t oscillator,bsp_bypass_mode_t mode,bsp_bypass_freq_range_t freq_range)776 __STATIC_INLINE void R_BSP_BypassModeCfg (bsp_bypass_oscillator_t oscillator,
777 bsp_bypass_mode_t mode,
778 bsp_bypass_freq_range_t freq_range)
779 {
780 #if BSP_FEATURE_BSP_SUPPORT_BYPASS
781 switch (oscillator)
782 {
783 case BSP_BYPASS_OSCILLATOR_AUDIO:
784 {
785 R_GPIO->PFC_OSCBYPS_b.OSCBYPS1 = mode & 1U;
786 R_GPIO->PFC_OSCBYPS_b.OSCPW1 = ((mode >> 1U) & 1U);
787 R_GPIO->PFC_OSCBYPS_b.OSCSF1 = freq_range;
788 break;
789 }
790
791 case BSP_BYPASS_OSCILLATOR_EMCLK:
792 {
793 R_GPIO->PFC_OSCBYPS_b.OSCBYPS2 = mode & 1U;
794 R_GPIO->PFC_OSCBYPS_b.OSCPW2 = ((mode >> 1U) & 1U);
795 R_GPIO->PFC_OSCBYPS_b.OSCSF2 = freq_range;
796 break;
797 }
798
799 case BSP_BYPASS_OSCILLATOR_RTC:
800 {
801 R_GPIO->PFC_OSCBYPS_b.OSCBYPS0 = mode & 1U;
802 R_GPIO->PFC_OSCBYPS_b.OSCPW0 = ((mode >> 1U) & 1U);
803 FSP_PARAMETER_NOT_USED(freq_range);
804 break;
805 }
806
807 default:
808
809 /* Do nothing. */
810 FSP_PARAMETER_NOT_USED(mode);
811 FSP_PARAMETER_NOT_USED(freq_range);
812 }
813
814 #else
815 FSP_PARAMETER_NOT_USED(oscillator);
816 FSP_PARAMETER_NOT_USED(mode);
817 FSP_PARAMETER_NOT_USED(freq_range);
818 #endif
819 }
820
821 /*******************************************************************************************************************//**
822 * Configures XSPI output Enable.
823 **********************************************************************************************************************/
R_BSP_XSPIOutputEnableCfg(void)824 __STATIC_INLINE void R_BSP_XSPIOutputEnableCfg (void)
825 {
826 #if BSP_FEATURE_BSP_SUPPORT_XSPI_OUTPUT
827 R_BSP_OENAccessEnable();
828 R_GPIO->PFC_OEN_b.OEN2 = BSP_IO_PRV_SET_OEN_ENABLE;
829 R_GPIO->PFC_OEN_b.OEN3 = BSP_IO_PRV_SET_OEN_ENABLE;
830 R_GPIO->PFC_OEN_b.OEN4 = BSP_IO_PRV_SET_OEN_ENABLE;
831 R_GPIO->PFC_OEN_b.OEN5 = BSP_IO_PRV_SET_OEN_ENABLE;
832 R_BSP_OENAccessDisable();
833 #endif
834 }
835
836 /** @} (end addtogroup BSP_IO) */
837
838 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
839 FSP_FOOTER
840
841 #endif
842
