1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @addtogroup QSPI 9 * @{ 10 **********************************************************************************************************************/ 11 12 #ifndef R_QSPI_H 13 #define R_QSPI_H 14 15 /*********************************************************************************************************************** 16 * Includes 17 **********************************************************************************************************************/ 18 #include "bsp_api.h" 19 #include <string.h> 20 #include "r_qspi_cfg.h" 21 #include "r_spi_flash_api.h" 22 23 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 24 FSP_HEADER 25 26 /*********************************************************************************************************************** 27 * Macro definitions 28 **********************************************************************************************************************/ 29 30 #define QSPI_DEVICE_START_ADDRESS (0x60000000) 31 32 /*********************************************************************************************************************** 33 * Typedef definitions 34 **********************************************************************************************************************/ 35 36 /* Minimum QSPCLK cycles for QSSL to remain high between operations. */ 37 typedef enum e_qspi_qssl_min_high_level 38 { 39 QSPI_QSSL_MIN_HIGH_LEVEL_1_QSPCLK, ///< QSSL deselected for at least 1 QSPCLK 40 QSPI_QSSL_MIN_HIGH_LEVEL_2_QSPCLK, ///< QSSL deselected for at least 2 QSPCLK 41 QSPI_QSSL_MIN_HIGH_LEVEL_3_QSPCLK, ///< QSSL deselected for at least 3 QSPCLK 42 QSPI_QSSL_MIN_HIGH_LEVEL_4_QSPCLK, ///< QSSL deselected for at least 4 QSPCLK 43 QSPI_QSSL_MIN_HIGH_LEVEL_5_QSPCLK, ///< QSSL deselected for at least 5 QSPCLK 44 QSPI_QSSL_MIN_HIGH_LEVEL_6_QSPCLK, ///< QSSL deselected for at least 6 QSPCLK 45 QSPI_QSSL_MIN_HIGH_LEVEL_7_QSPCLK, ///< QSSL deselected for at least 7 QSPCLK 46 QSPI_QSSL_MIN_HIGH_LEVEL_8_QSPCLK, ///< QSSL deselected for at least 8 QSPCLK 47 QSPI_QSSL_MIN_HIGH_LEVEL_9_QSPCLK, ///< QSSL deselected for at least 9 QSPCLK 48 QSPI_QSSL_MIN_HIGH_LEVEL_10_QSPCLK, ///< QSSL deselected for at least 10 QSPCLK 49 QSPI_QSSL_MIN_HIGH_LEVEL_11_QSPCLK, ///< QSSL deselected for at least 11 QSPCLK 50 QSPI_QSSL_MIN_HIGH_LEVEL_12_QSPCLK, ///< QSSL deselected for at least 12 QSPCLK 51 QSPI_QSSL_MIN_HIGH_LEVEL_13_QSPCLK, ///< QSSL deselected for at least 13 QSPCLK 52 QSPI_QSSL_MIN_HIGH_LEVEL_14_QSPCLK, ///< QSSL deselected for at least 14 QSPCLK 53 QSPI_QSSL_MIN_HIGH_LEVEL_15_QSPCLK, ///< QSSL deselected for at least 15 QSPCLK 54 QSPI_QSSL_MIN_HIGH_LEVEL_16_QSPCLK, ///< QSSL deselected for at least 16 QSPCLK 55 } qspi_qssl_min_high_level_t; 56 57 /* QSPCLK divider. */ 58 typedef enum e_qspi_qspclk_div 59 { 60 QSPI_QSPCLK_DIV_2 = 0x0, ///< QSPCLK = PCLK / 2 61 QSPI_QSPCLK_DIV_3 = 0x1, ///< QSPCLK = PCLK / 3 62 QSPI_QSPCLK_DIV_4 = 0x2, ///< QSPCLK = PCLK / 4 63 QSPI_QSPCLK_DIV_5 = 0x3, ///< QSPCLK = PCLK / 5 64 QSPI_QSPCLK_DIV_6 = 0x4, ///< QSPCLK = PCLK / 6 65 QSPI_QSPCLK_DIV_7 = 0x5, ///< QSPCLK = PCLK / 7 66 QSPI_QSPCLK_DIV_8 = 0x6, ///< QSPCLK = PCLK / 8 67 QSPI_QSPCLK_DIV_9 = 0x7, ///< QSPCLK = PCLK / 9 68 QSPI_QSPCLK_DIV_10 = 0x8, ///< QSPCLK = PCLK / 10 69 QSPI_QSPCLK_DIV_11 = 0x9, ///< QSPCLK = PCLK / 11 70 QSPI_QSPCLK_DIV_12 = 0xA, ///< QSPCLK = PCLK / 12 71 QSPI_QSPCLK_DIV_13 = 0xB, ///< QSPCLK = PCLK / 13 72 QSPI_QSPCLK_DIV_14 = 0xC, ///< QSPCLK = PCLK / 14 73 QSPI_QSPCLK_DIV_15 = 0xD, ///< QSPCLK = PCLK / 15 74 QSPI_QSPCLK_DIV_16 = 0xE, ///< QSPCLK = PCLK / 16 75 QSPI_QSPCLK_DIV_17 = 0xF, ///< QSPCLK = PCLK / 17 76 QSPI_QSPCLK_DIV_18 = 0x10, ///< QSPCLK = PCLK / 18 77 QSPI_QSPCLK_DIV_20 = 0x11, ///< QSPCLK = PCLK / 20 78 QSPI_QSPCLK_DIV_22 = 0x12, ///< QSPCLK = PCLK / 22 79 QSPI_QSPCLK_DIV_24 = 0x13, ///< QSPCLK = PCLK / 24 80 QSPI_QSPCLK_DIV_26 = 0x14, ///< QSPCLK = PCLK / 26 81 QSPI_QSPCLK_DIV_28 = 0x15, ///< QSPCLK = PCLK / 28 82 QSPI_QSPCLK_DIV_30 = 0x16, ///< QSPCLK = PCLK / 30 83 QSPI_QSPCLK_DIV_32 = 0x17, ///< QSPCLK = PCLK / 32 84 QSPI_QSPCLK_DIV_34 = 0x18, ///< QSPCLK = PCLK / 34 85 QSPI_QSPCLK_DIV_36 = 0x19, ///< QSPCLK = PCLK / 36 86 QSPI_QSPCLK_DIV_38 = 0x1A, ///< QSPCLK = PCLK / 38 87 QSPI_QSPCLK_DIV_40 = 0x1B, ///< QSPCLK = PCLK / 40 88 QSPI_QSPCLK_DIV_42 = 0x1C, ///< QSPCLK = PCLK / 42 89 QSPI_QSPCLK_DIV_44 = 0x1D, ///< QSPCLK = PCLK / 44 90 QSPI_QSPCLK_DIV_46 = 0x1E, ///< QSPCLK = PCLK / 46 91 QSPI_QSPCLK_DIV_48 = 0x1F, ///< QSPCLK = PCLK / 48 92 } qspi_qspclk_div_t; 93 94 /* Extended configuration. */ 95 typedef struct st_qspi_extended_cfg 96 { 97 qspi_qssl_min_high_level_t min_qssl_deselect_cycles; ///< Minimum QSSL deselect time 98 qspi_qspclk_div_t qspclk_div; ///< QSPCLK divider 99 } qspi_extended_cfg_t; 100 101 /** Instance control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_flash_api_t::open is called */ 102 typedef struct st_qspi_instance_ctrl 103 { 104 spi_flash_cfg_t const * p_cfg; // Pointer to initial configuration 105 spi_flash_data_lines_t data_lines; // Data lines 106 uint32_t total_size_bytes; // Total size of the flash in bytes 107 uint32_t open; // Whether or not driver is open 108 } qspi_instance_ctrl_t; 109 110 /********************************************************************************************************************** 111 * Exported global variables 112 **********************************************************************************************************************/ 113 114 /** @cond INC_HEADER_DEFS_SEC */ 115 /** Filled in Interface API structure for this Instance. */ 116 extern const spi_flash_api_t g_qspi_on_spi_flash; 117 118 /** @endcond */ 119 120 fsp_err_t R_QSPI_Open(spi_flash_ctrl_t * p_ctrl, spi_flash_cfg_t const * const p_cfg); 121 fsp_err_t R_QSPI_Close(spi_flash_ctrl_t * p_ctrl); 122 fsp_err_t R_QSPI_DirectWrite(spi_flash_ctrl_t * p_ctrl, 123 uint8_t const * const p_src, 124 uint32_t const bytes, 125 bool const read_after_write); 126 fsp_err_t R_QSPI_DirectRead(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_dest, uint32_t const bytes); 127 fsp_err_t R_QSPI_SpiProtocolSet(spi_flash_ctrl_t * p_ctrl, spi_flash_protocol_t spi_protocol); 128 fsp_err_t R_QSPI_XipEnter(spi_flash_ctrl_t * p_ctrl); 129 fsp_err_t R_QSPI_XipExit(spi_flash_ctrl_t * p_ctrl); 130 fsp_err_t R_QSPI_Write(spi_flash_ctrl_t * p_ctrl, 131 uint8_t const * const p_src, 132 uint8_t * const p_dest, 133 uint32_t byte_count); 134 fsp_err_t R_QSPI_Erase(spi_flash_ctrl_t * p_ctrl, uint8_t * const p_device_address, uint32_t byte_count); 135 fsp_err_t R_QSPI_StatusGet(spi_flash_ctrl_t * p_ctrl, spi_flash_status_t * const p_status); 136 fsp_err_t R_QSPI_BankSet(spi_flash_ctrl_t * p_ctrl, uint32_t bank); 137 fsp_err_t R_QSPI_DirectTransfer(spi_flash_ctrl_t * p_ctrl, 138 spi_flash_direct_transfer_t * const p_transfer, 139 spi_flash_direct_transfer_dir_t direction); 140 fsp_err_t R_QSPI_AutoCalibrate(spi_flash_ctrl_t * p_ctrl); 141 142 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 143 FSP_FOOTER 144 145 #endif 146 147 /*******************************************************************************************************************//** 148 * @} (end defgroup QSPI) 149 **********************************************************************************************************************/ 150
