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Searched refs:PLLCCR (Results 1 – 20 of 20) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/bsp/mcu/all/
Dbsp_clocks.c1755 if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (BSP_PRV_PLLCCR2 != R_SYSTEM->PLLCCR2) || in bsp_soft_reset_prepare()
1760 … if ((BSP_PRV_PLLCCR != R_SYSTEM->PLLCCR) || (stop_hoco && (1 == R_SYSTEM->PLLCCR_b.PLSRCSEL))) in bsp_soft_reset_prepare()
2181 R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; in bsp_clock_init()
2185 R_SYSTEM->PLLCCR = (uint16_t) BSP_PRV_PLLCCR; in bsp_clock_init()
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA2L1AB.h10202 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA2A1AB.h10464 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA4E10D.h10061 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA4W1AD.h10550 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA4M1AB.h10714 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA4M2AD.h11050 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA4M3AF.h11050 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA4E2B9.h11865 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA6E10F.h11479 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA6M1AD.h11246 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA6E2BB.h12069 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA6M4AF.h11813 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA4L1BD.h14356 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA6M2AF.h13227 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA6M3AH.h15885 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA6M5BH.h14075 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA8T1AH.h13673 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA8M1AH.h13708 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member
DR7FA8D1BH.h15297 …__IOM uint16_t PLLCCR; /*!< (@ 0x00000028) PLL Clock Control Register … member