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/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/mcu/all/
Dbsp_io.h449 R_PORT_NSR->P[pin >> 8] |= in R_BSP_PinSet()
457 ((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->P[pin >> in R_BSP_PinSet()
476 R_PORT_NSR->P[pin >> 8] &= in R_BSP_PinClear()
484 ((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->P[pin >> in R_BSP_PinClear()
503 R_PORT_NSR->P[pin >> 8] ^= in R_BSP_PinToggle()
511 ((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->P[pin >> in R_BSP_PinToggle()
554 R_PORT_NSR->P[port >> 8] = set_value; in R_BSP_PortWrite()
559 ((R_PORT_COMMON_Type *) (BSP_FEATURE_BSP_IO_SELECTABLE_NON_SAFETY_BASE + region))->P[port >> in R_BSP_PortWrite()
/hal_renesas-latest/drivers/rz/fsp/src/rzn/r_ioport/
Dr_ioport.c386 temp_value = (ioport_size_t) (R_PORT_NSR->P[port_num] & (~mask)); in R_IOPORT_PortWrite()
389 R_PORT_NSR->P[port_num] = (uint8_t) (temp_value | (value & mask)); in R_IOPORT_PortWrite()
410 temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask)); in R_IOPORT_PortWrite()
413 p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask)); in R_IOPORT_PortWrite()
424 temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask)); in R_IOPORT_PortWrite()
427 p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask)); in R_IOPORT_PortWrite()
469 p_ioport_regs->P[port_num] &= (uint8_t) (~(1U << pin_num)); in R_IOPORT_PinWrite()
473 p_ioport_regs->P[port_num] |= (uint8_t) (1U << pin_num); in R_IOPORT_PinWrite()
486 p_ioport_regs->P[port_num] &= (uint8_t) (~(1U << pin_num)); in R_IOPORT_PinWrite()
490 p_ioport_regs->P[port_num] |= (uint8_t) (1U << pin_num); in R_IOPORT_PinWrite()
[all …]
/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/mcu/all/
Dbsp_io.h40 #define BSP_IO_PRV_P_REG_BASE(base) (&R_GPIO->P ## base)
/hal_renesas-latest/drivers/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/
Dhw_sce_ra_private.h29 #define SCE_PRV_SEC_P_SECURE_BOOT R_BSP_ATTRIB_SECTION_CHANGE(P, SECURE_BOOT)
/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_ioport/
Dr_ioport.c72 #define IOPORT_PRV_P_REG_BASE(base) (&R_GPIO->P ## base)
/hal_renesas-latest/drivers/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/
Dhw_sce_ra_private.h29 #define SCE_PRV_SEC_P_SECURE_BOOT R_BSP_ATTRIB_SECTION_CHANGE(P, SECURE_BOOT)
/hal_renesas-latest/drivers/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/
Dhw_sce_ra_private.h29 #define SCE_PRV_SEC_P_SECURE_BOOT R_BSP_ATTRIB_SECTION_CHANGE(P, SECURE_BOOT)
/hal_renesas-latest/drivers/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/
Dhw_sce_ra_private.h30 #define SCE_PRV_SEC_P_SECURE_BOOT R_BSP_ATTRIB_SECTION_CHANGE(P, SECURE_BOOT)
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA2A1AB.h1338 …__IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Reg… member
6863 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA4W1AD.h1337 …__IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Reg… member
7042 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA4M1AB.h1337 …__IOM uint8_t P; /*!< (@ 0x00000000) Operational Amplifier n Offset Trimming Pch Reg… member
7042 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA2L1AB.h6928 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA4M2AD.h6932 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA4M3AF.h6932 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA4E2B9.h7302 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA6M1AD.h6896 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA6E2BB.h7302 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA6M4AF.h7695 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA4L1BD.h8916 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA6M2AF.h7624 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA6M3AH.h10897 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA6M5BH.h8820 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA8T1AH.h8540 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
DR7FA8M1AH.h8575 …__IOM uint32_t P : 1; /*!< [17..17] Positive-Phase Output (P) Control … member
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h5996 …__IOM uint8_t P[25]; /*!< (@ 0x00000000) Port [0..24] Register … member
28008 …__IOM uint8_t P : 1; /*!< [4..4] Positive-Phase Output (P) Control … member

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