| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m1/ |
| D | bsp_mcu_family_cfg.h | 37 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
38 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/ |
| D | bsp_mcu_family_cfg.h | 36 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
37 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4w1/ |
| D | bsp_mcu_family_cfg.h | 38 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
39 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/ |
| D | bsp_mcu_family_cfg.h | 38 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
41 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/ |
| D | bsp_mcu_family_cfg.h | 37 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
39 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/ |
| D | bsp_mcu_family_cfg.h | 37 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
38 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/ |
| D | bsp_mcu_family_cfg.h | 37 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
38 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e2/ |
| D | bsp_mcu_family_cfg.h | 282 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
283 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/ |
| D | bsp_mcu_family_cfg.h | 292 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
293 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e1/ |
| D | bsp_mcu_family_cfg.h | 301 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
302 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4l1/ |
| D | bsp_mcu_family_cfg.h | 294 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
295 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m2/ |
| D | bsp_mcu_family_cfg.h | 313 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
314 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m3/ |
| D | bsp_mcu_family_cfg.h | 314 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
315 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e1/ |
| D | bsp_mcu_family_cfg.h | 300 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
301 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m4/ |
| D | bsp_mcu_family_cfg.h | 300 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
301 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/ |
| D | bsp_mcu_family_cfg.h | 300 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
301 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/ |
| D | bsp_mcu_family_cfg.h | 336 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
337 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/ |
| D | bsp_mcu_family_cfg.h | 341 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
342 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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| /hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/ |
| D | bsp_mcu_family_cfg.h | 332 #define OFS_SEQ5 (1 << 28) | (1 << 30) macro
333 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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