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Searched refs:OFS_SEQ2 (Results 1 – 19 of 19) sorted by relevance

/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m1/
Dbsp_mcu_family_cfg.h34 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
38 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m1/
Dbsp_mcu_family_cfg.h33 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
37 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4w1/
Dbsp_mcu_family_cfg.h35 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
39 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2a1/
Dbsp_mcu_family_cfg.h35 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
41 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra2l1/
Dbsp_mcu_family_cfg.h34 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
39 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m2/
Dbsp_mcu_family_cfg.h34 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
38 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m3/
Dbsp_mcu_family_cfg.h34 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
38 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e2/
Dbsp_mcu_family_cfg.h279 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
283 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/
Dbsp_mcu_family_cfg.h289 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
293 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e1/
Dbsp_mcu_family_cfg.h298 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
302 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4l1/
Dbsp_mcu_family_cfg.h291 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
295 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m2/
Dbsp_mcu_family_cfg.h310 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
314 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4m3/
Dbsp_mcu_family_cfg.h311 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
315 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6e1/
Dbsp_mcu_family_cfg.h297 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
301 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m4/
Dbsp_mcu_family_cfg.h297 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
301 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra6m5/
Dbsp_mcu_family_cfg.h297 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
301 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8t1/
Dbsp_mcu_family_cfg.h333 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
337 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8d1/
Dbsp_mcu_family_cfg.h338 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
342 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
/hal_renesas-latest/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra8m1/
Dbsp_mcu_family_cfg.h329 #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) macro
333 #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)