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Searched refs:GTDLYCR2 (Results 1 – 5 of 5) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzg/r_gpt/
Dr_gpt.c855 R_GPT_ODC->GTDLYCR2 &= (uint16_t) (~p_instance_ctrl->channel_mask & UINT16_MAX); in R_GPT_PwmOutputDelaySet()
886 if (0U == (R_GPT_ODC->GTDLYCR2 & p_instance_ctrl->channel_mask)) in R_GPT_PwmOutputDelaySet()
901 R_GPT_ODC->GTDLYCR2 |= (uint16_t) p_instance_ctrl->channel_mask; in R_GPT_PwmOutputDelaySet()
1095 R_GPT_ODC->GTDLYCR2 = 0; in R_GPT_PwmOutputDelayInitialize()
1227 R_GPT_ODC->GTDLYCR2 &= (uint16_t) (~p_instance_ctrl->channel_mask & UINT16_MAX); in gpt_hardware_initialize()
/hal_renesas-latest/drivers/ra/fsp/src/r_gpt/
Dr_gpt.c919 R_GPT_ODC->GTDLYCR2 &= (uint16_t) (~p_instance_ctrl->channel_mask & UINT16_MAX); in R_GPT_PwmOutputDelaySet()
950 if (0U == (R_GPT_ODC->GTDLYCR2 & p_instance_ctrl->channel_mask)) in R_GPT_PwmOutputDelaySet()
965 R_GPT_ODC->GTDLYCR2 |= (uint16_t) p_instance_ctrl->channel_mask; in R_GPT_PwmOutputDelaySet()
1153 R_GPT_ODC->GTDLYCR2 = 0; in R_GPT_PwmOutputDelayInitialize()
1288 R_GPT_ODC->GTDLYCR2 &= (uint16_t) (~p_instance_ctrl->channel_mask & UINT16_MAX); in gpt_hardware_initialize()
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA6M1AD.h6834 …__IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 … member
DR7FA6M2AF.h7562 …__IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 … member
DR7FA6M3AH.h10835 …__IOM uint16_t GTDLYCR2; /*!< (@ 0x00000002) PWM Output Delay Control Register2 … member