1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef R_GPT_H 8 #define R_GPT_H 9 10 /*******************************************************************************************************************//** 11 * @addtogroup GPT 12 * @{ 13 **********************************************************************************************************************/ 14 15 /*********************************************************************************************************************** 16 * Includes 17 **********************************************************************************************************************/ 18 #include "bsp_api.h" 19 #include "r_timer_api.h" 20 21 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 22 FSP_HEADER 23 24 /*********************************************************************************************************************** 25 * Macro definitions 26 **********************************************************************************************************************/ 27 28 /*********************************************************************************************************************** 29 * Typedef definitions 30 **********************************************************************************************************************/ 31 32 /** Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet(). */ 33 typedef enum e_gpt_io_pin 34 { 35 GPT_IO_PIN_GTIOCA = 0, ///< GTIOCA 36 GPT_IO_PIN_GTIOCB = 1, ///< GTIOCB 37 GPT_IO_PIN_GTIOCA_AND_GTIOCB = 2, ///< GTIOCA and GTIOCB 38 GPT_IO_PIN_TROUGH = 4, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. 39 GPT_IO_PIN_CREST = 8, ///< Used in @ref R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected. 40 GPT_IO_PIN_ONE_SHOT_LEADING_EDGE = 4, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRC and GTCCRE registers when One-Shot Pulse mode is selected. 41 GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE = 8, ///< Used in @ref R_GPT_DutyCycleSet to set GTCCRD and GTCCRF registers when One-Shot Pulse mode is selected. 42 } gpt_io_pin_t; 43 44 /** Forced buffer push operation used in One-Sot Pulse mode with R_GPT_DutyCycleSet(). */ 45 typedef enum e_gpt_buffer_force_push 46 { 47 GPT_BUFFER_FORCE_PUSH = 64, ///< Used in @ref R_GPT_DutyCycleSet to force push the data from GTCCRn registers to temporary buffer A or B when One-Shot Pulse mode is selected. 48 } gpt_buffer_force_push; 49 50 /** Level of GPT pin */ 51 typedef enum e_gpt_pin_level 52 { 53 GPT_PIN_LEVEL_LOW = 0, ///< Pin level low 54 GPT_PIN_LEVEL_HIGH = 1, ///< Pin level high 55 } gpt_pin_level_t; 56 57 /** Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent 58 * a bitmask. Multiple sources can be ORed together. */ 59 typedef enum e_gpt_source 60 { 61 /** No active event sources. */ 62 GPT_SOURCE_NONE = 0U, 63 64 /** Action performed on GTETRGA rising edge. **/ 65 GPT_SOURCE_GTETRGA_RISING = (1U << 0), 66 67 /** Action performed on GTETRGA falling edge. **/ 68 GPT_SOURCE_GTETRGA_FALLING = (1U << 1), 69 70 /** Action performed on GTETRGB rising edge. **/ 71 GPT_SOURCE_GTETRGB_RISING = (1U << 2), 72 73 /** Action performed on GTETRGB falling edge. **/ 74 GPT_SOURCE_GTETRGB_FALLING = (1U << 3), 75 76 /** Action performed on GTETRGC rising edge. **/ 77 GPT_SOURCE_GTETRGC_RISING = (1U << 4), 78 79 /** Action performed on GTETRGC falling edge. **/ 80 GPT_SOURCE_GTETRGC_FALLING = (1U << 5), 81 82 /** Action performed on GTETRGB rising edge. **/ 83 GPT_SOURCE_GTETRGD_RISING = (1U << 6), 84 85 /** Action performed on GTETRGB falling edge. **/ 86 GPT_SOURCE_GTETRGD_FALLING = (1U << 7), 87 88 /** Action performed when GTIOCA input rises while GTIOCB is low. **/ 89 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW = (1U << 8), 90 91 /** Action performed when GTIOCA input rises while GTIOCB is high. **/ 92 GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH = (1U << 9), 93 94 /** Action performed when GTIOCA input falls while GTIOCB is low. **/ 95 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW = (1U << 10), 96 97 /** Action performed when GTIOCA input falls while GTIOCB is high. **/ 98 GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH = (1U << 11), 99 100 /** Action performed when GTIOCB input rises while GTIOCA is low. **/ 101 GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW = (1U << 12), 102 103 /** Action performed when GTIOCB input rises while GTIOCA is high. **/ 104 GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH = (1U << 13), 105 106 /** Action performed when GTIOCB input falls while GTIOCA is low. **/ 107 GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW = (1U << 14), 108 109 /** Action performed when GTIOCB input falls while GTIOCA is high. **/ 110 GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH = (1U << 15), 111 } gpt_source_t; 112 113 /** Configurations for output pins. */ 114 typedef struct s_gpt_output_pin 115 { 116 bool output_enabled; ///< Set to true to enable output, false to disable output 117 gpt_pin_level_t stop_level; ///< Select a stop level from ::gpt_pin_level_t 118 } gpt_output_pin_t; 119 120 /** Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. */ 121 typedef struct s_gpt_gtior_setting 122 { 123 union 124 { 125 uint32_t gtior; 126 struct 127 { 128 /* Settings for GTIOCxA pin. */ 129 uint32_t gtioa : 5; ///< GTIOCA Pin Function Select. 130 uint32_t : 1; // Reserved 131 uint32_t oadflt : 1; ///< GTIOCA Pin Output Value Setting at the Count Stop. 132 uint32_t oahld : 1; ///< GTIOCA Pin Output Setting at the Start/Stop Count. 133 uint32_t oae : 1; ///< GTIOCA Pin Output Enable 134 uint32_t oadf : 2; ///< GTIOCA Pin Disable Value Setting. 135 uint32_t : 2; /// Reserved 136 uint32_t nfaen : 1; /// Noise Filter A Enable. 137 uint32_t nfcsa : 2; /// Noise Filter A Sampling Clock Select. 138 139 /* Settings for GTIOCxB pin. */ 140 uint32_t gtiob : 5; ///< GTIOCB Pin Function Select. 141 uint32_t : 1; // Reserved 142 uint32_t obdflt : 1; ///< GTIOCB Pin Output Value Setting at the Count Stop. 143 uint32_t obhld : 1; ///< GTIOCB Pin Output Setting at the Start/Stop Count. 144 uint32_t obe : 1; ///< GTIOCB Pin Output Enable 145 uint32_t obdf : 2; ///< GTIOCB Pin Disable Value Setting. 146 uint32_t : 2; /// Reserved 147 uint32_t nfben : 1; /// Noise Filter B Enable. 148 uint32_t nfcsb : 2; /// Noise Filter B Sampling Clock Select. 149 } gtior_b; 150 }; 151 } gpt_gtior_setting_t; 152 153 /** Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB. 154 * The noise filter samples the external signal at intervals of the P0CLK divided by one of the values. 155 * When 3 consecutive samples are at the same level (high or low), then that level is passed on as 156 * the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section. 157 */ 158 typedef enum e_gpt_capture_filter 159 { 160 GPT_CAPTURE_FILTER_NONE = 0U, ///< None - no filtering 161 GPT_CAPTURE_FILTER_CLOCK_SOURCE_DIV_1 = 1U, ///< CLK/1 - fast sampling 162 GPT_CAPTURE_FILTER_CLOCK_SOURCE_DIV_4 = 3U, ///< CLK/4 163 GPT_CAPTURE_FILTER_CLOCK_SOURCE_DIV_16 = 5U, ///< CLK/16 164 GPT_CAPTURE_FILTER_CLOCK_SOURCE_DIV_64 = 7U, ///< CLK/64 - slow sampling 165 } gpt_capture_filter_t; 166 167 /** Trigger options to start A/D conversion. */ 168 typedef enum e_gpt_adc_trigger 169 { 170 GPT_ADC_TRIGGER_NONE = 0U, ///< None - no output disable request 171 GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A = 1U << 0, ///< Request A/D conversion from ADC unit 0 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match 172 GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A = 1U << 1, ///< Request A/D conversion from ADC unit 0 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_a_compare_match 173 GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B = 1U << 2, ///< Request A/D conversion from ADC unit 1 at up counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match 174 GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B = 1U << 3, ///< Request A/D conversion from ADC unit 1 at down counting compare match of @ref gpt_extended_pwm_cfg_t::adc_b_compare_match 175 } gpt_adc_trigger_t; 176 177 /** POEG channel to link to this channel. */ 178 typedef enum e_gpt_poeg_link 179 { 180 GPT_POEG_LINK_POEG0 = 0U, ///< Link this GPT channel to POEG channel 0 (GTETRGA) 181 GPT_POEG_LINK_POEG1 = 1U, ///< Link this GPT channel to POEG channel 1 (GTETRGB) 182 GPT_POEG_LINK_POEG2 = 2U, ///< Link this GPT channel to POEG channel 2 (GTETRGC) 183 GPT_POEG_LINK_POEG3 = 3U, ///< Link this GPT channel to POEG channel 3 (GTETRGD) 184 } gpt_poeg_link_t; 185 186 /** Select trigger to send output disable request to POEG. */ 187 typedef enum e_gpt_output_disable 188 { 189 GPT_OUTPUT_DISABLE_NONE = 0U, ///< None - no output disable request 190 GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR = 1U << 0, ///< Request output disable if a dead time error occurs 191 GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH = 1U << 1, ///< Request output disable if GTIOCA and GTIOCB are high at the same time 192 GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW = 1U << 2, ///< Request output disable if GTIOCA and GTIOCB are low at the same time 193 } gpt_output_disable_t; 194 195 /** Disable level options for GTIOC pins. */ 196 typedef enum e_gpt_gtioc_disable 197 { 198 GPT_GTIOC_DISABLE_PROHIBITED = 0U, ///< Do not allow output disable 199 GPT_GTIOC_DISABLE_SET_HI_Z = 1U, ///< Set GTIOC to high impedance when output is disabled 200 GPT_GTIOC_DISABLE_LEVEL_LOW = 2U, ///< Set GTIOC level low when output is disabled 201 GPT_GTIOC_DISABLE_LEVEL_HIGH = 3U, ///< Set GTIOC level high when output is disabled 202 } gpt_gtioc_disable_t; 203 204 /** Trigger options to start A/D conversion. */ 205 typedef enum e_gpt_adc_compare_match 206 { 207 GPT_ADC_COMPARE_MATCH_ADC_A = 0U, ///< Set A/D conversion start request value for GPT A/D converter start request A 208 GPT_ADC_COMPARE_MATCH_ADC_B = 3U, ///< Set A/D conversion start request value for GPT A/D converter start request B 209 } gpt_adc_compare_match_t; 210 211 /** Interrupt skipping modes */ 212 typedef enum e_gpt_interrupt_skip_source 213 { 214 GPT_INTERRUPT_SKIP_SOURCE_NONE = 0U, ///< Do not skip interrupts 215 GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW = 1U, ///< Count and skip overflow and underflow interrupts 216 217 /** Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in 218 * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest 219 * interrupt. */ 220 GPT_INTERRUPT_SKIP_SOURCE_CREST = 1U, 221 222 /** Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in 223 * @ref gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough 224 * interrupt. */ 225 GPT_INTERRUPT_SKIP_SOURCE_TROUGH = 2U, 226 } gpt_interrupt_skip_source_t; 227 228 /** Number of interrupts to skip between events */ 229 typedef enum e_gpt_interrupt_skip_count 230 { 231 GPT_INTERRUPT_SKIP_COUNT_0 = 0U, ///< Do not skip interrupts 232 GPT_INTERRUPT_SKIP_COUNT_1, ///< Skip one interrupt 233 GPT_INTERRUPT_SKIP_COUNT_2, ///< Skip two interrupts 234 GPT_INTERRUPT_SKIP_COUNT_3, ///< Skip three interrupts 235 GPT_INTERRUPT_SKIP_COUNT_4, ///< Skip four interrupts 236 GPT_INTERRUPT_SKIP_COUNT_5, ///< Skip five interrupts 237 GPT_INTERRUPT_SKIP_COUNT_6, ///< Skip six interrupts 238 GPT_INTERRUPT_SKIP_COUNT_7, ///< Skip seven interrupts 239 } gpt_interrupt_skip_count_t; 240 241 /** ADC events to skip during interrupt skipping */ 242 typedef enum e_gpt_interrupt_skip_adc 243 { 244 GPT_INTERRUPT_SKIP_ADC_NONE = 0U, ///< Do not skip ADC events 245 GPT_INTERRUPT_SKIP_ADC_A = 1U, ///< Skip ADC A events 246 GPT_INTERRUPT_SKIP_ADC_B = 4U, ///< Skip ADC B events 247 GPT_INTERRUPT_SKIP_ADC_A_AND_B = 5U, ///< Skip ADC A and B events 248 } gpt_interrupt_skip_adc_t; 249 250 /** Buffering mode */ 251 typedef enum e_gpt_buffer_mode 252 { 253 GPT_BUFFER_MODE_SINGLE = 1, ///< Single-buffer mode 254 GPT_BUFFER_MODE_DOUBLE = 2 ///< Double-buffer mode 255 } gpt_buffer_mode_t; 256 257 /** Delay setting for the PWM Delay Generation Circuit (PDG). */ 258 typedef enum e_gpt_pwm_output_delay_setting 259 { 260 GPT_PWM_OUTPUT_DELAY_SETTING_0_32, ///< Delay is not applied. 261 GPT_PWM_OUTPUT_DELAY_SETTING_1_32, ///< Delay of 1 / 32 GTCLK period applied. 262 GPT_PWM_OUTPUT_DELAY_SETTING_2_32, ///< Delay of 2 / 32 GTCLK period applied. 263 GPT_PWM_OUTPUT_DELAY_SETTING_3_32, ///< Delay of 3 / 32 GTCLK period applied. 264 GPT_PWM_OUTPUT_DELAY_SETTING_4_32, ///< Delay of 4 / 32 GTCLK period applied. 265 GPT_PWM_OUTPUT_DELAY_SETTING_5_32, ///< Delay of 5 / 32 GTCLK period applied. 266 GPT_PWM_OUTPUT_DELAY_SETTING_6_32, ///< Delay of 6 / 32 GTCLK period applied. 267 GPT_PWM_OUTPUT_DELAY_SETTING_7_32, ///< Delay of 7 / 32 GTCLK period applied. 268 GPT_PWM_OUTPUT_DELAY_SETTING_8_32, ///< Delay of 8 / 32 GTCLK period applied. 269 GPT_PWM_OUTPUT_DELAY_SETTING_9_32, ///< Delay of 9 / 32 GTCLK period applied. 270 GPT_PWM_OUTPUT_DELAY_SETTING_10_32, ///< Delay of 10 / 32 GTCLK period applied. 271 GPT_PWM_OUTPUT_DELAY_SETTING_11_32, ///< Delay of 11 / 32 GTCLK period applied. 272 GPT_PWM_OUTPUT_DELAY_SETTING_12_32, ///< Delay of 12 / 32 GTCLK period applied. 273 GPT_PWM_OUTPUT_DELAY_SETTING_13_32, ///< Delay of 13 / 32 GTCLK period applied. 274 GPT_PWM_OUTPUT_DELAY_SETTING_14_32, ///< Delay of 14 / 32 GTCLK period applied. 275 GPT_PWM_OUTPUT_DELAY_SETTING_15_32, ///< Delay of 15 / 32 GTCLK period applied. 276 GPT_PWM_OUTPUT_DELAY_SETTING_16_32, ///< Delay of 16 / 32 GTCLK period applied. 277 GPT_PWM_OUTPUT_DELAY_SETTING_17_32, ///< Delay of 17 / 32 GTCLK period applied. 278 GPT_PWM_OUTPUT_DELAY_SETTING_18_32, ///< Delay of 18 / 32 GTCLK period applied. 279 GPT_PWM_OUTPUT_DELAY_SETTING_19_32, ///< Delay of 19 / 32 GTCLK period applied. 280 GPT_PWM_OUTPUT_DELAY_SETTING_20_32, ///< Delay of 20 / 32 GTCLK period applied. 281 GPT_PWM_OUTPUT_DELAY_SETTING_21_32, ///< Delay of 21 / 32 GTCLK period applied. 282 GPT_PWM_OUTPUT_DELAY_SETTING_22_32, ///< Delay of 22 / 32 GTCLK period applied. 283 GPT_PWM_OUTPUT_DELAY_SETTING_23_32, ///< Delay of 23 / 32 GTCLK period applied. 284 GPT_PWM_OUTPUT_DELAY_SETTING_24_32, ///< Delay of 24 / 32 GTCLK period applied. 285 GPT_PWM_OUTPUT_DELAY_SETTING_25_32, ///< Delay of 25 / 32 GTCLK period applied. 286 GPT_PWM_OUTPUT_DELAY_SETTING_26_32, ///< Delay of 26 / 32 GTCLK period applied. 287 GPT_PWM_OUTPUT_DELAY_SETTING_27_32, ///< Delay of 27 / 32 GTCLK period applied. 288 GPT_PWM_OUTPUT_DELAY_SETTING_28_32, ///< Delay of 28 / 32 GTCLK period applied. 289 GPT_PWM_OUTPUT_DELAY_SETTING_29_32, ///< Delay of 29 / 32 GTCLK period applied. 290 GPT_PWM_OUTPUT_DELAY_SETTING_30_32, ///< Delay of 30 / 32 GTCLK period applied. 291 GPT_PWM_OUTPUT_DELAY_SETTING_31_32, ///< Delay of 31 / 32 GTCLK period applied. 292 GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS, ///< Bypass the PWM Output Delay Circuit. 293 } gpt_pwm_output_delay_setting_t; 294 295 /** Select which PWM Output Delay setting to apply. */ 296 typedef enum e_gpt_pwm_output_delay_edge 297 { 298 GPT_PWM_OUTPUT_DELAY_EDGE_RISING, ///< Configure the PWM Output Delay setting for rising edge. 299 GPT_PWM_OUTPUT_DELAY_EDGE_FALLING, ///< Configure the PWM Output Delay setting for falling edge. 300 } gpt_pwm_output_delay_edge_t; 301 302 /** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref timer_api_t::open is called. */ 303 typedef struct st_gpt_instance_ctrl 304 { 305 uint32_t open; // Whether or not channel is open 306 const timer_cfg_t * p_cfg; // Pointer to initial configurations 307 R_GPT0_Type * p_reg; // Base register for this channel 308 uint32_t channel_mask; // Channel bitmask 309 timer_variant_t variant; // Timer variant 310 311 void (* p_callback)(timer_callback_args_t *); // Pointer to callback 312 timer_callback_args_t * p_callback_memory; // Pointer to optional callback argument memory 313 void const * p_context; // Pointer to context to be passed into callback function 314 } gpt_instance_ctrl_t; 315 316 /** GPT extension for advanced PWM features. */ 317 typedef struct st_gpt_extended_pwm_cfg 318 { 319 uint8_t trough_ipl; ///< Trough interrupt priority 320 IRQn_Type trough_irq; ///< Trough interrupt 321 gpt_poeg_link_t poeg_link; ///< Select which POEG channel controls output disable for this GPT channel 322 gpt_output_disable_t output_disable; ///< Select which trigger sources request output disable from POEG 323 gpt_adc_trigger_t adc_trigger; ///< Select trigger sources to start A/D conversion 324 uint32_t dead_time_count_up; ///< Set a dead time value for counting up 325 uint32_t dead_time_count_down; ///< Set a dead time value for counting down 326 uint32_t adc_a_compare_match; ///< Select the compare match value 327 uint32_t adc_b_compare_match; ///< Select the compare match value 328 gpt_interrupt_skip_source_t interrupt_skip_source; ///< Interrupt source to count for interrupt skipping 329 gpt_interrupt_skip_count_t interrupt_skip_count; ///< Number of interrupts to skip between events 330 gpt_interrupt_skip_adc_t interrupt_skip_adc; ///< ADC events to skip when interrupt skipping is enabled 331 gpt_gtioc_disable_t gtioca_disable_setting; ///< Select how to configure GTIOCA when output is disabled 332 gpt_gtioc_disable_t gtiocb_disable_setting; ///< Select how to configure GTIOCB when output is disabled 333 } gpt_extended_pwm_cfg_t; 334 335 /** GPT extension configures the output pins for GPT. */ 336 typedef struct st_gpt_extended_cfg 337 { 338 gpt_output_pin_t gtioca; ///< Configuration for GPT I/O pin A 339 gpt_output_pin_t gtiocb; ///< Configuration for GPT I/O pin B 340 gpt_source_t start_source; ///< Event sources that trigger the timer to start 341 gpt_source_t stop_source; ///< Event sources that trigger the timer to stop 342 gpt_source_t clear_source; ///< Event sources that trigger the timer to clear 343 gpt_source_t capture_a_source; ///< Event sources that trigger capture of GTIOCA 344 gpt_source_t capture_b_source; ///< Event sources that trigger capture of GTIOCB 345 346 /** Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source 347 * and count_down_source, then the timer count source is P0CLK. */ 348 gpt_source_t count_up_source; 349 350 /** Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source 351 * and count_down_source, then the timer count source is P0CLK. */ 352 gpt_source_t count_down_source; 353 354 /* Debounce filter for GTIOCxA input signal pin. */ 355 gpt_capture_filter_t capture_filter_gtioca; 356 357 /* Debounce filter for GTIOCxB input signal pin. */ 358 gpt_capture_filter_t capture_filter_gtiocb; 359 360 uint8_t capture_a_ipl; ///< Capture A interrupt priority 361 uint8_t capture_b_ipl; ///< Capture B interrupt priority 362 IRQn_Type capture_a_irq; ///< Capture A interrupt 363 IRQn_Type capture_b_irq; ///< Capture B interrupt 364 gpt_extended_pwm_cfg_t const * p_pwm_cfg; ///< Advanced PWM features, optional 365 gpt_gtior_setting_t gtior_setting; ///< Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins. 366 } gpt_extended_cfg_t; 367 368 /********************************************************************************************************************** 369 * Exported global variables 370 **********************************************************************************************************************/ 371 372 /** @cond INC_HEADER_DEFS_SEC */ 373 /** Filled in Interface API structure for this Instance. */ 374 extern const timer_api_t g_timer_on_gpt; 375 376 /** @endcond */ 377 378 /*********************************************************************************************************************** 379 * Public APIs 380 **********************************************************************************************************************/ 381 fsp_err_t R_GPT_Open(timer_ctrl_t * const p_ctrl, timer_cfg_t const * const p_cfg); 382 fsp_err_t R_GPT_Stop(timer_ctrl_t * const p_ctrl); 383 fsp_err_t R_GPT_Start(timer_ctrl_t * const p_ctrl); 384 fsp_err_t R_GPT_Reset(timer_ctrl_t * const p_ctrl); 385 fsp_err_t R_GPT_Enable(timer_ctrl_t * const p_ctrl); 386 fsp_err_t R_GPT_Disable(timer_ctrl_t * const p_ctrl); 387 fsp_err_t R_GPT_PeriodSet(timer_ctrl_t * const p_ctrl, uint32_t const period_counts); 388 fsp_err_t R_GPT_DutyCycleSet(timer_ctrl_t * const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin); 389 fsp_err_t R_GPT_InfoGet(timer_ctrl_t * const p_ctrl, timer_info_t * const p_info); 390 fsp_err_t R_GPT_StatusGet(timer_ctrl_t * const p_ctrl, timer_status_t * const p_status); 391 fsp_err_t R_GPT_CounterSet(timer_ctrl_t * const p_ctrl, uint32_t counter); 392 fsp_err_t R_GPT_OutputEnable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); 393 fsp_err_t R_GPT_OutputDisable(timer_ctrl_t * const p_ctrl, gpt_io_pin_t pin); 394 fsp_err_t R_GPT_AdcTriggerSet(timer_ctrl_t * const p_ctrl, 395 gpt_adc_compare_match_t which_compare_match, 396 uint32_t compare_match_value); 397 fsp_err_t R_GPT_PwmOutputDelaySet(timer_ctrl_t * const p_ctrl, 398 gpt_pwm_output_delay_edge_t edge, 399 gpt_pwm_output_delay_setting_t delay_setting, 400 uint32_t const pin); 401 fsp_err_t R_GPT_CallbackSet(timer_ctrl_t * const p_api_ctrl, 402 void ( * p_callback)(timer_callback_args_t *), 403 void const * const p_context, 404 timer_callback_args_t * const p_callback_memory); 405 fsp_err_t R_GPT_Close(timer_ctrl_t * const p_ctrl); 406 fsp_err_t R_GPT_PwmOutputDelayInitialize(); 407 408 /*******************************************************************************************************************//** 409 * @} (end defgroup GPT) 410 **********************************************************************************************************************/ 411 412 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 413 FSP_FOOTER 414 415 #endif 416
