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Searched refs:GPTCKSRDY (Results 1 – 15 of 15) sorted by relevance

/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA2L1AB.h10696 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA2A1AB.h10958 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA4E10D.h10555 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA4W1AD.h11044 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA4M1AB.h11208 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA4M2AD.h11544 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA4M3AF.h11544 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA4E2B9.h12359 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA6E10F.h11973 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA6M1AD.h11740 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA6E2BB.h12563 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA6M4AF.h12307 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA6M2AF.h13721 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA6M3AH.h16379 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member
DR7FA6M5BH.h14569 …__IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag … member