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Searched refs:CPG_PL1_DDIV (Results 1 – 2 of 2) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/mcu/all/
Dbsp_clocks.c179 R_CPG->CPG_PL1_DDIV = in bsp_clock_freq_init_cfg()
702 R_CPG->CPG_PL1_DDIV = (uint32_t) (R_CPG_CPG_PL1_DDIV_DIV_PLL1SET_WEN_Msk | in bsp_prv_clock_divider_set()
/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/
Dcpg_iodefine.h342 __IOM uint32_t CPG_PL1_DDIV; member