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Searched refs:CLO (Results 1 – 21 of 21) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/cmsis/Device/RENESAS/Include/R9A08G045S/iodefines/
Driic_iodefine.h36 __IOM uint8_t CLO : 1; member
/hal_renesas-latest/drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
DR7FA2L1AB.h7293 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA2A1AB.h7228 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA4E10D.h6998 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA4W1AD.h7407 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA4M1AB.h7407 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA4M2AD.h7297 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA4M3AF.h7297 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA4E2B9.h7667 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA6E10F.h7726 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA6M1AD.h7261 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA6E2BB.h7667 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA6M4AF.h8060 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA4L1BD.h9303 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA6M2AF.h7989 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA6M3AH.h11262 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA6M5BH.h9185 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA8T1AH.h8930 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA8M1AH.h8965 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
DR7FA8D1BH.h10554 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member
/hal_renesas-latest/drivers/rz/fsp/src/rzn/bsp/cmsis/Device/RENESAS/Include/
DR9A07G084.h5031 …__IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output … member