Searched refs:BSP_PRV_SCKDIVCR_DIV_VALUE (Results 1 – 2 of 2) sorted by relevance
142 #define BSP_PRV_SCKDIVCR_DIV_VALUE(div) (((div) & 8U) ? (3U << ((div) & ~8U)) : (1U << (div))) macro143 #define BSP_PRV_CPUCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_CPUCLK_DIV)146 #define BSP_PRV_ICLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_ICLK_DIV)151 #define BSP_PRV_PCLKA_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKA_DIV)152 #define BSP_PRV_PCLKB_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKB_DIV)153 #define BSP_PRV_PCLKC_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKC_DIV)154 #define BSP_PRV_PCLKD_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKD_DIV)155 #define BSP_PRV_PCLKE_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_PCLKE_DIV)156 #define BSP_PRV_BCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_BCLK_DIV)157 #define BSP_PRV_FCLK_DIV_VALUE BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_CFG_FCLK_DIV)
1039 uint32_t requested_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE( in prv_clock_dividers_set()1041 uint32_t current_iclk_div = BSP_PRV_SCKDIVCR_DIV_VALUE(R_SYSTEM->SCKDIVCR_b.ICK); in prv_clock_dividers_set()1083 uint32_t iclk_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(iclk_div); in bsp_prv_clock_set()1086 … uint32_t clock_freq_hz_post_change = g_clock_freq[clock] / BSP_PRV_SCKDIVCR_DIV_VALUE(cpuclk_div); in bsp_prv_clock_set()1535 #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) in bsp_prv_clock_set_hard_reset()1561 #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET) in bsp_prv_clock_set_hard_reset()
