Searched refs:BSP_PRV_GIC_REG_BITS1 (Results 1 – 1 of 1) sorted by relevance
51 #define BSP_PRV_GIC_REG_BITS1 (1U) macro108 (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); in r_bsp_irq_clear_pending()113 GICR_TARGET0_INTREG->GICR_ICPENDR0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); in r_bsp_irq_clear_pending()171 (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); in r_bsp_irq_cfg()185 GICR_TARGET0_INTREG->GICR_IGROUPR0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); in r_bsp_irq_cfg()215 (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); in r_bsp_irq_enable_no_clear()220 GICR_TARGET0_INTREG->GICR_ISENABLER0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); in r_bsp_irq_enable_no_clear()242 (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); in r_bsp_irq_disable()247 GICR_TARGET0_INTREG->GICR_ICENABLER0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); in r_bsp_irq_disable()
