1 /* 2 * Copyright (c) 2020 - 2025 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*********************************************************************************************************************** 8 * 9 * AUTOGENERATED FILE. DO NOT EDIT. 10 * 11 **********************************************************************************************************************/ 12 13 #ifndef BSP_FEATURE_H 14 #define BSP_FEATURE_H 15 16 /*********************************************************************************************************************** 17 * Includes <System Includes> , "Project Includes" 18 **********************************************************************************************************************/ 19 20 #include "bsp_peripheral.h" 21 22 /*********************************************************************************************************************** 23 * Macro definitions 24 **********************************************************************************************************************/ 25 26 /** The main oscillator drive value is based upon the oscillator frequency selected in the configuration. */ 27 #define CGC_MAINCLOCK_DRIVE_RESERVED_MASK (0x0U) 28 #if (BSP_CFG_XTAL_HZ >= (10000000)) 29 #define CGC_MAINCLOCK_DRIVE (0x0U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) 30 #else 31 #define CGC_MAINCLOCK_DRIVE (0x1U | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) 32 #endif 33 34 // *UNCRUSTIFY-OFF* 35 36 #define BSP_FEATURE_ACMPHS_IS_AVAILABLE (0UL) 37 #define BSP_FEATURE_ACMPHS_MIN_WAIT_TIME_US (0UL) // Feature not available on this device. 38 #define BSP_FEATURE_ACMPHS_VREF (0UL) // Feature not available on this device. 39 40 #define BSP_FEATURE_ACMPLP_IS_AVAILABLE (1UL) 41 #define BSP_FEATURE_ACMPLP_HAS_COMPSEL_REGISTERS (0UL) // COMPSELn registers are available. 42 #define BSP_FEATURE_ACMPLP_MIN_WAIT_TIME_US (100UL) // Operation stabilization wait time. 43 44 #define BSP_FEATURE_ADC_IS_AVAILABLE (1UL) 45 #define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1UL) // Check to see if the ADADC register is available on any ADC peripheral. 46 #define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0UL) // Check to see if the ADCALEXE register is available on any ADC peripheral. 47 #define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKC) // Clock source used for the ADC peripheral. 48 #define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (0UL) // The Extended Input Control Register (ADEXICR) controls if sensors are enabled per group. 49 #define BSP_FEATURE_ADC_HAS_ADBUF (0UL) // Determine if the ADBUFn registers are present. 50 #define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (0UL) // Determine if the ADPRC field exists on the ADCER register. 51 #define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1UL) // Determine if the ADRFMT field exists on the ADCER register. 52 #define BSP_FEATURE_ADC_HAS_ADHVREFCNT (1UL) // Determine if the ADHVREFCNT register is available. 53 #define BSP_FEATURE_ADC_HAS_PGA (0UL) // Determine if ADPGACR is present. 54 #define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (0UL) // Specifies configuration for the sample and hold circuit is available (specifically ADSHCR register). 55 #define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0UL) // Determine if VREFAMPCNT is present. 56 #define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12UL) // Maximum ADC resolution supported. 57 #define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (5000UL) // Minimum time, in nanoseconds, required for ADC sampling of the sensors. 58 #define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (1UL) // Specifies that the temperature and VREF sensors are exclusive to other ADC channel operations and cannot be executed concurrently. 59 #define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (1UL) // Determine if the temperature sensor supports calibration, either factory or runtime. 60 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (0UL) // Determine if TSCDR is available. 61 #define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00UL) // Create the mask for the valid calibration data provided by TSCDR. 62 #define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (0UL) // Determine if the TSCR register is present. 63 #define BSP_FEATURE_ADC_TSN_SLOPE (-3300LL) // Typical slope for the temperature sensor, in uV/degC. 64 #define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x03FF007FUL) // Mask of available channels in ADC unit 0. 65 #define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x00UL) // Mask of available channels in ADC unit 1. 66 #define BSP_FEATURE_ADC_VALID_UNIT_MASK (0x01UL) // Mask of whole, physical ADC units present in the MCU. 67 68 #define BSP_FEATURE_ADC_B_IS_AVAILABLE (0UL) 69 #define BSP_FEATURE_ADC_B_PGA_CHANNEL_MASK (0x00UL) // Feature not available on this device. 70 #define BSP_FEATURE_ADC_B_PGA_SUPPORTED (0UL) // Feature not available on this device. 71 #define BSP_FEATURE_ADC_B_TSN_CALIBRATION32_MASK (0x00UL) // Feature not available on this device. 72 #define BSP_FEATURE_ADC_B_TSN_SLOPE (0UL) // Feature not available on this device. 73 #define BSP_FEATURE_ADC_B_UNIT_0_CHANNELS (0x00ULL) // Feature not available on this device. 74 #define BSP_FEATURE_ADC_B_UNIT_1_CHANNELS (0x00ULL) // Feature not available on this device. 75 76 #define BSP_FEATURE_ADC_D_IS_AVAILABLE (0UL) 77 #define BSP_FEATURE_ADC_D_CHANNELS (0x00UL) // Feature not available on this device. 78 #define BSP_FEATURE_ADC_D_SCAN_MODE_CHANNELS (0x00UL) // Feature not available on this device. 79 80 #define BSP_FEATURE_AGT_IS_AVAILABLE (1UL) 81 #define BSP_FEATURE_AGT_AGT_CHANNEL_COUNT (0U) // Number of channels for only AGT (not AGTW) peripherals. 82 #define BSP_FEATURE_AGT_AGTW_CHANNEL_COUNT (2U) // Number of channels for only AGTW (not AGT) peripherals. 83 #define BSP_FEATURE_AGT_USE_AGTIOSEL_ALT (0UL) // Indicates use of AGTIOSEL_ALT instead of AGTIOSEL for AGTW instances. 84 #define BSP_FEATURE_AGT_VALID_CHANNEL_MASK (0x03UL) // A mask of all valid AGTx channels. 85 86 #define BSP_FEATURE_BSP_CODE_CACHE_VERSION (1UL) // Version of C-Cache implemented in a CM33 core. 87 #define BSP_FEATURE_BSP_FLASH_CACHE (0UL) // Flash cache is present. 88 #define BSP_FEATURE_BSP_FLASH_CACHE_DISABLE_OPM (0UL) // Constraints exist for flash cache operation either during power mode sequencing or flash programming access. 89 #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1UL) // Indicates the prefetch buffer is available on the flash. 90 #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0UL) // Indicates there is a separate clock for the ADC. 91 #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1UL) // Indicates there is a separate clock for the CANFD. 92 #define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0UL) // Indicates there is a separate clock for the CEC. 93 #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0UL) // Check for the ICSTATS bit field that specifies clock power architecture type. 94 #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0UL) // DCDCCTL register is present in SYSC. 95 #define BSP_FEATURE_BSP_HAS_DTCM (0UL) // Indicates DTCM is available. 96 #define BSP_FEATURE_BSP_HAS_EXTRA_PERIPHERAL0_CLOCK (0UL) // Flag indicating an extra peripheral clock is present. 97 #define BSP_FEATURE_BSP_HAS_FSXP_CLOCK (0UL) // Indicates FSXP (subsystem clock) is available. 98 #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0UL) // Indicates that the MCU has a power domain specifically for graphics peripherals. 99 #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (1UL) // Indicates there is a separate clock for the I3C. 100 #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0UL) // Indicates there is a separate IIC clock. 101 #define BSP_FEATURE_BSP_HAS_ITCM (0UL) // Indicates ITCM is available. 102 #define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0UL) // Indicates there is a separate clock for the LCD. 103 #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0UL) // Indicates there is a separate clock for the OSPI. 104 #define BSP_FEATURE_BSP_HAS_OFS2 (0UL) // Indicates the OFS2 register is available. 105 #define BSP_FEATURE_BSP_HAS_OFS3 (0UL) // OSF3 register is available; currently only available for RA8. 106 #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0UL) // Indicates the AES peripheral is available for an RA2 device. 107 #define BSP_FEATURE_BSP_HAS_SCE5 (0UL) // Indicates the SCE5 crypto engine is available. 108 #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0UL) // Indicates there is a separate SCI clock. 109 #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0UL) // Indicates there is a separate SCI SPI clock. 110 #define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0UL) // Indicates there is a separate clock for the SDADC. 111 #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0UL) // Indicates the MCU has security MPU systems available. 112 #define BSP_FEATURE_BSP_HAS_SP_MON (0UL) // Indicates the Stack Pointer monitor is available. 113 #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0UL) // Indicates there is a separate clock for the SPI. 114 #define BSP_FEATURE_BSP_HAS_SYRACCR (0UL) // SYRACCR register is available. 115 #define BSP_FEATURE_BSP_HAS_TZFSAR (1UL) // Specifies the TrustZone filter can be secured. 116 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0UL) // Indicates there is a USB clock divider setting as part of the SCKDIVCR registers. 117 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1UL) // Indicates that a request bit must be set before changing USB clock settings. 118 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1UL) // Indicates the USB clock has a selectable source. 119 #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0UL) // Indicates the USBCKCR_ALT register should be used instead of USBCKCR. 120 #define BSP_FEATURE_BSP_HAS_USB60_CLOCK (0UL) // Indicates the USB60 clock is available. 121 #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0UL) // USBCKDIVCR register is available. 122 #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0x00U) // Location of the FMIFRT register. 123 #define BSP_FEATURE_BSP_MMF_SUPPORTED (0UL) // Memory-mirror function is available. 124 #define BSP_FEATURE_BSP_MPU_REGION0_MASK (0x00UL) // Mask for allowed address range of the MPU. 125 #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5 (0UL) // GPT stop bits use MSTPCRD.MSTPD5. 126 #define BSP_FEATURE_BSP_MSTP_GPT_MSTPD5_MAX_CH (0UL) // Largest channel number associated with GPT on the MSTPCRD.MSTPD5 field on this MCU. 127 #define BSP_FEATURE_BSP_MSTP_HAS_MSTPCRE (1UL) // Indicates the MSTP peripheral has an MSTPCRE register. 128 #define BSP_FEATURE_BSP_MSTP_POEG_MSTPD13 (0UL) // Indicates the MSTP uses bit 13 of MSTPCRD to control the POEG. 129 #define BSP_FEATURE_BSP_NUM_PMSAR (9UL) // Number of available Port Security Attribution Registers. 130 #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1UL) // Indicates security attribution settings for banks are present in the OFS registers. 131 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF1FFUL) // Inverted mask of the HOCOFRQx bit field of the OFS1 register. 132 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9UL) // Offset to the OFS1.HOCOFRQx bitfield. 133 #define BSP_FEATURE_BSP_OSIS_PADDING (0UL) // Indicates there is 32-bits of padding between each 32-bit word of the OSIS ID registers. 134 #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0UL) // Indicates extra modules must be manually stopped before switching the system clock from the PLL. 135 #define BSP_FEATURE_BSP_RESET_TRNG (0UL) // Specifies the TRNG must be reset after clock initialization to prevent excess current draw. 136 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FIVE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring five wait cycles. 137 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_FOUR_ROM_WAITS (0UL) // The maximum frequency allowed without having four ROM wait cycles. 138 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_NO_RAM_WAITS (0UL) // The maximum frequency that can be used before wait cycles are necessary. 139 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_ONE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring one wait cycle. 140 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_THREE_ROM_WAITS (0UL) // Maximum frequency allowed before requiring three wait cycles. 141 #define BSP_FEATURE_BSP_SYS_CLOCK_FREQ_TWO_ROM_WAITS (0UL) // Maximum frequency allowed before requiring two wait cycles. 142 #define BSP_FEATURE_BSP_UNIQUE_ID_OFFSET (0x00UL) // Bit offset of the Unique ID in the mcu info block. 143 #define BSP_FEATURE_BSP_UNIQUE_ID_POINTER (0x01008190UL) // Address of the MCU Unique ID register (UIDR). 144 #define BSP_FEATURE_BSP_VBATT_HAS_VBTCR1_BPWSWSTP (0UL) // VCC can switch to VBAT if the voltage drops too low. 145 146 #define BSP_FEATURE_CAN_IS_AVAILABLE (0UL) 147 #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0UL) // Feature not available on this device. 148 #define BSP_FEATURE_CAN_CLOCK (0UL) // Feature not available on this device. 149 #define BSP_FEATURE_CAN_MCLOCK_ONLY (0UL) // Feature not available on this device. 150 #define BSP_FEATURE_CAN_NUM_CHANNELS (0UL) // Feature not available on this device. 151 152 #define BSP_FEATURE_CANFD_IS_AVAILABLE (1UL) 153 #define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') // Flexible data rate support. 154 #define BSP_FEATURE_CANFD_LITE (1UL) // CANFD Lite or CANFD_B is the standard CAN peripheral for new designs. 155 #define BSP_FEATURE_CANFD_NUM_CHANNELS (1UL) // Number of CANFD channels per CANFD peripheral instance. 156 #define BSP_FEATURE_CANFD_NUM_INSTANCES (1UL) // Number of hardware instances of the CANFD peripheral. 157 158 #define BSP_FEATURE_CGC_EXECUTE_FROM_LOCO (1UL) // Indicates the system clock can be sourced by the LOCO. 159 #define BSP_FEATURE_CGC_HAS_BCLK (0UL) // External Bus Clock is available. 160 #define BSP_FEATURE_CGC_HAS_CPUCLK (0UL) // CPU Clock is available. 161 #define BSP_FEATURE_CGC_HAS_EXTRACLK2 (0UL) // System contains an extra clock domain. 162 #define BSP_FEATURE_CGC_HAS_FCLK (1UL) // FlashIF clock is available. 163 #define BSP_FEATURE_CGC_HAS_FLDWAITR (1UL) // FLDWAITR register is available. 164 #define BSP_FEATURE_CGC_HAS_FLL (0UL) // FLL is available. 165 #define BSP_FEATURE_CGC_HAS_FLWT (0UL) // FLWT register is available. 166 #define BSP_FEATURE_CGC_HAS_HOCOWTCR (0UL) // HOCOWTCR register is available. 167 #define BSP_FEATURE_CGC_HAS_MEMWAIT (1UL) // MEMWAIT register is available. 168 #define BSP_FEATURE_CGC_HAS_OSTDCSE (0UL) // OSTDCSE register is available. 169 #define BSP_FEATURE_CGC_HAS_PCLKA (1UL) // Peripheral module clock A is available. 170 #define BSP_FEATURE_CGC_HAS_PCLKB (1UL) // Peripheral module clock B is available. 171 #define BSP_FEATURE_CGC_HAS_PCLKC (1UL) // Peripheral module clock C is available. 172 #define BSP_FEATURE_CGC_HAS_PCLKD (1UL) // Peripheral module clock D is available. 173 #define BSP_FEATURE_CGC_HAS_PCLKE (0UL) // Peripheral module clock E is available. 174 #define BSP_FEATURE_CGC_HAS_PLL (1UL) // PLL is available. 175 #define BSP_FEATURE_CGC_HAS_PLL2 (0UL) // PLL2 is available. 176 #define BSP_FEATURE_CGC_HAS_PLLRTC (0UL) // PLLRTC is available. 177 #define BSP_FEATURE_CGC_HAS_SOPCCR (1UL) // SOPCCR register is available. 178 #define BSP_FEATURE_CGC_HAS_SOSC (1UL) // Sub-clock oscillator is available. 179 #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0UL) // SRAMPRCR2 register is available. 180 #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0UL) // SRAM Wait State Control Register is available. 181 #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0UL) // Changes to OPCCR must only occur with HOCO is stopped or stable. 182 #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0UL) // HOCO wait control register changes value for 64 MHz speed. 183 #define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0UL) // HOCO stabilization wait time when using SCI0. 184 #define BSP_FEATURE_CGC_HOCOWTCR_VALUE (0UL) // HOCO stabilization wait time register value for 64 MHz. 185 #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) // Reset value of the ICLK divider. 186 #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61UL) // LOCO stabilization time in microseconds. 187 #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000UL) // Maximum frequency during low-speed operation. 188 #define BSP_FEATURE_CGC_LOW_SPEED_SUPPORT_MAIN_OSC (1UL) // The main clock oscillator is available in low-speed mode. 189 #define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0UL) // Maximum frequency during low-voltage mode. 190 #define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (8000000UL) // Middle speed clock maximum frequency. 191 #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (1UL) // MOCO stabilization time in microseconds. 192 #define BSP_FEATURE_CGC_MODRV_MASK (R_SYSTEM_MOMCR_MODRV1_Msk | CGC_MAINCLOCK_DRIVE_RESERVED_MASK) // Mask used on MODRV register. 193 #define BSP_FEATURE_CGC_MODRV_SHIFT (R_SYSTEM_MOMCR_MODRV1_Pos) // Shift used for MODRV register. 194 #define BSP_FEATURE_CGC_OSCILLATON_STOP_DETECT (1UL) // Oscillation stop detection is available. 195 #define BSP_FEATURE_CGC_PLL_HOCO_MAX_CPUCLK_HZ (0UL) // Maximum allowed clock speed when HOCO is the PLL source clock for the CPUCLK. 196 #define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ (80000000UL) // Maximum output frequency for PLL unit 1. 197 #define BSP_FEATURE_CGC_PLL_OUT_MIN_HZ (24000000UL) // Minimum output frequency for PLL unit 1. 198 #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MAX_HZ (0UL) // Maximum frequency of the PLL reference clock. 199 #define BSP_FEATURE_CGC_PLL_REFERENCE_CLK_MIN_HZ (0UL) // Minimum frequency of the PLL reference clock. 200 #define BSP_FEATURE_CGC_PLL_SRC_MAX_HZ (12500000UL) // Maximum input frequency for PLL unit 1. 201 #define BSP_FEATURE_CGC_PLL_SRC_MIN_HZ (4000000UL) // Minimum output frequency for PLL unit 1. 202 #define BSP_FEATURE_CGC_PLL1_NUM_OUTPUT_CLOCKS (1UL) // Number of output clocks for PLL1. 203 #define BSP_FEATURE_CGC_PLL2_NUM_OUTPUT_CLOCKS (0UL) // Number of output clocks for PLL2. 204 #define BSP_FEATURE_CGC_PLL2_OUT_MAX_HZ (0UL) // Maximum output frequency for PLL unit 2. 205 #define BSP_FEATURE_CGC_PLL2_OUT_MIN_HZ (0UL) // Minimum output frequency for PLL unit 2. 206 #define BSP_FEATURE_CGC_PLLCCR_TYPE (5UL) // Indicates the type of PLLCCR register and PLL. 207 #define BSP_FEATURE_CGC_PLLCCR_VCO_MAX_HZ (80000000UL) // PLL VCO maximum frequency. 208 #define BSP_FEATURE_CGC_PLLCCR_VCO_MIN_HZ (0UL) // PLL VCO minimum frequency. 209 #define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0UL) // Time required, in microseconds, between changing PLLCCR.PLLMUL to clearing PLLCR.PLLSTP. 210 #define BSP_FEATURE_CGC_REGISTER_SET_B (0UL) // Clock generation uses an alternative register set. 211 #define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0UL) // Requires the SCKDIVCR.BCLK bits [18:16] to match SCKDIBCR.PCLKB. 212 #define BSP_FEATURE_CGC_SCKDIVCR2_HAS_EXTRA_CLOCKS (0UL) // Indicates the SCKDIVCR2 register has additional clocks. 213 #define BSP_FEATURE_CGC_SODRV_MASK (0x03UL) // Sub-clock drive field mask. 214 #define BSP_FEATURE_CGC_SODRV_SHIFT (0UL) // Sub-clock drive field shift. 215 #define BSP_FEATURE_CGC_SRAMPRCR_KW_OFFSET (1UL) // Bit offset for SRAMPRCR.KW field. 216 #define BSP_FEATURE_CGC_SRAMPRCR_KW_VALUE (0x78U) // Write enable key code for SRAMPRCR bit. 217 #define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0x01UL) // Reset value for the OPCCR regsiter. 218 #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR (0x44004444UL) // Reset value for the SCKDIVCR register. 219 #define BSP_FEATURE_CGC_STARTUP_SCKDIVCR2 (0x00UL) // Reset value for the SCKDIVCR2 register. 220 #define BSP_FEATURE_CGC_STARTUP_SCKSCR (0x01UL) // Reset value for the SCKSCR register. 221 222 #define BSP_FEATURE_CRC_IS_AVAILABLE (1UL) 223 #define BSP_FEATURE_CRC_HAS_CRCCR0_LMS (1UL) // The CRC peripheral supports both LSB- and MSB-first calculations. 224 #define BSP_FEATURE_CRC_HAS_SNOOP (0UL) // The CRC peripheral can snoop on (monitor a) SCI data register for data to checksum. 225 #define BSP_FEATURE_CRC_POLYNOMIAL_MASK (0x3EU) // Mask of available CRC polynomials; should match the mask of indexes relating to r_crc_api.h::crc_polynomial_t. 226 #define BSP_FEATURE_CRC_SNOOP_ADDRESS_TYPE_TDR (0x00UL) // Used to indicate the type of register being snooped on; derived from the least-significant nybble of the address of SCI TDR registers. 227 228 #define BSP_FEATURE_CRYPTO_HAS_AES (1UL) // AES support is available. 229 #define BSP_FEATURE_CRYPTO_HAS_AES_WRAPPED (1UL) // AES support with key-wrapping is available. 230 #define BSP_FEATURE_CRYPTO_HAS_CTR_DRBG (1UL) // AES CTR-DRBG pseudo random number support is available. 231 #define BSP_FEATURE_CRYPTO_HAS_ECC (1UL) // ECC support is available. 232 #define BSP_FEATURE_CRYPTO_HAS_ECC_WRAPPED (1UL) // ECC support with key-wrapping is available. 233 #define BSP_FEATURE_CRYPTO_HAS_HASH (1UL) // Hashing support is available. 234 #define BSP_FEATURE_CRYPTO_HAS_RSA (0UL) // RSA support is available. 235 #define BSP_FEATURE_CRYPTO_HAS_RSA_WRAPPED (0UL) // RSA support with key-wrapping is available. 236 237 #define BSP_FEATURE_CTSU_IS_AVAILABLE (1UL) 238 #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (2UL) // Number of CTSUCHAC registers. 239 #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (2UL) // Number of CTSUCHTRC registers. 240 #define BSP_FEATURE_CTSU_HAS_TXVSEL (1UL) // CTSUCR0.CTSUTXVSEL field is available. 241 #define BSP_FEATURE_CTSU_VERSION (2UL) // Version of the CTSU peripheral. 242 243 #define BSP_FEATURE_DAC_IS_AVAILABLE (1UL) 244 #define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x00UL) // DAADSCR register is available. 245 #define BSP_FEATURE_DAC_B_CHANNELS_PER_UNIT (0UL) // Number of available channels per DAC_B instance. 246 #define BSP_FEATURE_DAC_B_UNIT_COUNT (0UL) // Number of available DAC_B instance. 247 #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0UL) // DAPC register is available. 248 #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1UL) // At least one channel supports A/D synchronization with the DAC. 249 #define BSP_FEATURE_DAC_HAS_DAVREFCR (1UL) // DAVREFCR register is available. 250 #define BSP_FEATURE_DAC_HAS_INTERNAL_OUTPUT (0UL) // DAC output can be routed to specific extra internal modules. 251 #define BSP_FEATURE_DAC_HAS_OUTPUT_AMPLIFIER (0UL) // DAAMPCR register is available. 252 253 #define BSP_FEATURE_DAC8_IS_AVAILABLE (0UL) 254 #define BSP_FEATURE_DAC8_CHANNELS_PER_UNIT (0UL) // Feature not available on this device. 255 #define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0UL) // Feature not available on this device. 256 #define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0UL) // Feature not available on this device. 257 #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0UL) // Feature not available on this device. 258 #define BSP_FEATURE_DAC8_UNIT_COUNT (0UL) // Feature not available on this device. 259 260 #define BSP_FEATURE_DAC12_IS_AVAILABLE (1UL) 261 #define BSP_FEATURE_DAC12_CHANNELS_PER_UNIT (1UL) // Number of available channels per DAC12 instance. 262 #define BSP_FEATURE_DAC12_UNIT_COUNT (1UL) // Number of available DAC12 instance. 263 264 #define BSP_FEATURE_DMAC_IS_AVAILABLE (1UL) 265 #define BSP_FEATURE_DMAC_HAS_DELSR (0UL) // DELSRn registers are available in the DMA peripheral block. 266 #define BSP_FEATURE_DMAC_HAS_DMCTL (0UL) // DMCTL register is available in the DMA peripheral block. 267 #define BSP_FEATURE_DMAC_HAS_REPEAT_BLOCK_MODE (1UL) // DMTMD register's MD bit-field allows repeat-block transfers (value: 0b11). 268 #define BSP_FEATURE_DMAC_MAX_CHANNEL (8UL) // Number of DMAC channels available. 269 270 #define BSP_FEATURE_DOC_IS_AVAILABLE (1UL) 271 #define BSP_FEATURE_DOC_VERSION (2UL) // The version of the DOC peripheral. 272 273 #define BSP_FEATURE_DTC_TRANSFER_INFO_ALIGNMENT (4UL) // Byte alignment that must be used for DTC transfer info structs. 274 275 #define BSP_FEATURE_DWT_CYCCNT (1UL) // CYCNT register is available on CM33 and higher devices. 276 277 #define BSP_FEATURE_ELC_VERSION (1UL) // Version of the ELC peripheral. 278 279 #define BSP_FEATURE_ESC_IS_AVAILABLE (0UL) 280 #define BSP_FEATURE_ESC_MAX_PORTS (0UL) // Feature not available on this device. 281 282 #define BSP_FEATURE_ETHER_IS_AVAILABLE (0UL) 283 #define BSP_FEATURE_ETHER_FIFO_DEPTH (0x00UL) // Feature not available on this device. 284 #define BSP_FEATURE_ETHER_MAX_CHANNELS (0UL) // Feature not available on this device. 285 #define BSP_FEATURE_ETHER_MAX_QUEUE_NUM (0UL) // Feature not available on this device. 286 #define BSP_FEATURE_ETHER_SUPPORTS_TZ_SECURE (0UL) // Feature not available on this device. 287 288 #define BSP_FEATURE_FLASH_ARC_NSEC_MULTIPLE_MAX_COUNT (0UL) // Number of bits per counter when ARC_NSEC is configured as multiple counters. 289 #define BSP_FEATURE_FLASH_ARC_NSEC_NUM_COUNTERS (0L) // Number of non-secure application anti-rollback counters that can be configured. 290 #define BSP_FEATURE_FLASH_ARC_NSEC_SINGLE_MAX_COUNT (0UL) // Number of counter bits available when using the ARC_NSEC counter as a single, large counter. 291 #define BSP_FEATURE_FLASH_ARC_OEMBL_MAX_COUNT (0UL) // Number of counter bits for the ARC_OEMBL counter. 292 #define BSP_FEATURE_FLASH_ARC_SEC_MAX_COUNT (0UL) // Number of counter bits for the ARC_SEC counter. 293 #define BSP_FEATURE_FLASH_CODE_FLASH_START (0x00UL) // Start address of the Code Flash region. 294 #define BSP_FEATURE_FLASH_DATA_FLASH_START (0x08000000UL) // Start address of the Data Flash region. 295 #define BSP_FEATURE_FLASH_SUPPORTS_ACCESS_WINDOW (0UL) // Flash supports protected access window (AWS register is available). 296 #define BSP_FEATURE_FLASH_SUPPORTS_ANTI_ROLLBACK (0UL) // Flash supports anti-rollback counter (ARC_* registers are available). 297 #define BSP_FEATURE_FLASH_SUPPORTS_ID_CODE (0UL) // ID code is supported (OSIS register is available). 298 #define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_SIZE (0UL) // Size of the user lockable areas (non-OFS registers). 299 #define BSP_FEATURE_FLASH_USER_LOCKABLE_AREA_START (0x00UL) // Start address of the first non-OFS lockable word by LK_CD_A0. 300 301 #define BSP_FEATURE_FLASH_HP_IS_AVAILABLE (1UL) 302 #define BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START (0x00200000UL) // Start of the second code flash bank. 303 #define BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE (0x0800UL) // Block size of region 0. 304 #define BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE (0x00010000UL) // Size of region 0. 305 #define BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE (0x0800UL) // Block size of region 1. 306 #define BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE (8UL) // Write size for code flash. 307 #define BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE (256UL) // Block size of data flash. 308 #define BSP_FEATURE_FLASH_HP_DF_WRITE_SIZE (1UL) // Write size for data flash. 309 #define BSP_FEATURE_FLASH_HP_HAS_BANKSEL (1UL) // BANKSEL, BANKSEL_SEC and BANKSEL_SEL registers are present. 310 #define BSP_FEATURE_FLASH_HP_HAS_FMEPROT (1UL) // FMEPROT register is present. 311 #define BSP_FEATURE_FLASH_HP_SUPPORTS_DUAL_BANK (1UL) // Device contains two code banks. 312 #define BSP_FEATURE_FLASH_HP_VERSION (4UL) // Version of the FLASH_HP (FACI) peripheral/hardware. 313 314 #define BSP_FEATURE_FLASH_LP_IS_AVAILABLE (0UL) 315 #define BSP_FEATURE_FLASH_LP_AWS_FAW_MASK (0x00UL) // Feature not available on this device. 316 #define BSP_FEATURE_FLASH_LP_AWS_FAW_SHIFT (0UL) // Feature not available on this device. 317 #define BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE (0x00UL) // Feature not available on this device. 318 #define BSP_FEATURE_FLASH_LP_CF_DUAL_BANK_START (0x00UL) // Feature not available on this device. 319 #define BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE (0x00UL) // Feature not available on this device. 320 #define BSP_FEATURE_FLASH_LP_DF_BLOCK_SIZE (0x00UL) // Feature not available on this device. 321 #define BSP_FEATURE_FLASH_LP_DF_WRITE_SIZE (0x00UL) // Feature not available on this device. 322 #define BSP_FEATURE_FLASH_LP_FLASH_CLOCK_SRC (0) // Feature not available on this device. 323 #define BSP_FEATURE_FLASH_LP_SUPPORTS_DUAL_BANK (0UL) // Feature not available on this device. 324 #define BSP_FEATURE_FLASH_LP_VERSION (0UL) // Feature not available on this device. 325 326 #define BSP_FEATURE_GPT_IS_AVAILABLE (1UL) 327 #define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x03UL) // Mask of 32-bit GPT channel indices. 328 #define BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK (0x00UL) // Mask of GPT channels supporting A/D conversion start. 329 #define BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED (0UL) // At least one GPT channel with A/D conversion start is available. 330 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_STEP_SIZE (2UL) // Multiplicative step size of the clock divider (GTCR.TPCS). 331 #define BSP_FEATURE_GPT_CLOCK_DIVIDER_VALUE_7_9_VALID (0UL) // Whether or not the bit-values of 0b0111 and 0b1001 are valid divider settings (GTCR.TPCS). 332 #define BSP_FEATURE_GPT_EVENT_COUNT_CHANNEL_MASK (0x3FUL) // Mask of channels that support event count input (has GTUPSR register). 333 #define BSP_FEATURE_GPT_EVENT_COUNT_SUPPORTED (1UL) // At least one channel supports event counts. 334 #define BSP_FEATURE_GPT_GPTE_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTE implementation. 335 #define BSP_FEATURE_GPT_GPTE_SUPPORTED (0UL) // At least one GPTE implementation is available. 336 #define BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK (0x00UL) // Mask of GPT channels that are the GPTEH implementation. 337 #define BSP_FEATURE_GPT_GPTEH_SUPPORTED (0UL) // At least one GPTEH implementation is available. 338 #define BSP_FEATURE_GPT_GTDVU_CHANNEL_MASK (0x3FUL) // Mask of channels that support dead time control. 339 #define BSP_FEATURE_GPT_GTDVU_SUPPORTED (1UL) // At least one GPT channel with GTDVU support is available. 340 #define BSP_FEATURE_GPT_ODC_128_RESOLUTION_CHANNEL_MASK (0x00UL) // Mask of PWM channels which support 128-bit delay resolution. 341 #define BSP_FEATURE_GPT_ODC_128_RESOLUTION_SUPPORTED (0UL) // The PWM delay circuit supports 128-bit resolution for delays. 342 #define BSP_FEATURE_GPT_ODC_FRANGE_FREQ_MIN (0UL) // Minimum frequency for standard PDG operation, must set GTCLYCR.FRANGE bit below this value. 343 #define BSP_FEATURE_GPT_ODC_FRANGE_SET_BIT(gpt_frequency) (0UL) // Obtains the set bit based on the GPT frequency and the FRANGE threshold. 344 #define BSP_FEATURE_GPT_ODC_FREQ_MAX (0UL) // Maximum supported frequency of the PWM Delay Generation circuit. 345 #define BSP_FEATURE_GPT_ODC_FREQ_MIN (0UL) // Minimum supported frequency of the PWM Delay Generation circuit. 346 #define BSP_FEATURE_GPT_OPS_CHANNEL_MASK (0x01UL) // Mask of channels supporting output phase switching. 347 #define BSP_FEATURE_GPT_OPS_SUPPORTED (1UL) // At least one GPT channel with OPS support is available. 348 #define BSP_FEATURE_GPT_TPCS_SHIFT (0UL) // Shift value to convert TPCS bit values to real multiplicative values. 349 350 #define BSP_FEATURE_I3C_IS_AVAILABLE (1UL) 351 #define BSP_FEATURE_I3C_HAS_HDR_MODE (1UL) // I3C support high data rate mode. 352 #define BSP_FEATURE_I3C_MAX_DEV_COUNT (4UL) // Maximum number of bus devices. 353 #define BSP_FEATURE_I3C_MSTP_OFFSET (4UL) // Offset of the MSTP bit for the I3C peripherals. 354 #define BSP_FEATURE_I3C_NTDTBP0_DEPTH (2UL) // Depth of the normal transmit data buffer. 355 #define BSP_FEATURE_I3C_NUM_CHANNELS (1UL) // Total number of available channels. 356 357 #define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0UL) // Number of IELSRn registers that have a fixed event source. 358 #define BSP_FEATURE_ICU_HAS_FILTER (1UL) // ICU contains digital input filtering. 359 #define BSP_FEATURE_ICU_HAS_IELSR (1UL) // ICU Event Link is available. 360 #define BSP_FEATURE_ICU_HAS_INTERRUPT_GROUPS (0UL) // Indicates that event links are grouped with multiple sources. 361 #define BSP_FEATURE_ICU_HAS_LOCO_FILTER (1UL) // Register IRQCR has LOCOSEL. 362 #define BSP_FEATURE_ICU_HAS_WUPEN1 (1UL) // WUPEN1 register is available. 363 #define BSP_FEATURE_ICU_HAS_WUPEN2 (1UL) // WUPEN2 register is available. 364 #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFUL) // Mask of available IRQ control registers. 365 #define BSP_FEATURE_ICU_NMIER_MAX_INDEX (15UL) // Maximum bit field index of valid fields of the NMIER register. 366 #define BSP_FEATURE_ICU_SBYEDCR_MASK (0x00ULL) // A mask of valid bits for [SBYEDCR1:SBYEDCR0]. 367 #define BSP_FEATURE_ICU_WUPEN_MASK (0x00000880FB8DFFFFULL) // A mask of valid bits for [WUPEN1:WUPEN0]. 368 369 #define BSP_FEATURE_IIC_IS_AVAILABLE (1UL) 370 #define BSP_FEATURE_IIC_B_CHECK_SCL_STATUS (0UL) // SCL status needs to be checked before writing the transmission data in master mode. 371 #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x01UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. 372 #define BSP_FEATURE_IIC_B_VALID_CHANNEL_MASK (0x01UL) // Mask of available IIC_B or compatible I3C channels. 373 #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5UL) // Multiplication factor to calculate SDA bus free time. 374 #define BSP_FEATURE_IIC_FAST_MODE_PLUS (1UL) // Mask of channels which support "Fast Mode Plus": up to 1 Mbps bit rates. 375 #define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x01UL) // Mask of available IIC channels. 376 377 #define BSP_FEATURE_IOPORT_ELC_PORTS (0x1EUL) // Mask of valid indices for ELC signal mapping of port input data. 378 #define BSP_FEATURE_IOPORT_VERSION (1UL) // Version of the system PFS block. 379 380 #define BSP_FEATURE_IWDT_IS_AVAILABLE (1UL) 381 #define BSP_FEATURE_IWDT_CLOCK_FREQUENCY (15000UL) // Frequency of the independent watchdog clock source. 382 #define BSP_FEATURE_IWDT_SUPPORTS_REGISTER_START_MODE (0UL) // IWDT peripheral supports register start mode. 383 384 #define BSP_FEATURE_KINT_IS_AVAILABLE (0UL) 385 #define BSP_FEATURE_KINT_HAS_MSTP (0UL) // Feature not available on this device. 386 387 #define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {} // An array of tuples (MSTP index, bit) that indicate which modules must enter the stop state before the system enters low power mode or when changes to SCKDIVCR are made. 388 #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0UL) // Indicates some modules must be explicitly stopped before entering low power modes or changing SCKDIVCR. 389 #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00ULL) // Mask of valid bit-fields of the DPSIEGRn registers. 390 #define BSP_FEATURE_LPM_DPSIER_MASK (0x00ULL) // Mask of valid bit-fields of the DPSIERn registers. 391 #define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0UL) // The device supports deep sleep mode. 392 #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0UL) // The device supports deep standby mode. 393 #define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0UL) // The DPSBYCR.DEEPCUT field is available. 394 #define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0UL) // The DPSBYCR.DPSBY field is available. 395 #define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0UL) // The DPSBYCR.SRKEEP field is available. 396 #define BSP_FEATURE_LPM_HAS_DPSIEGR3 (0UL) // The DPSIEGR3 register is available. 397 #define BSP_FEATURE_LPM_HAS_DPSIEGR4 (0UL) // The DPSIEGR4 register is available. 398 #define BSP_FEATURE_LPM_HAS_DPSIER4 (0UL) // The DPSIER4 register is available. 399 #define BSP_FEATURE_LPM_HAS_DPSIER5 (0UL) // The DPSIER5 register is available. 400 #define BSP_FEATURE_LPM_HAS_FLASH_MODE_SELECT (0UL) // The SBYCR.FLSTP field is available. 401 #define BSP_FEATURE_LPM_HAS_HOCO_STARTUP_SPEED_MODE (0UL) // The SBYCR.FWKUP field is available. 402 #define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0UL) // LDOs for clock sources can be enabled/disabled. 403 #define BSP_FEATURE_LPM_HAS_LPSCR (0UL) // The LPSCR register is available. 404 #define BSP_FEATURE_LPM_HAS_PDRAMSCR (0UL) // The PDRAMSCRn registers are available. 405 #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0UL) // The SBYCR.OPE field is available. 406 #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1UL) // The SBYCR.SSBY field is available. 407 #define BSP_FEATURE_LPM_HAS_SNOOZE (1UL) // The MCU supports Snooze. 408 #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1UL) // The SNZEDCR1 register is available. 409 #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0UL) // The SNZREQCR1 register is available. 410 #define BSP_FEATURE_LPM_HAS_STANDBY_SOSC_SELECT (0UL) // The SBYCR.RTCLPC field is available. 411 #define BSP_FEATURE_LPM_HAS_STCONR (0UL) // The STCONR register is available. 412 #define BSP_FEATURE_LPM_RTC_REGISTER_CLOCK_DISABLE (0UL) // RTC registers' clock should be disabled for additional power savings in LPM. 413 #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0UL) // Indicates that bit 14 of the SBYCR register should always be set. 414 #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x029FUL) // Mask of valid bits for the SNZEDCRn registers. 415 #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7380FFFFULL) // Mask of valid bits for the SNZREQCRn registers. 416 #define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0UL) // The Middle-speed On-Chip Oscillator must be operating prior to entering standby mode. 417 #define BSP_FEATURE_LPM_STANDBY_MODE_CLEAR_DTCST (0UL) // DTCST register must be cleared prior to entering standby mode. 418 419 #define BSP_FEATURE_LVD_IS_AVAILABLE (1UL) 420 #define BSP_FEATURE_LVD_EXLVD_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVD pin input. 421 #define BSP_FEATURE_LVD_EXLVDVBAT_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage high threshold. 422 #define BSP_FEATURE_LVD_EXLVDVBAT_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VBAT reference voltage low threshold. 423 #define BSP_FEATURE_LVD_EXLVDVRTC_HI_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage high threshold. 424 #define BSP_FEATURE_LVD_EXLVDVRTC_LOW_THRESHOLD ((lvd_threshold_t) 0U) // External LVD for VRTC reference voltage low threshold. 425 #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0UL) // Digital input filtering is available. 426 #define BSP_FEATURE_LVD_HAS_EXT_MONITOR (0UL) // Voltage monitoring is available for an external power supply via pin. 427 #define BSP_FEATURE_LVD_HAS_LVDLVLR (0UL) // LVDLVLR register is available. 428 #define BSP_FEATURE_LVD_MONITOR_1_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_3_10V) // Typical higher bound of the detection threshold for LVD1. 429 #define BSP_FEATURE_LVD_MONITOR_1_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_1_LEVEL_1_65V) // Typical lower bound of the detection threshold for LVD1. 430 #define BSP_FEATURE_LVD_MONITOR_1_STABILIZATION_TIME_US (300UL) // Maximum stabilization time to wait after LVD1 is enabled. 431 #define BSP_FEATURE_LVD_MONITOR_2_HI_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_3_13V) // Typical higher bound of the detection threshold for LVD2. 432 #define BSP_FEATURE_LVD_MONITOR_2_LOW_THRESHOLD (LVD_THRESHOLD_MONITOR_2_LEVEL_1_67V) // Typical lower bound of the detection threshold for LVD2. 433 #define BSP_FEATURE_LVD_MONITOR_2_STABILIZATION_TIME_US (1200UL) // Maximum stabilization time to wait after LVD2 is enabled. 434 #define BSP_FEATURE_LVD_MONITOR_MASK (0x03UL) // Mask of programmable monitors. 435 #define BSP_FEATURE_LVD_SUPPORT_RESET_ON_RISING_EDGE (0UL) // Voltage monitors support rising edge detections (i.e. 436 #define BSP_FEATURE_LVD_VBAT_STABILIZATION_TIME_US (0UL) // Detection delay time for EXLVDVBAT pin input. 437 #define BSP_FEATURE_LVD_VERSION (1UL) // Version of the LVD peripheral. 438 #define BSP_FEATURE_LVD_VRTC_LVL_STABILIZATION_TIME_US (0UL) // Stabilization wait time after writing to VRTLVDCR.LVL. 439 #define BSP_FEATURE_LVD_VRTC_STABILIZATION_TIME_US (0UL) // Detection delay time for VRTC pin input. 440 441 #define BSP_FEATURE_MACL_SUPPORTED (0UL) // On-chip multiplier and multiply-accumulator is available. 442 443 #define BSP_FEATURE_OPAMP_IS_AVAILABLE (0UL) 444 #define BSP_FEATURE_OPAMP_BASE_ADDRESS (0UL) // Feature not available on this device. 445 #define BSP_FEATURE_OPAMP_HAS_MIDDLE_SPEED (0UL) // Feature not available on this device. 446 #define BSP_FEATURE_OPAMP_HAS_SWITCHES (0UL) // Feature not available on this device. 447 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_HS_US (0UL) // Feature not available on this device. 448 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_LP_US (0UL) // Feature not available on this device. 449 #define BSP_FEATURE_OPAMP_MIN_WAIT_TIME_MS_US (0UL) // Feature not available on this device. 450 #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0UL) // Feature not available on this device. 451 #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0x00UL) // Feature not available on this device. 452 453 #define BSP_FEATURE_OSPI_IS_AVAILABLE (0UL) 454 #define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. 455 #define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. 456 457 #define BSP_FEATURE_OSPI_B_IS_AVAILABLE (0UL) 458 #define BSP_FEATURE_OSPI_B_DEVICE_0_START_ADDRESS (0x00UL) // Feature not available on this device. 459 #define BSP_FEATURE_OSPI_B_DEVICE_1_START_ADDRESS (0x00UL) // Feature not available on this device. 460 461 #define BSP_FEATURE_POEG_CHANNEL_MASK (0x0FUL) // Mask of valid channels for POEG. 462 #define BSP_FEATURE_POEG_HAS_POEGG_DERRST (0UL) // Indicates POEGG.DERRSTn registers are available. 463 464 #define BSP_FEATURE_QSPI_IS_AVAILABLE (1UL) 465 #define BSP_FEATURE_QSPI_DEVICE_START_ADDRESS (0x60000000UL) // Start address of the CS0 memory mapped region for QSPI. 466 467 #define BSP_FEATURE_RSIP_AES_B_SUPPORTED (0UL) // The device supports cryptography using AES_B. 468 #define BSP_FEATURE_RSIP_AES_SUPPORTED (0UL) // The device supports cryptography using AES. 469 #define BSP_FEATURE_RSIP_RSIP_E11A_SUPPORTED (1UL) // The device supports cryptography using RISP_E11A. 470 #define BSP_FEATURE_RSIP_RSIP_E31A_SUPPORTED (0UL) // The device supports cryptography using RISP_E31A. 471 #define BSP_FEATURE_RSIP_RSIP_E50D_SUPPORTED (0UL) // The device supports cryptography using RSIP_E50D. 472 #define BSP_FEATURE_RSIP_RSIP_E51A_SUPPORTED (0UL) // The device supports cryptography using RSIP_E51A. 473 #define BSP_FEATURE_RSIP_SCE5_SUPPORTED (0UL) // The device supports cryptography using SCE5. 474 #define BSP_FEATURE_RSIP_SCE5B_SUPPORTED (0UL) // The device supports cryptography using SCE5B. 475 #define BSP_FEATURE_RSIP_SCE7_SUPPORTED (0UL) // The device supports cryptography using SCE7. 476 #define BSP_FEATURE_RSIP_SCE9_SUPPORTED (0UL) // The device supports cryptography using SCE9. 477 #define BSP_FEATURE_RSIP_TRNG_SUPPORTED (0UL) // The device supports a TRNG module. 478 479 #define BSP_FEATURE_RTC_IS_AVAILABLE (1UL) 480 #define BSP_FEATURE_RTC_HAS_HP_MODE (0UL) // Indicates HP mode is available. 481 #define BSP_FEATURE_RTC_HAS_RADJ_ADJ6 (0UL) // ADJ6 is appended to upper part of RADJ.ADJ[0:5] as ADJ[6]. 482 #define BSP_FEATURE_RTC_HAS_ROPSEL (1UL) // The RCR4.ROPSEL field is available. 483 #define BSP_FEATURE_RTC_HAS_TCEN (1UL) // Timer capture is available. 484 #define BSP_FEATURE_RTC_IS_IRTC (0UL) // RTC has a separate power domain (VRTC) for the sub-clock oscillator and RTC peripheral. 485 #define BSP_FEATURE_RTC_RTCCR_CHANNELS (3UL) // Number of RTCCRn registers that are available. 486 487 #define BSP_FEATURE_SAU_IS_AVAILABLE (0UL) 488 #define BSP_FEATURE_SAU_UART_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. 489 490 #define BSP_FEATURE_SCI_IS_AVAILABLE (1UL) 491 #define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (0x0239UL) // Mask of channels with data compare match (DCCR) available. 492 #define BSP_FEATURE_SCI_CHANNELS (0x023BUL) // Mask of available SCI channels. 493 #define BSP_FEATURE_SCI_CLOCK (FSP_PRIV_CLOCK_PCLKA) // Clock source routed to the SCI peripherals. 494 #define BSP_FEATURE_SCI_IRDA_CHANNEL_MASK (0x20UL) // Mask of channels that support IrDA. 495 #define BSP_FEATURE_SCI_IRDA_SUPPORTED (1UL) // Indicates IrDA is supported on at least one SCI channel. 496 #define BSP_FEATURE_SCI_LIN_CHANNELS (0x02UL) // Mask of channels that can support LIN. 497 #define BSP_FEATURE_SCI_SPI_SCKSEL_VALUE (0UL) // Mask indicating CCR4.SCKSEL is available. 498 #define BSP_FEATURE_SCI_UART_ABCSE_RESTRICTED_CHANNELS (0x02UL) // List of channels that do not support ABCSE functionality. 499 #define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x0239UL) // Mask of channels which support CTS external pins. 500 #define BSP_FEATURE_SCI_UART_DE_IS_INVERTED (0UL) // Indicates the PSEL value used to enable `DEn` output signal is opposite compared to other MCUs. 501 #define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x0239UL) // Mask of channels which support the UART FIFO. 502 #define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16UL) // Depth of the UART FIFO if available. 503 #define BSP_FEATURE_SCI_VERSION (1UL) // Version of the SCI peripheral. 504 505 #define BSP_FEATURE_SDHI_IS_AVAILABLE (0UL) 506 #define BSP_FEATURE_SDHI_CLOCK (0UL) // Feature not available on this device. 507 #define BSP_FEATURE_SDHI_HAS_CARD_DETECTION (0UL) // Feature not available on this device. 508 #define BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT (0UL) // Feature not available on this device. 509 #define BSP_FEATURE_SDHI_SUPPORTS_8_BIT_MMC (0UL) // Feature not available on this device. 510 #define BSP_FEATURE_SDHI_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. 511 512 #define BSP_FEATURE_SDRAM_START_ADDRESS (0x00UL) // Start address of the external address space for SDRAM memory. 513 514 #define BSP_FEATURE_SLCDC_IS_AVAILABLE (1UL) 515 #define BSP_FEATURE_SLCDC_CONTRAST_MAX (22UL) // Maximum contrast index for standard bias methods. 516 #define BSP_FEATURE_SLCDC_CONTRAST_MAX_4BIAS (9UL) // Maximum contrast index for 1/4 bias method. 517 #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (1UL) // LCD waveform supports 8-time slices. 518 #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (1UL) // Internal voltage generation is available. 519 #define BSP_FEATURE_SLCDC_HAS_VL1SEL (1UL) // Internal voltage generator can be used as the LCD reference voltage. 520 #define BSP_FEATURE_SLCDC_HAS_VLCD_MDSET2 (1UL) // VLCD register has MDSET2. 521 #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (51UL) // Maximum index of supported segment registers. 522 523 #define BSP_FEATURE_SPI_IS_AVAILABLE (1UL) 524 #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) // Clock source for SPI peripherals. 525 #define BSP_FEATURE_SPI_HAS_SPCR3 (1UL) // SPCR3 register is available. 526 #define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1UL) // SPCMDn.SSLKP field is available. 527 #define BSP_FEATURE_SPI_MAX_CHANNEL (1UL) // Number of available SPI channels. 528 #define BSP_FEATURE_SPI_SSL_LEVEL_KEEP_VALID_CHANNEL_MASK (0x01UL) // Mask of channel indices that support SSL Level Keep. 529 530 #define BSP_FEATURE_SRAM_SRAMWTSC_WAIT_CYCLE_ENABLE (0x00UL) // Mask of bits needed to enable SRAM wait for all regions. 531 532 #define BSP_FEATURE_SSI_IS_AVAILABLE (1UL) 533 #define BSP_FEATURE_SSI_FIFO_NUM_STAGES (32UL) // Depth of the SSI data FIFO. 534 #define BSP_FEATURE_SSI_VALID_CHANNEL_MASK (1UL) // Mask of valid SSI channel indices. 535 536 #define BSP_FEATURE_SYSC_HAS_VBTICTLR (0UL) // System supports VBATT input control to the RTC. 537 538 #define BSP_FEATURE_TAU_IS_AVAILABLE (0UL) 539 #define BSP_FEATURE_TAU_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. 540 541 #define BSP_FEATURE_TFU_IS_AVAILABLE (0UL) 542 #define BSP_FEATURE_TFU_SUPPORTED (0UL) // Feature not available on this device. 543 544 #define BSP_FEATURE_TML_IS_AVAILABLE (0UL) 545 #define BSP_FEATURE_TML_MAX_CLOCK_DIVIDER (0UL) // Feature not available on this device. 546 #define BSP_FEATURE_TML_NUM_CHANNELS (0UL) // Feature not available on this device. 547 #define BSP_FEATURE_TML_VALID_CHANNEL_MASK (0x00UL) // Feature not available on this device. 548 549 #define BSP_FEATURE_TRNG_HAS_MODULE_STOP (0UL) // A module stop control is available for TRNG. 550 551 #define BSP_FEATURE_TZ_IS_AVAILABLE (1UL) 552 #define BSP_FEATURE_TZ_HAS_DLM (1UL) // Device Lifecycle Management Monitor (DLMMON) register is available. 553 #define BSP_FEATURE_TZ_HAS_TRUSTZONE (1UL) // The device supports Arm TrustZone. 554 #define BSP_FEATURE_TZ_NS_OFFSET (0x00UL) // Offset for the Non-secure address space of a peripheral. 555 #define BSP_FEATURE_TZ_VERSION (1UL) // Version of the TrustZone implementation. 556 557 #define BSP_FEATURE_UARTA_IS_AVAILABLE (1UL) 558 #define BSP_FEATURE_UARTA_HAS_CLOCK_OUTPUT (1UL) // CLKAn can be output from the device. 559 #define BSP_FEATURE_UARTA_MSTP_OFFSET (0UL) // Offset for the UARTA MSTP bit. 560 #define BSP_FEATURE_UARTA_PCLK_RESTRICTION (1UL) // The peripheral clock for UARTA must be >= the UARTn operating clock. 561 562 #define BSP_FEATURE_ULPT_IS_AVAILABLE (0UL) 563 #define BSP_FEATURE_ULPT_MAX_CHANNEL_NUM (0UL) // Feature not available on this device. 564 #define BSP_FEATURE_ULPT_VALID_CHANNEL_MASK (0UL) // Feature not available on this device. 565 566 #define BSP_FEATURE_USB_IS_AVAILABLE (1UL) 567 #define BSP_FEATURE_USB_HAS_NOT_HOST (0UL) // Indicates that USB Host mode is not available. 568 #define BSP_FEATURE_USB_HAS_PIPE04567 (0UL) // USB peripheral only has pipes 0, 4, 5, 6, and 7. 569 #define BSP_FEATURE_USB_HAS_TYPEC (0UL) // Supports USB-C control specifications. 570 #define BSP_FEATURE_USB_HAS_USBFS (1UL) // Supports USB 2.0 Full-Speed mode. 571 #define BSP_FEATURE_USB_HAS_USBFS_BC (0UL) // Supports battery charging in full-speed mode. 572 #define BSP_FEATURE_USB_HAS_USBHS (0UL) // Supports USB 2.0 High-Speed mode. 573 #define BSP_FEATURE_USB_HAS_USBHS_BC (0UL) // Supports battery charging in high-speed mode. 574 #define BSP_FEATURE_USB_HAS_USBLS_PERI (0UL) // Supports low-speed connections in device controller mode. 575 #define BSP_FEATURE_USB_REG_PHYSECTRL_CNEN (0UL) // Indicates the PHYSECTRL.CNEN field is available. 576 #define BSP_FEATURE_USB_REG_PHYSLEW (0UL) // Indicates the PHYSLEW register is available. 577 #define BSP_FEATURE_USB_REG_PHYSLEW_VALUE (0x00UL) // Reset value of the PHYSLEW register. 578 #define BSP_FEATURE_USB_REG_UCKSEL_UCKSELC (1UL) // Indicates the UCKSEL.UCKSELC bit field is available. 579 #define BSP_FEATURE_USB_REG_USBMC_VDCEN (0UL) // Indicates the USBMC.VDCEN bit field is available. 580 #define BSP_FEATURE_USB_REG_USBMC_VDDUSBE (0UL) // Indicates the USBMC.VDDUSBE bit field is available. 581 582 // *UNCRUSTIFY-ON* 583 584 #endif 585
