Searched refs:BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 (Results 1 – 3 of 3) sorted by relevance
449 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) in bsp_prv_clock_selector_set()511 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) in bsp_prv_clock_selector_set()576 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) in bsp_prv_clock_selector_set()638 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) in bsp_prv_clock_selector_set()731 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) in bsp_prv_clock_divider_set()781 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) in bsp_prv_clock_divider_set()831 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) in bsp_prv_clock_divider_set()881 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) in bsp_prv_clock_divider_set()
436 #define BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 (0) // Select 400MHz macro
46 #define BSP_CFG_SELSPI_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400) …