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Searched refs:BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 (Results 1 – 3 of 3) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/mcu/all/
Dbsp_clocks.c449 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) in bsp_prv_clock_selector_set()
511 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) in bsp_prv_clock_selector_set()
576 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) in bsp_prv_clock_selector_set()
638 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel) in bsp_prv_clock_selector_set()
731 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) in bsp_prv_clock_divider_set()
781 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) in bsp_prv_clock_divider_set()
831 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) in bsp_prv_clock_divider_set()
881 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source) in bsp_prv_clock_divider_set()
Dbsp_clocks.h436 #define BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 (0) // Select 400MHz macro
/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/
Dbsp_clock_cfg.h46 #define BSP_CFG_SELSPI_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400) …