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Searched refs:BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 (Results 1 – 3 of 3) sorted by relevance

/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/mcu/all/
Dbsp_clocks.c453 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel) in bsp_prv_clock_selector_set()
515 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel) in bsp_prv_clock_selector_set()
580 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel) in bsp_prv_clock_selector_set()
642 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel) in bsp_prv_clock_selector_set()
735 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source) in bsp_prv_clock_divider_set()
785 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source) in bsp_prv_clock_divider_set()
835 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source) in bsp_prv_clock_divider_set()
885 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source) in bsp_prv_clock_divider_set()
Dbsp_clocks.h437 #define BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 (2) // Select 266MHz macro
/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/
Dbsp_clock_cfg.h42 #define BSP_CFG_SELOCTA_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266) …