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Searched refs:BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 (Results 1 – 3 of 3) sorted by relevance

/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/
Dbsp_clock_cfg.h23 #define BSP_CFG_SEL_SDHI0_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266) …
26 #define BSP_CFG_SEL_SDHI1_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266) …
29 #define BSP_CFG_SEL_SDHI2_SET_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266) …
/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/mcu/all/
Dbsp_clocks.c326 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel) in bsp_prv_clock_selector_set()
365 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel) in bsp_prv_clock_selector_set()
404 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel) in bsp_prv_clock_selector_set()
Dbsp_clocks.h433 #define BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 (3) // Select 266MHz macro