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Searched refs:BSP_CLOCKS_PL3B_DIV_1 (Results 1 – 2 of 2) sorted by relevance

/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/
Dbsp_clock_cfg.h36 #define BSP_CFG_DIVPL3B_SET_DIV (BSP_CLOCKS_PL3B_DIV_1) …
/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/mcu/all/
Dbsp_clocks.h373 #define BSP_CLOCKS_PL3B_DIV_1 (0) // Divide P1CLK source clock by 1 macro