Searched refs:BSP_CLOCKS_PL3A_DIV_1 (Results 1 – 2 of 2) sorted by relevance
34 #define BSP_CFG_DIVPL3A_SET_DIV (BSP_CLOCKS_PL3A_DIV_1) …
380 #define BSP_CLOCKS_PL3A_DIV_1 (0) // Divide P2CLK source clock by 1 macro
