1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BSP_CLOCKS_H 8 #define BSP_CLOCKS_H 9 10 /*********************************************************************************************************************** 11 * Includes 12 **********************************************************************************************************************/ 13 #include "bsp_clock_cfg.h" 14 #include "bsp_api.h" 15 16 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 17 FSP_HEADER 18 19 /*********************************************************************************************************************** 20 * Macro definitions 21 **********************************************************************************************************************/ 22 23 /*********************************************************************************************************************** 24 * Start clock supply 25 * 26 * @param ip fsp_ip_t enum value for the unit to which the clock is supplied. 27 * @param channel The channel. Use ch 0 for units without channels. Only single bit can be set. 28 **********************************************************************************************************************/ 29 #define R_BSP_MODULE_CLKON(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 30 FSP_CRITICAL_SECTION_ENTER; \ 31 BSP_CLKON_REG_ ## ip(channel) = 0x00000000U \ 32 | (BSP_CLKON_BIT_ ## ip(channel) << \ 33 16U) \ 34 | (BSP_CLKON_BIT_ ## ip(channel)); \ 35 while ((BSP_CLKMON_REG_ ## ip(channel) & \ 36 BSP_CLKMON_BIT_ ## ip(channel)) == 0U) \ 37 { /* wait */}; \ 38 FSP_CRITICAL_SECTION_EXIT;} 39 40 /*********************************************************************************************************************** 41 * Stop clock supply 42 * 43 * @param ip fsp_ip_t enum value for the unit to stop clock. 44 * @param channel The channel. Use ch 0 for units without channels. Only single bit can be set. 45 **********************************************************************************************************************/ 46 #define R_BSP_MODULE_CLKOFF(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 47 FSP_CRITICAL_SECTION_ENTER; \ 48 BSP_CLKON_REG_ ## ip(channel) = 0x00000000U \ 49 | (BSP_CLKON_BIT_ ## ip(channel) << \ 50 16U); \ 51 while ((BSP_CLKMON_REG_ ## ip(channel) & \ 52 BSP_CLKMON_BIT_ ## ip(channel)) != 0U) \ 53 { /* wait */}; \ 54 FSP_CRITICAL_SECTION_EXIT;} 55 56 /*********************************************************************************************************************** 57 * Reset assertion 58 * 59 * @param ip fsp_ip_t enum value for the unit to be reset. 60 * @param channel The channel. Use ch 0 for units without channels. Only single bit can be set. 61 **********************************************************************************************************************/ 62 #define R_BSP_MODULE_RSTON(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 63 FSP_CRITICAL_SECTION_ENTER; \ 64 BSP_RST_REG_ ## ip(channel) = 0x00000000U \ 65 | (BSP_RST_BIT_ ## ip(channel) << 16U); \ 66 FSP_CRITICAL_SECTION_EXIT;} 67 68 /*********************************************************************************************************************** 69 * Reset deassertion 70 * 71 * @param ip fsp_ip_t enum value for the unit to release from reset state. 72 * @param channel The channel. Use ch 0 for units without channels. Only single bit can be set. 73 **********************************************************************************************************************/ 74 #define R_BSP_MODULE_RSTOFF(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ 75 FSP_CRITICAL_SECTION_ENTER; \ 76 BSP_RST_REG_ ## ip(channel) = 0x00000000U \ 77 | (BSP_RST_BIT_ ## ip(channel) << 16U) \ 78 | (BSP_RST_BIT_ ## ip(channel)); \ 79 while ((BSP_RSTMON_REG_ ## ip(channel) & \ 80 BSP_RSTMON_BIT_ ## ip(channel)) != 0U) \ 81 { /* wait */}; \ 82 FSP_CRITICAL_SECTION_EXIT;} 83 84 /*********************************************************************************************************************** 85 * Definition of macros to control GTM clock ON/OFF and reset ON/OFF 86 **********************************************************************************************************************/ 87 #ifndef BSP_CLKON_REG_FSP_IP_GTM 88 #define BSP_CLKON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_CLKON_GTM) 89 #endif 90 #ifndef BSP_CLKON_BIT_FSP_IP_GTM 91 #define BSP_CLKON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_CLKON_GTM_CLK0_ON_Pos + (channel))) 92 #endif 93 94 #ifndef BSP_CLKMON_REG_FSP_IP_GTM 95 #define BSP_CLKMON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_CLKMON_GTM) 96 #endif 97 #ifndef BSP_CLKMON_BIT_FSP_IP_GTM 98 #define BSP_CLKMON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_CLKMON_GTM_CLK0_MON_Pos + (channel))) 99 #endif 100 101 #ifndef BSP_RST_REG_FSP_IP_GTM 102 #define BSP_RST_REG_FSP_IP_GTM(channel) (R_CPG->CPG_RST_GTM) 103 #endif 104 #ifndef BSP_RST_BIT_FSP_IP_GTM 105 #define BSP_RST_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_RST_GTM_UNIT0_RSTB_Pos + (channel))) 106 #endif 107 108 #ifndef BSP_RSTMON_REG_FSP_IP_GTM 109 #define BSP_RSTMON_REG_FSP_IP_GTM(channel) (R_CPG->CPG_RSTMON_GTM) 110 #endif 111 #ifndef BSP_RSTMON_BIT_FSP_IP_GTM 112 #define BSP_RSTMON_BIT_FSP_IP_GTM(channel) (1U << (R_CPG_CPG_RSTMON_GTM_RST0_MON_Pos + (channel))) 113 #endif 114 115 /*********************************************************************************************************************** 116 * Definition of macros to control GPT clock ON/OFF and reset ON/OFF 117 **********************************************************************************************************************/ 118 #define BSP_CLKON_REG_FSP_IP_GPT(channel) (R_CPG->CPG_CLKON_GPT) 119 #define BSP_CLKON_BIT_FSP_IP_GPT(channel) (1U << (R_CPG_CPG_CLKON_GPT_CLK0_ON_Pos)) 120 121 #define BSP_CLKMON_REG_FSP_IP_GPT(channel) (R_CPG->CPG_CLKMON_GPT) 122 #define BSP_CLKMON_BIT_FSP_IP_GPT(channel) (1U << (R_CPG_CPG_CLKMON_GPT_CLK0_MON_Pos)) 123 124 #define BSP_RST_REG_FSP_IP_GPT(channel) (R_CPG->CPG_RST_GPT) 125 #define BSP_RST_BIT_FSP_IP_GPT(channel) (1U << (R_CPG_CPG_RST_GPT_UNIT0_RSTB_Pos)) 126 127 #define BSP_RSTMON_REG_FSP_IP_GPT(channel) (R_CPG->CPG_RSTMON_GPT) 128 #define BSP_RSTMON_BIT_FSP_IP_GPT(channel) (1U << (R_CPG_CPG_RSTMON_GPT_RST0_MON_Pos)) 129 130 /*********************************************************************************************************************** 131 * Definition of macros to control POEG clock ON/OFF and reset ON/OFF 132 **********************************************************************************************************************/ 133 #define BSP_CLKON_REG_FSP_IP_POEG(channel) (R_CPG->CPG_CLKON_POEG) 134 #define BSP_CLKON_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_CLKON_POEG_CLK0_ON_Pos + (channel))) 135 136 #define BSP_CLKMON_REG_FSP_IP_POEG(channel) (R_CPG->CPG_CLKMON_POEG) 137 #define BSP_CLKMON_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_CLKMON_POEG_CLK0_MON_Pos + (channel))) 138 139 #define BSP_RST_REG_FSP_IP_POEG(channel) (R_CPG->CPG_RST_POEG) 140 #define BSP_RST_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_RST_POEG_UNIT0_RSTB_Pos + (channel))) 141 142 #define BSP_RSTMON_REG_FSP_IP_POEG(channel) (R_CPG->CPG_RSTMON_POEG) 143 #define BSP_RSTMON_BIT_FSP_IP_POEG(channel) (1U << (R_CPG_CPG_RSTMON_POEG_RST0_MON_Pos + (channel))) 144 145 /*********************************************************************************************************************** 146 * Definition of macros to control IM33 clock ON/OFF and reset ON/OFF 147 **********************************************************************************************************************/ 148 #define BSP_CLKON_REG_FSP_IP_IM33(channel) (R_CPG->CPG_CLKON_IM33) 149 #define BSP_CLKON_BIT_FSP_IP_IM33(channel) (1U << (R_CPG_CPG_CLKON_IM33_CLK0_ON_Pos + (channel))) 150 151 #define BSP_CLKMON_REG_FSP_IP_IM33(channel) (R_CPG->CPG_CLKMON_IM33) 152 #define BSP_CLKMON_BIT_FSP_IP_IM33(channel) (1U << (R_CPG_CPG_CLKMON_IM33_CLK0_MON_Pos + (channel))) 153 154 #define BSP_RST_REG_FSP_IP_IM33(channel) (R_CPG->CPG_RST_IM33) 155 #define BSP_RST_BIT_FSP_IP_IM33(channel) (1U << (R_CPG_CPG_RST_IM33_UNIT0_RSTB_Pos + (channel))) 156 157 #define BSP_RSTMON_REG_FSP_IP_IM33(channel) (R_CPG->CPG_RSTMON_IM33) 158 #define BSP_RSTMON_BIT_FSP_IP_IM33(channel) (1U << (R_CPG_CPG_RSTMON_IM33_RST0_MON_Pos + (channel))) 159 160 /*********************************************************************************************************************** 161 * Definition of macros to control SCIF clock ON/OFF and reset ON/OFF 162 **********************************************************************************************************************/ 163 #define BSP_CLKON_REG_FSP_IP_SCIF(channel) (R_CPG->CPG_CLKON_SCIF) 164 #define BSP_CLKON_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_CLKON_SCIF_CLK0_ON_Pos + (channel))) 165 166 #define BSP_CLKMON_REG_FSP_IP_SCIF(channel) (R_CPG->CPG_CLKMON_SCIF) 167 #define BSP_CLKMON_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_CLKMON_SCIF_CLK0_MON_Pos + (channel))) 168 169 #define BSP_RST_REG_FSP_IP_SCIF(channel) (R_CPG->CPG_RST_SCIF) 170 #define BSP_RST_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_RST_SCIF_UNIT0_RSTB_Pos + (channel))) 171 172 #define BSP_RSTMON_REG_FSP_IP_SCIF(channel) (R_CPG->CPG_RSTMON_SCIF) 173 #define BSP_RSTMON_BIT_FSP_IP_SCIF(channel) (1U << (R_CPG_CPG_RSTMON_SCIF_RST0_MON_Pos + (channel))) 174 175 /*********************************************************************************************************************** 176 * Definition of macros to control RIIC clock ON/OFF and reset ON/OFF 177 **********************************************************************************************************************/ 178 #define BSP_CLKON_REG_FSP_IP_RIIC(channel) (R_CPG->CPG_CLKON_I2C) 179 #define BSP_CLKON_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_CLKON_I2C_CLK0_ON_Pos + (channel))) 180 181 #define BSP_CLKMON_REG_FSP_IP_RIIC(channel) (R_CPG->CPG_CLKMON_I2C) 182 #define BSP_CLKMON_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_CLKMON_I2C_CLK0_MON_Pos + (channel))) 183 184 #define BSP_RST_REG_FSP_IP_RIIC(channel) (R_CPG->CPG_RST_I2C) 185 #define BSP_RST_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_RST_I2C_UNIT0_RSTB_Pos + (channel))) 186 187 #define BSP_RSTMON_REG_FSP_IP_RIIC(channel) (R_CPG->CPG_RSTMON_I2C) 188 #define BSP_RSTMON_BIT_FSP_IP_RIIC(channel) (1U << (R_CPG_CPG_RSTMON_I2C_RST0_MON_Pos + (channel))) 189 190 /*********************************************************************************************************************** 191 * Definition of macros to control RSPI clock ON/OFF and reset ON/OFF 192 **********************************************************************************************************************/ 193 #define BSP_CLKON_REG_FSP_IP_RSPI(channel) (R_CPG->CPG_CLKON_RSPI) 194 #define BSP_CLKON_BIT_FSP_IP_RSPI(channel) (1U << (R_CPG_CPG_CLKON_RSPI_CLK0_ON_Pos + (channel))) 195 196 #define BSP_CLKMON_REG_FSP_IP_RSPI(channel) (R_CPG->CPG_CLKMON_RSPI) 197 #define BSP_CLKMON_BIT_FSP_IP_RSPI(channel) (1U << (R_CPG_CPG_CLKMON_RSPI_CLK0_MON_Pos + (channel))) 198 199 #define BSP_RST_REG_FSP_IP_RSPI(channel) (R_CPG->CPG_RST_RSPI) 200 #define BSP_RST_BIT_FSP_IP_RSPI(channel) (1U << (R_CPG_CPG_RST_RSPI_UNIT0_RSTB_Pos + (channel))) 201 202 #define BSP_RSTMON_REG_FSP_IP_RSPI(channel) (R_CPG->CPG_RSTMON_RSPI) 203 #define BSP_RSTMON_BIT_FSP_IP_RSPI(channel) (1U << (R_CPG_CPG_RSTMON_RSPI_RST0_MON_Pos + (channel))) 204 205 /*********************************************************************************************************************** 206 * Definition of macros to control MHU clock ON/OFF and reset ON/OFF 207 **********************************************************************************************************************/ 208 #define BSP_CLKON_REG_FSP_IP_MHU(channel) (R_CPG->CPG_CLKON_MHU) 209 #define BSP_CLKON_BIT_FSP_IP_MHU(channel) (1U << (R_CPG_CPG_CLKON_MHU_CLK0_ON_Pos)) 210 211 #define BSP_CLKMON_REG_FSP_IP_MHU(channel) (R_CPG->CPG_CLKMON_MHU) 212 #define BSP_CLKMON_BIT_FSP_IP_MHU(channel) (1U << (R_CPG_CPG_CLKMON_MHU_CLK0_MON_Pos)) 213 214 #define BSP_RST_REG_FSP_IP_MHU(channel) (R_CPG->CPG_RST_MHU) 215 #define BSP_RST_BIT_FSP_IP_MHU(channel) (1U << (R_CPG_CPG_RST_MHU_UNIT0_RSTB_Pos)) 216 217 #define BSP_RSTMON_REG_FSP_IP_MHU(channel) (R_CPG->CPG_RSTMON_MHU) 218 #define BSP_RSTMON_BIT_FSP_IP_MHU(channel) (1U << (R_CPG_CPG_RSTMON_MHU_RST0_MON_Pos)) 219 220 /*********************************************************************************************************************** 221 * Definition of macros to control DMAC clock ON/OFF and reset ON/OFF 222 **********************************************************************************************************************/ 223 #define BSP_CLKON_REG_FSP_IP_DMAC(channel) (R_CPG->CPG_CLKON_DMAC_REG) 224 #define BSP_CLKON_BIT_FSP_IP_DMAC(channel) (3U << (R_CPG_CPG_CLKON_DMAC_REG_CLK0_ON_Pos)) 225 226 #define BSP_CLKMON_REG_FSP_IP_DMAC(channel) (R_CPG->CPG_CLKMON_DMAC_REG) 227 #define BSP_CLKMON_BIT_FSP_IP_DMAC(channel) (3U << (R_CPG_CPG_CLKMON_DMAC_REG_CLK0_MON_Pos)) 228 229 #define BSP_RST_REG_FSP_IP_DMAC(channel) (R_CPG->CPG_RST_DMAC) 230 #define BSP_RST_BIT_FSP_IP_DMAC(channel) (3U << (R_CPG_CPG_RST_DMAC_UNIT0_RSTB_Pos)) 231 232 #define BSP_RSTMON_REG_FSP_IP_DMAC(channel) (R_CPG->CPG_RSTMON_DMAC) 233 #define BSP_RSTMON_BIT_FSP_IP_DMAC(channel) (3U << (R_CPG_CPG_RSTMON_DMAC_RST0_MON_Pos)) 234 235 #define BSP_CLKON_REG_FSP_IP_DMAC_s(channel) BSP_CLKON_REG_FSP_IP_DMAC(channel) 236 #define BSP_CLKON_BIT_FSP_IP_DMAC_s(channel) BSP_CLKON_BIT_FSP_IP_DMAC(channel) 237 238 #define BSP_CLKMON_REG_FSP_IP_DMAC_s(channel) BSP_CLKMON_REG_FSP_IP_DMAC(channel) 239 #define BSP_CLKMON_BIT_FSP_IP_DMAC_s(channel) BSP_CLKMON_BIT_FSP_IP_DMAC(channel) 240 241 #define BSP_RST_REG_FSP_IP_DMAC_s(channel) BSP_RST_REG_FSP_IP_DMAC(channel) 242 #define BSP_RST_BIT_FSP_IP_DMAC_s(channel) BSP_RST_BIT_FSP_IP_DMAC(channel) 243 244 #define BSP_RSTMON_REG_FSP_IP_DMAC_s(channel) BSP_RSTMON_REG_FSP_IP_DMAC(channel) 245 #define BSP_RSTMON_BIT_FSP_IP_DMAC_s(channel) BSP_RSTMON_BIT_FSP_IP_DMAC(channel) 246 247 /*********************************************************************************************************************** 248 * Definition of macros to control SSI clock ON/OFF and reset ON/OFF 249 **********************************************************************************************************************/ 250 #define BSP_CLKON_REG_FSP_IP_SSI(channel) (R_CPG->CPG_CLKON_SSI) 251 #define BSP_CLKON_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_CLKON_SSI_CLK0_ON_Pos + (channel))) 252 253 #define BSP_CLKMON_REG_FSP_IP_SSI(channel) (R_CPG->CPG_CLKMON_SSI) 254 #define BSP_CLKMON_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_CLKMON_SSI_CLK0_MON_Pos + (channel))) 255 256 #define BSP_RST_REG_FSP_IP_SSI(channel) (R_CPG->CPG_RST_SSIF) 257 #define BSP_RST_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_RST_SSIF_UNIT0_RSTB_Pos + (channel))) 258 259 #define BSP_RSTMON_REG_FSP_IP_SSI(channel) (R_CPG->CPG_RSTMON_SSIF) 260 #define BSP_RSTMON_BIT_FSP_IP_SSI(channel) (1U << (R_CPG_CPG_RSTMON_SSIF_RST0_MON_Pos + (channel))) 261 262 /*********************************************************************************************************************** 263 * Definition of macros to control CANFD clock ON/OFF and reset ON/OFF 264 **********************************************************************************************************************/ 265 #define BSP_CLKON_REG_FSP_IP_CANFD(channel) (R_CPG->CPG_CLKON_CANFD) 266 #define BSP_CLKON_BIT_FSP_IP_CANFD(channel) (1U << (R_CPG_CPG_CLKON_CANFD_CLK0_ON_Pos + (channel))) 267 268 #define BSP_CLKMON_REG_FSP_IP_CANFD(channel) (R_CPG->CPG_CLKMON_CANFD) 269 #define BSP_CLKMON_BIT_FSP_IP_CANFD(channel) (1U << (R_CPG_CPG_CLKMON_CANFD_CLK0_MON_Pos + (channel))) 270 271 #define BSP_RST_REG_FSP_IP_CANFD(channel) (R_CPG->CPG_RST_CANFD) 272 #define BSP_RST_BIT_FSP_IP_CANFD(channel) (1U << (R_CPG_CPG_RST_CANFD_UNIT0_RSTB_Pos + (channel))) 273 274 #define BSP_RSTMON_REG_FSP_IP_CANFD(channel) (R_CPG->CPG_RSTMON_CANFD) 275 #define BSP_RSTMON_BIT_FSP_IP_CANFD(channel) (1U << (R_CPG_CPG_RSTMON_CANFD_RST0_MON_Pos + (channel))) 276 277 /*********************************************************************************************************************** 278 * Definition of macros to control ADC clock ON/OFF and reset ON/OFF 279 **********************************************************************************************************************/ 280 #define BSP_CLKON_REG_FSP_IP_ADC(channel) (R_CPG->CPG_CLKON_ADC) 281 #define BSP_CLKON_BIT_FSP_IP_ADC(channel) (3U << R_CPG_CPG_CLKON_ADC_CLK0_ON_Pos) 282 283 #define BSP_CLKMON_REG_FSP_IP_ADC(channel) (R_CPG->CPG_CLKMON_ADC) 284 #define BSP_CLKMON_BIT_FSP_IP_ADC(channel) (3U << R_CPG_CPG_CLKMON_ADC_CLK0_MON_Pos) 285 286 #define BSP_RST_REG_FSP_IP_ADC(channel) (R_CPG->CPG_RST_ADC) 287 #define BSP_RST_BIT_FSP_IP_ADC(channel) (3U << R_CPG_CPG_RST_ADC_UNIT0_RSTB_Pos) 288 289 #define BSP_RSTMON_REG_FSP_IP_ADC(channel) (R_CPG->CPG_RSTMON_ADC) 290 #define BSP_RSTMON_BIT_FSP_IP_ADC(channel) (3U << R_CPG_CPG_RSTMON_ADC_RST0_MON_Pos) 291 292 /*********************************************************************************************************************** 293 * Definition of macros to control TSU clock ON/OFF and reset ON/OFF 294 **********************************************************************************************************************/ 295 #define BSP_CLKON_REG_FSP_IP_TSU(channel) (R_CPG->CPG_CLKON_TSU) 296 #define BSP_CLKON_BIT_FSP_IP_TSU(channel) (1U << (R_CPG_CPG_CLKON_TSU_CLK0_ON_Pos + (channel))) 297 298 #define BSP_CLKMON_REG_FSP_IP_TSU(channel) (R_CPG->CPG_CLKMON_TSU) 299 #define BSP_CLKMON_BIT_FSP_IP_TSU(channel) (1U << (R_CPG_CPG_CLKMON_TSU_CLK0_MON_Pos + (channel))) 300 301 #define BSP_RST_REG_FSP_IP_TSU(channel) (R_CPG->CPG_RST_TSU) 302 #define BSP_RST_BIT_FSP_IP_TSU(channel) (1U << (R_CPG_CPG_RST_TSU_UNIT0_RSTB_Pos + (channel))) 303 304 #define BSP_RSTMON_REG_FSP_IP_TSU(channel) (R_CPG->CPG_RSTMON_TSU) 305 #define BSP_RSTMON_BIT_FSP_IP_TSU(channel) (1U << (R_CPG_CPG_RSTMON_TSU_RST0_MON_Pos + (channel))) 306 307 /*********************************************************************************************************************** 308 * Definition of macros to control WDT clock ON/OFF and reset ON/OFF 309 **********************************************************************************************************************/ 310 #define BSP_CLKON_REG_FSP_IP_WDT(channel) (R_CPG->CPG_CLKON_WDT) 311 #define BSP_CLKON_BIT_FSP_IP_WDT(channel) (3U << (R_CPG_CPG_CLKON_WDT_CLK0_ON_Pos + 2U * (channel))) 312 313 #define BSP_CLKMON_REG_FSP_IP_WDT(channel) (R_CPG->CPG_CLKMON_WDT) 314 #define BSP_CLKMON_BIT_FSP_IP_WDT(channel) (3U << (R_CPG_CPG_CLKMON_WDT_CLK0_MON_Pos + 2U * (channel))) 315 316 #define BSP_RST_REG_FSP_IP_WDT(channel) (R_CPG->CPG_RST_WDT) 317 #define BSP_RST_BIT_FSP_IP_WDT(channel) (1U << (R_CPG_CPG_RST_WDT_UNIT0_RSTB_Pos + (channel))) 318 319 #define BSP_RSTMON_REG_FSP_IP_WDT(channel) (R_CPG->CPG_RSTMON_WDT) 320 #define BSP_RSTMON_BIT_FSP_IP_WDT(channel) (1U << (R_CPG_CPG_RSTMON_WDT_RST0_MON_Pos + (channel))) 321 322 /*********************************************************************************************************************** 323 * Definition of macros to control SCI clock ON/OFF and reset ON/OFF 324 **********************************************************************************************************************/ 325 #define BSP_CLKON_REG_FSP_IP_SCI(channel) (R_CPG->CPG_CLKON_SCI) 326 #define BSP_CLKON_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_CLKON_SCI_CLK0_ON_Pos + (channel))) 327 328 #define BSP_CLKMON_REG_FSP_IP_SCI(channel) (R_CPG->CPG_CLKMON_SCI) 329 #define BSP_CLKMON_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_CLKMON_SCI_CLK0_MON_Pos + (channel))) 330 331 #define BSP_RST_REG_FSP_IP_SCI(channel) (R_CPG->CPG_RST_SCI) 332 #define BSP_RST_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_RST_SCI_UNIT0_RSTB_Pos + (channel))) 333 334 #define BSP_RSTMON_REG_FSP_IP_SCI(channel) (R_CPG->CPG_RSTMON_SCI) 335 #define BSP_RSTMON_BIT_FSP_IP_SCI(channel) (1U << (R_CPG_CPG_RSTMON_SCI_RST0_MON_Pos + (channel))) 336 337 /*********************************************************************************************************************** 338 * Definition of macros to control TSU clock ON/OFF and reset ON/OFF 339 **********************************************************************************************************************/ 340 #define BSP_CLKON_REG_FSP_IP_MTU3(channel) (R_CPG->CPG_CLKON_MTU) 341 #define BSP_CLKON_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_CLKON_MTU_CLK0_ON_Pos)) 342 343 #define BSP_CLKMON_REG_FSP_IP_MTU3(channel) (R_CPG->CPG_CLKMON_MTU) 344 #define BSP_CLKMON_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_CLKMON_MTU_CLK0_MON_Pos)) 345 346 #define BSP_RST_REG_FSP_IP_MTU3(channel) (R_CPG->CPG_RST_MTU) 347 #define BSP_RST_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_RST_MTU_UNIT0_RSTB_Pos)) 348 349 #define BSP_RSTMON_REG_FSP_IP_MTU3(channel) (R_CPG->CPG_RSTMON_MTU) 350 #define BSP_RSTMON_BIT_FSP_IP_MTU3(channel) (1U << (R_CPG_CPG_RSTMON_MTU_RST0_MON_Pos)) 351 352 /* CPG_PL1_DDIV.DIVPL1_SET options. */ 353 #define BSP_CLOCKS_PL1_DIV_1 (0) // Divide ICLK source clock by 1 354 #define BSP_CLOCKS_PL1_DIV_2 (1) // Divide ICLK source clock by 2 355 #define BSP_CLOCKS_PL1_DIV_4 (2) // Divide ICLK source clock by 4 356 #define BSP_CLOCKS_PL1_DIV_8 (3) // Divide ICLK source clock by 8 357 358 /* CPG_PL2_DDIV.DIVPL2B_SET options. */ 359 #define BSP_CLOCKS_PL2B_DIV_1 (0) // Divide P0CLK source clock by 1 360 #define BSP_CLOCKS_PL2B_DIV_2 (1) // Divide P0CLK source clock by 2 361 #define BSP_CLOCKS_PL2B_DIV_4 (2) // Divide P0CLK source clock by 4 362 #define BSP_CLOCKS_PL2B_DIV_8 (3) // Divide P0CLK source clock by 8 363 #define BSP_CLOCKS_PL2B_DIV_32 (4) // Divide P0CLK source clock by 32 364 365 /* CPG_PL3_DDIV.DIVPL3C_SET options. */ 366 #define BSP_CLOCKS_PL3C_DIV_1 (0) // Divide SPI0CLK source clock by 1 367 #define BSP_CLOCKS_PL3C_DIV_2 (1) // Divide SPI0CLK source clock by 2 368 #define BSP_CLOCKS_PL3C_DIV_4 (2) // Divide SPI0CLK source clock by 4 369 #define BSP_CLOCKS_PL3C_DIV_8 (3) // Divide SPI0CLK source clock by 8 370 #define BSP_CLOCKS_PL3C_DIV_32 (4) // Divide SPI0CLK source clock by 32 371 372 /* CPG_PL3_DDIV.DIVPL3B_SET options. */ 373 #define BSP_CLOCKS_PL3B_DIV_1 (0) // Divide P1CLK source clock by 1 374 #define BSP_CLOCKS_PL3B_DIV_2 (1) // Divide P1CLK source clock by 2 375 #define BSP_CLOCKS_PL3B_DIV_4 (2) // Divide P1CLK source clock by 4 376 #define BSP_CLOCKS_PL3B_DIV_8 (3) // Divide P1CLK source clock by 8 377 #define BSP_CLOCKS_PL3B_DIV_32 (4) // Divide P1CLK source clock by 32 378 379 /* CPG_PL3_DDIV.DIVPL3A_SET options. */ 380 #define BSP_CLOCKS_PL3A_DIV_1 (0) // Divide P2CLK source clock by 1 381 #define BSP_CLOCKS_PL3A_DIV_2 (1) // Divide P2CLK source clock by 2 382 #define BSP_CLOCKS_PL3A_DIV_4 (2) // Divide P2CLK source clock by 4 383 #define BSP_CLOCKS_PL3A_DIV_8 (3) // Divide P2CLK source clock by 8 384 #define BSP_CLOCKS_PL3A_DIV_32 (4) // Divide P2CLK source clock by 32 385 386 /* CPG_PL6_DDIV.DIVPL6B_SET options. */ 387 #define BSP_CLOCKS_PL6B_DIV_1 (0) // Divide I3CLK source clock by 1 388 #define BSP_CLOCKS_PL6B_DIV_2 (1) // Divide I3CLK source clock by 2 389 #define BSP_CLOCKS_PL6B_DIV_4 (2) // Divide I3CLK source clock by 4 390 #define BSP_CLOCKS_PL6B_DIV_8 (3) // Divide I3CLK source clock by 8 391 #define BSP_CLOCKS_PL6B_DIV_32 (4) // Divide I3CLK source clock by 32 392 393 /* CPG_PL6_DDIV.DIVPL6A_SET options. */ 394 #define BSP_CLOCKS_PL6A_DIV_1 (0) // Divide I2CLK source clock by 1 395 #define BSP_CLOCKS_PL6A_DIV_2 (1) // Divide I2CLK source clock by 2 396 #define BSP_CLOCKS_PL6A_DIV_4 (2) // Divide I2CLK source clock by 4 397 #define BSP_CLOCKS_PL6A_DIV_8 (3) // Divide I2CLK source clock by 8 398 #define BSP_CLOCKS_PL6A_DIV_32 (4) // Divide I2CLK source clock by 32 399 400 /* CPG_SDHI_DDIV.DIVSDHI2_SET options. */ 401 #define BSP_CLOCKS_SDHI2_DIV_1 (0) // Divide SD2CLK source clock by 1 402 #define BSP_CLOCKS_SDHI2_DIV_2 (1) // Divide SD2CLK source clock by 2 403 404 /* CPG_SDHI_DDIV.DIVSDHI1_SET options. */ 405 #define BSP_CLOCKS_SDHI1_DIV_1 (0) // Divide SD1CLK source clock by 1 406 #define BSP_CLOCKS_SDHI1_DIV_2 (1) // Divide SD1CLK source clock by 2 407 408 /* CPG_SDHI_DDIV.DIVSDHI0_SET options. */ 409 #define BSP_CLOCKS_SDHI0_DIV_1 (0) // Divide SD0CLK source clock by 1 410 #define BSP_CLOCKS_SDHI0_DIV_2 (1) // Divide SD0CLK source clock by 2 411 412 /* CPG_OCTA_DDIV.DIVOCTA_SET options. */ 413 #define BSP_CLOCKS_OCTA_DIV_1 (0) // Divide OCCLK source clock by 1 414 #define BSP_CLOCKS_OCTA_DIV_2 (1) // Divide OCCLK source clock by 2 415 #define BSP_CLOCKS_OCTA_DIV_4 (2) // Divide OCCLK source clock by 4 416 #define BSP_CLOCKS_OCTA_DIV_8 (3) // Divide OCCLK source clock by 8 417 #define BSP_CLOCKS_OCTA_DIV_32 (4) // Divide OCCLK source clock by 32 418 419 /* CPG_SPI_DDIV.DIVSPI_SET options. */ 420 #define BSP_CLOCKS_SPI_DIV_1 (0) // Divide SPICLK source clock by 1 421 #define BSP_CLOCKS_SPI_DIV_2 (1) // Divide SPICLK source clock by 2 422 #define BSP_CLOCKS_SPI_DIV_4 (2) // Divide SPICLK source clock by 4 423 #define BSP_CLOCKS_SPI_DIV_8 (3) // Divide SPICLK source clock by 8 424 #define BSP_CLOCKS_SPI_DIV_32 (4) // Divide SPICLK source clock by 32 425 426 /* CPG_PLL_DSEL options. */ 427 #define BSP_CLOCKS_SOURCE_CLOCK_OSC_0024 (0) // Select OSC/1000 clock 428 #define BSP_CLOCKS_SOURCE_CLOCK_PLL4 (1) // Select PLL4 clock 429 430 /* CPG_SDHI_DSEL options. */ 431 #define BSP_CLOCKS_SOURCE_CLOCK_PLL2_800 (0) // Select 800MHz 432 #define BSP_CLOCKS_SOURCE_CLOCK_PLL6_500 (2) // Select 500MHz 433 #define BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 (3) // Select 266MHz 434 435 /* CPG_OCTA_SSEL and CPG_SPI_SSEL options. */ 436 #define BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 (0) // Select 400MHz 437 #define BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 (2) // Select 266MHz 438 #define BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 (3) // Select 250MHz 439 440 /*********************************************************************************************************************** 441 * Typedef definitions 442 **********************************************************************************************************************/ 443 444 /*********************************************************************************************************************** 445 * Exported global variables 446 **********************************************************************************************************************/ 447 448 /*********************************************************************************************************************** 449 * Exported global functions (to be accessed by other files) 450 **********************************************************************************************************************/ 451 452 /* Public functions defined in bsp_clocks.c */ 453 void bsp_clock_init(void); // Used internally by BSP 454 void bsp_clock_freq_init_cfg(void); // Used internally by BSP 455 456 #if BSP_TZ_CFG_INIT_SECURE_ONLY 457 void bsp_clock_freq_var_init(void); // Used internally by BSP 458 459 #endif 460 461 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 462 FSP_FOOTER 463 464 #endif 465
