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Searched refs:BSP_CFG_DIVPL6A_SET_DIV (Results 1 – 2 of 2) sorted by relevance

/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/
Dbsp_clock_cfg.h54 #define BSP_CFG_DIVPL6A_SET_DIV (BSP_CLOCKS_PL6A_DIV_1) … macro
/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/mcu/all/
Dbsp_clocks.c210 setting_value = (uint32_t) ((BSP_CFG_DIVPL6A_SET_DIV << R_CPG_CPG_PL6_DDIV_DIVPL6A_SET_Pos) | in bsp_clock_freq_init_cfg()