Home
last modified time | relevance | path

Searched refs:BSP_CFG_DIVPL2B_SET_DIV (Results 1 – 2 of 2) sorted by relevance

/hal_renesas-latest/zephyr/rz/rz_cfg/fsp_cfg/bsp/rzg3s/
Dbsp_clock_cfg.h18 #define BSP_CFG_DIVPL2B_SET_DIV (BSP_CLOCKS_PL2B_DIV_1) … macro
/hal_renesas-latest/drivers/rz/fsp/src/rzg/bsp/mcu/all/
Dbsp_clocks.c184 setting_value = (uint32_t) (BSP_CFG_DIVPL2B_SET_DIV << R_CPG_CPG_PL2_DDIV_DIVPL2B_SET_Pos); in bsp_clock_freq_init_cfg()