1 /* 2 * ========================================================== 3 * 4 * Copyright (C) 2020 QuickLogic Corporation 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * File : eoss3_hal_pkfb.h 16 * Purpose : 17 * 18 * =========================================================== 19 * 20 */ 21 22 #ifndef __EOSS3_HAL_PKFB_H_ 23 #define __EOSS3_HAL_PKFB_H_ 24 25 #include "eoss3_dev.h" 26 #include "test_types.h" 27 #include "eoss3_hal_def.h" 28 29 /****************************************************************************** 30 * Packet FIFO * 31 ******************************************************************************/ 32 /*! \enum FIFO_Type 33 \brief FIFO types available 34 */ 35 typedef enum 36 { 37 FIFO0 = 0, 38 FIFO1, 39 FIFO2, 40 FIFO8K, 41 FIFO_INVALID = -1 42 }FIFO_Type; 43 44 /*! \enum FIFO_SrcType 45 \brief FIFO sources that can push data to FIFO 46 */ 47 typedef enum 48 { 49 FIFO_SRC_M4 = 0, 50 FIFO_SRC_FFE0, 51 FIFO_SRC_FFE1, 52 FIFO_SRC_INVALID = -1 53 } FIFO_SrcType; 54 55 /*! \enum FIFO_DestType 56 \brief FIFO destinations that can pop data from FIFO 57 */ 58 typedef enum 59 { 60 FIFO_DEST_M4 = 0, 61 FIFO_DEST_AP, 62 FIFO_DEST_INVALID = -1, 63 } FIFO_DestType; 64 65 /*! \enum FIFO_PushIntType 66 \brief FIFO interrupt configuration for Push side 67 */ 68 typedef enum 69 { 70 FIFO_PUSH_INT_OVERFLOW = 0x1, 71 FIFO_PUSH_INT_THRESHOLD = 0x2, 72 FIFO_PUSH_INT_SRAM_SLEEP = 0x4, 73 FIFO_PUSH_INT_INVALID = -1 74 }FIFO_PushIntType; 75 76 /*! \enum FIFO_PopIntType 77 \brief FIFO interrupt configuration for Pop side 78 */typedef enum 79 { 80 FIFO_POP_INT_UNDERFLOW = 0x1, 81 FIFO_POP_INT_THRESHOLD = 0x2, 82 FIFO_POP_INT_SRAM_SLEEP = 0x4, 83 FIFO_POP_INT_INVALID = -1 84 }FIFO_PopIntType; 85 86 87 /*! \def FIFO_WORD_WIDTH 88 \brief A macro to define FIFO0, FIFO1 and FIFO2 WORD Width. 89 */ 90 #define FIFO_WORD_WIDTH 4 //4 Bytes or 32 bits 91 92 /*! \def FIFO8X_WORD_WIDTH 93 \brief A macro to define 8K FIFO WORD Width. 94 */ 95 #define FIFO8X_WORD_WIDTH 4 //4 Bytes or 32 bits 96 97 /*! \def FIFO0_SZ 98 \brief A macro to define FIFO 0 size in words. 99 */ 100 #define FIFO0_SZ (256) 101 102 /*! \def FIFO1_SZ 103 \brief A macro to define FIFO 1 size in words. 104 */ 105 #define FIFO1_SZ (128) 106 107 /*! \def FIFO2_SZ 108 \brief A macro to define FIFO 2 size in words. 109 */ 110 #define FIFO2_SZ (128) 111 112 /*! \def FIFO8K_SZ 113 \brief A macro to define FIFO 8K size in words. 114 */ 115 #define FIFO8K_SZ (8*1024) 116 117 ///@cond PKFB_MACROS 118 /****************************************************************************** 119 * PKFB * 120 ******************************************************************************/ 121 /* FIFO interrupt configuration bit definition */ 122 #define FIFO_NO_INT (0x00) 123 #define FIFO_PUSH_OVERFLOW_INT (0x01) 124 #define FIFO_PUSH_THRESH_INT (0x02) 125 #define FIFO_PUSH_SLEEP_INT (0x04) 126 #define FIFO_POP_UNDERFLOW_INT (0x08) 127 #define FIFO_POP_THRESH_INT (0x10) 128 #define FIFO_POP_SLEEP_INT (0x20) 129 130 /* Macros and bit definition for FIFO control register */ 131 132 #define FIFO_CTRL_ENABLE ((uint32_t) (0x00000000)) 133 #define FIFO_CTRL_PUSH_MUX ((uint32_t) (0x00000001)) 134 #define FIFO_CTRL_POP_MUX ((uint32_t) (0x00000002)) 135 #define FIFO_CTRL_PUSH_INT_MUX ((uint32_t) (0x00000003)) 136 #define FIFO_CTRL_POP_INT_MUX ((uint32_t) (0x00000004)) 137 #define FIFO_CTRL_FFE_SEL ((uint32_t) (0x00000005)) 138 139 #define FIFOx_CTRL_ENABLE(FIFO_INDEX) (PKFB->PKFB_FIFOCTRL |= 1<<((FIFO_INDEX * 8) + FIFO_CTRL_ENABLE)) 140 #define FIFOx_CTRL_DISABLE(FIFO_INDEX) (PKFB->PKFB_FIFOCTRL &= (~1<<((FIFO_INDEX * 8)+ FIFO_CTRL_ENABLE))) 141 142 #define FIFOx_CTRL_PUSH_FFE(FIFO_INDEX) (PKFB->PKFB_FIFOCTRL |= 1<<((FIFO_INDEX * 8) + FIFO_CTRL_PUSH_MUX)) 143 #define FIFOx_CTRL_PUSH_M4(FIFO_INDEX) (PKFB->PKFB_FIFOCTRL &= ~(1<<((FIFO_INDEX * 8) + FIFO_CTRL_PUSH_MUX))); (PKFB->PKFB_FIFOCTRL &= ~(1<<((FIFO_INDEX * 8) + FIFO_CTRL_POP_INT_MUX))) 144 145 #define FIFOx_CTRL_POP_AP(FIFO_INDEX) (PKFB->PKFB_FIFOCTRL |= 1<<((FIFO_INDEX * 8) + FIFO_CTRL_POP_MUX)); (PKFB->PKFB_FIFOCTRL |= 1<<((FIFO_INDEX * 8) + FIFO_CTRL_PUSH_INT_MUX)) 146 #define FIFOx_CTRL_POP_M4(FIFO_INDEX) (PKFB->PKFB_FIFOCTRL &= ~(1<<((FIFO_INDEX * 8) + FIFO_CTRL_POP_MUX))); (PKFB->PKFB_FIFOCTRL &= ~(1<<((FIFO_INDEX * 8) + FIFO_CTRL_PUSH_INT_MUX))) 147 148 #define FIFOx_CTRL_FFE0_SEL(FIFO_INDEX) (FIFOx_CTRL_PUSH_FFE(FIFO_INDEX)); (PKFB->PKFB_FIFOCTRL &= ~(1<<((FIFO_INDEX * 8) + FIFO_CTRL_FFE_SEL))) 149 #define FIFOx_CTRL_FFE1_SEL(FIFO_INDEX) (FIFOx_CTRL_PUSH_FFE(FIFO_INDEX)); (PKFB->PKFB_FIFOCTRL |= (1<<((FIFO_INDEX * 8) + FIFO_CTRL_FFE_SEL))) 150 151 #define FIFOx_CTRL_RESET(FIFO_INDEX) (PKFB->PKFB_FIFOCTRL &= ~(0xFF<<(FIFO_INDEX * 8))) 152 153 /* Macros and bit definition for FIFO Status register */ 154 #define FIFO_STATUS_SRAM_SLEEP_ON (0x00000000) 155 #define FIFO_STATUS_SRAM_SLEEP_LS (0x00000001) 156 #define FIFO_STATUS_SRAM_SLEEP_DS (0x00000002) 157 #define FIFO_STATUS_SRAM_SLEEP_SD (0x00000003) 158 #define FIFO_STATUS_PUSH_INT_OVER (0x00000004) 159 #define FIFO_STATUS_PUSH_INT_THRESH (0x00000008) 160 #define FIFO_STATUS_PUSH_INT_SLEEP (0x00000010) 161 #define FIFO_STATUS_POP_INT_UNDER (0x00000020) 162 #define FIFO_STATUS_POP_INT_THRESH (0x00000040) 163 #define FIFO_STATUS_POP_INT_SLEEP (0x00000080) 164 165 166 #define FIFOx_STATUS_SRAM_SLEEP(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS & (FIFO_STATUS_SRAM_SLEEP_SD)<<(FIFO_INDEX * 8)) 167 168 #define IS_FIFOx_STATUS_SRAM_ACTIVE(FIFO_INDEX) (!FIFOx_STATUS_SRAM_SLEEP(FIFO_INDEX)?1:0) 169 #define IS_FIFOx_STATUS_SRAM_LS(FIFO_INDEX) (FIFOx_STATUS_SRAM_SLEEP(FIFO_INDEX) == (FIFO_STATUS_SRAM_SLEEP_LS)<<(FIFO_INDEX * 8)? 1:0) 170 #define IS_FIFOx_STATUS_SRAM_DS(FIFO_INDEX) (FIFOx_STATUS_SRAM_SLEEP(FIFO_INDEX) == (FIFO_STATUS_SRAM_SLEEP_DS)<<(FIFO_INDEX * 8)? 1:0) 171 #define IS_FIFOx_STATUS_SRAM_SD(FIFO_INDEX) (FIFOx_STATUS_SRAM_SLEEP(FIFO_INDEX) == (FIFO_STATUS_SRAM_SLEEP_SD)<<(FIFO_INDEX * 8)? 1:0) 172 173 174 #define FIFOx_STATUS_CLEAR_PUSH_INT_OVER(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS |= (FIFO_STATUS_PUSH_INT_OVER)<<(FIFO_INDEX * 8)) 175 #define FIFOx_STATUS_READ_PUSH_INT_OVER(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS & (FIFO_STATUS_PUSH_INT_OVER)<<(FIFO_INDEX * 8)) 176 177 #define FIFOx_STATUS_CLEAR_PUSH_INT_THRESH(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS |= (FIFO_STATUS_PUSH_INT_THRESH)<<(FIFO_INDEX * 8)) 178 #define FIFOx_STATUS_READ_PUSH_INT_THRESH(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS & (FIFO_STATUS_PUSH_INT_THRESH)<<(FIFO_INDEX * 8)) 179 180 #define FIFOx_STATUS_CLEAR_PUSH_INT_SLEEP(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS |= (FIFO_STATUS_PUSH_INT_SLEEP)<<(FIFO_INDEX * 8)) 181 #define FIFOx_STATUS_READ_PUSH_INT_SLEEP(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS & (FIFO_STATUS_PUSH_INT_SLEEP)<<(FIFO_INDEX * 8)) 182 183 #define FIFOx_STATUS_CLEAR_POP_INT_UNDER(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS |= (FIFO_STATUS_POP_INT_UNDER)<<(FIFO_INDEX * 8)) 184 #define FIFOx_STATUS_READ_POP_INT_UNDER(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS & (FIFO_STATUS_POP_INT_UNDER)<<(FIFO_INDEX * 8)) 185 186 #define FIFOx_STATUS_CLEAR_POP_INT_THRESH(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS |= (FIFO_STATUS_POP_INT_THRESH)<<(FIFO_INDEX * 8)) 187 #define FIFOx_STATUS_READ_POP_INT_THRESH(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS & (FIFO_STATUS_POP_INT_THRESH)<<(FIFO_INDEX * 8)) 188 189 #define FIFOx_STATUS_CLEAR_POP_INT_SLEEP(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS |= (FIFO_STATUS_POP_INT_SLEEP)<<(FIFO_INDEX * 8)) 190 #define FIFOx_STATUS_READ_POP_INT_SLEEP(FIFO_INDEX) (PKFB->PKFB_FIFOSTATUS & (FIFO_STATUS_POP_INT_SLEEP)<<(FIFO_INDEX * 8)) 191 192 /* Macros and bit definition for FIFO PUSH control register */ 193 #define FIFO_SLEEP_EN (0) 194 #define FIFO_SLEEP_TYPE (1) 195 #define FIFO_INT_OVER_UNDER (2) 196 #define FIFO_INT_THRESH (3) 197 #define FIFO_INT_SRAM_SLEEP (4) 198 #define FIFO_THRESH (16) 199 200 #define FIFOx_PUSH_SLEEP_ENABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) |= 1<<FIFO_SLEEP_EN) 201 #define FIFOx_PUSH_SLEEP_DISABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_SLEEP_EN)) 202 203 //#define FIFOx_PUSH_SLEEP_DS(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_SLEEP_TYPE)) 204 //#define FIFOx_PUSH_SLEEP_SD(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) |= (1<<FIFO_SLEEP_TYPE)) 205 206 #define FIFOx_PUSH_INT_OVER_ENABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) |= (1<<FIFO_INT_OVER_UNDER)) 207 #define FIFOx_PUSH_INT_OVER_DISABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_INT_OVER_UNDER)) 208 209 #define FIFOx_PUSH_INT_THRESH_ENABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) |= (1<<FIFO_INT_THRESH)) 210 #define FIFOx_PUSH_INT_THRESH_DISABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_INT_THRESH)) 211 212 #define FIFOx_PUSH_INT_SRAM_SLEEP_ENABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) |= (1<<FIFO_INT_SRAM_SLEEP)) 213 #define FIFOx_PUSH_INT_SRAM_SLEEP_DISABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_INT_SRAM_SLEEP)) 214 215 #define FIFOx_PUSH_THRESHOLD(FIFO_INDEX, COUNT) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) |= (COUNT<<FIFO_THRESH)) 216 #define FIFOx_PUSH_THRESHOLD_RESET(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) &= ~(0x1FF<<FIFO_THRESH)) 217 218 #define FIFOx_PUSH_CTRL_RESET(FIFO_INDEX) (*(&PKFB->PKFB_PF0PUSHCTRL+ FIFO_INDEX*0x4) = 0) 219 220 /* Macros and bit definition for FIFO POP control register */ 221 #define FIFOx_POP_SLEEP_ENABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) |= 1<<FIFO_SLEEP_EN) 222 #define FIFOx_POP_SLEEP_DISABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_SLEEP_EN)) 223 224 #define FIFOx_POP_SLEEP_DS(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_SLEEP_TYPE)) 225 #define FIFOx_POP_SLEEP_SD(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) |= (1<<FIFO_SLEEP_TYPE)) 226 227 #define FIFOx_POP_INT_OVER_ENABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) |= (1<<FIFO_INT_OVER_UNDER)) 228 #define FIFOx_POP_INT_OVER_DISABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_INT_OVER_UNDER)) 229 230 #define FIFOx_POP_INT_THRESH_ENABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) |= (1<<FIFO_INT_THRESH)) 231 #define FIFOx_POP_INT_THRESH_DISABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_INT_THRESH)) 232 233 #define FIFOx_POP_INT_SRAM_SLEEP_ENABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) |= (1<<FIFO_INT_SRAM_SLEEP)) 234 #define FIFOx_POP_INT_SRAM_SLEEP_DISABLE(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) &= ~(1<<FIFO_INT_SRAM_SLEEP)) 235 236 #define FIFOx_POP_THRESHOLD(FIFO_INDEX, COUNT) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) |= (COUNT<<FIFO_THRESH)) 237 #define FIFOx_POP_THRESHOLD_RESET(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) &= ~(0x1FF<<FIFO_THRESH)) 238 239 #define FIFOx_POP_RESET(FIFO_INDEX) (*(&PKFB->PKFB_PF0POPCTRL+ FIFO_INDEX*0x4) = 0) 240 241 /* Macros and bit definition for FIFO count register */ 242 #define FIFO_COUNT (0x000001FF) 243 #define FIFO_PUSH_OFFSET (16) 244 #define FIFO_EMPTY_MASK (15) 245 #define FIFO_FULL_MASK (31) 246 247 248 #define FIFOx_GET_POP_COUNT(FIFO_INDEX) (*(&PKFB->PKFB_PF0CNT + FIFO_INDEX*0x4) & FIFO_COUNT) 249 #define FIFOx_GET_PUSH_COUNT(FIFO_INDEX) ((*(&PKFB->PKFB_PF0CNT + FIFO_INDEX*0x4)>>FIFO_PUSH_OFFSET) & FIFO_COUNT) 250 251 #define IS_FIFO_EMPTY(FIFO_INDEX) (*(&PKFB->PKFB_PF0CNT + FIFO_INDEX*0x4) & (1<<FIFO_EMPTY_MASK)) 252 #define IS_FIFO_FULL(FIFO_INDEX) (*(&PKFB->PKFB_PF0CNT + FIFO_INDEX*0x4) & (1<<FIFO_FULL_MASK)) 253 254 /* Macros for FIFO data register */ 255 #define FIFOx_DATA_WRITE(FIFO_INDEX, VALUE) (*(&PKFB->PKFB_PF0DATA + FIFO_INDEX*0x4) |= VALUE) 256 #define FIFOx_DATA_READ(FIFO_INDEX) (*(&PKFB->PKFB_PF0DATA + FIFO_INDEX*0x4)) 257 258 /* Add FIFO collision macros and bit definitions */ 259 260 ///@endcond PKFB_MACROS 261 262 /*! \struct FIFO_Config eoss3_hal_pkfb.h "inc/eoss3_hal_pkfb.h" 263 * \brief FIFO configuration for PUSH source and POP destination. 264 */ 265 typedef struct 266 { 267 FIFO_Type eFifoID; /*!< FIFO number to configure */ 268 FIFO_SrcType eSrc; /*!< FIFO PUSH source */ 269 FIFO_DestType eDest; /*!< FIFO POP destination */ 270 }FIFO_Config; 271 272 /*! \struct FIFO_IntConfig eoss3_hal_pkfb.h "inc/eoss3_hal_pkfb.h" 273 * \brief FIFO interrupt configuration for PUSH and POP side. 274 */ 275 typedef struct 276 { 277 FIFO_DestType ePushIntMux; /*!< FIFO owner that should receive PUSH interrupts */ 278 FIFO_DestType ePopIntMux; /*!< FIFO owner that should receive POP interrupts */ 279 FIFO_PushIntType ePushIntType; /*!< FIFO PUSH side interrupts type */ 280 FIFO_PushIntType ePopIntType; /*!< FIFO POP side interrupt types */ 281 UINT32_t uiPushThresholdCount; /*!< Threshold in words to generate PUSH side interrupt */ 282 UINT32_t uiPopThresholdCount; /*!< Threshold in workds to generate POP side interrupt */ 283 }FIFO_IntConfig; 284 285 /* Exported functions --------------------------------------------------------*/ 286 /*! \fn void HAL_FIFO_Enable(FIFO_Type eFifoID) 287 * \brief Enable FIFO for PUSH/POP operation. 288 * 289 * \param eFifoID FIFO ID to enable 290 */ 291 void HAL_FIFO_Enable(FIFO_Type eFifoID); 292 293 294 /*! \fn void HAL_FIFO_Disable(FIFO_Type eFifoID) 295 * \brief Enable FIFO for PUSH/POP operation. 296 * 297 * \param eFifoID FIFO ID to disable 298 */ 299 void HAL_FIFO_Disable(FIFO_Type eFifoID); 300 301 302 /*! \fn UINT32_t HAL_FIFO_Read(FIFO_Type eFifoID, INT32_t iLen, UINT32_t *puiRxBuf) 303 * \brief Read data from FIFO. 304 * 305 * \param eFifoID FIFO ID to read from 306 * \param iLen number of 32 bit words to read 307 * \param puiRxBuf pointer to buffer where data has to be read 308 * \return UINT32_t Number of 32-bit words read from FIFO 309 */ 310 UINT32_t HAL_FIFO_Read(FIFO_Type eFifoID, INT32_t iLen, UINT32_t *puiRxBuf); 311 312 313 /*! \fn UINT32_t HAL_FIFO8K_Read(FIFO_Type eFifoID, INT32_t iLen, UINT16_t *pusRxBuf) 314 * \brief Read data from 8K FIFO. 315 * 316 * \param eFifoID FIFO ID of 8K FIFO 317 * \param iLen number of 16 bit words to read 318 * \param pusRxBuf pointer to buffer where data has to be read 319 * \return UINT32_t Number of 16-bit words read from FIFO 320 */ 321 UINT32_t HAL_FIFO8K_Read(FIFO_Type eFifoID, INT32_t iLen, UINT16_t *pusRxBuf); 322 323 324 /*! \fn UINT32_t HAL_FIFO_Write(FIFO_Type eFifoID, INT32_t iLen, UINT32_t *puiTxBuf) 325 * \brief Write data to FIFO. 326 * 327 * \param eFifoID FIFO ID to write 328 * \param iLen number of 32 bit words to write 329 * \param puiTxBuf pointer to buffer with data to be written to FIFO 330 * \return UINT32_t Number of 32-bit words written to FIFO 331 */ 332 UINT32_t HAL_FIFO_Write(FIFO_Type eFifoID, INT32_t iLen, UINT32_t *puiTxBuf); 333 334 335 /*! \fn UINT32_t HAL_FIFO8K_Write(FIFO_Type eFifoID, INT32_t iLen, UINT16_t *pusTxBuf) 336 * \brief Write data to 8K FIFO. 337 * 338 * \param eFifoID FIFO ID of 8K FIFO to write 339 * \param iLen number of 16 bit words to write 340 * \param pusTxBuf pointer to buffer with data to be written to FIFO 341 * \return UINT32_t Number of 16-bit words written to FIFO 342 */ 343 UINT32_t HAL_FIFO8K_Write(FIFO_Type eFifoID, INT32_t iLen, UINT16_t *pusTxBuf); 344 345 346 /*! \fn void HAL_FIFO_PushSleepEnable(FIFO_Type eFifoID) 347 * \brief Enable sleep mode on PUSH side of FIFO. 348 * 349 * \param eFifoID FIFO ID to enable PUSH side sleep mode 350 */ 351 void HAL_FIFO_PushSleepEnable(FIFO_Type eFifoID); 352 353 354 /*! \fn void HAL_FIFO_PushSleepDisable(FIFO_Type eFifoID) 355 * \brief Disable sleep mode on PUSH side of FIFO. 356 * 357 * \param eFifoID FIFO ID to disable PUSH side sleep mode 358 */ 359 void HAL_FIFO_PushSleepDisable(FIFO_Type eFifoID); 360 361 362 /*! \fn void HAL_FIFO_PopSleepEnable(FIFO_Type eFifoID) 363 * \brief Enable sleep mode on POP side of FIFO. 364 * 365 * \param eFifoID FIFO ID to enable POP side sleep mode 366 */ 367 void HAL_FIFO_PopSleepEnable(FIFO_Type eFifoID); 368 369 370 /*! \fn void HAL_FIFO_PopSleepDisable(FIFO_Type eFifoID) 371 * \brief Disable sleep mode on POP side of FIFO. 372 * 373 * \param eFifoID FIFO ID to disable POP side sleep mode 374 */ 375 void HAL_FIFO_PopSleepDisable(FIFO_Type eFifoID); 376 377 378 /*! \fn void HAL_FIFO_PopCount(FIFO_Type eFifoID) 379 * \brief Number of words available in FIFO to pop. 380 * 381 * \param eFifoID FIFO ID to read available word count for POP 382 */ 383 UINT32_t HAL_FIFO_PopCount(FIFO_Type eFifoID); 384 385 386 /*! \fn void HAL_FIFO_PushCount(FIFO_Type eFifoID) 387 * \brief Number of words available for PUSH operation in FIFO. 388 * 389 * \param eFifoID FIFO ID to read available word count for PUSH 390 */ 391 UINT32_t HAL_FIFO_PushCount(FIFO_Type eFifoID); 392 393 394 /*! \fn HAL_StatusTypeDef HAL_FIFO_Init(FIFO_Config xFifoConfig) 395 * \brief Initialize FIFO source and destination for PUSH and POP operation. 396 * 397 * \param xFifoConfig FIFO_Config structure filled by user to initialize FIFO 398 * \return HAL_StatusTypeDef Status of FIFO initialization. HAL_OK or HAL_ERROR. 399 */ 400 HAL_StatusTypeDef HAL_FIFO_Init(FIFO_Config xFifoConfig); 401 402 /*! \fn HAL_StatusTypeDef HAL_FIFO_ConfigInt(FIFO_IntConfig xFifoIntConfig) 403 * \brief Initialize FIFO interrupts for different conditions. i.e. overflow, underflow 404 * threshold, sleep etc. 405 * 406 * \param xFifoIntConfig FIFO_Config structure filled by user to initialize FIFO 407 * \return HAL_StatusTypeDef Status of FIFO interrupt configuration. HAL_OK or HAL_ERROR. 408 */ 409 HAL_StatusTypeDef HAL_FIFO_ConfigInt(FIFO_IntConfig xFifoIntConfig); 410 411 412 /*! \fn void HAL_FIFO_ClkInit(FIFO_Type eFifoID) 413 * \brief Initialize clock for FIFO. 414 * 415 * \param eFifoID FIFO ID to initialize clock 416 */ 417 void HAL_FIFO_ClkInit(FIFO_Type eFifoID); 418 419 /*! \fn void HAL_FIFO_ClkDeInit(FIFO_Type eFifoID) 420 * \brief Disable clock for FIFO. 421 * 422 * \param eFifoID FIFO ID to disable clock 423 */ 424 void HAL_FIFO_ClkDeInit(FIFO_Type eFifoID); 425 426 /*! \fn HAL_StatusTypeDef HAL_FIFO_PowerInit(FIFO_Type eFifoID) 427 * \brief Initialize power for FIFO. 428 * 429 * \param eFifoID FIFO ID to initialize power 430 * \return HAL_StatusTypeDef Status of power initialization of FIFO. HAL_OK or HAL_ERROR. 431 */ 432 HAL_StatusTypeDef HAL_FIFO_PowerInit(FIFO_Type eFifoID); 433 434 #endif /* __EOSS3_HAL_PKFB_H_ */ 435
