1 /* 2 * ========================================================== 3 * 4 * Copyright (C) 2020 QuickLogic Corporation 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * File : eoss3_hal_pads.h 16 * Purpose : This file contains macros, structures and APIs to 17 * configure pads 18 * 19 * 20 * =========================================================== 21 * 22 */ 23 24 #ifndef __EOSS3_HAL_PADS_H 25 #define __EOSS3_HAL_PADS_H 26 27 #include "eoss3_dev.h" 28 #include <stdbool.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /*Sensorhub3B Pads, BGA package */ 35 #define PAD_0 ((uint8_t) 0) /* Pin 0 */ 36 #define PAD_1 ((uint8_t) 1) /* Pin 1 */ 37 #define PAD_2 ((uint8_t) 2) 38 #define PAD_3 ((uint8_t) 3) 39 #define PAD_4 ((uint8_t) 4) 40 #define PAD_5 ((uint8_t) 5) 41 #define PAD_6 ((uint8_t) 6) 42 #define PAD_7 ((uint8_t) 7) 43 #define PAD_8 ((uint8_t) 8) 44 #define PAD_9 ((uint8_t) 9) 45 #define PAD_10 ((uint8_t) 10) 46 47 #define PAD_11 ((uint8_t) 11) 48 #define PAD_12 ((uint8_t) 12) 49 #define PAD_13 ((uint8_t) 13) 50 #define PAD_14 ((uint8_t) 14) 51 #define PAD_15 ((uint8_t) 15) 52 #define PAD_16 ((uint8_t) 16) 53 #define PAD_17 ((uint8_t) 17) 54 #define PAD_18 ((uint8_t) 18) 55 #define PAD_19 ((uint8_t) 19) 56 #define PAD_20 ((uint8_t) 20) 57 58 #define PAD_21 ((uint8_t) 21) 59 #define PAD_22 ((uint8_t) 22) 60 #define PAD_23 ((uint8_t) 23) 61 #define PAD_24 ((uint8_t) 24) 62 #define PAD_25 ((uint8_t) 25) 63 #define PAD_26 ((uint8_t) 26) 64 #define PAD_27 ((uint8_t) 27) 65 #define PAD_28 ((uint8_t) 28) 66 #define PAD_29 ((uint8_t) 29) 67 #define PAD_30 ((uint8_t) 30) 68 69 #define PAD_31 ((uint8_t) 31) 70 #define PAD_32 ((uint8_t) 32) 71 #define PAD_33 ((uint8_t) 33) 72 #define PAD_34 ((uint8_t) 34) 73 #define PAD_35 ((uint8_t) 35) 74 #define PAD_36 ((uint8_t) 36) 75 #define PAD_37 ((uint8_t) 37) 76 #define PAD_38 ((uint8_t) 38) 77 #define PAD_39 ((uint8_t) 39) 78 #define PAD_40 ((uint8_t) 40) 79 80 #define PAD_41 ((uint8_t) 41) 81 #define PAD_42 ((uint8_t) 42) 82 #define PAD_43 ((uint8_t) 43) 83 #define PAD_44 ((uint8_t) 44) 84 #define PAD_45 ((uint8_t) 45) 85 86 /// @endcond 87 88 /// @cond EXTENDED_REGS_OFFSET 89 /*Extended Configuration registers offset*/ 90 #define SDA0_SEL 0x100 91 #define SDA1_SEL 0x104 92 #define SDA2_SEL 0x108 93 #define SCL0_SEL 0x10C 94 #define SCL1_SEL 0x110 95 #define SCL2_SEL 0x114 96 #define SPIs_CLK_SEL 0x118 97 #define SPIs_SSn_SEL 0x11C 98 #define SPIs_MOSI_SEL 0x120 99 #define SPIm_MISO_SEL 0x124 100 #define PDM_DATA_SEL 0x128 101 #define I2S_DATA_SEL 0x12C 102 #define UART_RXD_SEL 0x134 103 #define IRDA_SIRIN_SEL 0x138 104 #define S_INTR_0_SEL 0x13C 105 #define S_INTR_1_SEL 0x140 106 #define S_INTR_2_SEL 0x144 107 #define S_INTR_3_SEL 0x148 108 #define S_INTR_4_SEL 0x14C 109 #define S_INTR_5_SEL 0x150 110 #define S_INTR_6_SEL 0x154 111 #define S_INTR_7_SEL 0x158 112 #define nUARTCTS_SEL 0x15C 113 #define IO_REG_SEL 0x160 114 #define SW_CLK_SEL 0x170 115 #define SW_IO_SEL 0x174 116 #define FBIO_SEL_1 0x180 117 #define FBIO_SEL_2 0x184 118 #define SPI_SENSOR_MISO_SEL 0x190 119 #define SPI_SENSOR_MOSI_SEL 0x194 120 #define I2S_WD_CLKIN_SEL 0x1A0 121 #define I2S_CLKIN_SEL 0x1A4 122 #define PDM_STAT_IN_SEL 0x1A8 123 #define PDM_CLKIN_SEL 0x1AC3 124 /*Ext registers End*/ 125 126 #define EXT_REG_OFFSET_SHIFT 20 127 #define EXT_REG_OFFSET_BASE SDA0_SEL 128 129 /// @endcond 130 131 /*Pads Functions, INPUT functions configuration does not need any value 132 * so it has been taken as virtual function ID eg. sensor interrupt=0x8*/ 133 134 /// @cond PAD_CONFIG_ALTERNATE_FUNCTIONS 135 #define PAD0_FUNC_SEL_SCL_0 ((uint32_t) (0x00 | (SCL0_SEL << EXT_REG_OFFSET_SHIFT))) 136 #define PAD0_FUNC_SEL_FBIO_0 ((uint32_t) (0x01 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 137 #define PAD0_FUNC_SEL_RESERVE2 ((uint32_t) (0x02)) 138 #define PAD0_FUNC_SEL_RESERVE3 ((uint32_t) (0x03)) 139 140 #define PAD1_FUNC_SEL_SDA_0 ((uint32_t) (0x00 | (SDA0_SEL << EXT_REG_OFFSET_SHIFT))) 141 #define PAD1_FUNC_SEL_FBIO_1 ((uint32_t) (0x01 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 142 143 #define PAD2_FUNC_SEL_FBIO_2 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 144 #define PAD2_FUNC_SEL_SPI_SENSOR_SSn_2 ((uint32_t) (0x01)) 145 #define PAD2_FUNC_SEL_DEBUG_MON_0 ((uint32_t) (0x02)) 146 #define PAD2_FUNC_SEL_BATT_MON ((uint32_t) (0x03)) 147 #define PAD2_FUNC_SEL_SENS_INT_1 ((uint32_t) (0x00 | (S_INTR_1_SEL << EXT_REG_OFFSET_SHIFT))) 148 149 //#define PAD3_FUNC_SEL_S_INTR_0 ((uint32_t) (0x00)) /*old AP_INTR , FIXME: Input line Intr*/ 150 #define PAD3_FUNC_SEL_FBIO_3 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 151 #define PAD3_FUNC_SEL_SENS_INT_0 ((uint32_t) (0x00 | (S_INTR_0_SEL << EXT_REG_OFFSET_SHIFT))) 152 153 #define PAD4_FUNC_SEL_FBIO_4 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 154 #define PAD4_FUNC_SEL_SPI_SENSOR_SSn_3 ((uint32_t) (0x01)) 155 #define PAD4_FUNC_SEL_DEBUG_MON_1 ((uint32_t) (0x02)) 156 #define PAD4_FUNC_SEL_SDA_1_DPU ((uint32_t) (0x03)) 157 #define PAD4_FUNC_SEL_SENS_INT_2 ((uint32_t) (0x00 | (S_INTR_2_SEL << EXT_REG_OFFSET_SHIFT))) 158 159 #define PAD5_FUNC_SEL_FBIO_5 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 160 #define PAD5_FUNC_SEL_SPI_SENSOR_SSn_4 ((uint32_t) (0x01)) 161 #define PAD5_FUNC_SEL_DEBUG_MON_2 ((uint32_t) (0x02)) 162 #define PAD5_FUNC_SEL_SDA_0_DPU ((uint32_t) (0x03)) 163 #define PAD5_FUNC_SEL_SENS_INT_3 ((uint32_t) (0x00 | (S_INTR_3_SEL << EXT_REG_OFFSET_SHIFT))) 164 165 #define PAD6_FUNC_SEL_FBIO_6 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 166 #define PAD6_FUNC_SPI_SENSOR_MOSI ((uint32_t) (0x01 | (SPI_SENSOR_MOSI_SEL << EXT_REG_OFFSET_SHIFT))) 167 #define PAD6_FUNC_SEL_DEBUG_MON_3 ((uint32_t) (0x02)) 168 #define PAD6_FUNC_SEL_GPIO_0 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 169 //#define PAD6_FUNC_SEL_FCLK ((uint32_t) (0x0)) Fixme:Not used 170 #define PAD6_FUNC_SEL_IRDA_SIRIN ((uint32_t) (0x00 | (IRDA_SIRIN_SEL << EXT_REG_OFFSET_SHIFT))) 171 #define PAD6_FUNC_SEL_SENS_INT_1 ((uint32_t) (0x00 | (S_INTR_1_SEL << EXT_REG_OFFSET_SHIFT))) 172 173 #define PAD7_FUNC_SEL_FBIO_7 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 174 #define PAD7_FUNC_SPI_SENSOR_SSN5 ((uint32_t) (0x01)) 175 #define PAD7_FUNC_SEL_DEBUG_MON_4 ((uint32_t) (0x02)) 176 #define PAD7_FUNC_SEL_SWV ((uint32_t) (0x03)) 177 //#define PAD7_FUNC_SEL_SENS_INT_5 ((uint32_t) (0x00 | (S_INTR_5_SEL << EXT_REG_OFFSET_SHIFT))) 178 #define PAD7_FUNC_SEL_SENS_INT_4 ((uint32_t) (0x00 | (S_INTR_4_SEL << EXT_REG_OFFSET_SHIFT))) 179 180 #define PAD8_FUNC_SEL_FBIO_8 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 181 #define PAD8_FUNC_PDM_CKO ((uint32_t) (0x01)) 182 #define PAD8_FUNC_I2S_CKO ((uint32_t) (0x02)) 183 #define PAD8_FUNC_IRDA_SIROUT ((uint32_t) (0x03)) 184 #define PAD8_FUNC_SEL_SPI_SENSOR_MISO ((uint32_t) (0x00 | (SPI_SENSOR_MISO_SEL << EXT_REG_OFFSET_SHIFT))) 185 #define PAD8_FUNC_SEL_SENS_INT_2 ((uint32_t) (0x00 | (S_INTR_2_SEL << EXT_REG_OFFSET_SHIFT))) 186 187 #define PAD9_FUNC_SEL_FBIO_9 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 188 #define PAD9_FUNC_SEL_SPI_SENSOR_SSn_1 ((uint32_t) (0x01)) 189 #define PAD9_FUNC_SEL_I2S_WD_CKO ((uint32_t) (0x02)) 190 #define PAD9_FUNC_SEL_GPIO_1 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 191 #define PAD9_FUNC_SEL_PDM_STAT_IN ((uint32_t) (0x00 | (PDM_STAT_IN_SEL << EXT_REG_OFFSET_SHIFT))) 192 #define PAD9_FUNC_SEL_SENS_INT_3 ((uint32_t) (0x00 | (S_INTR_3_SEL << EXT_REG_OFFSET_SHIFT))) 193 194 #define PAD10_FUNC_SEL_FBIO_10 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 195 #define PAD10_FUNC_SEL_SPI_SENSOR_CLK ((uint32_t) (0x01)) 196 #define PAD10_FUNC_SEL_RESERVE ((uint32_t) (0x02)) 197 #define PAD10_FUNC_SEL_SWV ((uint32_t) (0x03)) 198 #define PAD10_FUNC_SEL_I2S_DIN ((uint32_t) (0x00 | (I2S_DATA_SEL << EXT_REG_OFFSET_SHIFT))) 199 #define PAD10_FUNC_SEL_PDM_DIN ((uint32_t) (0x00 | (PDM_DATA_SEL << EXT_REG_OFFSET_SHIFT))) 200 #define PAD10_FUNC_SEL_SENS_INT_4 ((uint32_t) (0x00 | (S_INTR_4_SEL << EXT_REG_OFFSET_SHIFT))) 201 202 #define PAD11_FUNC_SEL_FBIO_11 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 203 #define PAD11_FUNC_SEL_SPI_SENSOR_SSn_6 ((uint32_t) (0x01)) 204 #define PAD11_FUNC_SEL_DEBUG_MON_5 ((uint32_t) (0x02)) 205 #define PAD11_FUNC_SEL_GPIO_2 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 206 #define PAD11_FUNC_SEL_SENS_INT_5 ((uint32_t) (0x00 | (S_INTR_5_SEL << EXT_REG_OFFSET_SHIFT))) 207 208 #define PAD12_FUNC_SEL_FBIO_12 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 209 #define PAD12_FUNC_SEL_SPI_SENSOR_SSn_7 ((uint32_t) (0x01)) 210 #define PAD12_FUNC_SEL_DEBUG_MON_6 ((uint32_t) (0x02)) 211 #define PAD12_FUNC_SEL_IRDA_SIROUT ((uint32_t) (0x03)) 212 #define PAD12_FUNC_SEL_SENS_INT_6 ((uint32_t) (0x00 | (S_INTR_6_SEL << EXT_REG_OFFSET_SHIFT))) 213 214 #define PAD13_FUNC_SEL_FBIO_13 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 215 #define PAD13_FUNC_SEL_SPI_SENSOR_SSn_8 ((uint32_t) (0x01)) 216 #define PAD13_FUNC_SEL_DEBUG_MON_7 ((uint32_t) (0x02)) 217 #define PAD13_FUNC_SEL_SWV ((uint32_t) (0x03)) 218 #define PAD13_FUNC_SEL_SENS_INT_7 ((uint32_t) (0x00 | (S_INTR_7_SEL << EXT_REG_OFFSET_SHIFT))) 219 220 #define PAD14_FUNC_SEL_FBIO_14 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 221 #define PAD14_FUNC_SEL_IRDA_SIROUT ((uint32_t) (0x01)) 222 #define PAD14_FUNC_SEL_SCL_1 ((uint32_t) (0x02 | (SCL1_SEL << EXT_REG_OFFSET_SHIFT))) 223 #define PAD14_FUNC_SEL_GPIO_3 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 224 #define PAD14_FUNC_SEL_SW_DP_CLK ((uint32_t) (0x00 | (SW_CLK_SEL << EXT_REG_OFFSET_SHIFT))) 225 #define PAD14_FUNC_SEL_UART_RXD ((uint32_t) (0x00 | (UART_RXD_SEL << EXT_REG_OFFSET_SHIFT))) 226 #define PAD14_FUNC_SEL_SENS_INT_5 ((uint32_t) (0x00 | (S_INTR_5_SEL << EXT_REG_OFFSET_SHIFT))) 227 228 #define PAD15_FUNC_SEL_SW_DP_IO ((uint32_t) (0x00)) 229 #define PAD15_FUNC_SEL_FBIO_15 ((uint32_t) (0x01 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 230 #define PAD15_FUNC_SEL_SDA_1 ((uint32_t) (0x02 | (SDA1_SEL << EXT_REG_OFFSET_SHIFT))) 231 #define PAD15_FUNC_SEL_UART_TXD ((uint32_t) (0x03)) 232 #define PAD15_FUNC_SEL_DEBUG_MON_8 ((uint32_t) (0x03)) 233 #define PAD15_FUNC_SEL_IRDA_SIRIN ((uint32_t) (0x00 | (IRDA_SIRIN_SEL << EXT_REG_OFFSET_SHIFT))) 234 #define PAD15_FUNC_SEL_SENS_INT_6 ((uint32_t) (0x00 | (S_INTR_6_SEL << EXT_REG_OFFSET_SHIFT))) 235 236 #define PAD16_FUNC_SEL_FBIO_16 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 237 #define PAD16_FUNC_SEL_SPIs_CLK ((uint32_t) (0x00 | (SPIs_CLK_SEL << EXT_REG_OFFSET_SHIFT))) 238 #define PAD16_FUNC_SEL_UART_RXD ((uint32_t) (0x00 | (UART_RXD_SEL << EXT_REG_OFFSET_SHIFT))) 239 240 #define PAD17_FUNC_SEL_SPIs_MISO ((uint32_t) (0x00)) 241 #define PAD17_FUNC_SEL_FBIO_17 ((uint32_t) (0x01 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 242 #define PAD17_FUNC_SEL_nUARTCTS ((uint32_t) (0x00 | (nUARTCTS_SEL << EXT_REG_OFFSET_SHIFT))) 243 244 #define PAD18_FUNC_SEL_FBIO_18 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 245 #define PAD18_FUNC_SEL_SWV ((uint32_t) (0x01)) 246 #define PAD18_FUNC_SEL_DEBUG_MON_0 ((uint32_t) (0x02)) 247 #define PAD18_FUNC_SEL_GPIO_4 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 248 #define PAD18_FUNC_SEL_SENS_INT_1 ((uint32_t) (0x00 | (S_INTR_1_SEL << EXT_REG_OFFSET_SHIFT))) 249 250 #define PAD19_FUNC_SEL_FBIO_19 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 251 #define PAD19_FUNC_SEL_UART_TXD ((uint32_t) (0x02)) 252 #define PAD19_FUNC_SEL_SPIs_MOSI ((uint32_t) (0x00 | (SPIs_MOSI_SEL << EXT_REG_OFFSET_SHIFT))) 253 254 #define PAD20_FUNC_SEL_FBIO_20 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 255 #define PAD20_FUNC_SEL_UART_TXD ((uint32_t) (0x01)) 256 #define PAD20_FUNC_SEL_SPIs_SSn ((uint32_t) (0x00 | (SPIs_SSn_SEL << EXT_REG_OFFSET_SHIFT))) 257 258 #define PAD21_FUNC_SEL_FBIO_21 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 259 #define PAD21_FUNC_SEL_nUARTRTS ((uint32_t) (0x01)) 260 #define PAD21_FUNC_SEL_DEBUG_MON_1 ((uint32_t) (0x02)) 261 #define PAD21_FUNC_SEL_GPIO_5 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 262 #define PAD21_FUNC_SEL_IRDA_SIRIN ((uint32_t) (0x00 | (IRDA_SIRIN_SEL << EXT_REG_OFFSET_SHIFT))) 263 #define PAD21_FUNC_SEL_SENS_INT_2 ((uint32_t) (0x00 | (S_INTR_2_SEL << EXT_REG_OFFSET_SHIFT))) 264 265 #define PAD22_FUNC_SEL_FBIO_22 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 266 #define PAD22_FUNC_SEL_IRDA_SIROUT ((uint32_t) (0x01)) 267 #define PAD22_FUNC_SEL_DEBUG_MON_2 ((uint32_t) (0x02)) 268 #define PAD22_FUNC_SEL_GPIO_6 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 269 #define PAD22_FUNC_SEL_nUARTCTS ((uint32_t) (0x00 | (nUARTCTS_SEL << EXT_REG_OFFSET_SHIFT))) 270 #define PAD22_FUNC_SEL_SENS_INT_3 ((uint32_t) (0x00 | (S_INTR_3_SEL << EXT_REG_OFFSET_SHIFT))) 271 272 #define PAD23_FUNC_SEL_FBIO_23 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 273 #define PAD23_FUNC_SEL_SPIm_SSn2 ((uint32_t) (0x01)) 274 #define PAD23_FUNC_SEL_SWV ((uint32_t) (0x02)) 275 #define PAD23_FUNC_SEL_GPIO_7 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 276 #define PAD23_FUNC_SEL_AP_I2S_WD_CLK_IN ((uint32_t) (0x00 | (I2S_WD_CLKIN_SEL << EXT_REG_OFFSET_SHIFT))) 277 #define PAD23_FUNC_SEL_SENS_INT_7 ((uint32_t) (0x00 | (S_INTR_7_SEL << EXT_REG_OFFSET_SHIFT))) 278 279 #define PAD24_FUNC_SEL_FBIO_24 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 280 #define PAD24_FUNC_SEL_AP_I2S_DOUT ((uint32_t) (0x01)) 281 #define PAD24_FUNC_SEL_UART_TXD ((uint32_t) (0x02)) 282 #define PAD24_FUNC_SEL_GPIO_0 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 283 #define PAD24_FUNC_SEL_IRDA_SIRIN ((uint32_t) (0x00 | (IRDA_SIRIN_SEL << EXT_REG_OFFSET_SHIFT))) 284 #define PAD24_FUNC_SEL_SENS_INT_1 ((uint32_t) (0x00 | (S_INTR_1_SEL << EXT_REG_OFFSET_SHIFT))) 285 286 #define PAD25_FUNC_SEL_FBIO_25 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 287 #define PAD25_FUNC_SEL_SPIm_SSN3 ((uint32_t) (0x01)) 288 #define PAD25_FUNC_SEL_SWV ((uint32_t) (0x02)) 289 #define PAD25_FUNC_SEL_IRDA_SIROUT ((uint32_t) (0x03)) 290 #define PAD25_FUNC_SEL_UART_RXD ((uint32_t) (0x00 | (UART_RXD_SEL << EXT_REG_OFFSET_SHIFT))) 291 #define PAD25_FUNC_SEL_SENS_INT_2 ((uint32_t) (0x00 | (S_INTR_2_SEL << EXT_REG_OFFSET_SHIFT))) 292 293 #define PAD26_FUNC_SEL_FBIO_26 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 294 #define PAD26_FUNC_SEL_SPI_SENSOR_SSn_4 ((uint32_t) (0x01)) 295 #define PAD26_FUNC_SEL_DEBUG_MON_3 ((uint32_t) (0x02)) 296 #define PAD26_FUNC_SEL_GPIO_1 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 297 #define PAD26_FUNC_SEL_SENS_INT_4 ((uint32_t) (0x00 | (S_INTR_4_SEL << EXT_REG_OFFSET_SHIFT))) 298 299 #define PAD27_FUNC_SEL_FBIO_27 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 300 #define PAD27_FUNC_SEL_SPI_SENSOR_SSn_5 ((uint32_t) (0x01)) 301 #define PAD27_FUNC_SEL_DEBUG_MON_4 ((uint32_t) (0x02)) 302 #define PAD27_FUNC_SEL_SPIm_SSn2 ((uint32_t) (0x03)) 303 #define PAD27_FUNC_SEL_SPIm_SSN2 (PAD27_FUNC_SEL_SPIm_SSn_2) //deprecated 304 #define PAD27_FUNC_SEL_SENS_INT_5 ((uint32_t) (0x00 | (S_INTR_5_SEL << EXT_REG_OFFSET_SHIFT))) 305 306 #define PAD28_FUNC_SEL_FBIO_28 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 307 #define PAD28_FUNC_SEL_SPI_SENSOR_MOSI ((uint32_t) (0x01 | (SPI_SENSOR_MOSI_SEL << EXT_REG_OFFSET_SHIFT))) 308 #define PAD28_FUNC_SEL_DEBUG_MON_5 ((uint32_t) (0x02)) 309 #define PAD28_FUNC_SEL_GPIO_2 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 310 #define PAD28_FUNC_SEL_I2S_DIN ((uint32_t) (0x00 | (I2S_DATA_SEL << EXT_REG_OFFSET_SHIFT))) 311 #define PAD28_FUNC_SEL_PDM_DIN ((uint32_t) (0x00 | (PDM_DATA_SEL << EXT_REG_OFFSET_SHIFT))) 312 #define PAD28_FUNC_SEL_IRDA_SIRIN ((uint32_t) (0x00 | (IRDA_SIRIN_SEL << EXT_REG_OFFSET_SHIFT))) 313 #define PAD28_FUNC_SEL_SENS_INT_3 ((uint32_t) (0x00 | (S_INTR_3_SEL << EXT_REG_OFFSET_SHIFT))) 314 315 #define PAD29_FUNC_SEL_FBIO_29 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 316 #define PAD29_FUNC_SEL_PDM_CKO ((uint32_t) (0x01)) 317 #define PAD29_FUNC_SEL_I2S_CKO ((uint32_t) (0x02)) 318 #define PAD29_FUNC_SEL_IRDA_SIROUT ((uint32_t) (0x03)) 319 #define PAD29_FUNC_SEL_SPI_SENSOR_MISO ((uint32_t) (0x00 | (SPI_SENSOR_MISO_SEL << EXT_REG_OFFSET_SHIFT))) 320 #define PAD29_FUNC_SEL_SENS_INT_4 ((uint32_t) (0x00 | (S_INTR_4_SEL << EXT_REG_OFFSET_SHIFT))) 321 322 #define PAD30_FUNC_SEL_FBIO_30 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 323 #define PAD30_FUNC_SEL_SPI_SENSOR_SSn_1 ((uint32_t) (0x01)) 324 #define PAD30_FUNC_SEL_I2S_WD_CKO ((uint32_t) (0x02)) 325 #define PAD30_FUNC_SEL_GPIO_3 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 326 #define PAD30_FUNC_SEL_PDM_STAT_IN ((uint32_t) (0x00 | (PDM_STAT_IN_SEL << EXT_REG_OFFSET_SHIFT))) 327 #define PAD30_FUNC_SEL_SENS_INT_5 ((uint32_t) (0x00 | (S_INTR_5_SEL << EXT_REG_OFFSET_SHIFT))) 328 329 #define PAD31_FUNC_SEL_FBIO_31 ((uint32_t) (0x00 | (FBIO_SEL_1 << EXT_REG_OFFSET_SHIFT))) 330 #define PAD31_FUNC_SEL_SPI_SENSOR_CLK ((uint32_t) (0x01)) 331 #define PAD31_FUNC_SEL_RESERVE ((uint32_t) (0x02)) 332 #define PAD31_FUNC_SEL_GPIO_4 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 333 #define PAD31_FUNC_SEL_AP_I2S_CLK_IN ((uint32_t) (0x00 | (I2S_CLKIN_SEL << EXT_REG_OFFSET_SHIFT))) 334 #define PAD31_FUNC_SEL_SENS_INT_6 ((uint32_t) (0x00 | (S_INTR_6_SEL << EXT_REG_OFFSET_SHIFT))) 335 336 #define PAD32_FUNC_SEL_FBIO_32 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 337 #define PAD32_FUNC_SEL_SPI_SENSOR_SSn_5 ((uint32_t) (0x01)) 338 #define PAD32_FUNC_SEL_DEBUG_MON_6 ((uint32_t) (0x02)) 339 #define PAD32_FUNC_SEL_SDA_1 ((uint32_t) (0x03 | (SDA1_SEL << EXT_REG_OFFSET_SHIFT))) 340 #define PAD32_FUNC_SEL_SENS_INT_6 ((uint32_t) (0x00 | (S_INTR_6_SEL << EXT_REG_OFFSET_SHIFT))) 341 342 #define PAD33_FUNC_SEL_FBIO_33 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 343 #define PAD33_FUNC_SEL_SPI_SENSOR_SSn_6 ((uint32_t) (0x01)) 344 #define PAD33_FUNC_SEL_DEBUG_MON_7 ((uint32_t) (0x02)) 345 #define PAD33_FUNC_SEL_SCL_1 ((uint32_t) (0x03 | (SCL1_SEL << EXT_REG_OFFSET_SHIFT))) 346 #define PAD33_FUNC_SEL_SENS_INT_7 ((uint32_t) (0x00 | (S_INTR_7_SEL << EXT_REG_OFFSET_SHIFT))) 347 348 #define PAD34_FUNC_SEL_SPIm_CLK ((uint32_t) (0x00)) 349 #define PAD34_FUNC_SEL_FBIO_34 ((uint32_t) (0x01 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 350 #define PAD34_FUNC_SEL_AP_PDM_STAT_O ((uint32_t) (0x02 | (PDM_STAT_IN_SEL << EXT_REG_OFFSET_SHIFT))) 351 #define PAD34_FUNC_SEL_DEBUG_MON_0 ((uint32_t) (0x03)) 352 #define PAD34_FUNC_SEL_SENS_INT_7 ((uint32_t) (0x00 | (S_INTR_7_SEL << EXT_REG_OFFSET_SHIFT))) 353 354 #define PAD35_FUNC_SEL_FBIO_35 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 355 #define PAD35_FUNC_SEL_SPIm_SSn3 ((uint32_t) (0x01)) 356 #define PAD35_FUNC_SEL_SPIm_SSN3 ((uint32_t) (0x01)) // Deprecated 357 #define PAD35_FUNC_SEL_SPI_SENSOR_SSn_7 ((uint32_t) (0x02)) 358 #define PAD35_FUNC_SEL_DEBUG_MON_1 ((uint32_t) (0x03)) 359 #define PAD36_FUNC_SEL_SENS_INT_1 ((uint32_t) (0x00 | (S_INTR_1_SEL << EXT_REG_OFFSET_SHIFT))) 360 361 #define PAD36_FUNC_SEL_FBIO_36 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 362 #define PAD36_FUNC_SEL_SWV ((uint32_t) (0x01)) 363 #define PAD36_FUNC_SEL_SPI_SENSOR_SSn_2 ((uint32_t) (0x02)) 364 #define PAD36_FUNC_SEL_GPIO_5 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 365 #define PAD36_FUNC_SEL_SPIm_MISO ((uint32_t) (0x00 | (SPIm_MISO_SEL << EXT_REG_OFFSET_SHIFT))) 366 #define PAD36_FUNC_SEL_SENS_INT_1 ((uint32_t) (0x00 | (S_INTR_1_SEL << EXT_REG_OFFSET_SHIFT))) 367 368 #define PAD37_FUNC_SEL_FBIO_37 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 369 #define PAD37_FUNC_SEL_SDA_2_DPU ((uint32_t) (0x01)) 370 #define PAD37_FUNC_SEL_SPI_SENSOR_SSn_8 ((uint32_t) (0x02)) 371 #define PAD37_FUNC_SEL_DEBUG_MON_2 ((uint32_t) (0x03)) 372 #define PAD37_FUNC_SEL_SENS_INT_2 ((uint32_t) (0x00 | (S_INTR_2_SEL << EXT_REG_OFFSET_SHIFT))) 373 374 #define PAD38_FUNC_SEL_SPIm_MOSI ((uint32_t) (0x00)) 375 #define PAD38_FUNC_SEL_FBIO_38 ((uint32_t) (0x01 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 376 #define PAD38_FUNC_SEL_DEBUG_MON_3 ((uint32_t) (0x02)) 377 #define PAD38_FUNC_SEL_GPIO_6 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 378 #define PAD38_FUNC_SEL_AP_PDM_CKO_IN ((uint32_t) (0x00)) 379 #define PAD38_FUNC_SEL_SENS_INT_2 ((uint32_t) (0x00 | (S_INTR_2_SEL << EXT_REG_OFFSET_SHIFT))) 380 381 #define PAD39_FUNC_SEL_SPIm_SSn1 ((uint32_t) (0x00)) 382 #define PAD39_FUNC_SEL_FBIO_39 ((uint32_t) (0x01 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 383 #define PAD39_FUNC_SEL_AP_PDM_IO ((uint32_t) (0x02)) 384 #define PAD39_FUNC_SEL_DEBUG_MON_4 ((uint32_t) (0x03)) 385 #define PAD39_FUNC_SEL_SENS_INT_3 ((uint32_t) (0x00 | (S_INTR_3_SEL << EXT_REG_OFFSET_SHIFT))) 386 387 #define PAD40_FUNC_SEL_FBIO_40 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 388 #define PAD40_FUNC_SEL_SCL_2 ((uint32_t) (0x01 | (SCL2_SEL << EXT_REG_OFFSET_SHIFT))) 389 #define PAD40_FUNC_SEL_DEBUG_MON_5 ((uint32_t) (0x02)) 390 #define PAD40_FUNC_SEL_RESERVED ((uint32_t) (0x03)) 391 #define PAD40_FUNC_SEL_IRDA_SIRIN ((uint32_t) (0x00 | (IRDA_SIRIN_SEL << EXT_REG_OFFSET_SHIFT))) 392 #define PAD40_FUNC_SEL_SENS_INT_3 ((uint32_t) (0x00 | (S_INTR_3_SEL << EXT_REG_OFFSET_SHIFT))) 393 394 #define PAD41_FUNC_SEL_FBIO_41 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 395 #define PAD41_FUNC_SEL_SDA_2 ((uint32_t) (0x01 | (SDA2_SEL << EXT_REG_OFFSET_SHIFT))) 396 #define PAD41_FUNC_SEL_DEBUG_MON_6 ((uint32_t) (0x02)) 397 #define PAD41_FUNC_SEL_IRDA_SIROUT ((uint32_t) (0x03)) 398 #define PAD41_FUNC_SEL_SENS_INT_6 ((uint32_t) (0x00 | (S_INTR_6_SEL << EXT_REG_OFFSET_SHIFT))) 399 400 #define PAD42_FUNC_SEL_FBIO_42 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 401 #define PAD42_FUNC_SEL_SWV ((uint32_t) (0x01)) 402 #define PAD42_FUNC_SEL_DEBUG_MON_7 ((uint32_t) (0x02)) 403 #define PAD42_FUNC_SEL_SDA_1_DPU ((uint32_t) (0x03)) 404 #define PAD42_FUNC_SEL_SENS_INT_7 ((uint32_t) (0x00 | (S_INTR_7_SEL << EXT_REG_OFFSET_SHIFT))) 405 406 #define PAD43_FUNC_SEL_AP_INTR ((uint32_t) (0x00)) 407 #define PAD43_FUNC_SEL_FBIO_43 ((uint32_t) (0x01 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 408 409 #define PAD44_FUNC_SEL_SW_DP_IO ((uint32_t) (0x00)) 410 #define PAD44_FUNC_SEL_FBIO_44 ((uint32_t) (0x01 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 411 #define PAD44_FUNC_SEL_SDA_1 ((uint32_t) (0x02 | (SDA1_SEL << EXT_REG_OFFSET_SHIFT))) 412 #define PAD44_FUNC_SEL_UART_TXD ((uint32_t) (0x03)) 413 #define PAD44_FUNC_SEL_IRDA_SIRIN ((uint32_t) (0x00 | (IRDA_SIRIN_SEL << EXT_REG_OFFSET_SHIFT))) 414 #define PAD44_FUNC_SEL_SENS_INT_4 ((uint32_t) (0x00 | (S_INTR_4_SEL << EXT_REG_OFFSET_SHIFT))) 415 416 #define PAD45_FUNC_SEL_FBIO_45 ((uint32_t) (0x00 | (FBIO_SEL_2 << EXT_REG_OFFSET_SHIFT))) 417 #define PAD45_FUNC_SEL_IRDA_SIROUT ((uint32_t) (0x01)) 418 #define PAD45_FUNC_SEL_SCL_1 ((uint32_t) (0x02 | (SCL1_SEL << EXT_REG_OFFSET_SHIFT))) 419 #define PAD45_FUNC_SEL_GPIO_7 ((uint32_t) (0x03 | (IO_REG_SEL << EXT_REG_OFFSET_SHIFT))) 420 #define PAD45_FUNC_SEL_SW_DP_CLK ((uint32_t) (0x00)) 421 #define PAD45_FUNC_SEL_UART_RXD ((uint32_t) (0x00 | (UART_RXD_SEL << EXT_REG_OFFSET_SHIFT))) 422 #define PAD45_FUNC_SEL_SENS_INT_5 ((uint32_t) (0x00 | (S_INTR_5_SEL << EXT_REG_OFFSET_SHIFT))) 423 424 /// @endcond 425 #ifdef __cplusplus 426 } 427 #endif 428 429 #endif /* __EOSS3_HAL_PADS_H */ 430
