1 /* 2 * ========================================================== 3 * 4 * Copyright (C) 2020 QuickLogic Corporation 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * File : s3x_clock_hal.h 16 * Purpose : 17 * 18 * 19 * =========================================================== 20 * 21 */ 22 23 #ifndef __S3X_CLOCK_HAL_H 24 #define __S3X_CLOCK_HAL_H 25 26 27 #include "eoss3_dev.h" 28 #include "test_types.h" 29 #define MHZ 1000000 30 #define KHZ 1000 31 32 33 typedef enum 34 { 35 /*C01 clk gate*/ 36 S3X_A0_01_CLK, // 0 to A0 ********** A0 from C08 also. Need to check ****************** 37 S3X_SDMA_SRAM_CLK, // 1 to SDMA SRAM 38 S3X_PKT_FIFO_CLK, // 2 to Packet FIFO 39 S3X_FFE_CLK, // 3 to FFE 40 S3X_CFG_DMA_A1_CLK, // 4 to CFG DMA Bridge inside A1 / AHB2APB bridge 41 S3X_I2S_A1_CLK, // 5 to I2S module inside A1 42 S3X_SDMA_CLK, // 6 to SDMA 43 S3X_EFUSE_01_CLK, // 7 to eFuse *********** eFUSE from C02 also. Need to check*************** 44 S3X_SPT_CLK, // 8 to SPT 45 46 47 /*C02 clk gate*/ 48 S3X_A1_CLK, // 9 to A1 including CFGSM 49 S3X_FB_02_CLK, // 10 to FB *********** FB from C16 also. Need to check****************** 50 S3X_EFUSE_02_CLK, // 11 to eFuse *********** eFUSE from C01 also. Need to check*************** 51 52 53 /*C08 X4 clk gate*/ 54 S3X_FFE_X4_CLK, // 12 to FFE X4 clk 55 56 /*C08 X1 clk gate*/ 57 S3X_FFE_X1_CLK, // 13 to FFE X1 clk 58 S3X_A0_08_CLK, // 14 to A0 ********** A0 from C01 also. Need to check ****************** 59 S3X_ASYNC_FIFO_0_CLK, // 15 to PF ASYNC FIFO 0 60 61 /*C9 Clk Gate */ 62 S3X_AUDIO_APB, // 16 63 S3X_CLKGATE_PIF, // 17 64 S3X_CLKGATE_FB, //18 65 /*C10 clk gate*/ 66 /*TODO : Check for S3X_M4_BM_TB_CLK. Current status - Not handled*/ 67 S3X_M4_BM_TB_CLK, // 19 to M4 Bus Matrix and Trace block 68 // This bit will be set if any of the Memories (M4S0~M4S3)been wakeup by Hardware. 69 S3X_M4_S0_S3_CLK,// 20 to M4 SRAM Instance, M4S0~M4S3. 70 S3X_M4_S4_S7_CLK,// 21 to M4 SRAM Instance, M4S4~M4S7 71 S3X_M4_S8_S11_CLK,// 22 to M4 SRAM Instance, M4S8~M4S11 72 S3X_M4_S12_S15_CLK,// 23 to M4 SRAM Instance, M4S12~M4S15 73 S3X_AUDIO_DMA_CLK,// 24 to AUDIO DMA 74 S3X_SYNCUP_A0_AHB_CLK,// 25 to the SYNC Up on A0 and AHB Interface of Batching Memory 75 76 /*C11 clk gate*/ 77 S3X_M4_PRPHRL_CLK,// 26 to M4 peripherals - AHB/APB bridge, UART, WDT and TIMER 78 79 /*CS clk gate*/ 80 S3X_SWD_PIN_CLK, // 27 to SWD Clk from PIN 81 82 /*C16 clk gate*/ 83 S3X_FB_16_CLK, // 28 to FB *********** FB from C02 also. Need to check****************** 84 85 /*CLK reserved 0*/ 86 87 /*C19 clk gate*/ 88 S3X_ADC_CLK,// 29 To ADC 89 90 /*C21 clk gate*/ 91 S3X_FB_21_CLK, // 30 To FB(additional clock) ********** FB from C16 also. Need to check****************** 92 93 /* C30 C31 */ 94 S3X_PDM_LEFT, //31 95 S3X_PDM_RIGHT, //32 96 S3X_PDM_STEREO, //33 97 S3X_I2S_MASTER, //34 98 S3X_LPSD, //35 99 S3X_MAX_CLK //36 100 }S3x_CLK_ID; 101 #define MAX_QOS_REQ 3 102 typedef enum { 103 MIN_HSOSC_FREQ = 0x1, 104 MIN_CPU_FREQ = 0x2, 105 MIN_OP_FREQ = 0x4, 106 OP_REQ_END = 0x4 107 } QOS_REQ_TYPE; 108 109 /*To enable clock. Pass the clock ID as defined in the enum S3x_CLK_ID*/ 110 int S3x_Clk_Enable(UINT32_t clk_id); 111 112 /*To disable clock. Pass the clock ID as defined in the enum S3x_CLK_ID*/ 113 int S3x_Clk_Disable(UINT32_t clk_id); 114 115 /*To set clock rate. Pass the cloack ID and the desired rate*/ 116 int S3x_Clk_Set_Rate(UINT32_t clk_id, UINT32_t rate); 117 118 /**To set clock rate. Pass the clock ID and the desired range of rate (min and max rate value)*/ 119 //int S3x_Clk_Set_Rate(UINT32_t clk_id, UINT32_t rate_min, UINT32_t rate_max); 120 121 /*To get the rate for the corresponding clock ID. Pass the clock ID as defined in the enum S3x_CLK_ID*/ 122 int S3x_Clk_Get_Rate(UINT32_t clk_id); 123 124 /*To get Status for the clock*/ 125 int S3x_Clk_Get_Status(UINT32_t clk_id); 126 127 /*To get the use count for the clock ID (gate)*/ 128 int S3x_Clk_Get_Usecnt(UINT32_t clk_id); 129 130 int S3x_Register_Qos_Node(UINT32_t clk_id); 131 132 int S3x_Set_Qos_Req(UINT32_t clk_id, QOS_REQ_TYPE, UINT32_t val); 133 134 int S3x_Get_Qos_Req(UINT32_t clk_id, QOS_REQ_TYPE req); 135 136 int S3x_Clear_Qos_Req(UINT32_t clk_id, QOS_REQ_TYPE); 137 138 #endif /* __S3X_CLOCK_HAL_H */ 139
