| /hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/ |
| D | fsl_trng.c | 99 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCM… argument
126 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) argument
127 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (valu… argument
142 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_… argument
157 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_… argument
186 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) argument
187 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (v… argument
204 …define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SC… argument
220 …define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SC… argument
249 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) argument
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| D | fsl_flash.c | 2001 …us_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) in FLASH_GetProperty() argument
2003 if ((config == NULL) || (value == NULL)) in FLASH_GetProperty()
2011 *value = config->PFlashSectorSize; in FLASH_GetProperty()
2015 *value = config->PFlashTotalSize; in FLASH_GetProperty()
2019 *value = config->PFlashTotalSize / (uint32_t)config->PFlashBlockCount; in FLASH_GetProperty()
2023 *value = (uint32_t)config->PFlashBlockCount; in FLASH_GetProperty()
2027 *value = config->PFlashBlockBase; in FLASH_GetProperty()
2032 *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; in FLASH_GetProperty()
2034 *value = 0; in FLASH_GetProperty()
2039 *value = config->PFlashAccessSegmentSize; in FLASH_GetProperty()
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| D | fsl_lpi2c.c | 331 uint32_t value; in LPI2C_MasterInit() local
353 value = base->MCFGR0; in LPI2C_MasterInit()
354 value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK)); in LPI2C_MasterInit()
355 value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) | in LPI2C_MasterInit()
358 base->MCFGR0 = value; in LPI2C_MasterInit()
361 value = base->MCFGR1; in LPI2C_MasterInit()
362 value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); in LPI2C_MasterInit()
363 value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig); in LPI2C_MasterInit()
364 value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck); in LPI2C_MasterInit()
365 base->MCFGR1 = value; in LPI2C_MasterInit()
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| D | fsl_spm.h | 773 void SPM_BypassDcdcBattMonitor(SPM_Type *base, bool enable, uint32_t value);
806 static inline void SPM_SetDcdcVdd1p2ValueHsrun(SPM_Type *base, uint32_t value) in SPM_SetDcdcVdd1p2ValueHsrun() argument
808 …se->DCDCC6 = (base->DCDCC6 & ~SPM_DCDCC6_DCDC_HSVDD_TRIM_MASK) | SPM_DCDCC6_DCDC_HSVDD_TRIM(value); in SPM_SetDcdcVdd1p2ValueHsrun()
819 static inline void SPM_SetDcdcVdd1p2ValueBuck(SPM_Type *base, uint32_t value) in SPM_SetDcdcVdd1p2ValueBuck() argument
822 …->DCDCC6 & ~SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK_MASK) | SPM_DCDCC6_DCDC_VDD1P2CTRL_TRG_BUCK(value); in SPM_SetDcdcVdd1p2ValueBuck()
833 static inline void SPM_SetDcdcVdd1p8Value(SPM_Type *base, uint32_t value) in SPM_SetDcdcVdd1p8Value() argument
835 …C6 = (base->DCDCC6 & ~SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG_MASK) | SPM_DCDCC6_DCDC_VDD1P8CTRL_TRG(value); in SPM_SetDcdcVdd1p8Value()
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| D | fsl_ewm.c | 19 uint32_t value = 0U; in EWM_Init() local
27 value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | in EWM_Init()
39 base->CTRL = value; in EWM_Init()
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| D | fsl_wdog32.c | 45 uint32_t value = 0U; in WDOG32_Init() local
48 …value = WDOG_CS_EN(config->enableWdog32) | WDOG_CS_CLK(config->clockSource) | WDOG_CS_INT(config->… in WDOG32_Init()
60 base->CS = value; in WDOG32_Init()
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| D | fsl_lptmr.c | 90 base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | in LPTMR_Init()
131 config->value = kLPTMR_Prescale_Glitch_0; in LPTMR_GetDefaultConfig()
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| D | fsl_dac.h | 332 static inline void DAC_SetData(LPDAC_Type *base, uint32_t value) in DAC_SetData() argument
334 base->DATA = LPDAC_DATA_DATA(value); in DAC_SetData()
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| D | fsl_spm.c | 145 void SPM_BypassDcdcBattMonitor(SPM_Type *base, bool enable, uint32_t value) in SPM_BypassDcdcBattMonitor() argument
150 …se->DCDCC3 = (base->DCDCC3 & ~SPM_DCDCC3_DCDC_VBAT_VALUE_MASK) | SPM_DCDCC3_DCDC_VBAT_VALUE(value); in SPM_BypassDcdcBattMonitor()
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| D | fsl_lpadc.h | 579 static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) in LPADC_SetOffsetValue() argument
581 base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; in LPADC_SetOffsetValue()
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| D | fsl_flash.h | 1070 …s_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
1086 …us_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value);
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| D | fsl_lptmr.h | 113 lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ member
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| /hal_openisa-latest/vega_sdk_riscv/RISCV/ |
| D | core_riscv32.h | 92 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) in __REV() argument
94 return __builtin_bswap32(value); in __REV()
97 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) in __REV16() argument
99 return __builtin_bswap16(value); in __REV16()
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| /hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/ |
| D | RV32M1_ri5cy.h | 23993 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) argument
24000 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) argument
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| D | RV32M1_zero_riscy.h | 32643 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) argument
32650 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) argument
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