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Searched refs:temp (Results 1 – 5 of 5) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c602 uint32_t temp; in XCVR_Configure() local
635 temp = XCVR_ANA->TX_DAC_PA; in XCVR_Configure()
636 temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK; in XCVR_Configure()
637 temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4); in XCVR_Configure()
638 XCVR_ANA->TX_DAC_PA = temp; in XCVR_Configure()
640 temp = XCVR_ANA->BB_LDO_2; in XCVR_Configure()
641 temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK; in XCVR_Configure()
642 temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0); in XCVR_Configure()
643 XCVR_ANA->BB_LDO_2 = temp; in XCVR_Configure()
645 temp = XCVR_ANA->RX_LNA; in XCVR_Configure()
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Ddbg_ram_capture.c93 uint32_t temp; in unpack_sequential_data() local
116 temp = XCVR_MISC->PACKET_RAM_CTRL; in unpack_sequential_data()
117 temp &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MASK; in unpack_sequential_data()
118 temp |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE(pkt_ram_number); in unpack_sequential_data()
119 XCVR_MISC->PACKET_RAM_CTRL = temp; in unpack_sequential_data()
187 uint32_t temp; in dbg_ram_set_trigger() local
201 temp = XCVR_MISC->PACKET_RAM_CTRL; in dbg_ram_set_trigger()
202temp &= ~(XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG_MASK | XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_TRG_MA… in dbg_ram_set_trigger()
203temp |= XCVR_CTRL_PACKET_RAM_CTRL_DBG_START_TRG(start_trig) | XCVR_CTRL_PACKET_RAM_CTRL_DBG_STOP_T… in dbg_ram_set_trigger()
204 XCVR_MISC->PACKET_RAM_CTRL = temp; in dbg_ram_set_trigger()
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Dfsl_xcvr_trim.c366 uint32_t temp, end_of_rx_wu; in rx_dc_sample_average() local
383 temp = XCVR_TSM->END_OF_SEQ; in rx_dc_sample_average()
384 …end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_… in rx_dc_sample_average()
438 uint32_t temp, end_of_rx_wu; in rx_dc_sample_average_long() local
455 temp = XCVR_TSM->END_OF_SEQ; in rx_dc_sample_average_long()
456 …end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_… in rx_dc_sample_average_long()
507 static uint32_t dc_temp, temp; in rx_dc_est_average() local
513 temp = XCVR_TSM->END_OF_SEQ; in rx_dc_est_average()
514 …end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_… in rx_dc_est_average()
522 temp = dc_meas_i; in rx_dc_est_average()
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/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpuart.c220 uint32_t temp; in LPUART_Init() local
290 temp = base->BAUD; in LPUART_Init()
296 temp |= LPUART_BAUD_BOTHEDGE_MASK; in LPUART_Init()
300 temp &= ~LPUART_BAUD_OSR_MASK; in LPUART_Init()
301 temp |= LPUART_BAUD_OSR(osr - 1); in LPUART_Init()
304 temp &= ~LPUART_BAUD_SBR_MASK; in LPUART_Init()
305 base->BAUD = temp | LPUART_BAUD_SBR(sbr); in LPUART_Init()
310 temp = base->CTRL & in LPUART_Init()
314 temp |= in LPUART_Init()
322 temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ in LPUART_Init()
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Dfsl_mmdvsq.c17 uint32_t temp = 0; in MMDVSQ_GetDivideRemainder() local
19 temp = base->CSR; in MMDVSQ_GetDivideRemainder()
20 temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK); in MMDVSQ_GetDivideRemainder()
22 temp |= MMDVSQ_CSR_USGN(isUnsigned) | MMDVSQ_CSR_REM(true); in MMDVSQ_GetDivideRemainder()
24 base->CSR = temp; in MMDVSQ_GetDivideRemainder()
38 uint32_t temp = 0; in MMDVSQ_GetDivideQuotient() local
40 temp = base->CSR; in MMDVSQ_GetDivideQuotient()
41 temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK); in MMDVSQ_GetDivideQuotient()
43 temp |= MMDVSQ_CSR_USGN(isUnsigned) | MMDVSQ_CSR_REM(false); in MMDVSQ_GetDivideQuotient()
45 base->CSR = temp; in MMDVSQ_GetDivideQuotient()