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Searched refs:reg (Results 1 – 16 of 16) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_msmc.c21 uint32_t reg; in SMC_SetPowerModeRun() local
23 reg = base->PMCTRL; in SMC_SetPowerModeRun()
25 reg &= ~SMC_PMCTRL_RUNM_MASK; in SMC_SetPowerModeRun()
26 reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); in SMC_SetPowerModeRun()
27 base->PMCTRL = reg; in SMC_SetPowerModeRun()
34 uint32_t reg; in SMC_SetPowerModeHsrun() local
36 reg = base->PMCTRL; in SMC_SetPowerModeHsrun()
38 reg &= ~SMC_PMCTRL_RUNM_MASK; in SMC_SetPowerModeHsrun()
39 reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); in SMC_SetPowerModeHsrun()
40 base->PMCTRL = reg; in SMC_SetPowerModeHsrun()
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Dfsl_clock.h822 uint32_t reg = (*(volatile uint32_t *)name); in CLOCK_SetIpSrc() local
824 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrc()
825 …assert(!(reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by other co… in CLOCK_SetIpSrc()
827 reg = (reg & ~PCC_CLKCFG_PCS_MASK) | PCC_CLKCFG_PCS(src); in CLOCK_SetIpSrc()
833 (*(volatile uint32_t *)name) = reg & ~PCC_CLKCFG_CGC_MASK; in CLOCK_SetIpSrc()
834 (*(volatile uint32_t *)name) = reg; in CLOCK_SetIpSrc()
853 uint32_t reg = (*(volatile uint32_t *)name); in CLOCK_SetIpSrcDiv() local
855 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_SetIpSrcDiv()
856 …assert(!(reg & PCC_CLKCFG_INUSE_MASK)); /* Should not change if clock has been enabled by other co… in CLOCK_SetIpSrcDiv()
858 …reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS… in CLOCK_SetIpSrcDiv()
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Dfsl_mu.h256 uint32_t reg = base->CR; in MU_SetFlagsNonBlocking() local
257 reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_Fn_MASK)) | MU_CR_Fn(flags); in MU_SetFlagsNonBlocking()
258 base->CR = reg; in MU_SetFlagsNonBlocking()
399 uint32_t reg = base->CR; in MU_EnableInterrupts() local
400 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; in MU_EnableInterrupts()
401 base->CR = reg; in MU_EnableInterrupts()
420 uint32_t reg = base->CR; in MU_DisableInterrupts() local
421 reg &= ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | mask); in MU_DisableInterrupts()
422 base->CR = reg; in MU_DisableInterrupts()
493 uint32_t reg = base->CR; in MU_HoldCoreBReset()
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Dfsl_llwu.c17 uint32_t reg; in LLWU_SetExternalWakeupPinMode() local
36 uint8_t reg; in LLWU_SetExternalWakeupPinMode()
83 reg = *regBase; in LLWU_SetExternalWakeupPinMode()
89 reg &= ~(0x3U << regOffset); in LLWU_SetExternalWakeupPinMode()
90 reg |= ((uint32_t)pinMode << regOffset); in LLWU_SetExternalWakeupPinMode()
91 *regBase = reg; in LLWU_SetExternalWakeupPinMode()
303 uint32_t reg; in LLWU_ClearPinFilterFlag() local
305 reg = base->FILT; in LLWU_ClearPinFilterFlag()
309 reg |= LLWU_FILT_FILTF1_MASK; in LLWU_ClearPinFilterFlag()
313 reg |= LLWU_FILT_FILTF2_MASK; in LLWU_ClearPinFilterFlag()
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Dfsl_lptmr.h179 uint32_t reg = base->CSR; in LPTMR_EnableInterrupts() local
182 reg &= ~(LPTMR_CSR_TCF_MASK); in LPTMR_EnableInterrupts()
183 reg |= mask; in LPTMR_EnableInterrupts()
184 base->CSR = reg; in LPTMR_EnableInterrupts()
196 uint32_t reg = base->CSR; in LPTMR_DisableInterrupts() local
199 reg &= ~(LPTMR_CSR_TCF_MASK); in LPTMR_DisableInterrupts()
200 reg &= ~mask; in LPTMR_DisableInterrupts()
201 base->CSR = reg; in LPTMR_DisableInterrupts()
335 uint32_t reg = base->CSR; in LPTMR_StartTimer() local
338 reg &= ~(LPTMR_CSR_TCF_MASK); in LPTMR_StartTimer()
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Dfsl_tpm.c396 uint32_t reg = base->CONTROLS[chnlNumber].CnSC & ~(TPM_CnSC_CHF_MASK); in TPM_UpdateChnlEdgeLevelSelect() local
409 reg &= ~(TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); in TPM_UpdateChnlEdgeLevelSelect()
410 reg |= ((uint32_t)level << TPM_CnSC_ELSA_SHIFT) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); in TPM_UpdateChnlEdgeLevelSelect()
412 base->CONTROLS[chnlNumber].CnSC = reg; in TPM_UpdateChnlEdgeLevelSelect()
415 reg &= (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK); in TPM_UpdateChnlEdgeLevelSelect()
416 while (reg != (base->CONTROLS[chnlNumber].CnSC & in TPM_UpdateChnlEdgeLevelSelect()
519 uint32_t reg; in TPM_SetupDualEdgeCapture() local
560 reg = base->FILTER; in TPM_SetupDualEdgeCapture()
561 reg &= ~(TPM_FILTER_CH0FVAL_MASK << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); in TPM_SetupDualEdgeCapture()
562 reg |= (filterValue << (TPM_FILTER_CH1FVAL_SHIFT * (chnlPairNumber + 1))); in TPM_SetupDualEdgeCapture()
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Dfsl_xrdc.h635 uint32_t reg = base->PID[master]; in XRDC_SetPidLockMode() local
637 reg = ((reg & ~XRDC_PID_LK2_MASK) | XRDC_PID_LK2(lockMode)); in XRDC_SetPidLockMode()
639 base->PID[master] = reg; in XRDC_SetPidLockMode()
923 uint32_t reg = base->MRGD[mem].MRGD_W[3]; in XRDC_SetMemAccessLockMode() local
925 reg = ((reg & ~XRDC_MRGD_W_LK2_MASK) | XRDC_MRGD_W_LK2(lockMode)); in XRDC_SetMemAccessLockMode()
927 base->MRGD[mem].MRGD_W[3] = reg; in XRDC_SetMemAccessLockMode()
929 uint32_t reg = base->MRGD[mem].MRGD_W[4]; in XRDC_SetMemAccessLockMode()
931 reg = ((reg & ~XRDC_MRGD_W_LK2_MASK) | XRDC_MRGD_W_LK2(lockMode)); in XRDC_SetMemAccessLockMode()
933 base->MRGD[mem].MRGD_W[4] = reg; in XRDC_SetMemAccessLockMode()
1124 uint32_t reg = base->PDAC_W[periph][1]; in XRDC_SetPeriphAccessLockMode() local
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Dfsl_clock.c50 #define PCC_PCS_VAL(reg) ((reg & PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT) argument
51 #define PCC_FRAC_VAL(reg) ((reg & PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT) argument
52 #define PCC_PCD_VAL(reg) ((reg & PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT) argument
196 uint32_t reg = (*(volatile uint32_t *)name); in CLOCK_GetIpFreq() local
201 assert(reg & PCC_CLKCFG_PR_MASK); in CLOCK_GetIpFreq()
218 switch (PCC_PCS_VAL(reg)) in CLOCK_GetIpFreq()
237 if (0U != (reg & (PCC_CLKCFG_PCD_MASK | PCC_CLKCFG_FRAC_MASK))) in CLOCK_GetIpFreq()
239 return freq * (PCC_FRAC_VAL(reg) + 1U) / (PCC_PCD_VAL(reg) + 1U); in CLOCK_GetIpFreq()
361 uint32_t reg = SCG->SOSCCSR; in CLOCK_DeinitSysOsc() local
364 if (reg & SCG_SOSCCSR_SOSCSEL_MASK) in CLOCK_DeinitSysOsc()
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Dfsl_mu.c92 uint32_t reg = base->CR; in MU_TriggerInterrupts() local
95 if (!(reg & mask)) in MU_TriggerInterrupts()
98 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; in MU_TriggerInterrupts()
99 base->CR = reg; in MU_TriggerInterrupts()
116 uint32_t reg = base->CCR; in MU_BootCoreB() local
118 reg = (reg & ~(MU_CCR_HR_MASK | MU_CCR_RSTH_MASK | MU_CCR_BOOT_MASK)) | MU_CCR_BOOT(mode); in MU_BootCoreB()
120 base->CCR = reg; in MU_BootCoreB()
122 uint32_t reg = base->CR; in MU_BootCoreB() local
124 …reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_HR_MASK | MU_CR_RSTH_MASK | MU_CR_BBOOT_… in MU_BootCoreB()
126 base->CR = reg; in MU_BootCoreB()
Dfsl_rtc.c190 uint32_t reg; in RTC_Init() local
204 reg = base->CR; in RTC_Init()
206 reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); in RTC_Init()
207 reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); in RTC_Init()
210 reg &= ~(RTC_CR_WPS_MASK); in RTC_Init()
211 reg |= RTC_CR_WPS(config->wakeupSelect); in RTC_Init()
213 base->CR = reg; in RTC_Init()
Dfsl_rtc.h389 uint32_t reg = base->CR; in RTC_SetOscCapLoad() local
391 reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK); in RTC_SetOscCapLoad()
392 reg |= capLoad; in RTC_SetOscCapLoad()
394 base->CR = reg; in RTC_SetOscCapLoad()
Dfsl_tpm.h559 uint32_t reg = base->SC; in TPM_StartTimer() local
561 reg &= ~(TPM_SC_CMOD_MASK); in TPM_StartTimer()
562 reg |= TPM_SC_CMOD(clockSource); in TPM_StartTimer()
563 base->SC = reg; in TPM_StartTimer()
Dfsl_lpit.c117 uint32_t reg = 0; in LPIT_SetupChannel() local
126 reg = (LPIT_TCTRL_MODE(chnlSetup->timerMode) | LPIT_TCTRL_TRG_SRC(chnlSetup->triggerSource) | in LPIT_SetupChannel()
131 base->CHANNEL[channel].TCTRL = reg; in LPIT_SetupChannel()
Dfsl_cau3.c2193 static void cau3_pkha_write_word(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t index, uint32_t… in cau3_pkha_write_word() argument
2199 switch (reg) in cau3_pkha_write_word()
2222 static uint32_t cau3_pkha_read_word(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t index) in cau3_pkha_read_word() argument
2229 switch (reg) in cau3_pkha_read_word()
2251 CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t quad, const uint8_t *data, size_t dataSize) in cau3_pkha_write_reg() argument
2261 cau3_pkha_write_word(base, reg, startIndex++, cau3_get_word_from_unaligned(data)); in cau3_pkha_write_reg()
2269 cau3_pkha_write_word(base, reg, startIndex, outWord); in cau3_pkha_write_reg()
2277 static void cau3_pkha_read_reg(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t quad, uint8_t *da… in cau3_pkha_read_reg() argument
2286 word = cau3_pkha_read_word(base, reg, startIndex++); in cau3_pkha_read_reg()
2369 static void cau3_pkha_mode_set_src_reg_copy(cau3_mode_t *outMode, cau3_pkha_reg_area_t reg) in cau3_pkha_mode_set_src_reg_copy() argument
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Dfsl_cau3_ble.c2388 static void cau3_pkha_write_word(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t index, uint32_t… in cau3_pkha_write_word() argument
2394 switch (reg) in cau3_pkha_write_word()
2417 static uint32_t cau3_pkha_read_word(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t index) in cau3_pkha_read_word() argument
2424 switch (reg) in cau3_pkha_read_word()
2446 CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t quad, const uint8_t *data, size_t dataSize) in cau3_pkha_write_reg() argument
2456 cau3_pkha_write_word(base, reg, startIndex++, cau3_get_word_from_unaligned(data)); in cau3_pkha_write_reg()
2464 cau3_pkha_write_word(base, reg, startIndex, outWord); in cau3_pkha_write_reg()
2472 static void cau3_pkha_read_reg(CAU3_Type *base, cau3_pkha_reg_area_t reg, uint8_t quad, uint8_t *da… in cau3_pkha_read_reg() argument
2481 word = cau3_pkha_read_word(base, reg, startIndex++); in cau3_pkha_read_reg()
2564 static void cau3_pkha_mode_set_src_reg_copy(cau3_mode_t *outMode, cau3_pkha_reg_area_t reg) in cau3_pkha_mode_set_src_reg_copy() argument
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Dfsl_xrdc.c322 uint32_t reg = base->MRGD[mem].MRGD_W[4]; in XRDC_SetMemExclAccessLockMode() local
328 base->MRGD[mem].MRGD_W[4] = reg; in XRDC_SetMemExclAccessLockMode()