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Searched refs:mask (Results 1 – 25 of 49) sorted by relevance

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/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_rtc.c308 void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) in RTC_EnableInterrupts() argument
313 if (kRTC_TimeInvalidInterruptEnable == (kRTC_TimeInvalidInterruptEnable & mask)) in RTC_EnableInterrupts()
317 if (kRTC_TimeOverflowInterruptEnable == (kRTC_TimeOverflowInterruptEnable & mask)) in RTC_EnableInterrupts()
321 if (kRTC_AlarmInterruptEnable == (kRTC_AlarmInterruptEnable & mask)) in RTC_EnableInterrupts()
325 if (kRTC_SecondsInterruptEnable == (kRTC_SecondsInterruptEnable & mask)) in RTC_EnableInterrupts()
330 if (kRTC_MonotonicOverflowInterruptEnable == (kRTC_MonotonicOverflowInterruptEnable & mask)) in RTC_EnableInterrupts()
341 if (kRTC_TestModeInterruptEnable == (kRTC_TestModeInterruptEnable & mask)) in RTC_EnableInterrupts()
345 if (kRTC_FlashSecurityInterruptEnable == (kRTC_FlashSecurityInterruptEnable & mask)) in RTC_EnableInterrupts()
350 if (kRTC_TamperPinInterruptEnable == (kRTC_TamperPinInterruptEnable & mask)) in RTC_EnableInterrupts()
356 if (kRTC_SecurityModuleInterruptEnable == (kRTC_SecurityModuleInterruptEnable & mask)) in RTC_EnableInterrupts()
[all …]
Dfsl_flexio.h469 static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_EnableShifterStatusInterrupts() argument
471 base->SHIFTSIEN |= mask; in FLEXIO_EnableShifterStatusInterrupts()
482 static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_DisableShifterStatusInterrupts() argument
484 base->SHIFTSIEN &= ~mask; in FLEXIO_DisableShifterStatusInterrupts()
495 static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_EnableShifterErrorInterrupts() argument
497 base->SHIFTEIEN |= mask; in FLEXIO_EnableShifterErrorInterrupts()
508 static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_DisableShifterErrorInterrupts() argument
510 base->SHIFTEIEN &= ~mask; in FLEXIO_DisableShifterErrorInterrupts()
521 static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) in FLEXIO_EnableTimerStatusInterrupts() argument
523 base->TIMIEN |= mask; in FLEXIO_EnableTimerStatusInterrupts()
[all …]
Dfsl_gpio.h153 static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) in GPIO_SetPinsOutput() argument
155 base->PSOR = mask; in GPIO_SetPinsOutput()
164 static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) in GPIO_ClearPinsOutput() argument
166 base->PCOR = mask; in GPIO_ClearPinsOutput()
175 static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) in GPIO_TogglePinsOutput() argument
177 base->PTOR = mask; in GPIO_TogglePinsOutput()
223 void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
329 static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) in FGPIO_SetPinsOutput() argument
331 base->PSOR = mask; in FGPIO_SetPinsOutput()
340 static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) in FGPIO_ClearPinsOutput() argument
[all …]
Dfsl_port.h265 static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config… in PORT_SetMultiplePinsConfig() argument
271 if (mask & 0xffffU) in PORT_SetMultiplePinsConfig()
273 base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; in PORT_SetMultiplePinsConfig()
275 if (mask >> 16) in PORT_SetMultiplePinsConfig()
277 base->GPCHR = (mask & 0xffff0000U) | pcrl; in PORT_SetMultiplePinsConfig()
303 static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interru… in PORT_SetMultipleInterruptPinsConfig() argument
307 if (mask & 0xffffU) in PORT_SetMultipleInterruptPinsConfig()
309 base->GICLR = (config << 16) | (mask & 0xffffU); in PORT_SetMultipleInterruptPinsConfig()
311 if (mask >> 16) in PORT_SetMultipleInterruptPinsConfig()
313 base->GICHR = (config << 16) | (mask & 0xffff0000U); in PORT_SetMultipleInterruptPinsConfig()
[all …]
Dfsl_dac.h196 static inline void DAC_SetReset(LPDAC_Type *base, uint32_t mask) in DAC_SetReset() argument
198 base->RCR |= mask; in DAC_SetReset()
210 static inline void DAC_ClearReset(LPDAC_Type *base, uint32_t mask) in DAC_ClearReset() argument
212 base->RCR &= ~mask; in DAC_ClearReset()
248 static inline void DAC_EnableInterrupts(LPDAC_Type *base, uint32_t mask) in DAC_EnableInterrupts() argument
250 base->IER |= mask; in DAC_EnableInterrupts()
259 static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask) in DAC_DisableInterrupts() argument
261 base->IER &= ~mask; in DAC_DisableInterrupts()
278 static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable) in DAC_EnableDMA() argument
282 base->DER |= mask; in DAC_EnableDMA()
[all …]
Dfsl_trng.c127 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (valu… argument
187 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (v… argument
250 #define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (v… argument
317 #define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (v… argument
384 #define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (v… argument
451 #define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (v… argument
518 #define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) |… argument
583 #define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) |… argument
632 #define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) |… argument
682 #define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) |… argument
[all …]
Dfsl_usdhc.h673 bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout);
710 static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask) in USDHC_EnableInterruptStatus() argument
712 base->INT_STATUS_EN |= mask; in USDHC_EnableInterruptStatus()
721 static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask) in USDHC_DisableInterruptStatus() argument
723 base->INT_STATUS_EN &= ~mask; in USDHC_DisableInterruptStatus()
732 static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask) in USDHC_EnableInterruptSignal() argument
734 base->INT_SIGNAL_EN |= mask; in USDHC_EnableInterruptSignal()
743 static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) in USDHC_DisableInterruptSignal() argument
745 base->INT_SIGNAL_EN &= ~mask; in USDHC_DisableInterruptSignal()
772 static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask) in USDHC_ClearInterruptStatusFlags() argument
[all …]
Dfsl_mu.h363 static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t mask) in MU_ClearStatusFlags() argument
380 base->SR = (mask & regMask); in MU_ClearStatusFlags()
397 static inline void MU_EnableInterrupts(MU_Type *base, uint32_t mask) in MU_EnableInterrupts() argument
400 reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; in MU_EnableInterrupts()
418 static inline void MU_DisableInterrupts(MU_Type *base, uint32_t mask) in MU_DisableInterrupts() argument
421 reg &= ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | mask); in MU_DisableInterrupts()
447 status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask);
560 static inline void MU_MaskHardwareReset(MU_Type *base, bool mask) in MU_MaskHardwareReset() argument
562 if (mask) in MU_MaskHardwareReset()
Dfsl_lpcmp.h260 static inline void LPCMP_EnableInterrupts(LPCMP_Type *base, uint32_t mask) in LPCMP_EnableInterrupts() argument
262 base->IER |= mask; in LPCMP_EnableInterrupts()
271 static inline void LPCMP_DisableInterrupts(LPCMP_Type *base, uint32_t mask) in LPCMP_DisableInterrupts() argument
273 base->IER &= ~mask; in LPCMP_DisableInterrupts()
294 static inline void LPCMP_ClearStatusFlags(LPCMP_Type *base, uint32_t mask) in LPCMP_ClearStatusFlags() argument
296 base->CSR = mask; in LPCMP_ClearStatusFlags()
Dfsl_lpit.h213 static inline void LPIT_EnableInterrupts(LPIT_Type* base, uint32_t mask) in LPIT_EnableInterrupts() argument
215 base->MIER |= mask; in LPIT_EnableInterrupts()
225 static inline void LPIT_DisableInterrupts(LPIT_Type* base, uint32_t mask) in LPIT_DisableInterrupts() argument
227 base->MIER &= ~mask; in LPIT_DisableInterrupts()
270 static inline void LPIT_ClearStatusFlags(LPIT_Type* base, uint32_t mask) in LPIT_ClearStatusFlags() argument
273 base->MSR = mask; in LPIT_ClearStatusFlags()
Dfsl_lpspi.h599 static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) in LPSPI_EnableInterrupts() argument
601 base->IER |= mask; in LPSPI_EnableInterrupts()
614 static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) in LPSPI_DisableInterrupts() argument
616 base->IER &= ~mask; in LPSPI_DisableInterrupts()
639 static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) in LPSPI_EnableDMA() argument
641 base->DER |= mask; in LPSPI_EnableDMA()
655 static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) in LPSPI_DisableDMA() argument
657 base->DER &= ~mask; in LPSPI_DisableDMA()
765 static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) in LPSPI_SetAllPcsPolarity() argument
767 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); in LPSPI_SetAllPcsPolarity()
Dfsl_lptmr.h177 static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) in LPTMR_EnableInterrupts() argument
183 reg |= mask; in LPTMR_EnableInterrupts()
194 static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) in LPTMR_DisableInterrupts() argument
200 reg &= ~mask; in LPTMR_DisableInterrupts()
264 static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) in LPTMR_ClearStatusFlags() argument
266 base->CSR |= mask; in LPTMR_ClearStatusFlags()
Dfsl_wdog32.h224 static inline void WDOG32_EnableInterrupts(WDOG_Type *base, uint32_t mask) in WDOG32_EnableInterrupts() argument
226 base->CS |= mask; in WDOG32_EnableInterrupts()
241 static inline void WDOG32_DisableInterrupts(WDOG_Type *base, uint32_t mask) in WDOG32_DisableInterrupts() argument
243 base->CS &= ~mask; in WDOG32_DisableInterrupts()
280 void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask);
Dfsl_lpadc.h400 static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) in LPADC_ClearStatusFlags() argument
402 base->STAT = mask; in LPADC_ClearStatusFlags()
418 static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) in LPADC_EnableInterrupts() argument
420 base->IE |= mask; in LPADC_EnableInterrupts()
429 static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) in LPADC_DisableInterrupts() argument
431 base->IE &= ~mask; in LPADC_DisableInterrupts()
Dfsl_ewm.h162 static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) in EWM_EnableInterrupts() argument
164 base->CTRL |= mask; in EWM_EnableInterrupts()
177 static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) in EWM_DisableInterrupts() argument
179 base->CTRL &= ~mask; in EWM_DisableInterrupts()
Dfsl_lpuart.c577 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) in LPUART_EnableInterrupts() argument
579 base->BAUD |= ((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); in LPUART_EnableInterrupts()
582 ((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); in LPUART_EnableInterrupts()
584 mask &= 0xFFFFFF00U; in LPUART_EnableInterrupts()
585 base->CTRL |= mask; in LPUART_EnableInterrupts()
588 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) in LPUART_DisableInterrupts() argument
590 base->BAUD &= ~((mask << 8) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); in LPUART_DisableInterrupts()
593 ~((mask << 8) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); in LPUART_DisableInterrupts()
595 mask &= 0xFFFFFF00U; in LPUART_DisableInterrupts()
596 base->CTRL &= ~mask; in LPUART_DisableInterrupts()
[all …]
Dfsl_flexio_uart.c235 void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) in FLEXIO_UART_EnableInterrupts() argument
237 if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) in FLEXIO_UART_EnableInterrupts()
241 if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) in FLEXIO_UART_EnableInterrupts()
247 void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) in FLEXIO_UART_DisableInterrupts() argument
249 if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) in FLEXIO_UART_DisableInterrupts()
253 if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) in FLEXIO_UART_DisableInterrupts()
273 void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) in FLEXIO_UART_ClearStatusFlags() argument
275 if (mask & kFLEXIO_UART_TxDataRegEmptyFlag) in FLEXIO_UART_ClearStatusFlags()
279 if (mask & kFLEXIO_UART_RxDataRegFullFlag) in FLEXIO_UART_ClearStatusFlags()
283 if (mask & kFLEXIO_UART_RxOverRunFlag) in FLEXIO_UART_ClearStatusFlags()
Dfsl_flexio_spi.c412 void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) in FLEXIO_SPI_EnableInterrupts() argument
414 if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) in FLEXIO_SPI_EnableInterrupts()
418 if (mask & kFLEXIO_SPI_RxFullInterruptEnable) in FLEXIO_SPI_EnableInterrupts()
424 void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) in FLEXIO_SPI_DisableInterrupts() argument
426 if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) in FLEXIO_SPI_DisableInterrupts()
430 if (mask & kFLEXIO_SPI_RxFullInterruptEnable) in FLEXIO_SPI_DisableInterrupts()
436 void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) in FLEXIO_SPI_EnableDMA() argument
438 if (mask & kFLEXIO_SPI_TxDmaEnable) in FLEXIO_SPI_EnableDMA()
443 if (mask & kFLEXIO_SPI_RxDmaEnable) in FLEXIO_SPI_EnableDMA()
460 void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) in FLEXIO_SPI_ClearStatusFlags() argument
[all …]
/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/cfgs_rv32m1/
Dfsl_xcvr_gfsk_bt_0p7_h_0p5_config.c35 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
132 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
134 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
136 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
261 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
263 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
265 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
388 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
390 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
392 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
[all …]
Dfsl_xcvr_msk_config.c35 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
122 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
124 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
126 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
251 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
253 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
255 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
381 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
383 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
385 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
[all …]
Dfsl_xcvr_gfsk_bt_0p5_h_0p5_config.c35 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
119 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
121 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
123 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
250 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
252 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
254 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
381 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
383 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
385 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
[all …]
Dfsl_xcvr_gfsk_bt_0p3_h_0p5_config.c35 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
132 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
134 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
136 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
259 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
261 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
263 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
385 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
387 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
389 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
[all …]
Dfsl_xcvr_gfsk_bt_0p5_h_0p32_config.c35 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
120 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
122 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
124 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
247 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
249 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
251 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
373 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
375 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
377 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
[all …]
Dfsl_xcvr_gfsk_bt_0p5_h_1p0_config.c34 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
120 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
122 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
124 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
249 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
251 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
253 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
377 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
379 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
381 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
Dfsl_xcvr_gfsk_bt_0p5_h_0p7_config.c34 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK |
120 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
122 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
124 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
248 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
250 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
252 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,
376 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK,
378 … .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK,
380 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK,

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