1 /*
2 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_COMMON_H_
10 #define _FSL_COMMON_H_
11
12 #include <assert.h>
13 #include <stdbool.h>
14 #include <stdint.h>
15 #include <string.h>
16
17 #if defined(__ICCARM__)
18 #include <stddef.h>
19 #endif
20
21 #include "fsl_device_registers.h"
22
23 /*!
24 * @addtogroup ksdk_common
25 * @{
26 */
27
28 /*******************************************************************************
29 * Definitions
30 ******************************************************************************/
31
32 /*! @brief Construct a status code value from a group and code number. */
33 #define MAKE_STATUS(group, code) ((((group)*100) + (code)))
34
35 /*! @brief Construct the version number for drivers. */
36 #define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
37
38 /*! @name Driver version */
39 /*@{*/
40 /*! @brief common driver version 2.0.0. */
41 #define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
42 /*@}*/
43
44 /* Debug console type definition. */
45 #define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
46 #define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
47 #define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
48 #define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
49 #define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
50 #define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
51 #define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
52 #define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
53
54 /*! @brief Status group numbers. */
55 enum _status_groups
56 {
57 kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
58 kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
59 kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
60 kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
61 kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
62 kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
63 kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
64 kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
65 kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
66 kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
67 kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
68 kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
69 kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
70 kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
71 kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
72 kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
73 kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
74 kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
75 kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
76 kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
77 kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
78 kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
79 kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
80 kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
81 kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
82 kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
83 kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
84 kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
85 kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
86 kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
87 kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
88 kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
89 kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
90 kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
91 kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
92 kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
93 kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
94 kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
95 kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
96 kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
97 kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
98 kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
99 kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
100 kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
101 kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
102 kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
103 kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
104 kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
105 kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
106 kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
107 kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
108 kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
109 kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
110 kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
111 kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
112 kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
113 kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
114 kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
115 kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
116 kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
117 kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
118 kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
119 };
120
121 /*! @brief Generic status return codes. */
122 enum _generic_status
123 {
124 kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
125 kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
126 kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
127 kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
128 kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
129 kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
130 kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
131 };
132
133 /*! @brief Type used for all status and error return values. */
134 typedef int32_t status_t;
135
136 /*
137 * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
138 * defined in previous of this file.
139 */
140 #include "fsl_clock.h"
141
142 /*
143 * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
144 */
145 #if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
146 (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
147 #include "fsl_reset.h"
148 #endif
149
150 /*! @name Min/max macros */
151 /* @{ */
152 #if !defined(MIN)
153 #define MIN(a, b) ((a) < (b) ? (a) : (b))
154 #endif
155
156 #if !defined(MAX)
157 #define MAX(a, b) ((a) > (b) ? (a) : (b))
158 #endif
159 /* @} */
160
161 /*! @brief Computes the number of elements in an array. */
162 #if !defined(ARRAY_SIZE)
163 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
164 #endif
165
166 /*! @name UINT16_MAX/UINT32_MAX value */
167 /* @{ */
168 #if !defined(UINT16_MAX)
169 #define UINT16_MAX ((uint16_t)-1)
170 #endif
171
172 #if !defined(UINT32_MAX)
173 #define UINT32_MAX ((uint32_t)-1)
174 #endif
175 /* @} */
176
177 /*! @name Timer utilities */
178 /* @{ */
179 /*! Macro to convert a microsecond period to raw count value */
180 #define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
181 /*! Macro to convert a raw count value to microsecond */
182 #define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
183
184 /*! Macro to convert a millisecond period to raw count value */
185 #define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
186 /*! Macro to convert a raw count value to millisecond */
187 #define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
188 /* @} */
189
190 /*! @name Alignment variable definition macros */
191 /* @{ */
192 #if (defined(__ICCARM__))
193 /**
194 * Workaround to disable MISRA C message suppress warnings for IAR compiler.
195 * http://supp.iar.com/Support/?note=24725
196 */
197 _Pragma("diag_suppress=Pm120")
198 #define SDK_PRAGMA(x) _Pragma(#x)
199 _Pragma("diag_error=Pm120")
200 /*! Macro to define a variable with alignbytes alignment */
201 #define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
202 /*! Macro to define a variable with L1 d-cache line size alignment */
203 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
204 #define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
205 #endif
206 /*! Macro to define a variable with L2 cache line size alignment */
207 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
208 #define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
209 #endif
210 #elif defined(__CC_ARM)
211 /*! Macro to define a variable with alignbytes alignment */
212 #define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
213 /*! Macro to define a variable with L1 d-cache line size alignment */
214 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
215 #define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
216 #endif
217 /*! Macro to define a variable with L2 cache line size alignment */
218 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
219 #define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
220 #endif
221 #elif defined(__GNUC__)
222 /*! Macro to define a variable with alignbytes alignment */
223 #define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
224 /*! Macro to define a variable with L1 d-cache line size alignment */
225 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
226 #define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
227 #endif
228 /*! Macro to define a variable with L2 cache line size alignment */
229 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
230 #define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
231 #endif
232 #else
233 #error Toolchain not supported
234 #define SDK_ALIGN(var, alignbytes) var
235 #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
236 #define SDK_L1DCACHE_ALIGN(var) var
237 #endif
238 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
239 #define SDK_L2CACHE_ALIGN(var) var
240 #endif
241 #endif
242
243 /*! Macro to change a value to a given size aligned value */
244 #define SDK_SIZEALIGN(var, alignbytes) \
245 ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
246 /* @} */
247
248 /*! @name Non-cacheable region definition macros */
249 /* @{ */
250 #if (defined(__ICCARM__))
251 #if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
252 #define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
253 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
254 #else
255 #define AT_NONCACHEABLE_SECTION(var) var
256 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
257 #endif
258 #elif(defined(__CC_ARM))
259 #if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
260 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
261 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
262 __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
263 #else
264 #define AT_NONCACHEABLE_SECTION(var) var
265 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
266 #endif
267 #elif(defined(__GNUC__))
268 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
269 * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
270 */
271 #if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
272 #define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
273 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
274 __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
275 #else
276 #define AT_NONCACHEABLE_SECTION(var) var
277 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
278 #endif
279 #else
280 #error Toolchain not supported.
281 #define AT_NONCACHEABLE_SECTION(var) var
282 #define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
283 #endif
284 /* @} */
285
286 /*******************************************************************************
287 * API
288 ******************************************************************************/
289
290 #if defined(__cplusplus)
291 extern "C" {
292 #endif
293
294 /*!
295 * @brief Enable specific interrupt.
296 *
297 * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
298 * levels. For example, there are NVIC and intmux. Here the interrupts connected
299 * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
300 * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
301 * to NVIC first then routed to core.
302 *
303 * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
304 * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
305 *
306 * @param interrupt The IRQ number.
307 * @retval kStatus_Success Interrupt enabled successfully
308 * @retval kStatus_Fail Failed to enable the interrupt
309 */
EnableIRQ(IRQn_Type interrupt)310 static inline status_t EnableIRQ(IRQn_Type interrupt)
311 {
312 if (NotAvail_IRQn == interrupt)
313 {
314 return kStatus_Fail;
315 }
316
317 #if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
318 if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
319 {
320 return kStatus_Fail;
321 }
322 #endif
323
324 #if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
325 EVENT_UNIT->INTPTEN |= (uint32_t)(1 << interrupt);
326 /* Read back to make sure write finished. */
327 (void)EVENT_UNIT->INTPTEN;
328 #else
329 #if defined(__GIC_PRIO_BITS)
330 GIC_EnableIRQ(interrupt);
331 #else
332 NVIC_EnableIRQ(interrupt);
333 #endif
334 #endif
335 return kStatus_Success;
336 }
337
338 /*!
339 * @brief Disable specific interrupt.
340 *
341 * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
342 * levels. For example, there are NVIC and intmux. Here the interrupts connected
343 * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
344 * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
345 * to NVIC first then routed to core.
346 *
347 * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
348 * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
349 *
350 * @param interrupt The IRQ number.
351 * @retval kStatus_Success Interrupt disabled successfully
352 * @retval kStatus_Fail Failed to disable the interrupt
353 */
DisableIRQ(IRQn_Type interrupt)354 static inline status_t DisableIRQ(IRQn_Type interrupt)
355 {
356 if (NotAvail_IRQn == interrupt)
357 {
358 return kStatus_Fail;
359 }
360
361 #if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
362 if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
363 {
364 return kStatus_Fail;
365 }
366 #endif
367
368 #if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
369 EVENT_UNIT->INTPTEN &= ~(uint32_t)(1 << interrupt);
370 /* Read back to make sure write finished. */
371 (void)EVENT_UNIT->INTPTEN;
372 #else
373 #if defined(__GIC_PRIO_BITS)
374 GIC_DisableIRQ(interrupt);
375 #else
376 NVIC_DisableIRQ(interrupt);
377 #endif
378 #endif
379 return kStatus_Success;
380 }
381
382 /*!
383 * @brief Disable the global IRQ
384 *
385 * Disable the global interrupt and return the current primask register. User is required to provided the primask
386 * register for the EnableGlobalIRQ().
387 *
388 * @return Current primask value.
389 */
DisableGlobalIRQ(void)390 static inline uint32_t DisableGlobalIRQ(void)
391 {
392 #ifndef __riscv
393 #if defined(CPSR_I_Msk)
394 uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
395
396 __disable_irq();
397
398 return cpsr;
399 #else
400 uint32_t regPrimask = __get_PRIMASK();
401
402 __disable_irq();
403
404 return regPrimask;
405 #endif
406 #else
407 uint32_t mstatus;
408
409 __ASM volatile ("csrrci %0, mstatus, 8" : "=r"(mstatus));
410
411 return mstatus;
412 #endif
413 }
414
415 /*!
416 * @brief Enaable the global IRQ
417 *
418 * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
419 * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
420 * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
421 *
422 * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
423 * DisableGlobalIRQ().
424 */
EnableGlobalIRQ(uint32_t primask)425 static inline void EnableGlobalIRQ(uint32_t primask)
426 {
427 #ifndef __riscv
428 #if defined(CPSR_I_Msk)
429 __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
430 #else
431 __set_PRIMASK(primask);
432 #endif
433 #else
434 __ASM volatile ("csrw mstatus, %0" : : "r"(primask));
435 #endif
436 }
437
438 /*!
439 * @brief install IRQ handler
440 *
441 * @param irq IRQ number
442 * @param irqHandler IRQ handler address
443 * @return The old IRQ handler address
444 */
445 uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
446
447 #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
448 /*!
449 * @brief Enable specific interrupt for wake-up from deep-sleep mode.
450 *
451 * Enable the interrupt for wake-up from deep sleep mode.
452 * Some interrupts are typically used in sleep mode only and will not occur during
453 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
454 * those clocks (significantly increasing power consumption in the reduced power mode),
455 * making these wake-ups possible.
456 *
457 * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
458 *
459 * @param interrupt The IRQ number.
460 */
461 void EnableDeepSleepIRQ(IRQn_Type interrupt);
462
463 /*!
464 * @brief Disable specific interrupt for wake-up from deep-sleep mode.
465 *
466 * Disable the interrupt for wake-up from deep sleep mode.
467 * Some interrupts are typically used in sleep mode only and will not occur during
468 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
469 * those clocks (significantly increasing power consumption in the reduced power mode),
470 * making these wake-ups possible.
471 *
472 * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
473 *
474 * @param interrupt The IRQ number.
475 */
476 void DisableDeepSleepIRQ(IRQn_Type interrupt);
477 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
478
479 #if defined(__cplusplus)
480 }
481 #endif
482
483 /*! @} */
484
485 #endif /* _FSL_COMMON_H_ */
486
