1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_LPADC_H_
9 #define _FSL_LPADC_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lpadc
15 * @{
16 */
17
18 /*! @file */
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
24 /*! @name Driver version */
25 /*@{*/
26 /*! @brief LPADC driver version 2.0.0. */
27 #define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
28 /*@}*/
29
30 /*!
31 * @brief Define the MACRO function to get command status from status value.
32 *
33 * The statusVal is the return value from LPADC_GetStatusFlags().
34 */
35 #define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT)
36
37 /*!
38 * @brief Define the MACRO function to get trigger status from status value.
39 *
40 * The statusVal is the return value from LPADC_GetStatusFlags().
41 */
42 #define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT)
43
44 /*!
45 * @brief Define hardware flags of the module.
46 */
47 enum _lpadc_status_flags
48 {
49 kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO
50 than it can hold. */
51 kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO
52 is greater than the setting watermark level. */
53 };
54
55 /*!
56 * @brief Define interrupt switchers of the module.
57 */
58 enum _lpadc_interrupt_enable
59 {
60 kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt
61 requests when FOF flag is asserted. */
62 kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt
63 requests when RDY flag is asserted. */
64 };
65
66 /*!
67 * @brief Define enumeration of sample scale mode.
68 *
69 * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum
70 * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the
71 * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows
72 * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.
73 */
74 typedef enum _lpadc_sample_scale_mode
75 {
76 kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */
77 kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */
78 } lpadc_sample_scale_mode_t;
79
80 /*!
81 * @brief Define enumeration of channel sample mode.
82 *
83 * The channel sample mode configures the channel with single end/differential, side A/B.
84 */
85 typedef enum _lpadc_sample_channel_mode
86 {
87 kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */
88 kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */
89 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
90 kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */
91 kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */
92 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
93 } lpadc_sample_channel_mode_t;
94
95 /*!
96 * @brief Define enumeration of hardware average selection.
97 *
98 * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to
99 * capture temporary results while the averaging iterations are executed.
100 */
101 typedef enum _lpadc_hardware_average_mode
102 {
103 kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */
104 kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */
105 kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */
106 kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */
107 kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */
108 kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */
109 kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */
110 kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */
111 } lpadc_hardware_average_mode_t;
112
113 /*!
114 * @brief Define enumeration of sample time selection.
115 *
116 * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher
117 * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption
118 * when command looping and sequencing is configured and high conversion rates are not required.
119 */
120 typedef enum _lpadc_sample_time_mode
121 {
122 kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */
123 kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */
124 kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */
125 kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */
126 kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */
127 kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */
128 kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */
129 kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */
130 } lpadc_sample_time_mode_t;
131
132 /*!
133 * @brief Define enumeration of hardware compare mode.
134 *
135 * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting
136 * guides operation of the automatic compare function to optionally only store when the compare operation is true.
137 * When compare is enabled, the conversion result is compared to the compare values.
138 */
139 typedef enum _lpadc_hardware_compare_mode
140 {
141 kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */
142 kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */
143 kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */
144 } lpadc_hardware_compare_mode_t;
145
146 /*!
147 * @brief Define enumeration of reference voltage source.
148 *
149 * For detail information, need to check the SoC's specification.
150 */
151 typedef enum _lpadc_reference_voltage_mode
152 {
153 kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */
154 kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */
155 kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */
156 } lpadc_reference_voltage_source_t;
157
158 /*!
159 * @brief Define enumeration of power configuration.
160 *
161 * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be
162 * possible. Refer to the device data sheet for power and performance capabilities for each setting.
163 */
164 typedef enum _lpadc_power_level_mode
165 {
166 kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */
167 kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */
168 kLPADC_PowerLevelAlt3 = 2U, /*!< ... */
169 kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */
170 } lpadc_power_level_mode_t;
171
172 /*!
173 * @brief Define enumeration of trigger priority policy.
174 *
175 * This selection controls how higher priority triggers are handled.
176 */
177 typedef enum _lpadc_trigger_priority_policy
178 {
179 kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command
180 processing, the current conversion is aborted and the new
181 command specified by the trigger is started. */
182 kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing,
183 the current conversion is completed (including averaging iterations
184 and compare function if enabled) and stored to the result FIFO
185 before the higher priority trigger/command is initiated. */
186 } lpadc_trigger_priority_policy_t;
187
188 /*!
189 * @beief LPADC global configuration.
190 *
191 * This structure would used to keep the settings for initialization.
192 */
193 typedef struct
194 {
195 #if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
196 bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock
197 selection logic at the chip level and is optionally used for the ADC clock source. */
198 #endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
199 #if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
200 bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true".
201 If voltage reference option1 input is above 1.8V, it should be "false". */
202 #endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
203 bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When
204 enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the
205 ADC will wait for the current averaging iteration/FIFO storage to complete before
206 acknowledging stop or wait mode entry. */
207 bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without
208 startup delays(at the cost of higher DC current consumption). */
209 uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered
210 while the ADC is active and there is a counted delay defined by this field after an
211 initial trigger transitions the ADC from its Idle state to allow time for the analog
212 circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must
213 result in a longer delay than the analog startup time. */
214 lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for
215 conversions.*/
216 lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */
217 lpadc_trigger_priority_policy_t triggerPrioirtyPolicy; /*!< Control how higher priority triggers are handled, see to
218 #lpadc_trigger_priority_policy_mode_t. */
219 bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during
220 command execution sequencing between LOOP iterations, between commands in a sequence, and
221 between conversions when command is executing in "Compare Until True" configuration. */
222 uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay
223 is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing
224 function is enabled. The available value range is in 9-bit. */
225 /* for FIFO. */
226 uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored
227 in the ADC Result FIFO is greater than the value in this field, the ready flag would be
228 asserted to indicate stored data has reached the programmable threshold. */
229
230 } lpadc_config_t;
231
232 /*!
233 * @brief Define structure to keep the configuration for conversion command.
234 */
235 typedef struct
236 {
237 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
238 lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */
239 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
240 lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */
241 uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */
242 uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes.
243 1-15 is available, 0 is to terminate the chain after this command. */
244 bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number
245 of times the selected channel is converted consecutively; when enabled, the
246 "loopCount" field defines how many consecutive channels are converted as part
247 of the command execution. */
248 uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next
249 command or Idle state. Command executes LOOP+1 times. 0-15 is available. */
250 lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */
251 lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */
252
253 lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */
254 uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */
255 uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */
256 } lpadc_conv_command_config_t;
257
258 /*!
259 * @brief Define structure to keep the configuration for conversion trigger.
260 */
261 typedef struct
262 {
263 uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated
264 trigger event. */
265 uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event.
266 When this field is clear, then no delay is incurred. When this field is set to a non-zero
267 value, the duration for the delay is 2^delayPower ADCK cycles. The available value range
268 is 4-bit. */
269 uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same
270 priority level setting, the lower order trigger event has the higher priority. The lower
271 value for this field is for the higher priority, the available value range is 1-bit. */
272 bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the
273 input trigger source or not. THe software trigger is always available. */
274 } lpadc_conv_trigger_config_t;
275
276 /*!
277 * @brief Define the structure to keep the conversion result.
278 */
279 typedef struct
280 {
281 uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */
282 uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */
283 uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */
284 uint16_t convValue; /*!< Data result. */
285 } lpadc_conv_result_t;
286
287 #if defined(__cplusplus)
288 extern "C" {
289 #endif
290
291 /*******************************************************************************
292 * API
293 ******************************************************************************/
294 /*!
295 * @name Initialization & de-initialization.
296 * @{
297 */
298
299 /*!
300 * @brief Initializes the LPADC module.
301 *
302 * @param base LPADC peripheral base address.
303 * @param config Pointer to configuration structure. See "lpadc_config_t".
304 */
305 void LPADC_Init(ADC_Type *base, const lpadc_config_t *config);
306
307 /*!
308 * @brief Gets an available pre-defined settings for initial configuration.
309 *
310 * This function initializes the converter configuration structure with an available settings. The default values are:
311 * @code
312 * config->enableInDozeMode = true;
313 * config->enableAnalogPreliminary = false;
314 * config->powerUpDelay = 0x80;
315 * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
316 * config->powerLevelMode = kLPADC_PowerLevelAlt1;
317 * config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately;
318 * config->enableConvPause = false;
319 * config->convPauseDelay = 0U;
320 * config->FIFOWatermark = 0U;
321 * @endcode
322 * @param config Pointer to configuration structure.
323 */
324 void LPADC_GetDefaultConfig(lpadc_config_t *config);
325
326 /*!
327 * @brief De-initializes the LPADC module.
328 *
329 * @param base LPADC peripheral base address.
330 */
331 void LPADC_Deinit(ADC_Type *base);
332
333 /*!
334 * @brief Switch on/off the LPADC module.
335 *
336 * @param base LPADC peripheral base address.
337 * @param enable switcher to the module.
338 */
LPADC_Enable(ADC_Type * base,bool enable)339 static inline void LPADC_Enable(ADC_Type *base, bool enable)
340 {
341 if (enable)
342 {
343 base->CTRL |= ADC_CTRL_ADCEN_MASK;
344 }
345 else
346 {
347 base->CTRL &= ~ADC_CTRL_ADCEN_MASK;
348 }
349 }
350
351 /*!
352 * @brief Do reset the conversion FIFO.
353 *
354 * @param base LPADC peripheral base address.
355 */
LPADC_DoResetFIFO(ADC_Type * base)356 static inline void LPADC_DoResetFIFO(ADC_Type *base)
357 {
358 base->CTRL |= ADC_CTRL_RSTFIFO_MASK;
359 }
360
361 /*!
362 * @brief Do reset the module's configuration.
363 *
364 * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL).
365 *
366 * @param base LPADC peripheral base address.
367 */
LPADC_DoResetConfig(ADC_Type * base)368 static inline void LPADC_DoResetConfig(ADC_Type *base)
369 {
370 base->CTRL |= ADC_CTRL_RST_MASK;
371 base->CTRL &= ~ADC_CTRL_RST_MASK;
372 }
373
374 /* @} */
375
376 /*!
377 * @name Status
378 * @{
379 */
380
381 /*!
382 * @brief Get status flags.
383 *
384 * @param base LPADC peripheral base address.
385 * @return status flags' mask. See to #_lpadc_status_flags.
386 */
LPADC_GetStatusFlags(ADC_Type * base)387 static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)
388 {
389 return base->STAT;
390 }
391
392 /*!
393 * @brief Clear status flags.
394 *
395 * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.
396 *
397 * @param base LPADC peripheral base address.
398 * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags.
399 */
LPADC_ClearStatusFlags(ADC_Type * base,uint32_t mask)400 static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
401 {
402 base->STAT = mask;
403 }
404
405 /* @} */
406
407 /*!
408 * @name Interrupts
409 * @{
410 */
411
412 /*!
413 * @brief Enable interrupts.
414 *
415 * @param base LPADC peripheral base address.
416 * @mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
417 */
LPADC_EnableInterrupts(ADC_Type * base,uint32_t mask)418 static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
419 {
420 base->IE |= mask;
421 }
422
423 /*!
424 * @brief Disable interrupts.
425 *
426 * @param base LPADC peripheral base address.
427 * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
428 */
LPADC_DisableInterrupts(ADC_Type * base,uint32_t mask)429 static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
430 {
431 base->IE &= ~mask;
432 }
433
434 /*!
435 * @name DMA Control
436 * @{
437 */
438
439 /*!
440 * @brief Switch on/off the DMA trigger for FIFO watermark event.
441 *
442 * @param base LPADC peripheral base address.
443 * @param enable Switcher to the event.
444 */
LPADC_EnableFIFOWatermarkDMA(ADC_Type * base,bool enable)445 static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)
446 {
447 if (enable)
448 {
449 base->DE |= ADC_DE_FWMDE_MASK;
450 }
451 else
452 {
453 base->DE &= ~ADC_DE_FWMDE_MASK;
454 }
455 }
456
457 /* @} */
458
459 /*!
460 * @name Trigger and conversion with FIFO.
461 * @{
462 */
463
464 /*!
465 * @brief Get the count of result kept in conversion FIFO.
466 *
467 * @param base LPADC peripheral base address.
468 * @return The count of result kept in conversion FIFO.
469 */
LPADC_GetConvResultCount(ADC_Type * base)470 static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)
471 {
472 return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT;
473 }
474
475 /*!
476 * @brief Get the result in conversion FIFO.
477 *
478 * @param base LPADC peripheral base address.
479 * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
480 *
481 * @return Status whether FIFO entry is valid.
482 */
483 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result);
484
485 /*!
486 * @brief Configure the conversion trigger source.
487 *
488 * Each programmable trigger can launch the conversion command in command buffer.
489 *
490 * @param base LPADC peripheral base address.
491 * @param triggerId ID for each trigger. Typically, the available value range is from 0.
492 * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t.
493 */
494 void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config);
495
496 /*!
497 * @brief Gets an available pre-defined settings for trigger's configuration.
498 *
499 * This function initializes the trigger's configuration structure with an available settings. The default values are:
500 * @code
501 * config->commandIdSource = 0U;
502 * config->loopCountIndex = 0U;
503 * config->triggerIdSource = 0U;
504 * config->enableHardwareTrigger = false;
505 * @endcode
506 * @param config Pointer to configuration structure.
507 */
508 void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config);
509
510 /*!
511 * @brief Do software trigger to conversion command.
512 *
513 * @param base LPADC peripheral base address.
514 * @param triggerIdMask Mask value for software trigger indexes, which count from zero.
515 */
LPADC_DoSoftwareTrigger(ADC_Type * base,uint32_t triggerIdMask)516 static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)
517 {
518 /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */
519 base->SWTRIG = triggerIdMask;
520 }
521
522 /*!
523 * @brief Configure conversion command.
524 *
525 * @param base LPADC peripheral base address.
526 * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
527 * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
528 */
529 void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config);
530
531 /*!
532 * @brief Gets an available pre-defined settings for conversion command's configuration.
533 *
534 * This function initializes the conversion command's configuration structure with an available settings. The default
535 * values are:
536 * @code
537 * config->sampleScaleMode = kLPADC_SampleFullScale;
538 * config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA;
539 * config->channelNumber = 0U;
540 * config->chainedNextCmdNumber = 0U;
541 * config->enableAutoChannelIncrement = false;
542 * config->loopCount = 0U;
543 * config->hardwareAverageMode = kLPADC_HardwareAverageCount1;
544 * config->sampleTimeMode = kLPADC_SampleTimeADCK3;
545 * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled;
546 * config->hardwareCompareValueHigh = 0U;
547 * config->hardwareCompareValueLow = 0U;
548 * @endcode
549 * @param config Pointer to configuration structure.
550 */
551 void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config);
552
553 #if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS
554 /*!
555 * @brief Enable the calibration function.
556 *
557 * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes
558 * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value
559 * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6-
560 * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the
561 * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
562 *
563 * @param base LPADC peripheral base address.
564 * @bool enable switcher to the calibration function.
565 */
566 void LPADC_EnableCalibration(ADC_Type *base, bool enable);
567 #endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
568
569 #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
570 /*!
571 * @brief Set proper offset value to trim ADC.
572 *
573 * To minimize the offset during normal operation, software should read the conversion result from
574 * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register.
575 *
576 * @param base LPADC peripheral base address.
577 * @param value Setting offset value.
578 */
LPADC_SetOffsetValue(ADC_Type * base,uint32_t value)579 static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)
580 {
581 base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT;
582 }
583 #endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
584
585 #if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS
586 #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
587 /*!
588 * @brief Do auto calibration.
589 *
590 * Calibration function should be executed before using converter in application. It used the software trigger and a
591 * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including:
592 * -LPADC_EnableCalibration(...)
593 * -LPADC_LPADC_SetOffsetValue(...)
594 * -LPADC_SetConvCommandConfig(...)
595 * -LPADC_SetConvTriggerConfig(...)
596 *
597 * @param base LPADC peripheral base address.
598 */
599 void LPADC_DoAutoCalibration(ADC_Type *base);
600 #endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
601 #endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
602
603 /* @} */
604
605 #if defined(__cplusplus)
606 }
607 #endif
608 /*!
609 * @}
610 */
611 #endif /* _FSL_LPADC_H_ */
612
