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/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c304 freq /= (sysClkConfig.divSlow + 1U); in CLOCK_GetSysClkFreq()
Dfsl_clock.h463 uint32_t divSlow : 4; /*!< Slow clock divider, see @ref scg_sys_clk_div_t. */ member