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/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c300 freq /= (sysClkConfig.divCore + 1U); /* divided by the DIVCORE firstly. */ in CLOCK_GetSysClkFreq()
Dfsl_clock.h467 uint32_t divCore : 4; /*!< Core clock divider, see @ref scg_sys_clk_div_t. */ member