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Searched refs:channel (Results 1 – 14 of 14) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_edma.h30 #define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) argument
33 #define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] argument
233 uint8_t channel; /*!< eDMA channel number. */ member
282 void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd);
317 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel);
345 uint32_t channel,
359 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *…
371 uint32_t channel, in EDMA_SetChannelPreemptionConfig() argument
374 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); in EDMA_SetChannelPreemptionConfig()
377 DMA_DCHPRIn(base, channel) = in EDMA_SetChannelPreemptionConfig()
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Dfsl_dmamux.h76 static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) in DMAMUX_EnableChannel() argument
78 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); in DMAMUX_EnableChannel()
80 base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; in DMAMUX_EnableChannel()
92 static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) in DMAMUX_DisableChannel() argument
94 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); in DMAMUX_DisableChannel()
96 base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; in DMAMUX_DisableChannel()
106 static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) in DMAMUX_SetSource() argument
108 assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); in DMAMUX_SetSource()
110 …base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(s… in DMAMUX_SetSource()
122 static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) in DMAMUX_EnablePeriodTrigger() argument
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Dfsl_edma.c68 void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) in EDMA_InstallTCD() argument
70 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); in EDMA_InstallTCD()
75 base->TCD[channel].SADDR = tcd->SADDR; in EDMA_InstallTCD()
76 base->TCD[channel].SOFF = tcd->SOFF; in EDMA_InstallTCD()
77 base->TCD[channel].ATTR = tcd->ATTR; in EDMA_InstallTCD()
78 base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; in EDMA_InstallTCD()
79 base->TCD[channel].SLAST = tcd->SLAST; in EDMA_InstallTCD()
80 base->TCD[channel].DADDR = tcd->DADDR; in EDMA_InstallTCD()
81 base->TCD[channel].DOFF = tcd->DOFF; in EDMA_InstallTCD()
82 base->TCD[channel].CITER_ELINKNO = tcd->CITER; in EDMA_InstallTCD()
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Dfsl_intmux.h77 static inline void INTMUX_ResetChannel(INTMUX_Type *base, uint32_t channel) in INTMUX_ResetChannel() argument
79 assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT); in INTMUX_ResetChannel()
81 base->CHANNEL[channel].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK; in INTMUX_ResetChannel()
97 static inline void INTMUX_SetChannelMode(INTMUX_Type *base, uint32_t channel, intmux_channel_logic_… in INTMUX_SetChannelMode() argument
99 assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT); in INTMUX_SetChannelMode()
101 base->CHANNEL[channel].CHn_CSR = INTMUX_CHn_CSR_AND(logic); in INTMUX_SetChannelMode()
115 static inline void INTMUX_EnableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq) in INTMUX_EnableInterrupt() argument
117 assert(channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT); in INTMUX_EnableInterrupt()
120 …base->CHANNEL[channel].CHn_IER_31_0 |= (1U << ((uint32_t)irq - FSL_FEATURE_INTMUX_IRQ_START_INDEX)… in INTMUX_EnableInterrupt()
130 static inline void INTMUX_DisableInterrupt(INTMUX_Type *base, uint32_t channel, IRQn_Type irq) in INTMUX_DisableInterrupt() argument
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Dfsl_intmux.c38 static void INTMUX_CommonIRQHandler(INTMUX_Type *intmuxBase, uint32_t channel);
81 static void INTMUX_CommonIRQHandler(INTMUX_Type *intmuxBase, uint32_t channel) in INTMUX_CommonIRQHandler() argument
85 pendingIrqOffset = intmuxBase->CHANNEL[channel].CHn_VEC; in INTMUX_CommonIRQHandler()
102 uint32_t channel; in INTMUX_Init() local
110 for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++) in INTMUX_Init()
112 INTMUX_ResetChannel(base, channel); in INTMUX_Init()
114 EnableIRQ(s_intmuxIRQNumber[instance][channel]); in INTMUX_Init()
121 uint32_t channel; in INTMUX_Deinit() local
129 for (channel = 0; channel < FSL_FEATURE_INTMUX_CHANNEL_COUNT; channel++) in INTMUX_Deinit()
132 DisableIRQ(s_intmuxIRQNumber[instance][channel]); in INTMUX_Deinit()
Dfsl_lpit.h197 status_t LPIT_SetupChannel(LPIT_Type* base, lpit_chnl_t channel, const lpit_chnl_params_t* chnlSetu…
297 static inline void LPIT_SetTimerPeriod(LPIT_Type* base, lpit_chnl_t channel, uint32_t ticks) in LPIT_SetTimerPeriod() argument
299 base->CHANNEL[channel].TVAL = ticks; in LPIT_SetTimerPeriod()
315 static inline uint32_t LPIT_GetCurrentTimerCount(LPIT_Type* base, lpit_chnl_t channel) in LPIT_GetCurrentTimerCount() argument
317 return base->CHANNEL[channel].CVAL; in LPIT_GetCurrentTimerCount()
336 static inline void LPIT_StartTimer(LPIT_Type* base, lpit_chnl_t channel) in LPIT_StartTimer() argument
338 base->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << channel); in LPIT_StartTimer()
347 static inline void LPIT_StopTimer(LPIT_Type* base, lpit_chnl_t channel) in LPIT_StopTimer() argument
349 base->CLRTEN |= (LPIT_CLRTEN_CLR_T_EN_0_MASK << channel); in LPIT_StopTimer()
Dfsl_lpi2c_edma.c232 EDMA_ResetChannel(handle->rx->base, handle->rx->channel); in LPI2C_MasterTransferEDMA()
235 EDMA_ResetChannel(handle->tx->base, handle->tx->channel); in LPI2C_MasterTransferEDMA()
273 EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, NULL); in LPI2C_MasterTransferEDMA()
274 … EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, kEDMA_MajorInterruptEnable); in LPI2C_MasterTransferEDMA()
295 EDMA_SetTransferConfig(handle->rx->base, handle->rx->channel, &transferConfig, NULL); in LPI2C_MasterTransferEDMA()
296 … EDMA_EnableChannelInterrupts(handle->rx->base, handle->rx->channel, kEDMA_MajorInterruptEnable); in LPI2C_MasterTransferEDMA()
325 EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); in LPI2C_MasterTransferEDMA()
364 if (handle->tx->base->TCD[handle->tx->channel].DLAST_SGA == 0) in LPI2C_MasterTransferGetCountEDMA()
369 … (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->tx->base, handle->tx->channel); in LPI2C_MasterTransferGetCountEDMA()
374 … (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->rx->base, handle->rx->channel); in LPI2C_MasterTransferGetCountEDMA()
Dfsl_lpspi_edma.c287 …EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); in LPSPI_MasterTransferEDMA()
342 …_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, in LPSPI_MasterTransferEDMA()
344 …eChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, in LPSPI_MasterTransferEDMA()
348 …EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); in LPSPI_MasterTransferEDMA()
484 …_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, in LPSPI_MasterTransferEDMA()
489 …_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, in LPSPI_MasterTransferEDMA()
494 …_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, in LPSPI_MasterTransferEDMA()
580 … handle->edmaRxRegToRxDataHandle->channel); in LPSPI_MasterTransferGetCountEDMA()
738 …EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); in LPSPI_SlaveTransferEDMA()
793 …_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, in LPSPI_SlaveTransferEDMA()
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Dfsl_lpit.c113 status_t LPIT_SetupChannel(LPIT_Type* base, lpit_chnl_t channel, const lpit_chnl_params_t* chnlSetu… in LPIT_SetupChannel() argument
120 if ((channel == kLPIT_Chnl_0) && (chnlSetup->chainChannel == true)) in LPIT_SetupChannel()
131 base->CHANNEL[channel].TCTRL = reg; in LPIT_SetupChannel()
Dfsl_lpuart_edma.c297 … EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); in LPUART_TransferGetReceiveCountEDMA()
315 … EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); in LPUART_TransferGetSendCountEDMA()
Dfsl_flexio_uart_edma.c306 … EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); in FLEXIO_UART_TransferGetReceiveCountEDMA()
324 … EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); in FLEXIO_UART_TransferGetSendCountEDMA()
Dfsl_flexio_spi_edma.c342 … EDMA_GetRemainingMajorLoopCount(handle->rxHandle->base, handle->rxHandle->channel)); in FLEXIO_SPI_MasterTransferGetCountEDMA()
348 … EDMA_GetRemainingMajorLoopCount(handle->txHandle->base, handle->txHandle->channel)); in FLEXIO_SPI_MasterTransferGetCountEDMA()
/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c1688 xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) in XCVR_OverrideChannel() argument
1692 if (channel == 0xFF) in XCVR_OverrideChannel()
1713 if (channel >= 128) in XCVR_OverrideChannel()
1727 ANT->CHANNEL_NUM = channel; in XCVR_OverrideChannel()
1733 GENFSK->CHANNEL_NUM = channel; in XCVR_OverrideChannel()
1742 temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK in XCVR_OverrideChannel()
1760 … XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator); in XCVR_OverrideChannel()
1764 temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer); in XCVR_OverrideChannel()
Dfsl_xcvr.h1222 xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel);