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/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_common.h153 #define MIN(a, b) ((a) < (b) ? (a) : (b)) argument
157 #define MAX(a, b) ((a) > (b) ? (a) : (b)) argument
Dfsl_cau3_ble.c1049 uint8_t * a) in cau3_aes_ccm_encr() argument
1055 a[CAU3_AES_BLOCK_SIZE - 1 - i] = (uint8_t)0; in cau3_aes_ccm_encr()
1060 cau3_aes_ctr_inc(a, L); in cau3_aes_ccm_encr()
1062 completionStatus = cau3_aes_ecb_encrypt(base, keySlot, a, out); in cau3_aes_ccm_encr()
1073 cau3_aes_ctr_inc(a, L); in cau3_aes_ccm_encr()
1074 completionStatus = cau3_aes_ecb_encrypt(base, keySlot, a, out); in cau3_aes_ccm_encr()
1086 static void cau3_aes_ccm_encr_start(uint32_t L, const uint8_t *nonce, uint8_t *a) in cau3_aes_ccm_encr_start() argument
1089 a[0] = L - 1; /* Flags = L' */ in cau3_aes_ccm_encr_start()
1090 cau3_memcpy(&a[1], nonce, 15 - L); in cau3_aes_ccm_encr_start()
1098 uint8_t *a, in cau3_aes_ccm_encr_auth() argument
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Dfsl_flash.h168 #define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) argument
Dfsl_flash.c22 #define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) argument
25 #define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) argument
Dfsl_cau3.h673 int CAU3_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB);
Dfsl_cau3_ble.h752 int CAU3_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB);
Dfsl_cau3.c2543 int CAU3_PKHA_CompareBigNum(const uint8_t *a, size_t sizeA, const uint8_t *b, size_t sizeB) in CAU3_PKHA_CompareBigNum() argument
2548 while ((sizeA) && (0u == a[sizeA - 1])) in CAU3_PKHA_CompareBigNum()
2584 uint32_t chXor = a[i] ^ b[i]; in CAU3_PKHA_CompareBigNum()
2587 val = (int)chXor * (a[i] - b[i]); in CAU3_PKHA_CompareBigNum()
/hal_openisa-latest/vega_sdk_riscv/
DCMakeLists.txt7 # The HAL uses a CPU name to expose core-specific features.