1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #include "fsl_trng.h"
9
10 #if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT
11
12 /*******************************************************************************
13 * Definitions
14 *******************************************************************************/
15 /* Default values for user configuration structure.*/
16 #if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \
17 defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES))
18 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8
19 #elif(defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \
20 defined(KL82Z7_SERIES))
21 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4
22 #elif defined(K81F25615_SERIES)
23 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2
24 #else
25 #define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0
26 #endif
27
28 #define TRNG_USER_CONFIG_DEFAULT_LOCK 0
29 #define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200
30 #define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 2500
31 #define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63
32 #define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1
33 #define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34
34
35 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 1384
36 #define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 268)
37 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 405
38 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 178)
39 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 220
40 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 122)
41 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 125
42 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 88)
43 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75
44 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64)
45 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47
46 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46)
47 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47
48 #define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46)
49 #define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912
50 #define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467)
51 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 0x3fffff
52 #define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600
53
54 /*! @brief TRNG work mode */
55 typedef enum _trng_work_mode
56 {
57 kTRNG_WorkModeRun = 0U, /*!< Run Mode. */
58 kTRNG_WorkModeProgram = 1U /*!< Program Mode. */
59 } trng_work_mode_t;
60
61 /*! @brief TRNG statistical check type*/
62 typedef enum _trng_statistical_check
63 {
64 kTRNG_StatisticalCheckMonobit =
65 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */
66 kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy
67 generation. */
68 kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy
69 generation. */
70 kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy
71 generation. */
72 kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy
73 generation. */
74 kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy
75 generation. */
76 kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during
77 entropy generation. */
78 kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */
79 kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */
80 } trng_statistical_check_t;
81
82 /*******************************************************************************
83 * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
84 ******************************************************************************/
85 /*!
86 * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW)
87 *
88 * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation,
89 * the RTY_CT value indicates the number of times a retry should occur before
90 * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This
91 * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing
92 * the MCTL[RST_DEF] bit to 1.
93 */
94 /*@{*/
95 /*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */
96 #define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT)
97
98 /*! @brief Set the RTY_CT field to a new value. */
99 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value)))
100 /*@}*/
101
102 /*******************************************************************************
103 * TRNG_SCML - RNG Statistical Check Monobit Limit Register
104 ******************************************************************************/
105 /*!
106 * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW)
107 *
108 * Reset value: 0x010C0568U
109 *
110 * The RNG Statistical Check Monobit Limit Register defines the allowable
111 * maximum and minimum number of ones/zero detected during entropy generation. To pass
112 * the test, the number of ones/zeroes generated must be less than the programmed
113 * maximum value, and the number of ones/zeroes generated must be greater than
114 * (maximum - range). If this test fails, the Retry Counter in SCMISC will be
115 * decremented, and a retry will occur if the Retry Count has not reached zero. If
116 * the Retry Count has reached zero, an error will be generated. Note that this
117 * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0,
118 * this offset is used as SCMC readback register.
119 */
120 /*!
121 * @name Constants and macros for entire TRNG_SCML register
122 */
123 /*@{*/
124 #define TRNG_SCML_REG(base) ((base)->SCML)
125 #define TRNG_RD_SCML(base) (TRNG_SCML_REG(base))
126 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value))
127 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value)))
128 /*@}*/
129 /*!
130 * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW)
131 *
132 * Monobit Maximum Limit. Defines the maximum allowable count taken during
133 * entropy generation. The number of ones/zeroes detected during entropy generation
134 * must be less than MONO_MAX, else a retry or error will occur. This register is
135 * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1.
136 */
137 /*@{*/
138 /*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */
139 #define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT)
140
141 /*! @brief Set the MONO_MAX field to a new value. */
142 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value)))
143 /*@}*/
144 /*!
145 * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW)
146 *
147 * Monobit Range. The number of ones/zeroes detected during entropy generation
148 * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur.
149 * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF]
150 * bit to 1.
151 */
152 /*@{*/
153 /*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */
154 #define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT)
155
156 /*! @brief Set the MONO_RNG field to a new value. */
157 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value)))
158 /*@}*/
159
160 /*******************************************************************************
161 * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register
162 ******************************************************************************/
163
164 /*!
165 * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW)
166 *
167 * Reset value: 0x00B20195U
168 *
169 * The RNG Statistical Check Run Length 1 Limit Register defines the allowable
170 * maximum and minimum number of runs of length 1 detected during entropy
171 * generation. To pass the test, the number of runs of length 1 (for samples of both 0
172 * and 1) must be less than the programmed maximum value, and the number of runs of
173 * length 1 must be greater than (maximum - range). If this test fails, the
174 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
175 * Count has not reached zero. If the Retry Count has reached zero, an error will
176 * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if
177 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback
178 * register.
179 */
180 /*!
181 * @name Constants and macros for entire TRNG_SCR1L register
182 */
183 /*@{*/
184 #define TRNG_SCR1L_REG(base) ((base)->SCR1L)
185 #define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base))
186 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value))
187 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value)))
188 /*@}*/
189
190 /*!
191 * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW)
192 *
193 * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1
194 * (for both 0 and 1) detected during entropy generation. The number of runs of
195 * length 1 detected during entropy generation must be less than RUN1_MAX, else a
196 * retry or error will occur. This register is cleared to 01E5h (decimal 485) by
197 * writing the MCTL[RST_DEF] bit to 1.
198 */
199 /*@{*/
200 /*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */
201 #define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT)
202
203 /*! @brief Set the RUN1_MAX field to a new value. */
204 #define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value)))
205 /*@}*/
206
207 /*!
208 * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW)
209 *
210 * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1)
211 * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a
212 * retry or error will occur. This register is cleared to 0102h (decimal 258) by
213 * writing the MCTL[RST_DEF] bit to 1.
214 */
215 /*@{*/
216 /*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */
217 #define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT)
218
219 /*! @brief Set the RUN1_RNG field to a new value. */
220 #define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value)))
221 /*@}*/
222
223 /*******************************************************************************
224 * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register
225 ******************************************************************************/
226
227 /*!
228 * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW)
229 *
230 * Reset value: 0x007A00DCU
231 *
232 * The RNG Statistical Check Run Length 2 Limit Register defines the allowable
233 * maximum and minimum number of runs of length 2 detected during entropy
234 * generation. To pass the test, the number of runs of length 2 (for samples of both 0
235 * and 1) must be less than the programmed maximum value, and the number of runs of
236 * length 2 must be greater than (maximum - range). If this test fails, the
237 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
238 * Count has not reached zero. If the Retry Count has reached zero, an error will
239 * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if
240 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback
241 * register.
242 */
243 /*!
244 * @name Constants and macros for entire TRNG_SCR2L register
245 */
246 /*@{*/
247 #define TRNG_SCR2L_REG(base) ((base)->SCR2L)
248 #define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base))
249 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value))
250 #define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value)))
251 /*@}*/
252
253 /*
254 * Constants & macros for individual TRNG_SCR2L bitfields
255 */
256
257 /*!
258 * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW)
259 *
260 * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2
261 * (for both 0 and 1) detected during entropy generation. The number of runs of
262 * length 2 detected during entropy generation must be less than RUN2_MAX, else a
263 * retry or error will occur. This register is cleared to 00DCh (decimal 220) by
264 * writing the MCTL[RST_DEF] bit to 1.
265 */
266 /*@{*/
267 /*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */
268 #define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT)
269
270 /*! @brief Set the RUN2_MAX field to a new value. */
271 #define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value)))
272 /*@}*/
273
274 /*!
275 * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW)
276 *
277 * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1)
278 * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a
279 * retry or error will occur. This register is cleared to 007Ah (decimal 122) by
280 * writing the MCTL[RST_DEF] bit to 1.
281 */
282 /*@{*/
283 /*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */
284 #define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT)
285
286 /*! @brief Set the RUN2_RNG field to a new value. */
287 #define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value)))
288 /*@}*/
289
290 /*******************************************************************************
291 * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register
292 ******************************************************************************/
293
294 /*!
295 * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW)
296 *
297 * Reset value: 0x0058007DU
298 *
299 * The RNG Statistical Check Run Length 3 Limit Register defines the allowable
300 * maximum and minimum number of runs of length 3 detected during entropy
301 * generation. To pass the test, the number of runs of length 3 (for samples of both 0
302 * and 1) must be less than the programmed maximum value, and the number of runs of
303 * length 3 must be greater than (maximum - range). If this test fails, the
304 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
305 * Count has not reached zero. If the Retry Count has reached zero, an error will
306 * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if
307 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback
308 * register.
309 */
310 /*!
311 * @name Constants and macros for entire TRNG_SCR3L register
312 */
313 /*@{*/
314 #define TRNG_SCR3L_REG(base) ((base)->SCR3L)
315 #define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base))
316 #define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value))
317 #define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value)))
318 /*@}*/
319
320 /*
321 * Constants & macros for individual TRNG_SCR3L bitfields
322 */
323
324 /*!
325 * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW)
326 *
327 * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3
328 * (for both 0 and 1) detected during entropy generation. The number of runs of
329 * length 3 detected during entropy generation must be less than RUN3_MAX, else a
330 * retry or error will occur. This register is cleared to 007Dh (decimal 125) by
331 * writing the MCTL[RST_DEF] bit to 1.
332 */
333 /*@{*/
334 /*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */
335 #define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT)
336
337 /*! @brief Set the RUN3_MAX field to a new value. */
338 #define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value)))
339 /*@}*/
340
341 /*!
342 * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW)
343 *
344 * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1)
345 * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a
346 * retry or error will occur. This register is cleared to 0058h (decimal 88) by
347 * writing the MCTL[RST_DEF] bit to 1.
348 */
349 /*@{*/
350 /*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */
351 #define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT)
352
353 /*! @brief Set the RUN3_RNG field to a new value. */
354 #define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value)))
355 /*@}*/
356
357 /*******************************************************************************
358 * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register
359 ******************************************************************************/
360
361 /*!
362 * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW)
363 *
364 * Reset value: 0x0040004BU
365 *
366 * The RNG Statistical Check Run Length 4 Limit Register defines the allowable
367 * maximum and minimum number of runs of length 4 detected during entropy
368 * generation. To pass the test, the number of runs of length 4 (for samples of both 0
369 * and 1) must be less than the programmed maximum value, and the number of runs of
370 * length 4 must be greater than (maximum - range). If this test fails, the
371 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
372 * Count has not reached zero. If the Retry Count has reached zero, an error will
373 * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if
374 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback
375 * register.
376 */
377 /*!
378 * @name Constants and macros for entire TRNG_SCR4L register
379 */
380 /*@{*/
381 #define TRNG_SCR4L_REG(base) ((base)->SCR4L)
382 #define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base))
383 #define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value))
384 #define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value)))
385 /*@}*/
386
387 /*
388 * Constants & macros for individual TRNG_SCR4L bitfields
389 */
390
391 /*!
392 * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW)
393 *
394 * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4
395 * (for both 0 and 1) detected during entropy generation. The number of runs of
396 * length 4 detected during entropy generation must be less than RUN4_MAX, else a
397 * retry or error will occur. This register is cleared to 004Bh (decimal 75) by
398 * writing the MCTL[RST_DEF] bit to 1.
399 */
400 /*@{*/
401 /*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */
402 #define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT)
403
404 /*! @brief Set the RUN4_MAX field to a new value. */
405 #define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value)))
406 /*@}*/
407
408 /*!
409 * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW)
410 *
411 * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1)
412 * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a
413 * retry or error will occur. This register is cleared to 0040h (decimal 64) by
414 * writing the MCTL[RST_DEF] bit to 1.
415 */
416 /*@{*/
417 /*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */
418 #define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT)
419
420 /*! @brief Set the RUN4_RNG field to a new value. */
421 #define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value)))
422 /*@}*/
423
424 /*******************************************************************************
425 * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register
426 ******************************************************************************/
427
428 /*!
429 * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW)
430 *
431 * Reset value: 0x002E002FU
432 *
433 * The RNG Statistical Check Run Length 5 Limit Register defines the allowable
434 * maximum and minimum number of runs of length 5 detected during entropy
435 * generation. To pass the test, the number of runs of length 5 (for samples of both 0
436 * and 1) must be less than the programmed maximum value, and the number of runs of
437 * length 5 must be greater than (maximum - range). If this test fails, the
438 * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
439 * Count has not reached zero. If the Retry Count has reached zero, an error will
440 * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if
441 * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback
442 * register.
443 */
444 /*!
445 * @name Constants and macros for entire TRNG_SCR5L register
446 */
447 /*@{*/
448 #define TRNG_SCR5L_REG(base) ((base)->SCR5L)
449 #define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base))
450 #define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value))
451 #define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value)))
452 /*@}*/
453
454 /*
455 * Constants & macros for individual TRNG_SCR5L bitfields
456 */
457
458 /*!
459 * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW)
460 *
461 * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5
462 * (for both 0 and 1) detected during entropy generation. The number of runs of
463 * length 5 detected during entropy generation must be less than RUN5_MAX, else a
464 * retry or error will occur. This register is cleared to 002Fh (decimal 47) by
465 * writing the MCTL[RST_DEF] bit to 1.
466 */
467 /*@{*/
468 /*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */
469 #define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT)
470
471 /*! @brief Set the RUN5_MAX field to a new value. */
472 #define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value)))
473 /*@}*/
474
475 /*!
476 * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW)
477 *
478 * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1)
479 * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a
480 * retry or error will occur. This register is cleared to 002Eh (decimal 46) by
481 * writing the MCTL[RST_DEF] bit to 1.
482 */
483 /*@{*/
484 /*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */
485 #define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT)
486
487 /*! @brief Set the RUN5_RNG field to a new value. */
488 #define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value)))
489 /*@}*/
490
491 /*******************************************************************************
492 * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register
493 ******************************************************************************/
494
495 /*!
496 * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW)
497 *
498 * Reset value: 0x002E002FU
499 *
500 * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable
501 * maximum and minimum number of runs of length 6 or more detected during entropy
502 * generation. To pass the test, the number of runs of length 6 or more (for
503 * samples of both 0 and 1) must be less than the programmed maximum value, and the
504 * number of runs of length 6 or more must be greater than (maximum - range). If
505 * this test fails, the Retry Counter in SCMISC will be decremented, and a retry
506 * will occur if the Retry Count has not reached zero. If the Retry Count has
507 * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is
508 * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is
509 * used as SCR6PC readback register.
510 */
511 /*!
512 * @name Constants and macros for entire TRNG_SCR6PL register
513 */
514 /*@{*/
515 #define TRNG_SCR6PL_REG(base) ((base)->SCR6PL)
516 #define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base))
517 #define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value))
518 #define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value)))
519 /*@}*/
520
521 /*
522 * Constants & macros for individual TRNG_SCR6PL bitfields
523 */
524
525 /*!
526 * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW)
527 *
528 * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6
529 * or more (for both 0 and 1) detected during entropy generation. The number of
530 * runs of length 6 or more detected during entropy generation must be less than
531 * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh
532 * (decimal 47) by writing the MCTL[RST_DEF] bit to 1.
533 */
534 /*@{*/
535 /*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */
536 #define TRNG_RD_SCR6PL_RUN6P_MAX(base) \
537 ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT)
538
539 /*! @brief Set the RUN6P_MAX field to a new value. */
540 #define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \
541 (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value)))
542 /*@}*/
543
544 /*!
545 * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW)
546 *
547 * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and
548 * 1) detected during entropy generation must be greater than RUN6P_MAX -
549 * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh
550 * (decimal 46) by writing the MCTL[RST_DEF] bit to 1.
551 */
552 /*@{*/
553 /*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */
554 #define TRNG_RD_SCR6PL_RUN6P_RNG(base) \
555 ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT)
556
557 /*! @brief Set the RUN6P_RNG field to a new value. */
558 #define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \
559 (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value)))
560 /*@}*/
561
562 /*******************************************************************************
563 * TRNG_PKRMAX - RNG Poker Maximum Limit Register
564 ******************************************************************************/
565
566 /*!
567 * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW)
568 *
569 * Reset value: 0x00006920U
570 *
571 * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during
572 * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is
573 * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used
574 * as the PKRSQ readback register.
575 */
576 /*!
577 * @name Constants and macros for entire TRNG_PKRMAX register
578 */
579 /*@{*/
580 #define TRNG_PKRMAX_REG(base) ((base)->PKRMAX)
581 #define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base))
582 #define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value))
583 #define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value)))
584 /*@}*/
585
586 /*
587 * Constants & macros for individual TRNG_PKRMAX bitfields
588 */
589
590 /*!
591 * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW)
592 *
593 * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is
594 * run which requires a maximum and minimum limit. The maximum allowable result is
595 * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if
596 * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by
597 * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers
598 * combined are used to define the minimum allowable Poker result, which is PKR_MAX -
599 * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used
600 * to read the Poker Test Square Calculation result in register PKRSQ, as defined
601 * in the following section.
602 */
603 /*@{*/
604 /*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */
605 #define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT)
606
607 /*! @brief Set the PKR_MAX field to a new value. */
608 #define TRNG_WR_PKRMAX_PKR_MAX(base, value) \
609 (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value)))
610 /*@}*/
611
612 /*******************************************************************************
613 * TRNG_PKRRNG - RNG Poker Range Register
614 ******************************************************************************/
615
616 /*!
617 * @brief TRNG_PKRRNG - RNG Poker Range Register (RW)
618 *
619 * Reset value: 0x000009A3U
620 *
621 * The RNG Poker Range Register defines the difference between the TRNG Poker
622 * Maximum Limit and the minimum limit. These limits are used during the TRNG
623 * Statistical Check Poker Test.
624 */
625 /*!
626 * @name Constants and macros for entire TRNG_PKRRNG register
627 */
628 /*@{*/
629 #define TRNG_PKRRNG_REG(base) ((base)->PKRRNG)
630 #define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base))
631 #define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value))
632 #define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value)))
633 /*@}*/
634
635 /*
636 * Constants & macros for individual TRNG_PKRRNG bitfields
637 */
638
639 /*!
640 * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW)
641 *
642 * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which
643 * requires a maximum and minimum limit. The maximum is programmed in the
644 * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG
645 * value from the programmed maximum value. This field is writable only if
646 * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is
647 * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that
648 * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1.
649 */
650 /*@{*/
651 /*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */
652 #define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT)
653
654 /*! @brief Set the PKR_RNG field to a new value. */
655 #define TRNG_WR_PKRRNG_PKR_RNG(base, value) \
656 (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value)))
657 /*@}*/
658
659 /*******************************************************************************
660 * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register
661 ******************************************************************************/
662
663 /*!
664 * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW)
665 *
666 * Reset value: 0x00006400U
667 *
668 * The RNG Frequency Count Maximum Limit Register defines the maximum allowable
669 * count taken by the Entropy sample counter during each Entropy sample. During
670 * any sample period, if the count is greater than this programmed maximum, a
671 * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note
672 * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If
673 * MCTL[PRGM] is 0, this address is used as FRQCNT readback register.
674 */
675 /*!
676 * @name Constants and macros for entire TRNG_FRQMAX register
677 */
678 /*@{*/
679 #define TRNG_FRQMAX_REG(base) ((base)->FRQMAX)
680 #define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base))
681 #define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value))
682 #define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value)))
683 /*@}*/
684
685 /*
686 * Constants & macros for individual TRNG_FRQMAX bitfields
687 */
688
689 /*!
690 * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW)
691 *
692 * Frequency Counter Maximum Limit. Defines the maximum allowable count taken
693 * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
694 * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1.
695 * Note that if MCTL[PRGM] bit is 0, this register address is used to read the
696 * Frequency Count result in register FRQCNT, as defined in the following section.
697 */
698 /*@{*/
699 /*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */
700 #define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT)
701
702 /*! @brief Set the FRQ_MAX field to a new value. */
703 #define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \
704 (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value)))
705 /*@}*/
706
707 /*******************************************************************************
708 * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register
709 ******************************************************************************/
710
711 /*!
712 * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW)
713 *
714 * Reset value: 0x00000640U
715 *
716 * The RNG Frequency Count Minimum Limit Register defines the minimum allowable
717 * count taken by the Entropy sample counter during each Entropy sample. During
718 * any sample period, if the count is less than this programmed minimum, a
719 * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated.
720 */
721 /*!
722 * @name Constants and macros for entire TRNG_FRQMIN register
723 */
724 /*@{*/
725 #define TRNG_FRQMIN_REG(base) ((base)->FRQMIN)
726 #define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base))
727 #define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value))
728 #define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value)))
729 /*@}*/
730
731 /*
732 * Constants & macros for individual TRNG_FRQMIN bitfields
733 */
734
735 /*!
736 * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW)
737 *
738 * Frequency Count Minimum Limit. Defines the minimum allowable count taken
739 * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
740 * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64
741 * by writing the MCTL[RST_DEF] bit to 1.
742 */
743 /*@{*/
744 /*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */
745 #define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT)
746
747 /*! @brief Set the FRQ_MIN field to a new value. */
748 #define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \
749 (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value)))
750 /*@}*/
751
752 /*******************************************************************************
753 * TRNG_MCTL - RNG Miscellaneous Control Register
754 ******************************************************************************/
755
756 /*!
757 * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW)
758 *
759 * Reset value: 0x00012001U
760 *
761 * This register is intended to be used for programming, configuring and testing
762 * the RNG. It is the main register to read/write, in order to enable Entropy
763 * generation, to stop entropy generation and to block access to entropy registers.
764 * This is done via the special TRNG_ACC and PRGM bits below. The RNG
765 * Miscellaneous Control Register is a read/write register used to control the RNG's True
766 * Random Number Generator (TRNG) access, operation and test. Note that in many
767 * cases two RNG registers share the same address, and a particular register at the
768 * shared address is selected based upon the value in the PRGM field of the MCTL
769 * register.
770 */
771 /*!
772 * @name Constants and macros for entire TRNG_MCTL register
773 */
774 /*@{*/
775 #define TRNG_MCTL_REG(base) ((base)->MCTL)
776 #define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base))
777 #define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value))
778 #define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value)))
779 /*@}*/
780
781 /*!
782 * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW)
783 *
784 * Force System Clock. If set, the system clock is used to operate the TRNG,
785 * instead of the ring oscillator. This is for test use only, and indeterminate
786 * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is
787 * being written to 1 simultaneously to writing this bit. This bit is cleared by
788 * writing the RST_DEF bit to 1.
789 */
790 /*@{*/
791 /*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */
792 #define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT)
793
794 /*! @brief Set the FOR_SCLK field to a new value. */
795 #define TRNG_WR_MCTL_FOR_SCLK(base, value) \
796 (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value)))
797 /*@}*/
798
799 /*!
800 * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW)
801 *
802 * Oscillator Divide. Determines the amount of dividing done to the ring
803 * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is
804 * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This
805 * field is cleared to 00 by writing the RST_DEF bit to 1.
806 *
807 * Values:
808 * - 0b00 - use ring oscillator with no divide
809 * - 0b01 - use ring oscillator divided-by-2
810 * - 0b10 - use ring oscillator divided-by-4
811 * - 0b11 - use ring oscillator divided-by-8
812 */
813 /*@{*/
814 /*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */
815 #define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT)
816
817 /*! @brief Set the OSC_DIV field to a new value. */
818 #define TRNG_WR_MCTL_OSC_DIV(base, value) \
819 (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value)))
820 /*@}*/
821
822 /*!
823 * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW)
824 *
825 * Sample Mode. Determines the method of sampling the ring oscillator while
826 * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM
827 * bit is being written to 1 simultaneously with writing this field. This field
828 * is cleared to 01 by writing the RST_DEF bit to 1.
829 *
830 * Values:
831 * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical
832 * Checker
833 * - 0b01 - use raw data into both Entropy shifter and Statistical Checker
834 * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into
835 * Statistical Checker
836 * - 0b11 - reserved.
837 */
838 /*@{*/
839 /*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */
840 #define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT)
841
842 /*! @brief Set the SAMP_MODE field to a new value. */
843 #define TRNG_WR_MCTL_SAMP_MODE(base, value) \
844 (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value)))
845 /*@}*/
846
847 /*!
848 * @name Register TRNG_MCTL, field PRGM[16] (RW)
849 *
850 * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode,
851 * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is
852 * in Program Mode. Note that different RNG registers are accessible at the same
853 * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG
854 * register descriptions.
855 */
856 /*@{*/
857 /*! @brief Read current value of the TRNG_MCTL_PRGM field. */
858 #define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT)
859
860 /*! @brief Set the PRGM field to a new value. */
861 #define TRNG_WR_MCTL_PRGM(base, value) \
862 (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value)))
863 /*@}*/
864
865 /*!
866 * @name Register TRNG_MCTL, field RST_DEF[6] (WO)
867 *
868 * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and
869 * bits within registers, to their default state. This bit is writable only if PRGM
870 * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this
871 * bit. Reading this bit always produces a 0.
872 */
873 /*@{*/
874 /*! @brief Set the RST_DEF field to a new value. */
875 #define TRNG_WR_MCTL_RST_DEF(base, value) \
876 (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value)))
877 /*@}*/
878
879 /*!
880 * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW)
881 *
882 * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy
883 * value that can be read via the ENT0-ENT15 registers. The Entropy value may be
884 * read once the ENT VAL bit is asserted. Also see ENTa register descriptions
885 * (For a = 0 to 15).
886 */
887 /*@{*/
888 /*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */
889 #define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT)
890
891 /*! @brief Set the TRNG_ACC field to a new value. */
892 #define TRNG_WR_MCTL_TRNG_ACC(base, value) \
893 (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value)))
894 /*@}*/
895
896 /*!
897 * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO)
898 *
899 * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before
900 * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG
901 * free-running ring oscillator whenever new entropy is being generated and turns off the
902 * ring oscillator when entropy generation is complete. If the RNG clock is
903 * stopped while the TRNG ring oscillator is running, the oscillator will continue
904 * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG
905 * ring oscillator is not running. and therefore it is ok to stop the RNG clock.
906 */
907 /*@{*/
908 /*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */
909 #define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT)
910 /*@}*/
911
912 /*!
913 * @name Register TRNG_MCTL, field ENT_VAL[10] (RO)
914 *
915 * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then
916 * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0
917 * through ENT14 should be read before reading ENT15).
918 */
919 /*@{*/
920 /*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */
921 #define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT)
922 /*@}*/
923
924 /*!
925 * @name Register TRNG_MCTL, field ERR[12] (W1C)
926 *
927 * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear
928 * errors. Writing 0 has no effect.
929 */
930 /*@{*/
931 /*! @brief Read current value of the TRNG_MCTL_ERR field. */
932 #define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT)
933
934 /*! @brief Set the ERR field to a new value. */
935 #define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value)))
936 /*@}*/
937
938 /*******************************************************************************
939 * TRNG_SDCTL - RNG Seed Control Register
940 ******************************************************************************/
941
942 /*!
943 * @brief TRNG_SDCTL - RNG Seed Control Register (RW)
944 *
945 * Reset value: 0x0C8009C4U
946 *
947 * The RNG Seed Control Register contains two fields. One field defines the
948 * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field
949 * indicates the number of samples that will taken during each TRNG Entropy
950 * generation (SAMP_SIZE).
951 */
952 /*!
953 * @name Constants and macros for entire TRNG_SDCTL register
954 */
955 /*@{*/
956 #define TRNG_SDCTL_REG(base) ((base)->SDCTL)
957 #define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base))
958 #define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value))
959 #define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value)))
960 /*@}*/
961
962 /*
963 * Constants & macros for individual TRNG_SDCTL bitfields
964 */
965
966 /*!
967 * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW)
968 *
969 * Sample Size. Defines the total number of Entropy samples that will be taken
970 * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1.
971 * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h
972 * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1.
973 */
974 /*@{*/
975 /*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */
976 #define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT)
977
978 /*! @brief Set the SAMP_SIZE field to a new value. */
979 #define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \
980 (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value)))
981 /*@}*/
982
983 /*!
984 * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW)
985 *
986 * Entropy Delay. Defines the length (in system clocks) of each Entropy sample
987 * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read
988 * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by
989 * writing the MCTL[RST_DEF] bit to 1.
990 */
991 /*@{*/
992 /*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */
993 #define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT)
994
995 /*! @brief Set the ENT_DLY field to a new value. */
996 #define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value)))
997 /*@}*/
998
999 /*******************************************************************************
1000 * TRNG_SBLIM - RNG Sparse Bit Limit Register
1001 ******************************************************************************/
1002
1003 /*!
1004 * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW)
1005 *
1006 * Reset value: 0x0000003FU
1007 *
1008 * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is
1009 * selected during Entropy Generation. It defines the maximum number of consecutive Von
1010 * Neumann samples which may be discarded before an error is generated. Note
1011 * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If
1012 * MCTL[PRGM] is 0, this address is used as TOTSAM readback register.
1013 */
1014 /*!
1015 * @name Constants and macros for entire TRNG_SBLIM register
1016 */
1017 /*@{*/
1018 #define TRNG_SBLIM_REG(base) ((base)->SBLIM)
1019 #define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base))
1020 #define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value))
1021 #define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value)))
1022 /*@}*/
1023
1024 /*
1025 * Constants & macros for individual TRNG_SBLIM bitfields
1026 */
1027
1028 /*!
1029 * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW)
1030 *
1031 * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE],
1032 * samples are discarded if two consecutive raw samples are both 0 or both 1. If
1033 * this discarding occurs for a long period of time, it indicates that there is
1034 * insufficient Entropy. The Sparse Bit Limit defines the maximum number of
1035 * consecutive samples that may be discarded before an error is generated. This field
1036 * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by
1037 * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this
1038 * register address is used to read the Total Samples count in register TOTSAM, as
1039 * defined in the following section.
1040 */
1041 /*@{*/
1042 /*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */
1043 #define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT)
1044
1045 /*! @brief Set the SB_LIM field to a new value. */
1046 #define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value)))
1047 /*@}*/
1048
1049 /*******************************************************************************
1050 * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
1051 ******************************************************************************/
1052
1053 /*!
1054 * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW)
1055 *
1056 * Reset value: 0x0001001FU
1057 *
1058 * The RNG Statistical Check Miscellaneous Register contains the Long Run
1059 * Maximum Limit value and the Retry Count value. This register is accessible only when
1060 * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot
1061 * be written.
1062 */
1063 /*!
1064 * @name Constants and macros for entire TRNG_SCMISC register
1065 */
1066 /*@{*/
1067 #define TRNG_SCMISC_REG(base) ((base)->SCMISC)
1068 #define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base))
1069 #define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value))
1070 #define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value)))
1071 /*@}*/
1072
1073 /*
1074 * Constants & macros for individual TRNG_SCMISC bitfields
1075 */
1076
1077 /*!
1078 * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW)
1079 *
1080 * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive
1081 * samples of all 1, or all 0, that is allowed during the Entropy generation.
1082 * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes
1083 * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF]
1084 * bit to 1.
1085 */
1086 /*@{*/
1087 /*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */
1088 #define TRNG_RD_SCMISC_LRUN_MAX(base) \
1089 ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT)
1090
1091 /*! @brief Set the LRUN_MAX field to a new value. */
1092 #define TRNG_WR_SCMISC_LRUN_MAX(base, value) \
1093 (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value)))
1094 /*@}*/
1095
1096 /*******************************************************************************
1097 * TRNG_ENT - RNG TRNG Entropy Read Register
1098 ******************************************************************************/
1099
1100 /*!
1101 * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO)
1102 *
1103 * Reset value: 0x00000000U
1104 *
1105 * The RNG TRNG can be programmed to generate an entropy value that is readable
1106 * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the
1107 * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this
1108 * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value.
1109 * Note that once ENT15 is read, the entropy value will be cleared and a new
1110 * value will begin generation, so it is important that ENT15 be read last. These
1111 * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1
1112 * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read.
1113 */
1114 /*!
1115 * @name Constants and macros for entire TRNG_ENT register
1116 */
1117 /*@{*/
1118 #define TRNG_ENT_REG(base, index) ((base)->ENT[index])
1119 #define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index))
1120 /*@}*/
1121
1122 /*******************************************************************************
1123 * TRNG_SEC_CFG - RNG Security Configuration Register
1124 ******************************************************************************/
1125
1126 /*!
1127 * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW)
1128 *
1129 * Reset value: 0x00000000U
1130 *
1131 * The RNG Security Configuration Register is a read/write register used to
1132 * control the test mode, programmability and state modes of the RNG. Many bits are
1133 * place holders for this version. More configurability will be added here. Clears
1134 * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0
1135 * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use
1136 * these registers, if hard coded.
1137 */
1138 /*!
1139 * @name Constants and macros for entire TRNG_SEC_CFG register
1140 */
1141 /*@{*/
1142 #define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG)
1143 #define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base))
1144 #define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value))
1145 #define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value)))
1146 /*@}*/
1147
1148 /*!
1149 * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW)
1150 *
1151 * If set the TRNG registers cannot be programmed. That is, regardless of the
1152 * TRNG access mode in the SA-TRNG Miscellaneous Control Register.
1153 *
1154 * Values:
1155 * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
1156 * Control Register's access mode bit.
1157 * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
1158 * TRNG register programming.
1159 */
1160 /*@{*/
1161 /*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */
1162 #define TRNG_RD_SEC_CFG_NO_PRGM(base) \
1163 ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT)
1164
1165 /*! @brief Set the NO_PRGM field to a new value. */
1166 #define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \
1167 (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value)))
1168 /*@}*/
1169
1170 /*! @brief Array to map TRNG instance number to base pointer. */
1171 static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS;
1172
1173 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1174 /*! @brief Clock array name */
1175 static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS;
1176 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1177
1178 /*******************************************************************************
1179 * Prototypes
1180 *******************************************************************************/
1181 static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig);
1182 static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count);
1183 static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
1184 trng_statistical_check_t statistical_check,
1185 const trng_statistical_check_limit_t *limit);
1186 static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index);
1187 static uint32_t trng_GetInstance(TRNG_Type *base);
1188
1189 /*******************************************************************************
1190 * Code
1191 ******************************************************************************/
1192
trng_GetInstance(TRNG_Type * base)1193 static uint32_t trng_GetInstance(TRNG_Type *base)
1194 {
1195 uint32_t instance;
1196
1197 /* Find the instance index from base address mappings. */
1198 for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++)
1199 {
1200 if (s_trngBases[instance] == base)
1201 {
1202 break;
1203 }
1204 }
1205
1206 assert(instance < ARRAY_SIZE(s_trngBases));
1207
1208 return instance;
1209 }
1210
1211 /*FUNCTION*********************************************************************
1212 *
1213 * Function Name : TRNG_InitUserConfigDefault
1214 * Description : Initializes user configuration structure to default settings.
1215 *
1216 *END*************************************************************************/
TRNG_GetDefaultConfig(trng_config_t * userConfig)1217 status_t TRNG_GetDefaultConfig(trng_config_t *userConfig)
1218 {
1219 status_t result;
1220
1221 if (userConfig != 0)
1222 {
1223 userConfig->lock = TRNG_USER_CONFIG_DEFAULT_LOCK;
1224 userConfig->clockMode = kTRNG_ClockModeRingOscillator;
1225 userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV;
1226 userConfig->sampleMode = kTRNG_SampleModeRaw;
1227 userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY;
1228 userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE;
1229 userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT;
1230
1231 /* Statistical Check Parameters.*/
1232 userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT;
1233 userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT;
1234
1235 userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM;
1236 userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM;
1237 userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM;
1238 userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM;
1239 userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM;
1240 userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM;
1241 userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM;
1242 userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM;
1243 userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM;
1244 userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM;
1245 userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM;
1246 userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM;
1247 userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM;
1248 userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM;
1249 userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM;
1250 userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM;
1251 userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM;
1252 userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM;
1253
1254 result = kStatus_Success;
1255 }
1256 else
1257 {
1258 result = kStatus_InvalidArgument;
1259 }
1260
1261 return result;
1262 }
1263
1264 /*!
1265 * @brief Sets the TRNG retry count.
1266 *
1267 * This function sets the retry counter which defines the number of times a
1268 * statistical check may fails during the TRNG Entropy Generation before
1269 * generating an error.
1270 */
trng_SetRetryCount(TRNG_Type * base,uint8_t retry_count)1271 static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count)
1272 {
1273 status_t status;
1274
1275 if ((retry_count >= 1u) && (retry_count <= 15u))
1276 {
1277 /* Set retry count.*/
1278 TRNG_WR_SCMISC_RTY_CT(base, retry_count);
1279 status = kStatus_Success;
1280 }
1281 else
1282 {
1283 status = kStatus_InvalidArgument;
1284 }
1285 return status;
1286 }
1287
1288 /*!
1289 * @brief Sets statistical check limits.
1290 *
1291 * This function is used to set minimum and maximum limits of statistical checks.
1292 *
1293 */
trng_SetStatisticalCheckLimit(TRNG_Type * base,trng_statistical_check_t statistical_check,const trng_statistical_check_limit_t * limit)1294 static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base,
1295 trng_statistical_check_t statistical_check,
1296 const trng_statistical_check_limit_t *limit)
1297 {
1298 uint32_t range;
1299 status_t status = kStatus_Success;
1300
1301 if (limit && (limit->maximum > limit->minimum))
1302 {
1303 range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/
1304
1305 switch (statistical_check)
1306 {
1307 case kTRNG_StatisticalCheckMonobit: /* Allowable maximum and minimum number of ones/zero detected during
1308 entropy generation. */
1309 if ((range <= 0xffffu) && (limit->maximum <= 0xffffu))
1310 {
1311 TRNG_WR_SCML_MONO_MAX(base, limit->maximum);
1312 TRNG_WR_SCML_MONO_RNG(base, range);
1313 }
1314 else
1315 {
1316 status = kStatus_InvalidArgument;
1317 }
1318 break;
1319 case kTRNG_StatisticalCheckRunBit1: /* Allowable maximum and minimum number of runs of length 1 detected
1320 during entropy generation. */
1321 if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu))
1322 {
1323 TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum);
1324 TRNG_WR_SCR1L_RUN1_RNG(base, range);
1325 }
1326 else
1327 {
1328 status = kStatus_InvalidArgument;
1329 }
1330 break;
1331 case kTRNG_StatisticalCheckRunBit2: /* Allowable maximum and minimum number of runs of length 2 detected
1332 during entropy generation. */
1333 if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu))
1334 {
1335 TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum);
1336 TRNG_WR_SCR2L_RUN2_RNG(base, range);
1337 }
1338 else
1339 {
1340 status = kStatus_InvalidArgument;
1341 }
1342 break;
1343 case kTRNG_StatisticalCheckRunBit3: /* Allowable maximum and minimum number of runs of length 3 detected
1344 during entropy generation. */
1345 if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu))
1346 {
1347 TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum);
1348 TRNG_WR_SCR3L_RUN3_RNG(base, range);
1349 }
1350 else
1351 {
1352 status = kStatus_InvalidArgument;
1353 }
1354 break;
1355 case kTRNG_StatisticalCheckRunBit4: /* Allowable maximum and minimum number of runs of length 4 detected
1356 during entropy generation. */
1357 if ((range <= 0xfffu) && (limit->maximum <= 0xfffu))
1358 {
1359 TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum);
1360 TRNG_WR_SCR4L_RUN4_RNG(base, range);
1361 }
1362 else
1363 {
1364 status = kStatus_InvalidArgument;
1365 }
1366 break;
1367 case kTRNG_StatisticalCheckRunBit5: /* Allowable maximum and minimum number of runs of length 5 detected
1368 during entropy generation. */
1369 if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
1370 {
1371 TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum);
1372 TRNG_WR_SCR5L_RUN5_RNG(base, range);
1373 }
1374 else
1375 {
1376 status = kStatus_InvalidArgument;
1377 }
1378 break;
1379 case kTRNG_StatisticalCheckRunBit6Plus: /* Allowable maximum and minimum number of length 6 or more detected
1380 during entropy generation */
1381 if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu))
1382 {
1383 TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum);
1384 TRNG_WR_SCR6PL_RUN6P_RNG(base, range);
1385 }
1386 else
1387 {
1388 status = kStatus_InvalidArgument;
1389 }
1390 break;
1391 case kTRNG_StatisticalCheckPoker: /* Allowable maximum and minimum limit of "Poker Test" detected during
1392 entropy generation . */
1393 if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu))
1394 {
1395 TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum);
1396 TRNG_WR_PKRRNG_PKR_RNG(base, range);
1397 }
1398 else
1399 {
1400 status = kStatus_InvalidArgument;
1401 }
1402 break;
1403 case kTRNG_StatisticalCheckFrequencyCount: /* Allowable maximum and minimum limit of entropy sample frquency
1404 count during entropy generation . */
1405 if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu))
1406 {
1407 TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum);
1408 TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum);
1409 }
1410 else
1411 {
1412 status = kStatus_InvalidArgument;
1413 }
1414 break;
1415 default:
1416 status = kStatus_InvalidArgument;
1417 break;
1418 }
1419 }
1420
1421 return status;
1422 }
1423
1424 /*FUNCTION*********************************************************************
1425 *
1426 * Function Name : trng_ApplyUserConfig
1427 * Description : Apply user configuration settings to TRNG module.
1428 *
1429 *END*************************************************************************/
trng_ApplyUserConfig(TRNG_Type * base,const trng_config_t * userConfig)1430 static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig)
1431 {
1432 status_t status;
1433
1434 if (((status = trng_SetRetryCount(base, userConfig->retryCount)) == kStatus_Success) &&
1435 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit)) ==
1436 kStatus_Success) &&
1437 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit)) ==
1438 kStatus_Success) &&
1439 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit)) ==
1440 kStatus_Success) &&
1441 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit)) ==
1442 kStatus_Success) &&
1443 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit)) ==
1444 kStatus_Success) &&
1445 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit)) ==
1446 kStatus_Success) &&
1447 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus,
1448 &userConfig->runBit6PlusLimit)) == kStatus_Success) &&
1449 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit)) ==
1450 kStatus_Success) &&
1451 ((status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount,
1452 &userConfig->frequencyCountLimit)) == kStatus_Success))
1453 {
1454 TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode);
1455 TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv);
1456 TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode);
1457 TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay);
1458 TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize);
1459 TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit);
1460 TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit);
1461 }
1462
1463 return status;
1464 }
1465
1466 /*!
1467 * @brief Gets a entry data from the TRNG.
1468 *
1469 * This function gets an entropy data from TRNG.
1470 * Entropy data is spread over TRNG_ENT_COUNT registers.
1471 * Read register number is defined by index parameter.
1472 */
trng_ReadEntropy(TRNG_Type * base,uint32_t index)1473 static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index)
1474 {
1475 uint32_t data;
1476
1477 index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/
1478
1479 data = TRNG_RD_ENT(base, index);
1480
1481 if (index == (TRNG_ENT_COUNT - 1))
1482 {
1483 /* Dummy read. Defect workaround.
1484 * TRNG could not clear ENT_VAL flag automatically, application
1485 * had to do a dummy reading operation for anyone TRNG register
1486 * to clear it firstly, then to read the RTENT0 to RTENT15 again */
1487 index = TRNG_RD_ENT(base, 0);
1488 }
1489
1490 return data;
1491 }
1492
TRNG_Init(TRNG_Type * base,const trng_config_t * userConfig)1493 status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig)
1494 {
1495 status_t result;
1496
1497 /* Check input parameters.*/
1498 if ((base != 0) && (userConfig != 0))
1499 {
1500 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1501 /* Enable the clock gate. */
1502 CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]);
1503 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1504
1505 /* Reset the registers of TRNG module to reset state. */
1506 /* Must be in program mode.*/
1507 TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
1508 /* Reset Defaults.*/
1509 TRNG_WR_MCTL_RST_DEF(base, 1);
1510
1511 /* Set configuration.*/
1512 if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success)
1513 {
1514 /* Start entropy generation.*/
1515 /* Set to Run mode.*/
1516 TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun);
1517 /* Enable TRNG Access Mode. To generate an Entropy
1518 * value that can be read via the true0-true15 registers.*/
1519 TRNG_WR_MCTL_TRNG_ACC(base, 1);
1520
1521 if (userConfig->lock == 1) /* Disable programmability of TRNG registers. */
1522 {
1523 TRNG_WR_SEC_CFG_NO_PRGM(base, 1);
1524 }
1525
1526 result = kStatus_Success;
1527 }
1528 }
1529 else
1530 {
1531 result = kStatus_InvalidArgument;
1532 }
1533
1534 return result;
1535 }
1536
TRNG_Deinit(TRNG_Type * base)1537 void TRNG_Deinit(TRNG_Type *base)
1538 {
1539 /* Check input parameters.*/
1540 if (base)
1541 {
1542 /* Move to program mode. Stop entropy generation.*/
1543 TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram);
1544
1545 /* Check before clock stop.
1546 TRNG turns on the TRNG free-running ring oscillator whenever new entropy
1547 is being generated and turns off the ring oscillator when entropy generation
1548 is complete. If the TRNG clock is stopped while the TRNG ring oscillator
1549 is running, the oscillator continues running though the RNG clock.
1550 is stopped. */
1551 while (TRNG_RD_MCTL_TSTOP_OK(base) == 0)
1552 {
1553 }
1554
1555 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1556 /* Disable Clock*/
1557 CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]);
1558 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1559 }
1560 }
1561
TRNG_GetRandomData(TRNG_Type * base,void * data,size_t dataSize)1562 status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize)
1563 {
1564 status_t result = kStatus_Success;
1565 uint32_t random_32;
1566 uint8_t *random_p;
1567 uint32_t random_size;
1568 uint8_t *data_p = (uint8_t *)data;
1569 uint32_t i;
1570 int index = 0;
1571
1572 /* Check input parameters.*/
1573 if (base && data && dataSize)
1574 {
1575 do
1576 {
1577 /* Wait for Valid or Error flag*/
1578 while ((TRNG_RD_MCTL_ENT_VAL(base) == 0) && (TRNG_RD_MCTL_ERR(base) == 0))
1579 {
1580 }
1581
1582 /* Check HW error.*/
1583 if (TRNG_RD_MCTL_ERR(base))
1584 {
1585 result = kStatus_Fail; /* TRNG module error occurred */
1586 /* Clear error.*/
1587 TRNG_WR_MCTL_ERR(base, 1);
1588 break; /* No sense stay here.*/
1589 }
1590
1591 /* Read Entropy.*/
1592 random_32 = trng_ReadEntropy(base, index++);
1593
1594 random_p = (uint8_t *)&random_32;
1595
1596 if (dataSize < sizeof(random_32))
1597 {
1598 random_size = dataSize;
1599 }
1600 else
1601 {
1602 random_size = sizeof(random_32);
1603 }
1604
1605 for (i = 0U; i < random_size; i++)
1606 {
1607 *data_p++ = *random_p++;
1608 }
1609
1610 dataSize -= random_size;
1611 } while (dataSize > 0);
1612
1613 /* Start a new entropy generation.
1614 It is done by reading of the last entropy register.*/
1615 if ((index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1))
1616 {
1617 trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1));
1618 }
1619 }
1620 else
1621 {
1622 result = kStatus_InvalidArgument;
1623 }
1624
1625 return result;
1626 }
1627
1628 #endif /* FSL_FEATURE_SOC_TRNG_COUNT */
1629
