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/hal_openisa-latest/vega_sdk_riscv/RISCV/
Dcore_riscv32.h111 #define __O volatile /*!< Defines 'write only' permissions */ macro
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy.h631 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
1310 __O uint32_t CC_CMD; /**< Start Command Register, offset: 0x204 */
1315 __O uint32_t COM; /**< Command Register, offset: 0x430 */
1318 __O uint32_t CW; /**< Clear Written Register, offset: 0x440 */
1351 …__O uint32_t PKE[128]; /**< PKHA E Register, array offset: 0xE00, array …
2618 …__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offse…
2619 …__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset:…
2620 …__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A …
2621 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
2622 …__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C…
[all …]
DRV32M1_ri5cy.h660 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
1527 __O uint32_t CC_CMD; /**< Start Command Register, offset: 0x204 */
1532 __O uint32_t COM; /**< Command Register, offset: 0x430 */
1535 __O uint32_t CW; /**< Clear Written Register, offset: 0x440 */
1568 …__O uint32_t PKE[128]; /**< PKHA E Register, array offset: 0xE00, array …
2835 …__O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offse…
2836 …__O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset:…
2837 …__O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A …
2838 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
2839 …__O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C…
[all …]