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Searched refs:ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h32516 #define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK (0x80000000U) macro
32518 …t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK)
DRV32M1_zero_riscy.h32350 #define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK (0x80000000U) macro
32352 …t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK)