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Searched refs:ZLL_IRQSTS_SRCADDR_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h31793 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) macro
31795 … (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
DRV32M1_zero_riscy.h31627 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U) macro
31629 … (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)