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Searched refs:XRDC_HWCFG2_PIDP5_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h23399 #define XRDC_HWCFG2_PIDP5_MASK (0x20U) macro
23405 … (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK)
DRV32M1_zero_riscy.h30931 #define XRDC_HWCFG2_PIDP5_MASK (0x20U) macro
30937 … (((uint32_t)(((uint32_t)(x)) << XRDC_HWCFG2_PIDP5_SHIFT)) & XRDC_HWCFG2_PIDP5_MASK)