Home
last modified time | relevance | path

Searched refs:XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h31270 #define XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATU… macro
DRV32M1_zero_riscy.h30401 #define XCVR_WOR_WOR_STATUS_TIMESTAMP1_STS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_WOR_WOR_STATU… macro