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Searched refs:XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h31028 #define XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK (0x80000U) macro
31030 …(uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_ZERO_FDEV_SHIFT)) & XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK)
DRV32M1_zero_riscy.h30159 #define XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK (0x80000U) macro
30161 …(uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_ZERO_FDEV_SHIFT)) & XCVR_TX_DIG_CTRL_ZERO_FDEV_MASK)