Home
last modified time | relevance | path

Searched refs:XCVR_TSM_CTRL_FORCE_TX_EN_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c1841 XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; in XCVR_ForceTxWu()
1846 XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; in XCVR_ForceTxWd()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h29267 #define XCVR_TSM_CTRL_FORCE_TX_EN_MASK (0x4U) macro
29273 …(((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK)
DRV32M1_zero_riscy.h28398 #define XCVR_TSM_CTRL_FORCE_TX_EN_MASK (0x4U) macro
28404 …(((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK)