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Searched refs:XCVR_TSM_BASE (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h30919 #define XCVR_TSM_BASE (0x410302C0u) macro
30921 #define XCVR_TSM ((XCVR_TSM_Type *)XCVR_TSM_BASE)
30923 #define XCVR_TSM_BASE_ADDRS { XCVR_TSM_BASE }
DRV32M1_zero_riscy.h30050 #define XCVR_TSM_BASE (0x410302C0u) macro
30052 #define XCVR_TSM ((XCVR_TSM_Type *)XCVR_TSM_BASE)
30054 #define XCVR_TSM_BASE_ADDRS { XCVR_TSM_BASE }